Assignment 2

Power Electronics and Drives

1. A snubber is a circuit that is used in semiconductor devices for protection and performance
enhancements. They have many different purposes, such as the reduction of power dissipation in power
electronic switching networks. Snubber circuit is actually a combination of resistor and capacitor
connected in series with a switch. It is an energy absorbing circuit mostly used in SCR circuits in order
to avoid any kind of spikes or sudden changes in the AC current that may badly affect the circuit.
Before SCR is fired by gate pulse, C s charges to full voltage Vs. When the SCR is turned on, capacitor
discharges through the SCR and sends a current equal to V s/ (resistance of local path formed by Cs and
SCR). As this resistance is quite low, the turn-on di/dt will tend to be excessive and as a result, SCR
may be destroyed. In order to limit the magnitude of discharge current, a resistance R s is inserted in
series with Cs.

2.
3.
4.
5. When we apply gate pulse, SCR changes its state from Forward Blocking Mode to Forward
Conduction Mode. But the point which should be thought of that, does SCR immediately jumps to
Forward Conduction Mode when we apply gate pulse or there is some transition time? In fact, there is a
transition time from forward off state to forward on state. This transition time is called SCR or thyristor
turn on time.
Switching Characteristics of SCR during Turn Off is the transition of SCR from forward conduction
state to forward blocking state. This transition process involves bringing the anode current below
holding current, sweeping out of charges from outer p and n junction and recombination of holes and
electrons at the interior junction. Thus, it is a dynamic process. This dynamic process of bringing SCR
to off state is called commutation process or turn off process.

6. The middle two layers are split into two separate parts. Because of this, the two transistors are
formed. The transistor T1 is pnp, whereas T2 is npn. The base of T1 is connected to collector of T2.
Similarly base of T2 is connected to collector of T1. These transistors are in common base
configuration. When the SCR is forward biased and gate is open, various currents flow.
The anode to cathode current is ID. The collector current, emitter current and leakage currents of T1 are
related as
𝑰𝒄𝟏 = 𝑎𝟏𝑰𝑫 +𝑰𝒄𝒐𝟏

𝑰𝒄𝟐 = 𝑎𝟐𝑰𝑫 +𝑰𝒄𝒐𝟐

 𝑰𝑫 = 𝑰𝑪𝟏 + 𝑰𝑪𝟐
ID = IC0

1-(a1-a2)

Here ICO is the reverse leakage current of the reverse biased junction J2. And 1 is the common base
current gain of T1, and 2 is common base current gain of T2. Initially when forward voltage is
small, (1 + 2) is very small and less than 1. Hence forward blocking current as given by equation
(1) is also small. As forward voltage applied across the SCR increases, the values of 1 and 2 also
increase. When (1 + 2) tends unity, then ID approaches infinity as given by equation (1) At this
instant, internal regeneration starts and the SCR goes into forward conduction (ON-state) mode. The
current through the SCR is only limited by the external load.
Once the SCR goes into conduction, the two-transistor model is no more applicable. Here note that the
internal regeneration takes place in the SCR due to avalanche breakdown of reverse biased junction
J2. It does not take place when SCR is reverse biased. When the current through the SCR falls below
holding current, the forward blocking state is regained. Then 1 and 2 of transistors are also
reduced to small values. When the gate current Ig is applied, then equation (1) will be written as

𝑰𝑪𝑶 + 𝑰a
ID -
1-(a1 – a2)
Thus, the forward leakage current (ID) is increased due to gate drive (Ig). This leakage current flows
through junction J2 and its avalanche break-down occurs at lower forward voltage. Thus, with the
gate drive, the SCR is turned on at voltages less than VBO. Hence gate becomes convenient way of
triggering the SCR. Once the SCR is turned-on, the gate has no control over its conduction.

7. The GTO can be turned-off by gate drive. Thus, gate has full control over the operation of GTO. The
V-I characteristics of GTO in forward direction are similar to that of SCR. But in reverse direction
GTO has virtually no blocking capability. Observe that GTO starts conducting in reverse direction after
very small reverse (20 to 30 V) voltage. This is because of the anode short structure.

 BASIC STRUCTURE
 Gate and cathodes are highly inter digited with various geometric forms. This maximizes periphery of
the cathode and minimize gate-cathode distance.
 There are n+ regions at regular intervals in the p+ anode layer. This n+ layer makes direct contact
with n- layer. This is called anode short. These speeds up the turn-off mechanism of GTO.
 The operation of GTO can be explained with the help of two transistor analogy. The gain of p-n-p
transistor is reduced. This reduces the regenerative action. Hence turn-off of GTO can be achieved by
negative current from gate.
 From the below graph we infer that the junction J3 blocks reverse voltages. But J3 has very small
reverse breakdown voltage. Thus, GTO has asymmetric voltage blocking capability.

8. IGBT has been developed by combining into it the best qualities of both BJT and PMOSFET. Thus an
IGBT possesses high input impedance like a PMOSFET 3."'1d has low on-state power loss as in a BJT.
Further, IGBT is free from second breakdown problem present in BJT. All these merits have made
IGBT very popular amongst power-electronics engineers. IGBT is also known as metal oxide insulated
gate transistor (MOSIGT), conductively-modulated field effect transistor (COMFET) or gain-
modulated FET (GEMFET). It was also initially called insulated gate transistor (IGT).

It is constructed virtually in the same manner as a power MOSFET. There is, however, a major
difference in the substrate, The n+ 1ayer substrate at the drain in a PMOSFET is now substituted in the
IGBT by a p+ layer substrate called collector C. Like a power MOSFET, an IGBT has also thousands
of basic structure cells connected appropriately on a single chip of silicon. In IGBT, p+ substrate is
called injection layer because it injects holes into n- layer. The n- layer is called drift region. As in other
semiconductor devices, thickness of n- layer determines the voltage blocking capability of IGBT. The p
layer is called body of IGBT. The n- layer in between p+ and p regions serves to accommodate the
depletion layer of pn - junction i.e., junction J2
9. In many power control applications the required voltage and current ratings exceed the voltage and
current that can be provided by a single SCR. Under such situations the SCRs are required to be
connected in series or in parallel to meet the requirements. Sometimes even if the required rating is
available, multiple connections are employed for reasons of economy and easy availability of SCRs of
lower ratings.
Like any other electrical equipment, characteristics/properties of two SCRs of same make and ratings
are never same and this leads to certain problems in the circuit. The mismatching of SCRs is due to
differences in
i. turn-on time
ii. turn-off time
iii. leakage current in forward direction
iv. leakage current in reverse direction and
v. recovery voltage.
Derating Factor is the amount by which the string efficiency deviates from unity or 100%.
DFR = [1 – String Efficiency] = [100 – % String Efficiency]
Derating Factor gives an idea of unused capacity available in a sting of SCRs. This is the reason; it is
a measure of reliability of string. The lesser the value of sting efficiency, the lesser will be voltage /
current sharing by the individual SCRs. This means, more unused capacity will be available with the
string and hence more DFR. But lesser string efficiency increases the cost of string. Thus a
compromise is made in between economy and reliability by properly designing a value of string
efficiency.
String Efficiency of SCR is the degree of capacity utilization of individual SCRs in a string of series /
parallel connected SCRs. String efficiency is always less than 1.

𝐀𝐜𝐭𝐮𝐚𝐥 𝐕𝐨𝐥𝐭𝐚𝐠𝐞/𝐂𝐮𝐫𝐫𝐞𝐧𝐭 𝐑𝐚𝐭𝐢𝐧𝐠 𝐨𝐟 𝐰𝐡𝐨𝐥𝐞 𝐬𝐭𝐫𝐢𝐧𝐠

𝐒𝐭𝐫𝐢𝐧𝐠 𝐄𝐟𝐟𝐢𝐜𝐢𝐞𝐧𝐜𝐲 =
𝑽𝒐𝒍𝒕𝒂𝒈𝒆/𝑪𝒖𝒓𝒓𝒆𝒏𝒕 𝑹𝒂𝒕𝒊𝒏𝒈 𝒐𝒇 𝒐𝒏𝒆 𝑺𝑪𝑹 ∗ 𝑁𝑢𝑚𝑏𝑒𝑟 𝒐𝒇 𝑺𝑪𝑹𝒔 𝒊𝒏 𝒔𝒕𝒓𝒊𝒏𝒈
 When the required voltage rating exceeds the SCR voltage rating, a number of SCRs are
required to be connected in series to share the forward and reverse voltage. As it is not
possible to have SCRs of completely identical characteristics, deviation in characteristics
lead to the following two major problems during series connections of the SCRs:
(i) Unequal distribution of voltage across SCRs.
(ii) Difference in recovery characteristics.

10. The construction of a MOSFET is a bit similar to the FET. An oxide layer is deposited on
the substrate to which the gate terminal is connected. This oxide layer acts as an insulator
(sio2 insulates from the substrate), and hence the MOSFET has another name as IGFET. In
the construction of MOSFET, a lightly doped substrate, is diffused with a heavily doped
region. Depending upon the substrate used, they are called as P-type and N-type MOSFETs.

The voltage at gate controls the operation of the MOSFET. In this case, both positive and negative
voltages can be applied on the gate as it is insulated from the channel. With negative gate bias
voltage, it acts as depletion MOSFET while with positive gate bias voltage it acts as an
Enhancement MOSFET.

The switching characteristics of a power MOSFET are influenced to a large extent by the internal
capacitance of the device and the internal impedance of the gate drive circuit. At turn-on, there is an
initial delay tdn during which input capacitance charges to gate threshold voltage V GST. Here tdn is
called turn-on delay time.
There is further delay tr, called rise time, during which gate voltage rises to VGSP, a voltage sufficient
to drive the MOSFET into on state. During tr, drain current rises from zero to full-on current ID.
Thus, the total turn-on-time is ton=tdn + tr. The turn-on time can be reduced by using low-impedance
gate- drive source.
As MOSFET is a majority carrier device, trn-off process is initiated soon after removal of gat e
voltage at time t1. The turn-off delay time, t df, is the time during which input capacitance discharges
from overdrive gate voltage VI to Vosp. The fall time, tf is the time during which input capacitance
discharges from Vosp to threshold voltage. During tfl drain current falls from ID to zero. So when VGs
≤ VGST, PMOSFET tum-off is complete.

(a)
Transfer Characteristics: This characteristic shows the variation of drain current I D as a
function of gate-source voltage Ves. Threshold voltage VGST is an important parameter of
MOSFET. VGST is the minimum positive voltage between gate and source to induce n-
channel. Thus, for threshold voltage below VGST device is in the off-state. Magnitude of
VGST is of the order of 2 to 3 V.

(b)
Output Characteristics: PMOSFET output characteristics, indicate the variation of drain
current ID as a function of drain-source voltage V DS, with gate-source voltage Ves as a
parameter. For low values of VDS, the graph between lD – VDS is almost linear; this
indicates a constant value of on-resistance RDS=VDS/ID. For given VGS, if VDS is increased,
output characteristic is relatively flat, indicating that drain current is nearly constant. A
load line intersects the output characteristics at A and B. Here A indicates fully-on
condition and B fully-off state. PMOSFET operates as a switch either at A or at B just like
a BJT. When power MOSFET is driven with large gate-source voltage, MOSFET is turned
on, VDSON is small. Here, the MOSFET acting as a closed switch, is said to be driven into
ohmic region (called saturation region in BJT). When device turns on, PMOSFET
traverses iD - VDS characteristics
(c)
from cut-off, to active region and then to the ohmic region.

i. BJT is a bipolar device whereas PMOSFET is a unipolar device.

ii. A PMOSFET has high input impedance (mega ohm) whereas input impedance of BJT is
low (a few kilo-ohm).
iii. PMOSFET has lower switching losses but its on-resistance and conduction losses are
more. A BJT has higher switching losses but lower conduction loss. So, at high frequency
applications, PMOSFET is the obvious choice. But at lower operating frequencies (less
than about 10 to 20 kHz ), BJT is superior.
iv. PMOSFET is voltage-controlled device whereas BJT is current controlled device.
v. PMOSFET has positive temperature coefficient for resistance. Th is makes parallel
operation of PMOSFETs easy. If a PMOSFET shares increased Cl1Trent initially, it heats
 up faster, its resistance rises and this increased resistance causes this current to shift to
other devices in parallel. A BJT has negative temperature coefficient, so current sharing
resistors are necessary during parallel operation of BJTs.
vi. In PMOSFETs, secondary breakdown does not occur , because it has positive temperature
coefficient. As BJT has negative temperature coefficient, secondary breakdown does
occur. In BJT, with decrease in resistance with rise in temperature, the current increases.
This increased current over the same area results in hot spots and breakdown of the BJT.
vii. PMOSFETs in higher voltage ratings have more conduction loss.
viii. The state of the art PMOSFETs are available with ratings upon 500 V, 140 A
whereas BJTs are available with ratings upto 1200 V, 800 A.
11.
12. semiconductor device each statement represents is:
a. Two-terminal three-layer device: Power diode
b. Majority carrier devices: IGBT, SIT and PMOSFET
c. Bipolar devices: Diode, MCT, BJT and IGBT
d. Negative pulse turn-on device: MCT
e. On operation in ohmic region: PMOSFET
f. Normally on device: SIT
g. ON-state in saturation region: BJT
h. Two-terminal two-layer device: Signal Diode
i. Uncontrolled turn-on and turn-off device: Diode
j. Controlled turn-on and turn-off devices: BJT, MOSFET, IGBT, SIT, MCT