Received May 22, 2021, accepted June 9, 2021, date of publication June 14, 2021, date of current version

June 21, 2021.

Digital Object Identifier 10.1109/ACCESS.2021.3088939

Comparative Analysis of Hybrid NPP and NPC

Seven-Level Inverter With Switched-Capacitor
YUANMAO YE , (Member, IEEE), GUOXIN ZHANG, JINLIANG HUANG,
SHIKAI CHEN, AND XIAOLIN WANG
School of Automation, Guangdong University of Technology, Guangzhou 510006, China
Corresponding author: Xiaolin Wang ([email protected])
This work was supported in part by the National Natural Science Foundation of China under Grant 51907033, and in part by the Natural
Science Foundation of Guangdong Province under Grant 2020A1515110977.

ABSTRACT In this work, the general structure of a hybrid NPP/NPC seven-level inverter is derived from
a dual-T-type inverter. Compared with the original structure, the general structure is more flexible as there
are four specific circuit configurations to meet different applications. In addition to self-balanced capacitor
voltages and boost capability, various commercial NPP and NPC modules can be used to speed up the
design process. Circuit description, operation principle, modulation and simulation results are analyzed
comparatively. Theoretical analysis and simulation comparison indicate that the four configurations of the
hybrid NPP/NPC inverter have their own merits and demerits. Especially, except for a bidirectional switch, all
switching components of the NPP + NPC configuration have the same voltage stress as the dc input voltage
making it is better in the aspect of component selection, and it is more suitable for high voltage applications.
The performance of the NPP + NPC inverter is experimentally demonstrated by an 1kW prototype and its
efficiency is closed to 96%.

INDEX TERMS Multilevel inverter, neutral-point-piloted, neutral-point-clamped, switched-capacitor.

I. INTRODUCTION successfully applied for high-speed motor drives [9]. In the-

With the rapid development of new energy and electric vehi- ory, the NPP has the same operation and control as the
cles, the demand for high-performance inverters is grow- NPC [10]. However, two high-voltage-rated switches are
ing rapidly [1], [2]. As multilevel inverters (MLIs) have employed in NPP and this structure is usually limited to the
the advantages of near-sinusoidal output voltage waveforms, three-level configuration [11], [12].
reduced voltage stress (dv/dt), operation with lower switch- To get more output levels, various hybrid MLIs have
ing frequency and so on, they have been widely applied in been developed by combining NPC, FC, CHB and NPP
motor drivers, renewable energy sources and high-voltage in [13]–[18]. Specifically, the nested NPP (NNPP) inverter
dc transmission [3]. The conventional types of MLIs, such presented in [13] is capable of generating five output lev-
as neutral-point-clamped (NPC) and flying capacitor (FC) els. To reduce the number of switches, another 5-level
inverters, are very attractive due to their advantages of high NNPP inverter is developed in [14] by removing one bidi-
efficiency and high power density [4], [5]. However, when rectional switch, but at the cost of a complex strategy for
these topologies are expanded to more output levels, their capacitors’ voltage balancing. In the work [15], [16], two
applications are restricted by complex clamping circuits and hybrid seven-level inverters are developed by cascading the
the imbalance of capacitor voltage [6]. Another conventional end-side flying-capacitor-fed H-bridge with the front-side
type of MLI, cascaded H-bridge (CHB) inverter, attracts three-level inverter. With the combination of some features
attention because of its superiority like modularity and simple of 3-level FC and 3-level NPC, the active NPC (ANPC)
structure [7]. However, a large number of isolated dc sources 7-level inverter is introduced in [17]. In the work [18], the
are required for each H-bridge unit [8]. Additionally, neutral- 9-level ANPC inverter is formed by a two-level converter
point-piloted (NPP) inverter, also known as T-type inverter, is and a five-level ANPC unit. However, a common problem
for the MLIs of [15]–[18] is that the voltage balance of
The associate editor coordinating the review of this manuscript and capacitors depends on the proper selection of redundant
approving it for publication was Zhilei Yao . switching states, which requires complex voltage sensors and

This work is licensed under a Creative Commons Attribution 4.0 License. For more information, see https://creativecommons.org/licenses/by/4.0/
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control algorithms. Moreover, none of the MLIs of [13]–[18]

have voltage-boosting capability.
To improve the voltage-boosting capability and solve the
problem of capacitor voltage balancing, a new type of MLIs
based on switched-capacitor (SC) technique has been devel-
oped in recent years [19]–[21]. In SC-MLIs, SCs are taken
as dc voltage sources and they are charged by the dc source
through switching components. From the aspect of mini-
mizing power transmission loss, it is desirable to use fewer
switches in the charging path of SCs [22]. Taking the 7-level
SC-MLIs presented in [23]–[30] as examples, there are four
transistors found in SCs’ charging path of [24]–[30], while
two transistors found in SC’s charging path of [23]. In addi-
FIGURE 1. Hybrid NPP/NPC 7-level inverter. (a) Dual-T-type structure [23].
tion, the 7-level inverter of [23] is developed by cascading (b) General structure. (c) Three-phase configuration. (d) Equivalent circuit.
two NPP units. Various commercial three-level NPP modules
can therefore be used to reduce the design difficulty and
speed up commercialization. However, the two NPP units are When the dc input voltage is 2E, the capacitor CS1 and CS2
with different voltage stresses. This is not beneficial to the are charged by the dc source through S2 − DS1 and S1 − DS2 ,
selection of components. respectively. Hence, the transistors S1 − S2 , diodes DS1 − DS2
In theory, a three-level NPC circuit has the same function and capacitors CS1 − CS2 are rated at 2E while the switch S3
as a T-type unit, and then the dual-T-type 7-level inverter is rated at E. As the switches S4 and S5 are in parallel with
can be extended to four different structures, i.e., NPP + the series-connection of CS1 and CS2 and the switch S6 is
NPP [23], NPP + NPC, NPC + NPC and NPC + NPP. Con- connected at the midpoint of CS1 and CS2 , the voltage stresses
sidering the three-level NPC and NPP circuits have different for S4 and S5 are 4E while that for S6 is 2E.
configurations and they have their own merit and demerit, In addition, to reduce charging current variation di/dt of
the four structures of 7-level inverters must have different SCs at switching instants, a small inductor L is inserted
performances. Hence, the purpose of this paper is to analyze between the left-side unit and the midpoint of CS1 and CS2 .
the four structures and compare their performance, and then Its value is very small so that the effect will be neglected in
find the best solution for 7-level inverters. the following analysis.
The rest of the paper is organized as follows. In Section II,
the general structure of the hybrid NPP/NPC 7-level inverter B. OPERATION PRINCIPLE
is derived from the dual-T-type 7-level inverter of [23]. Then, To facilitate analysis, it is assumed that all switching devices
the operation is analyzed and the characteristics of the four are ideal and all the capacitors are so large that their voltages
structures are compared comprehensively. In Section III, the are constant.
hybrid NPP/NPC 7-level inverter is further analyzed when At any time, only one of the switches S1 ∼ S3 is turned ON
it operates with the PD-PWM strategy. After that, various while the other two are OFF and the switches S4 ∼ S6 have
existing 7-level inverters are taken into comparison with the the same operation principle, there are therefore a total of 9
four structures of the hybrid NPP/NPC 7-level inverter in switching states correspond to 7 levels of the output voltage,
Section IV. The simulation and experimental verification are as illustrated in Table 1. Note that 1 and 0 represent ON and
given in Section V and the paper is finally concluded in OFF states of the related switch, respectively. Capacitors’
Section VI. states of ‘C’, ‘D’ and ‘N’ are indicative of charging, discharg-
ing and idle states, respectively.
II. HYBRID NPP/NPC SEVEN-LEVEL TOPOLOGIES
A. CIRCUIT DESCRIPTION
TABLE 1. Switching states of the equivalent circuit of fig. 1(d).
As shown in Fig. 1(a), the dual-T-type 7-level inverter of [23]
involves two dc-link capacitors Cdc1 and Cdc2 , two SCs CS1
and CS2 , two T-type switching units as well as two charging
transistors T1 and T2 for SCs. Considering the three-level
NPC switching circuit has the same function as a T-type unit
and the two charging transistors T1 and T2 can be replaced
with two diodes DS1 and DS2 , the general structure of the
hybrid NPP/NPC 7-level inverter is derived as illustrated
in Fig. 1(b) and its three-phased configuration is shown
in Fig. 1(c). As the NPC and NPP units have the same function
and both of them can be equivalent to a kind of circuit that
is implemented by three switches, as depicted in Fig. 1(d).

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To optimize the capacitor voltage ripples, the states ‘4’ developed as shown in Fig. 3(a). It is formed by a current
and ‘6’ will not be adopted in actual operation so that the limiting resistor RS and its by-pass switch T .
remaining 7 state circuits are shown in Fig. 2. It indicates that During the soft-start stage, the by-pass switch T is turned
the capacitors CS1 and CS2 are recharged by the dc source OFF and all charging current flows through the current limit-
directly for the levels of ±E and ±3E. And the load current ing resistor RS . The two transistors S1 and S2 are controlled by
can flow in both directions. a pair of complementary high-frequency square wave signals,
so that CS1 and CS2 are alternately charged by the dc source
through S2 − DS1 and S1 − DS2 . After all the capacitors
are charged to their rated voltages, the by-pass switch T is
turned ON.

FIGURE 2. State circuits of the hybrid NPP/NPC 7-level inverter. (a) uO =

0. (b) uO = ±E. (c) uO = ±2E. (d) uO = ±3E.

FIGURE 3. Soft-start of the hybrid NPP/NPC 7-level inverter. (a) Circuit

configuration. (b) Simulation waveforms. (c) Experimental results.
C. SELF-BALANCED CAPACITOR VOLTAGES
As illustrated in Fig. 1 and Table 1, both of structure and
operation of the hybrid NPP/NPC 7-level inverter are sym- When the dc input voltage is 240V, RS = 50, Cdc1 =
metrical. The capacitors CS1 and CS2 are responsible for Cdc2 = 1500µF, CS1 = CS2 = 2000µF, L = 1µH and
the positive- and negative-half cycles of the output voltage, the switching frequency for S1 and S2 is set to 5kHz, the
respectively. For both resistive and inductive loads, the func- simulation and experimental waveforms including the capac-
tions of the two capacitors are the same and they handle the itors’ voltages VCS1,2 , VCdc1,2 , the start-up current iRs and
same amount of power. Hence, the two capacitor voltages are the capacitors’ current iL are shown in Figs. 3(b) and 3(c).
balanced naturally. Moreover, CS1 and CS2 are connected in The results indicate that the start charging current of capac-
parallel with the dc input source for the levels of +E and −E, itors is effectively limited by the soft-start circuit. Finally,
respectively. Their voltages can therefore be balanced to the the voltages VCS1,2 and VCdc1,2 stabilize at 240V and 120V,
same as the input voltage 2E automatically. respectively.

D. PRE-CHARGING CIRCUIT AND SOFT-START E. COMPARISON OF DIFFERENT CONFIGURATIONS

Although all the capacitors of the hybrid NPP/NPC inverter As mentioned before, there are four specific configurations
can be self-charged to their rated voltages after start-up, the for the hybrid NPP/NPC 7-level inverter. Table 2 shows the
inrush charging current will occur as two diodes DS1 and comparison of the four configurations regarding the number
DS2 are connected in series with the dc source and the initial of transistors (NT ), the number of diodes (ND ), the number of
capacitor voltages are zero. This will challenge the safety of capacitors (NC ), the number of gate drivers (NG ), the max-
components. To overcome this issue, a soft-start circuit is imum blocking voltage (MBV) of switching components,

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TABLE 2. Comparison of the four circuit configurations.

TABLE 3. Switching states of the NPP + NPC 7-level inverter.

FIGURE 4. PD-PWM strategy for the NPP + NPC 7-level inverter.

(a) Modulation signal and carriers. (b) Gating signals. (c) Output voltage.
as well as the total standing voltage (TSV) of switches and
diodes.
The comparison result indicates that the four circuit config-
urations have the same number of transistors and capacitors. When the PD-PWM is applied, there are six carriers
The configuration NPC + NPC has minimum MBV and u1 ∼ u6 used to compare with the reference signal uref to
TSV of switches, but it requires the maximum number of generate the gating signals of the NPP + NPC 7-level inverter
diodes and gate drivers and its TSV of diodes is up to 10. as shown in Fig. 4(a). As illustrated in Table 3, the transistor
The configurations NPC + NPP and NPP + NPP have fewer S4 is turned ON for the levels of +E to +3E. Its gating
diodes and gate drivers as well as lower TSV of diodes, but signal VGS4 is therefore generated by comparing uref with u3 ,
their MBV is twice of NPC + NPC. The configuration NPP + i.e., VGS4 = 1 when uref > u3 . Similarly, the gating signal
NPC has two more diodes than the NPP + NPP and higher VGS5 is generated by comparing uref with u4 , i.e., VGS5 =
TSV than the NPC + NPC, but it has the lowest MBV and 1 when uref > u4 . The transistors S6 and S7 are controlled in
TSV of switches as well as less number of diodes and gate complementary with S4 and S5 , respectively. For the transistor
drivers. Overall, each configuration has its own merits and S1 , it is turned ON for the levels of −E and +3E. Its gating
demerits. Just from the aspect of the selection of switches, signal generation logic is that VGS1 = 1 when uref > u1
NPP + NPC is better as all switching components are rated or u5 < uref < u4 . Similarly, the gating signal generation
at the dc input voltage 2E except the bidirectional switch S3 . logic for the transistor S2 is that VGS2 = 1 when uref < u6
Hence, the following sections take it as an example to analyze or u3 < uref < u2 . The transistor S3 is turned ON only when
the features of the hybrid NPP/NPC 7-level inverter. both S1 and S2 are OFF. With these gating signals’ generation
logic, the modulation logic circuit of the NPP + NPC 7-
III. PERFORMANCE ANALYSIS WITH PD-PWM STRATEGY level inverter is summarized as shown in Fig. 5. As a result,
A. MODULATION the ideal waveforms for the gating signals and output voltage
As well known, multi-carrier PWM (MCPWM) is the most of the NPP + NPC 7-level inverter with PD-PWM are shown
popular modulation strategy for MLIs. For single-phase in Figs. 4(b) and 4(c).
MLIs, there is almost the same performance for the three
types of MCPWM methods, i.e., phase-disposition PWM B. DESIGN OF SWITCHED CAPACITORS
(PD-PWM), phase-opposition-disposition PWM (POD- The same as other SC-based MLIs, the value of capacitors
PWM) and alternate-phase-opposition-disposition PWM should be determined by their voltage ripples.
(APOD-PWM). For the three-phase configuration of MLIs, With the PD-PWM, the capacitor CS1 continuously dis-
however, the PD-PWM is much better than POD-PWM and charges to the load during the interval of θ ∼ π − θ, while
APOD-PWM in the aspects of waveform shape and THD of CS2 continuously discharges to the load during the interval
the output line voltages [31]. Hence, this work adopts the of π + θ ∼ 2π − θ, as illustrated in Fig. 6. The amount of
PD-PWM to modulate the NPP + NPC 7-level inverter and charge flowing out of CS1 during the interval of θ ∼ π − θ
then analyzes its performance. is equivalent to that flowing out of CS2 during the interval

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FIGURE 6. SCs’ voltage ripples of the hybrid NPP/NPC 7-level inverter

with PD-PWM strategy.

FIGURE 5. Modulation logic of the NPP + NPC 7-level inverter with

PD-PWM strategy.

of π + θ ∼ 2π − θ, i.e.,
Z (π −θ)/ω
QCS1 = QCS2 = IO sin(ωt − ϕ)dt (1)
θ/ω
where ω is the angular frequency, IO is the amplitude of the
load current, ϕ is the phase difference between the output
voltage and the load current, θ is an angle when the reference
signal uref reaches 2, i.e., FIGURE 7. Capacitance versus the modulation ratio and the output power
when δ = 10%.
2
θ = arcsin (2)
Aref when δ = 10% and ω = 100π. It indicates that CS1,2 increases
where Aref is the amplitude of the reference signal uref . along with the modulation ratio Ma and the output power PO .
Assuming the two capacitors have the same capacitance
CS1,2 , their voltage ripples are given by C. CHARGING CURRENT STRESS REDUCTION
QCs1,2 In the hybrid NPP/NPC 7-level inverter, CS1 and CS2 are
1VCS1,2 = (3) charged by the dc source through S2 − DS1 and S1 − DS2 ,
Cs1,2
respectively. If there is no current limit, huge current pulses
The maximum voltage ripple is obtained when the phase will appear at switching instants.
difference ϕ = 0, i.e. the load is pure resistive. In this case, Taking CS1 as an example, after continuously discharging
the amplitude of the load current is VO /R and the amplitude for the interval of θ ∼ π − θ, as illustrated in Fig. 6,
of the output voltage is estimated by VO = E × Aref . The it operates alternately in charging and discharging modes
voltage ripples can be further expressed by when the output level is switched between +E and +2E.
2E q 2 With the small inductor L, the equivalent discharging and
1VCS1,2 ≤ Aref − 4 (4)
ωRCs1,2 charging circuits are shown in Figs. 8(a) and 8(b), and the
ideal waveforms are depicted in Fig. 8(c), wherein VF1 is the
Considering that the voltage ripple ratio of SCs is δ =
forward voltage drop of DS1 , r1 is the total resistance of the
1VCS1,2 /2E and 2E = 240V, the output power and modula-
charging loop.
tion ratio are PO = VO × IO /2 and Ma = Aref /3, respectively,
The waveform of Fig. 8(c) indicates that the capacitor
the capacitance CS1,2 can be determined by
q current can be switched from the load current iO to the pulse
PO 9M 2a − 4 charging current immediately when L = 0. The charging
CS1,2 ≥ (5) current peak can be limited by the loop resistance r1 but with
64800ωδMa2 high current stress di/dt.
Intuitively, Fig. 7 shows the curves of the capaci- When L > 0, the current will first drop from −iO to
tance versus the modulation ratio and the output power, zero and then rise gradually. The greater the inductance L,

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2) SWITCHING LOSS OF TRANSISTORS

Generally, there are two methods for estimating the switching
loss of a transistor, one of which is based on the overlap of
the transistor’s current and voltage at switching instants, and
the other is based on the transistor’s switching frequency fS
and its parasitic capacitance COSS as well as its voltage stress
VDS [33], i.e.
PLoss_sw = fS C oss V 2DS (7)
For the NPP unit, the switching frequency S3 is equal to the
carriers’ frequency fC while that of S1 and S2 are half of the
carriers’ frequency fC . The voltage stresses of S1 and S2 are
2E while that of S3 is E, the switching loss of the NPP unit is
therefore given by
PLoss_sw1 = 4fC C oss1,2 E 2 + fC C oss3 E 2 (8)
FIGURE 8. Operation of CS1 when uO is switched between +E and +2E .
(a) Equivalent discharging circuit. (b) Equivalent charging circuit.
where Coss1,2 is the parasitic capacitance for S1 and S2 , Coss3
(b) Capacitor voltage and current variation. is that for S3 .
In addition, the diodes DS1 and DS2 have the same switch-
ing frequency as S1 and S2 , their switching loss is therefore
the slower the capacitor current variation and the slower the given by
charging speed. Considering there is a small dead-time for
PLoss_sw2 = 4fC C osds1,2 E 2 (9)
S1 and S2 in practice, the inductor L should therefore be
so small that its current can drop to zero during the dead- where Cosds1,2 is the parasitic capacitance for DS1 and DS2 .
time. In this case, the energy stored in the small induc- For the NPC unit, S4 and S6 operate at carriers’ frequency
tor L will be dissipated through sneak circuits as analyzed when the output level is switched between 0 and +E, S5
in [32]. and S7 operate at carriers’ frequency when the output level
Overall, the amplitude of the pulse charging current can is switched between 0 and −E, as shown in Fig. 3. As the
be effectively limited by the components’ parasitic resistance diodes D1 and D2 provide current paths for the level of 0, their
of the charging loop, and the current variation di/dt can be switching frequency is the same as S4 ∼ S7 . In one cycle of
limited by the inductor L. the output voltage, the number of state switching for each of
S4 ∼ S7 and D1 − D2 is therefore given by
D. POWER LOSS ANALYSIS
arcsin A1ref fC 1
As the NPP + NPC 7-level inverter operates alternately in the nS = 2 × fC × = arcsin (10)
charging and discharging processes of capacitors, the power 2π fref πfref Aref
loss can be summarized into three categories which are where Aref is the amplitude of the reference signal uref .
charging loss of capacitors, switching loss of transistors and As the voltage stresses for all components of the NPC are
conduction loss caused by the load current. 2E, their total switching loss is given by
PLosssw3 = 4Coss4∼7 + 2Cosd1,2 × nS × fref × (2E)2



1) CHARGING LOSS OF SWITCHED CAPACITORS
16Coss4∼7 + 8Cosd1,2 E 2 f C


For the NPP + NPC 7-level inverter, CS1 is charged through 1
= arcsin (11)
S2 − DS1 for the level of +E while CS2 is charged through π Aref
S1 −DS2 for the level of −E. The energy loss is the difference
where Coss4∼7 is the parasitic capacitance for S4 ∼ S7 ,
between the energy flowing out of the dc source and that flow-
Cosd1,2 is that for D1 and D2 .
ing into the capacitor, and it is determined by the capacitors’
The total switching loss of the NPP + NPC 7-level inverter
voltage ripple 1VCS1,2 . Hence, the charging loss of CS1 and
is the sum of (8), (9) and (11).
CS2 is given by
1 3) CONDUCTION LOSS CAUSED BY LOAD CURRENT
PLoss_cr = Cs1,2 1V 2CS1,2 fref × 2 = CS1,2 1V 2CS1,2 fref (6) For the NPP unit, one of S1 , S2 and S3 are turned ON to
2
provide paths for the load current at any time.
where again CS1,2 is the capacitance, 1VCS1,2 is the voltage For the NPC unit, two of S4 ∼ S7 are turned ON to provide
ripple as shown in Fig. 6, fref is the frequency of the reference paths for the load current at any time. The diodes D1 and D2
signal uref . This part of power loss is actually absorbed by the provide paths for the level of 0, therefore, there is no current
parasitic resistance of components in the charging loop. flowing through them for a pure resistive load.

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TABLE 4. Comparison results of different 7-level inverters.

Considering the voltage stress for S1,2,4∼7 is double that path of SCs, the total conducting transistors (TCT) of all
for S3 but S3 is implemented by two anti-series transistors, output levels, the MBV and TSV of switches and diodes,
it is assumed that all switches have the same on-resistance the voltage gain (VG), the cost function (CF), the self-balance
and the same forward voltage drop. (SB) capability for capacitor voltages, and the applicability
Except for the level of 0, the load current always flows of various 3-level NPC or NPP commercial modules (CM),
through one dc-link capacitor. And it flows through one of as illustrated in Table 4. Here the VG is the ratio of the
CS1 and CS2 during the levels ±2E and ±3E. To simplify maximum output voltage to the dc input voltage, and the CF
the analysis, it is assumed that the load current always flows is defined by
through one dc-link capacitor and one SCs, and the equivalent NT +ND +NC +NG +TCT +TSV sw +TSV dio
series resistance is ESReq = ESRdc + ESRSC . CF = (14)
7
Summing up the above analysis, the conduction loss
caused by the NPP and NPC units as well as the capacitors The comparison results indicate that two hybrid cascaded
are therefore given by inverters of [15], [16] and the ANPC inverter of [17] have the

2 minimum number of transistors and lower MBV and CF, but
PLoss_Con1 = 3rS1 + ESReq Irms + 3V FT Iav (12) they don’t have the boost capability and the voltage balance
where rS1 and VFT are the on-resistance and forward voltage of the flying capacitors depends on the switching sequence
drop for each of the transistors, Irms and Iav are the rms and selection. Hence, it is inevitable to sense the flying capac-
average values of the load current. itors’ voltage and control it through a complex algorithm.
For the diodes DS1 and DS2 , they provide load current paths As mentioned before, the two NPP units in [23] are with
for the levels of ±E. And all currents charged into CS1 and different voltage stresses and its MBV is up to 4. In the
CS2 have to flow through DS1 and DS2 , respectively, and these works [24]–[29], the MBV is reduced to 2, and the TSV of
currents are provided to load for the levels of ±2E and ±3E. switches and diodes of [24]–[28] is lower than the hybrid
Hence, all load currents have to flow through DS1 and DS2 . NPP/NPC topologies. However, the TCT of [24]–[26], [29]
The power loss of the two diodes caused by the load current all exceeded 30 while the structure of [27], [28] cannot
is therefore given by be extended for three-phase applications. For the inverter
√ of [30], too many transistors are used. Additionally, the NS_C
2 2 of [24]–[30] is 4 which increases power transmission loss.
PLoss_Con2 = VFD × Iav = Irms VFD (13)
π In contrast, the four hybrid NPP/NPC topologies employ the
where VFD is the forward voltage drop of DS1 and DS2 , fewest transistors and gate drivers. They have lower TCT, and
Iav is the average value of the load current for positive- or the NS _C is 2. The self-balanced capacitor voltages and boost
negative-half cycle. capability are also competitive compared to the topologies
The total conduction loss of the NPP + NPC 7-level of [15]–[17]. Moreover, various commercial 3-level NPC
inverter is the sum of (12) and (13). or NPP modules can be applied in the hybrid NPP/NPC
topologies for simplifying the design process and speeding
IV. COMPARISON WITH OTHER 7-LEVEL INVERTERS up commercialization.
For a fair study, various 7-level inverters presented in the Moreover, just from the aspect of the number of compo-
recent three years are taken to compare with the hybrid nents, the PUC and MPUC 7-level inverters of [34], [35]
NPP/NPC 7-level inverter in terms of the numbers of tran- use fewer components than the proposed inverter. However,
sistors (NT ), diodes (ND ), capacitors (NC ), gate drivers (NG ), the maximum voltage level of the PUC inverter is equal to
the number of switching components (NS _C ) in the charging the dc input voltage while that for the MPUC inverter is the

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sum of the two dc sources. They therefore do not have boost

capability. In contrast, the proposed uses a single dc source
and it has boost capability. Of course, the boosting feature
is at the cost of using two large capacitors CS1 and CS2 .
Moreover, easy three-phase expansion is another advantage
of the proposed inverter compared with the PUC and MPUC
inverters.

V. SIMULATION AND EXPERIMENTAL RESULTS

To make a comparative analysis and verify the feasibility of
the hybrid NPP/NPC 7-level inverter, both simulation and FIGURE 10. Efficiency comparison.

experimental results for single-phase configuration are pro-

vided in this section.

A. SIMULATION RESULTS
Four simulation models were built in the PLECS software by
referring to the structure of Fig. 1(b), wherein all parameters
and components are given in Table 5.

TABLE 5. Specification and components of the simulation models.

FIGURE 11. Simulation results of Ma changing of the NPP + NPC

configuration for an inductive load 100-50mH.

given in Table 5, three categories of power loss of the NPP +

NPC configuration can be calculated, i.e., the charging loss of
capacitors is 19.2W, the switching loss of transistors is 3.8W
and the conduction loss caused by the load current is 28.54W.
As a result, the total power loss of the NPP + NPC topology
is 51.54W, which is slightly lower than the simulation result
of 53.69W.
Fig. 10 shows the efficiency comparison of the
hybrid NPP/NPC topologies and the other three inverters
of [24]–[26], wherein all simulation models were built in the
PLECS software under the same conditions. It indicates that
the two hybrid topologies of NPP + NPP and NPP + NPC
have higher efficiency when the load changes from 100 to
FIGURE 9. Power loss breakdown of the hybrid NPP/NPC topologies for a
resistive load 100. 500. Moreover, although the NPP + NPP configuration
has higher efficiency, it is difficult to be used for high
Fig. 9 shows the power loss breakdown of the hybrid voltage applications as it uses two high-voltage transistors.
NPP/NPC topologies for a resistive load 100. Specifically, In contrast, the NPP + NPC configuration is more suitable
the measured power loss caused by capacitors CS1 , CS2 and for high voltage applications as it also has high efficiency
diodes DS1 , DS2 for four topologies are almost the same. and the unified blocking voltage of components.
As CS1 and CS2 are charged by the dc source through the When the modulation ratio Ma changes from 0.9 to 0.1,
left-side unit of Fig. 1(b), the power loss of the left-side unit the simulation results of the NPP + NPC inverter with an
is higher than that of the right-side unit. Based on the power inductive load 100-50mH are shown in Fig. 11. It indicates
loss analysis of Section III-D and the simulation parameters that the number of output levels changes from 7 to 5 and

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further to 3 as the decrease of Ma . However, the four capaci-

tors’ voltages are very stable and self-balanced.

B. EXPERIMENTAL RESULTS
An 1kW experimental prototype of the NPP + NPC 7-level
inverter was built as shown in Fig. 12. The specification and
components are listed in Table 6. The PD-PWM strategy is
implemented in an FPGA controller and the modulation ratio
Ma is set to 0.9.

TABLE 6. Specification and Components of the NPP + NPC 7-Level

Prototype.

FIGURE 13. Experimental results for a resistive load 50. (a) Output
voltage and Switches’ voltages. (b) Capacitor voltages.

the small inductor L, the charging current changes smoothly

at switching instants and its variation di/dt is suppressed
FIGURE 12. Experimental prototype of the NPP + NPC 7-level inverter. effectively.
Fig. 15 shows the experimental waveforms for an inductive
Fig. 13 shows the experimental waveforms for a resistive load 50-50mH. It can be observed from Fig. 15(a) that the
load 50. It can be observed from Fig. 13(a) that the output output voltage uO is still a staircase PWM waveform and the
voltage uO is a 7-level PWM waveform and its maximum output current iO is a nearly sinusoidal wave. The measured
value is nearly 360V which is 1.5 times the dc input voltage. rms values of uO and iO are 224.36V and 4.25A, respectively.
The measured rms value of uO is 224.58V. As the input The capacitor voltages still can be self-balanced and have
current is 4.39A, the power conversion efficiency is therefore some ripples. As shown in Fig. 15(b), the harmonics of uO
about 95.74%. Except for the switch S3 is rated at 120V, all are mainly distributed around the carrier frequency 5kHz and
other switches are rated at 240V, which demonstrates that the its integer multiple and there are a few harmonics of iO . The
voltage stresses for all switches do not exceed the dc input low harmonic components of uO are suppressed by the PD-
voltage. As shown in Fig. 13(b), the voltages of Cdc1 and PWM strategy.
Cdc2 are maintained at 120V while that of CS1 and CS2 are The dynamic responses of the prototype are shown
maintained at 120V. The measured voltage ripples for CS1 and in Fig. 16. It indicates that the output current and capacitor
CS2 are about 15.28V. It is higher than the theoretical value voltages can quickly be in another steady state while the
of 13.86V estimated by equation (4), which is mainly caused output voltage is very stable for the step-change of either
by the error of capacitance and the line impedance. resistive load or inductive load. Additionally, the power con-
Fig. 14 shows the charging current waveform of the version efficiency increases to 96.85% when the load changes
switched capacitors CS1 and CS2 with and without inductor to 100.
L. The maximum charging current spike is found when the Finally, when the load R = 50, the power loss distribution
voltages of CS1 and CS2 reach their minimum values. With of the NPP + NPC 7-level prototype is estimated according

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FIGURE 14. Charging current waveform of the switched capacitors CS1

and CS2 . (a) Without inductor L. (b) With inductor L.

FIGURE 16. Waveforms of dynamic responses. (a) Step-change of load

between 50 and 100. (b) Step-change of load between 50-50mH and
100-50mH.

FIGURE 17. Power loss distribution of the prototype when R = 50.

(a) Three types of power losses. (b) Power loss breakdown of
components.

of capacitors. As a result, capacitor loss accounts for the

FIGURE 15. Experimental results for an inductive load 50-50mH.
majority of total power loss, followed by transistor loss, while
(a) Output voltage, current and capacitor voltages. (b) Frequency diode loss is relatively small.
spectrum of the output voltage and current.

VI. CONCLUSION
to the analysis of Section III-D, as shown in Fig. 17. The This paper analyzed comparatively a hybrid NPP/NPC
results indicate that the majority of power loss is caused by 7-level inverter structure with four specific circuit config-
the charging loss of the capacitors. This part of the loss will urations. The general structure is derived from the recent
be consumed by the parasitic resistance in the charging loop work [23] and it has a boosting factor of 1.5 and self-balanced
including on-resistance of transistors and diodes and ESR capacitor voltages. According to the theoretical analysis and

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 Y. Ye et al.: Comparative Analysis of Hybrid NPP and NPC Seven-Level Inverter

simulation results, it is found that the four configurations of [18] N. Sandeep and U. R. Yaragatti, ‘‘Operation and control of a nine-
the NPP/NPC inverter have their own merits and demerits. level modified ANPC inverter topology with reduced part count for
grid-connected applications,’’ IEEE Trans. Ind. Electron., vol. 65, no. 6,
Especially, the dual-NPP inverter has the advantages of fewer pp. 4810–4818, Jun. 2018.
components and higher efficiency, while the NPP + NPC [19] Y. Hinago and H. Koizumi, ‘‘A switched-capacitor inverter using
configuration has lower voltage stress of components making series/parallel conversion with inductive load,’’ IEEE Trans. Ind. Electron.,
vol. 59, no. 2, pp. 878–887, Feb. 2012.
it more suitable for high-voltage applications. Experimental [20] Y. Ye, K. W. E. Cheng, J. Liu, and K. Ding, ‘‘A step-up switched-capacitor
results indicate that the NPP + NPC inverter has good per- multilevel inverter with self-voltage balancing,’’ IEEE Trans. Ind. Elec-
formance for both steady-state and dynamic change of loads. tron., vol. 61, no. 12, pp. 6672–6680, Dec. 2014.
[21] A. Iqbal, M. D. Siddique, B. P. Reddy, and P. K. Maroti, ‘‘Quadruple boost
In addition, various commercialized NPC and NPP modules multilevel inverter (QB-MLI) topology with reduced switch count,’’ IEEE
can be used to simplify the design of the hybrid NPP/NPC Trans. Power Electron., vol. 36, no. 7, pp. 7372–7377, Jul. 2021.
inverters. [22] T. Roy and P. K. Sadhu, ‘‘A step-up multilevel inverter topology using novel
switched capacitor converters with reduced components,’’ IEEE Trans. Ind.
Electron., vol. 68, no. 1, pp. 236–247, Jan. 2021.
REFERENCES [23] S. S. Lee and K.-B. Lee, ‘‘Dual-T-type seven-level boost active-neutral-
point-clamped inverter,’’ IEEE Trans. Power Electron., vol. 34, no. 7,
[1] L. Franquelo, J. Rodriguez, J. Leon, S. Kouro, R. Portillo, and M. Prats,
pp. 6031–6035, Jul. 2019.
‘‘The age of multilevel converters arrives,’’ IEEE Ind. Electron. Mag.,
[24] S. S. Lee, Y. Bak, S.-M. Kim, A. Joseph, and K.-B. Lee, ‘‘New family
vol. 2, no. 2, pp. 28–39, Jun. 2008.
of boost switched-capacitor seven-level inverters (BSC7LI),’’ IEEE Trans.
[2] Z. Yao, Y. Zhang, and X. Hu, ‘‘Transformerless grid-connected PV inverter
Power Electron., vol. 34, no. 11, pp. 10471–10479, Nov. 2019.
without common mode leakage current and shoot-through problems,’’
[25] M. J. Sathik, N. Sandeep, and F. Blaabjerg, ‘‘High gain active neutral point
IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 67, no. 12, pp. 3257–3261,
clamped seven-level self-voltage balancing inverter,’’ IEEE Trans. Circuits
Dec. 2020.
Syst. II, Exp. Briefs, vol. 67, no. 11, pp. 2567–2571, Nov. 2020.
[3] M. Vijeh, M. Rezanejad, E. Samadaei, and K. Bertilsson, ‘‘A general [26] J. Zeng, W. Lin, and J. Liu, ‘‘Switched-capacitor-based active-neutral-
review of multilevel inverters based on main submodules: Structural point point-clamped seven-level inverter with natural balance and boost ability,’’
of view,’’ IEEE Trans. Power Electron., vol. 34, no. 10, pp. 9479–9502, IEEE Access, vol. 7, pp. 126889–126896, 2019.
Oct. 2019. [27] J. Liu, X. Zhu, and J. Zeng, ‘‘A seven-level inverter with self-balancing and
[4] S. K. Giri, S. Mukherjee, S. Kundu, S. Banerjee, and C. Chakraborty, ‘‘An low-voltage stress,’’ IEEE J. Emerg. Sel. Topics Power Electron., vol. 8,
improved PWM scheme for three-level inverter extending operation into no. 1, pp. 685–696, Mar. 2020.
overmodulation region with neutral-point voltage balancing for full power- [28] B. P. Reddy, M. D. Siddique, A. Iqbal, S. Mekhilef, S. Rahman, and
factor range,’’ IEEE J. Emerg. Sel. Topics Power Electron., vol. 6, no. 3, P. K. Maroti, ‘‘7L-SCBI topology with minimal semiconductor device
pp. 1527–1539, Sep. 2018. count,’’ IET Power Electron., vol. 13, no. 14, pp. 3199–3203, Nov. 2020.
[5] A. Salem, H. Van Khang, K. G. Robbersmyr, M. Norambuena, and [29] A. Iqbal, M. D. Siddique, M. Al-Hitmi, and S. Mekhilef, ‘‘New switched-
J. Rodriguez, ‘‘Voltage source multilevel inverters with reduced device capacitor based boost seven-level ANPC (7L-ANPC) boost inverter topol-
count: Topological review and novel comparative factors,’’ IEEE Trans. ogy,’’ in Proc. IEEE Energy Convers. Congr. Expo. (ECCE), Oct. 2020,
Power Electron., vol. 36, no. 3, pp. 2720–2747, Mar. 2021. pp. 1856–1860.
[6] S. K. Annam, R. K. Pongiannan, and N. Yadaiah, ‘‘A hysteresis space [30] A. Iqbal, M. D. Siddique, J. S. M. Ali, S. Mekhilef, and J. Lam, ‘‘A new
vector PWM for PV tied Z-source NPC-MLI with DC-link neutral point eight switch seven level boost active neutral point clamped (8S-7L-
balancing,’’ IEEE Access, vol. 9, pp. 54420–54434, 2021. BANPC) inverter,’’ IEEE Access, vol. 8, pp. 203972–203981, 2020.
[7] M. Malinowski, K. Gopakumar, J. Rodriguez, and M. A. Pérez, ‘‘A survey [31] Y. Ye, S. Chen, R. Sun, X. Wang, and Y. Yi, ‘‘Three-phase step-up multi-
on cascaded multilevel inverters,’’ IEEE Trans. Ind. Electron., vol. 57, level inverter with self-balanced switched-capacitor,’’ IEEE Trans. Power
no. 7, pp. 2197–2206, Jul. 2010. Electron., vol. 36, no. 7, pp. 7652–7664, Jul. 2021.
[8] C. I. Odeh, A. Lewicki, and M. Morawiec, ‘‘A single-carrier-based pulse- [32] Y. Ye, T. Hua, S. Chen, and X. Wang, ‘‘Neutral-point-clamped five-
width modulation template for cascaded H-bridge multilevel inverters,’’ level inverter with self-balanced switched-capacitor,’’ IEEE Trans. Ind.
IEEE Access, vol. 9, pp. 42182–42191, 2021. Electron., early access, Mar. 23, 2021, doi: 10.1109/TIE.2021.3066932.
[9] V. Guennegues, B. Gollentz, F. Meibody-Tabar, S. Rael, and L. Leclere, [33] M. K. Kazimierczuk, ‘‘Switching losses with linear MOSFET output
‘‘A converter topology for high speed motor drive applications,’’ in Proc. capacitance,’’ in Pulse-Width Modulated DC–DC Power Converters,
13th Eur. Conf. Power Electron. Appl. (EPE), Sep. 2009, pp. 1–8. 1st ed. West Sussex, U.K.: Wiley, 2008, ch. 2, pp. 37–38.
[10] H. Akagi, ‘‘Multilevel converters: Fundamental circuits and systems,’’ [34] Y. Ounejjar, K. Al-Haddad, and L.-A. Grégoire, ‘‘Packed U cells multilevel
Proc. IEEE, vol. 105, no. 11, pp. 2048–2065, Nov. 2017. converter topology: Theoretical study and experimental validation,’’ IEEE
[11] J. Zeng, W. Lin, D. Cen, and J. Liu, ‘‘Novel K-type multilevel inverter with Trans. Ind. Electron., vol. 58, no. 4, pp. 1294–1306, Apr. 2011.
reduced components and self-balance,’’ IEEE J. Emerg. Sel. Topics Power [35] H. Vahedi, M. Sharifzadeh, and K. Al-Haddad, ‘‘Modified seven-level pack
Electron., vol. 8, no. 4, pp. 4343–4354, Dec. 2020. U-cell inverter for photovoltaic applications,’’ IEEE J. Emerg. Sel. Topics
[12] Y. Zhang, Q. Wang, C. Hu, W. Shen, D. G. Holmes, and X. Yu, ‘‘A nine- Power Electron., vol. 6, no. 3, pp. 1508–1516, Sep. 2018.
level inverter for low-voltage applications,’’ IEEE Trans. Power Electron.,
vol. 35, no. 2, pp. 1659–1671, Feb. 2020.
[13] J. Li, J. Jiang, and S. Qiao, ‘‘A space vector pulse width modulation for five-
level nested neutral point piloted converter,’’ IEEE Trans. Power Electron., YUANMAO YE (Member, IEEE) received the
vol. 32, no. 8, pp. 5991–6004, Aug. 2017. B.Sc. degree in electrical engineering from the
[14] A. Bahrami and M. Narimani, ‘‘A new five-level T-type nested neutral
University of Jinan, Jinan, China, in 2007,
point clamped (T-NNPC) converter,’’ IEEE Trans. Power Electron., vol. 34,
the M.Sc. degree in control theory and control
no. 11, pp. 10534–10545, Nov. 2019.
engineering from the South China University of
[15] H. Yu, B. Chen, W. Yao, and Z. Lu, ‘‘Hybrid seven-level converter based on
T-type converter and H-bridge cascaded under SPWM and SVM,’’ IEEE
Technology, Guangzhou, China, in 2010, and the
Trans. Power Electron., vol. 33, no. 1, pp. 689–702, Jan. 2018. Ph.D. degree from The Hong Kong Polytechnic
[16] T. Abhilash, K. Annamalai, and S. V. Tirumala, ‘‘A seven-level VSI with a University, Hong Kong, in 2016. From Septem-
front-end cascaded three-level inverter and flying-capacitor-fed H-bridge,’’ ber 2010 to January 2014, he was with the Depart-
IEEE Trans. Ind. Appl., vol. 55, no. 6, pp. 6073–6088, Nov. 2019. ment of Electrical Engineering, The Hong Kong
[17] Y. P. Siwakoti, A. Mahajan, D. J. Rogers, and F. Blaabjerg, ‘‘A novel seven- Polytechnic University, as a Research Assistant. He is currently a Professor
level active neutral-point-clamped converter with reduced active switching with the School of Automation, Guangdong University of Technology. His
devices and DC-link voltage,’’ IEEE Trans. Power Electron., vol. 34, research interests include multilevel inverters, battery management systems,
no. 11, pp. 10492–10508, Nov. 2019. and switched-capacitor technique and its industrial applications.

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GUOXIN ZHANG was born in Shantou, China, SHIKAI CHEN was born in Shanwei, China,
in 1996. He received the B.Sc. degree from in 1996. He received the B.Sc. degree from
Guangdong Polytechnic Normal University, Guangdong Polytechnic Normal University,
Guangzhou, China, in 2019. He is currently Guangzhou, China, in 2018. He is currently
pursuing the M.Sc. degree with the School of pursuing the M.Sc. degree with the School of
Automation, Guangdong University of Technol- Automation, Guangdong University of Technol-
ogy, Guangzhou. ogy, Guangzhou.
His research interests include multilevel invert- His research interests include modular multi-
ers and switched-capacitor technique and its indus- level inverters and motor control.
trial applications.

XIAOLIN WANG received the B.Sc. degree in

electrical engineering and automation from Three
Gorges University, Yichang, China, in 2012,
JINLIANG HUANG was born in Shantou, China, and the M.Sc. and Ph.D. degrees from The
in 1997. He received the B.Sc. degree in electrical Hong Kong Polytechnic University, Hong Kong,
engineering and automation from the Dongguan in 2013 and 2018, respectively. She is cur-
University of Technology, Dongguan, China, rently an Assistant Professor with the School of
in 2020. He is currently pursuing the M.Sc. degree Automation, Guangdong University of Technol-
with the School of Automation, Guangdong Uni- ogy, Guangzhou, China.
versity of Technology, Guangzhou, China. Her research interests include battery manage-
His research interests include modular multi- ment systems, energy balancing systems, distribution system planning, and
level inverters and switched-capacitor power con- vehicle to grid (V2G).
version technique.

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