IT8726F

Environment Control Low Pin Count Input / Output (EC - LPC I/O)

Preliminary Specification V0.3

ITE TECH. INC.

Specification subject to Change without notice, AS IS and for reference only. For purchasing, please contact sales representatives. Please note that the IT8726F V0.3 is applicable to D version and future versions.

Copyright 2006 ITE Tech. Inc. This is Preliminary document release. All specifications are subject to change without notice. The material contained in this document supersedes all previous documentation issued for the related products included herein. Please contact ITE Tech. Inc. for the latest document(s). All sales are subject to ITEs Standard Terms and Conditions, a copy of which is included in the back of this document. ITE, IT8726F is a trademark of ITE Tech. Inc. All other trademarks are claimed by their respective owners. All specifications are subject to change without notice. Additional copies of this manual or other ITE literature may be obtained from: ITE Tech. Inc. Marketing Department 8F, No. 233-1, Bao Chiao RD., Hsin Tien, Taipei County 231, Taiwan, R.O.C. Phone: Fax: (02) 29126889 (02) 2910-2551, 2910-2552

If you have any marketing or sales questions, please contact: P.Y. Chang, at ITE Taiwan: E-mail: [email protected], Tel: 886-2-29126889 X6052, Fax: 886-2-29102551 To find out more about ITE, visit our World Wide Web at: http://www.ite.com.tw Or e-mail [email protected] for more product information/services

Revision History
Revision History
Section 4 8 8 Revision Section 4 Pin Configuration was revised. In section 8.11.4, Simple I/O Base Address LSB Register (Index=63h, Default=00h), bit 2-0 was revised to read only as 000b. For section 8.11.32, VID Input Register (Index=FCh, Default=--h), the description of bit 5-0 is revised. Page No. 7 61 66

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CONTENTS
1. Features ..................................................................................................................................................... 1 2. General Description ....................................................................................................................................... 3 3. Block Diagram................................................................................................................................................ 5 4. Pin Configuration ........................................................................................................................................... 7 5. IT8726F Pin Descriptions .............................................................................................................................. 9 6. List of GPIO Pins ......................................................................................................................................... 25 7. Power On Strapping Options and Special Pin Routings ............................................................................. 29 8. Configuration .............................................................................................................................................. 31 8.1 Configuring Sequence Description ................................................................................................... 31 8.2 Description of the Configuration Registers ....................................................................................... 33 8.2.1 Logical Device Base Address .............................................................................................. 38 8.3 Global Configuration Registers (LDN: All) ........................................................................................ 39 8.3.1 Configure Control (Index=02h)............................................................................................. 39 8.3.2 Logical Device Number (LDN, Index=07h) .......................................................................... 39 8.3.3 Chip ID Byte 1 (Index=20h, Default=87h) ............................................................................ 39 8.3.4 Chip ID Byte 2 (Index=21h, Default=16h) ............................................................................ 39 8.3.5 Configuration Select and Chip Version (Index=22h, Default=01h) ...................................... 39 8.3.6 Clock Selection Register (Index=23h, Default=00h) ............................................................ 39 8.3.7 Software Suspend and Flash I/F Control Register (Index=24h, Default=0000s0s0b, MB PnP)...................................................................................................................................... 40 8.3.8 GPIO Set 1 Multi-Function Pin Selection Register (Index=25h, Default=01h) .................... 41 8.3.9 PIO Set 2 Multi-Function Pin Selection Register (Index=26h, Default=00h) ....................... 41 8.3.10 GPIO Set 3 Multi-Function Pin Selection Register (Index=27h, Default=00h) .................... 42 8.3.11 GPIO Set 4 Multi-Function Pin Selection Register (Index=28h, Default=40h) .................... 43 8.3.12 GPIO Set 5 Multi-Function Pin Selection Register (Index=29h, Default=00h) .................... 43 8.3.13 Extended 1 Multi-Function Pin Selection Register (Index=2Ah, Default=00h) .................... 44 8.3.14 Logical Block Lock Register (Index=2Bh, Default=00h) ...................................................... 45 8.3.15 Extended 2 Multi-Function Pin Selection Register (Index=2Ch, Default=1Fh).................... 45 8.3.16 Test 1 Register (Index=2Eh, Default=00h) .......................................................................... 46 8.3.17 Test 2 Register (Index=2Fh, Default=00h)........................................................................... 46 8.4 FDC Configuration Registers (LDN=00h) ......................................................................................... 47 8.4.1 FDC Activate (Index=30h, Default=00h) .............................................................................. 47 8.4.2 FDC Base Address MSB Register (Index=60h, Default=03h) ............................................. 47 8.4.3 FDC Base Address LSB Register (Index=61h, Default=F0h).............................................. 47 8.4.4 FDC Interrupt Level Select (Index=70h, Default=06h)......................................................... 47 8.4.5 FDC DMA Channel Select (Index=74h, Default=02h) ......................................................... 47 8.4.6 FDC Special Configuration Register 1 (Index=F0h, Default=00h)....................................... 47 8.4.7 FDC Special Configuration Register 2 (Index=F1h, Default=00h)....................................... 48 8.5 Serial Port 1 Configuration Registers (LDN=01h) ............................................................................ 49 8.5.1 Serial Port 1 Activate (Index=30h, Default=00h).................................................................. 49 8.5.2 Serial Port 1 Base Address MSB Register (Index=60h, Default=03h) .................................. 49 8.5.3 Serial Port 1 Base Address LSB Register (Index=61h, Default=F8h)................................... 49 8.5.4 Serial Port 1 Interrupt Level Select (Index=70h, Default=04h) ............................................ 49 8.5.5 Serial Port 1 Special Configuration Register 1 (Index=F0h, Default=00h) .......................... 49 8.5.6 Serial Port 1 Special Configuration Register 2 (Index=F1h, Default=50h) .......................... 50 8.5.7 Serial Port 1 Special Configuration Register 3 (Index=F2h, Default=00h) .......................... 50 8.5.8 Serial Port 1 Special Configuration Register 4 (Index=F3h, Default=7Fh) .......................... 50

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8.6 Serial Port 2 Configuration Registers (LDN=02h) ............................................................................ 51 8.6.1 Serial Port 2 Activate (Index=30h, Default=00h).................................................................. 51 8.6.2 Serial Port 2 Base Address MSB Register (Index=60h, Default=02h) .................................. 51 8.6.3 Serial Port 2 Base Address LSB Register (Index=61h, Default=F8h)................................... 51 8.6.4 Serial Port 2 Interrupt Level Select (Index=70h, Default=03h) ............................................ 51 8.6.5 Serial Port 2 Special Configuration Register 1 (Index=F0h, Default=00h) .......................... 51 8.6.6 Serial Port 2 Special Configuration Register 2 (Index=F1h, Default=50h) .......................... 52 8.6.7 Serial Port 2 Special Configuration Register 3 (Index=F2h, Default=00h) .......................... 52 8.6.8 Serial Port 2 Special Configuration Register 4 (Index=F3h, Default=7Fh) .......................... 52 8.7 Parallel Port Configuration Registers (LDN=03h)............................................................................. 53 8.7.1 Parallel Port Activate (Index=30h, Default=00h).................................................................. 53 8.7.2 Parallel Port Primary Base Address MSB Register (Index=60h, Default=03h)..................... 53 8.7.3 Parallel Port Primary Base Address LSB Register (Index=61h, Default=78h) .................... 53 8.7.4 Parallel Port Secondary Base Address MSB Register (Index=62h, Default=07h)................ 53 8.7.5 Parallel Port Secondary Base Address LSB Register (Index=63h, Default=78h) ............... 53 8.7.6 Parallel Port Interrupt Level Select (Index =70h, Default=07h) ........................................... 53 8.7.7 Parallel Port DMA Channel Select (Index=74h, Default=03h) ............................................. 53 8.7.8 Parallel Port Special Configuration Register (Index=F0h, Default=03h) ............................. 54 8.8 Environment Controller Configuration Registers (LDN=04h) ........................................................... 55 8.8.1 Environment Controller Activate Register (Index=30h, Default=00h) .................................. 55 8.8.2 Environment Controller Base Address MSB Register (Index=60h, Default=02h) ................. 55 8.8.3 Environment Controller Base Address LSB Register (Index=61h, Default=90h) .................. 55 8.8.4 PME Direct Access Base Address MSB Register (Index=62h, Default=02h) ....................... 55 8.8.5 PME Direct Access Base Address LSB Register (Index=63h, Default=30h) ........................ 55 8.8.6 Environment Controller Interrupt Level Select (Index=70h, Default=09h) ........................... 55 8.8.7 APC/PME Event Enable Register (PER) (Index=F0h, Default=00h) ................................... 55 8.8.8 APC/PME Status Register (PSR) (Index=F1h, Default=00h) .............................................. 56 8.8.9 APC/PME Control Register 1 (PCR 1) (Index=F2h, Default=00h)....................................... 56 8.8.10 Environment Controller Special Configuration Register (Index=F3h, Default=00h) ............ 57 8.8.11 APC/PME Control Register 2 (PCR 2) (Index=F4h, Default=00h)....................................... 57 8.8.12 APC/PME Special Code Index Register (Index=F5h).......................................................... 57 8.8.13 APC/PME Special Code Data Register (Index=F6h)........................................................... 57 8.9 KBC (keyboard) Configuration Registers (LDN=05h)....................................................................... 58 8.9.1 KBC (keyboard) Activate (Index=30h, Default=01h)............................................................ 58 8.9.2 KBC (keyboard) Data Base Address MSB Register (Index=60h, Default=00h) .................. 58 8.9.3 KBC (keyboard) Data Base Address LSB Register (Index=61h, Default=60h) ................... 58 8.9.4 KBC (keyboard) Command Base Address MSB Register (Index=62h, Default=00h)......... 58 8.9.5 KBC (keyboard) Command Base Address LSB Register (Index=63h, Default=64h).......... 58 8.9.6 KBC (keyboard) Interrupt Level Select (Index=70h, Default=01h) ...................................... 58 8.9.7 KBC (keyboard) Interrupt Type (Index=71h, Default=02h) .................................................. 58 8.9.8 KBC (keyboard) Special Configuration Register (Index=F0h, Default=08h) ............................ 59 8.10 KBC (mouse) Configuration Registers (LDN=06h)........................................................................... 60 8.10.1 KBC (mouse) Activate (Index=30h, Default=00h)................................................................ 60 8.10.2 KBC (mouse) Interrupt Level Select (Index=70h, Default=0Ch) ............................................. 60 8.10.3 KBC (mouse) Interrupt Type (Index=71h, Default=02h) ...................................................... 60 8.10.4 KBC (mouse) Special Configuration Register (Index=F0h, Default=00h) ........................... 60 8.11 GPIO Configuration Registers (LDN=07h) ....................................................................................... 61 8.11.1 SMI# Normal Run Access Base Address MSB Register (Index=60h, Default=00h)........... 61 8.11.2 SMI# Normal Run Access Base Address LSB Register (Index=61h, Default=00h)............ 61 8.11.3 Simple I/O Base Address MSB Register (Index=62h, Default=00h).................................... 61 8.11.4 Simple I/O Base Address LSB Register (Index=63h, Default=00h)..................................... 61 8.11.5 Serial Flash I/F Base Address MSB Register (Index=64h, Default=00h) ............................ 61

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8.11.6 Serial Flash I/F Base Address LSB Register (Index=65h, Default=00h) ............................. 61 8.11.7 Panel Button De-bounce Interrupt Level Select Register (Index=70h, Default=00h) .......... 61 8.11.8 Watch Dog Timer Control Register (Index=71h, Default=00h) ............................................ 62 8.11.9 Watch Dog Timer Configuration Register (Index=72h, Default=001s0000h) ...................... 62 8.11.10 Watch Dog Timer Time-Out Value (LSB) Register (Index=73h, Default=38h) .................... 62 8.11.11 Watch Dog Timer Time-Out Value (MSB) Register (Index=74h, Default=00h) ................... 62 8.11.12 GPIO Pin Set 1, 2, 3, 4, 5 and 6 Polarity Registers (Index=B0h, B1h, B2h, B3h, B4h and B5h, Default=00h) ................................................................................................................ 62 8.11.13 GPIO Pin Set 1, 2, 3, 4, 5 and 6 Pin Internal Pull-up Enable Registers (Index=B8h, B9h, BAh, BBh, BCh and BDh, Default=00h)............................................................................... 63 8.11.14 Simple I/O Set 1, 2, 3, 4 and 5 Enable Registers (Index=C0h, C1h, C2h, C3h and C4h, Default=01h, 00h, 00h, 40h, and 00h) ................................................................................. 63 8.11.15 Simple I/O Set 1, 2, 3, 4 and 5 Output Enable Registers (Index=C8h, C9h, CAh, CBh and CCh, Default=01h, 00h, 00h, 40h, and 00h) ........................................................................ 63 8.11.16 Panel Button De-bounce 0 Input Pin Mapping Registers (Index=E0h, Default=00h) .......... 63 8.11.17 Panel Button De-bounce 1 Input Pin Mapping Registers (Index=E1h, Default=00h) .......... 63 8.11.18 IRQ External Routing 1-0 Input Pin Mapping Registers (Index=E3h-E2h, Default=00h) .... 63 8.11.19 IRQ External Routing 1-0 Interrupt Level Selection Register (Index=E4h, Default=00h).... 64 8.11.20 SMI# Control Register 1 (Index=F0h, Default=00h)............................................................. 64 8.11.21 SMI# Control Register 2 (Index=F1h, Default=00h)............................................................. 64 8.11.22 SMI# Status Register 1 (Index=F2h, Default=00h) .............................................................. 64 8.11.23 SMI# Status Register 2 (Index=F3h, Default=00h) .............................................................. 65 8.11.24 SMI# Pin Mapping Register (Index=F4h, Default=00h) ....................................................... 65 8.11.25 Hardware Monitor Thermal Output Pin Mapping Register (Index=F5h, Default=00h) ........ 65 8.11.26 Hardware Monitor Alert Beep Pin Mapping Register (Index=F6h, Default=00h)................. 65 8.11.27 Keyboard Lock Pin Mapping Register (Index=F7h, Default=00h) ....................................... 65 8.11.28 GP LED Blinking 1 Pin Mapping Register (Index=F8h, Default=00h).................................. 65 8.11.29 GP LED Blinking 1 Control Register (Index=F9h, Default=00h) .......................................... 66 8.11.30 GP LED Blinking 2 Pin Mapping Register (Index=FAh, Default=00h) .................................. 66 8.11.31 GP LED Blinking 2 Control Register (Index=FBh, Default=00h).......................................... 66 8.11.32 VID Input Register (Index=FCh, Default=--h)....................................................................... 66 8.11.33 VID Output Register (Index=FDh, Default=00h) .................................................................. 66 8.12 MIDI Port Configuration Registers (LDN=08h) ................................................................................. 67 8.12.1 MIDI Port Activate (Index=30h, Default=00h) ...................................................................... 67 8.12.2 MIDI Port Base Address MSB Register (Index=60h, Default=03h)....................................... 67 8.12.3 MIDI Port Base Address LSB Register (Index=61h, Default=00h)........................................ 67 8.12.4 MIDI Port Interrupt Level Select (Index=70h, Default=0Ah) ................................................ 67 8.12.5 MIDI Port Special Configuration Register (Index=F0h, Default=00h) .................................. 67 8.13 Game Port Configuration Registers (LDN=09h) ............................................................................... 68 8.13.1 Game Port Activate (Index=30h, Default=00h) .................................................................... 68 8.13.2 Game Port Base Address MSB Register (Index=60h, Default=02h) .................................... 68 8.13.3 Game Port Base Address LSB Register (Index=61h, Default=01h) ..................................... 68 8.14 Consumer IR Configuration Registers (LDN=0Ah)........................................................................... 69 8.14.1 Consumer IR Activate (Index=30h, Default=00h) ................................................................ 69 8.14.2 Consumer IR Base Address MSB Register (Index=60h, Default=03h)................................. 69 8.14.3 Consumer IR Base Address LSB Register (Index=61h, Default=10h).................................. 69 8.14.4 Consumer IR Interrupt Level Select (Index=70h, Default=0Bh) .......................................... 69 8.14.5 Consumer IR Special Configuration Register (Index=F0h, Default=00h)............................ 69 9. Functional Description ................................................................................................................................. 71 9.1 LPC Interface .................................................................................................................................... 71 9.1.1 LPC Transactions................................................................................................................. 71 9.1.2 LDRQ# Encoding ................................................................................................................. 71

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9.2 Serialized IRQ ................................................................................................................................... 71 9.2.1 Continuous Mode ................................................................................................................. 71 9.2.2 Quiet Mode ........................................................................................................................... 72 9.2.3 Waveform Samples of SERIRQ Sequence.......................................................................... 72 9.2.4 SERIRQ Sampling Slot ........................................................................................................ 73 General Purpose I/O ......................................................................................................................... 74 Advanced Power Supply Control and Power Management Event (PME#) ...................................... 76 SPI Serial Flash Controller................................................................................................................ 77 9.5.1 Overview............................................................................................................................... 77 9.5.2 Features ............................................................................................................................... 77 9.5.3 Register Descriptions ........................................................................................................... 77 9.5.3.1 Control Register (SPI_CTRL) .................................................................................. 77 9.5.3.2 Command Register (SPI_CMD) .............................................................................. 78 9.5.3.3 Address 0 Register (SPI_ADDR0) .......................................................................... 78 9.5.3.4 Address 1 Register (SPI_ADDR1) .......................................................................... 78 9.5.3.5 Address 2 Register (SPI_ADDR2) .......................................................................... 78 9.5.3.6 Input Data 0 Register (SPI_IDATA0)....................................................................... 78 9.5.3.7 Input Data 1 Register (SPI_IDATA1)....................................................................... 79 9.5.3.8 Output Data/Input Data 2 Register (SPI_ODATA/ SPI_IDATA2)............................ 79 9.5.4 Function Descriptions........................................................................................................... 79 Environment Controller ..................................................................................................................... 80 9.6.1 Interfaces.............................................................................................................................. 81 9.6.2 Registers .............................................................................................................................. 81 9.6.2.1 Address Port (Base+05h, Default=00h): ................................................................. 81 9.6.2.2 Register Description ................................................................................................ 85 9.6.2.2.1 Configuration Register (Index=00h, Default=18h) ........................... 85 9.6.2.2.2 Interrupt Status Register 1 (Index=01h, Default=00h)..................... 86 9.6.2.2.3 Interrupt Status Register 2 (Index=02h, Default=00h)..................... 86 9.6.2.2.4 Interrupt Status Register 3 (Index=03h, Default=00h)..................... 86 9.6.2.2.5 SMI# Mask Register 1 (Index=04h, Default=00h) ........................... 86 9.6.2.2.6 SMI# Mask Register 2 (Index=05h, Default=00h) ........................... 86 9.6.2.2.7 SMI# Mask Register 3 (Index=06h, Default=00h) ........................... 86 9.6.2.2.8 Interrupt Mask Register 1 (Index=07h, Default=00h) ...................... 87 9.6.2.2.9 Interrupt Mask Register 2 (Index=08h, Default=00h) ...................... 87 9.6.2.2.10 Interrupt Mask Register 3 (Index=09h, Default=80h) ...................... 87 9.6.2.2.11 VID Register (Index=0Ah) ................................................................ 87 9.6.2.2.12 Fan PWM Smoothing Step Frequency Selection Register (Index=0Bh, Default=09h) ......................................................................................... 87 9.6.2.2.13 Fan Tachometer 16-bit Counter Enable Register (Index=0Ch, Default=00h) ..................................................................................................... 88 9.6.2.2.14 Fan Tachometer 1-3 Reading Registers (Index=0Dh-0Fh) ............. 88 9.6.2.2.15 Fan Tachometer 1-3 Limit Registers (Index=10h-12h).................... 88 9.6.2.2.16 Fan Controller Main Control Register (Index=13h, Default=07h) .... 89 9.6.2.2.17 FAN_CTL Control Register (Index=14h, Default=50h) ( for FAN1, 3, 4, 5) ..................................................................................................... 89 9.6.2.2.18 FAN_CTL1 PWM Control Register (Index=15h, Default=00h/20h/40h/60h) ..................................................................................... 89 9.6.2.2.19 FAN_CTL2 PWM Control Register (Index=16h, Default=00h/20h/40h/60h) ..................................................................................... 90 9.6.2.2.20 FAN_CTL3 PWM Control Register (Index=17h, Default=00h/20h/40h/60h) ..................................................................................... 90

9.3 9.4 9.5

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9.6.2.2.21 Fan Tachometer 1-3 Extended Reading Registers (Index=18h-1Ah) . ..................................................................................................... 90 9.6.2.2.22 Fan Tachometer 1-3 Extended Limit Registers (Index=1Bh-1Dh) .. 90 9.6.2.2.23 VIN7-VIN0 Voltage Reading Registers (Index=27h-20h) ................ 90 9.6.2.2.24 VBAT Voltage Reading Register (Index=28h) ................................. 91 9.6.2.2.25 TMPIN3-1 Temperature Reading Registers (Index=2Bh-29h) ........ 91 9.6.2.2.26 VIN7-0 Low Limit Registers (Index=3Fh, 3Dh, 3Bh, 39h, 37h, 35h, 33h, 31h) ..................................................................................................... 91 9.6.2.2.27 TMPIN3-1 High Limit Registers (Index=44h, 42h, 40h)................... 91 9.6.2.2.28 TMPIN3-1 Low Limit Registers (Index=45h, 43h, 41h).................... 91 9.6.2.2.29 ADC Voltage Channel Enable Register (Index=50h, Default=00h). 91 9.6.2.2.30 ADC Temperature Channel Enable Register (Index=51h, Default=00h) ..................................................................................................... 91 9.6.2.2.31 TMPIN3-1 Thermal Output Limit Registers (Index=54h-52h, Default=7Fh) ..................................................................................................... 92 9.6.2.2.32 ADC Temperature Extra Channel Enable Register (Index=55h, Default=00h) ..................................................................................................... 92 9.6.2.2.33 Thermal Diode Zero Degree Adjust 1 Register (Index=56h, Default=00h) ..................................................................................................... 92 9.6.2.2.34 Thermal Diode Zero Degree Adjust 2 Register (Index=57h, Default=00h) ..................................................................................................... 92 9.6.2.2.35 Vendor ID Register (Index=58h, Default=90h) ................................ 92 9.6.2.2.36 Thermal Diode Zero Degree Adjust 3 Register (Index=59h, Default=00h) ..................................................................................................... 92 9.6.2.2.37 Code ID Register (Index=5Bh, Default=12h) ................................... 93 9.6.2.2.38 Beep Event Enable Register (Index=5Ch, Default=00h) ................. 93 9.6.2.2.39 Beep Frequency Divisor of Fan Event Register (Index=5Dh, Default=00h) ..................................................................................................... 93 9.6.2.2.40 Beep Frequency Divisor of Voltage Event Register (Index=5Eh, Default=00h) ..................................................................................................... 93 9.6.2.2.41 Beep Frequency Divisor of Temperature Event Register (Index=5Fh, Default=00h) ..................................................................................................... 93 9.6.2.2.42 FAN_CTL3-1 SmartGuardian Automatic Mode Temperature Limit of OFF Registers (Index=70h, 68h, 60h, Default=7Fh) ............................................. 93 9.6.2.2.43 FAN_CTL3-1 SmartGuardian Automatic Mode Temperature Limit of Fan Start Registers (Index=71h, 69h, 61h, Default=7Fh) ..................................... 93 9.6.2.2.44 FAN_CTL3-1 SmartGuardian Automatic Mode Start PWM Registers (Index=73h, 6Bh, 63h, Default=00h) ..................................................................... 94 9.6.2.2.45 FAN_CTL3-1 SmartGuardian Automatic Mode Control Registers (Index=74h, 6Ch, 64h, Default=00h) ..................................................................... 94 9.6.2.2.46 FAN_CTL3-1 SmartGuardian Automatic Mode -Temperature Registers (Index=75h, 6Dh, 65h, Default=7Fh).................................................. 94 9.6.2.2.47 Fan Tachometer 4-5 Reading LSB Registers (Index=80h,82h) ...... 94 9.6.2.2.48 Fan Tachometer 4-5 Reading MSB Registers (Index=81h,83h) ..... 94 9.6.2.2.49 Fan Tachometer 4-5 Limit LSB Registers (Index=84h,86h) ............ 95 9.6.2.2.50 Fan Tachometer 4-5 Limit MSB Registers (Index=85h,87h) ........... 95 9.6.2.2.51 FAN_CTL4 PWM Control Register (Index=88h, Default=00h) ........ 95 9.6.2.2.52 FAN_CTL5 PWM Control Register (Index=89h, Default=00h) ........ 95 9.6.2.2.53 External Temperature Sensor Host Status Register (Index=8Bh, Default=---00000b) ................................................................................................ 96 9.6.2.2.54 External Temperature Sensor Host Control Register (Index=8Ch, Default=02h) ..................................................................................................... 96

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9.6.2.2.55 External Temperature Sensor Host Command Register (Index=8Dh, Default=00h) ..................................................................................................... 97 9.6.2.2.56 External Temperature Sensor Transmit Slave Address Register (Index=8Eh, Default=99h) ..................................................................................... 97 9.6.2.2.57 External Temperature Sensor Host Data Register (Index=8Fh, Default=99h) ..................................................................................................... 97 9.6.2.2.58 FAN_CTL5-4 SmartGuardian Automatic Mode Temperature Limit of OFF Registers (Index=98h, 90h, Default=7Fh) ..................................................... 98 9.6.2.2.59 FAN_CTL5-4 SmartGuardian Automatic Mode Temperature Limit of Fan Start Registers (Index=99h, 91h, Default=7Fh) ............................................ 98 9.6.2.2.60 FAN_CTL5-4 SmartGuardian Automatic Mode Start PWM Registers (Index=9Bh, 93h, Default=00h) ............................................................................. 98 9.6.2.2.61 FAN_CTL5-4 SmartGuardian Automatic Mode Control Registers (Index=9Ch, 94h, Default=00h) ............................................................................. 98 9.6.2.2.62 FAN_CTL5-4 SmartGuardian Automatic Mode -Temperature Registers (Index=9Dh, 95h, Default=7Fh)............................................................. 98 9.6.3 Operation.............................................................................................................................. 99 9.6.3.1 Power On RESET and Software RESET ................................................................ 99 9.6.3.2 Starting Conversion ................................................................................................. 99 9.6.3.3 Voltage and Temperature Inputs ........................................................................... 100 9.6.3.4 Layout and Grounding ........................................................................................... 100 9.6.3.5 Fan Tachometer .................................................................................................... 101 9.6.3.6 Interrupt of the EC ................................................................................................. 101 9.6.3.7 FAN Controller FAN_CTLs ON-OFF and SmartGuardian Modes........................ 102 Floppy Disk Controller (FDC).......................................................................................................... 104 9.7.1 Introduction......................................................................................................................... 104 9.7.2 Reset .................................................................................................................................. 104 9.7.3 Hardware Reset (LRESET# Pin)........................................................................................ 104 9.7.4 Software Reset (DOR Reset and DSR Reset)................................................................... 104 9.7.5 Digital Data Separator ........................................................................................................ 104 9.7.6 Write Precompensation ...................................................................................................... 104 9.7.7 Data Rate Selection ........................................................................................................... 104 9.7.8 Status, Data and Control Registers.................................................................................... 105 9.7.8.1 Digital Output Register (DOR, FDC Base Address + 02h).................................... 105 9.7.8.2 Tape Drive Register (TDR, FDC Base Address + 03h) ........................................ 105 9.7.8.3 Main Status Register (MSR, FDC Base Address + 04h) ...................................... 105 9.7.8.4 Data Rate Select Register (DSR, FDC Base Address + 04h)............................... 106 9.7.8.5 Data Register (FIFO, FDC Base Address + 05h).................................................. 108 9.7.8.6 Digital Input Register (DIR, FDC Base Address + 07h) ........................................ 108 9.7.8.7 Diskette Control Register (DCR, FDC Base Address + 07h) ................................ 108 9.7.9 Controller Phases............................................................................................................... 108 9.7.9.1 Command Phase ................................................................................................... 108 9.7.9.2 Execution Phase.................................................................................................... 109 9.7.9.3 Result Phase ......................................................................................................... 109 9.7.9.4 Result Phase Status Registers.............................................................................. 109 9.7.10 Command Set .................................................................................................................... 111 9.7.11 Data Transfer Commands.................................................................................................. 121 9.7.11.1 Read Data.............................................................................................................. 121 9.7.11.2 Read Deleted Data ................................................................................................ 122 9.7.11.3 Read a Track ......................................................................................................... 122 9.7.11.4 Write Data.............................................................................................................. 122 9.7.11.5 Write Deleted Data ................................................................................................ 123

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9.7.11.6 Format A Track ...................................................................................................... 123 9.7.11.7 SCAN..................................................................................................................... 123 9.7.11.8 VERIFY.................................................................................................................. 124 9.7.12 Control Commands ............................................................................................................ 124 9.7.12.1 READ ID ................................................................................................................ 124 9.7.12.2 Configure ............................................................................................................... 125 9.7.12.3 RE-CALIBRATE..................................................................................................... 125 9.7.12.4 SEEK ..................................................................................................................... 125 9.7.12.5 RELATIVE SEEK................................................................................................... 126 9.7.12.6 DUMPREG ............................................................................................................ 126 9.7.12.7 LOCK ..................................................................................................................... 126 9.7.12.8 VERSION............................................................................................................... 126 9.7.12.9 SENSE INTERRUPT STATUS.............................................................................. 126 9.7.12.10 SENSE DRIVE STATUS ....................................................................................... 126 9.7.12.11 SPECIFY ............................................................................................................... 126 9.7.12.12 PERPENDICULAR MODE .................................................................................... 127 9.7.12.13 INVALID................................................................................................................. 128 9.7.13 DMA Transfers ................................................................................................................... 128 9.7.14 Low Power Mode................................................................................................................ 128 9.8 Serial Port (UART) Description....................................................................................................... 129 9.8.1 Data Registers.................................................................................................................... 129 9.8.2 Control Registers: IER, IIR, FCR, DLL, DLM, LCR and MCR ........................................... 129 9.8.3 Status Registers: LSR and MSR........................................................................................ 135 9.8.4 Reset .................................................................................................................................. 137 9.8.5 Programming...................................................................................................................... 137 9.8.6 Software Reset................................................................................................................... 137 9.8.7 Clock Input Operation......................................................................................................... 137 9.8.8 FIFO Interrupt Mode Operation.......................................................................................... 138 9.9 Smart Card Reader......................................................................................................................... 140 9.9.1 Features ............................................................................................................................. 140 9.9.2 Operation............................................................................................................................ 140 9.9.3 Connection of IFD to ICC Socket ....................................................................................... 140 9.9.4 Baud Rate Relationship Between UART and Smart Card Interface.................................. 141 9.9.5 Waveform Relationship ...................................................................................................... 141 9.9.6 Clock Divider ...................................................................................................................... 141 9.9.7 Waveform Example of Activation/Deactivation Sequence ................................................. 142 9.9.8 ATR and PTS Structure...................................................................................................... 142 9.9.9 Smart Card Operating Sequence Example........................................................................ 143 9.10 Parallel Port..................................................................................................................................... 144 9.10.1 SPP and EPP Modes ......................................................................................................... 144 9.10.2 EPP Mode Operation ......................................................................................................... 146 9.10.3 ECP Mode Operation ......................................................................................................... 147 9.11 Keyboard Controller (KBC) ............................................................................................................. 153 9.11.1 Host Interface ..................................................................................................................... 153 9.11.2 Data Registers and Status Register................................................................................... 154 9.11.3 Keyboard and Mouse Interface .......................................................................................... 154 9.11.4 KIRQ and MIRQ ................................................................................................................. 154 9.12 Consumer Remote Control (TV Remote) IR (CIR) ......................................................................... 155 9.12.1 Overview............................................................................................................................. 155 9.12.2 Features ............................................................................................................................. 155 9.12.3 Block Diagram .................................................................................................................... 155 9.12.4 Transmit Operation............................................................................................................. 156

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IT8726F
9.12.5 Receive Operation.............................................................................................................. 156 9.12.6 Register Descriptions and Address.................................................................................... 156 9.12.6.1 CIR Data Register (DR)......................................................................................... 157 9.12.6.2 CIR Interrupt Enable Register (IER)...................................................................... 157 9.12.6.3 CIR Receiver Control Register (RCR)................................................................... 158 9.12.6.4 CIR Transmitter Control Register 1 (TCR1) .......................................................... 159 9.12.6.5 CIR Transmitter Control Register (TCR2) ............................................................. 160 9.12.6.6 CIR Baud Rate Divisor Low Byte Register (BDLR)............................................... 163 9.12.6.7 CIR Baud Rate Divisor High Byte Register (BDHR) ............................................. 163 9.12.6.8 CIR Transmitter Status Register (TSR)................................................................. 163 9.12.6.9 CIR Receiver FIFO Status Register (RSR) ........................................................... 164 9.12.6.10 CIR Interrupt Identification Register (IIR) .............................................................. 164 9.13 Game Port Interface........................................................................................................................ 165 9.13.1 Game Port (Base+0h) ........................................................................................................ 165 9.14 MIDI Interface.................................................................................................................................. 165 9.14.1 MPU-401 Register Interface............................................................................................... 165 9.14.2 Operation............................................................................................................................ 166 10. DC Electrical Characteristics ..................................................................................................................... 169 11. AC Characteristics (VCC = 5V 5%, Ta = 0C to + 70C) ....................................................................... 173 11.1 Clock Input Timings ........................................................................................................................ 173 11.2 LCLK (PCICLK) and LRESET Timings........................................................................................... 173 11.3 LPC and SERIRQ Timings.............................................................................................................. 174 11.4 Serial Port, ASKIR, SIR and Consumer Remote Control Timings ................................................. 175 11.5 Modem Control Timings.................................................................................................................. 175 11.6 Floppy Disk Drive Timings .............................................................................................................. 176 11.7 EPP Address or Data Write Cycle Timings..................................................................................... 177 11.8 EPP Address or Data Read Cycle Timings .................................................................................... 178 11.9 ECP Parallel Port Forward Timings ................................................................................................ 178 11.10 ECP Parallel Port Backward Timings ............................................................................................ 179 11.11 RSMRST#, PWROK1/2, and ACPI Power Control Signals Timings ............................................. 179 11.12 AMD CPU Power Sequence Signals Timings ............................................................................... 180 12. Package Information .................................................................................................................................. 181 13. Ordering Information .................................................................................................................................. 183 14. Top Marking Information............................................................................................................................ 185

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Contents

FIGURES
Figure 7-1. IT8726F Special Applications Circuitry for Intel ICH ...................................................................... 30 Figure 9-1. Start Frame Timing ......................................................................................................................... 72 Figure 9-2. Stop Frame Timing ......................................................................................................................... 72 Figure 9-3. General Logic of GPIO Function .................................................................................................... 75 Figure 9-4. Application Example. Resistor should provide approximately 2V at the Analog Inputs. ................ 99 Figure 9-5. Temperature Interrupt Response Diagram................................................................................... 102 Figure 9-6. SmartGuardian Automatic Mode .................................................................................................. 103 Figure 9-7. Smart Card Reader Application.................................................................................................... 140 Figure 9-8. 9600 Baud Rate Example............................................................................................................. 141 Figure 9-9. Waveform Example of IFD............................................................................................................ 142 Figure 9-10. Keyboard and Mouse Interface .................................................................................................. 153 Figure 9-11. CIR Block Diagram ..................................................................................................................... 155 Figure 11-1. Clock Input Timings .................................................................................................................... 173 Figure 11-2. LCLK (PCICLK) and LRESET Timings....................................................................................... 173 Figure 11-3. LPC and SERIRQ Timings ......................................................................................................... 174 Figure 11-4. Serial Port, ASKIR, SIR and Consumer Remote Control Timings ............................................. 175 Figure 11-5. Modem Control Timings ............................................................................................................. 175 Figure 11-6. Floppy Disk Drive Timings.......................................................................................................... 176 Figure 11-7. EPP Address or Data Write Cycle Timings ................................................................................ 177 Figure 11-8. EPP Address or Data Read Cycle Timings ................................................................................ 178 Figure 11-9. ECP Parallel Port Forward Timings............................................................................................ 178 Figure 11-10. ECP Parallel Port Backward Timings ....................................................................................... 179

TABLES
Table 4-1. Pins Listed in Numeric Order............................................................................................................. 8 Table 5-1. Pin Description of Supplies Signals ................................................................................................... 9 Table 5-2. Pin Description of LPC Bus Interface Signals ................................................................................... 9 Table 5-3. Pin Description of MIDI Interface Signals ........................................................................................ 10 Table 5-4. Pin Description of Game Port Signals ............................................................................................. 10 Table 5-5. Pin Description of Hardware Monitor SignalsNote1 ............................................................................ 12 Table 5-6. Pin Description of Fan Controller Signals ........................................................................................ 14 Table 5-7. Pin Description of Infrared Port Signals........................................................................................... 14 Table 5-8. Pin Description of Serial Port 1 Signals ........................................................................................... 15 Table 5-9. Pin Description of Serial Port 2 Signals ........................................................................................... 16 Table 5-10. Pin Description of Parallel Port Signals ......................................................................................... 18 Table 5-11. Pin Description of Floppy Disk Controller Signals ......................................................................... 18 Table 5-12. Pin Description of Smart Card Reader Interface Signals .............................................................. 19

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IT8726F
Table 5-13. Pin Description of Keyboard Controller Signals............................................................................. 20 Table 5-14. Pin Description of Miscellaneous Signals...................................................................................... 21 Table 6-1. General Purpose I/O Group 1 (Set 1) .............................................................................................. 25 Table 6-2. General Purpose I/O Group 2 (Set 2) .............................................................................................. 25 Table 6-3. General Purpose I/O Group 3 (Set 3) .............................................................................................. 26 Table 6-4. General Purpose I/O Group 4 (Set 4) .............................................................................................. 26 Table 6-5. General Purpose I/O Group 5 (Set 5) .............................................................................................. 26 Table 6-6. General Purpose I/O Group 6 (Set 6) .............................................................................................. 27 Table 7-1. Power On Strapping Options ........................................................................................................... 29 Table 8-1. Global Configuration Registers........................................................................................................ 33 Table 8-2. FDC Configuration Registers........................................................................................................... 33 Table 8-3. Serial Port 1 Configuration Registers .............................................................................................. 34 Table 8-4. Serial Port 2 Configuration Registers .............................................................................................. 34 Table 8-5. Parallel Port Configuration Registers............................................................................................... 34 Table 8-6. Environment Controller Configuration Registers ............................................................................. 35 Table 8-7. KBC(Keyboard) Configuration Registers......................................................................................... 35 Table 8-8. KBC(Mouse) Configuration Registers ............................................................................................. 35 Table 8-9. GPIO Configuration Registers ......................................................................................................... 36 Table 8-10. MIDI Port Configuration Registers ................................................................................................. 37 Table 8-11. Game Port Configuration Registers............................................................................................... 37 Table 8-12. Consumer IR Configuration Registers........................................................................................... 38 Table 8-13. Base Address of Logical Devices .................................................................................................. 38 Table 9-1. Memory Stick Register List .............................................................................................................. 77 Table 9-2. Address Map on the LPC Bus ......................................................................................................... 81 Table 9-3. Environment Controller Registers.................................................................................................... 82 Table 9-4. Digital Output Register (DOR) ....................................................................................................... 105 Table 9-5. Tape Drive Register (TDR) ............................................................................................................ 105 Table 9-6. Main Status Register (MSR) .......................................................................................................... 106 Table 9-7. Data Rate Select Register (DSR) .................................................................................................. 107 Table 9-8. Data Register (FIFO) ..................................................................................................................... 108 Table 9-9. Digital Input Register (DIR) ............................................................................................................ 108 Table 9-10. Diskette Control Register (DCR).................................................................................................. 108 Table 9-11. Status Register 0 (ST0) ............................................................................................................... 109 Table 9-12. Status Register 1 (ST1) ............................................................................................................... 110 Table 9-13. Status Register 2 (ST2) ............................................................................................................... 110 Table 9-14. Status Register 3 (ST3) ............................................................................................................... 111 Table 9-15. Command Set Symbol Descriptions ............................................................................................ 111 Table 9-16. Command Set Summary.............................................................................................................. 114 Table 9-17. Effects of MT and N Bits .............................................................................................................. 122

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IT8726F V0.3

Contents
Table 9-18. SCAN Command Result .............................................................................................................. 123 Table 9-19. VERIFY Command Result ........................................................................................................... 124 Table 9-20. Interrupt Identification .................................................................................................................. 126 Table 9-21. HUT Values.................................................................................................................................. 127 Table 9-22. SRT Values .................................................................................................................................. 127 Table 9-23. HLT Values .................................................................................................................................. 127 Table 9-24. Effects of GAP and WG on FORMAT A TRACK and WRITE DATA Commands ....................... 128 Table 9-25. Effects of Drive Mode and Data Rate on FORMAT A TRACK and WRITE DATA Commands .. 128 Table 9-26. Serial Channel Registers ............................................................................................................. 129 Table 9-27. Interrupt Enable Register Description.......................................................................................... 130 Table 9-28. Interrupt Identification Register.................................................................................................... 131 Table 9-29. FIFO Control Register Description............................................................................................... 132 Table 9-30. Receiver FIFO Trigger Level Encoding ....................................................................................... 132 Table 9-31. Baud Rates Using (24 MHz 13) Clock...................................................................................... 133 Table 9-32. Line Control Register Description ................................................................................................ 134 Table 9-33. Stop Bits Number Encoding......................................................................................................... 134 Table 9-34. Modem Control Register Description........................................................................................... 135 Table 9-35. Line Status Register Description ................................................................................................. 135 Table 9-36. Modem Status Register Description ............................................................................................ 136 Table 9-37. Reset Control of Registers and Pinout Signals ........................................................................... 137 Table 9-38. SCRCLK Selections..................................................................................................................... 141 Table 9-39. Parallel Port Connector in Different Modes ................................................................................. 144 Table 9-40. Address Map and Bit Map for SPP and EPP Modes................................................................... 144 Table 9-41. Bit Map of the ECP Registers ...................................................................................................... 147 Table 9-42. ECP Register Definitions ............................................................................................................. 147 Table 9-43. ECP Mode Descriptions............................................................................................................... 148 Table 9-44. ECP Pin Descriptions................................................................................................................... 148 Table 9-45. Extended Control Register (ECR) Mode and Description ........................................................... 150 Table 9-46. Data Register READ/WRITE Controls......................................................................................... 153 Table 9-47. Status Register ............................................................................................................................ 154 Table 9-48. List of CIR Registers .................................................................................................................... 156 Table 9-49. Modulation Carrier Frequency ..................................................................................................... 161 Table 9-50. Receiver Demodulation Low Frequency (HCFS = 0) .................................................................. 162 Table 9-51. Receiver Demodulation High Frequency (HCFS = 1) ................................................................. 163 Table 11-1. Power Sequence AC Timing Parameter...................................................................................... 180

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Features
1. Features
Low Pin Count Interface Comply with Intel Low Pin Count Interface Specification Rev. 1.0 Supports LDRQ#, SERIRQ protocols Supports PCI PME# Interfaces

ACPI & LANDesk Compliant ACPI V. 1.0 compliant Register sets compatible with Plug and Play ISA Specification V. 1.0a LANDesk 3.X compliant Supports 12 logical devices

Smart Card Reader Compliant with Personal Computer Smart Card (PC/SC) Working Group standard Compliant with smart card (ISO 7816) protocols Supports card present detect Supports Smart Card insertion power-on feature Supports one programmable clock frequency, and 7.1 MHz and 3.5 MHz (Default) card clocks

Enhanced Hardware Monitor Built-in 8-bit Analog to Digital Converter 3 thermal inputs from remote thermal resistor or thermal diode or diode-connected transistor 8 voltage monitor inputs (VBAT is measured internally.) 1 chassis open detection input with low power Flip-Flop backed by the battery Watch Dog comparison of all monitored values Provides VID0 VID5 support for the CPU External Thermal Sensor Host support.

Consumer Remote Control (TV remote) IR with power-up feature IEEE 1284 Parallel Port Standard mode -- Bi-directional SPP compliant Enhanced mode -- EPP V. 1.7 and V. 1.9 compliant High speed mode -- ECP, IEEE 1284 compliant Back-drive current reduction Printer power-on damage reduction Supports POST (Power-On Self Test) Data Port

Fan Speed Controller Provides fan on-off and PWM control Supports 5 programmable Pulse Width Modulation (PWM) outputs 128 steps of PWM modes Monitors 5 fan tachometer inputs

Floppy Disk Controller Supports two 360K/ 720K/ 1.2M/ 1.44M/ 2.88M floppy disk drives Enhanced digital data separator 3-Mode drives supported Supports automatic write protection via software

SmartGuardian Controller Provides programmable fan speed automatic control Supports mix-and-match for temperature inputs and fan speed control outputs Overrides fan speed controller during catastrophic situations Provides over temperature beep tone warning

Two 16C550 UARTs Supports two standard Serial Ports Supports IrDA 1.0/ASKIR protocols Supports Smart Card Reader protocols

Keyboard Controller 8042 compatible for PS/2 keyboard and mouse Hardware KBC GateA20 and Keyboard reset output Supports any key, or 2-5 sequential keys, or 13 simultaneous keys keyboard power-on events Supports mouse double-click and/or mouse move power on events Supports Keyboard and Mouse I/F hardware auto-swap

www.ite.com.tw Specifications subject to Change without Notice

IT8726F V0.3 ITPM-PN-200640 By Joseph Huang, 9/8/2006

IT8726F
Game Port Built-in 558 quad timers and buffer chips Supports direct connection of two joysticks

AMD CPU Power Sequence Controller Built-in enhanced voltage comparator

Dedicated MIDI Interface MPU-401 UART mode compatible 48 General Purpose I/O Pins Input mode supports either switch de-bounce or programmable external IRQ input routing Output mode supports 2 sets of programmable LED blinking periods Serial Flash I/F for BIOS Supports SPI I/F Watch Dog Timer Time resolution 1 minute or 1 second, maximum 65535 minutes or 65535 seconds Output to KRST# when expired

ITE innovative automatic power-failure resume and power button de-bounce Dedicated Infrared pins VCCH and Vbat Supported Built-in 32.768 KHz Oscillator Single 24/48 MHz Clock Input +5V Power Supply 128-pin QFP

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IT8726F V0.3

General Description
2. General Description
The IT8726F is a Low Pin Count Interface-based highly integrated Super I/O. The IT8726F provides the most commonly used legacy Super I/O functionality plus the latest Environment Control initiatives, such as H/W Monitor, Fan Speed Controller, ITEs SmartGuardian function and Smart Card Reader Interface. The devices LPC interface complies with Intel LPC Interface Specification Rev. 1.0. The IT8726F is ACPI & LANDesk compliant. The IT8726F features the enhanced hardware monitor providing 3 thermal inputs from remote thermal resistors, or thermal diode or diode-connected transistor (2N3904). The device also provides the ITE innovative intelligent automatic Fan ON/OFF & speed control functions (SmartGuardian) to protect the system, reducing the system noise and power consumption. It also features a PC/SC and ISO 7816 compliant Smart Card Reader. The IT8726F contains one game port which supports 2 joysticks, 1 MIDI port, and 1 Fan Speed Controller. The fan speed controller is responsible to control 5 fan speeds through three 128 steps of Pulse Width Modulation (PWM) output pins and to monitor five FANs Tachometer inputs. It also features two 16C550 UARTs, one IEEE 1284 Parallel Port, one Floppy Disk Controller and one 8042 Keyboard Controller. The IT8726F has integrated 12 logical devices. One high-performance 2.88MB floppy disk controller, with digital data separator, supports two 360K/ 720K/ 1.2M/ 1.44M/ 2.88M floppy disk drives. One multi-mode high-performance parallel port features the bi-directional Standard Parallel Port (SPP), the Enhanced Parallel Port (EPP V. 1.7 and EPP V. 1.9 are supported), and the IEEE 1284 compliant Extended Capabilities Port (ECP). Two 16C550 standard compatible enhanced UARTs perform asynchronous communication, and also support either IR or MIDI interfaces. One game port with built-in 558 quad timers and buffer chips supports direct connection of 2 joysticks. The device also features one MPU-401 UART mode compatible MIDI port, one fan speed controller responsible for controlling / monitoring 5 fans and 6 GPIO ports (48 GPIO pins). The IT8726F also has an integrated 8042 compatible Keyboard Controller. These 12 logical devices can be individually enabled or disabled via software configuration registers. The IT8726F utilizes power-saving circuitry to reduce power consumption, and once a logical device is disabled the inputs are gated inhibit, the outputs are tri-state, and the input clock is disabled. The device requires a single 24/48 MHz clock input and operates with +5V power supply. The IT8726F is available in 128-pin QFP (Quad Flat Package).

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Block Diagram
3. Block Diagram
SERIRQ LDRQ#

24 / 48 MHz OSC. Serial Port I/F IR I/F SCR I/F Serial Port I/F

Clock Gen. 16C550 UART 1 IrDA 1.0 / ASKIR

LPC Interface & Plug-and-Play Registers Keyboard Controller MPU-401 UART mode
Central Interface Bus

LPC I/F

PME# Mouse I/F Keyboard I/F MIDI I/F CIR I/F Joystick I/F I/O Ports Serial Flash I/F Fan I/F Thermal Sensor

Smart Card

Reader 16C550 UART 2 IEEE1284 Parallel Port Floppy Disk Controller 8-bit ADC

Consumer I/R Game Port General Purpose I/O Serial Flash I/F Fan Speed Controller

Parallel Port I/F Floppy Drive I/F

Environment Controller

Monitored Voltages

Fan Tachometers

Thermal Resistor

Thermal Diode

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IT8726F V0.3

Pin Configuration
4. Pin Configuration

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SE RIRQ LFRAME# LAD0 LAD1 LAD2 LAD3 KRS T#/GP62 GA20/JP7 PCICLK PCIRS T5#/GP50 CLK IN GNDD DENSEL# MTRA# ETS_DA T/MTRB# DRVA# ETS_CLK/DRVB# WDATA# DIR# S TEP# HDSEL# WGATE# RDATA# TRK0# INDEX# WPT#

39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64

DTR2#/JP 4 RTS2/JP 5 DSR2#/GP64/VCORE_EN VCC SOUT2/JP 6 SIN2/GP 63/VCORE_GD FAN_TAC1 FAN_CTL1 FAN_TAC2/GP 52 FAN_CTL2/GP 51 FAN_TAC3/GP 37 FAN_CTL3/GP 36 VID5/GP 35 VID4/GP 34 GNDD VID3/GP 33 VID2/GP 32 VID1/GP 31 VID0/GP 30 VIDO5FAN_CTL4/JSBB2/GP 27 VIDO4/FAN_CTL5/JSBB1/GP 26 VIDO3/FAN_TAC4/JSBCY/GP 25 VIDO2/FAN_TAC5/JSBCX/GP 24 JSAB2/GP 23/SI JSAB1/GP 22/SCK VIDO1/JSACY/GP 21 VIDO0/JSACX/GP 20 MIDI_OUT/GP 17 MIDI_IN/GP16/SO2 RESETCON#/CIRTX/CE_N PCIRST1#/SCRRST/GP 14 PWROK 1/SCRPFET#/GP 13 PCIRST2#/SCRIO/GP 12 PCIRST3#/SCRCLK/GP 11 VCC VIDVCC LRESET# LDRQ#/JP 8

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38

128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103

CTS2#/GP65/VDA_E N RI2#/GP66/VLDT_EN DCD2#/GP67/CP U_PG SIN1 SOUT1/JP 3 DSR1# RTS1#/JP2 DTR1#/JP1 CTS1# RI1# DCD1# GNDD PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 STB# AFD# ERR# INIT# SLIN# ACK#

IT8726F 128-QFP

102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65

BUSY PE SLCT AVCC VIN0 VIN1 VIN2 VIN3/ATXPG VIN4/VLDT_12 VIN5/VDDA_25 VIN6/VDIMM_STR VIN7/PCIRSTIN# VREF TMPIN1 TMPIN2 TMPIN3/SO1 GNDA(D-) RSMRST#/CIRRX/GP55 PCIRST4#/SCRPSNT#/GP10/VDIMM_STR_EN MCLK/GP 56 MDAT/GP57 KCLK/GP60 KDAT/GP 61 3VSBSW#/GP40 PWROK2/GP41 SUSC#/GP53 PSON#/GP42 PANSWH#/GP 43 GNDD PME#/GP54 PWRON#/GP 44 SUSB#/GP45 GP46/IRRX VBAT COPEN# VCCH IRTX/GP47 DSKCHG#

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IT8726F V0.3

IT8726F
Table 4-1. Pins Listed in Numeric Order
Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 Signal DTR2#/JP4 RTS2#/JP5 DSR2#/GP64/ VCORE_EN VCC SOUT2/JP6 SIN2/GP63/ VCORE_GD FAN_TAC1 FAN_CTL1 FAN_TAC2/GP52 FAN_CTL2/GP51 FAN_TAC3/GP37 FAN_CTL3/GP36 VID5/GP35 VID4/GP34 GNDD VID3/GP33 VID2/GP32 VID1/GP31 VID0/GP30 VIDO5/ FAN_CTL4/ JSBB2/GP27 VIDO4/ FAN_CTL5/ JSBB1/GP26 VIDO3/ FAN_TAC4/ JSBCY/GP25 VIDO2/ FAN_TAC5/ JSBCX/GP24 JSAB2/GP23/SI JSAB1/GP22/SCK VIDO1/JSACY/ GP21 VIDO0/JSACX/ GP20 MIDI_OUT/GP17 MIDI_IN/GP16/ SO2 RESETCON#/ CIRTX/CE_N PCIRST1#/ SCRRST/GP14 PWROK1/ SCRPFET#/GP13 Pin 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 Signal PCIRST2#/ SCRIO/GP12 PCIRST3#/ SCRCLK/GP11 VCC VIDVCC LRESET# LDRQ#/JP8 SERIRQ LFRAME# LAD0 LAD1 LAD2 LAD3 KRST#/GP62 GA20/JP7 PCICLK PCIRST5#/GP50 CLKIN GNDD DENSEL# MTRA# ETS_DAT/MTRB# DRVA# ETS_CLK/DRVB# WDATA# DIR# STEP# HDSEL# WGATE# RDATA# TRK0# INDEX# WPT# Pin 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 Signal DSKCHG# IRTX/GP47 VCCH COPEN# VBAT GP46/IRRX SUSB#/GP45 PWRON#/GP44 PME#/GP54 GNDD PANSWH#/GP43 PSON#/GP42 SUSC#/GP53 PWROK2/GP41 3VSBSW#/GP40 KDAT/GP61 KCLK/GP60 MDAT/GP57 MCLK/GP56 PCIRST4#/ SCRPSNT#/GP10 /VDIMM_STR_EN RSMRST#/CIRRX/ GP55 GNDA(D-) TMPIN3/SO1 TMPIN2 TMPIN1 VREF VIN7/PCIRSTIN# VIN6/VDIMM_STR VIN5/VDDA_25 VIN4/VLDT_12 VIN3/ATXPG VIN2 Pin 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 VIN1 VIN0 AVCC SLCT PE BUSY ACK# SLIN# INIT# ERR# AFD# STB# PD0 PD1 PD2 PD3 PD4 PD5 PD6 PD7 GNDD DCD1# RI1# CTS1# DTR1#/JP1 RTS1#/JP2 DSR1# SOUT1/JP3 SIN1 DCD2#/GP67/ CPU_PG RI2#/GP66/ VLDT_EN CTS2#/GP65/ VDDA_EN Signal

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IT8726F V0.3

Pin Descriptions
5. IT8726F Pin Descriptions
Table 5-1. Pin Description of Supplies Signals
Pin(s) No. 4, 35 99 67 69 36 15, 50, 74, 117 86 Symbol VCC AVCC VCCH VBAT VIDVCC GNDD GNDA(D-) Attribute PWR PWR PWR PWR PWR GND GND Power Description +5V Power Supply. +5V Analog Power Supply. +5V VCC Help Supply. +3.3V Battery Supply. VID power supply. (1.2 or 3.3V) Digital Ground. Analog Ground.(D-)

Table 5-2. Pin Description of LPC Bus Interface Signals

Pin(s) No. 37 38 Symbol LRESET# LDRQ#/ JP8 SERIRQ LFRAME# LAD[0:3] PCICLK PCIRST5#/ GP50 Attribute DI DO16 Power VCC VCC Description LPC RESET #. EC block will not be reset by LRESET#, which is controlled by VCC PWRGD. LPC DMA Request #. An encoded signal for DMA channel select. During LRESET#, this pin is input for JP8 power-on strapping option. Serial IRQ. LPC Frame #. This signal indicates the start of LPC cycle. LPC Address / Data 0 - 3. 4-bit LPC address/bi-directional data lines. LAD0 is the LSB and LAD3 is the MSB. PCI Clock. 33 MHz PCI clock input for LPC I/F and SERIRQ. PCI Reset 5 # / General Purpose I/O 50. The first function of this pin is PCI Reset 5 #. It is a buffer output of LRESET# if bit1 of Index 2Ch is 0. It will be (LRESET# AND PCIRSTIN#) if bit1 of Index 2Ch is 1. The second function of this pin is the General Purpose I/O 50. The function configuration of this pin is decided by the software configuration registers. Power Management Event # / General Purpose I/O 54. The first function of this pin is the power management event #. It supports the PCI PME# interface. This signal allows the peripheral to request the system to wake up from the D3 (cold) state. The second function of this pin is the General Purpose I/O Port 5 Bit 4. The function configuration of this pin is determined by programming the software configuration registers.

39 40 41 44 47 48

DIO16 DI DIO16 DI DO16/ DIOD16

VCC VCC VCC VCC VCC

73

PME#/ GP54

DOD8/ DIOD8

VCCH

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IT8726F V0.3

IT8726F
Table 5-3. Pin Description of MIDI Interface Signals
Pin(s) No. 28 Symbol MIDI_OUT/ GP17 Attribute DO8/ DIOD8 Power VCC Description MIDI Output / General Purpose I/O 17. The first function of this pin is MIDI Output. The second function of this pin is the General Purpose I/O Port 1 Bit 7. The function configuration of this pin is determined by programming the software configuration registers. MIDI Input / General Purpose I/O 16 / Serial Output Data 2. The first function of this pin is MIDI Input. The second function of this pin is the General Purpose I/O Port 1 Bit 6. The third function of this pin is Serial Output Data from Serial Flash. The function configuration of this pin is determined by programming the software configuration registers.

29

MIDI_IN/ GP16/ SO2

DI/ DIOD8/ DI

VCC

Table 5-4. Pin Description of Game Port Signals

Pin(s) No. 27 Symbol VIDO0/ JSACX/ GP20 Attribute DIOD8/ DIOD8/ DIOD8 Power VCC Description VID Out 0 / Joystick A Coordinate X / General Purpose I/O 20. The first function of this pin is VID output pin 0. The second function of this pin is Joystick A Coordinate X. The third function of this pin is the General Purpose I/O Port 2 Bit 0. The function configuration of this pin is determined by programming the software configuration registers. VID Out 1 / Joystick A Coordinate Y / General Purpose I/O 21. The first function of this pin is VID output pin 1. The second function of this pin is Joystick A Coordinate Y. The third function of this pin is the General Purpose I/O Port 2 Bit 1. The function configuration of this pin is determined by programming the software configuration registers. Joystick A Button 1 / General Purpose I/O 22 / Serial Flash Clock. The first function of this pin is Joystick A Button 1. The second function of this pin is the General Purpose I/O Port 2 Bit 2. The third function is Serial Clock for Serial Flash. It can be multi-cycle function with JSAB1. The function configuration of this pin is determined by programming the software configuration registers. Joystick A Button 2 / General Purpose I/O 23/ Serial Flash In Data. The first function of this pin is Joystick A Button 2. The second function of this pin is the General Purpose I/O Port 2 Bit 3. The third function is Serial In Data for Serial Flash. It can be multi-cycle function with JSAB2. The function configuration of this pin is determined by programming the software configuration registers.

26

VIDO1/ JSACY/ GP21

DIOD8/ DIOD8/ DIOD8

VCC

25

JSAB1/ GP22/ SCK

DI/ DIOD8/ DOD8

VCC

24

JSAB2/ GP23/ SI

DI/ DIOD8/ DOD8

VCC

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Pin Descriptions
Pin(s) No. 23 Symbol VIDO2/ FAN_TAC5/ JSBCX/ GP24 Attribute DIOD8/ DI/ DIOD8/ DIOD8 Power VCC Description VID Out 2 / FAN_TAC5 / Joystick B Coordinate X / General Purpose I/O 24. The first function of this pin is VID output pin 2. The second function of this pin is Fan Tachometer Input 5. 0 to +5V amplitude fan tachometer input. The third function of this pin is Joystick B Coordinate X. The fourth function of this pin is the General Purpose I/O Port 2 Bit 4. The function configuration of this pin is determined by programming the software configuration registers. VID Out 3 / FAN_TAC4 / Joystick B Coordinate Y / General Purpose I/O 25. The first function of this pin is VID output pin 3. The second function of this pin is Fan Tachometer Input 4. 0 to +5V amplitude fan tachometer input. The third function of this pin is Joystick B Coordinate Y. The fourth function of this pin is the General Purpose I/O Port 2 Bit 5. The function configuration of this pin is determined by programming the software configuration registers. VID Out 4 / FAN_CTL5 / Joystick B Button 1 / General Purpose I/O 26. The first function of this pin is VID output pin 4. The second function of this pin is Fan Control Output 5. (PWM output signal to Fans FET.) The third function of this pin is Joystick B Button 1. The fourth function of this pin is the General Purpose I/O Port 2 Bit 6. The function configuration of this pin is determined by programming the software configuration registers. VID Out 5 / FAN_CTL4 / Joystick B Button 2 / General Purpose I/O 27. The first function of this pin is VID output pin 5. The second function of this pin is Fan Control Output 4. (PWM output signal to Fans FET.) The third function of this pin is Joystick B Button 2. The fourth function of this pin is the General Purpose I/O Port 2 Bit 7. The function configuration of this pin is determined by programming the software configuration registers.

22

VIDO3/ FAN_TAC4/ JSBCY/ GP25

DIOD8/ DI/ DIOD8/ DIOD8

VCC

21

VIDO4/ FAN_CTL5/ JSBB1/ GP26

DIOD8/ DOD8 DI/ DIOD8

VCC

20

VIDO5/ FAN_CTL4/ JSBB2/ GP27

DIOD8/ DOD8/ DI/ DIOD8

VCC

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IT8726F
Table 5-5. Pin Description of Hardware Monitor SignalsNote1
Pin(s) No. 98 96 95 Symbol VIN[0:2] ATXPG/ VIN3 Attribute AI DI/AI Power AVCC AVCC Description Voltage Analog Inputs [0:2]. 0 to 4.096V FSR Analog Inputs. Voltage Analog Input 3 / ATX Power Good. The first function of this pin is ATX Power Good. PWROK1/2 will be (VCC power-level-detect AND RESETCON# AND SUSB# AND ATXPG) if bit0 of Index 2Ch is 1, or (VCC power-level-detect AND RESETCON# AND SUSB#) if the bit is 0. The second function of this pin is 0 to 4.096V FSR Analog Inputs. The function configuration of this pin is determined by programming the software configuration registers. VLDT (1.2V) analog inputs / Voltage Analog Input 4. The first function of this pin is VLDT (1.2V) analog inputs. The second function of this pin is 0 to 4.096V FSR Analog Inputs. The function configuration of this pin is determined by programming the software configuration registers. VDDA (2.5V) analog inputs / Voltage Analog Input 5. The first function of this pin is VDDA (2.5V) analog inputs. The second function of this pin is 0 to 4.096V FSR Analog Inputs. The function configuration of this pin is determined by programming the software configuration registers. VDIMM DUAL STR (1.8V) analog inputs / Voltage Analog Input 6. The first function of this pin is VDIMM DUAL STR (1.8V) analog inputs. The second function of this pin is 0 to 4.096V FSR Analog Inputs. The function configuration of this pin is determined by programming the software configuration registers. Voltage Analog Input 7 / PCI Reset Input #. The first function of this pin is PCI Reset Input #. The second function of this pin is 0 to 4.096V FSR Analog Inputs. The function configuration of this pin is determined by programming the software configuration registers. Reference Voltage Output. Regulated and referred voltage for 3 external temperature sensors and negative voltage monitor. External Thermal Inputs [1:2]. Connected to thermistors [1:3] or thermal temperature sensors. External Thermal Inputs 3/ Serial Flash Output Data 1. The first function of this pin is connected to thermistor 3 or thermal temperature sensor. The second function of this pin is Serial Output Data 1 from Serial Flash. The function configuration of this pin is determined by programming the software configuration registers. Fan Tachometer Input 1. 0 to +5V amplitude fan tachometer input.

94

VLDT_12/ VIN4

AI/ AI

AVCC

93

VDDA_25/ VIN5

AI/AI

AVCC

92

VDIMM_STR/ VIN6

AI/ AI

AVCC

91

PCIRSTIN#/ VIN7

DI/ AI

AVCC

90 89 88 87

VREF TMPIN[1:3] TMPIN3/ SO1

AO AI AI/ DI

AVCC AVCC AVCC

FAN_TAC1

DI

VCC

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Pin Descriptions
Pin(s) No. 9 Symbol FAN_TAC2/ GP52 Attribute DI/ DIOD8 Power VCC Description Fan Tachometer Input 2 / General Purpose I/O 52. The first function of this pin is Fan Tachometer Input 2. 0 to +5V amplitude fan tachometer input. The second function of this pin is the General Purpose I/O Port 5 Bit 2. The function configuration of this pin is determined by programming the software configuration registers. Fan Tachometer Input 3 / General Purpose I/O 37. The first function of this pin is Fan Tachometer Input 3. 0 to +5V amplitude fan tachometer input. The second function of this pin is the General Purpose I/O Port 5 Bit 2. The function configuration of this pin is determined by programming the software configuration registers. Voltage ID 0 / General Purpose I/O 30. The first function of this pin is Voltage ID Input 0. The Voltage ID is the voltage supply readouts from the CPU. This value is read in the VID register. The input threshold can be selected by the power-on strapping of JP6 (pin 2). (2.0/0.8V when JP6=1, 0.8/0.4V when JP6=0) The second function of this pin is the General Purpose I/O 30. The function configuration of this pin is decided by the software configuration registers. Voltage ID 1 / General Purpose I/O 31. The first function of this pin is Voltage ID Input 1. The Voltage ID is the voltage supply readouts from the CPU. This value is read in the VID register. The input threshold can be selected by the power-on strapping of JP6 (pin 2). (2.0/0.8V when JP6=1, 0.8/0.4V when JP6=0) The second function of this pin is the General Purpose I/O 31. The function configuration of this pin is decided by the software configuration registers. Voltage ID 2 / General Purpose I/O 32. The first function of this pin is Voltage ID Input 2. The Voltage ID is the voltage supply readouts from the CPU. This value is read in the VID register. The input threshold can be selected by the power-on strapping of JP6 (pin 2). (2.0/0.8V when JP6=1, 0.8/0.4V when JP6=0) The second function of this pin is the General Purpose I/O 32.

11

FAN_TAC3/ GP37

DI/ DIOD8

VCC

19

VID0/ GP30

DIO8/ DIOD8

VCC

18

VID1/ GP31

DIO8/ DIOD8

VCC

17

VID2/ GP32

DIO8/ DIOD8

VCC

The function configuration of this pin is decided by the software configuration registers.
16 VID3/ GP33 DIO8/ DIOD8 VCC Voltage ID 3 / General Purpose I/O 33. The first function of this pin is Voltage ID Input 3. The Voltage ID is the voltage supply readouts from the CPU. This value is read in the VID register. The input threshold can be selected by the power-on strapping of JP6 (pin 2). (2.0/0.8V when JP6=1, 0.8/0.4V when JP6=0) The second function of this pin is the General Purpose I/O 33. The function configuration of this pin is decided by the software configuration registers.

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IT8726F
Pin(s) No. 14 Symbol VID4/ GP34 Attribute DIO8/ DIOD8 Power VCC Description Voltage ID 4 / General Purpose I/O 34. The first function of this pin is Voltage ID Input 4. The Voltage ID is the voltage supply readouts from the CPU. This value is read in the VID register. The input threshold can be selected by the power-on strapping of JP6 (pin 2). (2.0/0.8V when JP6=1, 0.8/0.4V when JP6=0) The second function of this pin is the General Purpose I/O 34. The function configuration of this pin is decided by the software configuration registers. Voltage ID 5 / General Purpose I/O 35. The first function of this pin is Voltage ID Input 5. The Voltage ID is the voltage supply readouts from the CPU. This value is read in the VID register. The input threshold can be selected by the power-on strapping of JP6 (pin 2). (2.0/0.8V when JP6=1, 0.8/0.4V when JP6=0) The second function of this pin is the General Purpose I/O 35. The function configuration of this pin is decided by the software configuration registers. Case Open Detection #. The Case Open Detection is connected to a specially designed low power CMOS flip-flop backed by the battery for case open state preservation during power loss.

13

VID5/ GP35

DIO8/ DIOD8

VCC

68

COPEN#

DIOD8

VCCH or VBAT

Table 5-6. Pin Description of Fan Controller Signals

Pin(s) No. 8 10 Symbol FAN_CTL1 FAN_CTL2/ GP51 Attribute DOD8 DOD8/ DIOD8 Power VCC VCC Description Fan Control Output 1. (PWM output signal to Fans FET.) Fan Control Output 2 / General Purpose I/O 51. The first function of this pin is Fan Control Output 2. (PWM output signal to Fans FET.) The second function of this pin is the General Purpose I/O Port 5 Bit 1. The function configuration of this pin is determined by programming the software configuration registers. Fan Control Output 3 / General Purpose I/O 36. The first function of this pin is Fan Control Output 3. (PWM output signal to Fans FET.) The second function of this pin is the General Purpose I/O Port 3 Bit 6. The function configuration of this pin is determined by programming the software configuration registers.

12

FAN_CTL3/ GP36

DOD8/ DIOD8

VCC

Table 5-7. Pin Description of Infrared Port Signals

Pin(s) No. 30 Symbol RESETCON#/ CIRTX/ CE_N Attribute DI/DOD8/ DOD8 Power VCC Description Reset Connect # / Consumer Infrared Transmit Output / Serial Flash Chip Enable. The first function of this pin is Reset Connect #. It connects to reset button, and also other reset source on the motherboard. The second function of this pin is Consumer Infrared Transmit Output. The third function of this pin is the Serial Flash chip enable. The function configuration of this pin is determined by programming the software configuration registers.

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Pin Descriptions
Pin(s) No. 85 Symbol RSMRST#/ CIRRX/ GP55 Attribute DOD8/ DI/ DIOD8 Power VCCH Description Resume Reset # / Consumer Infrared Receive Input / General Purpose I/O 55. The first function of this pin is Consumer Infrared Receive Input. The second function of this pin is Resume Reset #. It is power good signal of VCCH. The high threshold is 4V 0.2V, and the low threshold is 3.5V 0.2V The Third function of this pin is the General Purpose I/O Port 5 Bit 5. The function configuration of this pin is determined by programming the software configuration registers. General Purpose I/O 46 / Infrared Receive Input/. The first function of this pin is the Infrared Receive Input. The second function of this pin is General Purpose I/O Port 4 Bit 6. The function configuration of this pin is determined by programming the software configuration registers. Infrared Transmit Output / General Purpose I/O 47. The first function of this pin is Infrared Transmit output. The second function of this pin is the General Purpose I/O Port 4 Bit 7. The function configuration of this pin is determined by programming the software configuration registers.

70

GP46/ IRRX

DIOD8/ DI

VCCH

66

IRTX/ GP47

DO8/ DIOD8

VCC

Table 5-8. Pin Description of Serial Port 1 Signals

Pin(s) No. 125 124 Symbol SIN1 SOUT1/ JP3 Attribute DI DO8/ DI Power VCC VCC Description Serial Data Input 1. This input receives serial data from the communications link. Serial Data Output 1. This output sends serial data to the communications link. This signal is set to a marking state (logic 1) after a Master Reset operation or when the device is in one of the Infrared communications modes. During LRESET#, this pin is input for JP3 power-on strapping option. Data Set Ready 1 #. When the signal is low, it indicates that the MODEM or data set is ready to establish a communications link. The DSR# signal is a MODEM status input whose condition can be tested by reading the MSR register. Request to Send 1 #. When this signal is low, this output indicates to the MODEM or data set that the device is ready to send data. RTS# is activated by setting the appropriate bit in the MCR register to 1. After a Master Reset operation or during Loop mode, RTS# is set to its inactive state. During LRESET#, this pin is input for JP2 power-on strapping option. Data Terminal Ready 1 #. DTR# is used to indicate to the MODEM or data set that the device is ready to exchange data. DTR# is activated by setting the appropriate bit in the MCR register to 1. After a Master Reset operation or during Loop mode, DTR# is set to its inactive state. During LRESET#, this pin is input for JP1 power-on strapping option.

123

DSR1#

DI

VCC

122

RTS1#/ JP2

DO8/ DI

VCC

121

DTR1#/ JP1

DO8/ DI

VCC

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Pin(s) No. 120 Symbol CTS1# Attribute DI Power VCC Description Clear to Send 1 #. When the signal is low, it indicates that the MODEM or data set is ready to accept data. The CTS# signal is a MODEM status input whose condition can be tested by reading the MSR register. Ring Indicator 1 #. When the signal is low, it indicates that a telephone ring signal has been received by the MODEM. The RI# signal is a MODEM status input whose condition can be tested by reading the MSR register. Data Carrier Detect 1 #. When the signal is low, it indicates that the MODEM or data set has detected a carrier. The DCD# signal is a MODEM status input whose condition can be tested by reading the MSR register.

119

RI1#

DI

VCC

118

DCD1#

DI

VCC

Table 5-9. Pin Description of Serial Port 2 Signals

Pin(s) No. 6 Symbol VCORE_GD/ SIN2/ GP63 Attribute DI/ DI/ DIOD8 Power VCC Description VCORE Power-Good / Serial Data In 2/ General Purpose I/O 63. The first function of this pin is to indicate that the powergood signal is from the PWM controller for CPU core voltage. The second function of this pin is Serial Data In 2 of Serial Port 2. This input receives serial data from the communications link. The third function of this pin is the General Purpose I/O Port 6 Bit 3. This set only supports Simple I/O function. The function configuration of this pin is determined by programming the software configuration registers. Serial Data Out 2. This output sends serial data to the communications link. This signal is set to a marking state (logic 1) after a Master Reset operation or when the device is in one of the Infrared communications modes. The instant when internal power-ok is ready, this pin is input for JP6 power-on strapping option. VCORE enable / Data Set Ready 2 #/ General Purpose I/O 64. The first function of this pin is VCORE enable, which is to enable the PWM for CPU VCORE. The external pull high resistor is required. The second function of this pin is Data Set Ready 2 of Serial Port 2. When low, indicates that the MODEM or data set is ready to establish a communications link. The DSR# signal is a MODEM status input whose condition can be tested by reading the MSR register. The third function of this pin is the General Purpose I/O Port 6 Bit 4. This set only supports Simple I/O function. The function configuration of this pin is determined by programming the software configuration registers. Request to Send 2 #. When low, this output indicates to the MODEM or data set that the device is ready to send data. RTS# is activated by setting the appropriate bit in the MCR register to 1. After a Master Reset operation or during Loop mode, RTS# is set to its inactive state. During LRESET#, this pin is input for JP5 power-on strapping option.

SOUT2/ JP6

DO8/ DI

VCC

VCORE_EN/ DSR2#/ GP64

DI/ DI/ DIOD8

VCC

RTS2#/ JP5

DO8/ DI

VCC

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Pin Descriptions
Pin(s) No. 1 Symbol DTR2#/ JP4 Attribute DO8/ DI Power VCC Description Data Terminal Ready 2 #. DTR# is used to indicate to the MODEM or data set that the device is ready to exchange data. DTR# is activated by setting the appropriate bit in the MCR register to 1. After a Master Reset operation or during Loop mode, DTR# is set to its inactive state. During LRESET#, this pin is input for JP4 power-on strapping option VDDA Enable / Clear to Send 2 #/ General Purpose I/O 65. The first function of this pin is to enable the VDDA power for K8 CPU. The external pull high resistor is required. The second function of this pin is cleared to Send 2 of Serial Port 2. When low, indicates that the MODEM or data set is ready to accept data. The CTS# signal is a MODEM status input whose condition can be tested by reading the MSR register. The third function of this pin is the General Purpose I/O Port 6 Bit 5. This set only supports Simple I/O function. The function configuration of this pin is determined by programming the software configuration registers. VLDT Enable / Ring Indicator 2 #/ General Purpose I/O 66. The first function of this pin is to enable the VLDT voltage. The external pull high resistor is required. The second function of this pin is Ring Indicator 2 of Serial Port 2. When low, indicates that a telephone ring signal has been received by the MODEM. The RI# signal is a MODEM status input whose condition can be tested by reading the MSR register. The third function of this pin is the General Purpose I/O Port 6 Bit 6. This set only supports Simple I/O function. The function configuration of this pin is determined by programming the software configuration registers. CPU Power-Good / Data Carrier Detect 2 #/ General Purpose I/O 67. The first function of this pin is to output indicates that CPU power-good is ready. The external pull high resistor is required. The second function of this pin is Data Carrier Detect 2 of Serial Port 2. When low, indicates that the MODEM or data set has detected a carrier. The DCD# signal is a MODEM status input whose condition can be tested by reading the MSR register. The third function of this pin is the General Purpose I/O Port 6 Bit 7. This set only supports Simple I/O function. The function configuration of this pin is determined by programming the software configuration registers.

128

VDDA_EN/ CTS2#/ GP65

DOD8/ DI/ DIOD8

VCC

127

VLDT_EN/ RI2#/ GP66

DOD8/ DI/ DIOD8

VCC

126

CPU_PG/ DCD2#/ GP67

DOD16/ DI/ DIOD8

VCC

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IT8726F
Table 5-10. Pin Description of Parallel Port Signals
Pin(s) No. 100 101 102 103 104 Symbol SLCT PE BUSY ACK# SLIN# Attribute DI DI DI DI DIO24 Power VCC VCC VCC VCC VCC Description Printer Select. This signal goes high when the line printer has been selected. Printer Paper End. This signal is set high by the printer when it runs out of paper. Printer Busy. This signal goes high when the line printer has a local operation in progress and cannot accept data. Printer Acknowledge #. This signal goes low to indicate that the printer has already received a character and is ready to accept another one. Printer Select Input #. When the signal is low, the printer is selected. This signal is derived from the complement of bit 3 of the printer control register. Printer Initialize #. When the signal is low, the printer is selected. This signal is derived from the complement of bit 3 of the printer control register. Printer Error #. When the signal is low, it indicates that the printer has encountered an error. The error message can be read from bit 3 of the printer status register. Printer Auto Line Feed #. When the signal is low, it is derived from the complement of bit 1 of the printer control register and is used to advance one line after each line is printed. Printer Strobe #. When the signal is low, it is the complement of bit 0 of the printer control register and is used to strobe the printing data into the printer. Parallel Port Data [0:7]. This bus provides a byte-wide input or output to the system. The eight lines are held in a high impedance state when the port is deselected.

105

INIT#

DIO24

VCC

106

ERR#

DI

VCC

107

AFD#

DIO24

VCC

108

STB#

DI

VCC

109 116

PD[0:7]

DIO24

VCC

Table 5-11. Pin Description of Floppy Disk Controller Signals Pin(s) No.
51 52 53

Symbol
DENSEL# MTRA# ETS_DAT/ MTRB#

Attribute
DO24L DO24L DIOD24/ DO24L

Power
VCC VCC VCC

Description
FDD Density Select #. DENSEL# is high for high data rates (500 Kbps, 1 Mbps). DENSEL# is low for low data rates (250 Kbps, 300 Kbps). FDD Motor A Enable #. This signal is active low. External Thermal Sensor Data / FDD Motor B Enable #. The first function of this pin is External Thermal Sensor Data. The second function of this pin is FDD Motor B #. This signal is active low. The function configuration of this pin is determined by programming the software configuration registers. When External Thermal Sensor Host is enabled (bit6 of EC Index 0Ah), this pin is selected as ETS_DAT. FDD Drive A Enable #. This signal is active low.

54

DRVA#

DO24L

VCC

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Pin Descriptions
Pin(s) No.
55

Symbol
ETS_CLK/ DRVB#

Attribute
DIOD24/ DO24L

Power
VCC

Description
External Thermal Sensor Clock / FDD Drive B Enable #. The first function of this pin is External Thermal Sensor Clock. The second function of this pin is FDD Drive B #. This signal is active low. The function configuration of this pin is determined by programming the software configuration registers. When External Thermal Sensor Host is enabled (bit6 of EC Index 0Ah), this pin is selected as ETS_CLK. FDD Write Serial Data to the Drive #. This signal is active low. FDD Head Direction #. Step in when this signal is low and step out when high during a SEEK operation. FDD Step Pulse #. This signal is active low. FDD Head Select #. This signal is active low. FDD Write Gage Enable #. This signal is active low. FDD Read Disk Data #. This signal is active low. It is serial data input from FDD. FDD Track 0 #. This signal is active low. It indicates that the head of the selected drive is on track 0. FDD Index #. This signal is active low. It indicates the beginning of a disk track. FDD Write Protect #. This signal is active low. It indicates that the disk of the selected drive is write-protected. FDD Disk Change #. This signal is active low. It senses whether the drive door has been opened or a diskette has been changed.

56 57 58 59 60 61 62 63 64 65

WDATA# DIR# STEP# HDSEL# WGATE# RDATA# TRK0# INDEX# WPT# DSKCHG#

DO24L DO24L DO24L DO24L DO24L DI DI DI DI DI

VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC

Table 5-12. Pin Description of Smart Card Reader Interface Signals

Pin(s) No. 31 Symbol PCIRST1#/ SCRRST/ GP14 Attribute DOD8Note2/ DOD8/ DIOD8 Power VCC Description PCI Reset 1 # / Smart Card Reset / General Purpose I/O 14. The first function of this pin is PCI Reset 1 #. It is a buffer of LRESET#. The second function of this pin is Smart Card Reset. The third function of this pin is the General Purpose I/O Port 1 Bit 4. The function configuration of this pin is determined by programming the software configuration registers. Power OK 1 of VCC / Smart Card Power FET Control Output # / General Purpose I/O 13. The first function of this pin is Power OK 1 of VCC. The second function of this pin is Smart Card Power FET Control Output #. The Smart Card Reader interface requires this pin to drive an external Power FET to supply the current for the Smart Card. The third function of this pin is the General Purpose I/O Port 1 Bit 3. The function configuration of this pin is determined by programming the software configuration registers.

32

PWROK1/ SCRPFET#/ GP13

DOD8/ DOD8/ DIOD8

VCC

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Pin(s) No. 33 Symbol PCIRST2#/ SCRIO / GP12 Attribute DOD8Note2/ DIOD8/ DIOD8 Power VCC Description PCI Reset 2 # / Smart Card Serial Data I/O / General Purpose I/O 12. The first function of this pin is PCI Reset 2 #. It is a buffer of LRESET#. The second function of this pin is Smart Card Serial Data I/O. The third function of this pin is the General Purpose I/O Port 1 Bit 2. The function configuration of this pin is determined by programming the software configuration registers. PCI Reset 3 # / Smart Card Clock / General Purpose I/O 11. The first function of this pin is PCI Reset 3 #. It is a buffer of LRESET#. It is a buffer output of LRESET# if bit1 of Index 2Ch is 0. It will be (LRESET# AND PCIRSTIN#) if bit1 of Index 2Ch is 1. The second function of this pin is Smart Card Clock. Three different card clocks are selectable from this pin: high speed (7.1 MHz), low speed (Default: 3.5 MHz) and a programmable card clock. The third function of this pin is the General Purpose I/O Port 1 Bit 1. The function configuration of this pin is determined by programming the software configuration registers. VDIMM STR Enable / PCI Reset 4 # / Smart Card Present Detect # / General Purpose I/O 10. The first function of this pin is to enable the PWM for VDIMM_STR dual voltage. The external pull high resistor is required. The second function of this pin is PCI Reset 4 #. It is a buffer of LRESET# The third function of this pin is Smart Card Present Detect #. This pin provides the Smart Card insertion detection for the Smart Card Reader interface. Upon detecting the insertion of the Smart Card, this pin will trigger the power-on event. The fourth function of this pin is the General Purpose I/O Port 1 Bit 0. The function configuration of this pin is determined by programming the software configuration registers.

34

PCIRST3#/ SCRCLK / GP11

DOD8Note2/ DOD8/ DIOD8

VCC

84

VDIMM_STR_ EN/ PCIRST4#/ SCRPSNT#/ GP10

DOD8/ DOD8Note2/ DI/ DIOD8

VCCH

Table 5-13. Pin Description of Keyboard Controller Signals

Pin(s) No. 80 Symbol KDAT/ GP61 Attribute DIOD24/ DIOD24 Power VCCH Description Keyboard Data/ General Purpose I/O 61. The first function of this pin is Keyboard Data. The second function of this pin is the General Purpose I/O Port 6 Bit 1. This set only supports Simple I/O function. The function configuration of this pin is determined by programming the software configuration registers. This pin doesnt support internal pull-up. Keyboard Clock/ General Purpose I/O 60. The first function of this pin is Keyboard Clock. The second function of this pin is the General Purpose I/O Port 6 Bit 0. This set only supports Simple I/O function. The function configuration of this pin is determined by programming the software configuration registers. This pin doesnt support internal pull-up.

81

KCLK/ GP60

DIOD24/ DIOD24

VCCH

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IT8726F V0.3

Pin Descriptions
Pin(s) No. 82 Symbol MDAT/ GP57 Attribute DIOD24/ DIOD24 Power VCCH Description PS/2 Mouse Data/ General Purpose I/O 57. The first function of this pin is PS/2 Mouse Data. The second function of this pin is the General Purpose I/O Port 5 Bit 7. The function configuration of this pin is determined by programming the software configuration registers. This pin doesnt support internal pull-up. PS/2 Mouse Clock/ General Purpose I/O 56. The first function of this pin is PS/2 Mouse Clock. The second function of this pin is the General Purpose I/O Port 5 Bit 6. The function configuration of this pin is determined by programming the software configuration registers. This pin doesnt support internal pull-up. Keyboard Reset #/ General Purpose I/O 62. The first function of this pin is Keyboard Reset #. The second function of this pin is the General Purpose I/O Port 6 Bit 2. This set only supports Simple I/O function. The function configuration of this pin is determined by programming the software configuration registers. Gate Address 20. During LRESET#, this pin is input for JP7 power-on strapping option

83

MCLK/ GP56

DIOD24/ DIOD24

VCCH

45

KRST#/ GP62

DO16/ DIOD16

VCC

46

GA20/ JP7

DO16/ DI

VCC

Table 5-14. Pin Description of Miscellaneous Signals

Pin(s) No. 49 72 Symbol CLKIN PWRON#/ GP44 Attribute DI DOD8/ DIOD8 Power VCC VCCH Description 24 or 48 MHz Clock Input. Power On Request Output # / General Purpose I/O44. The first function of this pin is Power On Request Output #. The second function of this pin is the General Purpose I/O Port 4 Bit 4. The function configuration of this pin is determined by programming the software configuration registers. Main Power Switch Button Input # / General Purpose I/O 43. The first function of this pin is Main Power Switch Button Input #. The second function of this pin is the General Purpose I/O Port 4 Bit 3. The function configuration of this pin is determined by programming the software configuration registers. Power Supply On-Off Output # / General Purpose I/O 42. The first function of this pin is Power Supply On-Off Control Output #. The second function of this pin is the General Purpose I/O Port 4 Bit 2. The function configuration of this pin is determined by programming the software configuration registers. SUSB # Input / General Purpose I/O 45. The first function of this pin is SUSB # Input. The second function of this pin is the General Purpose I/O Port 4 Bit 5. The function configuration of this pin is determined by programming the software configuration registers.

75

PANSWH#/ GP43

DI/ DIOD8

VCCH

76

PSON#/ GP42

DOD8/ DIOD8

VCCH

71

SUSB#/ GP45

DI/ DIOD8

VCCH

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IT8726F
Pin(s) No. 77 Symbol SUSC#/ GP53 Attribute DI/ DIOD8 Power VCCH Description SUSC# Input / General Purpose I/O 53. The first function of this pin is SUSC# Input. The second function of this pin is the General Purpose I/O Port 5 Bit 3. The function configuration of this pin is determined by programming the software configuration registers. Power OK 2 of VCC / General Purpose I/O 41. The first function of this pin is Power OK 2 of VCC. The second function of this pin is the General Purpose I/O Port 4 Bit 1. The function configuration of this pin is determined by programming the software configuration registers. 3VSBSW# / General Purpose I/O 40. The first function of this pin is 3VSBSW#. The second function of this pin is the General Purpose I/O Port 4 Bit 0. The function configuration of this pin is determined by programming the software configuration registers.

78

PWROK2/ GP41

DOD8/ DIOD8

VCCH

79

3VSBSW#/ GP40

DO8/ DIOD8

VCCH

Note 1: In addition to providing a highly integrated chip, ITE has also implemented a SmartGuardian Utility for hardware monitor application, providing a total solution for customers. The SmartGuardian Utility and the application circuit of hardware monitor function (the function arrangement of VIN0-7, TMPIN1-3, FAN_TAC13 and FAN_CTL1-3) are interdependent. That is to say, the SmartGuardian Utility is programmed according to the application circuit of hardware monitor function. ITE strongly recommends customers to follow the referenced application circuit of IT8726F to reduce the time-to-market schedule. Pin No. 98 97 96 95 94 93 92 91 Symbol VIN0 VIN1 VIN2 VIN3 VIN4 VIN5 VIN6 VIN7 Recommended function arrangement 2 Volt for VCORE1 of CPU 2 Volt for VCORE2 of CPU 3.3 Volt for system 5 Volt for system +12 Volt for system -12 Volt for system -5 Volt for system 5 Volt for VCCH

Note 2: If the power-on strapping input JP4 is low, the output attributes of these pins will be push-pull. IO Cell: DO8: 8mA Digital Output buffer DOD8: 8mA Digital Open-Drain Output buffer DO16: 16mA Digital Output buffer DO24: 24mA Digital Output buffer DO24L: 24mA shink/8mA drive Digital Output buffer DIO8: 8mA Digital Input/Output buffer DIOD8: 8mA Digital Open-Drain Input/Output buffer DIO16: 16mA Digital Input/Output buffer DIOD16: 16mA Digital Open-Drain Input/Output buffer DIO24: 24mA Digital Input/Output buffer DIOD24: 24mA Digital Open-Drain Input/Output buffer DI: Digital Input AI: Analog Input www.ite.com.tw 22 IT8726F V0.3

Pin Descriptions
AO: Analog Output

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IT8726F V0.3

List of GPIO Pins

6. List of GPIO Pins
Table 6-1. General Purpose I/O Group 1 (Set 1)
Pin(s) No. 84 Symbol VDIMM_STR_EN/ PCIRST4#/ SCRPSNT#/ GP10 PCIRST3#/ SCRCLK/ GP11 PCIRST2#/ SCRIO/ GP12 PWROK1/ SCRPFET#/ GP13 PCIRST1#/ SCRRST/ GP14 RESETCON#/ CIRTX/ CE_N MIDI_IN/ GP16/ SO2 MIDI_OUT/ GP17 Attribute DOD8/ DOD8/ DI/ DIOD8 DOD8/ DOD8/ DIOD8 DOD8/ DIOD8/ DIOD8 DOD8/ DOD8/ DIOD8 DOD8/ DOD8/ DIOD8 DI/ DOD8/ DOD8/ DI/ DIOD8/ DI DO8/ DIOD8 Description VDIMM_STR enable / PCI Reset 4 # / Smart Card Present Detect # / General Purpose I/O 10.

34

PCI Reset 3 # / Smart Card Clock / General Purpose I/O 11.

33

PCI Reset 2 # / Smart Card Serial Data I/O / General Purpose I/O 12.

32

Power OK 1 of VCC / Smart Card Power FET Control Output # / General Purpose I/O 13. PCI Reset 1 # /Smart Card Reset / General Purpose I/O 14.

31

30

Reset Connect # /Consumer Infrared Transmit Output /Serial Flash Chip Enable# MIDI Input / General Purpose I/O 16 / Serial Flash Output Data 2.

29

28

MIDI Output / General Purpose I/O 17.

Table 6-2. General Purpose I/O Group 2 (Set 2)

Pin(s) No. 27 Symbol VIDO0/ JSACX/ GP20 VIDO1/ JSACY/ GP21 JSAB1/ GP22/ SCK JSAB2/ GP23/ SI VIDO2/ FAN_TAC5/ JSBCX/ GP24 VIDO3/ FAN_TAC4/ JSBCY/ GP25 VIDO4/ FAN_CTL5/ JSBB1/ GP26 Attribute DOD8/ DIOD8/ DIOD8 DOD8/ DIOD8/ DIOD8 DI/ DIOD8/ DO DI/ DIOD8/ DO DOD8/ DI/ DIOD8/ DIOD8 DOD8/ DI/ DIOD8/ DIOD8 DOD8/ DOD8/ DI/ DIOD8 Description VID out 0 / Joystick A Coordinate X / General Purpose I/O 20.

26

VID out 1 / Joystick A Coordinate Y / General Purpose I/O 21.

25

Joystick A Button 1 / General Purpose I/O 2 / Serial Flash Clock.

24

Joystick A Button 2 / General Purpose I/O 23 / Serial Flash In Data.

23

VID out 2 / FAN Tachometer input 5 /Joystick B Coordinate X / General Purpose I/O 24.

22

VID out 3 / FAN Tachometer input 4 /Joystick B Coordinate Y / General Purpose I/O 25.

21

VID out 4 / FAN_CTL 5 / Joystick B Button 1 / General Purpose I/O 26.

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IT8726F
Pin(s) No. 20 Symbol VIDO5/ FAN_CTL4/ JSBB2/ GP27 Attribute DOD8/ DOD8/ DI/ DIOD8 Description VID out 5 / FAN_CTL 4 / Joystick B Button 2 / General Purpose I/O 27.

Table 6-3. General Purpose I/O Group 3 (Set 3)

Pin(s) No. 19 18 17 16 14 13 12 11 Symbol VID0/ GP30 VID1/ GP31 VID2/ GP32 VID3/ GP33 VID4/ GP34 VID5/ GP35 FAN_CTL3/ GP36 FAN_TAC3/ GP37 Attribute DIO8/ DIOD8 DIO8/ DIOD8 DIO8/ DIOD8 DIO8/ DIOD8 DIO8/ DIOD8 DIO8/ DIOD8 DOD8/ DIOD8 DI/ DIOD8 Description Voltage ID 0 / General Purpose I/O 30. Voltage ID 1 / General Purpose I/O 31. Voltage ID 2 / General Purpose I/O 32. Voltage ID 3 / General Purpose I/O 33. Voltage ID 4 / General Purpose I/O 34. Voltage ID 5 / General Purpose I/O 35. Fan Control Output 3 / General Purpose I/O 36. Fan Tachometer Input 3 / General Purpose I/O 37.

Table 6-4. General Purpose I/O Group 4 (Set 4)

Pin(s) No. 79 78 76 75 72 71 70 66 Symbol 3VSBSW#/ GP40 PWROK2/ GP41 PSON#/ GP42 PANSWH#/ GP43 PWRON#/ GP44 SUSB#/GP45 GP46/IRRX IRTX/ GP47 Attribute DOD8/ DIOD8 DOD8/ DIOD8 DOD8/ DIOD8 DI/ DIOD8 DOD8/ DIOD8 DI/DIOD8 DIOD8/ DI DO8/ DIOD8 Description 3VSBSW# / General Purpose I/O 40. Power OK 2 of VCC / General Purpose I/O 41. Power Supply On-Off Control Output # / General Purpose I/O 42. Main Power Switch Button Input # / General Purpose I/O 43. Power On Request Output # / General Purpose I/O 44. SUSB # Input / General Purpose I/O 45. General Purpose I/O 46 / Infrared Receive Input. Infrared Transmit Output / General Purpose I/O 47.

Table 6-5. General Purpose I/O Group 5 (Set 5)

Pin(s) No. 48 10 9 77 73 Symbol PCIRST5#/ GP50 FAN_CTL2/ GP51 FAN_TAC2/ GP52 SUSC#/ GP53 PME#/ GP54 Attribute DO8/ DIOD16 DOD8/ DIOD8 DI/DIOD8 DI/ DIOD8 DOD8/ DIOD8 Description PCIRST5#/ General Purpose I/O 50. Fan Control Output 2 / General Purpose I/O 51. Fan Tachometer Input 2 / General Purpose I/O 52. SUSC# Input / General Purpose I/O 53 Power Management Event # / General Purpose I/O 54.

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IT8726F V0.3

List of GPIO Pins

Pin(s) No. 85 Symbol RSMRST#/ CIRRX/ GP55 MCLK/ GP56 MDAT/ GP57 Attribute DOD8/ DI/ DIOD8 DIOD24/ DIOD24 DIOD24/ DIOD24 Description Resume Reset # / Consumer Infrared Receive Input / General Purpose I/O 55. PS/2 Mouse Clock / General Purpose I/O 56. PS/2 Mouse Data / General Purpose I/O 57.

83 82

Table 6-6. General Purpose I/O Group 6 (Set 6)

Pin(s) No. 81 80 45 6 Symbol KCLK/ GP60 KDAT/ GP61 KRST#/ GP62 VCORE_GD/ SIN2/ GP63 VCORE_EN/ DSR2#/ GP64 VDDA_EN/ CTS2#/ GP65 VLDT_EN/ RI2#/ GP66 CPU_PG/ DCD2#/ GP67 Attribute DIOD24/ DIOD24 DIOD24/ DIOD24 DO16/ DIOD16 DI/ DI/ DIOD8 DOD8/ DI/ DIOD8 DOD8/ DI/ DIOD8 DOD8/ DI/ DIOD8 DOD16/ DI/ DIOD8 Description Keyboard Clock/ General Purpose I/O 60. Keyboard Data/ General Purpose I/O 61. Keyboard Reset/ General Purpose I/O 62. VCORE Power-Good/ Serial Data In 2/ General Purpose I/O 63.

VCORE Enable/ Data Set Ready 2 #/ General Purpose I/O 64.

128

VDDA Enable/ Clear to Send 2 #/ General Purpose I/O 65.

127

VLDT Enable/ Ring Indicator 2 #/ General Purpose I/O 66.

126

CPU Power-Good/ Data Carrier Detect 2 #/ General Purpose I/O 67.

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IT8726F

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Power on Strapping Options

7. Power On Strapping Options and Special Pin Routings
Table 7-1. Power On Strapping Options Symbol JP1 Pin-121 JP2 Pin-122 JP3 Pin-124 JP4 Pin-1 Flashseg1_EN Value 1 0 1 0 -1 0 11 [JP5, JP7] Pin-2, Pin-46 FAN_CTL_SEL 10 01 00 JP6 Pin-5 JP7 Pin-46 JP8 Pin-38 VID_ISEL 1 0 1 0 1 0 Disabled Flash I/F Address Segment FFF8_0000~FFFF_FFFF & 000E_0000~000F_FFFF is enabled. FLH_SO2 is selected as the Serial Flash I/F SO pin. FLH_SO1 is selected as the Serial Flash I/F SO pin. Chip selection in configuration. The output buffers of PCIRST1#, PCIRST2#, PCIRST3#, PCIRST4# and PCIRST5# are open-drain. The output buffers are push-pull. The default value of EC Index 15h/16h/17h is 00h. The default value of EC Index 15h/16h/17h is 20h The default value of EC Index 15h/16h/17h is 40h. The default value of EC Index 15h/16h/17h is 60h. The threshold voltage of VID is 2.0/0.8V. The threshold voltage of VID is 0.8/0.4V. Disable WDT to reset PWROK Enable WDT to reset PWROK Disable VID output pins Enable VID output pins Description

SerFlh_SO_SEL CHIP_SEL

BUF_SEL

WDT_EN

VIDO_EN

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IT8726F
Intel ICH PWBTN# VCCH SUSC# SUSB#

PWRON# SUSC# SUSB# (71) (77) (72) System On-Off Button PANSWH# (75) 3 VSBSW#(79) IT8726F

To switch Suspend to - RAM power ATX Power Supply PSON#

PSON#(76)

Figure 7-1. IT8726F Special Applications Circuitry for Intel ICH

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IT8726F V0.3

Configuration
8. Configuration
8.1 Configuring Sequence Description

After the hardware reset or power-on reset, IT8726F enters the normal mode with all logical devices disabled except KBC. The initial state (enable bit) of this logical device (KBC) is determined by the state of pin 121 (DTR1#) at the falling edge of the system reset during power-on reset.

Hardware Reset

Any other I/O transition cycle

Wait for key string

I/O write to 2Eh

N
Is the data "87h" ?

Y
Check Pass key

Any other I/O transition cycle

I/O write to 2Eh

N
Next Data?

Last Data?

Y
MB PnP Mode

There are three steps to completing the configuration setup: (1) Enter the MB PnP Mode; (2) Modify the data of configuration registers; (3) Exit the MB PnP Mode. Undesired result may occur if the MB PnP Mode is not exited normally. (1) Enter the MB PnP Mode To enter the MB PnP Mode, four special I/O write operations are to be performed during Wait for Key state. To ensure the initial state of the key-check logic, it is necessary to perform four write operations to the Special Address port (2Eh). Two different enter keys are provided to select configuration ports (2Eh/2Fh or 4Eh/4Fh) of the next step. 87h, 01h, 55h, 55h; or 87h, 01h, 55h, AAh; Address port Data port 2Eh 2Fh 4Eh 4Fh

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IT8726F
(2) Modify the Data of the Registers All configuration registers can be accessed after entering the MB PnP Mode. Before accessing a selected register, the content of Index 07h must be changed to the LDN to which the register belongs, except some Global registers. (3) Exit the MB PnP Mode Set bit 1 of the configure control register (Index=02h) to 1 to exit the MB PnP Mode.

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Configuration
8.2 Description of the Configuration Registers

All the registers except APC/PME registers will be reset to the default state when RESET is activated. Table 8-1. Global Configuration Registers LDN All All All All All All All 07h 07h 07h 07h 07h 07h 07h F4h F4h
Note1 Note1 Note1 Note1 Note1 Note1

Index 02h 07h 20h 21h 22h 23h 24h 25h 26h 27h 28h 29h 2Ah 2Bh 2Ch 2Eh 2Fh

R/W W R/W R R W-R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W

Reset NA NA 87h 16h 01h 00h 00h 01h 00h 00h 40h 00h 00h 00h 00h 00h 00h

Configuration Register or Action Configure Control Logical Device Number (LDN) Chip ID Byte 1 Chip ID Byte 2 Configuration Select and Chip Version Clock Selection Register Software Suspend and Flash I/F Control Register GPIO Set 1 Multi-Function Pin Selection Register GPIO Set 2 Multi-Function Pin Selection Register GPIO Set 3 Multi-Function Pin Selection Register GPIO Set 4 Multi-Function Pin Selection Register GPIO Set 5 Multi-Function Pin Selection Register Extended 1 Multi-Function Pin Selection Register Logical Block Configuration Lock Register Extended 2 Multi-Function Pin Selection Register Test 1 Register Test 2 Register

All
Note1 Note1 Note1

Table 8-2. FDC Configuration Registers LDN 00h 00h 00h 00h 00h 00h 00h Index 30h 60h 61h 70h 74h F0h F1h R/W R/W R/W R/W R/W R/W R/W R/W Reset 00h 03h F0h 06h 02h 00h 00h Configuration Register or Action FDC Activate FDC Base Address MSB Register FDC Base Address LSB Register FDC Interrupt Level Select FDC DMA Channel Select FDC Special Configuration Register 1 FDC Special Configuration Register 2

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IT8726F
Table 8-3. Serial Port 1 Configuration Registers LDN 01h 01h 01h 01h 01h 01h 01h 01h Index 30h 60h 61h 70h F0h F1h F2h F3h R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset 00h 03h F8h 04h 00h 50h 00h 7Fh Configuration Register or Action Serial Port 1 Activate Serial Port 1 Base Address MSB Register Serial Port 1 Base Address LSB Register Serial Port 1 Interrupt Level Select Serial Port 1 Special Configuration Register 1 Serial Port 1 Special Configuration Register 2 Serial Port 1 Special Configuration Register 3 Serial Port 1 Special Configuration Register 4

Table 8-4. Serial Port 2 Configuration Registers LDN 02h 02h 02h 02h 02h 02h 02h 02h Index 30h 60h 61h 70h F0h F1h F2h F3h R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset 00h 02h F8h 03h 00h 50h 00h 7Fh Configuration Register or Action Serial Port 2 Activate Serial Port 2 Base Address MSB Register Serial Port 2 Base Address LSB Register Serial Port 2 Interrupt Level Select Serial Port 2 Special Configuration Register 1 Serial Port 2 Special Configuration Register 2 Serial Port 2 Special Configuration Register 3 Serial Port 2 Special Configuration Register 4

Table 8-5. Parallel Port Configuration Registers LDN 03h 03h 03h 03h 03h 03h 03h 03h Index 30h 60h 61h 62h 63h 70h 74h F0h R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset 00h 03h 78h 07h 78h 07h 03h 03h Note3 Configuration Register or Action Parallel Port Activate Parallel Port Primary Base Address MSB Register Parallel Port Primary Base Address LSB Register Parallel Port Secondary Base Address MSB Register Parallel Port Secondary Base Address LSB Register Parallel Port Interrupt Level Select Parallel Port DMA Channel Select Note2 Parallel Port Special Configuration Register

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IT8726F V0.3

Configuration
Table 8-6. Environment Controller Configuration Registers LDN 04h 04h 04h 04h 04h 04h 04h 04h 04h 04h 04h 04h 04h Index 30h 60h 61h 62h 63h 70h F0h F1h F2h F3h F4h F5h F6h R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R-R/W R/W R/W Reset 00h 02h 90h 02h 30h 09h 00h 00h 00h 00h 00h Configuration Register or Action Environment Controller Activate Environment Controller Base Address MSB Register Environment Controller Base Address LSB Register PME Direct Access Base Address MSB Register PME Direct Access Base Address LSB Register Environment Controller Interrupt Level Select APC/PME Event Enable Register APC/PME Status Register APC/PME Control Register 1 Environment Controller Special Configuration Register APC/PME Control Register 2 APC/PME Special Code Index Register APC/PME Special Code Data Register

Table 8-7. KBC(Keyboard) Configuration Registers LDN 05h 05h 05h 05h 05h 05h 05h 05h Index 30h 60h 61h 62h 63h 70h 71h F0h R/W R/W R/W R/W R/W R/W R/W R-R/W R/W Reset 01h 00h 60h 00h 64h 01h 02h 00h Configuration Register or Action KBC Activate KBC Data Base Address MSB Register KBC Data Base Address LSB Register KBC Command Base Address MSB Register KBC Command Base Address LSB Register KBC Interrupt Level Select KBC Interrupt Type Note5 KBC Special Configuration Register

Table 8-8. KBC(Mouse) Configuration Registers LDN 06h 06h 06h 06h Index 30h 70h 71h F0h R/W R/W R/W R-R/W R/W Reset 00h 0Ch 02h 00h Configuration Register or Action KBC (Mouse) Activate KBC (Mouse) Interrupt Level Select KBC (Mouse) Interrupt Type Note5 KBC (Mouse) Special Configuration Register

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IT8726F
Table 8-9. GPIO Configuration Registers LDN 07h 07h 07h 07h 07h 07h 07h 07h 07h 07h 07h 07h 07h 07h 07h 07h 07h 07h 07h 07h 07h 07h 07h 07h 07h 07h 07h 07h 07h 07h 07h 07h 07h Index 60h 61h 62h 63h 64h 65h 70h 71h 72h 73h 74h B0h B1h B2h B3h B4h B5h B8h B9h BAh BBh BCh BDh C0h C1h C2h C3h C4h C8h C9h CAh CBh CCh R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Reset 00h 00h 00h 00h 00h 00h 00h 00h 38h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 01h 00h 00h 40h 00h 01h 00h 00h 40h 00h Configuration Register or Action SMI# Normal Run Access Base Address MSB Register SMI# Normal Run Access Base Address LSB Register Simple I/O Base Address MSB Register Simple I/O Base Address LSB Register Serial Flash I/F Base Address MSB Register Serial Flash I/F Base Address LSB Register Panel Button De-bounce Interrupt Level Select Register Watch Dog Timer Control Register Watch Dog Timer Time-out Value (LSB) Register Watch Dog Timer Time-out Value (MSB) Register GPIO Set 1 Pin Polarity Register GPIO Set 2 Pin Polarity Register GPIO Set 3 Pin Polarity Register GPIO Set 4 Pin Polarity Register GPIO Set 5 Pin Polarity Register GPIO Set 6 Pin Polarity Register GPIO Set 1 Pin Internal Pull-up Enable Register GPIO Set 2 Pin Internal Pull-up Enable Register GPIO Set 3 Pin Internal Pull-up Enable Register GPIO Set 4 Pin Internal Pull-up Enable Register GPIO Set 5 Pin Internal Pull-up Enable Register GPIO Set 6 Pin Internal Pull-up Enable Register Simple I/O Set 1 Enable Register Simple I/O Set 2 Enable Register Simple I/O Set 3 Enable Register Simple I/O Set 4 Enable Register Simple I/O Set 5 Enable Register Simple I/O Set 1 Output Enable Register Simple I/O Set 2 Output Enable Register Simple I/O Set 3 Output Enable Register Simple I/O Set 4 Output Enable Register Simple I/O Set 5 Output Enable Register

001S0000b Watch Dog Timer Configuration Register

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Configuration
Table 8-9. GPIO Configuration Registers [contd] LDN 07h 07h 07h 07h 07h 07h 07h 07h 07h 07h 07h 07h 07h 07h 07h 07h 07h 07h 07h Index E0h E1h E2h E3h E4h F0h F1h F2h F3h F4h F5h F6h F7h F8h F9h FAh FBh FCh FDh R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W-R R/W Reset 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h --h 00h Configuration Register or Action Panel Button De-bounce 0 Input Pin Mapping Register Panel Button De-bounce 1 Input Pin Mapping Register IRQ External Routing 0 Input Pin Mapping Register IRQ External Routing 1 Input Pin Mapping Register IRQ External Routing 1-0 Interrupt Level Selection Register SMI# Control Register 1 SMI# Control Register 2 SMI# Status Register 1 SMI# Status Register 2 SMI# Pin Mapping Register Hardware Monitor Thermal Output Pin Mapping Register Hardware Monitor Alert Beep Pin Mapping Register Keyboard Lock Pin Mapping Register GP LED Blinking 1 Pin Mapping Register GP LED Blinking 1 Control Register GP LED Blinking 2 Pin Mapping Register GP LED Blinking 2 Control Register VID Input Register VID Output Register

Table 8-10. MIDI Port Configuration Registers LDN 08h 08h 08h 08h 08h Index 30h 60h 61h 70h F0h R/W R/W R/W R/W R/W R/W Reset 00h 03h 00h 0Ah 00h Configuration Register or Action MIDI Port Activate MIDI Port Base Address MSB Register MIDI Port Base Address LSB Register MIDI Port Interrupt Level Select MIDI Port Special Configuration Register

Table 8-11. Game Port Configuration Registers LDN 09h 09h 09h Index 30h 60h 61h R/W R/W R/W R/W Reset 00h 02h 01h Configuration Register or Action Game Port Activate Game Port Base Address MSB Register Game Port Base Address LSB Register

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IT8726F
Table 8-12. Consumer IR Configuration Registers LDN 0Ah 0Ah 0Ah 0Ah 0Ah Index 30h 60h 61h 70h F0h R/W R/W R/W R/W R/W R/W Reset 00h 03h 10h 0Bh 00h Configuration Register or Action Consumer IR Activate Consumer IR Base Address MSB Register Consumer IR Base Address LSB Register Consumer IR Interrupt Level Select Consumer IR Special Configuration Register

Note 1: All these registers can be read from all LDNs. Note 2: When the ECP mode is not enabled, this register is read only as 04h, and cannot be written. Note 3: When the bit 2 of the Primary Base Address LSB Register of Parallel Port is set to 1, the EPP mode cannot be enabled. Bit 0 of this register is always 0. Note 4: These registers are read only unless the write enable bit (Index=F0h) is asserted. 8.2.1 Logical Device Base Address

The base I/O range of logical devices shown below is located in the base I/O address range of each logical device. Table 8-13. Base Address of Logical Devices Logical Devices LDN=0 FDC LDN=1 SERIAL PORT 1 LDN=2 SERIAL PORT 2 fLDN=3 PARALLEL PORT Address Base + (2 - 5) and + 7 Base + (0 -7) Base1 + (0 -7) Base1 + (0 -3) Base1 + (0 -7) Base1 + (0 -3) and Base2 + (0 -3) Base1 + (0 -7) and Base2 + (0 -3) Base3 LDN=4 Environment Controller LDN=5 KBC LDN=8 MIDI port LDN=9 Game Port LDN=A Consumer IR Base1 + (0 -7) Base2 + (0 -3) Base1 + Base2 Base + (0 -1) Base Base + (0 -7) COM port SPP SPP+EPP SPP+ECP SPP+EPP+ECP POST data port Environment Controller PME# KBC Notes

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Configuration
8.3 8.3.1 Global Configuration Registers (LDN: All) Configure Control (Index=02h)

This register is write only. Its values are not sticky; that is to say, a hardware reset will automatically clear the bits, and does not require the software to clear them. Bit 7-2 1 0 8.3.2 Description Reserved Returns to the Wait for Key state. This bit is used when the configuration sequence is completed. Resets all logical devices and restores configuration registers to their power-on states. Logical Device Number (LDN, Index=07h)

This register is used to select the current logical devices. By reading from or writing to the configuration of I/O, Interrupt, DMA and other special functions, all registers of the logical devices can be accessed. In addition, ACTIVATE command is only effective for the selected logical devices. This register is read/write. 8.3.3 Chip ID Byte 1 (Index=20h, Default=87h)

This register is the Chip ID Byte 1 and is read only. Bits [7:0]=87h when read. 8.3.4 Chip ID Byte 2 (Index=21h, Default=16h)

This register is the Chip ID Byte 2 and is read only. Bits [7:0]=16h when read. 8.3.5 Bit 7 Configuration Select and Chip Version (Index=22h, Default=01h) Description Configuration Select This bit is used to select the chip, which needs to be configured. When there are two IT8726F chips in a system, and a 1 is written, this bit will select JP3=1 (power-on strapping value of SOUT1) to be configured. The chip with JP3=0 will exit the configuration mode. To write 0, the chip with JP3=0 will be configured and the chip with JP3=0 will exit. If no write operations occur on this register, both chips will be configured. Reserved Version 0000b for C version 0001b for D version Clock Selection Register (Index=23h, Default=00h) Description XLOCK select These two bits determine XLOCK function. 00: Software XLOCK (default) 01: Reserved 10: Pin 48 (GP50) 11: Pin 11 (GP37) Reserved 39 IT8726F V0.3

6-4 3-0

8.3.6 Bit 7-6

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IT8726F
Bit 4 Description Clock Source Select of Watch Dog Timer 0: Internal oscillating clock (default) 1: External CLKIN Selects the delay of PWROK1/2. 00: POWOK1/2 will be delayed 300 ~600ms from VCC5V > 4.0V. 01: POWOK1/2 will be no delay from VCC5V > 4.0V. 10: POWOK1/2 will be delayed 150 ~300ms from VCC5V > 4.0V. 11: Reserved. Reserved CLKIN Frequency 0: 48 MHz 1: 24 MHz Software Suspend and Flash I/F Control Register (Index=24h, Default=0000s0s0b, MB PnP) Description Reserved Serial Flash I/F SO Selection 0: Pin 29 1: Pin 87 LPC Memory/FWM write to Serial Flash I/F Enable 0: Disable (default) 1: Enable Flash I/F Address Segment 3 (FFF8_0000h-FFFD_FFFFh, FFFE_0000h-FFFE_FFFFh) 0: Disable 1: Enable Flash I/F Address Segment 2 (FFEF_0000h-FFEF_FFFFh, FFEE_0000h-FFEE_FFFFh) 0: Disable (default) 1: Enable Flash I/F Address Segment 1 (FFFE_0000h_FFFF_FFFFh, 000E_0000h-000F_FFFFh) 0: Disable 1: Enable Software Suspend This register is the Software Suspend register. When the bit 0 is set, the IT8726F enters the Software Suspend state. All the devices, except KBC, remain inactive until this bit is cleared or when the wake-up event occurs. The wake-up event occurs at any transition on signals RI1# (pin 119) and Rl2# (pin 127). 0: Normal. 1: Software Suspend.

3-2

1 0

8.3.7 Bit 7-6 5 4 3 2 1

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Configuration
8.3.8 GPIO Set 1 Multi-Function Pin Selection Register (Index=25h, Default=01h)

If the enabled bits are not set, the multi-function pins will perform the original functions. On the other hand, if they are set, they will perform the GPIO functions. This register can be read from any LDN, but can only be written if LDN=07h. Bit 7 Description Function Selection of pin 28 0: MIDI Output (MIDI_OUT) 1: General Purpose I/O 17 (GP17) Function Selection of pin 29 0: MIDI Input (MIDI_IN) 1: General Purpose I/O 16 (GP16) Function Selection of pin 30, if bit5 of index 2A is 1. 0: Consumer Infrared Transmit Output (CIRTX) 1: General Purpose I/O 15 (GP15) Function Selection of pin 31, if bit4 of index 2A is 1. 0: Smart Card Reset (SCRRST) 1: General Purpose I/O 14 (GP14) Function Selection of pin 32, if bit3 of index 2A is 1. 0: Smart Card Power FET Control Output # 1: General Purpose I/O 13 (GP13) Function Selection of pin 33, if bit2 of index 2A is 1. 0: Smart Card Serial Data I/O (SCRIO) 1: General Purpose I/O 12 (GP12) Function Selection of pin 34, if bit1 of index 2A is 1. 0: Smart Card Clock (SCRCLK) 1: General Purpose I/O 11 (GP11) Function Selection of pin 84, if bit0 of index 2A is 1. 0: Smart Card Present Detect# (SCRPSNT#) 1: General Purpose I/O 10 (GP10) PIO Set 2 Multi-Function Pin Selection Register (Index=26h, Default=00h)

8.3.9

If the enabled bits are not set, the multi-function pins will perform the original functions. On the other hand, if they are set, they will perform the GPIO functions. This register can be read from any LDN, but can only be written if LDN=07h. Bit 7 Description Function Selection of pin 20 0: Joystick B Button 2 (JSBB2) 1: General Purpose I/O 27 (GP27) Function Selection of pin 21 0: Joystick B Button 1 (JSBB1) 1: General Purpose I/O 26 (GP26) Function Selection of pin 22 0: Joystick B Coordinate Y (JSBCY) 1: General Purpose I/O 25 (GP25) Function Selection of pin 23 0: Joystick B Coordinate X (JSBCX) 1: General Purpose I/O 24 (GP24)

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IT8726F
3 Function Selection of pin 24 0: Joystick A Button 2 (JSAB2) 1: General Purpose I/O 23 (GP23) Function Selection of pin 25 0: Joystick A Button 1 (JSAB1) 1: General Purpose I/O 22 (GP22) Function Selection of pin 26 0: Joystick A Coordinate Y (JSACY) 1: General Purpose I/O 21 (GP21) Function Selection of pin 27 0: Joystick A Coordinate X (JSACX) 1: General Purpose I/O 20 (GP20) GPIO Set 3 Multi-Function Pin Selection Register (Index=27h, Default=00h)

8.3.10

If the enabled bits are not set, the multi-function pins will perform the original functions. On the other hand, if they are set, they will perform the GPIO functions. This register can be read from any LDN, but can only be written if LDN=07h. Bit 7 Description Function Selection of pin 11 0: Fan Tachometer Input 3 (FAN_TAC3) 1: General Purpose I/O 37 (GP37) Function Selection of pin 12 0: Fan Control Output 3 (FAN_CTL3) 1: General Purpose I/O 36 (GP36) Function Selection of pin 13 0: Voltage ID5 (VID5) 1: General Purpose I/O 35 (GP35) Function Selection of pin 14 0: Voltage ID4 (VID4) 1: General Purpose I/O 34 (GP34) Function Selection of pin 16 0: Voltage ID3 (VID3) 1: General Purpose I/O 33 (GP33) Function Selection of pin 17 0: Voltage ID2 (VID2) 1: General Purpose I/O 32 (GP32) Function Selection of pin 18 0: Voltage ID1 (VID1) 1: General Purpose I/O 31 (GP31) Function Selection of pin 19 0: Voltage ID0 (VID0) 1: General Purpose I/O 30 (GP30)

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Configuration
8.3.11 GPIO Set 4 Multi-Function Pin Selection Register (Index=28h, Default=40h)

If the enabled bits are not set, the multi-function pins will perform the original functions. On the other hand, if they are set, they will perform the GPIO functions. This register can be read from any LDN, but can only be written if LDN=07h. Bit 7 Description Function Selection of pin 66 0: Infrared Transmit Output (IRTX). 1: General Purpose I/O 47 (GP47). Function Selection of pin 70 0: Infrared Receive Input (IRRX). 1: General Purpose I/O 46 (GP46). Function Selection of pin 71 0: SUSB#. 1: General Purpose I/O 45 (GP45). Function Selection of pin 72 0: Power On Request Output # (PWRON#). 1: General Purpose I/O 44 (GP44). Function Selection of pin 75 0: Main Power Switch Button Input # (PANSWH#). 1: General Purpose I/O 43 (GP43). Function Selection of pin 76 0: Power Supply ON-Off Control Output # (PSON#). 1: General Purpose I/O 42 (GP42). Function Selection of pin 78 0: PWROK2. 1: General Purpose I/O 41 (GP41). Function Selection of pin 79 0: 3VSBSW#. 1: General Purpose I/O 40 (GP40). GPIO Set 5 Multi-Function Pin Selection Register (Index=29h, Default=00h)

8.3.12

If the enabled bits are not set, the multi-function pins will perform the original functions. On the other hand, if they are set, they will perform the GPIO functions. This register can be read from any LDN, but can only be written if LDN=07h. Bit 7 Description Function Selection of pin 6, 3, 128,127, 126. 0: SIN2, DSR2#, CTS2#, RI2, DCD2#. 1: General Purpose I/O 63, 64, 65, 66, 67. Function Selection of pin 83, 82, 81, 80, 45. 0: MCLK, MDAT, KCLK, KDAT, KRST#. 1: General Purpose I/O 56, 57, 60, 61, 62. Function Selection of pin 85. 0: Consumer Infrared Receive Input (CIRRX) or RSMRST#. RSMRST# is an open-drain output function, which is active low about 16ms when VCCH5V is power-on. 1: General Purpose I/O 55 (GP55). Function Selection of pin 73. 0: Power Management Event # (PME#). 1: General Purpose I/O 54 (GP54). 43 IT8726F V0.3

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IT8726F
Bit 3 Description Function Selection of pin 77. 0: SUSC#. 1: General Purpose I/O 53 (GP53). Function Selection of pin 9. 0: Fan Tachometer Input 2 (FAN_TAC2). 1: General Purpose I/O 52 (GP52). Function Selection of pin 10. 0: Fan Control Output 2 (FAN_CTL2). 1: General Purpose I/O 51 (GP51). Function Selection of pin 48. 0: PCIRST5#, selected by bit2 of index 2C. 1: General Purpose I/O 50 (GP50). Extended 1 Multi-Function Pin Selection Register (Index=2Ah, Default=00h)

8.3.13

This register can be read from any LDN, but can only be written if LDN=07h. Bit 7 Description Enable 3VSBSW#. (For System Suspend-to-RAM) 0: 3VSBSW# will be always inactive. 1: 3VSBSW# enabled. It will be (NOT SUSB#) NAND SUSC#. Multi-function selection of pin 53. 0: MTRB#. 1: Reserved. (EC index 0Ah/bit6=1 external thermal sensor host enable, pin-53 swap to ETS_DAT function.) Extended multi-function selection of 30. 0: RESETCON#. 1: Determined by bit5 of GPIO Set 1 Multi-function Selection Register (Index 25h). Extended multi-function selection of pin 31. 0: PCIRST1#. 1: Determined by bit4 of GPIO Set 1 Multi-function Selection Register (Index 25h). Extended multi-function selection of pin 32. 0: PWROK1. 1: Determined by bit3 of GPIO Set 1 Multi-function Selection Register (Index 25h). Extended multi-function selection of pin 33. 0: PCIRST2#. 1: Determined by bit2 of GPIO Set 1 Multi-function Selection Register (Index 25h). Extended multi-function selection of pin 34. 0: PCIRST3#. 1: Determined by bit1 of GPIO Set 1 Multi-function Selection Register (Index 25h). Extended multi-function selection of pin 84. 0: PCIRST4#. 1: Determined by bit0 of GPIO Set 1 Multi-function Selection Register (Index 25h).

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Configuration
8.3.14 Logical Block Lock Register (Index=2Bh, Default=00h)

When lock function is enabled (bit7=1 or XLOCK# is low), configuration registers of the selected logical block and Clock Selection register (index = 23h), and this register will be read-only. Bit 7 Description Software Lock Enable. Once this bit is set to 1 by software, it can be only cleared by hardware reset. 0: Configuration lock is controlled by XLOCK#. (Default) 1: Configuration registers Logic Blocks selected by bits 6-0 and this register is read-only. GPIO Select. (LDN7) 0: GPIO Configuration registers are programmable. 1: GPIO Configuration registers are read-only if LOCK is enabled. KBC (Keyboard) and KBC (Mouse) Select. (LDN5 and LDN6) 0: KBC (Keyboard) and KBC (Mouse) Configuration registers are programmable. 1: KBC (Keyboard) and KBC (Mouse) Configuration registers are read-only if LOCK is enabled. EC Select. (LDN4) 0: EC Configuration registers are programmable. 1: EC Configuration registers are read-only if LOCK is enabled. Parallel Port Select. (LDN3) 0: Parallel Port Configuration registers are programmable. 1: Parallel Port Configuration registers are read-only if LOCK is enabled. Serial Port 2 Select. (LDN2) 0: Serial Port 2 Configuration registers are programmable. 1: Serial Port 2 Configuration registers are read-only if LOCK is enabled. Serial Port 1 Select. (LDN1) 0: Serial Port 1 Configuration registers are programmable. 1: Serial Port 1 Configuration registers are read-only if LOCK is enabled. FDC Select. (LDN0) The lock function will not affect bit0 of FDC Special Configuration register (software write protect). 0: FDC Configuration registers are programmable. 1: FDC Configuration registers are read-only (except Software Write Protect bit) if LOCK is enabled. Extended 2 Multi-Function Pin Selection Register (Index=2Ch, Default=1Fh)

8.3.15

This register can be read from any LDN, but can only be written if LDN=07h. Bit 7 6 Description Reserved (Do not program to 1.) AMD CPU Power Sequence Function Enable. 0: Enable. 1: Disable. Reserved Extended multi-function selection of pin 21, 23. 0: Disable FAN_CTL/FAN_TAC set 5. 1: Enable FAN_CTL/FAN_TAC set 5. (Game port should disable.) Extended multi-function selection of pin 20, 22. 0: Disable FAN_CTL/FAN_TAC set 4. 1: Enable FAN_CTL/FAN_TAC set 4. (Game port should disable.)

5 4

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IT8726F
Bit 2 Description Extended multi-function selection of pin 48 if bit0 of Index 29h is 0. 0: Reserved. 1: PCIRST5#. Enables PCIRSTIN# (pin 91), and switches VIN7 function to internal voltage divider for VCCH5V. 0: Disable. 1: Enable. Enables ATXPG (pin 95), and switches VIN3 function to internal voltage divider for VCC5V. 0: Disable. 1: Enable. Test 1 Register (Index=2Eh, Default=00h)

8.3.16

This register is the Test 1 Register and is reserved for ITE. It should not be set. 8.3.17 Test 2 Register (Index=2Fh, Default=00h)

This register is the Test 2 Register and is reserved for ITE. It should not be set.

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IT8726F V0.3

Configuration
8.4 8.4.1 Bit 7-1 0 FDC Configuration Registers (LDN=00h) FDC Activate (Index=30h, Default=00h) Description Reserved FDC Enable 1: Enable 0: Disable FDC Base Address MSB Register (Index=60h, Default=03h) Description Read only, with 0h for Base Address [15:12]. Mapped as Base Address [11:8]. FDC Base Address LSB Register (Index=61h, Default=F0h) Description Read/write, mapped as Base Address [7:3]. Read only as 000b. FDC Interrupt Level Select (Index=70h, Default=06h) Description Reserved with default 0h. Select the interrupt level Note1 for FDC. FDC DMA Channel Select (Index=74h, Default=02h) Description Reserved with default 00h. Select the DMA channel Note2 for FDC. FDC Special Configuration Register 1 (Index=F0h, Default=00h) Description Reserved with default 00h. FDD I/F Input pins internal pull-up control 0: Disable. 1: Enable. 1: IRQ sharing. 0: Normal IRQ. 1: Swap Floppy Drives A, B. 0: Normal. 1: 3-mode. 0: AT-mode. 1: Software Write Protect. 0: Normal.

8.4.2 Bit 7-4 3-0 8.4.3 Bit 7-3 2-0 8.4.4 Bit 7-4 3-0 8.4.5 Bit 7-3 2-0 8.4.6 Bit 7-5 4

3 2 1 0

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IT8726F
8.4.7 Bit 7-4 3-2 1-0 FDC Special Configuration Register 2 (Index=F1h, Default=00h) Description Reserved with default 00h. FDD B Data Rate Table Select (DRT1-0). FDD A Data Rate Table Select (DRT1-0).

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IT8726F V0.3

Configuration
8.5 8.5.1 Bit 7-1 0 Serial Port 1 Configuration Registers (LDN=01h) Serial Port 1 Activate (Index=30h, Default=00h) Description Reserved Serial Port 1 Enable 1: Enable 0: Disable Serial Port 1 Base Address MSB Register (Index=60h, Default=03h) Description Read only as 0h for Base Address[15:12]. Read/write, mapped as Base Address[11:8]. Serial Port 1 Base Address LSB Register (Index=61h, Default=F8h) Description Read/write, mapped as Base Address[7:3]. Read only as 000b. Serial Port 1 Interrupt Level Select (Index=70h, Default=04h) Description Reserved with default 0h. Select the interrupt level Note1 for Serial Port 1. Serial Port 1 Special Configuration Register 1 (Index=F0h, Default=00h) Description Reserved Serial Port 1 Mode Note3 000: Standard (default) 001: IrDA 1.0 (HP SIR) 010 : ASKIR 100 : Smart Card Reader (SCR) else : Reserved Reserved with default 0. Clock Source 00: 24 MHz/13 (Standard) 01: 24 MHz/12 (MIDI) 10: Reserved 11: Reserved 1: IRQ sharing. 0: Normal.

8.5.2 Bit 7-4 3-0 8.5.3 Bit 7-3 2-0 8.5.4 Bit 7-4 3-0 8.5.5 Bit 7 6-4

3 2-1

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IT8726F
8.5.6 Bit 7 6 5 4 3 Serial Port 1 Special Configuration Register 2 (Index=F1h, Default=50h) Description 1: No transmissions delay (40 bits) when the SIR or ASKIR is switched from RX mode to TX mode. 0: Transmission delays (40 bits) when the SIR or ASKIR is switched from RX mode to TX mode. 1: No receptions delay (40 bits) when the SIR or ASKIR is switched from TX mode to RX mode. 0: Reception delays (40 bits) when the SIR or ASKIR is switched from TX mode to RX mode. Single Mask Mode: When set, the RX of UART is masked under TX transmission. 1: Half Duplex (default). 0: Full Duplex. SIR RX polarity 1: Active low 0: Active high Reserved Serial Port 1 Special Configuration Register 3 (Index=F2h, Default=00h)

2-0 8.5.7

This register is valid only when Serial Port 1s Mode is Smart Card Reader. Bit 7-3 2 Description Reserved SCRPFET# polarity 1: Active high 0: Active low SCR_CLKSEL1-0 00: Stop 01: 3.5 MHz 10: 7.1 MHz 11: Special Divisor (96 MHz/DIV96M) Serial Port 1 Special Configuration Register 4 (Index=F3h, Default=7Fh)

1-0

8.5.8

This register is valid only when Serial Port 1s Mode is Smart Card Reader. Bit 7 Description SCRPSNT# Active Phase Control 1: Active high 0: Active low SCR DIV96M6-0

6-0

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Configuration
8.6 8.6.1 Bit 7-1 0 Serial Port 2 Configuration Registers (LDN=02h) Serial Port 2 Activate (Index=30h, Default=00h) Description Reserved Serial Port 2 Enable 1: Enable 0: Disable Serial Port 2 Base Address MSB Register (Index=60h, Default=02h) Description Read only with 0h for Base Address [15:12]. Read/write, mapped as Base Address[11:8]. Serial Port 2 Base Address LSB Register (Index=61h, Default=F8h) Description Read/write, mapped as Base Address [7:3]. Read only as 000b. Serial Port 2 Interrupt Level Select (Index=70h, Default=03h) Description Reserved with default 0h. Select the interrupt level Note1 for Serial Port 2. Serial Port 2 Special Configuration Register 1 (Index=F0h, Default=00h) Description Reserved Serial Port 2 Mode Note3 000: Standard (default) 001: IrDA 1.0 (HP SIR) 010 : ASKIR 100 : Smart Card Reader (SCR) else : Reserved Reserved with default 0. Clock Source 00: 24 MHz/13 (Standard) 01: 24 MHz/12 (MIDI) 10: Reserved 11: Reserved 1: IRQ sharing 0: Normal

8.6.2 Bit 7-4 3-0 8.6.3 Bit 7-3 2-0 8.6.4 Bit 7-4 3-0 8.6.5 Bit 7 6-4

3 2-1

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IT8726F
8.6.6 Bit 7 6 5 4 3 Serial Port 2 Special Configuration Register 2 (Index=F1h, Default=50h) Description 1: No transmission delay (40 bits) when the SIR or ASKIR is switched from RX mode to TX mode. 0: Transmission delay (40 bits) when the SIR or ASKIR is switched from RX mode to TX mode. 1: No reception delay (40 bits) when the SIR or ASKIR is switched from TX mode to RX mode. 0: Reception delay (40 bits) when the SIR or ASKIR is switched from TX mode to RX mode. Single Mask Mode: When set, the RX of UART is masked under TX transmission. 1: Half Duplex (default). 0: Full Duplex. SIR RX polarity 1: Active low 0: Active high Reserved Serial Port 2 Special Configuration Register 3 (Index=F2h, Default=00h)

2-0 8.6.7

This register is valid only when Serial Port 2s Mode is Smart Card Reader. Bit 7-3 2 Description Reserved SCRPFET# polarity. 1: Active high 0: Active low SCR_CLKSEL1-0. 00: Stop 01: 3.5 MHz 10: 7.1 MHz 11: Special Divisor ( 96 MHz/DIV96M) Serial Port 2 Special Configuration Register 4 (Index=F3h, Default=7Fh)

1-0

8.6.8

This register is valid only when Serial Port 2s Mode is Smart Card Reader. Bit 7 Description SCRPSNT# Active Phase Control 1: Active high 0: Active low SCR DIV96M6-0

6-0

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Configuration
8.7 8.7.1 Bit 7-1 0 Parallel Port Configuration Registers (LDN=03h) Parallel Port Activate (Index=30h, Default=00h) Description Reserved Parallel Port Enable 1: Enable 0: Disable Parallel Port Primary Base Address MSB Register (Index=60h, Default=03h) Description Read only as 0h for Base Address[15:12] Read/write, mapped as Base Address[11:8] Parallel Port Primary Base Address LSB Register (Index=61h, Default=78h)

8.7.2 Bit 7-4 3-0 8.7.3

If the bit 2 is set to 1, the EPP mode is disabled automatically. Bit 7-2 1-0 8.7.4 Bit 7-4 3-0 8.7.5 Bit 7-2 1-0 8.7.6 Bit 7-4 3-0 8.7.7 Bit 7-3 2-0 Description Read/write, mapped as Base Address[7:2] Read only as 00b. Parallel Port Secondary Base Address MSB Register (Index=62h, Default=07h) Description Read only as 0h for Base Address[15:12] Read/write, mapped as Base Address[11:8] Parallel Port Secondary Base Address LSB Register (Index=63h, Default=78h) Description Read/write, mapped as Base Address[7:2] Read only as 00b. Parallel Port Interrupt Level Select (Index =70h, Default=07h) Description Reserved with default 0h. Select the interrupt level Note1 for Parallel Port Parallel Port DMA Channel Select (Index=74h, Default=03h) Description Reserved with default 00h. Select the DMA channel Note2 for Parallel Port.

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IT8726F
8.7.8 Bit 7-4 3 2 1-0 Parallel Port Special Configuration Register (Index=F0h, Default=03h) Description Reserved 1: POST Data Port Disable 0: POST Data Port Enable 1: IRQ sharing 0: Normal Parallel Port Modes 00 : Standard Parallel Port mode (SPP) 01 : EPP mode 10 : ECP mode 11 : EPP mode & ECP mode

If the bit 1 is set, ECP mode is enabled. If the bit 0 is set, EPP mode is enabled. These two bits are independent. However, according to the EPP spec., when Parallel Port Primary Base Address LSB Register bit 2 is set to 1, the EPP mode cannot be enabled.

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Configuration
8.8 8.8.1 Bit 7-1 0 Environment Controller Configuration Registers (LDN=04h) Environment Controller Activate Register (Index=30h, Default=00h) Description Reserved Environment Controller Enable. 1: Enable 0: Disable This is a read/write register. Environment Controller Base Address MSB Register (Index=60h, Default=02h) Description Read only as 0h for Base Address[15:12]. Read/write, mapped as Base Address[11:8]. Environment Controller Base Address LSB Register (Index=61h, Default=90h) Description Read/write, mapped as Base Address[7:3]. Read only as 000b. PME Direct Access Base Address MSB Register (Index=62h, Default=02h) Description Read only as 0h for Base Address[15:12] Read/write, mapped as Base Address[11:8] PME Direct Access Base Address LSB Register (Index=63h, Default=30h) Description Read/write, mapped as Base Address[7:3] Read only as 000b. Environment Controller Interrupt Level Select (Index=70h, Default=09h) Description Reserved with default 0h. Select the interrupt level Note1 for Environment Controller APC/PME Event Enable Register (PER) (Index=F0h, Default=00h) Description It is set to 1 when VCCH is off. Write 1 to clear this bit. This bit is ineffective if a 0 is written to this bit. 0: Smart Card Reader card detect event disabled. 1: Smart Card Reader card detect event enabled. Reserved with default 0h. 0: PS/2 Mouse event disabled. 55 IT8726F V0.3

8.8.2 Bit 7-4 3-0 8.8.3 Bit 7-3 2-0 8.8.4 Bit 7-4 3-0 8.8.5 Bit 7-3 2-0 8.8.6 Bit 7-4 3-0 8.8.7 Bit 7 6 5 4

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IT8726F
Bit 3 2 1 0 1: PS/2 Mouse event enabled. 0: Keyboard event disabled. 1: Keyboard event enabled. 0: RI2# event disabled. 1: RI2# event enabled. 0: RI1# event disabled. 1: RI1# event enabled. 0: CIR event disabled. 1: CIR event enabled. APC/PME Status Register (PSR) (Index=F1h, Default=00h) Description It is set to 1 when VCC is ON at previous AC power failure and 0 when VCC is OFF. 0: No Smart Card Reader card detect event Detected. 1: Smart Card Reader card detect event Detected. Reserved 0: No PS/2 Mouse Event Detected. 1: PS/2 Mouse Event Detected. 0: No Keyboard Event Detected. 1: Keyboard Event Detected. 0: No RI2# Event Detected. 1: RI2# Event Detected. 0: No RI1# Event Detected. 1: RI1# Event Detected. 0: No CIR event Detected. 1: CIR event Detected. APC/PME Control Register 1 (PCR 1) (Index=F2h, Default=00h) Description PER and PSR normal run access enable PME# output control 0: Enabled 1: Disabled This bit is restored automatically to the previous VCC state before power failure occurs Disables all APC events after the power failure occurs, excluding PANSWH# Keyboard event mode selection when VCC is ON 1: Determined by PCR 2 0: Pulse falling edge on KCLK Mouse event when VCC is OFF 1: Click Key twice sequentially 0: Pulse falling edge on MCLK Mouse event when VCC is ON 1: Click Key twice sequentially 0: Pulse falling edge on MCLK CIRRX Pin Selection 1: Pin84 0: Pin85 Description

8.8.8 Bit 7 6 5 4 3 2 1 0

8.8.9 Bit 7 6

5 4 3

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Configuration
8.8.10 Bit 7-1 0 Environment Controller Special Configuration Register (Index=F3h, Default=00h) Description Reserved 1: IRQ sharing 0: Normal APC/PME Control Register 2 (PCR 2) (Index=F4h, Default=00h) Description Disable KCLK/KDAT and MCLK/MDAT auto-swap 0: Enable 1: Disable Reserved PSON# state when VCCH is switched from OFF to ON 0: High-Z (default power OFF). 1: Inverting of PSIN. Masks PANSWH# power-on event. Key Number of the Keyboard power-up event 00: 5 (Key string mode), 3 (Stroke keys at same time mode) 01: 4 (Key string mode), 2 (Stroke keys at same time mode) 10: 3 (Key string mode), 1 (Stroke keys at same time mode) 11: 2 (Key string mode), Reserved (Stroke keys at same time mode) Keyboard power-up event mode selection 00: KCLK falling edge 01: Key string mode 10: Stroke keys at same time mode 11: Reserved APC/PME Special Code Index Register (Index=F5h) Description Reserved (should be 00). Indicate which Identification Key Code or CIR code register is to be read/written via 0xF6. APC/PME Special Code Data Register (Index=F6h)

8.8.11 Bit 7

6 5

4 3-2

1-0

8.8.12 Bit 7-6 5-0 8.8.13

There are 5 bytes for Key String mode, 3 bytes for Stroke Keys at same time mode and CIR event codes.

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IT8726F
8.9 8.9.1 Bit 7-1 0 KBC (keyboard) Configuration Registers (LDN=05h) KBC (keyboard) Activate (Index=30h, Default=01h) Description Reserved KBC (keyboard) Enable 1: Enable 0: Disable KBC (keyboard) Data Base Address MSB Register (Index=60h, Default=00h) Description Read only as 0h for Base Address [15:12]. Read/write, mapped as Base Address [11:8]. KBC (keyboard) Data Base Address LSB Register (Index=61h, Default=60h) Description Read/write, mapped as Base Address[7:0] KBC (keyboard) Command Base Address MSB Register (Index=62h, Default=00h) Description Read only as 0h for Base Address[15:12] Read/write, mapped as Base Address[11:8] KBC (keyboard) Command Base Address LSB Register (Index=63h, Default=64h) Description Read/write, mapped as Base Address[7:0] KBC (keyboard) Interrupt Level Select (Index=70h, Default=01h) Description Reserved with default 0h. Select the interrupt level Note1 for KBC (keyboard) KBC (keyboard) Interrupt Type (Index=71h, Default=02h)

8.9.2 Bit 7-4 3-0 8.9.3 Bit 7-0 8.9.4 Bit 7-4 3-0 8.9.5 Bit 7-0 8.9.6 Bit 7-4 3-0 8.9.7

This register indicates the type of interrupt set for KBC (keyboard) and is read only as 02h when bit 0 of the KBC (keyboard) Special Configuration Register is cleared. When bit 0 is set, this type of interrupt can be selected as level or edge trigger. Bit 7-2 1 0 Description Reserved 1: High Level 0: Low Level 1: Level Type 0: Edge Type 58 IT8726F V0.3

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Configuration
8.9.8 Bit 7-5 4 3 2 1 0 KBC (keyboard) Special Configuration Register (Index=F0h, Default=08h) Description Reserved 1: IRQ sharing 0: Normal 1: KBCs clock 8 MHz 0: KBCs clock 12 MHz 1: Key lock enabled 0: Key lock disabled 1: Type of interrupt of KBC (keyboard) can be changed 0: Type of interrupt of KBC (keyboard) is fixed Reserved

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IT8726F
8.10 8.10.1 Bit 7-1 0 KBC (mouse) Configuration Registers (LDN=06h) KBC (mouse) Activate (Index=30h, Default=00h) Description Reserved KBC (mouse) Enable 1: Enable 0: Disable KBC (mouse) Interrupt Level Select (Index=70h, Default=0Ch) Description Reserved with default 0h. Select the interrupt level Note1 for KBC (mouse). KBC (mouse) Interrupt Type (Index=71h, Default=02h)

8.10.2 Bit 7-4 3-0 8.10.3

This register indicates the type of interrupt used for KBC (mouse) and is read only as 02h when bit 0 of the KBC (mouse) Special Configuration Register is cleared. When bit 0 is set, the type of interrupt can be selected as level or edge trigger. Bit 7-2 1 0 Description Reserved 1: High level 0: Low level 1: Level type 0: Edge type KBC (mouse) Special Configuration Register (Index=F0h, Default=00h) Description Reserved with default 00h. 1: IRQ sharing. 0: Normal. 1: Type of interrupt of KBC (mouse) can be changed. 0: Type of interrupt of KBC (mouse) is fixed.

8.10.4 Bit 7-2 1 0

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Configuration
8.11 8.11.1 Bit 7-4 3-0 8.11.2 Bit 7-0 8.11.3 Bit 7-4 3-0 8.11.4 Bit 7-3 2-0 8.11.5 Bit 7-4 3-0 8.11.6 Bit 7-3 2-0 8.11.7 Bit 7-4 3-0 GPIO Configuration Registers (LDN=07h) SMI# Normal Run Access Base Address MSB Register (Index=60h, Default=00h) Description Read only as 0h for Base Address [15:12]. Read/write, mapped as Base Address [11:8]. SMI# Normal Run Access Base Address LSB Register (Index=61h, Default=00h) Description Read/write, mapped as Base Address[7:0]. Simple I/O Base Address MSB Register (Index=62h, Default=00h) Description Read only as 0h for Base Address [15:12]. Read/write, mapped as Base Address [11:8]. Simple I/O Base Address LSB Register (Index=63h, Default=00h) Description Read/write, mapped as Base Address [7:3]. Read only as 000b. Serial Flash I/F Base Address MSB Register (Index=64h, Default=00h) Description Read only as 0h for Base Address [15:12]. Read/write, mapped as Base Address [11:8]. Serial Flash I/F Base Address LSB Register (Index=65h, Default=00h) Description Read/write, mapped as Base Address [7:3]. Read only as 000b. Panel Button De-bounce Interrupt Level Select Register (Index=70h, Default=00h) Description Reserved Select the interrupt level Note1 for Panel Button De-bounce.

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IT8726F
8.11.8 Bit 7 6 5 4 3-2 1 0 Watch Dog Timer Control Register (Index=71h, Default=00h) Description WDT is reset upon a CIR interrupt WDT is reset upon a KBC (mouse) interrupt WDT is reset upon a KBC (keyboard) interrupt WDT is reset upon a read or a write to the Game Port base address Reserved Force Time-out This bit is self-clearing WDT Status 1: WDT value reaches 0. 0: WDT value is not 0. Watch Dog Timer Configuration Register (Index=72h, Default=001s0000h) Description WDT Time-out value select 1 1: Second 0: Minute WDT output through KRST (pulse) enable 1: Enable 0: Disable WDT Time-out value Extra select 1: 4 s.64ms x WDT Timer-out value (default = 4s). 0: Determine by WDT Time-out value select 1 (bit 7 of this register). WDT output through PWROK1/PWROK2 (pulse) enable 1: Enable. 0: Disable This default value of this register is selected by JP7. Select the interrupt level Note1 for WDT Watch Dog Timer Time-Out Value (LSB) Register (Index=73h, Default=38h) Description WDT time-out value 7-0 Watch Dog Timer Time-Out Value (MSB) Register (Index=74h, Default=00h) Description WDT time-out value 15-8 GPIO Pin Set 1, 2, 3, 4, 5 and 6 Polarity Registers (Index=B0h, B1h, B2h, B3h, B4h and B5h, Default=00h)

8.11.9 Bit 7

3-0 8.11.10 Bit 7-0 8.11.11 Bit 7-0 8.11.12

These registers are used to program the GPIO pin type as polarity inverting or non-inverting. Bit 7-0 Description 1: Inverting 0: Non-inverting 62 IT8726F V0.3

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Configuration
8.11.13 GPIO Pin Set 1, 2, 3, 4, 5 and 6 Pin Internal Pull-up Enable Registers (Index=B8h, B9h, BAh, BBh, BCh and BDh, Default=00h)

These registers are used to enable the GPIO pin internal pull-up. Bit 7-0 Description 1: Enable 0: Disable Simple I/O Set 1, 2, 3, 4 and 5 Enable Registers (Index=C0h, C1h, C2h, C3h and C4h, Default=01h, 00h, 00h, 40h, and 00h)

8.11.14

These registers are used to select the function as the Simple I/O function or the Alternate function. Bit 7-0 Description 1: Simple I/O function 0: Alternate function Simple I/O Set 1, 2, 3, 4 and 5 Output Enable Registers (Index=C8h, C9h, CAh, CBh and CCh, Default=01h, 00h, 00h, 40h, and 00h)

8.11.15

These registers are used to determine the direction of the Simple I/O. Bit 7-0 Description 0: Input mode 1: Output mode Panel Button De-bounce 0 Input Pin Mapping Registers (Index=E0h, Default=00h) Description Reserved IRQ Enable Input pin Location. Please see Location mapping table Note4 Panel Button De-bounce 1 Input Pin Mapping Registers (Index=E1h, Default=00h) Description Reserved Input pin Location. Please see Location mapping table Note4 IRQ External Routing 1-0 Input Pin Mapping Registers (Index=E3h-E2h, Default=00h) Description Reserved IRQ Enable Input pin Location. Please see Location mapping table Note4

8.11.16 Bit 7 6 5-0 8.11.17 Bit 7-6 5-0 8.11.18 Bit 7 6 5-0

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IT8726F
8.11.19 Bit 7-4 3-0 8.11.20 Bit 7 6 5 4 3 2 1 0 8.11.21 Bit 7 6 5-3 2 1 0 8.11.22 IRQ External Routing 1-0 Interrupt Level Selection Register (Index=E4h, Default=00h) Description Select the interrupt level Note1 for IRQ External Routing 1. Select the interrupt level Note1 for IRQ External Routing 0. SMI# Control Register 1 (Index=F0h, Default=00h) Description Enables the generation of an SMI# due to MIDIs IRQ (EN_MIDI). Enables the generation of an SMI# due to KBC (Mouse)s IRQ (EN_MIRQ). Enables the generation of an SMI# due to KBC (Keyboard)s IRQ (EN_KIRQ). Enables the generation of an SMI# due to Environment Controllers IRQ (EN_ECIRQ). Enables the generation of an SMI# due to Parallel Ports IRQ (EN_PIRQ). Enables the generation of an SMI# due to Serial Port 2s IRQ (EN_S2IRQ). Enables the generation of an SMI# due to Serial Port 1s IRQ (EN_S1IRQ). Enables the generation of an SMI# due to FDCs IRQ (EN_FIRQ). SMI# Control Register 2 (Index=F1h, Default=00h) Description Forces to clear all the SMI# status register bits, non-sticky. 0: Edge trigger 1: Level trigger Reserved Enables the generation of an SMI# due to WDTs IRQ (EN_WDT). Enables the generation of an SMI# due to CIRs IRQ (EN_CIR). Enables the generation of an SMI# due to PBDs IRQ (EN_PBD). SMI# Status Register 1 (Index=F2h, Default=00h)

This register is used to read the status of SMI# inputs. Bit 7 6 5 4 3 2 1 0 Description MIDIs IRQ KBC (PS/2 Mouse)s IRQ KBC (Keyboard)s IRQ Environment Controllers IRQ Parallel Ports IRQ Serial Port 2s IRQ Serial Port 1s IRQ FDCs IRQ

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Configuration
8.11.23 SMI# Status Register 2 (Index=F3h, Default=00h)

This register is used to read the status of SMI# inputs. Bit 7-6 Description Panel Button De-bounce Status 1-0 Writing 1 will reset the statuses. 0: None detected 1: Detected Reserved WDTs IRQ CIRs IRQ PBDs IRQ SMI# Pin Mapping Register (Index=F4h, Default=00h) Description Reserved SMI# Pin Location Please see Location mapping table Note4. Hardware Monitor Thermal Output Pin Mapping Register (Index=F5h, Default=00h) Description Reserved Thermal Output Pin Location Please see Location mapping table Note4. Hardware Monitor Alert Beep Pin Mapping Register (Index=F6h, Default=00h) Description Reserved Alert Beep Pin Location Please see Location mapping table Note4. Keyboard Lock Pin Mapping Register (Index=F7h, Default=00h) Description Reserved Keyboard Lock Pin Location Please see Location mapping table Note4. GP LED Blinking 1 Pin Mapping Register (Index=F8h, Default=00h) Description Reserved GP LED Blinking 1 Location Please see Location mapping table Note4. 65 IT8726F V0.3

5-3 2 1 0 8.11.24 Bit 7-6 5-0

8.11.25 Bit 7-6 5-0

8.11.26 Bit 7-6 5-0

8.11.27 Bit 7-6 5-0

8.11.28 Bit 7-6 5-0

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IT8726F
8.11.29 Bit 7-4 3 2-1 GP LED Blinking 1 Control Register (Index=F9h, Default=00h) Description Reserved GP LED Blinking 1 short low pulse enabled GP LED 1 Frequency Control 00: 4 Hz 01: 1 Hz 10: 1/4 Hz 11: 1/8 Hz GP LED Blinking 1 Output low enabled GP LED Blinking 2 Pin Mapping Register (Index=FAh, Default=00h) Description Reserved GP LED Blinking 2 Location Please see Location mapping table Note4 GP LED Blinking 2 Control Register (Index=FBh, Default=00h) Description Reserved GP LED Blinking 2 short low pulse enabled. GP LED 2 Frequency Control. 00: 4 Hz 01: 1 Hz 10: 1/4 Hz 11: 1/8 Hz GP LED Blinking 2 Output low enabled. VID Input Register (Index=FCh, Default=--h) Description Reserved VID 5-0 inputs They are read-only. Bit 7-6 select the data source. Writing 1 to bit 0 to update initial VID input. VID Output Register (Index=FDh, Default=00h) Description VID_OE. VID output enable 1: Output 0: Input Reserved VID 5-0 output values

0 8.11.30 Bit 7-6 5-0

8.11.31 Bit 7-4 3 2-1

0 8.11.32 Bit 7-6 5-0

8.11.33 Bit 7 6 5-0

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Configuration
8.12 8.12.1 Bit 7-1 0 MIDI Port Configuration Registers (LDN=08h) MIDI Port Activate (Index=30h, Default=00h) Description Reserved MIDI Port Enable 1: Enable 0: Disable MIDI Port Base Address MSB Register (Index=60h, Default=03h) Description Read only with 0h for Base Address[15:12]. Read/write, mapped as Base Address[11:8]. MIDI Port Base Address LSB Register (Index=61h, Default=00h) Description Read/write, mapped as Base Address[7:3] Read only as 000b MIDI Port Interrupt Level Select (Index=70h, Default=0Ah) Description Reserved with default 0h Select the interrupt level Note1 for MIDI Port MIDI Port Special Configuration Register (Index=F0h, Default=00h) Description Reserved with default 00h. 1: IRQ sharing 0: Normal

8.12.2 Bit 7-4 3-0 8.12.3 Bit 7-3 2-0 8.12.4 Bit 7-4 3-0 8.12.5 Bit 7-1 0

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IT8726F
8.13 8.13.1 Bit 7-1 0 Game Port Configuration Registers (LDN=09h) Game Port Activate (Index=30h, Default=00h) Description Reserved Game Port Enable 1: Enabled (If enable, the multi function pin20, 21,22,23 will change to Game port function.) 0: Disabled Game Port Base Address MSB Register (Index=60h, Default=02h) Description Read only with 0h for Base Address[15:12] Read/write, mapped as Base Address[11:8] Game Port Base Address LSB Register (Index=61h, Default=01h) Description Read/write, mapped as Base Address[7:0]

8.13.2 Bit 7-4 3-0 8.13.3 Bit 7-0

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Configuration
8.14 8.14.1 Bit 7-1 0 Consumer IR Configuration Registers (LDN=0Ah) Consumer IR Activate (Index=30h, Default=00h) Description Reserved Consumer IR Enable 1: Enable 0: Disable Consumer IR Base Address MSB Register (Index=60h, Default=03h) Description Read only with 0h for Base Address[15:12] Read/write, mapped as Base Address[11:8] Consumer IR Base Address LSB Register (Index=61h, Default=10h) Description Read/write, mapped as Base Address[7:3] Read only as 000b Consumer IR Interrupt Level Select (Index=70h, Default=0Bh) Description Reserved with default 0h Select the interrupt level Note1 for Consumer IR Consumer IR Special Configuration Register (Index=F0h, Default=00h) Description Reserved with default 00h 1: IRQ sharing 0: Normal

8.14.2 Bit 7-4 3-0 8.14.3 Bit 7-3 2-0 8.14.4 Bit 7-4 3-0 8.14.5 Bit 7-1 0

Note 1: Interrupt level mapping Fh-Dh: not valid Ch: IRQ12 3h: IRQ3 2h: not valid 1h: IRQ1 0h: no interrupt selected Note 2: DMA channel mapping 7h-5h: not valid 4h: no DMA channel selected 3h: DMA3 2h: DMA2 1h: DMA1 0h: DMA0 www.ite.com.tw 69 IT8726F V0.3

IT8726F
Note 3: Except the standard mode, COM1 and COM2 cannot be selected in the same mode. Note 4: The Location mapping table Location Description 001 000 GP10 (pin 84). Powered by VCCH. 001 001 GP11 (pin 34). 001 010 GP12 (pin 33). 001 011 GP13 (pin 32). 001 100 GP14 (pin 31). 001 101 GP15 (pin 30). 001 110 GP16 (pin 29). 001 111 GP17 (pin 28). 010 000 GP20 (pin 27). 010 001 GP21 (pin 26). 010 010 GP22 (pin 25). 010 011 GP23 (pin 24). 010 100 GP24 (pin 23). 010 101 GP25 (pin 22). 010 110 GP26 (pin 21). 010 111 GP27 (pin 20). 011 000 GP30 (pin 19). 011 001 GP31 (pin 18). 011 010 GP32 (pin 17). 011 011 GP33 (pin 16). 011 100 GP34 (pin 14). 011 101 GP35 (pin 13). 011 110 GP36 (pin 12). 011 111 GP37 (pin 11). 100 000 GP40 (pin 79). Powered by VCCH. 100 001 GP41 (pin 78). Powered by VCCH. 100 010 GP42 (pin 76). Powered by VCCH. 100 011 GP43 (pin 75). Powered by VCCH. 100 100 GP44 (pin 72). Powered by VCCH. 100 101 GP45 (pin 71). Powered by VCCH. 100 110 GP46 (pin 70). Powered by VCCH. 100 111 GP47 (pin 66). 101 000 GP50 (pin 48). 101 001 GP51 (pin 10). 101 010 GP52 (pin 9). 101 011 GP53 (pin 77). Powered by VCCH. 101 100 GP54 (pin 73). Powered by VCCH. 101 101 GP55 (pin 85). Powered by VCCH. else Reserved

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Functional Description
9. Functional Description
9.1 LPC Interface

The IT8726F supports the peripheral site of the LPC I/F as described in the LPC Interface Specification Rev.1.0 (Sept. 29, 1997). In addition to the required signals (LAD3-0, LFRAME#, LRESET#, LCLK (LCLK is the same as PCICLK.)), the IT8726F also supports LDRQ#, SERIRQ and PME#. 9.1.1 LPC Transactions

The IT8726F supports some parts of the cycle types described in the LPC I/F specification. Memory read and Memory write cycles are used for the Flash I/F. I/O read and I/O write cycles are used for the programmed I/O cycles. DMA read and DMA write cycles are used for DMA cycles. All of these cycles are characteristic of the single byte transfer. For LPC host I/O read or write transactions, the Super I/O module processes a positive decoding, and the LPC interface can respond to the result of the current transaction by sending out SYNC values on LAD[3:0] signals or leave LAD[3:0] tri-state depending on its result. For DMA read or write transactions, the LPC interface will make reactions according to the DMA requests from the DMA devices in the Super I/O modules, and decides whether to ignore the current transaction or not. The FDC and ECP are 8-bit DMA devices, so if the LPC Host initializes a DMA transaction with data size of 16/32 bits, the LPC interface will process the first 8-bit data and response with a SYNC ready (0000b) which will terminate the DMA burst. The LPC interface will then re-issue another LDRQ# message to assert DREQn after finishing the current DMA transaction. 9.1.2 LDRQ# Encoding

The Super I/O module provides two DMA devices: the FDC and the ECP. The LPC Interface provides LDRQ# encoding to reflect the DREQ[3:0] status. Two LDRQ# messages or different DMA channels may be issued back-to-back to trace DMA requests quickly. But, four PCI clocks will be inserted between two LDRQ# messages of the same DMA channel to guarantee that there is at least 10 PCI clocks for one DMA request to change its status. (The LPC host will decode these LDRQ# messages, and send those decoded DREQn to the legacy DMA controller which runs at 4 MHz or 33/8 MHz). 9.2 Serialized IRQ

The IT8726F follows the specification of Serialized IRQ Support for PCI System, Rev. 6.0, September 1, 1995, to support the serialized IRQ feature, and is able to interface most PC chipsets. The IT8726F encodes the parallel interrupts to an SERIRQ which will be decoded by the chipset with built-in Interrupt Controllers (two 8259 compatible modules). 9.2.1 Continuous Mode

When in the Continuous mode, the SIRQ host initiates the Start frame of each SERIRQ sequence after sending out the Stop frame by itself. (The next Start frame may or may not begin immediately after the turnaround state of current Stop frame.) The SERIRQ is always activated and SIRQ host keeps polling all the IRQn and system events, even though no IRQn status is changed. The SERIRQ enter the Continuous mode following a system reset.

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IT8726F
9.2.2 Quiet Mode In the Quiet mode, when one SIRQ Slave detects its input IRQn/events have been changed, it may initiate the first clock of Start frame. The SIRQ host can then follow to complete the SERIRQ sequence. In the Quiet mode, the SERIRQ has no activity following the Stop frame until it is initiated by SIRQ Slave, which implies low activity = low mode power consumption. 9.2.3 Waveform Samples of SERIRQ Sequence

Start Frame
S/H H R T

IRQ0 Frame
S R T

IRQ1 Frame
S R T

SMI# Frame
S R T

IRQ3 Frame
S R T

IRQ4 Frame
S R T

PCICLK SERIRQ
S: Slave drive (4/6/8)T

H: Host drive

R: Recovery

T: Turn-around

S/H: Slave drive when in Quiet mode, Host drive when in Continuous mode

Figure 9-1. Start Frame Timing

Last Frame
S R T

Stop Frame
I H

(Quiet) R T W

Start Frame
S H

Last Frame
S R T

Stop Frame
H

(Continuous) R T H1

PCICLK SERIRQ
2 Tclk 0~n Tclk idle state 3 Tclk 0~n T, depends on master

S: Slave drive

H: Host drive

R: Recovery

T: Turn-around

I: Idle

W: Waiting

Figure 9-2. Stop Frame Timing

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Functional Description
9.2.4 Slot Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 32:22 SERIRQ Sampling Slot IRQn/ Events IRQ0 IRQ1 SMI# IRQ3 IRQ4 IRQ5 IRQ6 IRQ7 IRQ8 IRQ9 IRQ10 IRQ11 IRQ12 IRQ13 IRQ14 IRQ15 IOCHCK# INTA# INTB# INTC# INTD# Unassigned #of Clocks IT8726F Past Start 2 5 8 11 14 17 20 23 26 29 32 35 38 41 44 47 50 53 56 59 62 95 / 65 Y Y Y Y Y Y Y Y Y Y Y Y Y Y -

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IT8726F
9.3 General Purpose I/O The IT8726F provides five sets of flexible I/O control and special functions for the system designers via a set of multi-functional General Purpose I/O pins (GPIO). The GPIO functions will not be performed unless the related enable bits of the GPIO Multi-function Pin Selection registers (Index 25h, 26h, 27h, 28h and 29h of the Global Configuration Registers) are set. The GPIO functions include the simple I/O function and alternate function, and the function selection is determined by the Simple I/O Enable Registers (LDN=07h, Index=C0h, C1h, C2h, C3h and C4h). The Simple I/O function includes a set of registers, which correspond to the GPIO pins. All control bits are divided into five registers. The accessed I/O ports are programmable and are five consecutive I/O ports (Base Address+0, Base Address+1, Base Address+2, Base Address+3, Base Address+4). Base Address is programmed on the registers of GPIO Simple I/O Base Address LSB and MSB registers (LDN=07h, Index=60h and 61h). The Alternate Function provides several special functions for users, including Watch Dog Timer, SMI# output routing, External Interrupt routing, Panel Button De-bounce, Keyboard Lock input routing, LED Blinking, Thermal output routing, and Beep output routing. The last two are the sub-functions of Hardware Monitor. The Panel Button De-bounce is an input function. After the panel button de-bounce is enabled, a related status bit will be set when an active low pulse is detected on the GPIO pin. The status bits will be cleared by writing 1s to them. Panel Button De-bounce Interrupt will be issued if any one of the status bit is set. However, the new setting status will not issue another interrupt unless the previous status bit is cleared before being set. The Key Lock function locks the keyboard to inhibit the keyboard interface. The programming method is to set bit 2 on the register Index F0h of KBC (keyboard) (LDN=5). The pin location mapping, Index F7h must also be programmed correctly. The Blinking function provides a low frequency blink output. By connecting to some external components, it can be used to control a power LED. There are several frequencies that can be selected. The Watch Dog Timer (WDT) function is constituted by a time counter, a time-out status register, and the timer reset control logic. The time-out status bit may be mapped to an interrupt or KRST# through the WDT Configuration register. The WDT has a programmable time-out range from 1 to 65535 minutes or 1 to 65535 seconds. The units are also programmable, either a minute or a second, via bit7 of the WDT Configuration register. When the WDT Time-out Value register is set to a non-zero value, the WDT loads the value and begin counting down from the value. When the value reaches to 0, the WDT status register will be set. There are many system events that can reload the non-zero value into the WDT, which include a CIR interrupt, a Keyboard Interrupt, a Mouse Interrupt, or I/O reads/writes to the Game Port base address. The effect on the WDT for each of the events may be enabled or disabled through bits in the WDT control register. No matter what value in the time counter is, the host may force a time-out to occur by writing a 1 to the bit 1 of the WDT Configuration register. The External Interrupt routing function provides a useful feature for motherboard designers. Through this function, the parallel interrupts of other on-board devices can be easily re-routed into the Serial IRQ. The SMI# is a non-maskable interrupt dedicated to the transparent power management. It consists of different enabled interrupts generated from each of the functional blocks in the IT8726F. The interrupts are redirected as the SMI# output via the SMI# Control Register 1 and SMI# Control Register 2. The SMI# Status Registers 1 and 2 are used to read the status of the SMI input events. All the SMI# Status Register bits can be cleared when the corresponding source events become invalidated. These bits can also be cleared by writing 1 to bit 7 of SMI# Control Register 2, whether the events of the corresponding sources are invalidated or not. The SMI# events can be programmed as pulse mode or level mode whenever an SMI# event occurs. The logic equation of the SMI# event is described below: www.ite.com.tw 74 IT8726F V0.3

Functional Description
SMI# event = (EN_FIRQ and FIRQ) or (EN_S1IRQ and S1IRQ) or (EN_S2IRQ and S2IRQ) or (EN_PIRQ and PIRQ) or (EN_EC and EC_SMI) or (EN_PBDIRQ or PBDIRQ) or (EN_KIRQ and KIRQ) or (EN_MIRQ and MIRQ) or (EN_CIR and CIR_IRQ) or (EN_WDT and WDT_IRQ) or (EN_STPCLK and STPCLK_IRQ)

Thermal Output LED Blinking 1 LED Blinking 2 Beep# SMI#

1 2 3 4 5
Simple I/O Polarity enable
0

Simple I/O Register Bit-n

Pull-up enable

SD-bus WR#

DTYPE

Output enable
1 0

RD_ Interrupt SD-bus

status

GPIO PIN

De-bounce enable
De-bounce circuit

RD_(IDX=64h, 65h)

Panel Button De-bounce Bit-n

External IRQ Routing (Level 3 - 7, 9 - 11, 14-15) Keyboard lock

Figure 9-3. General Logic of GPIO Function

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IT8726F
9.4 Advanced Power Supply Control and Power Management Event (PME#) The circuit for advanced power supply control (APC) provides four power-up events, Keyboard, Mouse, CIR, and Smart Card Reader card detect. When any of these four events is true, PWRON# will perform a low state until VCC is switched to ON state. The four events include the followings: 1. 2. 3. 4. Detection of KCLK edge or special pattern of KCLK and KDAT. The special pattern of KCLK means pressing pre-set key string sequentially, and KDAT means pressing pre-set keys simultaneously Detection of MCLK edge or special pattern of MCLK and MDAT. The special pattern of MCLK and MDAT means clicking on any mouse button twice sequentially. Receiving CIR patterns are matched the previous stored pattern stored at the APC/PME Special Code Index and Data Register Detection of the Smart Card Reader Card Detect pulse on the SCRPSNT# input pin

The PANSWH# and PSON# are especially designed for the system. PANSWH# serves as a main power switch input which is wire-AND to the APC output PWRON#. PSON# is the ATX Power control output, which is a power-failure gating circuit. The power-failure gating circuit is responsible for gating the PSIN input until PANSWH# becomes active when the VCCH is switched from OFF to ON. The power-failure gating circuit can be disabled by setting the APC/PME Control Register 2 (LDN=04h, index F4h, bit 5). The gating circuit also provides an auto-restore function. When the bit 5 of PCR1 is set, the previous PSON# state will be restored when the VCCH is switched from OFF to ON. The Mask PWRON# Activation bit (bit 4 of PCR 1) is used to mask all Power-up events except Switch on event when the VCCH state is just switched from FAIL to OFF. In other words, when this bit is set and the power state is switched from FAIL to OFF, the only validated function is PANSWH#. The PCR2 register is responsible for determining the Keyboard power up events and APC conditions. Bit 4 is used to mask the PANSWH# power-on event on the PWRON# pin. To enable this bit, the keyboard power-up event should be enabled and set by (1) pressing pre-set key string sequentially or (2) stroking pre-set keys simultaneously. The APC/PME# special code index and data registers are used to specify the special key codes in the special power-up events of (1) pressing pre-set key string sequentially or (2) stroking pre-set keys simultaneously. A CIR event is generated if the input CIR RX pattern is the same as the previous stored pattern stored at PME Special Code Index and Data Registers (LDN=04h, Index=F5h and F6h). The total maximum physical codes are nineteen bytes (from Index 20h to 32h). The first byte (Index 20h) is used to specify the pattern length (in bytes). Bit [7:4] are used when VCC is on; and bit [3:0] when VCC goes OFF. The length represented in each 4 bits will be incremented by 3 internally as the actual length to be compared. For most of the CIR protocols, the first several bytes are always the same for each key (or pattern). The differences are always placed in the last several bytes. Thus, the system designer can program the IT8726F to generate a CIR PME# event as any keys when VCC is ON and a special key (i.e. POWER-ON) when VCC is OFF. The Smart Card Reader Card Detect event is used to power on the system when any Integrated Circuit Card is inserted in the Smart Card Reader. When inserted, a pulse will be generated on the SCRPSNT# input pin. If the relative enabled bit is enabled, the power-up event will be also generated. All APC registers (Index=F0h, F2h, F4h, F5h and F6h) are powered by back-up power (VBAT) when VCCH is OFF. PME# is used to wake up the system from low-power states (S1-S5). Except the five events of the APCs, there will be another event to generate PME#: RI1# and RI2# events. RI1# and RI2# are Ring Indicator of Modem status at ACPI S1 or S2 state. A falling edge on these pins issues PME# events if the enable bits are set.

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Functional Description
9.5 9.5.1 SPI Serial Flash Controller Overview

The SPI Serial Flash Controller is a LPC to serial Flash I/F controller. 9.5.2 Features

SPI Interface LPC memory cycle and firmware memory cycle supported. 9.5.3 Register Descriptions Table 9-1. Memory Stick Register List Address Base + 0h Base + 1h Base + 2h Base + 3h Base + 4h Base + 5h Base + 6h Base + 7h 9.5.3.1 R/W R/W R/W R/W R/W R/W R R R/W-R Default 20h 00h 00h 00h 00h --00h/-Name Control Register (SPI_CTRL) Command Register (SPI_CMD) Address 0 Register (SPI_ADDR0) Address 1 Register (SPI_ADDR1) Address 2 Register (SPI_ADDR2) Input Data 0 Register (SPI_IDATA0) Input Data 1 Register (SPI_IDATA1) Output Data Register (SPI_ODATA)/ Input Data 2 Register (SPI_IDATA2)

Control Register (SPI_CTRL)

Address: Base address + 0h Bit 7 R/W R Default Description SPI Status Report SPI I/F status. 0: SPI I/F is idle 1: SPI I/F is busy Start IO Transfer Start SPI cycle with the instruction/parameter given through I/O port. 0: No Start IO 1: Enable Start IO/going Multiple Byte mode Enable Multiple Byte mode in LPC memory write/read cycle 0: Disable 1: Enable SCK Selection Select SCK Frequency 0: 33MHz/2 1: 33MHz Input Data Byte Determine input data byte number in Start IO mode 00: None 01: 1 byte (SPI_DATAI0) 10: 2 bytes (SPI_DATAI0, SPI_DATAI1) 11: 3 bytes (SPI_DATAI0, SPI_DATAI1, SPI_DATAI2) 77 IT8726F V0.3

R/W

0b

R/W

1b

R/W

0b

3-2

R/W

00b

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IT8726F
Bit 1-0 R/W R/W Default 00b Description Output Data Byte Determine output data byte number (including Instruction, Address, Data) in Start IO mode. 00: 1 byte. (SPI_CMD) 01: 2 bytes. (SPI_CMD, SPI_DATAO) 10: 4 bytes. (SPI_CMD, ADDR2, ADDR1, ADDR0) 11: 5 bytes. (SPI_CMD, ADDR2, ADDR1, ADDR0, SPI_DATAO)

9.5.3.2

Command Register (SPI_CMD)

Address: Base address + 1h Bit 7-0 R/W R/W Default 00h Description Command Register (SPI_CMD [7:0]) This register will set the Instruction command code in Start IO mode. (The first byte)

9.5.3.3

Address 0 Register (SPI_ADDR0)

Address: Base address + 2h Bit 7-0 R/W R/W Default 00h Description Address 0 Register (SPI_ADDR0 [7:0]) This register will set the Address [7:0] in Start IO mode.

9.5.3.4

Address 1 Register (SPI_ADDR1)

Address: Base address + 3h Bit 70 R/W R/W Default 00h Description Address 1 Register (SPI_ADDR1 [7:0]) This register will set the Address [15:8] in Start IO mode.

9.5.3.5

Address 2 Register (SPI_ADDR2)

Address: Base address + 4h Bit 7-0 R/W R/W Default 00h Description Address 2 Register (SPI_ADDR2 [7:0]) This register will set the Address [23:16] in Start IO mode.

9.5.3.6

Input Data 0 Register (SPI_IDATA0)

Address: Base address + 5h Bit 7-0 R/W R Default Description Input Data 0 Register (SPI_IDATA0 [7:0]) This register will set the Input Data 0 byte in Start IO mode.

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Functional Description
9.5.3.7 Input Data 1 Register (SPI_IDATA1)

Address: Base address + 6h Bit 7-0 R/W R Default Description Input Data 1 Register (SPI_IDATA1 [7:0]) This register will set the Input Data 1 byte in Start IO mode.

9.5.3.8

Output Data/Input Data 2 Register (SPI_ODATA/ SPI_IDATA2)

Address: Base address + 7h Bit 7-0 R/W R/W Default 00h Description Output Data Register (SPI_ODATA [7:0])/ Input Data 2 Register (SPI_IDATA1 [7:0]) This register will set the Output Data byte in Start IO mode, or Input Data 2 when the input data byte number is 3.

9.5.4

Function Descriptions

Programming sequence: All the instruction code and byte numbers should refer to the Serial Flash product specification. Start IO mode: // 1: Check SPI I/F IOR [SPI_CTRL];

// check bit7 SPI status

// 2: Set the parameters. Dont care the write sequence. IOW [SPI_CMD] XXh: // Set SPI Instruction IOW [SPI_ADDR0] XXh: // Set SPI Address0, if necessary IOW [SPI_ADDR1] XXh: // Set SPI Address1, if necessary IOW [SPI_ADDR2] XXh: // Set SPI Address2, if necessary IOW [SPI_ODATA] XXh: // Set SPI Output Data, if necessary // 3: Start SPI I/F IOW [SPI_CTRL] {4h1, Input_data_byte, Output_data_byte};

LPC memory cycle: When the host issues LPC memory read cycle with the matching memory space, the controller will issue SPI read cycle automatically. The controller will pre-read 0-3 byte(s) data in buffers. The pre-read data byte number is determined by the starting address 0 and 1. The number will be 3 bytes if the two addresses are 00b. The number will be 2 bytes if two addresses are 01b. The number will be 1 byte if two addresses are 10b. There is no pre-read data if two addresses are 11b.If the address of the next coming LPC memory cycles matches the buffers address; no SPI read cycle would be issued. For most of the serial flash product, Write-Enable instruction through Start IO mode should be given before issuing LPC memory writes cycle. Normally, each LPC memory cycle will issue one byte SPI programming cycle (Instruction, Addresses, 1 byte Data). If Multiple Byte mode is enabled, multi-byte SPI programming cycle will be issued. For example: // LPC Memory Write Multiple byte mode // 1: Write-Enable command IOR [SPI_CTRL]; // check bit7 SPI status IOW [SPI_CMD] 06h: // Set SPI Instruction IOW [SPI_CTRL] {4h3, 2b00, 2b00}; // Start IO SPI cycle and enable LPC memory Multiple Byte mode www.ite.com.tw 79 IT8726F V0.3

IT8726F
// 2: LPC memory write cycles: The first LPC memory cycle will start SPI cycle and determine the // Programming page address. The following LPC memory write cycles should be continue addresses. // And, the total bytes cannot be more than 256 [starting address 7-0]. These conditions should be // Confirmed by the programmer. The controller will NOT check them. During this period, the SPI cycle // will not be finished. Between two MEMW cycle, HOLD# pin will assert and SCK will be forced in low. MEMW [Starting address]: // Set SPI Address and the first byte data. MEMW [Starting address+1]: // Set SPI second byte data. MEMW [Starting address+2]: // Set SPI third byte data. : MEMW [Starting address+N]: // Set SPI Nth byte data. // 3: Terminate SPI I/F IOW [SPI_CTRL] {4h0, 2b00, 2b00}; // Terminate LPC memory write Page Program mode and SPI cycle

// LPC Memory Read Multiple byte mode // 1: Write-Enable command IOW [SPI_CTRL] {4h2, 2b00, 2b00}; // Enable LPC memory Multiple Byte mode // 2: LPC memory read cycles: The first LPC memory cycle will start SPI cycle and determine the // reading address. The following LPC memory read cycles should be continue addresses. // And, the total bytes will not be limited. The programmer should confirm these conditions. // The controller will NOT check them. During this period, the SPI cycle will not be finished. Between two // MEMR cycle, HOLD# pin will assert and SCK will be forced in low. MEMR [Starting address]: // Set SPI Address and the first byte data. MEMR [Starting address+1]: // Set SPI second byte data. MEMR [Starting address+2]: // Set SPI third byte data. : MEMR [Starting address+N]: // Set SPI Nth byte data. // 3: Terminate SPI I/F IOW [SPI_CTRL] 9.6 {4h0, 2b00, 2b00}; // Terminate LPC memory Read Multiple Byte mode and SPI cycle

Environment Controller

The Environment Controller (EC), built in the IT8726F, includes eight voltage inputs, three temperature sensor inputs, five FAN Tachometer inputs, and three sets of advanced FAN Controllers. The EC monitors the hardware environment and implements environmental control for personal computers. The IT8726F contains an 8-bit ADC (Analog-to-Digital Converter) which is responsible for monitoring the voltages and temperatures. The ADC converts the analog inputs, ranging from 0V to 4.096V, to 8-bit digital bytes. Thanks to the additional external components, the analog inputs are able to monitor different voltage ranges, in addition to monitoring the fixed input range of 0V to 4.096V. Through the external thermistors, the temperature sensor inputs can be converted to 8-bit digital bytes, enabling the sensor inputs, and monitoring the temperature around the thermistors or thermal diode. A built-in ROM is also provided to adjust the nonlinear characteristics of thermistors. FAN Tachometer inputs are digital inputs with an acceptable input range of 0V to 5V, and are responsible for measuring the FANs Tachometer pulse periods. The EC of the IT8726F provides multiple internal registers and an interrupt generator for programmers to monitor the environment and control the FANs. Both the LPC Bus and Serial Bus interfaces are supported to accommodate the needs for various applications. www.ite.com.tw IT8726F V0.3 80

Functional Description
9.6.1 Interfaces

LPC Bus: The Environment Controller of the IT8726F decodes two addresses. Table 9-2. Address Map on the LPC Bus Registers or Ports Address register of the EC Data register of the EC Address Base+05h Base+06h

Note 1: The Base Address is determined by the Logical Device configuration registers of the Environment Controller (LDN=04h, registers index=60h, 61h). To access an EC register, the address of the register is written to the address port (Base+05h). Read or write data from or to that register via data port (Base+06h). 9.6.2 9.6.2.1 Bit 7 6-0 Registers Address Port (Base+05h, Default=00h): Description Outstanding; read only This bit is set when a data write is performed to Address Port via the LPC Bus. Index: Internal Address of RAM and Registers.

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IT8726F
Table 9-3. Environment Controller Registers Index 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1Ah 1Bh 1Ch 1Dh 20h 21h 22h R/W R/W R R R R/W R/W R/W R/W R/W R/W R R/W R/W R R R R/W R/W R/W R/W R/W R/W R/W R/W R R R R/W R/W R/W R R R Default 18h 00h 00h 00h 00h 00h 00h 00h 00h 80h 09h 00h 07h 50h 40h/60h 00h/20h/ FAN_CTL2 PWM Control Register 40h/60h 00h/20h/ FAN_CTL3 PWM Control Register 40h/60h Fan Tachometer 1 Extended Reading Register Fan Tachometer 2 Extended Reading Register Fan Tachometer 3 Extended Reading Register Fan Tachometer 1 Extended Limit Register Fan Tachometer 2 Extended Limit Register Fan Tachometer 3 Extended Limit Register VIN0 Voltage Reading Register VIN1 Voltage Reading Register VIN2 Voltage Reading Register 82 IT8726F V0.3 Configuration Interrupt Status 1 Interrupt Status 2 Interrupt Status 3 SMI# Mask 1 SMI# Mask 2 SMI# Mask 3 Interrupt Mask 1 Interrupt Mask 2 Interrupt Mask 3 VID Register Fan PWM Smoothing Step Frequency SelectionTachometer Divisor Register Fan Tachometer 16-bit Counter Enable Register Fan Tachometer 1 Reading Register Fan Tachometer 2 Reading Register Fan Tachometer 3 Reading Register Fan Tachometer 1 Limit Register Fan Tachometer 2 Limit Register Fan Tachometer 3 Limit Register Fan Controller Main Control Register FAN_CTL Control Register Registers or Action

00h/20h/ FAN_CTL1 PWM Control Register

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Functional Description
Index 23h 24h 25h 26h 27h 28h 29h 2Ah 2Bh 30h 31h 32h 33h 34h 35h 36h 37h 38h 39h 3Ah 3Bh 3Ch 3Dh 3Eh 3Fh 40h 41h 42h 43h 44h 45h 48h 50h 51h 52h 53h 54h R/W R R R R R R R R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Default 00h 00h 7Fh 7Fh 7Fh Registers or Action VIN3 Voltage Reading Register VIN4 Voltage Reading Register VIN5 Voltage Reading Register VIN6 Voltage Reading Register VIN7 Voltage Reading Register VBAT Voltage Reading Register TMPIN1 Temperature Reading Register TMPIN2 Temperature Reading Register TMPIN3 Temperature Reading Register VIN0 High Limit Register VIN0 Low Limit Register VIN1 High Limit Register VIN1 Low Limit Register VIN2 High Limit Register VIN2 Low Limit Register VIN3 High Limit Register VIN3 Low Limit Register VIN4 High Limit Register VIN4 Low Limit Register VIN5 High Limit Register VIN5 Low Limit Register VIN6 High Limit Register VIN6 Low Limit Register VIN7 High Limit Register VIN7 Low Limit Register TMPIN1 High Limit Register TMPIN1 Low Limit Register TMPIN2 High Limit Register TMPIN2 Low Limit Register TMPIN3 High Limit Register TMPIN3 Low Limit Register Reserved ADC Voltage Channel Enable Register ADC Temperature Channel Enable Register TMPIN1 Thermal Output Limit Register TMPIN2 Thermal Output Limit Register TMPIN3 Thermal Output Limit Register 83 IT8726F V0.3

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IT8726F
Index 55h 56h 57h 58h 59h 5Bh 5Ch 5Dh 5Eh 5Fh 60h 61h 62h 63h 64h 65h 68h 69h 6Ah 6Bh 6Ch 6Dh 70h 71h 72h 73h 74h 75h 80h 81h 82h 83h 84h 85h 86h R/W R/W R/W R/W R R/W R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R R R R R/W R/W R/W Default 00h 00h 00h 90h 00h 12h 00h 00h 00h 00h 7Fh 7Fh 7Fh 00h 00h 7Fh 7Fh 7Fh 7Fh 00h 00h 7Fh 7Fh 7Fh 7Fh 00h 00h 7Fh Registers or Action ADC Temperature Extra Channel Enable Register Thermal Diode 1 Zero Degree Adjust Register Thermal Diode 2 Zero Degree Adjust Register ITE Vendor ID Register Thermal Diode 3 Zero Degree Adjust Register Core ID Register Beep Event Enable Register Beep Frequency Divisor of Fan Event Register Beep Frequency Divisor of Voltage Event Register Beep Frequency Divisor of Temperature Event Register FAN_CTL1 SmartGuardian Automatic Mode Temperature Limit of OFF Register FAN_CTL1 SmartGuardian Automatic Mode Temperature Limit of Fan Start Registers Reserved Registers FAN_CTL1 SmartGuardian Automatic Mode Start PWM Registers FAN_CTL1 SmartGuardian Automatic Mode Control Registers FAN_CTL1 SmartGuardian Automatic Mode -Temperature Registers FAN_CTL2 SmartGuardian Automatic Mode Temperature Limit of OFF Register FAN_CTL2 SmartGuardian Automatic Mode Temperature Limit of Fan Start Registers Reserved Registers FAN_CTL2 SmartGuardian Automatic Mode Start PWM Registers FAN_CTL2 SmartGuardian Automatic Mode Control Registers FAN_CTL2 SmartGuardian Automatic Mode -Temperature Registers FAN_CTL3 SmartGuardian Automatic Mode Temperature Limit of OFF Register FAN_CTL3 SmartGuardian Automatic Mode Temperature Limit of Fan Start Registers Reserved Registers FAN_CTL3 SmartGuardian Automatic Mode Start PWM Registers FAN_CTL3 SmartGuardian Automatic Mode Control Registers FAN_CTL3 SmartGuardian Automatic Mode -Temperature Registers Fan Tachometer 4 Reading LSB Register Fan Tachometer 4 Reading MSB Register Fan Tachometer 5 Reading LSB Register Fan Tachometer 5 Reading MSB Register Fan Tachometer 4 Limit LSB Register Fan Tachometer 4 Limit MSB Register Fan Tachometer 5 Limit LSB Register 84 IT8726F V0.3

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Functional Description
Index 87h 88h 89h 8Bh 8Ch 8Dh 8Eh 8Fh 90h 91h 92h 93h 94h 95h 98h 99h 9Ah 9Bh 9Ch 9Dh 9.6.2.2 9.6.2.2.1 Bit 7 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Default 00h 00h -0h 02h 00h 99h 99h 7Fh 7Fh 7Fh 00h 00h 7Fh 7Fh 7Fh 7Fh 00h 00h 7Fh Registers or Action Fan Tachometer 5 Limit MSB Register FAN_CTL4 PWM Control Register FAN_CTL5 PWM Control Register External Temperature Sensor Host Status Register External Temperature Sensor Host Control Register External Temperature Sensor Host Command Register External Temperature Sensor Transmit Slave Address Register External Temperature Sensor Host Data Register FAN_CTL4 SmartGuardian Automatic Mode Temperature Limit of OFF Register FAN_CTL4 SmartGuardian Automatic Mode Temperature Limit of Fan Start Registers Reserved Registers FAN_CTL4 SmartGuardian Automatic Mode Start PWM Registers FAN_CTL4 SmartGuardian Automatic Mode Control Registers FAN_CTL4 SmartGuardian Automatic Mode -Temperature Registers FAN_CTL5 SmartGuardian Automatic Mode Temperature Limit of OFF Register FAN_CTL5 SmartGuardian Automatic Mode Temperature Limit of Fan Start Registers Reserved Registers FAN_CTL5 SmartGuardian Automatic Mode Start PWM Registers FAN_CTL5 SmartGuardian Automatic Mode Control Registers FAN_CTL5 SmartGuardian Automatic Mode -Temperature Registers

Register Description Configuration Register (Index=00h, Default=18h) R/W R/W Description Initialization A 1 restores all registers to their individual default values, except the Serial Bus Address register. This bit clears itself when the default value is 0. Update VBAT Voltage Reading COPEN# cleared Write 1 to clear COPEN# Read Only, Always 1. INT_Clear A 1 disables the SMI# and IRQ outputs with the contents of interrupt status bits remain unchanged. IRQ enables the IRQ Interrupt output SMI# Enable A 1 enables the SMI# Interrupt output.

6 5 4 3

R/W R/W R R/W

2 1

R/W R/W

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IT8726F
0 Start A 1 enables the startup of monitoring operations while a 0 sends the monitoring operation in the STANDBY mode. Interrupt Status Register 1 (Index=01h, Default=00h) R/W

9.6.2.2.2

Reading this register will clear itself following a read access. Bit 7 6 5 4 3-0 9.6.2.2.3 R/W R R R R R Description Reserved A 1 indicates the FAN_TAC5 Count limit has been reached. Reserved A 1 indicates a Case Open event has occurred. A 1 indicates the FAN_TAC4-1 Count limit has been reached.

Interrupt Status Register 2 (Index=02h, Default=00h)

Reading this register will clear itself after the read operation is completed. Bit 7-0 9.6.2.2.4 R/W R Description A 1 indicates a High or Low limit of VIN7-0 has been reached.

Interrupt Status Register 3 (Index=03h, Default=00h)

Reading this register will clear itself following a read access. Bit 7-3 2-0 9.6.2.2.5 Bit 7 6 5 4 3-0 9.6.2.2.6 Bit 7-0 9.6.2.2.7 Bit 7-3 2-0 R/W R R Description Reserved A 1 indicates a High or Low limit of Temperature 3-1 has been reached.

SMI# Mask Register 1 (Index=04h, Default=00h) R/W R/W R/W R/W R/W R/W Description Reserved A 1 disables the FAN_TAC5 interrupt status bit for SMI#. Reserved A 1 disables the Case Open Intrusion interrupt status bit for SMI#. A 1 disables the FAN_TAC4-1 interrupt status bit for SMI#.

SMI# Mask Register 2 (Index=05h, Default=00h) R/W R/W Description A 1 disables the VIN7-0 interrupt status bit for SMI#.

SMI# Mask Register 3 (Index=06h, Default=00h) R/W R/W R/W Description Reserved A 1 disables the Temperature 3-1 interrupt status bit for SMI#.

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Functional Description
9.6.2.2.8 Bit 7 6 5 4 3-0 9.6.2.2.9 Bit 7-0 9.6.2.2.10 Bit 7 6-3 2-0 9.6.2.2.11 Bit 7 Interrupt Mask Register 1 (Index=07h, Default=00h) R/W R/W R/W R/W R/W R/W Description Reserved A 1 disables the FAN_TAC5 interrupt status bit for IRQ. Reserved A 1 disables the Case Open Intrusion interrupt status bit for IRQ. A 1 disables the FAN_TAC4-1 interrupt status bit for IRQ.

Interrupt Mask Register 2 (Index=08h, Default=00h) R/W R/W Description A 1 disables the VIN7-0 interrupt status bit for IRQ.

Interrupt Mask Register 3 (Index=09h, Default=80h) R/W R/W R/W R/W Description A 1 disables the External Thermal Sensor interrupt. Reserved A 1 disables the Temperature 3-1 interrupt status bit for IRQ.

VID Register (Index=0Ah) R/W R/W Description Pseudo-EOC (end of conversion of ADC) A Pseudo-EOC bit can speed up the FAN speed setup time in SmartGuardian automatic mode. (Write the bit to 1 then write 0) External Thermal Sensor Host Enable 0: Disable 1: Enable VID5-0 Inputs

R/W

5-0 9.6.2.2.12 Bit 7-6

Fan PWM Smoothing Step Frequency Selection Register (Index=0Bh, Default=09h) R/W R/W Description FAN PWM Smoothing Step Frequency Selection 00: 1KHz 01: 256Hz 10: 64Hz 11: 16Hz Reserved

5-0

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IT8726F
9.6.2.2.13 Bit 7 Fan Tachometer 16-bit Counter Enable Register (Index=0Ch, Default=00h) R/W R/W Description TMPIN3 Enhanced Interrupt Mode Enable 0: Original mode 1: The interrupt will be generated when the TMPIN3 is higher than the high limit or lower than the low limit. TMPIN2 Enhanced Interrupt Mode Enable 0: Original mode 1: The interrupt will be generated when the TMPIN2 is higher than the high limit or lower than the low limit. FAN_TAC5 Enable 0: Disable 1: Enable FAN_TAC4 Enable 0: Disable 1: Enable TMPIN1 Enhance Interrupt Mode Enable 0: Original mode. 1: The interrupt will be generated when the TMPIN1 is higher than the high limit or lower than the low limit. FAN_TAC3, 16-bit Counter Divisor Enable 0: disable 1: enable FAN_TAC2 16-bit Counter Divisor Enable 0: Disable 1: Enable FAN_TAC1 16-bit Counter Divisor Enable 0: Disable 1: Enable

R/W

R/W

R/W

R/W

2 1 0

R/W R/W R/W

9.6.2.2.14 Bit 7-0 9.6.2.2.15 Bit 7-0

Fan Tachometer 1-3 Reading Registers (Index=0Dh-0Fh) R/W R Description The number of counts of the internal clock per revolution.

Fan Tachometer 1-3 Limit Registers (Index=10h-12h) R/W R/W Description Limit Value

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Functional Description
9.6.2.2.16 Bit 7 6-4 Fan Controller Main Control Register (Index=13h, Default=07h) R/W R R/W Description Reserved FAN_TAC3-1 Enable 0: Disable 1: Enable Reserved FAN_CTL3-1 Output Mode Selection 0: ON/OFF mode 1: SmartGuardian mode

3 2-0

R/W R/W

9.6.2.2.17 Bit 7

FAN_CTL Control Register (Index=14h, Default=50h) ( for FAN1, 3, 4, 5) R/W R/W Description FAN_CTL Polarity 0: Active low 1: Active high PWM base clock select 000: 48Mhz(PWM Frequency=375Khz). 001: 24Mhz(PWM Frequency=187.5Khz). 010: 12Mhz(PWM Frequency=93.75Khz) 011: 8Mhz(PWM Frequency=62.5Khz) 100: 6Mhz(PWM Frequency=46.875Khz) 101: 3Mhz(PWM Frequency=23.43Khz) 110: 1.5Mhz(PWM Frequency=11.7Khz) 111: 0.75Mhz(PWM Frequency=5.86Khz). PWM Minimum Duty Select 0: 0 %. For a given PWM value, the actual duty is PWM/128 X 100%. 1: 20 %. For a given PWM value (not 00h), the actual duty is (PWM+32)/160 X 100%. If the given PWM value is 00h, the actual duty will be 0%. FAN_CTL3-1 ON/OFF Mode Control These bits are only available when the relative output modes are selected in ON/OFF mode. 0: OFF 1: ON

6-4

R/W

R/W

2-0

R/W

9.6.2.2.18

FAN_CTL1 PWM Control Register (Index=15h, Default=00h/20h/40h/60h)

This default value of this register is selected by JP5 and JP7. Bit 7 R/W R/W Description FAN_CTL1 PWM mode Automatic/Software Operation Selection 0: Software operation. 1: Automatic operation. 128 steps of PWM control when in Software operation (bit 7=0), or Temperature input selection when in Automatic operation (bit 7=1). Bits[1:0]: 00: TMPIN1 01: TMPIN2 10: TMPIN3 11: Reserved 89 IT8726F V0.3

6-0

R/W

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IT8726F
9.6.2.2.19 FAN_CTL2 PWM Control Register (Index=16h, Default=00h/20h/40h/60h)

This default value of this register is selected by JP5 and JP7. Bit 7 R/W R/W Description FAN_CTL2 PWM mode Automatic/Software Operation Selection 0: Software Operation 1: Automatic Operation 128 steps of PWM control when in Software operation (bit 7=0), or Temperature input selection when in Automatic operation (bit 7=1). Bits[1:0]: 00: TMPIN1 01: TMPIN2 10: TMPIN3 11: Reserved

6-0

R/W

9.6.2.2.20

FAN_CTL3 PWM Control Register (Index=17h, Default=00h/20h/40h/60h)

This default value of this register is selected by JP5 and JP7. Bit 7 R/W R/W Description FAN_CTL3 PWM mode Automatic/Software Operation Selection 0: Software Operation 1: Automatic Operation 128 steps of PWM control when in Software operation (bit 7=0), or Temperature input selection when in Automatic operation (bit 7=1). Bits[1:0]: 00: TMPIN1 01: TMPIN2 10: TMPIN3 11: Reserved

6-0

R/W

9.6.2.2.21 Bit 7-0 9.6.2.2.22 Bit 7-0 9.6.2.2.23 Bit 7-0

Fan Tachometer 1-3 Extended Reading Registers (Index=18h-1Ah) R/W R Description The number of counts of the internal clock per revolution. [15:8]

Fan Tachometer 1-3 Extended Limit Registers (Index=1Bh-1Dh) R/W R Description Limit Value. [15:8]

VIN7-VIN0 Voltage Reading Registers (Index=27h-20h) R/W R Description Voltage Reading Values

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9.6.2.2.24 Bit 7-0 9.6.2.2.25 Bit 7-0 9.6.2.2.25.1 Bit 7-0 9.6.2.2.26 Bit 7-0 9.6.2.2.27 Bit 7-0 9.6.2.2.28 Bit 7-0 9.6.2.2.29 Bit 7-0 9.6.2.2.30 VBAT Voltage Reading Register (Index=28h) R/W R Description VBAT Voltage Reading Value

TMPIN3-1 Temperature Reading Registers (Index=2Bh-29h) R/W R Description Temperature Reading Values

VIN7-0 High Limit Registers (Index=3Eh, 3Ch, 3Ah, 38h, 36h, 34h, 32h, 30h) R/W R/W Description High Limit Value

VIN7-0 Low Limit Registers (Index=3Fh, 3Dh, 3Bh, 39h, 37h, 35h, 33h, 31h) R/W R/W Description Low Limit Value

TMPIN3-1 High Limit Registers (Index=44h, 42h, 40h) R/W R/W Description High Limit Value

TMPIN3-1 Low Limit Registers (Index=45h, 43h, 41h) R/W R/W Description Low Limit value

ADC Voltage Channel Enable Register (Index=50h, Default=00h) R/W R/W Description ADC VIN7-VIN0 Scan Enable

ADC Temperature Channel Enable Register (Index=51h, Default=00h)

TMPIN3-1 cannot be enabled in both Thermal Resistor mode and Thermal Diode (Diode connected Transistor) mode. Bit 7-6 5-3 2-0 R/W R/W R/W R/W Description Reserved TMPIN3-1 is enabled in Thermal Resistor mode. TMPIN3-1 is enabled in Thermal Diode (or Diode-connected Transistor) mode.

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9.6.2.2.31 Bit 7-0 9.6.2.2.32 Bit 7 TMPIN3-1 Thermal Output Limit Registers (Index=54h-52h, Default=7Fh) R/W R/W Description Thermal Output Limit Value

ADC Temperature Extra Channel Enable Register (Index=55h, Default=00h) R/W R/W Description TEMPIN3 Temperature Reading Source Selection 0: TEMPIN3 thermal sensor 1: External Temperature Sensor Host FAN_CTRL2 PWM base clock select. 000: 48Mhz(PWM Frequency=375Khz) 001: 24Mhz(PWM Frequency=187.5Khz) 010: 12Mhz(PWM Frequency=93.75Khz) 011: 8Mhz(PWM Frequency=62.5Khz) 100: 6Mhz(PWM Frequency=46.875Khz) 101: 3Mhz(PWM Frequency=23.43Khz) 110: 1.5Mhz(PWM Frequency=11.7Khz) 111: 0.75Mhz(PWM Frequency=5.86Khz) FAN_CTRL2 PWM Minimum Duty Select. 0: 0 %. For a given PWM value, the actual duty is PWM/128 X 100%. 1: 20 %. For a given PWM value (not 00h), the actual duty is (PWM+32)/160 X 100%. If the given PWM value is 00h, the actual duty will be 0%. VIN6-4 is enabled in Thermal Resistor mode.

6-4

R/W

R/W

2-0

R/W

9.6.2.2.33 Thermal Diode Zero Degree Adjust 1 Register (Index=56h, Default=00h) This register is read only unless the bit 7 of 5Ch is set. Bit 7-0 R/W R/W Description Thermal Diode 1 Zero Degree Voltage Value

9.6.2.2.34 Thermal Diode Zero Degree Adjust 2 Register (Index=57h, Default=00h) This register is read only unless the bit 7 of 5Ch is set. Bit 7-0 9.6.2.2.35 Bit 7-0 R/W R/W Description Thermal Diode 2 Zero Degree Voltage Value

Vendor ID Register (Index=58h, Default=90h) R/W R Description ITE Vendor ID. Read Only

9.6.2.2.36 Thermal Diode Zero Degree Adjust 3 Register (Index=59h, Default=00h) This register is read only unless the bit 7 of 5Ch is set. Bit 7-0 R/W R/W Description Thermal Diode 3 Zero Degree Voltage Value 92 IT8726F V0.3

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Functional Description
9.6.2.2.37 Bit 7-0 9.6.2.2.38 Bit 7 6-3 2 1 0 9.6.2.2.39 Bit 7-4 3-0 9.6.2.2.40 Bit 7-4 3-0 9.6.2.2.41 Bit 7-4 3-0 9.6.2.2.42 Code ID Register (Index=5Bh, Default=12h) R/W R Description ITE Vendor ID. Read Only

Beep Event Enable Register (Index=5Ch, Default=00h) R/W R/W R/W R/W R/W R/W Description Thermal Diode Zero Degree Adjust register write enable. Reserved Enables Beep action when TMPINs exceed limit. Enables Beep action when VINs exceed limit. Enables Beep action when FAN_TACs exceed limit.

Beep Frequency Divisor of Fan Event Register (Index=5Dh, Default=00h) R/W R/W R/W Description Tone Divisor. Tone=500/(bits[7:4]+1). Frequency Divisor. Frequency=10K/(bits[3:0]+1).

Beep Frequency Divisor of Voltage Event Register (Index=5Eh, Default=00h) R/W R/W R/W Description Tone Divisor. Tone=500/(bits[7:4]+1). Frequency Divisor. Frequency=10K/(bits[3:0]+1).

Beep Frequency Divisor of Temperature Event Register (Index=5Fh, Default=00h) R/W R/W R/W Description Tone Divisor. Tone=500/(bits[7:4]+1). Frequency Divisor. Frequency=10K/(bits[3:0]+1).

FAN_CTL3-1 SmartGuardian Automatic Mode Temperature Limit of OFF Registers (Index=70h, 68h, 60h, Default=7Fh) R/W R/W Description Temperature Limit Value of Fan OFF

Bit 7-0 9.6.2.2.43

FAN_CTL3-1 SmartGuardian Automatic Mode Temperature Limit of Fan Start Registers (Index=71h, 69h, 61h, Default=7Fh) R/W R/W Description Temperature Limit Value of Fan Start

Bit 7-0

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9.6.2.2.44 FAN_CTL3-1 SmartGuardian Automatic Mode Start PWM Registers (Index=73h, 6Bh, 63h, Default=00h) R/W R/W R/W Description Slope PWM bit[6] Please refer to the description of SmartGuardian Automatic Mode Control Register. Start PWM Value

Bit 7 6-0 9.6.2.2.45

FAN_CTL3-1 SmartGuardian Automatic Mode Control Registers (Index=74h, 6Ch, 64h, Default=00h) R/W R/W Description FAN Smoothing This bit enables the FAN PWM smoothing changing. 0: Disable 1: Enable Reserved Slope PWM bit[5:0] Slope = (Slope PWM bit[6:3] + Slope PWM bit[2:0] / 8) PWM value/

Bit 7

6 5-0

R/W R/W

9.6.2.2.46

FAN_CTL3-1 SmartGuardian Automatic Mode -Temperature Registers (Index=75h, 6Dh, 65h, Default=7Fh) R/W R/W Description Direct-Down Control This bit selects the PWM linear changing decreasing mode. 0: Slow decreasing mode 1: Direct decreasing mode Reserved -Temperature interval [4:0]

Bit 7

6-5 4-0 9.6.2.2.47 Bit 7-0 9.6.2.2.48 Bit 7-0

R/W

Fan Tachometer 4-5 Reading LSB Registers (Index=80h,82h) R/W R Description The number of counts of the internal clock per revolution.

Fan Tachometer 4-5 Reading MSB Registers (Index=81h,83h) R/W R Description The number of counts of the internal clock per revolution.

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9.6.2.2.49 Bit 7-0 9.6.2.2.50 Bit 7-0 Fan Tachometer 4-5 Limit LSB Registers (Index=84h,86h) R/W R/W Description Limit Value

Fan Tachometer 4-5 Limit MSB Registers (Index=85h,87h) R/W R/W Description Limit Value

9.6.2.2.51 FAN_CTL4 PWM Control Register (Index=88h, Default=00h) Bit 7 R/W R/W Description FAN_CTL4 PWM mode Automatic/Software Operation Selection 0: Software Operation 1: Automatic Operation 128 steps of PWM control when in Software operation (bit 7=0), or Temperature input selection when in Automatic operation (bit 7=1). Bits[1:0]: 00: TMPIN1 01: TMPIN2 10: TMPIN3 11: Reserved

6-0

R/W

9.6.2.2.52 FAN_CTL5 PWM Control Register (Index=89h, Default=00h) Bit 7 R/W R/W Description FAN_CTL5 PWM mode Automatic/Software Operation Selection 0: Software Operation 1: Automatic Operation 128 steps of PWM control when in Software operation (bit 7=0), or Temperature input selection when in Automatic operation (bit 7=1). Bits[1:0]: 00: TMPIN1 01: TMPIN2 10: TMPIN3 11: Reserved

6-0

R/W

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9.6.2.2.53 Bit 7 6 5 4 External Temperature Sensor Host Status Register (Index=8Bh, Default=---00000b) R/W R R R R/WC Description I/F DATA (ETSDAT_IN) This bit reports the pin status of ETSDAT (pin 53). I/F CLK (ETSCLK_IN) This bit reports the pin status of ETSCLK (pin 55). Reserved Failed (FAIL) Writing a 1 to it clears this bit. 0: No failure 1: A failure occurs because a KILL is given. Bus Error (BSER) Writing a 1 to it clears this bit. When the thermal host is not in AMDSI mode (bit3 of 8Ch = 0), this bit reports the bus loses arbitration. 0: No Bus Error 1: There are bus errors. Device Error (DVER) Writing a 1 to it clears this bit. In AMDSI mode, it reports valid bit of Data phase. If this bit is 0(valid data =0), the data is valid. If this bit is 1 (valid data=1), the slave device indicates it is not read to respond or the slave does not support that command. 0: No Device Error 1: This bit is set when one of the following conditions happen: (1) Illegal Command Field (2) 25ms Time-out Error. (3) No Response ACK Finish (FNSH) Writing a 1 to it clears this bit. 0: None 1: This bit is set when the stop condition is detected. HOST Busy (BUSY) 0: Current transaction is completed 1: This bit is set while the command is in operation.

R/WC

R/WC

R/WC

9.6.2.2.54 Bit 7-6

External Temperature Sensor Host Control Register (Index=8Ch, Default=02h) R/W

R/W

Description Auto-Start Control (Auto-START) The host will start the transaction in a regular rate automatically. 00: 32 Hz 01: 16 Hz 10: 8 Hz 11: 4 Hz Auto-Start (Auto-START) 0: Disable auto-start. 1: Enable auto-start. The host will start the transaction in a regular rate, determined in bits [6:5] automatically. SMBCLK Control (SMBCLK_CTL) 0: SMBCLK will perform as normal function. 1: Force SMBCLK low. AMDSI Enable (AMDSIEN) The host controller should be enabled. (SMHEN) 0: Disable 1: Enable IT8726F V0.3 96

R/W

4 3

R/W R/W

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Functional Description
Bit 2-1 R/W R/W Description Host Command (HCMD) These bits select the host command type. In SMBUS mode, the external temperature sensor host only supports four types of commands, Send/Receive Byte and Write/Read Byte. Bit 0 of the Transmit Slave Address Register determines if the command is a read or write. In AMDSI mode, the host supports two types, 8-bit and 16-bit data size commands. 00: Send Byte/Receive Byte 01: Write Byte/Read Byte Others: Reserved Start (START) This bit is write-only. Writing 0 to it during transaction will issue a kill process. And, bit4 of 8Bh register will be set. Writing 1 to it during NOT BUSY state (bit0 of 8Bh = 0) will start a transaction. Writing 1 to it during BUSY state (bit0 of 8Bh = 1) will not issue any transaction. So, the programmer should check the BUSY status before issuing a transaction. 0: This bit always returns 0 when read. 1: When this bit is set, the host controller will perform the transaction.

R/W

9.6.2.2.55 Bit 7-0

External Temperature Sensor Host Command Register (Index=8Dh, Default=00h) R/W R/W Description Host Command Register (HCMD [7:0]) This register is the command field of the protocol. In SMBUS mode, it is the command code byte. In AMDSI mode, it is Command field. If the host controller is busy, programmer does not change the value of this register, or the host will send the wrong command. If the value is out of definition (for example, 03h to FFh for AMDSI protocol), the host will transfer it as the normal value. No any error will be found from the host controller.

9.6.2.2.56 Bit 7-1 0

External Temperature Sensor Transmit Slave Address Register (Index=8Eh, Default=99h) R/W R/W R/W Description Slave Address (SLADR[7:1]) or Second Data [7:1] (in AMDSI mode) Address of the target slave. Direction (DIR) or Second Data [0] (in AMDSI mode) Direction of the host command 0: Write 1: Read

9.6.2.2.57 Bit 7-0

External Temperature Sensor Host Data Register (Index=8Fh, Default=99h) R/W R/W Description Data Register (HODATA [7:0]) This register(Bits[7:0]) is the Data field for SMBUS mode or the first data field for AMDSI. In SMBUS mode, this register is bi-directional. It is output data field when the command type is send/write byte, and is read data when the command type is receive/read byte. If the host controller is busy, programmer does not change the value of this register, or the host will send the wrong command. In AMDSI mode, this register will latch the LSB byte data of 16-bit data size command or the data byte of 8-bit data size command.

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9.6.2.2.58 FAN_CTL5-4 SmartGuardian Automatic Mode Temperature Limit of OFF Registers (Index=98h, 90h, Default=7Fh) R/W R/W Description Temperature Limit Value of Fan OFF.

Bit 7-0 9.6.2.2.59

FAN_CTL5-4 SmartGuardian Automatic Mode Temperature Limit of Fan Start Registers (Index=99h, 91h, Default=7Fh) R/W R/W Description Temperature Limit Value of Fan Start

Bit 7-0 9.6.2.2.60

FAN_CTL5-4 SmartGuardian Automatic Mode Start PWM Registers (Index=9Bh, 93h, Default=00h) R/W R/W R/W Description Slope PWM bit[6] Please refer to the description of SmartGuardian Automatic Mode Control Register. Start PWM Value

Bit 7 6-0 9.6.2.2.61

FAN_CTL5-4 SmartGuardian Automatic Mode Control Registers (Index=9Ch, 94h, Default=00h) R/W R/W Description FAN Smoothing This bit enables the FAN PWM smoothing changing. 0: Disable 1: Enable Fan Spin-up Feedback enables This bit enables FAN_TAC reading to stop the spin-up of FAN_CTL. 0: Disable 1: Enable Slope PWM bit[5:0] Slope = (Slope PWM bit[6:3] + Slope PWM bit[2:0] / 8) PWM value/

Bit 7

R/W

5-0

R/W

9.6.2.2.62

FAN_CTL5-4 SmartGuardian Automatic Mode -Temperature Registers (Index=9Dh, 95h, Default=7Fh) R/W R/W Description Direct-Down Control This bit selects the PWM linear changing decreasing mode. 0: Slow decreasing mode. 1: Direct decreasing mode. Reserved -Temperature interval [4:0].

Bit 7

6-5 4-0

R/W

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9.6.3 9.6.3.1 Operation Power On RESET and Software RESET

When the system power is first applied, the EC performs a power on reset on the registers which are returned to default values (due to system hardware reset), and the EC will acquire a monitored value before it goes inactive. The ADC is active to monitor the VBAT pin and then goes inactive. Except the function of the Serial Bus Interface Address register, software reset (bit 7 of Configuration register) is able to accomplish all the functions as the hardware reset does. 9.6.3.2 Starting Conversion

The monitoring function in the EC is activated when the bit 3 of Configuration Register is cleared (low) and bit 0 of Configuration Register is set (high). Otherwise, several enable bits should be set to enable the monitoring function. Those enable bits are categorized into three groups: positive voltages, temperatures and FAN Tachometer inputs. Before the EC monitoring function can be used, the steps below should be followed: 1. 2. 3. Set the Limits Set the interrupt Masks Set the Enable bits

The EC monitoring process can then be started.

VREF
Rc=10 K

Tin TD TD-

Tin TD TD-

Tin Rt

TMPIN1 TMPIN2 TMPIN3

VS
(-12V,-5V)

Vin Rin Rf VREF

Vin

VS

Vin Ra Rb
Battery Voltage

VIN0 VIN1 VIN2 VIN3 VIN4 VIN5 VIN6 VIN7 VBAT

ADC and MUX

Figure 9-4. Application Example. Resistor should provide approximately 2V at the Analog Inputs.

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9.6.3.3 Voltage and Temperature Inputs

The 8-bit ADC has a 16mV LSB, with a 0V to 4.096V input range. The 2.5V and 3.3V supplies of PC applications can be directly connected to the inputs. The 5V and 12V inputs should be divided into the acceptable range. When the divided circuit is used to measure the positive voltage, the recommended range for Ra and Rb is from 10K to 100K. The negative voltage can be measured by the same divider unless the divider is connected to VREF (constant voltage, 4.096V), not ground. The temperature measurement system of the EC converts the voltage of the TMPINs to 8-bit twos-complement. The system also includes an OP amp providing a constant voltage. It also additionally includes an external thermistor, a constant resistance, the ADC and a conversion table ROM.
Temperature Digital Output Format Binary Hex

+ 125C + 25C + 1 C + 0 C - 1 C - 25C - 55C

01111101 00011001 00000001 00000000 11111111 11100111 11001001

7Dh 19h 01h 00h FFh E7h C9h

With the addition of the external application circuit, the actual voltages are calculated as below: Positive Voltage: Vs = Vin X (Ra+Rb) / Rb Negative Voltage: Vs = (1+Rin/Rf) X Vin (Rin/Rf) X VREF All the analog inputs are equipped with the internal diodes that clamp the input voltage exceeding the power supply and ground. But, the current limiting input resistor is recommended since no dividing circuit is available.
9.6.3.4 Layout and Grounding

A separate and low-impedance ground plane for analog ground is needed in achieving accurate measurement. The analog ground also provides a ground point for the voltage dividers including the temperature loops and analog components. Analog components such as voltage dividers, feedback resistors and the constant resistors of the temperature loops should be located as close as possible to the IT8726F. But, the thermistors of the temperature loops should be positioned within the measuring area. In addition, the power supply bypass, and the parallel combination of 10F and 0.1F bypass capacitors connected between AVCC and ground, should also be located as close as possible to the IT8726F. Due to the small differential voltage of thermal diode (diode-connected transistor), there are many PCB layouts recommendations:

Position the sensor as close as possible Ground of the sensor should be directly short to GNDA with excellent noise immunity Keep trace away from the noise source. (High voltage, fast data bus, fast clock, CRTs ) Wider trace width (10 mil at least) and guard ground (flanking and under) are recommended Position 10uF and 0.1F bypass capacitors as close to IT8726F AVCC as possible

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9.6.3.5 Fan Tachometer

The Fan Tachometer inputs gate a 22.5 kHz clock into an 8-bit or a16-bit counter (maximum count=255 or 65535) for one period of the input signals. Counts are based on 2 pulses per revolution tachometer output. RPM = 1.35 X 106 / (Count X Divisor) ; (Default Divisor = 2) The maximum input signal range is from 0 to VCC. The additional application is needed to clamp the input voltage and current.
9.6.3.6 Interrupt of the EC

The EC generates interrupts as a result of each of its Limit registers on the analog voltage, temperature, and FAN monitor. All the interrupts are indicated in two Interrupt Status Registers. The IRQ and SMI# outputs have individual mask registers. These two Interrupts can also be enabled/disabled in the Configuration Register. The Interrupt Status Registers will be reset after being read. When the Interrupt Status Registers are cleared, the Interrupt lines will also be cleared. When a read operation is completed before the completion of the monitoring loop sequence, it indicates an Interrupt Status Register has been cleared. Due to slow monitoring sequence, the EC needs 1.5 seconds to allow all the EC Registers to be safely updated between completed read operations. When the bit 3 of the Configuration Register is set to high, the Interrupt lines are cleared and the monitoring loop will be stopped. The loop will resume when this bit is cleared. All the analog voltage inputs have high and low Limit Registers that generate Interrupts, except that the FAN monitoring inputs only have low Limit Register to warn the host. The IT8726F provides three modes dedicated to temperature interrupts in the EC: Interrupt mode, Enhanced Interrupt mode and Comparator mode.
In Interrupt mode, an interrupt will be generated whenever the temperature exceeds Th limit, and the corresponding Interrupt status bits will be set to high until being reset by reading Interrupt Status Register 3. Once an interrupt event has occurred by crossing Th limit, then after being reset, an interrupt will only occur again when the temperature goes below TL limit. Again, it will set the corresponding status bit to high until being reset by reading the Interrupt Status Register 3. Enhanced interrupt mode. When the enhanced interrupt mode is enabled (bit3, 6 and 7 of EC index 0Ch for TMPIN1, 2, and 3 respectively), the interrupt will generate when the temperature is higher than the high limit or lower than the low limit.

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Th TL Temperature Interrupt
Time (a) Interrupt Mode

Th TL Temperature Interrupt
Time (b) Enhanced Interrupt Mode

TL = 127 C Th Temperature Interrupt

Time (c) Comparator Mode Figure 9-5. Temperature Interrupt Response Diagram When the TL limit register is set to 127C, the temperature interrupts enter the Comparator mode. In this mode, an interrupt will be generated whenever the temperature exceeds the Th limit. The interrupt will also be cleared by reading the Interrupt Status Register 3, but the interrupt will be set again following the completion of another measurement cycle. It will remain set until the temperature goes below the Th limit.
9.6.3.7 FAN Controller FAN_CTLs ON-OFF and SmartGuardian Modes

The IT8726F provides an advanced FAN Controller. Two modes are provided for each controller: ON_OFF and SmartGuardian modes. The former is a logical ON or OFF, and the latter is a PWM output. With the addition of external application circuits the FANs voltage values can be varied easily. There are also two mode options in the SmartGuardian mode: software and automatic modes. In the software mode, the PWM value is subject to the changes in the values of bits 6-0 of FAN_CTL 1-5 PWM Control Registers (Index=15h, 16h, 17h, 88h, 89h). With the application circuits, FAN_CTL can generate 128 steps of voltage. So, the FAN_CTL 1-3 PWM Control Registers can vary the voltage by changing the PWM value. Fan speeds or other
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voltage control cooling device can be varied in 128 steps. In the automatic mode, the PWM value is subject to the temperature inputs by linear changing. When the temperature exceeds a start limit, FAN_CTL spins in a start PWM value (Index 9Bh, 93h,73h, 6Bh, 63h). When the temperature reading is between the Start limit and the full limit (=Ts+(128- Start PWM)/Slope), the PWM value changes depending of the temperature reading if the reading exceeds the right boundary. If the temperature increases X , the PWM value will increase X * K. K (Slope) is a constant value with 4 bits for the integer and 3 bits for the decimal, and is determined in bit7 of FAN_CTL 5-1 SmartGuardian Automatic mode Start PWM register and bits 5-0 of FAN_CTL 5-1 SmartGuardian Automatic mode control registers. Else, if the reading doesnt exceed the right boundary, the PWM value will keep the original value. For example, if PWM is now at a value Pa, it will not change if Tb < the temperature reading < Ta. If the new reading (Tnew) > Ta, the new PWM value will be Start PWM + K * (Tnew Ts). If the new reading < Tb, there are two decreasing mode. If bit 7 of FAN_CTL 5-1 SmartGuardian Automatic mode -Temperature is 0, the new PWM value will be Start PWM + K * ( (Tnew+Ta)/2 Ts). If the bit is 1, the new PWM value will be Start PWM + K * (Tnew Ts). When the temperature is lower than the start limit but larger than the OFF limit (Index 98h, 90h, 70h, 68h, 60h), FAN_CTL will not stop, but keep in start PWM value until the temperature is lower than the OFF limit.

: -Temperature

PWM Duty full

Pa Tb Ta Slope Temperature reading

Start stop
OFF Limit To

Start Limit Ts

Figure 9-6. SmartGuardian Automatic Mode

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9.7 9.7.1 Floppy Disk Controller (FDC) Introduction

The Floppy Disk Controller provides the interface between a host processor and up to two floppy disk drives. It integrates a controller and a digital data separator with write precompensation, data rate selection logic, microprocessor interface, and a set of registers. The FDC supports data transfer rates of 250 Kbps, 300 Kbps, 500 Kbps, and 1 Mbps. It operates in PC/AT mode and supports 3-mode type drives. Additionally, the FDC is software compatible with the 82077. The FDC configuration is handled by software and a set of Configuration registers. Status, Data, and Control registers facilitate the interface between the host microprocessor and the disk drive, providing information about the condition and/or state of the FDC. These configuration registers can select the data rate, enable interrupts, drives, and DMA modes, and indicate errors in the data or operation of the FDC/FDD. The controller manages data transfers using a set of data transfer and control commands. These commands are handled in three phases: Command, Execution, and Result. Not all commands utilize all these three phases.
9.7.2 Reset

The IT8726F device implements both software and hardware reset options for the FDC. Either type of the resets will reset the FDC, terminating all operations and placing the FDC into an idle state. A reset during a write to the disk will corrupt the data and the corresponding CRC.
9.7.3 Hardware Reset (LRESET# Pin)

When the FDC receives a LRESET# signal, all registers of the FDC core are cleared (except those programmed by the SPECIFY command). To exit the reset state, the host must clear the DOR bit.
9.7.4 Software Reset (DOR Reset and DSR Reset)

When the reset bit in the DOR or the DSR is set, all registers of the FDC core are cleared. A reset performed by setting the reset bit in the DOR has higher priority over a reset performed by setting the reset bit in the DSR. In addition, to exit the reset state, the DSR bit is self-clearing, while the host must clear the DOR bit.
9.7.5 Digital Data Separator

The internal digital data separator is comprised of a digital PLL and associated support circuitry. It is responsible for synchronizing the raw data signal read from the floppy disk drive. The synchronized signal is used to separate the encoded clock from the data pulses.
9.7.6 Write Precompensation

Write precompensation is a method that can be used to adjust the effects of bit shift on data as it is written to the disk. It is harder for the data separator to read data that has been subject to bit shifting. Soft read errors can occur due to such bit shifting. Write precompensation predicts where the bit shifting might occur within a data pattern and shifts the individual data bits back to their nominal positions. The FDC permits the selection of write precompensation via the Data Rate Select Register (DSR) bits 2 through 4.
9.7.7 Data Rate Selection

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Selecting one of the four possible data rates for the attached floppy disks is accomplished by setting the Diskette Control Register (DCR) or Data Rate Select Register (DSR) bits to 0 and 1. The data rate is determined by the last value that is written to either the DCR or the DSR. When the data rate is set, the data separator clock is scaled appropriately.
9.7.8 9.7.8.1 Status, Data and Control Registers Digital Output Register (DOR, FDC Base Address + 02h)

This is a read/write register. It controls drive selection and motor enables as well as a software reset bit and DMA enable. The I/O interface reset may be used at any time to clear the DORs contents.
Table 9-4. Digital Output Register (DOR) Bit 7-6 5 Symbol MOTB EN Description Reserved Drive B Motor Enable 0: Disable Drive B motor 1: Enable Drive B motor Drive A Motor Enable 0: Disable Drive A motor 1: Enable Drive A motor Disk Interrupt and DMA Enable 0: Disable disk interrupt and DMA (DRQx, DACKx#, TC and INTx) 1: Enable disk interrupt and DMA FDC Function Reset 0: Reset FDC function 1: Clear reset of FDC function This reset does not affect the DSR, DCR or DOR. Reserved Drive Selection 0: Select Drive A 1: Select Drive B

4 3 2

MOTA EN DMAEN RESET#

1 0

DVSEL

9.7.8.2

Tape Drive Register (TDR, FDC Base Address + 03h)

This is a read/write register and is included for 82077 software compatibility. The contents of this register are not used internal to the device.
Table 9-5. Tape Drive Register (TDR) Bit 7-2 1-0 Symbol Reserved TP_SEL[1:0] Tape Drive Selection TP_SEL[1:0] : Drive selected 00: None 01: 1 10: 2 11: 3 Description

9.7.8.3

Main Status Register (MSR, FDC Base Address + 04h)

This is a read only register. It indicates the general status of the FDC, and is able to receive data from the host. The MSR should be read before each byte is sent to or received from the Data register, except when in www.ite.com.tw IT8726F V0.3 105

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DMA mode.
Table 9-6. Main Status Register (MSR) Bit 7 Symbol RQM Description Request for Master FDC Request for Master 0: The FDC is busy and cannot receive data from the host. 1: The FDC is ready and the host can transfer data. Data I/O Direction Indicates the direction of data transfer once a RQM has been set. 0: Write 1: Read Non-DMA Mode This bit selects Non-DMA mode of operation. 0: DMA mode selected 1: Non-DMA mode selected This mode is selected via the SPECIFY command during the Execution phase of a command. Diskette Control Busy Indicates whether a command is in progress (the FDD is busy). 0: A command has been executed and the end of the Result phase has been reached. 1: A command is being executed. Reserved Drive B Busy Indicates whether Drive B is in the SEEK portion of a command. 0: Not busy 1: Busy Drive A Busy Indicates whether Drive A is in the SEEK portion of a command. 0: Not busy. 1: Busy.

DIO

NDM

CB

3-2 1

DBB

DAB

9.7.8.4

Data Rate Select Register (DSR, FDC Base Address + 04h)

This is a write only register. It is used to determine the data rate, amount of write precompensation, power down mode, and software reset. The data rate of the floppy disk controller is the most recent write of either the DSR or DCR. The DSR is unaffected by a software reset. The DSR can be set to 02h by a hardware reset. The 02h represents the default precompensation, and 250 Kbps indicates the data transfer rate.

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Table 9-7. Data Rate Select Register (DSR) Bit 7 Symbol Description S/W RESET Software Reset It is active high and shares the same function with the RESET# of the DOR except that this bit is self-clearing. POWER Power Down DOWN When this bit is written with a 1, the floppy controller is put into manual low power mode. The clocks of the floppy controller and data separator circuits will be turned off until a software reset or the Data Register or Main Status Register is accessed. Reserved PRE-COMP Precompensation Select 2-0 These three bits are used to determine the value of write precompensation that will be applied to the WDATA# pin. Track 0 is the default starting track number, which can be changed by the CONFIGURE command for precompensation. PRE_COMP Precompensation Delay 0.0 ns 41.7 ns 83.3 ns 125.0 ns 166.7 ns 208.3 ns 250.0 ns Default

5 4-2

111 001 010 011 100 101 110 000

Default Precompensation Delays Data Rate Precompensation Delay 1 Mbps 41.7 ns 500 Kbps 125.0 ns 300 Kbps 125.0 ns 250 Kbps 125.0 ns

1-0

DRATE1-0

Data Rate Select Bits 1-0 00 01 10 11 Data Transfer Rate 500 Kbps 300 Kbps 250 Kbps (default) 1 Mbps

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9.7.8.5 Data Register (FIFO, FDC Base Address + 05h)

This is an 8-bit read/write register. It transfers command information, diskette drive status information, and the result phase status between the host and the FDC. The FIFO consists of several registers in a stack. Only one register in the stack is permitted to transfer information or status to the data bus at a time.
Table 9-8. Data Register (FIFO) Bit 7-0 Symbol Description Data Command information, diskette drive status, or result phase status data

9.7.8.6

Digital Input Register (DIR, FDC Base Address + 07h)

This is a read only register and shares this address with the Diskette Control Register (DCR).
Table 9-9. Digital Input Register (DIR) Bit 7 Symbol DSKCHG Description Diskette Change Indicates the inverting value of the bit monitored from the input of the Floppy Disk Change pin (DSKCHG#). Undefined

6-0
9.7.8.7

Diskette Control Register (DCR, FDC Base Address + 07h)

This is a write only register and shares this address with the Digital Input Register (DIR). The DCR register controls the data transfer rate for the FDC.
Table 9-10. Diskette Control Register (DCR) Bit 7-2 Symbol Description Reserved Always 0 Data Rate Select Bits 1-0 Data Transfer Rate 00 500 Kbps 01 300 Kbps 10 250 Kbps 11 1 Mbps

1-0

DRATE1-0

9.7.9

Controller Phases

The FDC handles data transfers and control commands in three phases: Command, Execution and Result. Not all commands utilize these three phases.
9.7.9.1 Command Phase

Upon reset, the FDC enters the Command phase and is ready to receive commands from the host. The host must verify that MSR bit 7 (RQM) = 1 and MSR bit 6 (DIO) = 0, indicating the FDC is ready to receive data. For each command, a defined set of command code and parameter bytes must be transferred to the FDC in a given order. See sections 11.6.11 and 11.6.12 for details on the various commands. RQM is set false (0) after each byte-Read cycle, and set true (1) when a new parameter byte is required. The Command phase is completed when this set of bytes has been received by the FDC. The FDC automatically enters the next
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controller phase and the FIFO is disabled.
9.7.9.2 Execution Phase

Upon the completion of the Command phase, the FDC enters the Execution phase. It is in this phase that all data transfers occur between the host and the FDC. The SPECIFY command indicates whether this data transfer occurs in DMA or non-DMA mode. Each data byte is transferred via an IRQx or DRQx# based upon the DMA mode. On reset, the CONFIGURE command can automatically enable or disable the FIFO. The Execution phase is completed when all data bytes have been received. If the command executed does not require a Result phase, the FDC is ready to receive the next command.
9.7.9.3 Result Phase

For commands that require data written to the FIFO, the FDC enters the Result phase when the IRQ or DRQ is activated. The MSR bit 7 (RQM) and MSR bit 6 (DIO) must equal 1 to read the data bytes. The Result phase is completed when the host has read each of the defined set of result bytes for the given command. Right after the completion of the phase, RQM is set to 1, DIO is set to 0, and the MSR bit 4 (CB) is cleared, indicating the FDC is ready to receive the next command.
9.7.9.4 Result Phase Status Registers

For commands that contain a Result phase, these read only registers indicate the status of the most recently executed command.
Table 9-11. Status Register 0 (ST0) Bit 7-6 Symbol IC Description Interrupt Code 00: Execution of the command has been completed correctly. 01: Execution of the command began, but failed to complete successfully. 10: INVALID command. 11: Execution of the command was not completed correctly, due to a polling error. Seek End The FDC executed a SEEK or RE-CALIBRATE command. Equipment Check The TRK0# pin was not set after a RE-CALIBRATE command was issued. Not Used Head Address The current head address. Drive B Select Drive A Select

5 4 3 2 1 0

SE EC NU H DSB DSA

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Table 9-12. Status Register 1 (ST1) Bit 7 Symbol EN Description End of Cylinder Indicates the FDC attempted to access a sector beyond the final sector of the track. This bit will be set if the Terminal Count (TC) signal is not issued after a READ DATA or WRITE DATA command. Not Used Data Error A CRC error occurred in either the ID field or the data field of a sector. Overrun/ Underrun An overrun on a READ operation or underrun on a WRITE operation occurs when the FDC is not serviced by the CPU or DMA within the required time interval. Not Used No Data No data are available to the FDC when either of the following conditions is met: The floppy disk cannot find the indicated sector while the READ DATA or READ DELETED DATA commands are executed While executing a READ ID command, an error occurs upon reading the ID field While executing a READ A TRACK command, the FDC cannot find the starting sector Not Writeable Set when a WRITE DATA, WRITE DELETED DATA, or FORMAT A TRACK command is being executed on a write-protected diskette. Missing Address Mark This flag bit is set when either of the following conditions is met: The FDC cannot find a Data Address Mark or a Deleted Data Address Mark on the specified track. The FDC cannot find any ID address on the specified track after two index pulses are detected from the INDEX# pin. Table 9-13. Status Register 2 (ST2) Bit 7 6 Symbol NU CM Description Not Used Control Mark This flag bit is set when either of the following conditions is met: 1. The FDC finds a Deleted Data Address Mark during a READ DATA command 2. The FDC finds a Data Address Mark during a READ DELETED DATA command Data Error in Data Field This flag bit is set when a CRC error is found in the data field. Wrong Cylinder This flag bit is set when the track address in the ID field is different from the track address specified in the FDC. Scan Equal Hit This flag bit is set when the condition of "equal" is satisfied during a SCAN command. Scan Not Satisfied This flag bit is set when the FDC cannot find a sector on the cylinder during a SCAN command.

6 5 4

NU DE OR

3 2

NU ND

NW

MA

5 4

DD WC

SH

SN

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Table 9-13. Status Register 2 (ST2) [contd] Bit 1 Symbol BC Description Bad Cylinder This flag bit is set when the track address equals FFh and is different from the track address in the FDC. Missing Data Address Mark This flag bit is set when the FDC cannot find a Data Address Mark or Deleted Data Address Mark. Table 9-14. Status Register 3 (ST3) Bit 7 Symbol FT Description Fault Indicates the current status of the Fault signal from the FDD. Write Protect Indicates the current status of the Write Protect signal from the FDD. Ready Indicates the current status of the Ready signal from the FDD. Track 0 Indicates the current status of the Track 0 signal from the FDD. Two Side Indicates the current status of the Two Side signal from the FDD. Head Address Indicates the current status of the Head Select signal to the FDD. Unit Select Indicates the current status of the Unit Select signals to the FDD.

MD

6 5 4 3 2 1-0

WP RDY TK0 TS HD US1, US0

9.7.10

Command Set

The FDC utilizes a defined set of commands to communicate with the host. Each command is comprised of a unique first byte, which contains the op-code, and a series of additional bytes, which contain the required set of parameters and results. The descriptions use a common set of parameter byte symbols, which are presented in Table 10-14. The FDC commands may be executed whenever the FDC is in the Command phase. The FDC checks to see that the first byte is a valid command and, if so, proceeds. An interrupt is issued if it is not a valid command.
Table 9-15. Command Set Symbol Descriptions Cylinder Number The current/selected cylinder (track) number: 0 255. D Data The data pattern to be written into a sector. DC3DC0 Drive Configuration Bit3-0 Designate which drives are perpendicular drives on the PERPENDICULAR MODE command. DIR Direction Control Read/Write Head Step Direction Control. 0 = Step Out; 1 = Step In. DR0, DR1 Disk Drive Select The selected drive number: 0 or 1. DTL Data Length When N is defined as 00h, DTL designates the number of data bytes which users are going to read out or write into the Sector. When N is not 00h, DTL is undefined. www.ite.com.tw Symbol C Description

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Disable FIFO A 1 will disable the FIFO (default). A 0 will enable the FIFO. EC Enable Count If EC=1, DTL of VERIFY command will be SC. EIS Enable Implied Seek If EIS=1, a SEEK operation will be performed before executing any READ or WRITE command that requires the C parameter. EOT End of Track The final sector number on a cylinder. During a READ or WRITE operation, the FDC stops data transfer after the sector number is equal to EOT. GAP2 Gap 2 Length By PERPENDICULAR MODE command, this parameter changes Gap 2 length in the format. GPL Gap Length The length of Gap 3. During a FORMAT command, it determines the size of Gap 3. H Head Address The Head number 0 or 1, as specified in the sector ID field. (H = HD in all command words.) HD Head The selected Head number 0 or 1. Also controls the polarity of HDSEL#. (H = HD in all command words.) HLT Head Load Time The Head Load Time in the FDD (2 to 254 ms in 2 ms increments). HUT Head Unload Time The Head Unload Time after a READ or WRITE operation has been executed (16 to 240 ms in 16 ms increments). LOCK If LOCK=1, DFIFO, FIFOTHR, and PRETRK parameters of the CONFIGURE command will not be affected by a software reset. If LOCK=0 (default), the above parameters will be set to their default values following a software reset. MFM FM or MFM Mode If MFM is low, FM Mode (single density) is selected. If MFM is high, MFM Mode (double density) is selected. MT Multi-Track If MT is high, a Multi-Track operation is to be performed. In this mode, the FDC will automatically start searching for sector 1 on side 1 after finishing a READ/WRITE operation on the last sector on side 0. N Number The number of data bytes written into a sector, where: 00: 128 bytes (PC standard) 01: 256 bytes 02: 512 bytes 07: 16 Kbytes NCN New Cylinder Number A new cylinder number, which is to be reached as a result of the SEEK operation. Desired position of Head. ND Non-DMA Mode When ND is high, the FDC operates in the Non-DMA Mode. OW Overwrite If OW=1, DC3-0 of the PERPENDICULAR MODE command can be modified. Otherwise, those bits cannot be changed. PCN Present Cylinder Number The cylinder number at the completion of a SENSE INTERRUPT STATUS command. Position of Head at present time. www.ite.com.tw IT8726F V0.3 112 Symbol DFIFO Description

Functional Description
Symbol POLLD Description Polling Disable If POLLD=1, the internal polling routine is disabled. Precompensation Starting Track Number Programmable from track 0 255. Record The sector number, which will be read or written. Relative Cylinder Number To determine the relative cylinder offset from present cylinder as used by the RELATIVE SEEK command. The number of sectors per cylinder. Skip If SK=1, the Read Data operation will skip sectors with a Deleted Data Address Mark. Otherwise, the Read Deleted Data operation only accesses sectors with a Deleted Data Address Mark. Step Rate Time The Stepping Rate for the FDD (1 to 16 ms in 1 ms increments). Stepping Rate applies to all drives (F=1 ms, E=2 ms, etc.). Status 0 Status 1 Status 2 Status 3 ST03 stand for one of four registers that store the status information after a command has been executed. This information is available during the Result phase after command execution. These registers should not be confused with the Main Status Register (selected by A0 = 0). ST03 may be read only after a command has been executed and contain information associated with that particular command. If STP = 1 during a SCAN operation, the data in contiguous sectors are compared byte by byte with data sent from the processor (or DMA). If STP = 2, alternate sectors are read and compared.

PRETRK R RCN SC SK SRT ST0 ST1 ST2 ST3

STP

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Table 9-16. Command Set Summary READ DATA Data Bus D4 D3 D2 D1
0 0 C H R N EOT GPL DTL Data transfer between the FDD and the main system Status information after command execution 0 0 1 HDS 1 DR1

Phase R/W
Command W W W W W W W W W Execution Result R R R R R R R

D7
MT 0

D6
MFM 0

D5
SK 0

D0
0 DR0

Remarks
Command Codes Sector ID information before the command execution

ST0 ST1 ST2 C H R N

Sector ID information after command execution

Phase R/W
Command W W W W W W W W W Execution Result R R R R R R R

D7
MT 0

D6
MFM 0

D5
SK 0

READ DELETED DATA Data Bus D4 D3 D2 D1

0 0 C H R N EOT GPL DTL 1 0 1 HDS 0 DR1

D0
0 DR0

Remarks
Command Codes Sector ID information before the command execution

ST0 ST1 ST2 C H R N

Data transfer between the FDD and the main system Status information after command execution Sector ID information after command execution

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READ A TRACK Data Bus D4 D3 D2 D1
0 0 C H R N EOT GPL DTL Data transfer between the FDD and main system cylinder's contents from index hole to EOT Status information after command execution Sector ID information after command execution 0 0 0 HDS 1 DR1

Phase R/W
Command W W W W W W W W W Execution

D7
0 0

D6
MFM 0

D5
0 0

D0
0 DR0

Remarks
Command Codes Sector ID information before the command execution

Result

R R R R R R R

ST0 ST1 ST2 C H R N

Phase R/W
Command W W W W W W W W W Execution Result R R R R R R R

D7
MT 0

D6
MFM 0

D5
0 0

WRITE DATA Data Bus D4 D3 D2 D1

0 0 C H R N EOT GPL DTL 0 0 1 HDS 0 DR1

D0
1 DR0

Remarks
Command Codes Sector ID information before the command execution

ST0 ST1 ST2 C H R N

Data transfer between the FDD and the main system Status information after command execution Sector ID information after command execution

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WRITE DELETED DATA Data Bus D4 D3 D2 D1
0 0 C H R N EOT GPL DTL Data transfer between the FDD and the main system Status information after command execution Sector ID information after command execution 1 0 0 HDS 0 DR1

Phase R/W
Command W W W W W W W W W Execution Result R R R R R R R

D7
MT 0

D6
MFM 0

D5
0 0

D0
1 DR0

Remarks
Command Codes Sector ID information before the command execution

ST0 ST1 ST2 C H R N

Phase R/W
Command W W W W W W Execution W W W W R R R R R R R

D7
0 0

D6
MFM 0

D5
0 0

FORMAT A TRACK Data Bus D4 D3 D2 D1

0 0 N SC GPL D C H R N ST0 ST1 ST2 Undefined Undefined Undefined Undefined 1 0 1 HDS 0 DR1

D0
1 DR0 Bytes/Sector

Remarks
Command Codes

Sectors/Cylinder Gap 3 Filler Byte Input Sector Parameters per-sector FDC formats an entire cylinder

Result

Status information after command execution

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SCAN EQUAL Data Bus D4 D3 D2 D1
1 0 C H R N EOT GPL DTL Data transferred from the system to controller is compared to data read from disk Status information after command execution Sector ID information after command execution 0 0 0 HDS 0 DR1

Phase R/W
Command W W W W W W W W W Execution

D7
MT 0

D6
MFM 0

D5
SK 0

D0
1 DR0

Remarks
Command Codes Sector ID information before the command execution

Result

R R R R R R R

ST0 ST1 ST2 C H R N

Phase R/W
Command W W W W W W W W W Execution

D7
MT 0

D6
MFM 0

D5
SK 0

SCAN LOW OR EQUAL Data Bus D4 D3 D2 D1

1 0 C H R N EOT GPL DTL 1 0 0 HDS 0 DR1

D0
1 DR0

Remarks
Command Codes Sector ID information before the command execution

Result

R R R R R R R

ST0 ST1 ST2 C H R N

Data transferred from the system to controller is compared to data read from disk Status information after command execution Sector ID information after command execution

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SCAN HIGH OR EQUAL Data Bus D4 D3 D2 D1
1 0 C H R N EOT GPL DTL Data transferred from the system to controller is compared to data read from disk Status information after command execution Sector ID information after command execution 1 0 1 HDS 0 DR1

Phase R/W
Command W W W W W W W W W Execution

D7
MT 0

D6
MFM 0

D5
SK 0

D0
1 DR0

Remarks
Command Codes Sector ID information before the command execution

Result

R R R R R R R

ST0 ST1 ST2 C H R N

Phase R/W
Command W W W W W W W W W Execution Result R R R R R R R

D7
MT EC

D6
MFM 0

D5
SK 0

VERIFY Data Bus D4 D3 D2

1 0 C H R N EOT GPL DTL/SC 0 0 1 HDS

D1
1 DR1

D0
0 DR0

Remarks
Command Codes Sector ID information before the command execution

No data transfer takes place ST0 ST1 ST2 C H R N Sector ID information after command execution Status information after command execution

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READ ID Data Bus D4 D3 D2
0 0 1 0 0 HDS

Phase R/W
Command Execution Result R R R R R R R W W

D7
0 0

D6
MFM 0

D5
0 0

D1
1 DR1

D0
0 DR0

Remarks
Command Codes The first correct ID information on the Cylinder is stored in the Data Register Status information after command execution Sector ID information during execution phase

ST0 ST1 ST2 C H R N

Phase R/W
Command W W W Execution

D7
0 0 0

D6
0 0 EIS

D5
0 0

CONFIGURE Data Bus D4 D3 D2 D1

1 0 0 0 0 0 1 0

D0
1 0

Remarks
Configure Information

DFIFO POLLD PRETRK

FIFOTHR

Phase R/W
Command Execution W W

D7
0 0

D6
0 0

D5
0 0

RE-CALIBRATE Data Bus D4 D3 D2 D1

0 0 0 0 1 0 1 DR1

D0
1 DR0

Remarks
Command Codes Head retracted to Track 0

SEEK Phase R/W

Command W W W Execution

D7
0 0

D6
0 0

D5
0 0

Data Bus D4 D3
0 0 NCN 1 0

D2
1 HDS

D1
1 DR1

D0
1 DR0

Remarks
Command Codes

Head is positioned over proper cylinder on diskette

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RELATIVE SEEK Data Bus D4 D3 D2 D1
0 0 RCN Head is stepped in or out a programmable number of tracks 1 0 1 HDS 1 DR1

Phase R/W
Command W W W Execution

D7
1 0

D6
DIR 0

D5
0 0

D0
1 DR0

Remarks
Command Codes

Phase R/W
Command Execution Result R R R R R R R R R R W

D7
0

D6
0

D5
0

DUMPREG Data Bus D4 D3 D2

0 1 1

D1
1

D0
0

Remarks
Command Codes Registers placed in FIFO

PCN-Drive 0 PCN-Drive 1 PCN-Drive 2 PCN-Drive 3 SRT HLT HUT ND DC0 GAP FIFOTHR WG

SC/EOT
LOCK 0 0 DIS DC3 DC2 DC1 DFIFO POLLD PRETRK

LOCK Phase R/W

Command Result W R

D7
LOCK 0

D6
0 0

D5
0 0

Data Bus D4 D3
1 LOCK 0 0

D2
1 0

D1
0 0

D0
0 0

Remarks
Command Codes

Phase R/W
Command Result W R

D7
0 1

D6
0 0

D5
0 0

VERSION Data Bus D4 D3 D2

1 1 0 0 0 0

D1
0 0

D0
0 0

Remarks
Command Codes Enhanced Controller

Phase R/W
Command Result W R R

D7
0

D6
0

D5
0

SENSE INTERRUPT STATUS Data Bus D4 D3 D2 D1 D0

0 ST0 PCN 1 0 0 0

Remarks
Command Codes Status information at the end of each SEEK operation

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SENSE DRIVE STATUS Data Bus D4 D3 D2 D1
0 0 ST3 0 0 1 HDS 0 DR1

Phase R/W
Command Result W W R

D7
0 0

D6
0 0

D5
0 0

D0
0 DR0

Remarks
Command Codes Status information about FDD

Phase R/W
Command W W W

D7
0

D6
0 SRT

D5
0

SPECIFY Data Bus D4 D3 D2

0 HLT 0 0 HUT

D1
1

D0
1 ND

Remarks
Command Codes

Phase R/W
Command W

D7
0

D6
0

D5
0

PERPENDICULAR MODE Data Bus D4 D3 D2 D1

1 0 0 1

D0
0

Remarks
Command Codes

OW

DC3

DC2

DC1

DC0

GAP

WG

Phase R/W
Command Result W R

D7

D6

D5

INVALID Data Bus D4 D3 D2 Invalid codes

ST0

D1

D0

Remarks
INVALID Command Codes (NO-OP: FDC goes into standby state) ST0 = 80h

9.7.11

Data Transfer Commands

All data transfer commands utilize the same parameter bytes (except for FORMAT A TRACK command) and return the same result data bytes. The only difference between them is the five bits (bit 0bit 4) of the first byte.
9.7.11.1 Read Data

The READ DATA command contains nine command bytes that place the FDC into the Read Data mode. Each READ operation is initialized by a READ DATA command. The FDC locates the sector to be read by matching ID Address Marks and ID fields from the command with the information on the diskette. The FDC then transfers the data to the FIFO. When the data from the given sector have been read, the READ DATA command is completed and the sector address is automatically incremented by 1. The data from the next sector are read and transferred to the FIFO in the same manner. Such a continuous read function is called a "Multi-Sector Read Operation". If a TC or an implied TC (FIFO overrun/underrun) is received, the FDC stops sending data, but continues to read data from the current sector and checks the CRC bytes until the end of the sector is reached and the READ operation is completed. The sector size is determined by the N parameter value as calculated in the equation below: Sector Size = 2 www.ite.com.tw
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The DTL parameter determines the number of bytes to be transferred. Therefore, if N = 00h, setting the sector size to 128 and the DTL parameter value is less than this, the remaining bytes will be read and checked for CRC errors by the FDC. If this occurs in a WRITE operation, the remaining bytes will be filled with 0. If the sector size is not 128 (N > 00h), DTL should be set to FFh. In addition to performing Multi-Sector Read operations, the FDC can also perform Multi-Track Read operations. When the MT parameter is set, the FDC can read both sides of a disk automatically. The combination of N and MT parameter values determines the amount of data that can be transferred during either type of READ operation. Table 9-17 shows the maximum data transfer capacity and the final sector the FDC reads based on these parameters.
Table 9-17. Effects of MT and N Bits MT N Maximum Data Transfer Capacity Final Sector Read from Disk

0 1 0 1 0 1

1 1 2 2 3 3

256 X 26 = 6656 256 X 52 = 13312 512 X 15 = 7680 512 X 30 = 15360 1024 X 8 = 8192 1024 X16 =16384

26 on side 0 or side 1 26 on side 1 15 on side 0 or side 1 15 on side 1 8 on side 0 or side 1 16 on side 1

9.7.11.2 Read Deleted Data

The READ DELETED DATA command is the same as the READ DATA command, except that a Deleted Data Address Mark (as opposed to a Data Address Mark) is read at the beginning of the Data Field. This command is typically used to mark a bad sector on a diskette.
9.7.11.3 Read a Track

After receiving a pulse from the INDEX# pin, the READ A TRACK command reads the entire data field from each sector of the track as a continuous block. If any ID or Data Field CRC error is found, the FDC continues to read data from the track and indicates the error at the end. Because the Multi-Track [and Skip] operation[s] is[are] not allowed under this command, the MT and SK bits should be low (0) during the command execution. This command terminates normally when the number of sectors specified by EOT has not been read. If, however, no ID Address Mark has been found by the second occurrence of the INDEX pulse, the FDC will set the IC code in the ST0 to 01, indicating an abnormal termination, and then finish the command.
9.7.11.4 Write Data

The WRITE DATA command contains nine command bytes that place the FDC into the Write Data mode. Each WRITE operation is initialized by a WRITE DATA command. The FDC locates the sector to be written by reading ID fields and matching the sector address from the command with the information on the diskette. Then the FDC reads the data from the host via the FIFO and writes the data into the sectors data field. Finally, the FDC computes the CRC value, storing it in the CRC field and increments the sector number (stored in the R parameter) by 1. The next data field is written into the next sector in the same manner. Such a continuous write function is called a "Multi-Sector Write Operation". If a TC or an implied TC (FIFO overrun/underrun) is received, the FDC stops writing data and fills the remaining data field with 0s. If a check of the CRC value indicates an error in the sector ID Field, the FDC will set the IC code in the ST0 to 01 and the DE bit in the ST1 to 1, indicating an abnormal termination, and then
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terminate the WRITE DATA command. The maximum data transfer capacity and the DTL, N, and MT parameters are the same as in the READ DATA command.
9.7.11.5 Write Deleted Data

The WRITE DELETED DATA command is the same as the WRITE DATA command, except that a Deleted Data Address Mark (instead of a Data Address Mark) is written at the beginning of the Data Field. This command is typically used to mark a bad sector on a diskette.
9.7.11.6 Format A Track

The FORMAT A TRACK command is used to format an entire track. Initialized by an INDEX pulse, it writes data to the Gaps, Address Marks, ID fields and Data fields according to the density mode selected (FM or MFM). The Gap and Data field values are controlled by the host-specified values programmed into N, SC, GPL, and D during the Command phase. The Data field is filled with the data byte specified by D. The four data bytes per sector (C, H, R, and N) needed to fill the ID field are supplied by the host. The C, R, H, and N values must be renewed for each new sector of a track. Only the R parameter value must be changed when a sector is formatted, allowing the disk to be formatted with non-sequential sector addresses. These steps are repeated until a new INDEX pulse is received, at which point the FORMAT A TRACK command is terminated. 9.7.11.7 SCAN The SCAN command allows the data read from the disk to be compared with the data sent from the system. There are three SCAN commands: SCAN EQUAL Disk Data = System Data SCAN HIGH OR EQUAL Disk Data System Data SCAN LOW OR EQUAL Disk Data System Data The SCAN command execution continues until the scan condition has been met, or when the EOT has been reached, or if TC is asserted. Read errors on the disk have the same error condition as the READ DATA command. If the SK bit is set, sectors with Deleted Data Address Marks are ignored. If all sectors read are skipped, the command terminates with the D3 bit of the ST2 being set. The Result phase of the command is shown below:
Table 9-18. SCAN Command Result Command Status Register D2 D3 Condition

SCAN EQUAL SCAN HIGH OR EQUAL

0 1 0 0 1

1 0 1 0 0 1 0 0

Disk = System Disk System Disk = System Disk > System Disk < System Disk = System Disk < System Disk > System

SCAN LOW OR EQUAL

0 0 1

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9.7.11.8 VERIFY

The VERIFY command is used to read logical sectors containing a Normal Data Address Mark from the selected drive without transferring the data to the host. This command acts like a READ DATA command except that no data are transferred to the host. This command is designed for post-format or post write verification. Data are read from the disk, as the controller checks for valid Address Marks in the Address and Data Fields. The CRC is computed and checked against the previously stored value. Because no data are transferred to the host, the TC (Terminal Count of DMA) cannot be used to terminate this command. An implicit TC will be issued to the FDC by setting the EC bit. This implicit TC will occur when the SC value has been decremented to 0. This command can also be terminated by clearing the EC bit and when the EOT value is equal to the final sector to be checked.
Table 9-19. VERIFY Command Result MT EC SC/EOT Termination Result

0 0 0

0 0 1

SC = DTL EOT # Sectors per side SC = DTL EOT > # Sectors per side SC # Sectors Remaining AND EOT # Sectors per side SC > # Sectors Remaining OR EOT > # Sectors per side SC = DTL EOT > # Sectors per side SC = DTL EOT > # Sectors per side SC # Sectors Remaining AND EOT # Sectors per side SC > # Sectors Remaining OR EOT > # Sectors per side

No Error Abnormal Termination No Error

Abnormal Termination

1 1 1

0 0 1

No Error Abnormal Termination No Error

Abnormal Termination

9.7.12

Control Commands

The control commands do not transfer any data. Instead, these commands are used to monitor and manage the data transfer. Three of the Control commands generate an interrupt when finished READ ID, RECALIBRATE and SEEK. It is strongly recommended that a SENSE INTERRUPT STATUS command be issued after these commands to capture their valuable interrupt information. The RE-CALIBRATE, SEEK, and SPECIFY commands do not return any result bytes.
9.7.12.1 READ ID

The READ ID command is used to find the actual recording head position. It stores the first readable ID field value into the FDC registers. If the FDC cannot find an ID Address Mark by the time a second INDEX pulse is received, an abnormal termination will be generated by setting the IC code in the ST0 to 01. www.ite.com.tw IT8726F V0.3 124

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9.7.12.2 Configure

The CONFIGURE command determines some special operation modes of the controller. It needs not to be issued if the default values of the controller meet the system requirements. EIS: Enable Implied Seeks. A SEEK operation is performed before a READ, WRITE, SCAN, or VERIFY command. 0 = Disabled (default). 1 = Enabled. DFIFO: Disable FIFO. 0 = Enabled. 1 = Disabled (default). POLLD: Disable polling of the drives. 0 = Enabled (default). When enabled, a single interrupt is generated after a reset. 1 = Disabled. FIFOTHR: The FIFO threshold in the execution phase of data transfer commands. They are programmable from 00 to 0F hex (1 byte to 16 bytes). Defaults to 1 byte. PRETRK: The Precompensation Start Track Number. They are programmable from track 0 to FF hex (track 0 to track 255). Defaults to track 0.
9.7.12.3 RE-CALIBRATE

The RE-CALIBRATE command retracts the FDC read/write head to the track 0 position, resetting the value of the PCN counter and checking the TRK0# status. If TRK0# is low, the DIR# pin remains low and step pulses are issued. If TRK0# is high, SE [and EC bits] of the ST0 are set high, and the command is terminated. When TRK0# remains low for 79 step pulses, the RE-CALIBRATE command is terminated by setting SE and EC bits of ST0 to high. Consequently, for disks that can accommodate more than 80 tracks, more than one RECALIBRATE command is required to retract the head to the physical track 0. The FDC is in a non-busy state during the Execution phase of this command, making it possible to issue another RE-CALIBRATE command in parallel with the current command. On power-up, software must issue a RE-CALIBRATE command to properly initialize the FDC and the drives attached.
9.7.12.4 SEEK

The SEEK command controls the FDC read/write head movement from one track to another. The FDC compares the current head position, stored in PCN, with NCN values after each step pulse to determine what direction to move the head, if required. The direction of movement is determined below: PCN < NCN Step In: Sets DIR# signal to 1 and issues step pulses PCN > NCN Step Out: Sets DIR# signal to 0 and issues step pulses PCN = NCN Terminate the command by setting the ST0 SE bit to 1 The impulse rate of step pulse is controlled by Stepping Rate Time (SRT) bit in the SPECIFY command. The FDC is in a non-busy state during the Execution phase of this command, making it possible to issue another SEEK command in parallel with the current command.

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9.7.12.5 RELATIVE SEEK

The RELATIVE SEEK command steps the selected drive in or out in a given number of steps. The DIR bit is used to determine to step in or out. RCN (Relative Cylinder Number) is used to determine how many tracks to step the head in or out from the current track. After the step operation is completed, the controller generates an interrupt, but the command has no Result phase. No other command except the SENSE INTERRUPT STATUS command should be issued while a RELATIVE SEEK command is in progress.
9.7.12.6 DUMPREG

The DUMPREG command is designed for system run-time diagnostics, and application software development, and debug. This command has one byte of Command phase and 10 bytes of Result phase, which return the values of parameters set in other commands.
9.7.12.7 LOCK

The LOCK command allows the programmer to fully control the FIFO parameters after a hardware reset. If the LOCK bit is set to 1, the parameters DFIFO, FIFOTHR, and PRETRK in the CONFIGURE command are not affected by a software reset. If the bit is set to 0, those parameters are set to default values after a software reset.
9.7.12.8 VERSION

The VERSION command is used to determine the controller being used. In Result phase, a value of 90 hex is returned in order to be compatible with the 82077.
9.7.12.9 SENSE INTERRUPT STATUS

The SENSE INTERRUPT STATUS command resets the interrupt signal (IRQ) generated by the FDC, and identifies the cause of the interrupt via the IC code and SE bit of the ST0, as shown in Table 9-20. It may be necessary to generate an interrupt when any of the following conditions occur:

Before any Data Transfer or READ ID command After SEEK or RE-CALIBRATE commands (no result phase exists) When a data transfer is required during an Execution phase in the non-DMA mode
Table 9-20. Interrupt Identification SE IC Code Cause of Interrupt

0 1 1
9.7.12.10

11 00 01

Polling. Normal termination of SEEK or RE-CALIBRATE command. Abnormal termination of SEEK or RE-CALIBRATE command.

SENSE DRIVE STATUS

The SENSE DRIVE STATUS command acquires drive status information. It has no Execution phase.
9.7.12.11 SPECIFY

The SPECIFY command sets the initial values for the HUT (Head Unload Time), HLT (Head Load Time), SRT (Step Rate Time), and ND (Non-DMA mode) parameters. The possible values for HUT, SRT, and HLT are shown in Table 10-20, Table 10-21 and Table 10-22 respectively. The FDC is operated in DMA or nonDMA mode based on the value specified by the ND parameters.
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Table 9-21. HUT Values Parameter 1 Mbps 500 Kbps 300 Kbps 250 Kbps

0 1 E F

128 8 112 120

256 16 224 240

Table 9-22. SRT Values

426 26.7 373 400

512 32 448 480

Parameter

1 Mbps

500 Kbps

300 Kbps

250 Kbps

0 1 E F

8 7.5 1 0.5

16 15 2 1
Table 9-23. HLT Values

26.7 25 3.33 1.67

32 30 4 2

Parameter

1 Mbps

500 Kbps

300 Kbps

250 Kbps

00 01 02 7E 7F
9.7.12.12

128 1 2 126 127

PERPENDICULAR MODE

256 2 4 252 254

426 3.33 6.7 420 423

512 4 8 504 508

The PERPENDICULAR MODE command is used to support the unique READ/WRITE/FORMAT commands of Perpendicular Recording disk drives (4 Mbytes unformatted capacity). This command configures each of the four logical drives as a perpendicular or conventional disk drive via the DC3-DC0 bits, or with the GAP and WG control bits. Perpendicular Recording drives operate in Extra High Density mode at 1 Mbps, and are downward compatible with 1.44 Mbyte and 720 kbyte drives at 500 Kbps (High Density) and 250 Kbps (Double Density) respectively. This command should be issued during the initialization of the floppy disk controller. Then, when a drive is accessed for a FORMAT A TRACK or WRITE DATA command, the controller adjusts the format or Write Data parameters based on the data rate. If WG and GAP are used (not set to 00), the operation of the FDC is based on the values of GAP and WG. If WG and GAP are set to 00, setting DCn to 1 will set drive n to the Perpendicular mode. DC3-DC0 are unaffected by a software reset, but WG and GAP are both cleared to 0 after a software reset.

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Table 9-24. Effects of GAP and WG on FORMAT A TRACK and WRITE DATA Commands GAP WG Mode Length of GAP2 FORMAT FIELD Portion of GAP2 Re-Written by WRITE DATA Command

0 0 1 1

0 1 0 1

Conventional Perpendicular (500 Kbps) Reserved (Conventional) Perpendicular (1 Mbps)

22 bytes 22 bytes 22 bytes 41 bytes

0 bytes 19 bytes 0 bytes 38 bytes

Table 9-25. Effects of Drive Mode and Data Rate on FORMAT A TRACK and WRITE DATA Commands Data Rate Drive Mode Length of GAP2 FORMAT FIELD Portion of GAP2 Re-Written by WRITE DATA Command

250/300/500 Kbps 1 Mbps

Conventional Perpendicular Conventional Perpendicular

22 bytes 22 bytes 22 bytes 41 bytes

0 bytes 19 bytes 0 bytes 38 bytes

9.7.12.13 INVALID

The INVALID command indicates when an undefined command has been sent to FDC. The FDC will set the bit 6 and the bit 7 in the Main Status Register to 1 and terminate the command without issuing an interrupt.
9.7.13 DMA Transfers

DMA transfers are enabled by the SPECIFY command and are initiated by the FDC by activating the LDRQ# cycle during a DATA TRANSFER command. The FIFO is enabled directly by asserting the LPC DMA cycles.
9.7.14 Low Power Mode

When writing a 1 to the bit 6 of the DSR, the controller is set to low power mode immediately. All the clock sources including Data Separator, Microcontroller, and Write precompensation unit, will be gated. The FDC can be resumed from the low-power state in two ways: one is a software reset via the DOR or DSR, and the other is a read or write to either the Data Register or Main Status Register. The second method is more preferred since all internal register values are retained.

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9.8 Serial Port (UART) Description

The IT8726F incorporates two enhanced serial ports that perform serial to parallel conversion on received data, and parallel to serial conversion on transmitted data. Each of the serial channels individually contains a programmable baud rate generator which is capable of dividing the input clock by a number ranging from 1 to 65535. The data rate of each serial port can also be programmed from 115.2K baud down to 50 baud. The character options are programmable for 1 start bit; 1, 1.5 or 2 stop bits; even, odd, stick or no parity; and privileged interrupts.
Table 9-26. Serial Channel Registers Register DLAB* Address READ WRITE

Data

0 0 x

Base + 0h RBR (Receiver Buffer Register) Base + 1h IER (Interrupt Enable Register) Base + 3h LCR (Line Control Register) Base + 4h MCR (Modem Control Register) Base + 0h DLL (Divisor Latch LSB) Base + 1h DLM (Divisor Latch MSB) Base + 5h LSR (Line Status Register) Base + 6h MSR (Modem Status Register)

TBR (Transmitter Register) IER LCR MCR DLL DLM LSR MSR SCR

Buffer

Base + 2h IIR (Interrupt Identification Register) FCR (FIFO Control Register)

Control

x x 1 1 x

Status

x Base + 7h SCR (Scratch Pad Register) * DLAB is bit 7 of the Line Control Register.
9.8.1 Data Registers

The TBR and RBR individually hold from five to eight data bits. If the transmitted data are less than eight bits, it aligns to the LSB. Either received or transmitted data are buffered by a shift register, and are latched first by a holding register. The bit 0 of any word is first received and transmitted.
(1) Receiver Buffer Register (RBR) (Read only, Address offset=0, DLAB=0)

This register receives and holds the incoming data. It contains a non-accessible shift register which converts the incoming serial data stream into a parallel 8-bit word.
(2) Transmitter Buffer Register (TBR) (Write only, Address offset=0, DLAB=0)

This register holds and transmits the data via a non-accessible shift register, and converts the outgoing parallel data into a serial stream before the data transmission.
9.8.2 Control Registers: IER, IIR, FCR, DLL, DLM, LCR and MCR

(1) Interrupt Enable Register (IER) (Read/Write, Address offset=1, DLAB=0)

The IER is used to enable (or disable) four active high interrupts which activate the interrupt outputs with its lower four bits: IER(0), IER(1), IER(2), and IER(3).

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Table 9-27. Interrupt Enable Register Description Bit 7-4 3 Default 0 Description Reserved Enable MODEM Status Interrupt Sets this bit high to enable the Modem Status Interrupt when one of the Modem Status Registers changes its bit status. Enable Receiver Line Status Interrupt Sets this bit high to enable the Receiver Line Status Interrupt which is caused when Overrun, Parity, Framing or Break occurs. Enable Transmitter Holding Register Empty Interrupt Sets this bit high to enable the Transmitter Holding Register Empty Interrupt. Enable Received Data Available Interrupt Sets this bit high to enable the Received Data Available Interrupt and Time-out interrupt in the FIFO mode.

1 0

0 0

(2) Interrupt Identification Register (IIR) (Read only, Address offset=2)

This register facilitates the host CPU to determine interrupt priority and its source. The priority of four existing interrupt levels is listed below: 1. 2. 3. 4. Receiver Line Status (highest priority) Received Data Ready Transmitter Holding Register Empty Modem Status (lowest priority)

When a privileged interrupt is pending and the type of interrupt is stored in the IIR which is accessed by the Host, the serial channel holds back all interrupts and indicates the pending interrupts with the highest priority to the Host. Any new interrupts will not be acknowledged until the Host access is completed. The contents of the IIR are described in the table on the next page.

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Table 9-28. Interrupt Identification Register FIFO Mode Bit 3 Interrupt Identification Register Bit 2 Bit 1 Bit 0 Interrupt Set and Reset Functions Priority Level Interrupt Type Interrupt Source Interrupt Reset Control

0 0 0

X 1 1

X 1 0

1 0 0

First Second

None Receiver Line Status Received Data Available

None OE, PE, FE, or BI Received Data Available

Read LSR Read RBR or FIFO drops below the trigger level

Second

Character Time-out No characters have Read RBR Indication been removed from or input to the RCVR FIFO during the last 4 character times and there is at least 1 character in it during this time Transmitter Holding Transmitter Holding Register Empty Register Empty Modem Status CTS#, DSR#, RI#, DCD# Read IIR if THRE is the Interrupt Source Write THR Read MSR

Third

Fourth

Note: X = Not Defined

IIR(7), IIR(6): Are set when FCR(0) = 1. IIR(5), IIR(4): Always logic 0. IIR(3): In non-FIFO mode, this bit is a logic 0. In the FIFO mode, this bit is set along with bit 2 when a time-out Interrupt is pending. IIR(2), IIR(1): Used to identify the highest priority interrupt pending. IR(0): Used to indicate a pending interrupt in either a hard-wired prioritized or polled environment with a logic 0 state. In such a case, IIR contents may be used as a pointer that points to the appropriate interrupt service routine.

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(3) FIFO Control Register (FCR) (Write Only, Address offset=2)

This register is used to enable, clear the FIFO, and set the RCVR FIFO trigger level.
Table 9-29. FIFO Control Register Description Bit 7-6 Default Description Receiver Trigger Level Select These bits set the trigger levels for the RCVR FIFO interrupt. Reserved This bit does not affect the Serial Channel operation. RXRDY and TXRDY functions are not available on this chip. Transmitter FIFO Reset This self-clearing bit clears all contents of the XMIT FIFO and resets its related counter to 0 via a logic "1." Receiver FIFO Reset Setting this self-clearing bit to a logic 1 clears all contents of the RCVR FIFO and resets its related counter to 0 (except the shift register). FIFO Enable XMIT and RCVR FIFOs are enabled when this bit is set high. XMIT and RCVR FIFOs are disabled and cleared respectively when this bit is cleared to low. This bit must be a logic 1 if the other bits of the FCR are written to, or they will not be properly programmed. When this register is switched to non-FIFO mode, all its contents are cleared. Table 9-30. Receiver FIFO Trigger Level Encoding FCR (7) FCR (6) RCVR FIFO Trigger Level

5-4 3 2

0 0 0

0 0 1 1

0 1 0 1

1 byte 4 bytes 8 bytes 14 bytes

(4) Divisor Latches (DLL, DLM) (Read/Write, Address offset=0,1 DLAB=0)

Two 8-bit Divisor Latches (DLL and DLM) store the divisor values in a 16-bit binary format. They are loaded during the initialization to generate a desired baud rate.
(5) Baud Rate Generator (BRG)

Each serial channel contains a programmable BRG which can take any clock input (from DC to 8 MHz) to generate standard ANSI/CCITT bit rates for the channel clocking with an external clock oscillator. The DLL or DLM is a number of 16-bit format, providing the divisor range from 1 to 2 The output frequency is 16X data rate.
16

to obtain the desired baud rate.

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Table 9-31. Baud Rates Using (24 MHz 13) Clock Desired Baud Rate Divisor Used

50 75 110 134.5 150 300 600 1200 1800 2000 2400 3600 4800 7200 9600 19200 38400 57600 115200
(6) Scratch Pad Register (Read/Write, Address offset=7)

2304 1536 1047 857 768 384 192 96 64 58 48 32 24 16 12 6 3 2 1

This 8-bit register does not control the UART operation in any way. It is intended as a scratch pad register to be used by programmers to temporarily hold general purpose data.
(7) Line Control Register (LCR) (Read/Write, Address offset=3)

LCR controls the format of the data character and supplies the information of the serial line. Its contents are described on the next page.

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Table 9-32. Line Control Register Description Bit 7 Default 0 Description Divisor Latch Access Bit (DLAB) Must be set to high to access the Divisor Latches of the baud rate generator during READ or WRITE operations. It must be set low to access the Data Registers (RBR and TBR) or the Interrupt Enable Register. Set Break Forces the Serial Output (SOUT) to the spacing state (logic 0) by a logic 1, and this state will be preserved until a low level resetting LCR(6), enabling the serial port to alert the terminal in a communication system. Stick Parity When this bit and LCR(3) are high at the same time, the parity bit is transmitted, and then detected by receiver, in opposite state by LCR(4) to force the parity bit into a known state and to check the parity bit in a known state. Even Parity Select When parity is enabled (LCR(3) = 1), LCR(4) = 0 selects odd parity, and LCR(4) = 1 selects even parity. Parity Enable A parity bit, located between the last data word bit and stop bit, will be generated or checked (transmit or receive data) when LCR(3) is high. Number of Stop Bits This bit specifies the number of stop bits in each serial character, as summarized in table 10-32. Word Length Select [1:0] 11: 8 bits 10: 7 bits 01: 6 bits 00: 5 bits Table 9-33. Stop Bits Number Encoding LCR (2) Word Length No. of Stop Bits

1-0

00

0 1 1 1 1

5 bits 6 bits 7 bits 8 bits

1 1.5 2 2 2

Note: The receiver will ignore all stop bits beyond the first, regardless of the number used in transmission. (8) MODEM Control Register (MCR) (Read/Write, Address offset=4)

Controls the interface by the modem or data set (or device emulating a modem).

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Table 9-34. Modem Control Register Description Bit 7-5 4 Default 0 Description Reserved Internal Loopback Provides a loopback feature for diagnostic test of the serial channel when it is set high. Serial Output (SOUT) is set to the Marking State Shift Register output loops back into the Receiver Shift Register. All Modem Control inputs (CTS#, DSR#, RI# and DCD#) are disconnected. The four Modem Control outputs (DTR#, RTS#, OUT1 and OUT2) are internally connected to the four Modem Control inputs, and are forced to inactive high and the transmitted data are immediately received, allowing the processor to verify the transmit and receive data path of the serial channel. OUT2 The Output 2 bit enables the serial port interrupt output by a logic 1. OUT1 This bit does not have an output pin and can only be read or written by the CPU. Request to Send (RTS) Controls the Request to Send (RTS#) which is in an inverse logic state with that of MCR(1). Data Terminal Ready (DTR) Controls the Data Terminal ready (DTR#) which is in an inverse logic state with that of the MCR(0).

3 2 1

0 0 0

9.8.3

Status Registers: LSR and MSR

(1) Line Status Register (LSR) (Read/Write, Address offset=5)

This register provides status indications and is usually the first register read by the CPU to determine the cause of an interrupt or to poll the status of each serial channel. The contents of the LSR are described below:
Table 9-35. Line Status Register Description Bit 7 Default 0 Description Error in Receiver FIFO In 16450 mode, this bit is always 0. In the FIFO mode, it sets high when there is at least one parity error, framing or break interrupt in the FIFO. This bit is cleared when the CPU reads the LSR, if there are no subsequent errors in the FIFO. Transmitter Empty This read only bit indicates that the Transmitter Holding Register and Transmitter Shift Register are both empty. Otherwise, this bit is "0," and has the same function in the FIFO mode. Transmitter Holding Register Empty Transmitter Holding Register Empty (THRE). This read only bit indicates that the TBR is empty and is ready to accept a new character for transmission. It is set high when a character is transferred from the THR into the Transmitter Shift Register, causing a priority 3 IIR interrupt which is cleared by a read of IIR. In the FIFO mode, it is set when the XMIT FIFO is empty, and is cleared when at least one byte is written to the XMIT FIFO.

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4 0
Line Break Break Interrupt (BI) status bit indicates that the last character received was a break character, (invalid but entire character), including parity and stop bits. This occurs when the received data input is held in the spacing (logic 0) for longer than a full word transmission time (start bit + data bits + parity + stop bit). When any of these error conditions is detected (LSR(1) to LSR(4)), a Receiver Line Status interrupt (priority 1) will be generated in the IIR, with the IER(2) previously enabled. Framing Error Framing Error (FE) bit, a logic 1, indicates that the stop bit in the received character is not valid. It resets low when the CPU reads the contents of the LSR. Parity Error Parity error (PE) indicates by a logic 1 that the received data character does not have the correct even or odd parity, as selected by LCR(4). It will be reset to "0" whenever the LSR is read by the CPU. Overrun Error Overrun Error (OE) bit indicates by a logic 1 that the RBR has been overwritten by the next character before it had been read by the CPU. In the FIFO mode, the OE occurs when the FIFO is full and the next character has been completely received by the Shift Register. It will be reset when the LSR is read by the CPU. Data Ready A "1" indicates a character has been received by the RBR. A logic "0" indicates all the data in the RBR or the RCVR FIFO have been read.

(2) MODEM Status Register (MSR) (Read/Write, Address offset=6)

This 8-bit register indicates the current state of the control lines with modems or the peripheral devices in addition to this current state information. Four of these eight bits MSR(4) - MSR(7) can provide the state change information when a modem control input changes state. It is reset low when the Host reads the MSR.
Table 9-36. Modem Status Register Description Bit 7 Default 0 Description Data Carrier Detect Data Carrier Detect - Indicates the complement status of Data Carrier Detect (DCD#) input. If MCR(4) = 1, MSR(7) is equivalent to OUT2 of the MCR. Ring Indicator Ring Indicator (RI#) - Indicates the complement status to the RI# input. If MCR(4)=1, MSR(6) is equivalent to OUT1 in the MCR. Data Set Ready Data Set Ready (DSR#) - Indicates that the modem is ready to provide received data to the serial channel receiver circuitry. If the serial channel is in the Loop mode (MCR(4) = 1), MSR(5) is equivalent to DTR# in the MCR. Clear to Send Clear to Send (CTS#) - Indicates the complement of CTS# input. When the serial channel is in the Loop mode (MCR(4)=1), MSR(5) is equivalent to RTS# in the MCR. Delta Data Carrier Detect Indicates that the DCD# input state has been changed since the last time read by the Host. Trailing Edge Ring Indicator Indicates that the RI input state to the serial channel has been changed from a low to high since the last time read by the Host. The change to a logic 1 does not activate the TERI.

3 2

0 0

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Bit 1 Default 0 Description Delta Data Set Ready Delta Data Set Ready (DDSR) - A logic "1" indicates that the DSR# input state to the serial channel has been changed since the last time read by the Host. Delta Clear to Send This bit indicates the CTS# input to the chip has changed state since the last time the MSR was read.

9.8.4

Reset

The reset of the IT8726F should be held to an idle mode reset high for 500 ns until initialization, which causes the initialization of the transmitter and receiver internal clock counters.
Table 9-37. Reset Control of Registers and Pinout Signals Register/Signal Reset Control Reset Status

Interrupt Enable Register Interrupt Identification Register FIFO Control Register Line Control Register Modem Control Register Line Status Register Modem Status Register SOUT1, SOUT2 RTS1#, RTS2#, DTR1#, DTR2# IRQ of Serial Port

Reset Reset Reset Reset Reset Reset Reset Reset Reset Reset

All bits Low Bit 0 is high and bits 1-7 are low All bits Low All bits Low All bits Low Bits 5 and 6 are high, others are low Bits 0-3 low, bits 4-7 input signals High High High Impedance

9.8.5

Programming

Each serial channel of the IT8726F is programmed by control registers, whose contents define the character length, number of stop bits, parity, baud rate and modem interface. Even though the control register can be written in any given order, the IER should be the last register written because it controls the interrupt enables. After the port is programmed, these registers can still be updated whenever the port is not transferring data.
9.8.6 Software Reset

This approach allows the serial port returning to a completely known state without a system reset. This is achieved by writing the required data to the LCR, DLL, DLM and MCR. The LSR and RBR must be read before interrupts are enabled to clear out any residual data or status bits that may be invalid for subsequent operations.
9.8.7 Clock Input Operation

The input frequency of the Serial Channel is 24 MHz 13, not exactly 1.8432 MHz.

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9.8.8 FIFO Interrupt Mode Operation

(1) RCVR Interrupt

When setting FCR(0)=1 and IER(0)=1, the RCVR FIFO and receiver interrupts are enabled. The RCVR interrupt occurs under the following conditions: The receive data available interrupt will be issued only if the FIFO has reached its programmed trigger level. They will be cleared as soon as the FIFO drops below its trigger level. The receiver line status interrupt has higher priority over the received data available interrupt. The time-out timer will be reset after receiving a new character or after the Host reads the RCVR FIFO whenever a time-out interrupt occurs. The timer will be reset when the Host reads one character from the RCVR FIFO. RCVR FIFO time-out Interrupt: By enabling the RCVR FIFO and receiver interrupts, the RCVR FIFO time-out interrupt will occur under the following conditions: The RCVR FIFO time-out interrupt will occur only if there is at least one character in the FIFO whenever the interval between the most recent received serial character and the most recent Host READ from the FIFO is longer than four consecutive character times. The time-out timer will be reset after receiving a new character or after the Host reads the RCVR FIFO whenever a time-out interrupt occurs. The timer will be reset when the Host reads one character from the RCVR FIFO.
(2) XMIT Interrupt

By setting FCR(0) and IER(1) to high, the XMIT FIFO and transmitter interrupts are enabled, and the XMIT interrupt occurs under the conditions described below: a. The transmitter interrupt occurs when the XMIT FIFO is empty, and it will be reset if the THR is written or the IIR is read. b. The transmitter FIFO empty indications will be delayed one character time minus the last stop bit time whenever the following condition occurs: THRE = 1 and there have not been at least two bytes in the transmitter FIFO at the same time since the last THRE = 1. The transmitter interrupt after changing FCR(0) will be immediate, if it is enabled. Once the first transmitter interrupt is enabled, the THRE indication is delayed one character time minus the last stop bit time. The character time-out and RCVR FIFO trigger level interrupts are in the same priority order as the received data available interrupt. The XMIT FIFO empty is in the same priority as the transmitter holding register empty interrupt. FIFO Polled Mode Operation [FCR(0)=1, and IER(0), IER(1), IER(2), IER(3) or all are 0]. Either or both XMIT and RCVR can be in this operation mode. The operation mode can be programmed by users and is responsible for checking the RCVR and XMIT status via the LSR described below: LSR(7): RCVR FIFO error indication. LSR(6): XMIT FIFO and Shift register empty. LSR(5): The XMIT FIFO empty indication. LSR(4) - LSR(1): Specify that errors have occurred. Character error status is handled in the same way as in the interrupt mode. The IIR is not affected since IER(2)=0.
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LSR(0): High whenever the RCVR FIFO contains at least one byte. No trigger level is reached or time-out condition indicated in the FIFO Polled Mode.

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9.9 9.9.1 Smart Card Reader Features

As an IFD (InterFace Device) built in IT8726F, the Smart Card Reader (SCR) includes a standard UART (Either Serial Port 1 or Serial Port 2 is set in SCR mode) to control Smart Card interface handshaking and then performs data transfers, and can be connected to smart card socket directly. The Smart Card is capable of providing secured storage facilities for sensitive personal information (such as Private keys, Account numbers, Passwords, Medical information, etc.). Then the SCR can be used for a broad range of applications in GSM, ID, pay TV, banking (refer to EMV96 Spec.), and so forth. It also provides a Smart Card clock divider for those ICC (Integrated Circuit Card) without internal clocks.
9.9.2 Operation

The SCR is a low-power consumption design. Whenever the IFD is inactive, the clock divider will turn off internal clocks even when the clock of IFD controlling / monitoring state machine is turned off to save power consumption. Also it could be waked up immediately when IC card is removed in case of emergency or when the FET control function is turned on/off. The VCC power of IC card interface is powered from an external FET to protect the smart card interface. Also, the charge/discharge time for FET to reach 5V/0V is programmable, and FET performs automatically to meet ISO 7816 activation and deactivation sequences. The UARTs modem control lines: DTR#, RTS# and DCD# are used for controlling FET on/off, Smart Card Reset signal and IC card insertion detection respectively. When an IC card is being inserted, it will switch the SCRPSNT# (Smart Card Present Detect#) and then cause the DCD# signal to trigger an interrupt to the system. Then in the Smart Card interrupt service routine, the driver can assert the DTR# signal to power on the external FET (SCRPFET#) and the RTS# signal to control the Smart Card Reset signal (SCRRST). In the mean time, IT8726F will generate a proper clock frequency to allow the IC card using default serial transfer baud rate to send back an ATR (Answer-To-Reset) sequence. The interface signals are enabled after VCC reaches enough voltage level. Then transfer protocol may be negotiated to promote more efficient transfers. In the same way, when the IC card is removed in case of emergency or when the ICC processing is finished, the driver can de-assert the DTR# to turn off the FET power. But before the FET power-off and the reset, clock and data signals will be de-active, followed by a sufficient FET discharge time guaranteed to protect IC card and IFD.
9.9.3 Connection of IFD to ICC Socket
FET SCRPFET#

SCR_IFD in IT8712F

IC Card

SCRRST

UART

IFD

SCRIO SCRPRES#

VCC RESET CLOCK RFU

GND VPP I/O RFU

Clock Generator

SCRCLK

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9.9.4 Baud Rate Relationship Between UART and Smart Card Interface

To perform serial transfers correctly, the baud rate of UART must be set in ways similar to the ICC card.
Formula (Variation < 2%)

UART

24 MHz SCRCLK * D 13 Baud Rate = 16 * N F N =Divisor of UART, assigned by programming the DLM (Divisor Latch MSB) and DLL (Divisor Latch LSB). F =Clock Rate Conversion Factor, default = 372. D =Bit Rate Adjustment Factor, Default is 1. SCRCLK duty cycle is 45%-55%.
ICC With Internal Clock

Smart Card

ICC may use built-in internal clock, then the Baud rate is 9600 baud, just programming the Divisor Latch Registers of UART in the IT8726F for SCR IFD.
ICC Without Internal Clock

Baud rate is SCRCLK/372 before negotiating, and SCRCLK is limited within 1 MHz - 5MHz. During the ATR sequence, the default F value (Clock Rate Conversion Factor) is 372, and the default D value (Bit Rate Adjustment Factor) is 1.
9.9.5 Waveform Relationship
(24 MHz/13)/12 (24 MHz/13)/12/16

9600 Baud Rate Output SCRIO SCRCLK

1 etu=372 SCRCLK 16 BAUD clocks 1/9600 seconds

Figure 9-8. 9600 Baud Rate Example 9.9.6 Clock Divider

The SCRCLK is generated as the selection of SCR_CLKSEL1-0, which are determined in the S1 Special Configuration register 3 (LDN1_F2h) or S2 Special Configuration register 3 (LDN2_F2h).
Table 9-38. SCRCLK Selections SCR_CLKSEL1-0 Selections

00 01 10 11

Stop 3.5 MHz 7.1 MHz 96 MHz / SCR DIV96M Note

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9.9.7 Waveform Example of Activation/Deactivation Sequence

Activation Sequence
SCR_power-on

ATR from ICC with Internal Reset

Deactivation Sequence

Enable SCRIO

Enable : 1. SCRRST = ~RTS# 2. SCRCLK if SCR_CLKSEL1-0 is not 00b.

Flow_CLK DTR# RTS# SOUT CARDVCC SCRPRES# SCRPFET# SCRRST SCRCLK SCRIO
ATR, PTS, Xfer PTS, Tx

Interrupt if IC card emergency removed

VCC Charge time is 13/53/212 s Interrupt

Figure 9-9. Waveform Example of IFD Activation Sequence

Refer to the waveform above. The SCR IFD in the IT8726F will make sure the IFD is in data receive mode (i.e. the SOUT from UART is high), and the RTS# should be programmed to high. The SCRCLK is then enabled to output to the IC card (which means that the IC card can count SCRCLK clock numbers to start ATR responses), the data transfer is then enabled, and the SCRRST is the inverse logic state of RTS#. Also, the operation procedure guarantees the correct activation sequence even if the driver cannot program the SCRCLK and SCRRST in the precise time points. In this way, the hardware meets the ICC specification.
ATR

For the IC card with its own internal reset, its ATR begins within 400-40000 SCRCLK cycles. If no ATR is detected, the Smart Card IFD driver can then program the RTS# to low, and cause the SCRRST to high. For some types of IC cards without internal reset signals, it will check out the SCRRST as active low reset, and begins its ATR within 400-40000 SCRCLK cycles from the time point of SCRRST rising edge. The IT8726F does not support the type of IC Card that may send synchronous ATRs.
Deactivation and PTS Structure

Whenever the IC card is removed or when the IFD driver intends to power off the SCR interface, the IFD will enter the deactivation sequence.
9.9.8 ATR and PTS Structure

The contents of the ATR (Answer-To-Reset) and PTS (Protocol-Type-Select) are defined in ISO/IEC 7816-X standards, which must be fully communicated by the ICC Resource manager, the ICC Service provider or the ICC application software. After finalizing the coherent protocol, the SCR IFD enters the normal transfer mode. Since the SCRIO is the
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only data channel for both data transmit and receive as defined in the ICC Specification, the IT8726F can only support the half-duplex function. The SCRRST can be resent when a data transfer error occurs, and then the IFD driver will select a safer, lower-speed protocol to perform the data transfers again.
9.9.9 Smart Card Operating Sequence Example

H/W Reset IDLE

N

Waiting for ICC Insertion

Interrupt by UART sense PRESENT#

Insert
Y

Power Up, Clock Reset Card

N1

Power up FET to 5V, then allow CLOCK out and Reset control, I/O in receive mode Active level may differ ICC responses to Answer-To-Reset within 400 - 40000 cloc cycles of SCCLK, if N1, then RESET active high, if N2, then deactive

ATR
Y

Driver translates the ATR

Decoding ATR
Protocol Error

More Protocols
Y Y

If no protocol is available, then treat as all default setting; If more protocols are available, the Driver can select a suita transfer protocol

PTS Request
N N2

IFD sends Protocol-Type-Selection request, and intends to change Xfer protocol

PTS Confirm
Change Protocol

If the ICC accepts, then returns a confirm code Both IFD and ICC changed to new compromised protocol Begin to Xfer Data

Transfer
N

Finish
Y

For normal deactivation, the Driver controls the IFD to enter Deactive sequence Stop Clock Then power down FET

Clock Stop Power Down Emergency Remove

Remove

If users remove the ICC at any time

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9.10 Parallel Port

The IT8726F incorporates one multi-mode high performance parallel port, which supports the IBM AT, PS/2 compatible bi-directional Standard Parallel Port (SPP), the Enhanced Parallel Port (EPP) and the Extended Capabilities Port (ECP). Please refer to the IT8726F Configuration registers and Configuration Description for information on enabling/ disabling, changing the base address of the parallel port, and operation mode selection.
Table 9-39. Parallel Port Connector in Different Modes Host Connector Pin No. SPP EPP ECP

1 2-9 10 11 12 13 14 15 16 17

108 109-116 103 102 101 100 107 106 105 104

STB# PD0 - 7 ACK# BUSY PE SLCT AFD# ERR# INIT# SLIN#

WRITE# PD0 - 7 INTR WAIT# (NU) (1) (NU) (1) DSTB# (NU) (1) (NU) (1) ASTB#

NStrobe PD0 - 7 nAck Busy PeriphAck(2) PError nAckReverse(2) Select nAutoFd HostAck(2) nFault nPeriphRequest(2) nInit nReverseRequest(2) nSelectIn

Note 1: NU: Not used. Note 2: Fast mode. Note 3: For more information, please refer to the IEEE 1284 standard. 9.10.1 SPP and EPP Modes Table 9-40. Address Map and Bit Map for SPP and EPP Modes Register Address I/O D0 D1 D2 D3 D4 D5 D6 D7 Mode

Data Port Status Port Control Port EPP Data Port0 EPP Data Port1 EPP Data Port2 EPP Data Port3

Base 1+0h R/W Base 1+1h R Base 1+2h R/W Base 1+4h R/W Base 1+5h R/W Base 1+6h R/W Base 1+7h R/W

PD0 TMOUT STB PD0 PD0 PD0 PD0 PD0

PD1 1 AFD PD1 PD1 PD1 PD1 PD1

PD2 1 INIT PD2 PD2 PD2 PD2 PD2

PD3

PD4

PD5 PE PD5 PD5 PD5 PD5 PD5

PD6 1 PD6 PD6 PD6 PD6 PD6

PD7 1 PD7 PD7 PD7 PD7 PD7

SPP/EPP SPP/EPP EPP EPP EPP EPP EPP

ERR# SLCT PD3 PD3 PD3 PD3 PD3 PD4 PD4 PD4 PD4 PD4

ACK# BUSY# SPP/EPP

SLIN IRQE PDDIR

EPP Address Port Base 1+3h R/W

Note 1: The Base address 1 depends on the Logical Device configuration registers of Parallel Port (0X60, 0X61).

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(1) Data Port (Base Address 1 + 00h)

This is a bi-directional 8-bit data port. The direction of data flow is determined by the bit 5 of the logic state of the control port register. It forwards directions when the bit is low and reverses directions when the bit is high.
(2) Status Port (Base Address 1 + 01h)

This is a read only register. Writing to this register has no effects. The contents of this register are latched during an IOR cycle. Bit 7 - BUSY#: Inverse of printer BUSY signal, a logic "0" means that the printer is busy and cannot accept another character. A logic "1" means that it is ready to accept the next character. Bit 6 - ACK#: Printer acknowledge, a logic "0" means that the printer has received a character and is ready to accept another. A logic "1" means that it is still processing the last character. Bit 5 - PE: Paper end, a logic "1" indicates the paper end. Bit 4 - SLCT: Printer selected, a logic "1" means that the printer is on line. Bit 3 - ERR#: Printer error signal, a logic "0" means an error has been detected. Bits 2, 1 - Reserved: These bits are always "1" when read. Bit 0 - TMOUT: This bit is valid only in EPP mode and indicates that a 10-msec time-out has occurred in EPP operation. A logic "0" means no time-out occurred and a logic 1 means that a time-out error has been detected. This bit is cleared by an LRESET# or by writing a logic 1 to it. When the IT8726F is selected to non-EPP mode (SPP or ECP), this bit is always a logic "1" when read.
(3) Control Port (Base Address 1 + 02h)

This port provides all output signals to control the printer. The register can be read and written. Bits 6, 7- Reserved: These two bits are always "1" when read. Bit 5 - PDDIR: Data port direction control. This bit determines the direction of the data port register. Set this bit "0" to output the data port to PD bus, and "1" to input from PD bus. Bit 4 - IRQE: Interrupt request enable. Setting this bit "1" enables the interrupt requests from the parallel port to the Host. An interrupt request is generated by a "0" to "1" transition of the ACK# signal. Bit 3 - SLIN: Inverse of SLIN# pin. Setting this bit to "1" selects the printer. Bit 2 - INIT: Initiate printer. Setting this bit to "0" initializes the printer. Bit 1 - AFD: Inverse of the AFD# pin. Setting this bit to "1" causes the printer to automatically advance one line after each line is printed. Bit 0 - STB: Inverse of the STB# pin. This pin controls the data strobe signal to the printer.
(4) EPP Address Port (Base Address 1 + 03h)

The EPP Address Port is only available in the EPP mode. When the Host writes to this port, the contents of D0 -D7 are buffered and output to PD0 - PD7. The leading edge of IOW (Internal signal, active when LPC I/O WRITE cycle is on this address) causes an EPP ADDRESS WRITE cycle. When the Host reads from this port, the contents of PD0 - PD7 are read. The leading edge of IOR (Internal signal, active when LPC I/O READ cycle is on this address) causes an EPP ADDRESS READ cycle.
(5) EPP Data Ports 0-3 (Base Address 1 + 04-07h)

The EPP Data Ports are only available in the EPP mode. When the Host writes to these ports, the contents of D0 - D7 are buffered and output to PD0 - PD7. The leading edge of IOW (Internal signal, active when LPC I/O WRITE cycle is on this address) causes an EPP DATA WRITE cycle. When the Host reads from these ports, the contents of PD0 - PD7 are read. The leading edge of IOR (Internal signal, active when LPC I/O READ cycle is on this address) causes an EPP DATA READ cycle.

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9.10.2 EPP Mode Operation

When the parallel port of the IT8726F is set in the EPP mode, the SPP mode is also available. If no EPP Address/Data Port address is decoded (Base address + 03h- 07h), the PD bus is in the SPP mode, and the output signals such as STB#, AFD#, INIT#, and SLIN# are set by the SPP control port. The direction of the data port is controlled by the bit 5 of the control port register. There is a 10-msec time required to prevent the system from lockup. The time has elapsed from the beginning of the IOCHRDY (Internal signal: When active, the IT8726F will issue Long Wait in SYNC field) high (EPP READ/WRITE cycle) to WAIT# being de-asserted. If a time-out occurs, the current EPP READ/WRITE cycle is aborted and a logic "1" will be read in the bit 0 of the status port register. The Host must write 0 to bits 0, 1, 3 of the control port register before any EPP READ/WRITE cycle (EPP spec.). The pins STB#, AFD# and SLIN# are controlled by hardware for the hardware handshaking during EPP READ/WRITE cycle.
(1) EPP ADDRESS WRITE

1. 2. 3. 4.

The Host writes a byte to the EPP Address Port (Base address + 03h). The chip drives D0 - D7 onto PD0 - PD7. The chip asserts WRITE# (STB#) and ASTB# (SLIN#) after IOW becomes active. The peripheral de-asserts WAIT#, indicating that the chip may begin the termination of this cycle. Then, the chip de-asserts ASTB#, latches the address from D0 - D7 to PD bus, allowing the Host to complete the I/O WRITE cycle. The peripheral asserts WAIT#, indicating that it acknowledges the termination of the cycle. Then, the chip de-asserts WRITE to terminate the cycle.

(2) EPP ADDRESS READ

1. 2. 3. 4.

The Host reads a byte from the EPP Address Port. The chip drives PD bus to tri-state for the peripheral to drive. The chip asserts ASTB# after IOR becomes active. The peripheral drives the PD bus valid and de-asserts WAIT#, indicating that the chip may begin the termination of this cycle. Then, the chip de-asserts ASTB#, latches the address from PD bus to D0 -D7, allowing the Host to complete the I/O READ cycle. The peripheral drives the PD bus to tri-state and then asserts WAIT#, indicating that it acknowledges the termination of the cycle.

(3) EPP DATA WRITE

1. 2. 3. 4.

The host writes a byte to the EPP Data Port (Base address +04H - 07H). The chip drives D0- D7 onto PD0 -PD7. The chip asserts WRITE# (STB#) and DSTB# (AFD#) after IOW becomes active. The peripheral de-asserts WAIT#, indicating that the chip may begin the termination of this cycle. Then, the chip de-asserts DSTB#, latches the data from D0 - D7 to the PD bus, allowing the Host to complete the I/O WRITE cycle. The peripheral asserts WAIT#, indicating that it acknowledges the termination of the cycle. Then, the chip de-asserts WRITE to terminate the cycle.

(4) EPP DATA READ

1. 2. 3. 4.

The Host reads a byte from the EPP DATA Port. The chip drives PD bus to tri-state for the peripheral to drive. The chip asserts DSTB# after IOR becomes active. The peripheral drives PD bus valid and de-asserts WAIT#, indicating that the chip may begin the termination of this cycle. Then, the chip de-asserts DSTB#, latches the data from PD bus to D0 - D7, allowing the host to complete the I/O READ cycle. The peripheral tri-states the PD bus and then asserts WAIT#, indicating that it acknowledges the 146
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Functional Description
termination of the cycle.
9.10.3 ECP Mode Operation

This mode is both software and hardware compatible with the existing parallel ports, allowing ECP to be used as a standard LPT port when the ECP mode is not required. It provides an automatic high-burst-bandwidth channel that supports DMA or the ECP mode in both forward and reverse directions. A 16-byte FIFO is implemented in both forward and reverse directions to smooth data flow and enhance the maximum bandwidth requirement allowed. The port supports automatic handshaking for the standard parallel port to improve compatibility and expedite the mode transfer. It also supports run-length encoded (RLE) decompression in hardware. Compression is accomplished by counting identical bytes and transmitting an RLE byte that indicates how many times a byte has been repeated. The IT8726F does not support hardware RLE compression. For a detailed description, please refer to "Extended Capabilities Port Protocol and ISA Interface Standard".
Table 9-41. Bit Map of the ECP Registers Register D7 D6 D5 D4 D3 D2 D1 D0

data ecpAFifo dsr dcr cFifo ecpDFifo tFifo cnfgA cnfgB ecr

PD7 Addr/RLE nBusy 1

PD6 nAck 1

PD5 PError PDDIR

PD4 Select IRQE

PD3 nFault SelectIn

PD2 1 nInit

PD1 1 AutoFd

PD0 1 Strobe

Address or RLE field

Parallel Port Data FIFO ECP Data FIFO Test FIFO 0 0 0 intrValue mode 0 0 1 0 nErrIntrEn 0 0 dmaEn 0 0 ServiceIntr 0 0 full 0 0 empty

(1) ECP Register Definitions Table 9-42. ECP Register Definitions Name Address I/O ECP Mode Function

data ecpAFifo dsr dcr cFifo ecpDFifo tFifo cnfgA cnfgB ecr

Base 1 +000H Base 1 +000H Base 1 +001H Base 1 +002H Base 2 +000H Base 2 +000H Base 2 +000H Base 2 +000H Base 2 +001H Base 2 +002H

R/W R/W R/W R/W R/W R/W R/W R R/W R/W

000-001 011 All All 010 011 110 111 111 All

Data Register ECP FIFO (Address) Status Register Control Register Parallel Port Data FIFO ECP FIFO (DATA) Test FIFO Configuration Register A Configuration Register B Extended Control Register

Note 1: The Base address 1 depends on the Logical Device configuration registers of Parallel Port (0X60, 0X61). Note 2: The Base address 2 depends on the Logical Device configuration registers of Parallel Port (0X62, 0X63). www.ite.com.tw

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(2) ECP Mode Descriptions Table 9-43. ECP Mode Descriptions Mode Description

000 001 010 011 110 111

Standard Parallel Port Mode PS/2 Parallel Port Mode Parallel Port FIFO Mode ECP Parallel Port Mode Test Mode Configuration Mode

Note: Please refer to the ECP Register Description on pages 128-129 for a detailed description of the mode selection. (3) ECP Pin Descriptions Table 9-44. ECP Pin Descriptions Name nStrobe (HostClk) Attribute Description Used for handshaking with Busy to write data and addresses into the O peripheral device. Address or data or RLE data. PD0-PD7 I/O Used for handshaking with nAutoFd to transfer data from the peripheral nAck (PeriphClk) I device to the Host. The peripheral uses this signal for flow control in the forward direction Busy (PeriphACK) I (handshaking with nStrobe). In the reverse direction, this signal is used to determine whether a command or data information is present on PD0-PD7. Used to acknowledge nInit from the peripheral which drives this signal low, Perror I allowing the host to drive the PD bus. (nAckReverse) Printer On-Line Indication. Select I In the reverse direction, it is used for handshaking between the nAck and the nAutoFd (HostAck) O Host. When it is asserted, a peripheral data byte is requested. In the forward direction, this signal is used to determine whether a command or data information is present on PD0 - PD7. In the forward direction (only), the peripheral is allowed (but not required) to nFault I assert this signal (low) to request a reverse transfer while in ECP mode. The (nPeriphRequest) signal provides a mechanism for peer-to-peer communication. It is typically used to generate an interrupt to host, which has the ultimate control over the transfer direction. The host may drive this signal low to place the PD bus in the reverse nInit O direction. In the ECP mode, the peripheral is permitted to drive the PD bus (nReverseRequest) when nInit is low, and nSelectIn is high. NSelectIn O Always inactive (high) in the ECP mode. (1284 Active) (4) Data Port (Base 1+00h, Modes 000 and 001) Its contents will be cleared by a RESET. In a WRITE operation, the contents of the LPC data fields are latched by the Data Register. The contents are then sent without being inverted to PD0-PD7. In a READ operation, the contents of data ports are read and sent to the host. (5) ecpAFifo Port (Address/RLE) (Base 1 +00h, Mode 011) Any data byte written to this port are placed in the FIFO and tagged as an ECP Address/RLE. The hardware then automatically sends this data to the peripheral. Operation of this port is valid only in the forward direction (dcr(5)=0). www.ite.com.tw IT8726F V0.3 148

Functional Description
(6) Device Status Register (dsr) (Base 1 +01h, Mode All) Bits 0, 1 and 2 of this register are not implemented. These bit states are remained at high in a READ operation of the Printer Status Register. dsr(7): This bit is the inverted level of the Busy input. dsr(6): This bit is the state of the nAck input. dsr(5): This bit is the state of the PError input. dsr(4): This bit is the state of the Select input. dsr(3): This bit is the state of the nFault input. dsr(2)-dsr(0): These bits are always 1. (7) Device Control Register (dcr) (Base 1+02h, Mode All) Bits 6 and 7 of this register have no function. They are set high during the READ operation, and cannot be written. Contents in bits 0-5 are initialized to 0 when the RESET pin is active. dcr(7)-dcr(6): These two bits are always high. dcr(5):Except in the modes 000 and 010, setting this bit low means that the PD bus is in output operation; setting it high, in input operation. This bit will be forced to low in mode 000. dcr(4): Setting this bit high enables the interrupt request from peripheral to the host due to a rising edge of the nAck input. dcr(3): It is inverted and output to SelectIn. dcr(2): It is output to nInit without inversion. dcr(1): It is inverted and output to nAutoFd. dcr(0): It is inverted and output to nStrobe. (8) Parallel Port Data FIFO (cFifo) (Base 2+00h, Mode 010) Bytes written or DMA transferred from the Host to this FIFO are sent by a hardware handshaking to the peripheral according to the Standard Parallel Port protocol. This operation is only defined for the forward direction. (9) ECP Data FIFO (ecpDFifo) (Base 2+00h, Mode 011) When the direction bit dcr(5) is 0, bytes written or DMA transferred from the Host to this FIFO are sent by hardware handshaking to the peripheral according to the ECP parallel port protocol. When dcr(5) is 1, data bytes from the peripheral to this FIFO are read in an automatic hardware handshaking. The Host can receive these bytes by performing READ operations or DMA transfers from this FIFO. (10) Test FIFO (tFifo) (Base 2+00h, Mode 110) The host may operate READ/WRITE or DMA transfers to this FIFO in any directions. Data in this FIFO will be displayed on the PD bus without using hardware protocol handshaking. The tFifo will not accept new data after it is full. Making a READ from an empty tFifo causes the last data byte to return. (11) Configuration Register A (cnfgA) (Base 2+00h, Mode 111) This read only register indicates to the system that interrupts are ISA-Pulses compatible. This is an 8-bit implementation by returning a 10h. (12) Configuration Register B (cnfgB) (Base 2+01h, Mode 111) This register is read only. cnfgB(7): A logic 0 read indicates that the chip does not support hardware RLE compression. cnfgB(6): Reserved. cnfgB(5)-cnfg(3): A value 000 read indicates that the interrupt must be selected with jumpers. cnfgB(2)-cnfg(0): A value 000 read indicates that the DMA channel is jumpered 8-bit DMA. (13) Extended Control Register (ecr) (Base 2+02h, Mode All) ECP function control register. ecr(7)-ecr(5): These bits are used for READ/WRITE and mode selection. www.ite.com.tw

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Table 9-45. Extended Control Register (ECR) Mode and Description Mode and Description Standard Parallel Port Mode 000 The FIFO is reset and the direction bit dcr(5) is always 0 (forward direction) in this mode. PS/2 Parallel Port Mode It is similar to the SPP mode, except that the dcr(5) is read/write. When dcr(5) is 1, the PD bus is tri001 state. Reading the data port returns the value on the PD bus instead of the value of the data register. Parallel Port Data FIFO Mode This mode is similar to the 000 mode, except that the Host writes or DMA transfers the data bytes to 010 the FIFO. The FIFO data are then transmitted to the peripheral using the standard parallel port protocol automatically. This mode is only valid in the forward direction (dcr(5)=0). ECP Parallel Port Mode In the forward direction, bytes placed into the ecpDFifo and ecpAFifo are placed in a single FIFO 011 and automatically transmitted to the peripheral under the ECP protocol. In the reverse direction, bytes are transmitted to the ecpDFifo from the ECP port. 100, 101 Reserved, not defined. Test Mode 110 In this mode, the FIFO may be read from or written to, but it cannot be sent to the peripheral. Configuration Mode 111 In this mode, the cnfgA and cnfgB registers are accessible at 0x400 and 0x401. ECR

ecr(4): nErrIntrEn, READ/WRITE, Valid in ECP(011) Mode 1: Disables the interrupt generated on the asserting edge of the nFault input. 0: Enables the interrupt pulse on the asserting edge of the nFault. An interrupt pulse will be generated if nFault is asserted, or if this bit is written from 1 to 0 in the low-level nFault. ecr(3): dmaEn, READ/WRITE 1: Enables DMA. DMA starts when serviceIntr (ecr(2)) is 0. 0: Disables DMA unconditionally. ecr(2): ServiceIntr, READ/WRITE 1: Disables DMA and all service interrupts. 0: Enables the service interrupts. This bit will be set to 1 by hardware when one of the three service interrupts has occurred. Writing 1 to this bit will not generate an interrupt. Case 1: dmaEn=1 During DMA, this bit is set to 1 (a service interrupt generated) if the terminal count is reached.
Case 2: dmaEn=0, dcr(5)=0 This bit is set to 1 (a service interrupt generated) whenever there are writeIntrThreshold or more bytes space free in the FIFO. Case 3: dmaEn=0, dcr(5)=1 This bit is set to 1 (a service interrupt generated) whenever there are readIntrThreshold or more valid bytes to be read from the FIFO. ecr(1): full, read only 1: The FIFO is full and cannot accept another byte. 0: The FIFO has at least 1 free data byte space. ecr(0): empty, read only 1: The FIFO is empty. 0: The FIFO contains at least 1 data byte. (14) Mode Switching Operation www.ite.com.tw

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In programmed I/O control (mode 000 or 001), P1284 negotiation and all other tasks that happen before data transmission are software-controlled. Setting mode to 011 or 010 will cause the hardware to perform an automatic control-line handshaking, transferring information between the FIFO and the ECP port. From the mode 000 or 001, any other mode may be immediately switched to any other mode. To change direction, the mode must first be set to 001. In the extended forward mode, the FIFO must be cleared and all the signals must be de-asserted before returning to mode 000 or 001. In ECP reverse mode, all data must be read from the FIFO before returning to mode 000 or 001. Usually, unneeded data are accumulated during ECP reverse handshaking, when the mode is changed during a data transfer. In such conditions, nAutoFd will be de-asserted regardless of the transfer state. To avoid bugs during handshaking signals, these guidelines must be followed.
(15) Software Operation (ECP)

Before the ECP operation can begin, it is first necessary for the Host to switch the mode to 000 in order to negotiate with the parallel port. During this process, the Host determines whether the peripheral supports the ECP protocol. After this negotiation is completed, the mode is set to 011 (ECP). To enable the drivers, the direction must be set to 0. Both strobe and autoFd are set to 0, causing nStrobe and nAutoFd signals to be de-asserted. All FIFO data transfers are PWord wide and PWord aligned. Permitted only in the forward direction, Address/RLE transfers are byte-wide. The ECP Address/RLE bytes may be automatically sent by writing to the ecpAFifo. Similarly, data PWords may be automatically sent via the ecpDFifo. To change directions, the Host switches mode to 001. It then negotiates either the forward or reverse channel, sets the direction to 1 or 0, and finally switches mode to 001. If the direction is set to 1, the hardware performs the handshaking for each ECP data byte read, then tries to fill the FIFO. At this time, PWords may be read from the ecpDFifo while it retains data. It is also possible to perform the ECP transfers by handshaking with individual bytes under programmed control in mode = 001, or 000, even though this is a comparatively time-consuming approach.
(16) Hardware Operation (DMA)

The Standard PC DMA protocol (through LDRQ#) is followed. As in the programmed I/O case, software sets THE direction and state. Next, the desired count and memory addresses are programmed into DMA controller. The dmaEn is set to 1, and the serviceIntr is set to 0. To complete the process, the DMA channel with the DMA controller is unmasked. The contents in the FIFO are emptied or filled by DMA using the right mode and direction. DMA is always transferred to or from the FIFO located at 0 x 400. By generating an interrupt and asserting a serviceIntr, DMA is disabled when the DMA controller reaches the terminal count. By not asserting LDRQ# for more than 32 consecutive DMA cycles, blocking of refresh requests is eliminated. When it is necessary to disable a DMA while performing a transfer, the host DMA controller is disabled, serviceIntr is then set to 1, and dmaEn is next set to 0. If the contents in FIFO are empty or full, the DMA will start again. This is first done by enabling the host DMA controller, and then setting dmaEn to 1. Finally, serviceIntr is set to 0. Upon completion of a DMA transfer in the forward direction, the software program must wait until the contents in FIFO are empty and the busy line is low, ensuring that all data successfully reach the peripheral device.
(17) Interrupts

It is necessary to generate an interrupt when any of the following states are reached.
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1. 2. 3. 4. 5. serviceIntr = 0, dmaEn = 0, direction = 0, and the number of PWords in the FIFO is greater than or equal to writeIntrThreshold. serviceIntr = 0, dmaEn = 0, direction = 1, and the number of PWords in the FIFO is greater than or equal to readIntrThreshold. serviceIntr = 0, dmaEn = 1, and DMA reaches the terminal count. nErrIntrEn = 0 and nFault goes from high to low or when nErrIntrEn is set from 1 to 0 and nFault is asserted. ackIntEn = 1. In current implementations of using existing parallel ports, the interrupt generated may be either edge or level trigger type.

(18) Interrupt Driven Programmed I/O

It is also possible to use an interrupt-driven programmed I/O to execute either ECP or parallel port FIFOs. An interrupt will occur in the forward direction when serviceIntr is 0 and the number of free PWords in the FIFO is equal to or greater than writeIntrThreshold. If either of these conditions is not met, it may be filled with writeIntrThreshold PWords. An interrupt will occur in the reverse direction when serviceIntr is 0 and the number of available PWords in the FIFO is equal to readIntrThreshold. If it is full, the FIFO can be completely emptied in a single burst. If it is not full, only a number of PWords equal to readIntrThreshold may be read from the FIFO in a single burst. In the Test mode, software can determine the values of writeIntrThreshold, readIntrThreshold, and FIFO depth while accessing the FIFO. Any PC LPC bus implementation that is adjusted to expedite DMA or I/O transfer must ensure that the bandwidth on the ISA is maintained on the interface. Although the LPC (even PCI) bus of PC cannot be directly controlled, the interface bandwidth of ECP port can be constrained to perform at the optimum speed.
(19) Standard Parallel Port

In the forward direction with DMA, the standard parallel port is run at or close to the permitted peak bandwidth of 500 KB/sec. The state machine does not examine nAck, but just begins the next DMA based on the Busy signal.

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9.11 Keyboard Controller (KBC)

The keyboard controller is implemented using an 8-bit microcontroller that is capable of executing the 8042 instruction set. For general information, please refer to the description of the 8042 in the 8-bit controller handbook. In addition, the microcontroller can enter power-down mode by executing two types of powerdown instructions.

Keyboard P20 Controller P21

P26 T0 P27 P10 P23 T1 P22 P11 P24 P25

KRST* GATEA20 KCLK KDAT MCLK MDAT KIRQ MIRQ

Figure 9-10. Keyboard and Mouse Interface 9.11.1 Host Interface

The keyboard controller interfaces with the system through the 8042 style host interface. The table 10-45 shows how the interface decodes the control signals.
Table 9-46. Data Register READ/WRITE Controls Host Address Note R/W* Function

60h 60h 64h 64h

R W R W

READ DATA WRITE DATA, (Clear F1) READ Status WRITE Command, (set F1)

Note: These are the default values of the LDN5, 60h and 61h (DATA); LDN5, 62h and 63h (Command). All these registers are programmable. READ DATA: This is an 8-bit read only register. When read, the KIRQ output is cleared and OBF flag in the status register is cleared. WRITE DATA: This is an 8-bit write only register. When written, the F1 flag of the Status register is cleared and the IBF bit is set. READ Status: This is an 8-bit read only register. Refer to the description of the Status register for more information. WRITE Command: This is an 8-bit write only register. When written, both F1 and IBF flags of the Status register are set. www.ite.com.tw

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9.11.2 Data Registers and Status Register

The keyboard controller provides two data registers: one is DBIN for data input, and the other is DBOUT for data output. Each of the data registers is 8 bits wide. A write (microcontroller) to the DBOUT will load Keyboard Data Read Buffer, set OBF flag and set the KIRQ output. A read (microcontroller) of the DBIN will read the data from the Keyboard Data or Command Write Buffer and clear the IBF flag. The status register holds information concerning the status of the data registers, the internal flags, and some user-defined status bits. Please refer to Table 10-46. The bit 0 OBF is set to 1 when the microcontroller writes a data into DBOUT, and is cleared when the system initiates a DATA READ operation. The bit 1 IBF is set to 1 when the system initiates a WRITE operation, and is cleared when the microcontroller executes an IN A, DBB instruction. The F0 and F1 flags can be set or reset when the microcontroller executes the clear and complement flag instructions. F1 also holds the system WRITE information when the system performs the WRITE operations.
Table 9-47. Status Register

7 ST7
9.11.3

6 ST6

5 ST5

4 ST4

3 F1

2 F0

1 IBF

0 OBF

Keyboard and Mouse Interface

KCLK is the keyboard clock pin. Its output is the inversion of pin P26 of the microcontroller, and the input of KCLK is connected to the T0 pin of the microcontroller. KDAT is the keyboard data pin; its output is the inversion of pin P27 of the microcontroller, and the input of KDAT is connected to the P10 of the microcontroller. MCLK is the mouse clock pin; its output is the inversion of pin P23 of the microcontroller, and the input of MCLK is connected to the T1 pin of the microcontroller. MDAT is the Mouse data pin; its output is the inversion of pin P22 of the microcontroller, and the input of MDAT is connected to the P11 of the microcontroller. KRST# is pin P20 of the microcontroller. GATEA20 is the pin P21 of the microcontroller. These two pins are used as software controlled or user defined outputs. External pull-ups may be required for these pins.
9.11.4 KIRQ and MIRQ

KIRQ is the interrupt request for keyboard (Default IRQ1), and MIRQ is the interrupt request for mouse (Default IRQ12). KIRQ is internally connected to P24 pin of the microcontroller, and MIRQ is internally connected to pin P25 of the microcontroller.

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9.12 9.12.1 Consumer Remote Control (TV Remote) IR (CIR) Overview

The CIR is used in Consumer Remote Control equipment, and is a programmable amplitude shift keyed (ASK) serial communication protocol. By adjusting frequencies, baud rate divisors and sensitivity ranges, the CIR registers are able to support the popular protocols such as RC-5, NEC, and RECS-80. Software driver programming can support new protocols.
9.12.2 Features

Supports 30 kHz 57 kHz (low frequency) or 400 kHz 500 kHz (high frequency) carrier transmission Baud rates up to 115200 BPS (high frequency) Demodulation optional Supports transmission run-length encoding and deferral functions 32-byte FIFO for data transmission or data reception
9.12.3 Block Diagram

The CIR consists of the Transmitter and Receiver parts. The Transmitter part is responsible for transmitting data to the FIFO, processing the FIFO data by serialization, modulation and sending out the data through the LED device. The Receiver part is responsible for receiving data, processing data by demodulation, deserialization and storing data in the Receiver FIFO.
00000000 11110000

Transmitter
Transmitter FIFO Serialization Modulator

data

Host Interface

Interface & Registers

Baud Rate Gen.

data

Receiver
Interrupt Gen. Receiver FIFO Deserialization
Demodulator

00000000 11110000

Figure 9-11. CIR Block Diagram

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9.12.4 Transmit Operation

The data written to the Transmitter FIFO will be exactly serialized from LSB to MSB, modulated with carrier frequency and sent to the CIRTX output. The data are either in bit-string format or run-length decode. Before the data transmission can begin, code byte write operations must be performed to the Transmitter FIFO DR. The bit TXRLE in the TCR1 should be set to 1 before the run-length decode data can be written into the Transmitter FIFO. Set TXENDF in the TCR1 will enable the data transmission deferral, and avoid the transmitter FIFO underrun. The bit width of the serialized bit string is determined by the value programmed in the baud rate divisor registers BDLR and BDHR. When the bits HCFS and CFQ[4:0] are set, either the highspeed or low-speed carrier range is selected, and the corresponding carrier frequency will also be determined. Bits TXMPM[1:0] and TXMPW[2:0] specify the pulse numbers in a bit width and the required duty cycles of the carrier pulse according to the communication protocol. Only a logic 0 can activate the Transmitter LED in the format of a series of modulating pulses.
9.12.5 Receive Operation

The Receiver function is enabled if the bit RXEN in the RCR is set to 1. Either demodulated or modulated RX# signal is loaded in0to the Receiver FIFO, and the bit RXEND in the RCR determines the demodulation logic should be used or not. Determine the baud rate by programming the baud rate divisor registers BDLR and BDHR, and the carrier frequencies by programming the bits HCFS and CFQ[4:0]. Set RDWOS to 0 to sync. The bit RXACT in the RCR is set to 1 when the serial data or the selected carrier is incoming, and the sampled data will then be kept in the Receiver FIFO. Write 1 to the bit RXACT to stop the Receiver operation; 0 to the bit RXEN to disable the Receiver.
9.12.6 Register Descriptions and Address Table 9-48. List of CIR Registers Register Name R/W Address Default

CIR Data Register (DR) CIR Interrupt Enable Register (IER) CIR Receiver Control Register (RCR) CIR Transmitter Control Register 1 (TCR1) CIR Transmitter Control Register 2 (TCR2) CIR Transmitter Status Register (TSR) CIR Receiver Status Register (RSR) CIR Baud Rate Divisor Low Byte Register (BDLR) CIR Baud Rate Divisor High Byte Register (BDHR) CIR Interrupt Identification Register (IIR)

R/W R/W R/W R/W R/W R R R/W R/W R/W

Base + 0h Base + 1h Base + 2h Base + 3h Base + 4h Base + 5h Base + 6h Base + 5h Base + 6h Base + 7h

FFh 00h 01h 00h 5Ch 00h 00h 00h 00h 01h

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9.12.6.1 CIR Data Register (DR)

The DR, an 8-bit read/write register, is the data port for CIR. Data are transmitted and received through this register.
Address: Base Address + 0h Bit 7-6 R/W R/W Default FFh Description CIR Data Register (DR[7:0]) Writing data to this register causes data to be written to the Transmitter FIFO. Reading data from this register causes data to be received from the Receiver FIFO.

9.12.6.2 CIR Interrupt Enable Register (IER)

The IER, an 8-bit read/write register, is used to enable the CIR interrupt request.
Address: Base Address + 1h Bit 7-6 5 R/W R/W Default 0b Description Reserved RESET (RESET) This bit is a software reset function. Writing a 1 to this bit resets the registers of DR, IER, TCR1, BDLR, BDHR and IIR. This bit is then cleared to initial value automatically. Baud Rate Register Enable Function Enable (BR) This bit is used to control the baud rate registers enable read/write function. Set this bit to 1 to enable the baud rate registers for CIR. Set this bit to 0 to disable the baud rate registers for CIR. Interrupt Enable Function Control (IEC) This bit is used to control the interrupt enable function. Set this bit to 1 to enable the interrupt request for CIR. Set this bit to 0 to disable the interrupt request for CIR. Receiver FIFO Overrun Interrupt Enable (RFOIE) This bit is used to control Receiver FIFO Overrun Interrupt request. Set this bit to 1 to enable Receiver FIFO Overrun Interrupt request. Set this bit to 0 to disable Receiver FIFO Overrun Interrupt request. Receiver Data Available Interrupt Enable (RDAIE) This bit is used to enable Receiver Data Available Interrupt request. The Receiver will generate this interrupt when the data available in the FIFO exceed the FIFO threshold level. Set this bit to 1 to enable Receiver Data Available Interrupt request. Set this bit to 0 to disable Receiver Data Available Interrupt request. Transmitter Low Data Level Interrupt Enable (TLDLIE) This bit is used to enable Transmitter Low Data Level Interrupt request. The Transmitter will generate this interrupt when the data available in the FIFO are less than the FIFO threshold Level. Set this bit to 1 to enable Transmitter Low Data Level Interrupt request. Set this bit to 0 to disable Transmitter Low Data Level Interrupt request.

R/W

0b

R/W

0b

R/W

0b

R/W

0b

R/W

0b

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9.12.6.3 CIR Receiver Control Register (RCR)

The RCR, an 8-bit read/write register, is used to control the CIR Receiver.
Address: Base Address + 2h Bit 7 R/W R/W Default 0b Description Receiver Data Without Sync. (RDWOS) This bit is used to control the sync. logic for receiving data. Set this bit to 1 to obtain the receiving data without sync. logic. Set this bit to 0 to obtain the receiving data in sync. logic. High-Speed Carrier Frequency Select (HCFS) This bit is used to select Carrier Frequency between high-speed and low-speed. 0: 30-58 kHz (Default) 1: 400-500 kHz Receiver Enable (RXEN) This bit is used to enable Receiver function. Enable Receiver and the RXACT will be active if the selected carrier frequency is received. Set this bit to 1 to enable the Receiver function. Set this bit to 0 to disable the Receiver function. Receiver Demodulation Enable (RXEND) This bit is used to control the Receiver Demodulation logic. If the Receiver device can not demodulate the correct carrier, set this bit to 1. Set this bit to 1 to enable Receiver Demodulation logic. Set this bit to 0 to disable Receiver Demodulation logic. Receiver Active (RXACT) This bit is used to control the Receiver operation. This bit is set to 0 when the Receiver is inactive. This bit will be set to 1 when the Receiver detects a pulse (RXEND=0) or pulse-train (RXEND=1) with correct carrier frequency. The Receiver then starts to sample the input data when Receiver Active is set. Write a 1 to this bit to clear the Receiver Active condition and make the Receiver enter the inactive mode. Receiver Demodulation Carrier Range (RXDCR[2:0]) These three bits are used to set the tolerance of the Receiver. Demodulation carrier frequency. See Table 10-49 and Table 10-50.

R/W

0b

R/W

0b

R/W

0b

R/W

0b

2-0

R/W

001b

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9.12.6.4 CIR Transmitter Control Register 1 (TCR1)

The TCR1, an 8-bit read/write register, is used to control the Transmitter.

Address: Base Address + 3h Bit 7 R/W R/W Default 0b Description FIFO Clear (FIFOCLR) Writing a 1 to this bit clears the FIFO. This bit is then cleared to 0 automatically. Internal Loopback Enable (ILE) This bit is used to execute internal loopback for test and must be 0 in normal operation. Set this bit to 0 to disable the Internal Loopback mode. Set this bit to 1 to enable the Internal Loopback mode. FIFO Threshold Level (FIFOTL) These two bits are used to set the FIFO Threshold Level. The FIFO length is 32 bytes for TX or RX function (ILE = 0) in normal operation and 16 bytes for both TX and RX in internal Loopback mode (ILE = 1). 16-Byte Mode 32-Byte Mode 00 1 1 (Default) 01 3 7 10 7 17 11 13 25 Transmitter Run Length Enable (TXRLE) This bit controls the Transmitter Run Length encoding/decoding mode, which condenses a series of 1 or 0 into one byte with the bit value stored in bit 7 and number of bits minus 1 in bits 6 0. Set this bit to 1 to enable the Transmitter Run Length mode. Set this bit to 0 to disable the Transmitter Run Length mode. Transmitter Deferral (TXENDF) This bit is used to avoid Transmitter underrun condition. When this bit is set to 1, the Transmitter FIFO data will be kept until the transmitter time-out condition occurs, or the FIFO reaches full. Transmitter Modulation Pulse Mode (TXMPM[1:0]) These two bits are used to define the Transmitter modulation pulse mode. TXMPM[1:0] Modulation Pulse Mode C_pls mode (Default): Pulses are generated continuously for the entire logic 0 bit time. 8_pls mode: 8 pulses are generated for each logic 0 bit. 6_pls mode: 6 pulses are generated for each logic 0 bit. 11: Reserved.

R/W

0b

5-4

R/W

0b

R/W

0b

R/W

0b

1-0

R/W

0b

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9.12.6.5 CIR Transmitter Control Register (TCR2)

The TCR2, an 8-bit read/write register, is used to determine the carrier frequency.
Address: Base Address + 4h Bit R/W Default 7-3 R/W 01011b

2-0

R/W

100b

Description Carrier Frequency (CFQ[4:0]) These five bits are used to determine the modulation carrier frequency. See Table 10-48. Transmitter Modulation Pulse Width (TXMPW[2:0]) These three bits are used to set the Transmitter Modulation pulse width. The duty cycle of the carrier will be determined according to the settings of Carrier Frequency and the selection of Transmitter Modulation pulse width. TXMPW[2:0] HCFS = 0 HCFS = 1 000 Reserved Reserved 001 Reserved Reserved 010 6 s 0.7 s 011 7 s 0.8 s 100 8.7 s 0.9 s (Default) 101 10.6 s 1.0 s 110 13.3 s 1.16 s 111 Reserved Reserved

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Table 9-49. Modulation Carrier Frequency CFQ Low Frequency (HCFS =0) High Frequency (HCFS = 1)

00000 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 10000 10001 10010 10011 10100 10101 10110 10111 11000 11001 11010 11011 11100 11101 11110 11111

27 kHz 29 kHz 30 kHz 31 kHz 32 kHz 33 kHz 34 kHz 35 kHz 36 kHz 37 kHz 38 kHz (default) 39 kHz 40 kHz 41 kHz 42 kHz 43 kHz 44 kHz 45 kHz 46 kHz 47 kHz 48 kHz 49 kHz 50 kHz 51 kHz 52 kHz 53 kHz 54 kHz 55 kHz 56 kHz 57 kHz 58 kHz

400 kHz 450 kHz 480 kHz (default) 500 kHz -

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Table 9-50. Receiver Demodulation Low Frequency (HCFS = 0) RXDCR CFQ 001 Min. Max. 010 Min. Max. 011 Min. Max. 100 Min. Max. 101 Min. Max. 110 Min. Max. (Hz)

00001 00010 00011 00100 00101 00110 00111 01000 01001 01010
01011

26.25 29.75

24.5

31.5 22.75 33.25

21 22.5 24 25.5 27
28.5

35 19.25 36.75

17.5

38.5 28k

27.19 30.81 25.38 32.63 23.56 34.44 21.75 36.25 19.94 38.06 18.13 39.88 29k 28.13 31.88 26.25 33.75 24.38 35.63 30 34 28 36 26 38 37.5 20.63 39.38 18.75 41.25 30k 40 22 42 20 44 32k 29.06 32.94 27.13 34.88 25.19 36.81 23.25 38.75 21.31 40.69 19.38 42.63 31k 30.94 35.06 28.88 37.13 26.81 39.19 24.75 41.25 22.69 43.31 20.63 45.38 33k 31.88 36.13 29.75 38.25 27.63 40.38 33.75 38.25 31.5 40.5 29.25 42.75 42.5 23.38 44.63 21.25 46.75 34k 45 24.75 47.25 22.5 49.5 36k 32.81 37.19 30.63 39.38 28.44 41.56 26.25 43.75 24.06 45.94 21.88 48.13 35k 34.69 39.31 32.38 41.63 30.06 43.94 27.75 46.25 25.44 48.56 23.13 50.88 37k
35.63 40.38 33.25 42.75 30.88 45.13 47.5 26.13 49.88 23.75 52.25 38k

01100 01101 01110 01111 10000 10001 10010 10011 10100 10101 10110 10111 11000 11001 11010 11011 11100 11101 11110

36.56 41.44 34.13 43.88 31.69 46.31 29.25 48.75 26.81 51.19 24.38 53.63 39k 37.5 42.5 35 45 32.5 47.5 30 31.5 33 34.5 36 37.5 50 27.5 52.5 25 55 40k 38.44 43.56 35.88 46.13 33.31 48.69 30.75 51.25 28.19 53.81 25.63 56.38 41k 39.38 44.63 36.75 47.25 34.13 49.88 41.25 46.75 38.5 49.5 35.75 52.25 52.5 28.88 55.13 26.25 57.75 42k 55 30.25 57.75 27.5 60.5 44k 40.31 45.69 37.63 48.38 34.94 51.06 32.25 53.75 29.56 56.44 26.88 59.13 43k 42.19 47.81 39.38 50.63 36.56 53.44 33.75 56.25 30.94 59.06 28.13 61.88 45k 43.13 48.88 40.25 51.75 37.38 54.63 45 51 42 54 39 57 57.5 31.63 60.38 28.75 63.25 46k 60 33 63 30 66 48k 44.06 49.94 41.13 52.88 38.19 55.81 35.25 58.75 32.31 61.69 29.38 64.63 47k 45.94 52.06 42.88 55.13 39.81 58.19 36.75 61.25 33.69 64.31 30.63 67.38 49k 46.88 53.13 43.75 56.25 40.63 59.38 62.5 34.38 65.63 31.25 68.75 50k 41.1 69.77 39.47 75 52k 47.81 54.19 44.63 57.38 41.44 60.56 38.25 63.75 35.06 66.94 31.88 70.13 51k 49.18 54.55 46.88 57.69 44.78 61.22 42.86 65.22 50.63 57.38 47.25 60.75 43.88 64.13 52.5 59.5 49 63 45.5 66.5 40.5 42 49.69 56.31 46.38 59.63 43.06 62.94 39.75 66.25 36.44 69.56 33.13 72.88 53k 67.5 37.13 70.88 33.75 74.25 54k 70 38.5 73.5 35 77 56k 51.56 58.44 48.13 61.88 44.69 65.31 41.25 68.75 37.81 72.19 34.38 75.63 55k 53.44 60.56 49.88 64.13 46.31 67.69 42.75 71.25 39.19 74.81 35.63 78.38 57k

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Functional Description
Table 9-51. Receiver Demodulation High Frequency (HCFS = 1) RXDCR CFQ 001 Min. Max. 010 Min. Max. 011 Min. Max. 100 Min. Max. 101 Min. Max. 110 Min. Max. (Hz)

00011 01000 01011 01011

375 450

425 510

350 420

450 540

325 390

475 570

300 360 375

500 600

275 330

525 630

250 300

550 400k 660 480k

421.9 478.1 393.8 506.3 365.6 534.4 337.5 562.5 309.4 590.6 281.3 618.8 450k 468.8 531.3 437.5 562.5 406.3 593.8 625 343.8 656.3 312.5 687.5 500k

9.12.6.6 CIR Baud Rate Divisor Low Byte Register (BDLR)

The BDLR, an 8-bit read/write register, is used to program the CIR Baud Rate clock.
Address: Base Address + 5h (when BR = 1) Bit 7-0 R/W R/W Default 00h Description Baud Rate Divisor Low Byte (BDLR[7:0]) These bits are the low byte of the register used to divide the Baud Rate clock.

9.12.6.7 CIR Baud Rate Divisor High Byte Register (BDHR)

The BDHR, an 8-bit read/write register, is used to program the CIR Baud Rate clock.
Address: Base Address + 6h (when BR = 1) Description Baud Rate Divisor High Byte (BDHR[7:0]) These bits are the high byte of the register used to divide the Baud Rate clock. Baud rate divisor = 115200 / baud rate Ex1: 2400 bps 115200 /2400 = 48 48(d) = 0030(h) BDHR = 00h, BDLR = 30h Ex2: bit width = 0.565 ms ( 1770 bps ( 115200 / 1770 = 65(d) = 0041(h) ( BDHR = 00(h), BDLR = 41(h) 9.12.6.8 CIR Transmitter Status Register (TSR) Bit 7-0 R/W R/W Default 00h

The TSR, an 8-bit read only register, provides the Transmitter FIFO status.
Address: Base Address + 5h Bit 7-6 5-0 R/W R R Default 000000b Description Reserved Transmitter FIFO Byte Count (TXFBC[5:0]) Return the number of bytes left in the Transmitter FIFO.

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IT8726F
9.12.6.9 CIR Receiver FIFO Status Register (RSR)

The RSR, an 8-bit read only register, provides the Receiver FIFO status.
Address: Base Address + 6h Bit 7 R/W R Default 0b Description Receiver FIFO Time-out (RXFTO) This bit will be set to 1 when a Receiver FIFO time-out condition occurs. The conditions that must exist for a Receiver FIFO time-out condition to occur include the followings: a. At least one byte has been in the Receiver FIFO is not empty for 64 ms more b. The receiver has been inactive (RXACT=0) for over 64 ms or more c. More than 64 ms have elapsed since the last byte was read from the Receiver FIFO by the CPU Reserved Receiver FIFO Byte Count (RXFBC) Return the number of bytes left in the Receiver FIFO.

6 5-0

000000b

9.12.6.10

CIR Interrupt Identification Register (IIR)

The IIR, an 8-bit register, is used to identify the pending interrupts.

Address: Base address + 7h Bit 7-3 2-1 R/W R Default 00b Description Reserved Interrupt Identification These two bits are used to identify the source of the pending interrupt. IIR[1:0] Interrupt Source

00 01 10 0 R 1b

No interrupt Transmitter Low Data Level Interrupt Receiver Data Stored Interrupt

11 Receiver FIFO Overrun Interrupt Interrupt Pending This bit will be set to 1 while an interrupt is pending.

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Functional Description
9.13 Game Port Interface

The Game Port integrates four timers for two joysticks. The IT8726F allows the Game Port base address to be located anywhere within the host I/O address space from 100h to 0FFFh. Currently, most game software assume that the Game (or Joystick) I/O port is located at 201h. A write to the Game port base address will trigger four timers. A read from the same address returns four bits that correspond to the outputs from the four timers and four status bits corresponding to the joystick buttons. A button value of 0 indicates that the button is pressed. When the Game port base address is written, the X/Y timer bits go high. Once the Game port base address is written, each timer output remains high for a period of time specified by the current joystick position.
9.13.1 Bit Game Port (Base+0h) Symbol Description

7 6 5 4 3 2 1 0
9.14

JSBB2 JSBB1 JSAB2 JSAB1 JSBCY JSBCX JSACY JSACX

Joystick B, Button 2 ( pin 20 of Joystick connector) Joystick B, Button 1 ( pin 21 of Joystick connector) Joystick A, Button 2 ( pin 24 of Joystick connector) Joystick A, Button 1 ( pin 25 of Joystick connector) Joystick B, Coordinate Y ( pin 22 of Joystick connector) Joystick B, Coordinate X ( pin 23 of Joystick connector) Joystick A, Coordinate Y ( pin 26 of Joystick connector) Joystick A, Coordinate X ( pin 27 of Joystick connector)

MIDI Interface

The IT8726F supports the MIDI capability by incorporating hardware to emulate the MPU-401 in the UART mode. It is software compatible with MPU-401 interface, but only supports the UART mode (non-intelligent mode). The UART is used to convert parallel data to the serial data required by MIDI. The serial data format is RS-232 like: 1 start bit, 8 data bits, and 1 stop bit. The serial data rate is fixed at 31.25K baud.
9.14.1 MPU-401 Register Interface

The MPU-401 logical device occupies two consecutive I/O spaces. The device also uses an interrupt. Both the base address and the interrupt level are programmable. MIDI Base+0 is the MIDI Data port, and MIDI Base+ 1 is the Command/Status port.
MIDI Data Port: The MIDI Data Port is used to transmit and receive MIDI data. When in UART mode, all transmit data are transferred through a 16-byte FIFO and receive data through another 16-byte FIFO. MIDI Data Port, MIDI base+0, Read/Write Bit Symbol Description 7-0 D7-D0 MIDI data 7-0 Command/Status Port: The Command register is used to send instructions to the MPU-401. The Status register is used to receive status information from the MPU-401. These two registers occupy the same I/O address.

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IT8726F
Command Port, MIDI base+1, Write Only Bit 7-0 Symbol Description C7-C0 MIDI instruction command code 7-0

Status Port, MIDI base+1, Read Only Bit Symbol 7 RXS Receive Buffer Status Flag 0: Data in Receive Buffer. 1: Receive Buffer empty. 6 TXS Transmit Buffer Status Flag 0: Transmit Buffer not full. 1: Transmit Buffer full. 5-0 Reserved, always report 3Fh 9.14.2 Operation

Description

In the IT8726F, only two MPU-401 device instructions are available: RESET (code: FFh) and UART mode command (code: 3Fh). After power-up reset, the interface is in the Intelligent mode (non-UART mode). In this mode, the operation is defined as follows: 1. 2. 3. All reads of the DATA port, MIDI base+0, return the acknowledged code (FEh). Because only two commands are available, the receive buffer is always placed an acknowledge code in the intelligent mode. All writes to the DATA port, MIDI base+0, are ignored. All writes to the Command port, MIDI base+1, are monitored and acknowledged as follows: 3Fh: Sets the interface into the UART mode and loads an acknowledged code (FEh) into the receive buffer which generates an interrupt. FFh: Sets the interface into the initialization condition. Others: Not implemented.

UART Mode: 1. All reads of the DATA port, MIDI base+0, return the next byte in the receive buffer FIFO. The serial data received from the MIDI_IN pin is stored in the receive buffer FIFO. The bit 7 RXS of the Status register is updated to reflect the new receive buffer FIFO state. The receive data available interrupt will be issued only if the FIFO has reached its programmed trigger level. They will be cleared as soon as the FIFO drops below its trigger level. The trigger level is programmable by changing bits 2-1 of the MIDI port Special Configuration register, LDN8_F0h. 2. All writes to the DATA port, MIDI base+0, are placed in the transmit buffer FIFO. Whenever the transmit buffer FIFO is not empty, the data bytes are read from the buffer in turn and sent out from the MIDI_OUT pin. The bit 6 TXS of the Status register is updated to reflect the new transmit buffer FIFO state. 3. All writes to the Command port, MIDI base+1, are monitored and acknowledged as follows: FFh: Sets the interface into the initial condition. The interface returns to the intelligent mode. Others: No operation.

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DC Electrical Characteristics

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DC Electrical Characteristics
10. DC Electrical Characteristics
Absolute Maximum Ratings*

Applied Voltage ....................................-0.5V to 5.5V Input Voltage (Vi)....................... -0.5V to VCC+0.5V Output Voltage (Vo)................. -0.5V to VCC + 0.3V Operation Temperature (Topt) ............ 0C to +70C Storage Temperature .................... -55C to +125C Power Dissipation ........................................ 300mW

*Comments Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to this device. These are stress ratings only. Functional operation of this device at these or any other conditions above those indicated in the operational sections of this specification is not implied or intended. Exposure to the absolute maximum rating conditions for extended periods may affect device reliability.

DC Electrical Characteristics (VCC = 5V 5%, Ta = 0C to + 70C) Symbol Parameter Condition Min. Typ. Max. Unit DO8 Buffer VOL Low Output Voltage VOH High Output Voltage DOD8 Buffer VOL Low Output Voltage DO16 Buffer VOL Low Output Voltage

IOL = 8 mA IOH = -8 mA IOL = 8 mA IOL = 16 mA IOH = -16 mA IOL = 24 mA IOH = -16 mA IOL = 24 mA IOH = -8 mA IOL = 8 mA IOH = -8 mA 2.4 2.4 2.4 2.4 2.4

0.4

V V

0.4 0.4

V V V

VOH

High Output Voltage

DO24 Buffer VOL Low Output Voltage

0.4

V V

High Output Voltage DO24L Buffer VOL Low Output Voltage High Output Voltage DIO8 Type Buffer VOL Low Output Voltage VOH VIL VIH IIL IIH IOZ High Output Voltage Low Input Voltage High Input Voltage Low Input Leakage High Input Leakage 3-state Leakage VOH

VOH

0.4

V V

0.4 0.8 2.2

V V V V
A

VIN = 0 VIN = VCC

10 -10 20

A A

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IT8726F
DC Electrical Characteristics (VCC = 5V 5%, Ta = 0C to + 70C)[contd] Symbol Parameter Condition Min. Typ. Max. Unit DIOD8 Type Buffer VOL Low Output Voltage

IOL = 8 mA 2.2 VIN = 0 VIN = VCC 10

0.4 0.8

V V V
A

VIL VIH IIL IIH IOZ

Low Input Voltage High Input Voltage Low Input Leakage High Input Leakage

-10 20

A A

3-state Leakage DIO16 Type Buffer VOL VOH VIL VIH IIL IIH Low Output Voltage High Output Voltage Low Input Voltage High Input Voltage Low Input Leakage High Input Leakage VIN = 0 VIN = VCC 2.2 10 IOL = 16 mA IOH = -16 mA 2.4

0.4 0.8

V V V V
A

-10 20

A A

IOZ 3-state Leakage DIOD16 Type Buffer VOL VIL VIH IIL IIH Low Output Voltage Low Input Voltage High Input Voltage Low Input Leakage High Input Leakage VIN = 0 VIN = VCC 2.2 10 IOL = 16 mA

0.4 0.8

V V V
A

-10 20

A A

IOZ 3-state Leakage DIO24 Type Buffer VOL VOH VIL VIH IIL IIH Low Output Voltage High Output Voltage Low Input Voltage High Input Voltage Low Input Leakage High Input Leakage VIN = 0 VIN = VCC 2.2 10 IOL = 24 mA IOH = -16 mA 2.4

0.4 0.8

V V V V
A

-10 20 0.8 2.2

A A

IOZ 3-state Leakage DI Type Buffer VIL VIH IIL Low Input Voltage High Input Voltage Low Input Leakage VIN = 0 10

V V
A

IIH High Input Leakage VIN = VCC AI Type Buffer for AMD CPU power sequence function Vtrig
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-10 2.25 -

Trigger point for VDDA_25 170

VCC=5V

IT8726F V0.3

DC Electrical Characteristics
Vhyst Vtrig Vhyst Vtrig Vhyst Hysteresis for VDDA_25 Trigger point for VDIMM_STR Hysteresis for VDIMM_STR Trigger point for VLDT_12 Hysteresis for VLDT_12 VCC=5V VCC=5V 200 1.6V 130 1.0 100 mV V mV V mV

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AC Characteristics
11. AC Characteristics (VCC = 5V 5%, Ta = 0C to + 70C)
11.1 Clock Input Timings Symbol Parameter Min.
1

Typ.

Max.

Unit

t1 t2 t3 t4 t5

Clock High Pulse Width when CLKIN=48 MHz Clock Low Pulse Width when CLKIN=48 MHz Clock Period when CLKIN=48 MHz
1

8 8 20 21 22 18 18 40 42 44

nsec nsec nsec nsec nsec nsec

Clock High Pulse Width when CLKIN=24 MHz Clock Low Pulse Width when CLKIN=24 MHz
1

t6 Clock Period when CLKIN=24 MHz Not tested. Guaranteed by design.

t1 , t 4 2.2V

t2 ,t5

0.8V t3 ,t6

Figure 11-1. Clock Input Timings 11.2 LCLK (PCICLK) and LRESET Timings Parameter Min. Typ. Max. Unit

Symbol

t1 t2 t3 t4

LCLK Cycle Time LCLK High Time LCLK Low Time LRESET# Low Pulse Width

28 11 11 1.5

nsec nsec nsec

sec

t2 0.6VCC

t3 0.4VCC p-to-p (minimum) 0.2VCC t1

Figure 11-2. LCLK (PCICLK) and LRESET Timings

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IT8726F
11.3 LPC and SERIRQ Timings Parameter Min. Typ. Max. Unit Symbol

t1 t2 t3 t4 t5

Float to Active Delay Output Valid Delay Active to Float Delay Input Setup Time Input Hold Time

3 12 6 9 3

nsec nsec nsec nsec nsec

LCLK

t2 t1 t3

LPC Signals/ SERIRQ (Output) LPC Signals/ SERIRQ (Input)

Input Valid

t4

t5

Figure 11-3. LPC and SERIRQ Timings

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AC Characteristics
11.4 Serial Port, ASKIR, SIR and Consumer Remote Control Timings Parameter Conditions Min. Max.
Note1

Symbol

Unit

t1 t2 t3

Single Bit Time in Serial Port and ASKIR Modulation Signal Pulse Width in ASKIR Modulation Signal Period in ASKIR

Transmitter Receiver Transmitter Receiver Transmitter Receiver Transmitter, Fixed Receiver

tBTN 25 950 500 1975

tBTN + 25 tBTN + 2% 1050 2025 2000X(25/24) 1.78

nsec nsec nsec nsec nsec nsec

sec sec

tBTN 2%

2000X(23/24) 1.48 1

Transmitter, Variable (3/16) x tBTN 25 (3/16) x tBTN + 25 nsec t4 SIR Signal Pulse Width

Note 1: tBTN is the nominal bit time in Serial Port, ASKIR, and SIR. It is determined by the setting on the Baud Rate Divisor registers.
Serial Port t1

t2 Sharp-IR Consumer Remote Control t4 SIR

t3

Figure 11-4. Serial Port, ASKIR, SIR and Consumer Remote Control Timings 11.5 Modem Control Timings Parameter Min. Typ. Max. Unit

Symbol

t1

Float to active delay

CTS1#, DSR1#, DCD1#, CTS2#, DSR2#, DCD2# Interrupt (Internal signal) RI1#, RI2# t1
(Read MSR)

40

nsec

t1
(Read MSR)

t1

Figure 11-5. Modem Control Timings www.ite.com.tw

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IT8726F
11.6 Floppy Disk Drive Timings Parameter Min. Typ. Max. Unit Symbol

t1 t2 t3 t4 t5 t6 t7

DIR# active to STEP# low STEP# active time (low) DIR# hold time after STEP# STEP# cycle time INDEX# low pulse width RDATA# low pulse width WDATA# low pulse width 2X tmclk 40

4X tmclk tSRT

Note1

nsec nsec msec msec nsec nsec

24X tmclk
Note2

tSRT

1X tmclk

nsec

Note 1: tmclk is the cycle of main clock for the microcontroller of FDC. tmclk =8M/ 4M/ 2.4M/ 2M for 1M/ 500K/ 300K/ 250 Kbps transfer rates respectively. Note 2: tSRT is the cycle of the Step Rate Time. Please refer to the functional description of the SPECIFY command of the FDC.
t3 DIR# t2 t1 STEP# t5 INDEX# t6 RDATA# t7 WDATA# t4

Figure 11-6. Floppy Disk Drive Timings

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AC Characteristics
11.7 EPP Address or Data Write Cycle Timings Parameter Min. Typ. Max. Unit

Symbol

t1 t2 t3 t4 t5 t6

WRITE# asserted to PD[7:0] valid ASTB# or DSTB# asserted to WAIT# de-asserted WAIT# de-asserted to ASTB# or DSTB# de-asserted ASTB# or DSTB# de-asserted to WAIT# asserted WAIT# asserted to WRITE# de-asserted PD[7:0] invalid after WRITE# de-asserted 0 65 0 65 0

50 10 135

nsec nsec nsec nsec nsec nsec

WRITE# t3 ASTB# DSTB# t2 WAIT# t1 PD[ 7:0 ] t5 t4 t6

Figure 11-7. EPP Address or Data Write Cycle Timings

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IT8726F
11.8 EPP Address or Data Read Cycle Timings Parameter Min. Typ. Max. Unit

Symbol

t1 t2 t3 t4 t5 t6

ASTB# or DSTB# asserted to WAIT# de-asserted ASTB# or DSTB# asserted to PD[7:0] Hi-Z PD[7:0] valid to WAIT# de-asserted WAIT# de-asserted to ASTB# or DSTB# de-asserted ASTB# or DSTB# de-asserted to WAIT# asserted PD[7:0] invalid after ASTB# or DSTB# de-asserted 0 0 65 0 20

10

nsec nsec nsec

135

nsec nsec nsec

WRITE# ASTB# DSTB# t1 WAIT# t2 PD[ 7:0 ] t3 t6 t4 t5

Figure 11-8. EPP Address or Data Read Cycle Timings 11.9 ECP Parallel Port Forward Timings Parameter Min. Typ. Max. Unit

Symbol

t1 t2 t3 t4 t5 t6
PD[7:0], nAutoFd

PD[7:0] and nAutoFd valid to nStrobe asserted nStrobe asserted to Busy asserted Busy asserted to nStrobe de-asserted nStrobe de-asserted to Busy de-asserted Busy de-asserted to PD[7:0] and nAutoFd changed Busy de-asserted to nStrobe asserted 0 70 0 80 70

50 170 180 170

nsec nsec nsec nsec nsec nsec

t1 nStrobe t2 Busy t3 t4

t5

t6

Figure 11-9. ECP Parallel Port Forward Timings www.ite.com.tw

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AC Characteristics
11.10 ECP Parallel Port Backward Timings Symbol Parameter Min. Typ. Max. Unit

t1 t2 t3 t4 t5 t6

PD[7:0] valid to nAck asserted nAck asserted to nAutoFd asserted nAutoFd asserted to nAck de-asserted nAck de-asserted to nAutoFd de-asserted nAutoFd de-asserted to PD[7:0] changed nAutoFd de-asserted to nAck asserted

0 70 0 70 0 0 170 170

nsec nsec nsec nsec nsec nsec

PD[7:0] t1 nAck t2 nAutoFd t3 t4 t6 t5

Figure 11-10. ECP Parallel Port Backward Timings 11.11 RSMRST#, PWROK1/2, and ACPI Power Control Signals Timings Symbol Parameter Min. Typ. Max. Unit

t1 t2 t3

RSMRST# de-actives delay from VCCH5V=4V PWROK1/2 active delay from VCC5V=4V Overlap of PSON# and 3VSBSW#

13 350 8.5

16 400 10

19 450 11.5

msec msec msec

VCCH5V RSMRST#

VCCH5V=4+- 0.2V

VCCH5V=3.5+- 0.2V

<--

t1

-->

Figure 11-11. RSMRST# Timings

VCC5V
RESETCON#

VCC5V=4+- 0.2V

VCC5V=3.5+- 0.2V

PWROK1/2

<--

t2

-->

Figure 11-12. PWROK1/2 Timings

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IT8726F
SUSB# SUSC# EN_STR PWROK1/2 3VSBSW# PSON#

t3 --> t3 --> <--

<--

Figure 11-13. ACPI Power signals Timings 11.12 AMD CPU Power Sequence Signals Timings

Power on
t0 t1 t2 t3 t4 t5

Timing Sequence Enter S3 Exit S3

t11 t6 t7 t8 t0 t1 t3 t4 t5

Power off
t11 t6 t7 t8 t9 t10

EN_STR SUSB# PSON# ATX_PWRGD VDIMM_STR_EN VDDA_EN VCORE_EN VCORE_GD VLDT_EN CPU_PG

Table 11-1. Power Sequence AC Timing Parameter Item t0 t1 t2 Min Description 0 The falling edge of SUSB# to the assertion of PSON#. The rising edge of ATX_PWRGD to the assertion of VDIMM_STR_EN. 2ms + 2ms The assertion of VDIMM_STR_EN to the assertion of VDDA_EN. t_vdimm_g The t_vdimm_gd is the rise time of the VDIMM_STR_EN voltage from 0V d to 1.62V. 2ms + 2ms The assertion of VDDA_EN to the assertion of VCORE_EN. t_vdda_gd The t_vdda_gd is the rise time of the VDDA voltage from 0V to 2.25V. 50us The rising edge of VCORE_GD to the assertion of VLDT_EN. 2ms The assertion of VLDT_EN to the assertion of CPU_PWRGD. 2ms + t_vldt_gd The t_vldt_gd is the rise time of the VLDT voltage from 0V to 1.0V. 50us The de-assertion of CPU_PG to the de-assertion of VLDT_EN. 10ms The de-assertion of VLDT_EN to the de-assertion of VCORE_EN. 150ms The falling edge of VCORE_GD to the de-assertion of VDDA_EN. 10ms The de-assertion of VDDA_EN to the de-assertion of VDIMM_STR_EN or PSON#. 50ms The de-assertion of VDIMM_STR_EN to the de-assertion of PSON#. 50us The rising edge of SUSB# to the de-assertion of CPU_PG. Max Typ 1us 50us

t3 t4 t5 t6 t7 t8 t9 t10 t11

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Package Information
12. Package Information
QFP 128L Outline Dimensions unit: inches/mm
D D1 102 103 65 64
C

b
WITH PLATING

E1 E

BASE METAL

DETAIL "A"

128 1 e b 38 SEE DETAIL "B" A A2

39

L SEATING PLANE 0.10 y DETAIL "A"

O GAGE PLANE

A1

DETAIL "B"

L1

Symbol

Dimension in inches

Dimension in mm

Min.

Nom.

Max.

Min. 0.25 2.73 0.17 0.09 23.00 19.90 17.00 13.90

Nom.

Max.

A A1 A2 b c D D1 E E1 e L L1 y

0.134 0.010 0.107 0.112 0.117 0.007 0.009 0.011 0.004 0.008 0.906 0.913 0.921 0.783 0.787 0.791 0.669 0.677 0.685 0.547 0.551 0.555 0.020 BSC 0.029 0.035 0.041 0.063 BSC 0.004 0 7

3.40 2.85 2.97 0.22 0.27 0.20 23.20 23.40 20.00 20.10 17.20 17.40 14.00 14.10 0.5 BSC 0.73 0.88 1.03 1.60 BSC 0.10 0 7

Notes: 1. Dimensions D1 and E1 do not include mold protrusion. But mold mismatch is included. 2. Dimensions b does not include dambar protrusion. 3. Controlling dimension: millimeter DI-QFP128(14*20)v2 www.ite.com.tw

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Ordering Information
13. Ordering Information
Part No. Package

IT8726F

128 QFP

ITE also provides lead-free component. Please mark " -L " at the end of the Part No. when the parts ordered are lead-free.

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Top Marking Information

14. Top Marking Information

PART NO. DATE CODE (The seventh week of the year 2006) LOT NO.

PACKAGE TYPE
IT8726F-S 0607-#XS XXXXXX L

FUNCTION CODE (Option) VERSION ASSEMBLY HOUSE WAFER SOURCE For Lead free package (Other Option)

1. PACKAGE TYPE: R: SSOP M: SOP E: LQFP TE: TQFP 2. WAFER SOURCE: Y: 6 Inch Wafer House 3. ASSEMBLY HOUSE: S: SPIL(SILICONWARE PRECISION INDUSTRIES CO.,LTD.) A: ASE(ADVANCED SEMICONDUCTOR ENGINEENING INC. ) L: LS(LINGSEN PRECISION INDUSTRIES , LTD.) T: ticp(Taiwan IC Packaging Corporation ) 4. OTHERS: L: FOR LEAD FREE PACKAGE(XXXXXX L) X8 Inch Wafer House N: TSSOP F: QFP G: BGA

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