UNIT-2

1 a) Draw the pin diagram of the 8085 microprocessor and categorize the pins based on
function. [L4] [CO2] [8M]

Address Bus and Data Bus:

Address bus - A15-A8, it carries the most significant 8-bits of memory/IO address.
Data bus - AD7-AD0, it carries the least significant 8-bit address and data bus
Control and Status Signals:
 ALE – It is an Address Latch Enable signal. It goes high during first T state of a machine cycle
and
enables the lower 8-bits of the address, if its value is 1 otherwise data bus is activated.
 IO/M’– It is a status signal which determines whether the address is for input-output or
memory. 
When it is high(1) the address on the address bus is for input-output devices. When it is low(0)
the
address on the address bus is for the memory.
 SO, S1 – These are status signals. They distinguish the various types of operations such as halt,
reading, and instruction fetching or writing. 
 RD’ – It is a signal to control READ operation. When it is low the selected memory or input-
output
device is read.
 WR’ – It is a signal to control WRITE operation. When it goes low the data on the data bus is
written into the selected memory or I/O location. 
 READY – It senses whether a peripheral is ready to transfer data or not. If READY is high(1)
the
peripheral is ready. If it is low(0) the microprocessor waits till it goes high. It is useful for
interfacing low speed devices.
Power Supply and Clock Frequency:
 Vcc – +5v power supply
 Vss – Ground Reference
 XI, X2 – A crystal is connected at these two pins. The frequency is internally divided by two,
therefore, to operate a system at 3MHZ the crystal should have frequency of 6MHZ. 
 CLK (OUT) – This signal can be used as the system clock for other devices.
Interrupts and Peripheral Initiated Signals:
The 8085 has five interrupt signals that can be used to interrupt a program execution.
1. INTR
2. RST 7.5
3. RST 6.5
4. RST 5.5
5. TRAP
The microprocessor acknowledges Interrupt Request by INTA’ signal. In addition to Interrupts,
there are
three externally initiated signals namely RESET, HOLD and READY. To respond to HOLD
request, it has
one signal called HLDA.
 INTR – It is an interrupt request signal. 
 INTA’ – It is an interrupt acknowledgment sent by the microprocessor after INTR is received. 
Reset Signals:
 RESET IN’ – When the signal on this pin is low(0), the program-counter is set to zero, the
buses
are tristated and the microprocessor unit is reset.
 RESET OUT – This signal indicates that the MPU is being reset. The signal can be used to
reset
other devices.
DMA Signals:
 HOLD – It indicates that another device is requesting the use of the address and data bus.
Having
received HOLD request the microprocessor relinquishes the use of the buses as soon as the
current
machine cycle is completed. Internal processing may continue. After the removal of the HOLD
signal the processor regains the bus.
 HLDA – It is a signal which indicates that the hold request has been received after the removal
of a
HOLD request, the HLDA goes low.
Serial I/O Ports:
Serial transmission in 8085 is implemented by the two signals, SID and SOD. SID is a data line for serial
input
whereas SOD is a data line for serial output.

b) Outline the role of the following pins in the8085 microprocessor

i) RESET OUT ii) ALE iii) HOLD & HLDA iv) TRAP [L2] [CO2] [4M]
i) RESET OUT − This signal is used to reset all the connected devices when the microprocessor
is reset.
ii) ALE — Address Latch Enable: This is positive going pulse generated every time the 8085
begins an operation (machine cycle); it indicates that the bits on AD7-AD0 are address bits. This
is used primarily to latch the low-order address from the multiplexed bus and generate a separate
set of eight address lines, A7- A0.

iii) HOLD and HLDA

 The Hold and Hold Acknowledge signals are used for Direct Memory Access (DMA).

 The DMA Controller issued the Hold signal to the μP. In response the μP releases the System
bus.
 After releasing the system bus the μP acknowledges the Hold signal with HLDA signal. 

 The DMA Transfer thus begins.

 DMA Transfer is terminated by releasing the HOLD signal. 

iv) TRAP
A non-maskable interrupt is a Trap interrupt which implies that whenever this pin gets activated,
the 8085 always gets interrupted even if the stat of 8085 is in DI. The input of Trap input is level
sensitive and edge sesitive.

2. a) Define an interrupt and explain the different types of interrupts available in the 8085
microprocessors. [L2] [CO2] [6M]
Interrupt is a signal emitted by hardware or software when a process or an event needs
immediate
attention. It alerts the processor to a high priority process requiring interruption of the current
working
process. In I/O devices one of the bus control lines is dedicated for this purpose and is called the
Interrupt
Service Routine (ISR).

Types of Interrupts in 8085: Five hardware interrupts in 8085

1. TRAP

2. RST 7.5

3. RST 6.5

4. RST 5.5

5. INTR
TRAP:
 This is an edge as well as level triggered, vectored interrupt.

 It cannot be masked by SIM instruction and can neither be disabled by DI instruction. 

 It has the highest priority.

 Its vector address is 0024H.

RST 7.5
 This is an edge triggered, vectored interrupt.

 It can be masked by SIM instruction and can also be disabled by DI instruction.

 It has the second highest priority.

 Its vector address is 003CH.

RST 6.5
 This is a level triggered, vectored interrupt.

 It can be masked by SIM instruction and can also be disabled by DI instruction.

 It has the third highest priority.

 Its vector address is 0034H.

RST 5.5
 This is a level triggered, vectored interrupt.

 It can be masked by SIM instruction and can also be disabled by DI instruction.

 It has the fourth highest priority.

 Its vector address is 002CH.

INTR:
 This is a level triggered, non-vectored interrupt.

 It cannot be masked by SIM instruction but can be disabled by DI instruction. 

 It has the lowest priority.

 It has an acknowledgement signal INTA. 

 The address for the ISR is fetched from external

Hardware INTA:
 This is an acknowledgement signal for INTR (only).
 This signal is used to get the Op-Code (and hence the ISR address) from External hardware

in order to execute the ISR.

ALL Interrupts EXCEPT TRAP can be disabled though the DI instruction. These interrupts
can be
enabled again by the EI Instruction. Interrupts can be individually masked or unmasked by
SIM
instruction. TRAP and INTR are not affected by SIM instruction.
b) Explain the role of control &status signals in the 8085 microprocessor. [L1] [CO2[6M]
Control and status signals
These signals are used to identify the nature of operation. There are 3 control signal and 3 status
signals. Three control signals are RD, WR & ALE.
RD − This signal indicates that the selected IO or memory device is to be read and is ready for
accepting data available on the data bus.
WR − This signal indicates that the data on the data bus is to be written into a selected memory
or IO
location.
ALE − It is a positive going pulse generated when a new operation is started by the
microprocessor.
When the pulse goes high, it indicates address. When the pulse goes down it indicates data.
Three status signals are IO/M, S0 & S1.
IO/M - This signal is used to differentiate between IO and Memory operations, i.e. when it is
high
indicates IO operation and when it is low then it indicates memory operation.
S1 & S0 - These signals are used to identify the type of current operation
3 a) Discuss how the dataflow from memory to Microprocessor with neat diagram.
[L2] [CO2] [6M]
Data flow from memory to Microprocessor Unit for understanding the functions of various signals of the
8085, we
examine the process of communication (reading from and writing into memory) between the
microprocessor and
memory and the timings of these signals in relation to the system clock. The first step in the
communication process
is reading from memory or fetching an instruction.
Example: Illustrate the steps and the timing of data when the instruction code 0100 1111 (4FH—MOV C,
A), stored
in location 2005H, is being fetched.
For fetching the byte (4FH), the MPU needs to identify the memory location 2005H and enable the data
flow from
memory. This is called the Fetch cycle. The data flow is shown in Figure and the timings are explained
below

Fig 1 Data Flow from Memory to the MPU

b) Draw the timing diagram for transfer of byte from memory to microprocessor
[L4] [CO2] [6M]

Fig 2. Timing diagram of opcode fetch

To fetch the byte, the MPU performs the following steps:
Step 1: The program counter places the 16-bit memory address on the address bus Figure.2 shows that at
T1 the high-order memory address 20H is placed on the address lines A15- A8, the low-order memory
address 05H is placed on the busAD7- AD0, and the ALE signal goes high. Similarly, the status signal IO/
goes low, indicating that this is a memory-related operation. (For the sake of clarity, the other two status
signals, S1 and S0, are not shown in Figure 2

Step 2: The control unit sends he control signal to enable the memory chip The control signal is
sent out during the clock period T2, thus enabling the memory chip. The is active during two clock
periods.
Step 3: The byte from the memory location is placed on the data bus. When the memory is enabled, the
instruction byte (4FH) is placed on the busAD7 - AD0 and transferred to the microprocessor. The
signal causes 4FH to be placed on bus AD7-AD0 (shown by the arrow), and when goes high, it
causes the bus to go into high impedance.

Step 4: The byte is placed in the instruction decoder of the microprocessor, and the task is carried out
according to the instruction. The machine code or the byte (4FH) is decoded by the instruction decoder,
and the contents of the accumulator are copied into register C. This task is performed during the period T 4
in Figure.2

4 a) With a neat sketch and explain, the De-multiplexing of the Bus AD7- AD0 in 8085.
[L3][CO3] [6M]

The address in 8085 contains 16 bits, and data contains 8 pins, needs 24 pins in IC to be used
as address and data pins, rather than this designer as a different approach to reduce the usage of
pins for address & data. Only 16pins are used totally for address and data, in which 8 pins (AD 0
-AD 7) are combined, used to generate address & data.
Microprocessor generates both data & addresses one same 8 pins. The thing is to resolve both
address & data from these pins. This process is achieved through de multiplexing the address &
data signals

Demulplexing of address and data Busses (AD7 – AD0)

The address bus has 8 signal lines A8 –A15which are unidirectional. The other 8 address bits are
multiplexed (time shared) with the 8 data bits. So, the bits AD0 –AD7 are bi-directional and
serve as A0 – A7 and D0 –D7 at the same time. During the execution of the instruction, these
lines carry the address bits during the early part, then during the late parts of the execution, they
carry the 8 data bits. In order to separate the address from the data, we can use a latch to save the
value before the function of the bits changes. AD7–AD0 lines are serving a dual purpose and
that they need to be de multiplexed to get all the information. The high order bits of the address
remain on the bus for three clock periods. However, the low order bits remain for only one clock
period and they would be lost if they are not saved externally.
Also, the low order bits of the address disappear . The entire address for the full three clock
cycles, An external latch will be used to save the value of AD7–AD0 when it is carrying the
address bits. The ALE signal is used to enable this latch. ALE operates as a pulse during T1, we
will be able to latch the address. Then when ALE goes low, the address is saved and the AD7–
AD0 lines can be used for their purpose as the bi-directional data lines. The high order address is
placed on the address bus and hold for 3 clk periods, the low order address is lost after the first
clk period, this address needs to be holding however we need to use latch. The address AD7 –
AD0 is connected as inputs to the latch 74LS373.

b) Illustrate the generating control signal in 8085 Microprocessor. [L2] [CO2] [6M]
 Timing and control unit is a very important unit as it synchronizes the registers and flow of data through
various registers and other units.
 This unit consists of an oscillator and controller sequencer which sends control signals needed for
internal and external control of data and other units.
 The oscillator generates two-phase clock signals which aids in synchronizing all the registers of 8085

microprocessor.
 We use Timing and Controlling unit in 8085 for the generation of timing signals and the signals to
control. All the operations and functions both interior and exterior of a microprocessor are controlled by
this unit.

Block diagram representation of Timing & Control unit

Signals that are associated with Timing and control unit are:
1. Control Signals: READY, RD(bar), WR(bar),ALE

2. Status Signals: S0, S1,IO/M(bar)

3. DMA Signals: HOLD,HLDA

4. RESET Signals: RESET IN(bar), RESETOUT.

READY: It is used to sense whether the peripheral is ready or not for data transfer, If it is not ready, the
processor waits. Thus it is used to synchronize slower peripherals.
Address latch enable (ALE) : It is used to separate multiplexed address and data
bus.S0 & S1: It indicates the type of machine cycle in progress.
RESET Signals: RESETIN’ –Sets the PC to Zero and clears the INTE flag. RESET OUT–It is used to
reset other devices connected externally.
DMA Signals: HOLD–This signal indicates that another master is requesting to use address bus, data
and control bus. HLDA–It is used to acknowledge HOLD request.
RD: Read (active low). To indicate that the I/O or memory selected is to be read and data are available
on the bus.
WR: Write( Active low). This is to indicate that the data available on the bus are to be written tomemory
or I/O ports.
IO/M’: To differentiate I/O operation of memory operations. –‘0’ - indicates a memory operation.
–‘1’- indicates an I/O operation. IO/M’ combined with RD’ and WR’ to generate I/O and memorycontrol
sig
 Fig- Generation of control signals

5 a) Sketch neat the block diagram of 8085 Architecture and explain the function of each
block. [L3] [CO3] [8M]

8085 consists of the following functional units −

Accumulator
It is an 8-bit register used to perform arithmetic, logical, I/O & LOAD/STORE operations. It is connected
to internal data bus & ALU.
Arithmetic and logic unit
As the name suggests, it performs arithmetic and logical operations like Addition, Subtraction, AND, OR,
etc. on 8-bit data.

General purpose register

There are 6 general purpose registers in 8085 processor, i.e. B, C, D, E, H & L. Each register can hold 8-
bit data. These registers can work in pair to hold 16-bit data and their pairing combination is like B-C, D-
E & H-L.
Program counter
It is a 16-bit register used to store the memory address location of the next instruction to be executed.
Microprocessor increments the program whenever an instruction is being executed, so that the program
counter points to the memory address of the next instruction that is going to be executed.
Stack pointer It is also a 16-bit register works like stack, which is always incremented/decremented by 2
during push & pop operations.
Temporary register
It is an 8-bit register, which holds the temporary data of arithmetic and logical operations.
Flag register
It is an 8-bit register having five 1-bit flip-flops, which holds either 0 or 1 depending upon the result
stored in the accumulator. These are the set of 5 flip-flops − Sign (S)
 Zero (Z)

 Auxiliary Carry (AC)

 Parity (P)

 Carry (C)

Its bit position is shown in the following table −

D7 D6 D5 D4 D3 D2 D1 D0

S Z - AC - P - CY

Instruction register and decoder

It is an 8-bit register. When an instruction is fetched from memory then it is stored in the Instruction
register. Instruction decoder decodes the information present in the Instruction register.

Timing and control unit

It provides timing and control signal to the microprocessor to perform operations. Following are the
timing and control signals, which control external and internal circuits −
 Control Signals: READY, RD’, WR’, ALE

 Status Signals: S0, S1, IO/M’

 DMA Signals: HOLD, HLDA

 RESET Signals: RESET IN, RESET OUT

Interrupt control
As the name suggests it controls the interrupts during a process. When a microprocessor is executing a
main program and whenever an interrupt occurs, the microprocessor shifts the control from the main
program to process the incoming request. After the request is completed, the control goes back to the
main program.
There are 5 interrupt signals in 8085 microprocessors: INTR, RST 7.5, RST 6.5, RST 5.5, TRAP.
Serial Input/output control
It controls the serial data communication by using these two instructions: SID (Serial input data) and
SOD (Serial output data).
Address buffer and address-data buffer
The content stored in the stack pointer and program counter is loaded into the address buffer and address-
data buffer to communicate with the CPU. The memory and I/O chips are connected to these buses; the
CPU can exchange the desired data with the memory and I/O chips.
Address bus and data bus
Data bus carries the data to be stored. It is bidirectional, whereas address bus carries the location to where
it should be stored and it is unidirectional. It is used to transfer the data & Address I/O devices.

b) Discuss the different types of registers used in the 8085 microprocessors.

[L2] [CO2] [4M]
The classification registers in 8085
1. General purpose registers

2. Special purpose – Accumulator, Flag Register, Program Counter (PC), Stack Pointer (SP)

Figure: Block diagram representation of 8085 registers

GENERAL PURPOSE REGISTERS
The 8085 has six general-purpose registers. These registers are identified as B, C, D, E, H, and L,
W and Z registers are not used in programs. They can be combined as register pairs -— BC, DE,
and HL—to perform some 16-bit operations. These registers are programmable, meaning that a
programmer can use them to load or transfer data from the registers by using instructions.

SPECIAL PURPOSE REGISTERS -

ACCUMULATOR
The accumulator is an 8-bit register that is part of the arithmetic/logic unit (ALU). This register
is used to store 8-bit data and in-performing arithmetic and logical operations. The result of an
operation is stored in the accumulator. The accumulator is also identified as register A.

FLAG REGISTER
The 8085 has five flags to indicate five different types of data conditions. They are Zero (Z),
Carry (CY), Sign (S), Parity (P), and Auxiliary Carry (AC) flags. The most commonly used flags
arc Sign, Zero, and Carry. These flags have critical importance in the decision-making process of
the microprocessor

PROGRAM COUNTER (PC)

This register is a memory pointer. The size of pc is 16 bits. The function of the program counter
isto point to the memory address from which the next byte is to be fetched

STACK POINTER (SP)

The stack pointer is also a 16-bit register It points to a memory location in R/W memory, called
the stack. The beginning of the stack is defined by loading a 16-bit address in the stack pointer
(register).

6 a) Explain the functions of a program counter, stack pointer & ALU in 8085 µP.
[L2] [CO2] [6M]
Program Counter (PC):
Program is a sequence of instructions. Microprocessor fetches these instructions from the
memory andexecutes them sequentially. The program counter is a special purpose register which,
at a given time, stores the address of the next instruction to be fetched. Program counter acts as a
pointer to the next instruction.

Stack pointer (SP):

The stack is a LIFO (last in, first out) data structure implemented in the RAM area and is used to
store addresses and data when the microprocessor branches to a subroutine. The stack in 8085
performs both PUSH and POP operations. Both the operations work together with register pairs
following the LIFO principle. PUSH Operation in a Stack: The SP is decreased, and the higher-
order register pair contents (B in BC and D in DE) are replicated to the stack. Again, the SP is
decreased, and now lower order register pair contents are replicated to the stack. Here no flags or

register pair contents will get modified. POP Operation in the Stack: Stack’s top location
contents are replicated into stack lower register (C in BC). Then SP gets increased by 1. Then the
contents of stack location as shown by SP are replicated into stack’s higher register. Now, SP is
increased by 1.

ALU (Arithmetic and Logical Unit)

The arithmetic and logical unit is the combinational digital electronic circuit that can perform
arithmetic operations on integer binary numbers. It presents the arithmetic and logical operation.
The outputs of ALU will change asynchronously in response to the input. The basic arithmetic
and bitwise logic functions are supported by ALU

8085 has an 8-bit ALU.

 It performs 8-bit arithmetic operations like Addition and Subtraction. 

 It also performs logical operations like AND, OR, EX-OR NOT etc.

 It takes input from the Accumulator and the Temp register.

The output of most of the ALU operations is stored back into the Accumulator.
b) Draw the flag register of the 8085 microprocessor and explaineach bit in detail.
[L2] [CO2] [6M]
The Flag register is a Special Purpose Register. Depending upon the value of result after any
arithmetic and logical operation the flag bits become set (1) or reset (0). In 8085microprocessors,
flag register consists of 8 bits and only 5 of them are useful.
Sign Flag (S): After any operation if the MSB [B(7)] of the result is 1, it indicates the number is
negative and the sign flag becomes set, i.e. 1. If the MSB is 0, it indicates the number is positive

and the sign flag becomes reset i.e.0.from 00H to 7F, sign flag is 0 from 80H to FF, sign flag is 1
1- MSB is 1 (negative) and 0- MSB is 0 (positive)
Example:
MVI A 30 (load 30H in register A) MVI B 40 (load 40H in register B) SUB B (A = A – B)
These set of instructions will set the sign flag to 1 as 30 – 40 is a negative number. MVI A 40
(load 40H in register A) MVI B 30 (load 30H in register B) SUB B (A = A – B) These set of
instructions will reset the sign flag to 0 as 40 – 30 is a positive number.

Zero Flag (Z): After any arithmetical or logical operation if the result is 0 (00)H, the zero flag
becomes set i.e. 1, otherwise it becomes reset i.e. 0.

00H zero flag is 1, from 01H to FFH zero flag is 0 1 for zero result and 0 for non-zero result

Example:

MVI A 10 (load 10H in register A) SUB A (A = A - A)

Auxiliary Carry Flag (AC): This flag is used in BCD number system (0-9). If after any
arithmetic or logical operation D(3) generates any carry and passes on to B(4) this flag becomes
set i.e. 1, otherwise it becomes reset i.e. 0. This is the only flag register which is not accessible
by the programmer 0 for carry out from bit 3 on addition or borrow into bit 3 on subtraction 0-
otherwise
Example:
MOV A 2B (load 2BH in register A) MOV B 39 (load 39H in register B) ADD B (A = A + B)
These set of instructions will set the auxiliary carry flag to 1, as on adding 2B and 39, addition of
lower order nibbles B and 9 will generate a carry.
Parity Flag (P): If after any arithmetic or logical operation the result has even parity, an even
number of 1 bits, the parity register becomes set i.e. 1, otherwise it becomes reset i.e. 0. 1-
accumulator has even number of 1 bits 0-accumulator has odd parity

Example:

MVI A, 05 (load 05H in register A)

This instruction will set the parity flag to 1 as the BCD code of 05H is 00000101, which contains
even number of ones i.e. 2.
Carry Flag (CY): Carry is generated when performing n bit operations and the result is more
than n bits, then this flag becomes set i.e. 1, otherwise it becomes reset i.e. 0.

During subtraction (A-B), if A>B it becomes reset and if (A<B) it becomes set. Carry flag is also
called borrow flag. 1-carry out from MSB bit on addition or borrow into MSB bit on subtraction
0-no carry out or borrow into MSB bit

Example:

MVI A, 30 (load 30H in register A) MVI B 40 (load 40H in register B) SUB B (A = A – B)

These set of instructions will set the carry flag to 1 as 30 – 40 generates a carry/borrow.

MVI A 40 (load 40H in register A) MVI B 30 (load 30H in register B) SUB B (A = A – B)

These set of instructions will reset the sign flag to 0 as 40 – 30 does not generate any
carry/borrow

7 a) List out the instruction sets, Explain the instruction sets withexamples.
[L2][CO2] [6M]
Instruction Formats:

Each instruction (instruction format) is of two parts. One is task to be performed, called the
operation code or opcode and the second one is the data to be operated on, called the operand.
The operands or data can be specified in different ways. It may include an 8-bit or 16- bit data,
an internal register. a memory location, or 8- bit or 16-bit address. In some instructions, the
operand is implicit.

ONE-BYTE INSTRUCTIONS

A one-byte instruction includes a opcode and a operand in the same byte. Operand(s) are internal
registers and are in the instruction in form of codes. If there is no numeral present in the
instruction then that instruction will be of one-byte, for example, MOV C, A, RAL, and ADD B,
etc.

TWO-BYTE INSTRUCTIONS

In a two-byte instruction, the first byte specifies the operation code and second byte specifies the
operand. Source operand is a data byte and immediately following the opcode. If an 8-bit
numeral is present in the instruction, then that instruction will be of two-byte. Here, the numeral
may be a data or an address. For example, in MVI A, 35H and IN 29H, etc.
In a two- byte instruction, the first byte will be the opcode and the second byte will be for the
numeral present in the instruction.

THREE-BYTE INSTRUCTIONS

In a three-byte instruction, the first byte specifies the opcode, and the following two bytes
specify the 16-bit operand. The second byte is the low-order operand and the third byte is the
high-order operand. If a 16-bit numeral is present in the instruction, then that instruction will be
of three-byte. Here, the numeral may be a data or an address, for example, in LXI H,3500H and
STA 2500H.

b) Explain the Data transfer instructions of the 8085 microprocessorwith example.

[L2] [CO2] [6M]

OPCODE OPREND MEANING EXPLAINATION

8 a) Describe the Logical instructions of the 8085 microprocessor with example
[L2][CO2] [6M]
b) Discuss CMA, RAR, RAL, RLC and RRC instructions with suitable example.
[L2] [CO2] [6M]
ROTATE is a logical operation of 8085 microprocessors. It is a 1-byte instruction. This
instruction does not require any operand after the opcode. It operates the content of accumulator
and the result is also stored in the accumulator. The Rotate instruction is used to rotating the bits
of accumulator.

Types of ROTATE Instruction:

There are 4 categories of the ROTATE instruction: Rotate accumulator left (RLC), Rotate
accumulator left through carry (RAL), Rotate accumulator right (RRC), Rotate accumulator right
through carry (RAR). Among these four instructions; two are for rotating left and two are for
rotating right.

Rotate accumulator right through carry (RAR)

In 8085 Instruction set, RAR stands for “Rotate Accumulator Right involving Cy flag in
rotation”. It rotates the Accumulator contents to the right by 1-bit position. From the following
Fig. we are getting the operation details.

Rotate accumulator left through carry (RAL) – In this instruction, each bit is shifted to the
adjacent left position. Bit D7 becomes the carry bit and the carry bit is shifted into D0. Carry flag CY
is modified according to the bit D7.For example:
A = D7 D6 D5 D4 D3 D2 D1 D0
//before the instruction
A = 10101010; CY=0
//after 1st RAL
A = 01010100; CY=1
//after 2nd RAL
A = 10101001; CY=0
Rotate accumulator left (RLC) –
In this instruction, each bit is shifted to the adjacent left position. Bit D7 becomes D0. Carry flag
CY is
modified according to the bit D7.
For example: -
A = D7 D6 D5 D4 D3 D2 D2 D0
//before the instruction
A = 10101010; CY=0
//after 1st RLC
A = 01010101; CY=1
//after 2nd RLC
A = 10101010; CY=0
Rotate accumulator right (RRC) –
In this instruction, each bit is shifted to the adjacent right position. Bit D7 becomes D0. Carry
flag CY is
modified according to the bit D0.
For example:
A = D7 D6 D5 D4 D3 D2 D2 D0
//before the instruction
A = 10000001; CY=0
//after 1st RRC
A = 11000000; CY=1
//after 2nd RRC
A = 01100000; CY=0
9 a) Explain the Arithmetic instructions of the 8085 microprocessor
[L2] [CO2] [6M]
b) Explain the branch control instructions of the 8085 microprocessor
[L2] [CO2] [6M]
Branching instructions refer to the act of switching execution to a different instruction
sequence as a result of executing a branch instruction.
The three types of branching instructions are:

1. Jump (unconditional and conditional)

2. Call (unconditional and conditional)

3. Return (unconditional and conditional)

1. Jump Instructions – The jump instruction transfers the program sequence to the memory
address given in the operand based on the specified flag. Jump instructions are 2 types:
Unconditional Jump Instructions and Conditional Jump Instructions.
(a) Unconditional Jump Instructions: Transfers the program sequence to the
described memory address.

OPCODE OPERAND EXPLANATION EXAMPLE

JMP address Jumps to the address JMP 2050

b) Conditional Jump Instructions: Transfers the program sequence to the described

memory address only if the condition in satisfied.

OPCODE OPERAND EXPLANATION EXAMPLE

JC address Jumps to the address if carry flag is 1 JC 2050

JNC address Jumps to the address if carry flag is 0 JNC 2050

JZ address Jumps to the address if zero flag is 1 JZ 2050

 JNZ address Jumps to the address if zero flag is 0 JNZ 2050

JPE address Jumps to the address if parity flag is 1 JPE 2050

JPO address Jumps to the address if parity flag is 0 JPO 2050

JM address Jumps to the address if sign flag is 1 JM 2050

JP address Jumps to the address if sign flag 0 JP 2050

2. Call Instructions – The call instruction transfers the program sequence to the memory
address given in the operand. Before transferring, the address of the next instruction after
CALL is pushed onto the stack. Call instructions are 2 types: Unconditional Call Instructions
and Conditional Call Instructions.
(a) Unconditional Call Instructions: It transfers the program sequence to the memory
address given in the operand.

OPCODE OPERAND EXPLANATION EXAMPLE

CALL address Unconditionally calls CALL 2050

(b) Conditional Call Instructions: Only if the condition is satisfied, the instructions executes.

OPCODE OPERAND EXPLANATION EXAMPLE

CC address Call if carry flag is 1 CC 2050

CNC address Call if carry flag is 0 CNC 2050

CZ address Calls if zero flag is 1 CZ 2050

CNZ address Calls if zero flag is 0 CNZ 2050

 CPE address Calls if parity flag is 1 CPE 2050

CPO address Calls if parity flag is 0 CPO 2050

CM address Calls if sign flag is 1 CM 2050

CP address Calls if sign flag is 0 CP 2050

3. Return Instructions – The return instruction transfers the program sequence from the
subroutine to the calling program. Return instructions are 2 types: Unconditional Jump
Instructions and Conditional Jump Instructions.
(a) Unconditional Return Instruction: The program sequence is transferred unconditionally
from the subroutine to the calling program.

OPCODE OPERAND EXPLANATION EXAMPLE

RET none Return from the subroutine RET

unconditionally

(b) Conditional Return Instruction: The program sequence is transferred unconditionally

from the subroutine to the calling program only is the condition is satisfied.

OPCODE OPERAND EXPLANATION EXAMPLE

RC none Return from the subroutine if carry flag is 1 RC

RNC none Return from the subroutine if carry flag is 0 RNC

RZ none Return from the subroutine if zero flag is 1 RZ

RNZ none Return from the subroutine if zero flag is 0 RNZ

RPE none Return from the subroutine if parity flag is 1 RPE

 RPO none Return from the subroutine if parity flag is 0 RPO

RM none Returns from the subroutine if sign flag is 1 RM

RP none Returns from the subroutine if sign flag is 0 RP

10 a) Discuss conditional jump and unconditional jump instruction with an example

[L2] [CO3] [6M]
1. Jump Instructions – The jump instruction transfers the program sequence to the memory
address given in the operand based on the specified flag. Jump instructions are 2 types:
Unconditional Jump Instructions and Conditional Jump Instructions.
(a) Unconditional Jump Instructions: Transfers the program sequence to the
described memory address.

OPCODE OPERAND EXPLANATION EXAMPLE

JMP address Jumps to the address JMP 2050

b) Conditional Jump Instructions: Transfers the program sequence to the described

memory address only if the condition in satisfied.

OPCODE OPERAND EXPLANATION EXAMPLE

JC address Jumps to the address if carry flag is 1 JC 2050

JNC address Jumps to the address if carry flag is 0 JNC 2050

JZ address Jumps to the address if zero flag is 1 JZ 2050

JNZ address Jumps to the address if zero flag is 0 JNZ 2050

JPE address Jumps to the address if parity flag is 1 JPE 2050

 JPO address Jumps to the address if parity flag is 0 JPO 2050

JM address Jumps to the address if sign flag is 1 JM 2050

JP address Jumps to the address if sign flag 0 JP 2050

b) Discuss the data format and storage with an example

Data Formats and storage:

.DATA STORAGE