DWC Hdmi TX Databook

DesignWare® Cores HDMI Transmitter Controller
Databook
HDMI 1.3 TX Controller (without HDCP) – Product Code: 6934-0

HDMI 1.4 TX Controller (without HDCP) – Product Code: 4916-0
HDMI 1.4 TX Controller (with HDCP) – Product Code: 4922-0
HDMI 2.0 TX Controller (with HDCP) – Product Code: 7400-0
Version 2.12a
April 2016
HDMI Transmitter Controller Databook
Copyright Notice and Proprietary Information

© 2016 Synopsys, Inc. All rights reserved. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use,
reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
Destination Control Statement
All technical data contained in this publication is subject to the export control laws of the United States of America. Disclosure to nationals
of other countries contrary to United States law is prohibited. It is the reader's responsibility to determine the applicable regulations and
to comply with them.
Disclaimer
SYNOPSYS, INC., AND ITS LICENSORS MAKE NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS
MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
PARTICULAR PURPOSE.
Trademarks
Synopsys and certain Synopsys product names are trademarks of Synopsys, as set forth at
http://www.synopsys.com/Company/Pages/Trademarks.aspx.
All other product or company names may be trademarks of their respective owners.
Third-Party Links
Any links to third-party websites included in this document are for your convenience only. Synopsys does not endorse and is not
responsible for such websites and their practices, including privacy practices, availability, and content.
Synopsys, Inc.
690 E. Middlefield Road
Mountain View, CA 94043
www.synopsys.com
2 SolvNet Synopsys, Inc. Version 2.12a

DesignWare.com April 2016
Contents
Preface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Databook Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Related Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Web Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Customer Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Chapter 1
Product Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
1.1 General Product Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
1.1.1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
1.1.2 Standards Compliance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
1.1.3 Unsupported Features and Exceptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
1.1.4 HDMI Operational Model Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
1.2 Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
1.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
1.4 Speed and Clock Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
1.5 Area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Chapter 2
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
2.1 DWC_hdmi_tx Functional Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
2.2 Video Pixel Sampler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
2.3 Supported Video Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
2.4 Video Packetizer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
2.5 HDMI 2.0 TMDS Scrambling Feature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
2.6 Color Space Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
2.7 Audio Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
2.7.1 Supported Audio Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
2.7.2 I2S interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
2.7.3 S/PDIF Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
2.7.4 Generic Parallel Audio (GPA) Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
2.7.5 AHB Audio DMA Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
2.7.6 CTS Calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
2.8 Frame Composer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
2.8.1 Data Island Packets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
2.9 HDCP Encryption Engine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
2.9.1 HDCP 1.4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
2.9.2 HDCP 2.2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
2.10 AMBA APB 3.0 Slave Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Version 2.12a Synopsys, Inc. SolvNet 3

April 2016 DesignWare.com
Contents HDMI Transmitter Controller Databook
2.11 HDMI Tx PHY Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105

2.12 E-DID/HDCP/SCDC I2C E-DDC Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
2.12.1 I2C Master Interface Normal Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
2.12.2 I2C Master Interface Extended Read Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .107
2.12.3 I2C Master Interface SCDC Read Update . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
2.12.4 I2C Clock Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
2.13 CEC Hardware Engine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
Chapter 3
Parameter Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
3.1 Interfaces Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
3.2 Feature Definition Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
3.3 FPGA Prototyping Definition Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
3.4 Metastability Option Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
Chapter 4
Signal Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
4.1 Naming and Description Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
4.1.1 Signal Name . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
4.1.2 Signal Name Prefix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
4.1.3 Signal Name Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
4.2 Signal Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
4.2.1 Video Input Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
4.2.2 Audio Input Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
4.2.3 System and Slave Register Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
4.2.4 E-DDC Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
4.2.5 CEC Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
4.2.6 HDCP 1.4 Encryption Engine Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
4.2.7 HDCP 2.2 Encryption Engine Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
4.2.8 Scan Test Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
4.2.9 HDMI Tx PHY Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
4.2.10 HDMI 3-D TX PHY (PHY GEN 2) Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
4.2.11 HDMI HEAC PHY Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
4.2.12 HDMI-MHL TX PHY Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
4.2.13 HDMI 2.0 TX PHY Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
4.2.14 HDMI Tx External PHY Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
Chapter 5
Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
5.1 System and Slave Register Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
5.2 Video Input Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
5.3 I2S Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
5.4 S/PDIF Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
5.5 Generic Parallel Audio (GPA) Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
5.6 AHB Audio DMA Input Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
5.7 CEC Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
5.8 HDMI TX PHY Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
5.9 E-DDC Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
5.10 HDCP 1.4 Encryption Engine Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
5.11 HDCP 2.2 Encryption Engine Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148

HDMI Transmitter Controller Databook Contents
5.12 HDMI 3-D TX PHY (PHY GEN 2) Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157

5.13 HDMI-MHL or HDMI 2.0 TX PHY Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .159
5.14 HDMI TX External PHY Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
5.15 Scan Test Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
5.16 HDMI HEAC PHY Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181
Chapter 6
Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185
6.1 Identification Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189
6.1.1 design_id . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190
6.1.2 revision_id . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190
6.1.3 product_id0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191
6.1.4 product_id1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191
6.1.5 config0_id . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192
6.1.6 config1_id . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193
6.1.7 config2_id . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194
6.1.8 config3_id . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195
6.2 Interrupt Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196
6.2.1 ih_fc_stat0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197
6.2.2 ih_fc_stat1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198
6.2.3 ih_fc_stat2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199
6.2.4 ih_as_stat0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200
6.2.5 ih_phy_stat0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201
6.2.6 ih_i2cm_stat0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202
6.2.7 ih_cec_stat0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203
6.2.8 ih_vp_stat0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204
6.2.9 ih_i2cmphy_stat0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205
6.2.10 ih_ahbdmaaud_stat0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206
6.2.11 ih_decode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207
6.2.12 ih_mute_fc_stat0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208
6.2.13 ih_mute_fc_stat1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209
6.2.14 ih_mute_fc_stat2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210
6.2.15 ih_mute_as_stat0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211
6.2.16 ih_mute_phy_stat0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212
6.2.17 ih_mute_i2cm_stat0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213
6.2.18 ih_mute_cec_stat0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214
6.2.19 ih_mute_vp_stat0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215
6.2.20 ih_mute_i2cmphy_stat0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216
6.2.21 ih_mute_ahbdmaaud_stat0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217
6.2.22 ih_mute . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218
6.3 VideoSampler Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219
6.3.1 tx_invid0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220
6.3.2 tx_instuffing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222
6.3.3 tx_gydata0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223
6.3.4 tx_gydata1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223
6.3.5 tx_rcrdata0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224
6.3.6 tx_rcrdata1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224
6.3.7 tx_bcbdata0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225
6.3.8 tx_bcbdata1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225

6.4 VideoPacketizer Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226

6.4.1 vp_status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227
6.4.2 vp_pr_cd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228
6.4.3 vp_stuff . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230
6.4.4 vp_remap . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232
6.4.5 vp_conf . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233
6.4.6 vp_mask . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234
6.5 FrameComposer Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235
6.5.1 fc_invidconf . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243
6.5.2 fc_inhactiv0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244
6.5.3 fc_inhactiv1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245
6.5.4 fc_inhblank0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245
6.5.5 fc_inhblank1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246
6.5.6 fc_invactiv0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246
6.5.7 fc_invactiv1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247
6.5.8 fc_invblank . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247
6.5.9 fc_hsyncindelay0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248
6.5.10 fc_hsyncindelay1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248
6.5.11 fc_hsyncinwidth0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249
6.5.12 fc_hsyncinwidth1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249
6.5.13 fc_vsyncindelay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250
6.5.14 fc_vsyncinwidth . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250
6.5.15 fc_infreq0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251
6.5.16 fc_infreq1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251
6.5.17 fc_infreq2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252
6.5.18 fc_ctrldur . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252
6.5.19 fc_exctrldur . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253
6.5.20 fc_exctrlspac . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253
6.5.21 fc_ch0pream . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254
6.5.22 fc_ch1pream . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254
6.5.23 fc_ch2pream . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255
6.5.24 fc_aviconf3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255
6.5.25 fc_gcp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 256
6.5.26 fc_aviconf0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257
6.5.27 fc_aviconf1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258
6.5.28 fc_aviconf2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259
6.5.29 fc_avivid . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260
6.5.30 fc_avietb[0:1] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260
6.5.31 fc_avisbb[0:1] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261
6.5.32 fc_avielb[0:1] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261
6.5.33 fc_avisrb[0:1] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262
6.5.34 fc_audiconf0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262
6.5.35 fc_audiconf1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263
6.5.36 fc_audiconf2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263
6.5.37 fc_audiconf3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264
6.5.38 fc_vsdieeeid0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264
6.5.39 fc_vsdsize . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265
6.5.40 fc_vsdieeeid1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265
6.5.41 fc_vsdieeeid2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266

6.5.42 fc_vsdpayload[0:23] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266

6.5.43 fc_spdvendorname[0:7] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267
6.5.44 fc_spdproductname[0:15] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267
6.5.45 fc_spddeviceinf . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 268
6.5.46 fc_audsconf . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 268
6.5.47 fc_audsstat . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269
6.5.48 fc_audsv . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 270
6.5.49 fc_audsu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271
6.5.50 fc_audschnl0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272
6.5.51 fc_audschnl1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272
6.5.52 fc_audschnl2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273
6.5.53 fc_audschnl3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273
6.5.54 fc_audschnl4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274
6.5.55 fc_audschnl5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274
6.5.56 fc_audschnl6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275
6.5.57 fc_audschnl7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275
6.5.58 fc_audschnl8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 276
6.5.59 fc_ctrlqhigh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 276
6.5.60 fc_ctrlqlow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 277
6.5.61 fc_acp0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 277
6.5.62 fc_acp16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 278
6.5.63 fc_acp15 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 278
6.5.64 fc_acp14 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 279
6.5.65 fc_acp13 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 279
6.5.66 fc_acp12 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 280
6.5.67 fc_acp11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 280
6.5.68 fc_acp10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 281
6.5.69 fc_acp9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 281
6.5.70 fc_acp8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 282
6.5.71 fc_acp7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 282
6.5.72 fc_acp6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 283
6.5.73 fc_acp5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 283
6.5.74 fc_acp4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 284
6.5.75 fc_acp3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 284
6.5.76 fc_acp2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 285
6.5.77 fc_acp1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 285
6.5.78 fc_iscr1_0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 286
6.5.79 fc_iscr1_16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 286
6.5.80 fc_iscr1_15 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287
6.5.81 fc_iscr1_14 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287
6.5.82 fc_iscr1_13 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 288
6.5.83 fc_iscr1_12 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 288
6.5.84 fc_iscr1_11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 289
6.5.85 fc_iscr1_10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 289
6.5.86 fc_iscr1_9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 290
6.5.87 fc_iscr1_8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 290
6.5.88 fc_iscr1_7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291
6.5.89 fc_iscr1_6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291
6.5.90 fc_iscr1_5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 292

6.5.91 fc_iscr1_4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 292

6.5.92 fc_iscr1_3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293
6.5.93 fc_iscr1_2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293
6.5.94 fc_iscr1_1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 294
6.5.95 fc_iscr2_15 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 294
6.5.96 fc_iscr2_14 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 295
6.5.97 fc_iscr2_13 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 295
6.5.98 fc_iscr2_12 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 296
6.5.99 fc_iscr2_11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 296
6.5.100 fc_iscr2_10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 297
6.5.101 fc_iscr2_9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 297
6.5.102 fc_iscr2_8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 298
6.5.103 fc_iscr2_7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 298
6.5.104 fc_iscr2_6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 299
6.5.105 fc_iscr2_5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 299
6.5.106 fc_iscr2_4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300
6.5.107 fc_iscr2_3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300
6.5.108 fc_iscr2_2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 301
6.5.109 fc_iscr2_1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 301
6.5.110 fc_iscr2_0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 302
6.5.111 fc_datauto0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 303
6.5.112 fc_datauto1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 304
6.5.113 fc_datauto2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 304
6.5.114 fc_datman . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 305
6.5.115 fc_datauto3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 306
6.5.116 fc_rdrb0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 307
6.5.117 fc_rdrb1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 307
6.5.118 fc_rdrb2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 308
6.5.119 fc_rdrb3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 308
6.5.120 fc_rdrb4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 309
6.5.121 fc_rdrb5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 309
6.5.122 fc_rdrb6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 310
6.5.123 fc_rdrb7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 310
6.5.124 fc_rdrb8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 311
6.5.125 fc_rdrb9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 311
6.5.126 fc_rdrb10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 312
6.5.127 fc_rdrb11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 312
6.5.128 fc_rdrb12 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 313
6.5.129 fc_rdrb13 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 313
6.5.130 fc_mask0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 314
6.5.131 fc_mask1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 315
6.5.132 fc_mask2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 316
6.5.133 fc_prconf . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 317
6.5.134 fc_scrambler_ctrl . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 319
6.5.135 fc_multistream_ctrl . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 320
6.5.136 fc_packet_tx_en . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 321
6.5.137 fc_actspc_hdlr_cfg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 323
6.5.138 fc_invact_2d_0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 323
6.5.139 fc_invact_2d_1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 324

6.5.140 fc_gmd_stat . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 325

6.5.141 fc_gmd_en . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 326
6.5.142 fc_gmd_up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 327
6.5.143 fc_gmd_conf . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 328
6.5.144 fc_gmd_hb . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 329
6.5.145 fc_gmd_pb[0:27] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 330
6.5.146 fc_amp_hb1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 330
6.5.147 fc_amp_hb2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 331
6.5.148 fc_amp_pb[0:27] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 331
6.5.149 fc_nvbi_hb1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 332
6.5.150 fc_nvbi_hb2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 332
6.5.151 fc_nvbi_pb[0:26] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 333
6.5.152 fc_drm_up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 333
6.5.153 fc_drm_hb[0:1] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 334
6.5.154 fc_drm_pb[0:26] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 334
6.5.155 fc_dbgforce . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 335
6.5.156 fc_dbgaud0ch0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 335
6.5.157 fc_dbgaud1ch0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 336
6.5.158 fc_dbgaud2ch0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 336
6.5.159 fc_dbgaud0ch1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 337
6.5.160 fc_dbgaud1ch1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 337
6.5.161 fc_dbgaud2ch1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 338
6.5.162 fc_dbgaud0ch2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 338
6.5.163 fc_dbgaud1ch2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 339
6.5.164 fc_dbgaud2ch2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 339
6.5.165 fc_dbgaud0ch3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 340
6.5.166 fc_dbgaud1ch3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 340
6.5.167 fc_dbgaud2ch3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 341
6.5.168 fc_dbgaud0ch4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 341
6.5.169 fc_dbgaud1ch4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 342
6.5.170 fc_dbgaud2ch4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 342
6.5.171 fc_dbgaud0ch5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 343
6.5.172 fc_dbgaud1ch5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 343
6.5.173 fc_dbgaud2ch5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 344
6.5.174 fc_dbgaud0ch6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 344
6.5.175 fc_dbgaud1ch6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 345
6.5.176 fc_dbgaud2ch6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 345
6.5.177 fc_dbgaud0ch7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 346
6.5.178 fc_dbgaud1ch7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 346
6.5.179 fc_dbgaud2ch7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 347
6.5.180 fc_dbgtmds[0:2] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 347
6.6 PHYConfiguration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 348
6.6.1 phy_conf0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 350
6.6.2 phy_tst0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 351
6.6.3 phy_tst1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 352
6.6.4 phy_tst2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 352
6.6.5 phy_stat0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 353
6.6.6 phy_int0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 354
6.6.7 phy_mask0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 355

6.6.8 phy_pol0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 356

6.6.9 PHY_PCLFREQ0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 357
6.6.10 PHY_PCLFREQ1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 357
6.6.11 PHY_PLLCFGFREQ0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 358
6.6.12 PHY_PLLCFGFREQ1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 358
6.6.13 PHY_PLLCFGFREQ2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 359
6.6.14 phy_i2cm_slave . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 359
6.6.15 phy_i2cm_address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 360
6.6.16 phy_i2cm_datao_1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 360
6.6.17 phy_i2cm_datao_0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 361
6.6.18 phy_i2cm_datai_1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 361
6.6.19 phy_i2cm_datai_0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 362
6.6.20 phy_i2cm_operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 362
6.6.21 phy_i2cm_int . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 363
6.6.22 phy_i2cm_ctlint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 364
6.6.23 phy_i2cm_div . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 365
6.6.24 phy_i2cm_softrstz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 366
6.6.25 phy_i2cm_ss_scl_hcnt_1_addr . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 366
6.6.26 phy_i2cm_ss_scl_hcnt_0_addr . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 367
6.6.27 phy_i2cm_ss_scl_lcnt_1_addr . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 367
6.6.28 phy_i2cm_ss_scl_lcnt_0_addr . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 368
6.6.29 phy_i2cm_fs_scl_hcnt_1_addr . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 368
6.6.30 phy_i2cm_fs_scl_hcnt_0_addr . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 369
6.6.31 phy_i2cm_fs_scl_lcnt_1_addr . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 369
6.6.32 phy_i2cm_fs_scl_lcnt_0_addr . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 370
6.6.33 phy_i2cm_sda_hold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 370
6.6.34 jtag_phy_config . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 371
6.6.35 jtag_phy_tap_tck . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 372
6.6.36 jtag_phy_tap_in . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 372
6.6.37 jtag_phy_tap_out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 373
6.6.38 jtag_phy_addr . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 373
6.7 AudioSample Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 374
6.7.1 aud_conf0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 375
6.7.2 aud_conf1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 376
6.7.3 aud_int . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 377
6.7.4 aud_conf2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 378
6.7.5 aud_int1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 379
6.8 AudioPacketizer Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 380
6.8.1 aud_n1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 381
6.8.2 aud_n2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 381
6.8.3 aud_n3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 382
6.8.4 aud_cts1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 383
6.8.5 aud_cts2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 383
6.8.6 aud_cts3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 384
6.8.7 aud_inputclkfs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 385
6.8.8 aud_cts_dither . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 386
6.9 AudioSampleSPDIF Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 387
6.9.1 aud_spdif0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 388
6.9.2 aud_spdif1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 389

6.9.3 aud_spdifint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 390

6.9.4 aud_spdifint1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 391
6.9.5 aud_spdif2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 391
6.10 AudioSampleGP Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 392
6.10.1 gp_conf0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 393
6.10.2 gp_conf1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 393
6.10.3 gp_conf2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 394
6.10.4 gp_mask . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 395
6.11 AudioDMA Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 396
6.11.1 ahb_dma_conf0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 397
6.11.2 ahb_dma_start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 399
6.11.3 ahb_dma_stop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400
6.11.4 ahb_dma_thrsld . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 401
6.11.5 ahb_dma_straddr_set0[0:3] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 402
6.11.6 ahb_dma_stpaddr_set0[0:3] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 403
6.11.7 ahb_dma_bstraddr[0:3] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 404
6.11.8 ahb_dma_mblength0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 404
6.11.9 ahb_dma_mblength1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 405
6.11.10 ahb_dma_mask . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 406
6.11.11 ahb_dma_conf1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 407
6.11.12 ahb_dma_buffmask . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 407
6.11.13 ahb_dma_mask1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 408
6.11.14 ahb_dma_status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 408
6.11.15 ahb_dma_conf2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 409
6.11.16 ahb_dma_straddr_set1[0:3] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 409
6.11.17 ahb_dma_stpaddr_set1[0:3] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 410
6.12 MainController Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 411
6.12.1 mc_clkdis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 412
6.12.2 mc_swrstzreq . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 413
6.12.3 mc_opctrl . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 414
6.12.4 mc_flowctrl . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 415
6.12.5 mc_phyrstz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 415
6.12.6 mc_lockonclock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 416
6.12.7 mc_heacphy_rst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 417
6.12.8 mc_lockonclock_2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 417
6.12.9 mc_swrstzreq_2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 418
6.13 ColorSpaceConverter Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 419
6.13.1 csc_cfg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 421
6.13.2 csc_scale . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 422
6.13.3 csc_coef_a1_msb . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 423
6.13.4 csc_coef_a1_lsb . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 424
6.13.5 csc_coef_a2_msb . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 425
6.13.6 csc_coef_a2_lsb . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 425
6.13.7 csc_coef_a3_msb . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 426
6.13.8 csc_coef_a3_lsb . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 426
6.13.9 csc_coef_a4_msb . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 427
6.13.10 csc_coef_a4_lsb . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 427
6.13.11 csc_coef_b1_msb . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 428
6.13.12 csc_coef_b1_lsb . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 428

6.13.13 csc_coef_b2_msb . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 429

6.13.14 csc_coef_b2_lsb . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 429
6.13.15 csc_coef_b3_msb . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 430
6.13.16 csc_coef_b3_lsb . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 430
6.13.17 csc_coef_b4_msb . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 431
6.13.18 csc_coef_b4_lsb . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 431
6.13.19 csc_coef_c1_msb . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 432
6.13.20 csc_coef_c1_lsb . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 432
6.13.21 csc_coef_c2_msb . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 433
6.13.22 csc_coef_c2_lsb . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 433
6.13.23 csc_coef_c3_msb . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 434
6.13.24 csc_coef_c3_lsb . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 434
6.13.25 csc_coef_c4_msb . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 435
6.13.26 csc_coef_c4_lsb . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 435
6.13.27 csc_limit_up_msb . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 436
6.13.28 csc_limit_up_lsb . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 436
6.13.29 csc_limit_dn_msb . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 437
6.13.30 csc_limit_dn_lsb . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 437
6.14 HDCP Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 438
6.14.1 a_hdcpcfg0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 440
6.14.2 a_hdcpcfg1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 441
6.14.3 a_hdcpobs0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 442
6.14.4 a_hdcpobs1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 442
6.14.5 a_hdcpobs2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 443
6.14.6 a_hdcpobs3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 444
6.14.7 a_apiintclr . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 445
6.14.8 a_apiintstat . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 446
6.14.9 a_apiintmsk . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 447
6.14.10 a_vidpolcfg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 448
6.14.11 a_oesswcfg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 449
6.14.12 a_coreverlsb . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 449
6.14.13 a_corevermsb . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 450
6.14.14 a_ksvmemctrl . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 451
6.14.15 hdcp_bstatus[0:1] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 452
6.14.16 hdcp_m0[0:7] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 452
6.14.17 hdcp_ksv[0:634] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 453
6.14.18 hdcp_vh[0:19] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 454
6.14.19 hdcp_revoc_size_0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 454
6.14.20 hdcp_revoc_size_1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 455
6.14.21 hdcp_revoc_list[0:5059] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 455
6.14.22 hdcpreg_bksv0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 456
6.14.23 hdcpreg_bksv1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 456
6.14.24 hdcpreg_bksv2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 457
6.14.25 hdcpreg_bksv3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 457
6.14.26 hdcpreg_bksv4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 458
6.14.27 hdcpreg_anconf . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 458
6.14.28 hdcpreg_an0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 459
6.14.29 hdcpreg_an1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 459
6.14.30 hdcpreg_an2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 460

6.14.31 hdcpreg_an3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 460

6.14.32 hdcpreg_an4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 461
6.14.33 hdcpreg_an5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 461
6.14.34 hdcpreg_an6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 462
6.14.35 hdcpreg_an7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 462
6.14.36 hdcpreg_rmlctl . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 463
6.14.37 hdcpreg_rmlsts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 463
6.14.38 hdcpreg_seed0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 464
6.14.39 hdcpreg_seed1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 464
6.14.40 hdcpreg_dpk0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 465
6.14.41 hdcpreg_dpk1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 465
6.14.42 hdcpreg_dpk2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 466
6.14.43 hdcpreg_dpk3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 466
6.14.44 hdcpreg_dpk4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 467
6.14.45 hdcpreg_dpk5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 467
6.14.46 hdcpreg_dpk6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 468
6.15 HDCP22 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 469
6.15.1 hdcp22reg_id . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 470
6.15.2 hdcp22reg_ctrl . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 471
6.15.3 hdcp22reg_ctrl1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 473
6.15.4 hdcp22reg_sts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 474
6.15.5 hdcp22reg_mask . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 475
6.15.6 hdcp22reg_stat . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 476
6.15.7 hdcp22reg_mute . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 477
6.16 CEC Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 478
6.16.1 cec_ctrl . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 479
6.16.2 cec_mask . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 481
6.16.3 cec_addr_l . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 482
6.16.4 cec_addr_h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 483
6.16.5 cec_tx_cnt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 484
6.16.6 cec_rx_cnt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 485
6.16.7 cec_tx_data[0:15] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 485
6.16.8 cec_rx_data[0:15] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 486
6.16.9 cec_lock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 486
6.16.10 cec_wakeupctrl . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 487
6.17 EDDC Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 489
6.17.1 i2cm_slave . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 490
6.17.2 i2cm_address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 491
6.17.3 i2cm_datao . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 491
6.17.4 i2cm_datai . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 492
6.17.5 i2cm_operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 493
6.17.6 i2cm_int . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 494
6.17.7 i2cm_ctlint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 495
6.17.8 i2cm_div . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 496
6.17.9 i2cm_segaddr . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 496
6.17.10 i2cm_softrstz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 497
6.17.11 i2cm_segptr . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 497
6.17.12 i2cm_ss_scl_hcnt_1_addr . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 498
6.17.13 i2cm_ss_scl_hcnt_0_addr . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 498

6.17.14 i2cm_ss_scl_lcnt_1_addr . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 499

6.17.15 i2cm_ss_scl_lcnt_0_addr . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 499
6.17.16 i2cm_fs_scl_hcnt_1_addr . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500
6.17.17 i2cm_fs_scl_hcnt_0_addr . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500
6.17.18 i2cm_fs_scl_lcnt_1_addr . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 501
6.17.19 i2cm_fs_scl_lcnt_0_addr . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 501
6.17.20 i2cm_sda_hold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 502
6.17.21 i2cm_scdc_read_update . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 502
6.17.22 i2cm_read_buff0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 503
6.17.23 i2cm_read_buff1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 503
6.17.24 i2cm_read_buff2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 504
6.17.25 i2cm_read_buff3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 504
6.17.26 i2cm_read_buff4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 505
6.17.27 i2cm_read_buff5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 505
6.17.28 i2cm_read_buff6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 506
6.17.29 i2cm_read_buff7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 506
6.17.30 i2cm_scdc_update0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 507
6.17.31 i2cm_scdc_update1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 507
Chapter A
Internal Parameter Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 509
Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 511

Revision History
Date Version Description

April 2016 2.12a Updated:
■ Support of HDMI 2.0b specification
■ Table 1-1 on page 42 (added footnotes for ispdifclk, ii2sclk, igpaclk, iapbclk, and idmaclk)
■ Figure 2-6 on page 62 (corrected equations for CSC matrix)
■ “CTS Calculation” on page 79 (only one section needed for Audio Interfaces)
■ “HDCP 2.2” on page 105 (updated support information)
■ “HDCP 2.2 Encryption Engine Interface Signals” on page 124
■ Parameters:
- HDCP Version (HTX_HDCP_TYPE)
■ Signals:
- ispdifdata[3:0] (Registered field)
- “Scan Test Interface Signals” on page 169 (Exists field for most signals except for those
with “Always” as the value)
■ Registers:
- revision_id.revision_id
- aud_cts_dither (added note to bit fields)
- dividend
- divisor
- mc_opctrl
- mc_opsts
- a_apiintmsk (Value After Reset in register bits)
■ “Internal Parameters” on page 509
Added:
■ Synopsys HDMI PHY with At-Speed Scan
■ Note in “Data Island Scheduler” on page 88
■ Parameters:
- HDCP 2.2 Wrapper External Type (HTX_HDCP22_EXTERNAL_TYPE)
■ Signals:
- New at-speed scan signals in “Scan Test Interface Signals” on page 168 (depending on
HDMI PHY type)

Revision History HDMI Transmitter Controller Databook
(Continued)
June 2015 2.11a Added:
■ Dynamic Range and Mastering InfoFrame (DRM, packet header 0x87)
- ih_fc_stat2.DRM
- ih_mute_fc_stat2.DRM
- fc_datauto3.drm_auto
- fc_rdrb12
- fc_rdrb13
- fc_mask2.DRM
- fc_packet_tx_en.drm_tx_en
- fc_drm_up
- fc_drm_hb1 to fc_drm_hb2
- fc_drm_pb1 to fc_drm_pb27
■ I2C Bus Clear mechanism (Star 9000863135)
■ CTS dithering in manual mode (aud_cts_dither register)
■ Table 2-13 on page 80
Updated:
■ “Area” on page 43
■ HDMI Specification support (2.0 -> 2.0a)
■ Figure 2-4 on page 61
■ “CTS Calculation” on page 79
■ Signals
- Synchronous to: and Registered fields
irstz idpkack
ogpadatareg orevocmemaddress
odmahsize ohdcptmdsclk
odmahwdata ohdcptmdsrstz
odmahwrite iphyext_jtag_tdo
icecin iphyext_jtag_tdo_en
ii2c_msth13tddc_sclin iphyext_i2c_sclin
ii2c_msth13tddc_sdain iphyext_i2c_sdain
- Synchronous to: field for following signals:

- idmahresetn
- odpkclk

HDMI Transmitter Controller Databook Revision History
(Continued)
June 2015 2.11a Continued
Cont’d Cont’d Updated:
- orevocmemclk
- iphyext_tclk
- iphyext_prepclk
- Registered field for following signals:
iapbaddr iapbsel iapbenable
iapbwrite iapbwdata ii2sclk
ispdifdata igpaclk igpavalid
igpadata idmahclk idmahresp
idmahready idmahgrant oi2c_msth13tddc_sclout
oi2c_msth13tddc_sdaout idpkmemdatai odpkaddr
idpkdatain orndnumgenena irndnum
orevocmemdataout irevocmemdatain orevocmemcs
orevocmemwen ohdcpsfrrstz ist_hdcp2_capable
ist_hdcp2_not_capable ist_hdcp_authentication_lost ist_hdcp_authenticated
ist_hdcp_authentication_fail ihdcp_i2c_req ohdcp_i2c_grant
ophyext_i2c_sclout ohdcp_i2c_byte_xferd_p ihdcp_i2c_write
ihdcp_i2c_read ihdcp_i2c_addr ihdcp_i2c_slvaddr
ihdcp_i2c_datao ihdcp_i2c_short_read ihdcp_i2c_seq_access
ihdcp_i2c_fastmode ohdmi_color_depth
■ Registers
- aud_cts_3 (removed N_shift functionality – Star 9000879005)
Removed:
- References to Synopsys HDCP 2.2. For more information about this feature, contact
Synopsys Customer Support.
May 2015 2.10a Updated Table 2-2 on page 50 (Supported Video Modes - Star 9000880216)
January 2015 2.10a Added:
■ 4x2 S/PDIF channel support
■ Synopsys HDCP 2.2 Encryption Engine
■ HDCP SHA-1 calculation in hardware
■ Support for PCUV mapping on I2S audio data
■ APB Secure memory map
■ Spyglass support for Lint and CDC
■ Signals:
- oh22_int_nsec
- oh22_int_sec
- isec_apbclk
- isec_apbrstz
- isec_apbaddr
- isec_apbsel

(Continued)
January 2015 2.10a Continued
Conti’d Cont’d Added:
- isec_apbenable
- isec_apbwrite
- isec_apbwdata
- osec_apbrdata
- osec_apbready
■ Registers/Register bits for HDCP 2.2 integration:
- Bits 6 and 7 of Configuration Identification Register 1 (0x0005)
- jtag_phy_config
- jtag_phy_tap_tck
- jtag_phy_tap_in
- jtag_phy_tap_out
- jtag_phy_addr
- aud_spdif2 (0x3304) to enable valid channels (3:0) with 0x01 as default value
- Bit 7 of Main Controller Synchronous Clock Domain Disable Register (0x4001)
- Main Controller Status Register (0x4010)
- Bits 4 and 5 to Main Controller HDCP Bypass Control Register (0x4003), which allows
you to choose how video data is to be transmitted (unencrypted, encrypted with HDCP
1.4., Encrypted with HDCP 2.2)
- SFR Clock Base Time Register Low (0x4018)
- SFR Clock Base Time Register High (0x4019)
Updated:
■ ispdifdata input description
■ AUD_CONF1 register bits 7:5 (now reserved and read as zero)
■ Appendix A, “Internal Parameter Descriptions” (removed APB row)
Removed:
■ Deprecated non-standard I2S modes (Updated “I2S interface” on page 64)
■ Appendix A, “HDCP 1.4 Application Note” – this appendix is now in the DesignWare Cores
HDMI Tx Controller User Guide.

(Continued)
June 2014 2.01a Added:
■ HDMI 2.0 PHY interface
■ External HDCP 2.2 interface
- HDCP Version parameter
- HDCP 2.2 Encryption Engine Interface Signals
- HDCP 2.2 Encryption Engine Registers
■ Multistream Audio
■ HDMI 2.0 audio sample frequencies
■ NTSC VBI InfoFrame Packets
■ CSC support for input pixel repeated video modes
■ Registers:
- ih_fc_stat0.MAS[3]
- ih_fc_stat0.NVB[4]
- ih_fc_stat1.AMP[2]
- ih_mute_fc_stat0.NVB[3]
- ih_mute_fc_stat0.MAS[4]
- ih_mute_fc_stat1.AMP[2]
- fc_audsconf.aud_packet_layout[0]
- fc_datauto3.amp_auto[4]
- fc_datauto3.nvbi_auto[5]
- fc_rdrb8
- fc_rdrb9
- fc_rdrb10
- fc_rdrb11
- fc_multistream_ctrl
- fc_packet_tx_en
- fc_actspc_hdlr_cfg
- fc_invact_2d_0
- fc_invact_2d_1
- fc_amp_hb1
- fc_amp_hb2
- fc_amp_pb[28]

(Continued)
June 2014 2.01a - fc_nvbi_hb1
Continued Cont’d - fc_nvbi_hb2
- fc_nvbi_hb[27]
- hdcp22reg_ctrl
- hdcp22reg_ctrl1
- hdcp22reg_sts
- hdcp22reg_mask
- hdcp22reg_stat
- hdcp22reg_mute
Updated:
■ Table 1-1 (updated minimum and maximum frequency for cecclk
■ Table 1-2 and Table 1-3 (area for HDMI 1.x and HDMI 2.0)
■ “S/PDIF Interface”
■ Support for HBR over SDPIF parameter description
■ Appendix A.2.4, “OESS (Original Encryption Status Signaling) FSM” (corrected typo in
heading) – This appendix is now in the DWC HDMI Tx User Guide.
■ Moved interface sections from Chapter 2, “Functional Description” to Chapter 4, “Signal
Interfaces”
July 2013 2.00a Added:
■ Support for HDMI 2.0 features (DWC_HDMI_TX_20 parameter)
■ “HDMI 2.0 TMDS Scrambling Feature”
■ “HDCP Encryption Engine”
■ Registers:
- fc_scrambler_ctrl
- i2cm_read_buff0 to i2cm_read_buff7
- i2cm_scdc_read_update
- i2cm_scdc_update0
- i2cm_scdc_update1
■ Appendix A, “Internal Parameter Descriptions” (these are internal parameters referenced in
parameter, signal, and register descriptions)
Updated:
■ “Standards Compliance”
■ “Unsupported Features and Exceptions”
■ “HDMI Operational Model Overview”
■ “Features”
■ “Speed and Clock Requirements”
■ “Area”
■ Table 2-1
■ Figure 2-5
■ Figure 2-11(no longer in databook)
■ Figure 2-8

(Continued)
July 2013 2.00a ■ “Generic Parallel Audio (GPA) Interface”
Continued Cont’d ■ Table 2-9
■ Table 2-13
■ “Random Number Generation Interface”
■ “E-DID/HDCP/SCDC I2C E-DDC Interface”
■ “E-DDC Interface Signals”
■ Registers:
- config1_id
- ih_i2cm_stat0
- ih_mute_i2cm_stat0
- fc_avivid
- fc_aviconf0
- fc_exctrlspac
- ahb_dma_buffmask
- csc_coef_a1_msb, csc_coef_a1_lsb (added note)
- csc_coef_c4_msb, csc_coef_c4_lsb (corrected naming)
- i2cm_operation
- i2cm_int
- i2cm_ctlint
April 2013 1.40a This databook update is related to Star 9000612806.
Added:
■ Registers:
- hdcpreg_rmctl
Updated:
■ Table 1-2
■ Memory map table

(Continued)
February 2013 1.40a Added:
■ “Start-Stop, Auto-Start Mechanism”
■ “PCUV Insertion”
■ Software AHB audio DMA bus hreset internal control
■ Interruption decoding assistance register
■ Runtime ACR value change (N/CTS)
■ FIFO underrun/overrun status signalling
■ FPGA prototyping support
■ Support for software programmable encrypted DPK embedded storage
■ Support for HDMI-MHL TX PHY
■ “HDMI-MHL TX PHY Interface Signals”
■ Parameters:
- HDMITX_FPGA_SYNTHESIS
- FPGA_INTERNAL_AV_GENERATOR
- HDMITX_FPGA_HDCP_MEM
- DWC_HDMI_HDCP_DPK_ROMLESS
■ Registers:
- ih_decode
- aud_int1
- aud_spdifint1
- ahb_dma_status
- ahb_dma_mask1
- ahb_dma_straddr_set1_0 to ahb_dma_straddr_set1_3
- ahb_dma_stpaddr_set1_0 to ahb_dma_stpaddr_set1_3
- ahb_dma_conf2
- mc_swrstzreq_2
- hdcpreg_rmsts
- hdcpreg_seed0
- hdcpreg_seed1
- hdcpreg_dpk0
- hdcpreg_dpk1
- hdcpreg_dpk2
- hdcpreg_dpk3
- hdcpreg_dpk4
- hdcpreg_dpk5
- hdcpreg_dpk6
Updated:
■ Table 1-1 (i2sclk, ipixelclk)
■ Table 1-2
■ Figure 2-8
■ Figure 2-9
■ Figure 2-20

(Continued)
February 2013 1.40a ■ Signals
Cont’d Cont’d - Dependency descriptions for “HDCP 1.4 Encryption Engine Interface Signals”
■ Registers
- Added bit fields to the following registers:
ih_as_stat0.fifo_overrun (bit 3)
ih_ahbdmaaud_stat0.fifo_underrun (bit 7) and fifo_overrun (bit 6)
ih_mute_as_stat0.fifo_overrun (bit 3)
ih_mute_ahbdmaaud_stat0.fifo_underrun (bit 7) and fifo_overrun (bit 6)
aud_n3.ncts_atomic_write (bit 7)
ahb_dma_conf0.insert_pcuv (bit 6) and autostart_enable (bit 5)
gp_mask.fifo_overrun_mask (bit 4)
ahb_dma_buffmask.fifo_overrun_mask (bit 4)
- Updated bit descriptions for the following registers:
fc_aviconf3, fc_aviconf0
a_hdcpcfg1[2]
config2_id
“HDMI Source PHY Registers” (“Dependencies”)
“I2C Master PHY Registers” (“Dependencies”)
- Renamed the following registers
ahb_dma_straddr0 – ahb_dma_straddr3 to ahb_dma_straddr_set0_0 to
ahb_dma_straddr_set0_3
ahb_dma_stpaddr0 – ahb_dma_stpaddr3 to ahb_dma_stpaddr_set0_0 to
ahb_dma_stpaddr_set0_3
mc_clkdis (bit 1, tmdsclk_disable description)
mc_swrstzreq (bit 1, tmdsswrst_req description)
- Changed access for:
ih_mute* registers

(Continued)
May 2012 1.32a Added:
■ Hardware configuration parameters
- PHY_EXTERNAL
- HBR_ON_SPDIF
■ Note to “CEC Hardware Engine”
■ New bit field, insert_pucv [1], to gp_conf2 register
■ “I2C Interface for PHY Configuration”
Modified:
■ “DWC_hdmi_tx Clock Frequency”
■ Table 2-3 on page 63 (Supported Audio Formats)
■ “I2S interface”
■ “ispdifclk Input Clock Requirements”
■ Added note for Table 2-6 and Table 2-7
■ “DMA Engine”
■ “Audio FIFO”
■ “R Value Verification Method”
■ “Receiver or Repeater”
■ “I2C Clock Configuration” (formerly called “SFR_CLK Frequency Configuration”)
■ AMBA APB 3.0 Slave Interface
■ “Parameter Descriptions”
Signals
■ General updates to the whole Signals chapter (formatting and fixing typos)
■ idpkack
■ Added note to odpkclk
Registers
■ Updated names of all registers in “Register Descriptions” (from uppercase to lower case)
■ Description of fc_audiconf3 Registers
■ video_mapping bit description for TX_INVID0 register
■ Description of aud_inputclkfs
Removed:
■ Hardware configuration parameters
- CONFIG_IF
- SNPS_FASTSIM_HDMI_PHY
- Interface hardware configuration parameters:
Audio – TRIPLEIF and HBRIF
Configuration – SFR, AHB, OCP, I2C
■ “FIFO Occupancy/FIFO Almost Empty Flags” in “Audio FIFO” (outdated information)

(Continued)
June 2011 1.31a Modified
■ “Interfaces”
■ “Features”
■ “Area”
■ “Audio Interfaces”
■ “Supported Audio Formats”
■ AMBA APB 3.0 Slave Interface
■ “Generic Parallel Audio (GPA) Interface”
■ “AHB Audio DMA Interface”
■ “Frame Composer”
■ “Random Number Generation Interface”
■ “SFR Direct Interface”
■ External PHY changes in “Interfaces Parameters”
■ Signals:
- “E-DDC Interface Signals”
- ointerruptwakeup
- isfrclk
■ Registers:
- ih_as_stat0
- tx_invid0
- ahb_dma_conf0
- ahb_dma_start
- ahb_dma_stop
- ahb_dma_thrsld
- ahb_dma_bstaddr0 to ahb_dma_bstaddr3
- ahb_dma_mblength0 to ahb_dma_mblength1
- ahb_dma_int (obsolete register)
- ahb_dma_mask
- AHB_DMA_POL (deprecated register)
- ahb_dma_conf1
- a_hdcpcfg0
- a_hdcpcfg1
- config3_id
- fc_inhactiv1
- fc_inhblank1
- fc_invactiv1
- fc_invblank
- fc_hsyncindelay1
- fc_hsyncinwidth1
- fc_vsyncinwidth
- fc_gcp

(Continued)
June 2011 1.31a - mc_swrstzreq
Cont’d Cont’d - mc_phyrstz
■ Attention point added after Parameter descriptions in “Parameter Descriptions”
Added:
■ “I2C Interface for PHY Configuration”
■ Registers:
- mc_flowctrl
- mc_lockonclock_2
- i2cm_sda_hold
- i2cm_phy_sda_hold
■ Signals:
- “HDMI Tx External PHY Signals”
February 2011 1.30a Added:
■ “HBR and NL-PCM Support for I2S Interface”
■ Parameter “Interfaces Parameters”
Modified:
■ “Unsupported Features and Exceptions”
■ “Memory Requirements”
■ “HBR Parallel Audio Interface”
■ Signals
- odmahburst in “Interfaces Parameters”
- ihbrclk in “HBR Audio Interface”
■ Registers:
- tx_invid0
- fc_audiconf0 – fc_audiconf3
- gp_mask
- gp_mask
- ahb_dma_start
- ahb_dma_straddr_set0_0 to ahb_dma_straddr_set0_3
- ahb_dma_bstaddr0 to ahb_dma_bstaddr3
- AHB_DMA_POL (deprecated register)
- ahb_dma_buffmask
- “MainController Registers”

(Continued)
November 2010 1.30a Added:
■ 56-Bit HDCP DPK Memory Interface under “KEY ROM DEV – Device Private Keys ROM”
■ Parameter HTX_SPDIFBYPDRU to “Interfaces Parameters”
■ Value After Reset (If applicable) for DMA signals in the chapter “Signal Interfaces”
■ “AHB Audio DMA Input Interface Signals”
■ Five new Audio DMA Registers to “AudioDMA Registers”
■ Register IH_AHBDMAAUD_STAT0 to “Interrupt Registers”
■ 10 new sticky bit mute control registers to “Interrupt Registers”
■ Register aud_conf2
■ HDCP BKSV Registers
■ HDCP AN Registers
Modified:
■ “ispdifclk Input Clock Requirements” on page 66 for STAR 9000404679
■ HDCP Encryption Engine “Memory Requirements”
■ AHB DMA Audio interface signal names in “Audio Input Interface Signals”
■ Register ahb_dma_conf0
■ Parameter AUDIO_IF in “Interfaces Parameters”
July 2010 1.20a Updated Chapter 6, “Register Descriptions”. The following registers have changed for the
DWC_hdmi_tx when it has been configured to support HDMI 1.4 specification features.This
update removes any limitations on 3D video mode support.
Modified:
■ fc_inhblank1
■ fc_inhactiv1
■ fc_hsyncindelay1
■ fc_hsyncinwidth1
Added:
■ “Generic Parallel Audio (GPA) Interface”

(Continued)
June 2010 1.20a Continued
Cont’d ■ Information to signals description tables to capture the following:
- Active state
- Registered inputs/outputs
- Synchronous to: (clk)
- External Input Delay
- Dependencies
■ “Generic Parallel Audio (GPA) Interface Signals”
■ config3_id register
■ Generic Parallel Audio Interface Registers
Modified
■ “KEY ROM DEV – Device Private Keys ROM”
■ “HDCP 1.4 Encryption Engine Interface Signals” (to include new 8-bit memory interface
signals)
April 2010 1.10a Updated “Register Descriptions” chapter. Extensive changes made throughout. The following
register descriptions have changed:
■ vp_conf
■ fc_inhactiv0/fc_inhactiv1
■ fc_inhblank0/fc_inhblank1
■ fc_hsyncindelay1 – fixed typo in register name
■ fc_aviconf0–fc_aviconf2
■ fc_audiconf0 – fc_audiconf3
■ fc_audschnls0 to fc_audschnls8
■ fc_datauto0 through fc_datauto3
■ fc_rdrb0 through fc_rdrb7
■ fc_gmd_stat
■ fc_gmd_hb
■ fc_vsdpayload0 – fc_vsdpayload23
■ fc_spdproductname0 – fc_spdproductname15
■ i2cm_div

(Continued)
March 2010 1.10a Updated:
■ “Interfaces” on page 39
■ “Features” on page 40
■ “Input Data Mappings” on page 48
■ “Video Modes” on page 50
■ “Parameter Descriptions” on page 115
■ “Register Memory Map”8 and “Register and Field Descriptions”
Added:
■ Contents of the High Bit Rate (HBR) Audio Interface in HDMI Transmitter Controller
Application Note in “HBR Parallel Audio Interface”
■ Contents of the High-Bandwidth Digital Content Protection (HDCP) Application Note in
“HDCP Encryption Engine” on page 90 and in Appendix A on page 515 (this appendix is
now in the DWC HDMI Tx Controller User Guide)
■ “OCP Slave Interface Transfer Commands”
■ Hardware configuration parameters: (Table 3-2 on page 117)
- DWC_HDMI_TX_14
- HDMI_HEAC_PHY_EN
- DWC_HDMI_TX_INTPREPEN
■ “HDMI 3-D TX PHY (PHY GEN 2) Interface Signals”
■ “HDMI HEAC PHY Interface Signals”
■ Registers:
- config0_id, config1_id, config2_id
- ih_i2cmphy_stat0
- I2C Master PHY Registers
- i2cm_ss_scl_hcnt_1_addr through i2cm_fs_scl_lcnt_0_addr
Removed:
■ DDR video mode support
■ Audio Sampler HBR Mode 1 Operation
■ Moved chapters to new User Guide:
- “Building and Verifying Your HDMI Tx”
- “Verification Environment”
December 2009 1.01a ■ Converted to Synopsys templates
Added:
■ “Building and Verifying Your HDMI Tx” (now in User Guide)
■ “Verification Environment” (now in User Guide)
Updated:
■ “Product Overview” on page 33
September 2009 1.01a For changes in this release, refer to the DWC HDMI 1.3c Transmitter Controller Release Notes.
February 4, 2008 1.00a Initial release


Preface
This databook describes the DesignWare Cores HDMI Transmitter Controller, which, along with the
Synopsys DWC HDMI TX PHY, is a part of a complete HDMI Tx interface solution.
Throughout this databook, HDMI Tx is used to reference the DWC_hdmi_tx controller.
Databook Organization
The chapters of this databook are organized as follows:
■ Chapter 1, “Product Overview” provides an introduction to the HDMI Tx, including a block
diagram, supported features, deliverables, supported standards, and so.
■ Chapter 2, “Functional Description” details the functions of the HDMI Tx.
■ Chapter 3, “Parameter Descriptions” describes the hardware configuration parameters.
■ Chapter 4, “Signal Interfaces” provides descriptions of the HDMI Tx’s inputs/outputs.
■ Chapter 6, “Register Descriptions” provides the memory map of the HDMI Tx and descriptions of
the programmable software registers.
■ Appendix A, “Internal Parameter Descriptions” provides a description of the internal parameters
that might be indirectly referenced in expressions in the Signals, Parameters, or Registers chapters.
Related Documentation
Refer to the following documentation:
■ coreConsultant User’s Guide
■ coreAssembler User’s Guide
Web Resources
The following web links are various Synopsys online resources you may find useful:
■ DesignWare IP product information: http://www.designware.com
■ Your custom DesignWare IP page: http://www.mydesignware.com
■ Documentation through SolvNet: http://solvnet.synopsys.com (Solvnet ID required)
■ Synopsys Common Licensing (SCL): http://www.synopsys.com/keys

Preface HDMI Transmitter Controller Databook
Customer Support
To obtain support for your product, choose one of the following:
■ First, prepare the following debug information, if applicable:
❑ For environment setup problems or failures with configuration, simulation, or synthesis that
occur within coreConsultant or coreAssembler, use the following menu entry:
File > Build Debug Tar-file
Check all the boxes in the dialog box that apply to your issue. This menu entry gathers all the
Synopsys product data needed to begin debugging an issue and writes it to the file
core tool startup directory/debug.tar.gz.
❑ For simulation issues outside of coreConsultant or coreAssembler:
■ Create a waveforms file (such as VPD or VCD)
■ Identify the hierarchy path to the DesignWare instance
■ Identify the timestamp of any signals or locations in the waveforms that are not understood
■ Then, contact Support Center, with a description of your question and supplying the above
information, using one of the following methods:
❑ For fastest response, use the SolvNet website. If you fill in your information as explained below,
your issue is automatically routed to a support engineer who is experienced with your product.
The Sub Product entry is critical for correct routing.
Go to http://solvnet.synopsys.com/support/open_case.action.
Provide the requested information, including:
■ Product: DesignWare Cores
■ Sub Product: HDMI Controller
■ Version: 2.12a
■ Problem Type:
■ Priority:
■ Title: Provide a short summary of the issue or list the error message you have encountered.
■ Description: For simulation issues, include the timestamp of any signals or locations in
waveforms that are not understood
After creating the case, attach any debug files you created in the previous step.
❑ Or, send an e-mail message to [email protected] (your e-mail will be queued and
then, on a first-come, first-served basis, manually routed to the correct support engineer):
■ Include the Product name, Sub Product name, and Tool Version number in your e-mail (as
identified above) so it can be routed correctly.
■ For simulation issues, include the timestamp of any signals or locations in waveforms that are
not understood
■ Attach any debug files you created in the previous step.
❑ Or, telephone your local support center:
■ North America:
Call 1-800-245-8005 from 7 AM to 5:30 PM Pacific time, Monday through Friday.
■ All other countries:
http://www.synopsys.com/Support/GlobalSupportCenters

1
Product Overview
This chapter includes the following topics:

■ “General Product Description” on page 34
■ “Interfaces” on page 39
■ “Features” on page 40
■ “Speed and Clock Requirements” on page 42
■ “Area” on page 43

Product Overview HDMI Transmitter Controller Databook
1.1 General Product Description

The DesignWare Cores HDMI Transmitter Controller includes the DWC_hdmi_tx controller and its
verification environment. Synopsys also provides the coreConsultant tool for automated configuration,
simulation, and synthesis of the DWC_hdmi_tx controller.
The HDMI Tx Controller can be configured with or without a High-bandwidth Digital Content Protection
(HDCP) system. If you want HDCP enabled, you need an additional license. The DWC_hdmi_tx digital
controller is designed to interface with the Synopsys HDMI Transmitter Physical Layer (DWC HDMI Tx
PHY), enabling the integration of a complete HDMI Transmitter interface.
Figure 1-2 shows the DWC_hdmi_tx in an example system on chip design.
Figure 1-1 DWC_hdmi_tx in System on Chip Example
System Memory
System
CPU
Drivers
System Bus
MIPI DigRF PCIe USB Link HDMI

Controller Controller Controller Controller Controller 10/100
Ethernet
Controller
MIPI DigRF PCIe USB HDMI
PHY PHY PHY PHY PHY
Ethernet
PHY
RF Chip
Chip-to-Chip
Communications Data Multimedia Network
Sensor Module-to-Module Connectivity Communication
Interface Communications Connectivity

HDMI Transmitter Controller Databook Product Overview
1.1.1 Applications
Typical applications for an HDMI device built with the DWC_hdmi_tx controller are:
■ Blu-ray and HD-DVD player
■ A/V Receiver
■ Set-Top Box
■ Digital Still Camera
■ HDTV Camcorder
■ Portable Media Player
■ Video Game Console
■ Personal Computer
■ Mobile Phone
1.1.2 Standards Compliance

HDMI Tx conforms to the following standards:
■ HDMI 1.4b (www.hdmi.org)
■ HDMI 2.0b (www.hdmi.org)
■ HDMI CTS 1.4b (www.hdmi.org)
■ HDCP 1.4 (click here for specification)
■ AMBA® APB 3.0 Specification from ARM
AMBA is a registered trademark of ARM Limited and is used under license.
■ AMBA AHB 2.0 Specification from ARM
■ I2C Bus Specification, Version 2.1 from NXP
■ I2S Bus Specification, June 5, 1996
1.1.3 Unsupported Features and Exceptions

The following are features not supported in this version of DWC_hdmi_tx:
■ Low priority data island packets: (see Table 2-15 on page 87)
❑ One-bit audio (DSD and DST)
❑ MPEG
■ 3-D Audio Sample Packet
■ One Bit 3-D Audio Sample Packet
■ Multi-Stream One Bit Audio Sample Packet
■ Gamut profiles other than Profile 0
■ Dual-link DVI

1.1.4 HDMI Operational Model Overview

The High Definition Multimedia Interface (HDMI) is a wired digital interconnect that replaces the analog
SCART connection. HDMI is capable of transferring uncompressed video, audio, and data using a single
cable. The video pixel rates are typically from 25 MHz up to 297 MHz (4k x 2k and 3D video modes), but
HDMI can support higher rates up to 600 MHz. HDMI supports a number of audio standards, including: up
to eight IEC60958 L-PCM audio channels, IEC61937 compressed non-linear PCM (AC-3, MPEG-1/-2 Audio,
DTS®, MPEG-2/-4 AAC, ATRAC, WMA, MAT), and HBR audio formats (Dolby® True-HD and DTS-HD
Master Audio).
Additionally, HDMI has the capability of automatically setting the display format configuration (intelligent
link). Optionally, HDMI can include a content protection system called HDCP (High-bandwidth Data
Content Protection). The HDMI connections can be used to connect DVD recorders, set-top boxes, and game
consoles to flat panel televisions and an AV amplifier that can act as repeater/router.
HDMI system architecture consists of sources (transmitter) and sinks (receiver). As shown in Figure 1-2, the
HDMI cable and connectors carry four differential pairs that make up the TMDS data and clock channels.
These channels are used to carry video, audio, and auxiliary data. In addition, HDMI carries a VESA Data
Display Channel (DDC). The DDC is used for configuration and status exchange between a single source
and a single sink. The optional CEC protocol provides high-level control functions between all of the
various audiovisual products in a user’s environment.
Figure 1-2 HDMI Block Diagram

HDMI Source HDMI Sink
TMDS Channel 0 Video

Video
HDMI TMDS Channel 1 Audio

HDMI
Audio Transmitter Receiver
TMDS Channel 2
Control/Status
Control/Status
TMDS Clock Channel
EDID
Display Data Channel (DDC) ROM
CEC Line
CEC CEC
Utility Line
HEAC
CEC HEAC
CEC
detect
CEC High/Low
HPD Line

Audio, video, and auxiliary data is transmitted across the three TMDS data channels. A TMDS clock
running at 1x (24-bit true color mode), 1.25x (30-bit deep color mode), 1.5x (36-bit deep color mode), or 2x
(48-bit deep color mode), the video pixel rate is transmitted on the TMDS clock channel and used by the
receiver as a frequency reference for data recovery on the three TMDS data channels. Video data can have a
pixel size of 24, 30, 36, or 48 bits. Video at the default 24-bit color depth is carried at a TMDS clock rate equal
to the pixel clock rate. Higher color depths are carried using a correspondingly higher TMDS clock rate.
Video formats with TMDS rates below 25 MHz (such as, 13.5 MHz for 480i/NTSC) can be transmitted using
a pixel-repetition scheme. The video pixels can be encoded in either RGB, YCBCR 4:4:4, YCbCr 4:2:2, or
YCbCr 4:2:0 formats.
HDMI uses a packet structure to transmit audio and auxiliary data across the TMDS channels. To attain the
highest reliability required of audio and control data, this data is protected with a BCH error correction code
and is encoded using a special error reduction code to produce the transmitted 10-bit word.
Basic audio functionality consists of a single IEC 60958 L-PCM audio stream (two audio channels) at sample
rates of 32 kHz, 44.1 kHz, or 48 kHz, which can accommodate any normal stereo stream. Optionally, HDMI
can carry L-PCM audio at sample rates up to 192 kHz and with three to eight audio channels. HDMI can
also carry an IEC 61937 compressed (such as, surround sound) audio stream at bit rates up to 49.152 Mbps.
For bit rates above 6.144 Mbps, compressed audio streams conforming to IEC 61937 are carried using HBR
Audio Stream Packets. Each packet carries four IEC 60958 frames, which corresponds to (4x2x16 =) 128
contiguous bits of an IEC 61937 stream.
The source uses the DDC to read the sink’s Enhanced Extended Display Identification Data (E-EDID) to
obtain the sink’s configuration and/or capabilities.
The DesignWare Cores HDMI Tx Controller schedules the three periods: Video Data Period, Data Island
period, and Control period. During the Video Data Period, the active pixels of an active video line are
transmitted. During the Data Island period, audio and auxiliary data are transmitted using a series of
packets. The Control period is used when no video, audio, or auxiliary data needs to be transmitted. A
Control Period is required between any two periods that are not Control Periods. An example of each
period placement is shown in Figure 1-3 on page 38.
The optional HEAC (HDMI Ethernet and Audio Return Channel) functionality provides the capability of
transporting bi-directional Ethernet traffic and an S/PDIF Audio Return Channel (from the receiver to the
transmitter) over the HDMI cable.

Figure 1-3 TMDS Periods in 720x480p Video Frame

TMDS Periods in 720x480 Video Frame
V
e
r Data Island Period
t
I
c
a ControlPeriod
Command Period
l
Command Period
525
T
o 480
t
a A
l c
t
L i
i v Data Video Data Period
n e Island Active Video
e Period
s L
i
n
e
s
Horzontal Blanking 720 Active Pixels

858 Total Pixels

1.2 Interfaces
HDMI Tx has the following interfaces:
■ Optional HDCP 1.4 interface
❑ External ROM interface for key storage (required when the “Enable Software Programmable
Encrypted DPK Embedded Storage” option in coreConsultant is not set)
❑ External RAM interface for revocation
❑ External random number generator (optional)
■ Optional External HDCP 2.2 interface
Allows you to build your own interface or use a third-party HDCP 2.2 decryption engine
■ Video input interface
❑ RGB 4:4:4
❑ YCbCr 4:2:2
❑ YCbCr 4:4:4
❑ YCbCr 4:2:0
■ Digital audio input interface
❑ Four I2S interfaces for eight-channel audio
❑ Four S/PDIF interfaces for eight-channel audio
❑ Generic Parallel Audio
❑ AHB audio DMA
■ System interface
❑ AMBA APB
■ Scan test interface
■ Synopsys HDMI PHY with At-Speed Scan
■ HDMI Tx PHY interface
■ HDMI-MHL TX PHY interface
■ CEC interface

1.3 Features
HDMI Tx supports the following features:
■ Video formats:
❑ All CEA-861-E video formats up to 1080p at 60 Hz and 720p/1080i at 120 Hz
❑ Optional HDMI 1.4b video formats: (configuration dependent)
■ All CEA-861-E video formats up to 1080p at 120 Hz
■ HDMI 1.4b 4K x 2K video formats
■ HDMI 1.4b 3D video modes with up to 340 MHz (TMDS clock)
❑ Optional HDMI 2.0 video formats: (configuration dependent)
■ All CEA-861-F video formats
■ Dynamic Range and Mastering InfoFrame (DRM, packet header 0x87)
■ Colorimetry:
❑ 24/30/36/48-bit RGB 4:4:4
❑ 24/30/36/48-bit YCbCr 4:4:4
❑ 16/20/24-bit YCbCr 4:2:2
❑ 24/30/36/48-bit YCbCr 4:2:0
❑ xvYCC601
❑ xvYCC709
❑ Optional HDMI 1.4b colorimetry:
■ sYCC601
■ Adobe RGB
■ Adobe YCC601
■ Optional color space converter (CSC):
❑ RGB (4:4:4) to/from YCbCr (4:4:4 or 4:2:2)
■ Optional HDMI 1.4b supported Infoframes:
❑ Audio InfoFrame packet extension to support LFE playback level information
❑ AVI infoFrame packet extension to support YCC Quantization range (Limited Range, Full Range)
❑ AVI infoFrame packet extension to support Content type (Graphics, Photo, Cinema, Game)
❑ NTSC VBI infoframe packet extension to support the carriage of SCTE 127 [29] payloads
containing VBI data
■ Audio formats:
Table 2-3 on page 63 shows the supported audio formats for the DWC_hdmi_tx’s interfaces.
■ Up to 192 kHz IEC60958 audio sampling rate
For IEC61937 compressed audio
❑ HDMI 2.0b: up to 1536 kHz

❑ HDMI 1.4b: Up to 768 kHz

■ Pixel clock from 13.5 MHz up to 600 MHz
■ Option to remove pixel repetition clock (prepclk) from HDMI Tx interface for an easy integration
with third-party HDMI Tx PHYs
■ Flexible synchronous enable per clock domain to set functional power down modes
■ AMBA APB 3.0 register access
■ I2C DDC, EDID block read mode
■ SCDC I2C DDC access
■ TMDS Scrambler to enable support for 2160p@60Hz with RGB/YCbCr 4:4:4 or YCbCr 4:2:2
■ YCbCr 4:2:0 support to enable 2160p@60Hz at lower HDMI link speeds
■ Integrated CEC hardware engine
■ Advanced PHY testability
■ Synopsys and external PHY Interfaces
■ Configurable number of positive-edge-triggered flip-flops connected for data synchronization
■ Single-channel DVI 1.0 backward compatibility
All HDMI sources are compatible with all DVI-compliant sinks and all HDMI sinks are compatible
with DVI-compliant sources. All HDMI devices are compatible to the DVI 1.0 Specification, except
some rules. For more information on these rules, see the HDMI 1.4b Specification.

1.4 Speed and Clock Requirements

Table 1-1 shows the clock frequency of the DWC_hdmi_tx controller.
Table 1-1 DWC_hdmi_tx Clock Frequency
Clock Domain Minimum Frequency Maximum Frequency
ispdifclk 4.096 MHz 24.576 MHz (128x192k)

(HTX_SPDIFBYPDRU enabled and (128x32k)
HBR_ON_SPDIF disabled)
ispdifclka 4.096 MHz HDMI 1.4b: 98.304 MHz (128x768k)

(HTX_SPDIFBYPDRU enabled and (128x32k) HDMI 2.0b: 196.608 MHz (128x1536kHz)
HBR_ON_SPDIF enabled)
ispdifclk 16.384 MHz 98.304 MHz (4x128x192k)

(HTX_SPDIFBYPDRU disabled and (4x128x32k)
HBR_ON_SPDIF disabled)
ii2sclka 2.048 MHz 98.304 MHz
igpaclkb 4.096 MHz -c
ipixelclk 13.5 MHzd 340 MHze
isfrclk 18 MHz 27 MHz
iapbclk 27 MHz -c
icecclk 32.709 kHz 32.776 kHz
idmahclk 27 MHz -c
a. ii2sclk and ispdifclk clock accuracy requirements need to adhere to the HDMI specification requirements for
Audio Clock Regeneration (ACR). For further assistance, contact Synopsys Customer Support.
b. For igpaclk minimum clock frequency, the clock accuracy requirements must adhere to the HDMI specification
requirements for Audio Clock Regeneration (ACR). For further assistance, contact Synopsys Customer Support.
c. The maximum frequency limit is only imposed by synthesis and process technology.
d. PHY dependent value. The 13.5 MHz lower boundary is for a TX controller and a Synopsys HDMI Tx PHY with internal
pixel repetition function.
e. In HDMI 2.0b, the maximum frequency is 600 MHz.

1.5 Area
Table 1-2 provides area information for an HDMI 1.x configuration, which targets a TSMC 28-nm HPM SVT
process at 340 MHz using Design Compiler Reference Methodology without DFT insertion.
Table 1-2 HDMI Tx Area for HDMI 1.x
Configuration Interface Area (gates)
Base GP Audio 119 K
I2S 9K
S/PDIF without DRU 11 K
S/PDIF with DRU 13 K
S/PDIF with HBR support 4K
I2S and S/PDIF (DOUBLE) 22 K

Audio
GP Audio and I2S (GDOUBLE) 16 K
AHB audio DMA, FIFO depth=128 32 K
CEC 6K
CSC 42 K
Pixel Repetition 24 K
HDCP SHA-1 by software 21 K
HDCP SHA-1 by DWC_hdmi_tx 35 K
HDCP 1.4 with 8-bit memory interface 22 K
HDCP 1.4 with ROMless DPK storage 39 K
HDCP 1.4 with support for HDCP 2.2 EXT 41 K

Table 1-3 provides area information for an HDMI 2.0 configuration, which targets a TSMC 28-nm HPM SVT
process at 600 MHz using Design Compiler Reference Methodology without DFT insertion.
Table 1-3 HDMI Tx Area for HDMI 2.0
Configuration Interface Area (gates)
Base with HDMI 2.0 GP Audio 152 K
I2S 9K
S/PDIF withou DRU 11 K
S/PDIF with DRU 13 K
S/PDIF with HBR support 4K
DOUBLE 22 K
Audio with HDMI 2.0
GDOUBLE 17 K
CEC 6K
CSC 45 K
Pixel Repetition 23 K
HDCP SHA-1 by software 21 K
HDCP SHA-1 by DWC_hdmi_tx 35 K
HDCP 1.4 with 8-bit memory interface 22 K
HDCP 1.4 with ROMless DPK storage 39 K
HDCP 1.4 with support for HDCP 2.2 EXT 40 K

2
Functional Description
This chapter describes the functional architecture of the DWC HDMI Tx controller.
The topics described are:
■ “DWC_hdmi_tx Functional Overview” on page 46
■ “Video Pixel Sampler” on page 47HDMI 2.0b
■ “Supported Video Modes” on page 50
■ “Video Packetizer” on page 61
■ “HDMI 2.0 TMDS Scrambling Feature” on page 61
■ “Color Space Conversion” on page 62
■ “Audio Interfaces” on page 63
■ “Frame Composer” on page 87
■ “HDCP Encryption Engine” on page 89
■ “AMBA APB 3.0 Slave Interface” on page 105
■ “HDMI Tx PHY Support” on page 105
■ “E-DID/HDCP/SCDC I2C E-DDC Interface” on page 106
■ “CEC Hardware Engine” on page 111

Functional Description HDMI Transmitter Controller Databook
2.1 DWC_hdmi_tx Functional Overview

The DWC_hdmi_tx provides a variety of standard audio, video, and system interfaces. It includes an
optional high-bandwidth data content protection (HDCP) encryption engine for HDMI receiver
authentication, revocation, and data encryption. The HDCP feature requires an additional DesignWare
Cores license.
Figure 2-1 illustrates the block diagram of the DWC HDMI Tx solution.
Figure 2-1 DWC_hdmi_tx Controller Block Diagram
DWC_hdmi_tx
References
Color Space Video
Video Sampler
Video (page 47) Converter Packetizer
Interface (page 61) (page 61) TMDSCLKP
PLL
TMDSCLKN
I2S (page 64)
S/PDIF TMDSDATAP[0]
PLL
Audio (page 66) Audio Frame HDCP TMDSDATAN[0]
Interface GP Audio Packetizer Composer Encryptor
(page 67) (page 63) (page 87) (page 89) TMDSDATAP[1]
DMA (page 72) PLL
(page 72) TMDSDATAN[1]
Audio Sampler TMDSDATAP[2]

PLL
TMDSDATAN[2]
I2C
Register Master
(page 106) HDMI Tx PHY
AMBA APB Bank
Control (page 105) I2C/DDC
Interface DDC_SCL
Master
(page 106) DDC_SDA
Configuration Main Control
& CEC
Control Logic CEC
Controller External
(page 111)
Memory
Interface HDCP Keys
(page 94)
= additional license required for this feature = configuration dependent
The optional HDCP encryption engine is responsible for HDMI receiver authentication, revocation, and
data encryption. It has an exclusive read access to the external HDCP encryption Device Private Keys ROM,
making it impossible to access the confidential keys of the register bank and system interface.
You can configure the controller to manually override several automatic actions like the N/CTS calculation
or the controller’s power management state. Synchronous enables per clock domain give management
modes the ability to reduce the controller’s power consumption. For example, you can configure
DWC_hdmi_tx without HDCP encryption, which puts the HDCP engine in idle operation mode.
The input video stream can be either RGB 4:4:4, YCbCr 4:2:2, YCbCr 4:4:4, or YCbCr 4:2:0 in single data rate
(SDR) bus formats as described in Table 2-1 on page 48. The video mode’s timing format must follow the
CEA-861-E specification. An embedded color space conversion allows the pixel color format to be converted
on the HDMI source side to match the best with the HDMI sink capabilities.

HDMI Transmitter Controller Databook Functional Description
The input audio stream can be provided through a standard I2S format interface, S/PDIF, an AHB DMA
master, or a Generic Parallel interface (for all audio types: L-PCM, NL-PCM, and HBR), as described in the
“Audio Interfaces” on page 63.
The system interface (the interface that connects to the processor bus) is an AMBA APB.
Finally, the controller can output video in full HD with up to 48-bit color mode and inserts high fidelity
audio up to eight-channels over low resolution video formats by performing automatic pixel repetition over
the input video stream.
2.2 Video Pixel Sampler

The Video pixel sampler block is responsible for the video data synchronization, according to the video data
input mapping defined by the Color Depth (Deep Color) and format configuration. Optionally, for YCbCr
4:2:2 format, data mapping can be performed to conform to ITU.601 and ITU.656 standards but without the
support of embedded synchronizers.
Table 2-1 on page 48 provides input data mappings.
The video pixel sampler registers base address is 0x0200. For more detailed information on this register,
refer to Section “VideoSampler Registers” on page 219.

Table 2-1 Input Data Mappings

Input Format idata[47:0]
Color Color Sample M. 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Space Depth Code
8-bit 1 R[7:0] G[7:0] B[7:0]
10-bit 3 R[9:0] G[9:0] B[9:0]

RGB 4:4:4
12-bit 5 R[11:0] G[11:0] B[11:0]
16-bit 7 R[15:0] G[15:0] B[15:0]
8-bit 9 Cb[7:0] Y[7:0] Cr[7:0]
10-bit 11 Cb[9:0] Y[9:0] Cr[9:0]

YCrCb 4:4:4
12-bit 13 Cb[11:0] Y[11:0] Cr[11:0]
16-bit 15 Cb[15:0] Y[15:0] Cr[15:0]

Cb(n)[7:0] Y(n)[7:0]
8-bit 22
Cr(n)[7:0] Y(n+1)[7:0]
Cb(n)[9:0] Y(n)[9:0]
Video Input Mappings
YCrCb 4:2:2 10-bit 20

Cr(n)[9:0] Y(n+1)[9:0]
12-bit 18 Cb(n)[11:0] Y(n)[11:0]
Cr(n)[11:0] Y(n+1)[11:0]
8-bit Cb(L)(n)[7:0] Y(L)(n)[7:0] Y(L)(n+1)[7:0]
9
Cr(L+1)(n)[7:0] Y(L+1)(n)[7:0] Y(L+1)(n+1)[7:0]
10-bit Cb(L)(n)[9:0] Y(L)(n)[9:0] Y(L)(n+1)[9:0]
11
Cr(L+1)(n)[9:0] Y(L+1)(n)[9:0] Y(L+1)(n+1)[9:0]
YCrCb 4:2:0
Cb(L)(n)[11:0] Y(L)(n)[11:0] Y(L)(n+1)[11:0]
12-bit 13
Cr(L+1)(n)[11:0] Y(L+1)(n)[11:0] Y(L+1)(n+1)[11:0]
Cb(L)(n)[15:0] Y(L)(n)[15:0] Y(L)(n+1)[15:0]
16-bit 15
Cr(L+1)(n)[15:0] Y(L+1)(n)[15:0] Y(L+1)(n+1)[15:0]
8-bit 23 Y[7:0] Cb[7:0] Cr[7:0]
10-bit 24 Y[9:0] Cb[9:0] Cr[9:0]

YCrCb 4:4:4
12-bit 25 Y[11:0] Cb[11:0] Cr[11:0]
16-bit 26 Y[15:0] Cb[15:0] Cr[15:0]

Y(n)[11:0] Cb(n)[11:0] Cr(n)[11:0]
YCrCb 4:2:2 12-bit 27
Y(n+1)[11:0] Cb(n)[11:0] Cr(n)[11:0]
Y(L)(n)[7:0] Y(L)(n+1)[7:0] Cb(L)(n)[7:0]
8-bit 28
Y(L+1)(n)[7:0] Y(L+1)(n+1)[7:0] Cr(L+1)(n)[7:0]
Y(L)(n)[9:0] Y(L)(n+1)[9:0] Cb(L)(n)[9:0]
10-bit 29
Y(L+1)(n)[9:0] Y(L+1)(n+1)[9:0] Cr(L+1)(n)[9:0]
YCrCb 4:2:0
12-bit Y(L)(n)[11:0] Y(L)(n+1)[11:0] Cb(L)(n)[11:0]
30
Y(L+1)(n)[11:0] Y(L+1)(n+1)[11:0] Cr(L+1)(n)[11:0]
16-bit Y(L)(n)[15:0] Y(L)(n+1)[15:0] Cb(L)(n)[15:0]
31
Y(L+1)(n)[15:0] Y(L+1)(n+1)[15:0] Cr(L+1)(n)[15:0]

For each video timing format, there is a specific timing parameter defined in the CEA-861-F specification.
The following timing diagram is an example for the video mode format 1 (640x480p @ 59.94/60 Hz):
Data Enable = idataen, HSYNC = ihsync, VSYNC = ivsync.
Figure 2-2 Timing Parameters for 640x480p @ 59.94/60 Hz
800 Total Horizontal Clocks per line
Data
Enable
160 640 Clocks for Active Video
96
16 48 clocks
HSYNC
Progressive Frame: 45 Vertical Blanking Lines 480 Active Vertical Lines
Data
Enable
800 clocks 144
16
HSYNC
515 515 517 24 525 1 2 3 4 5 6 7 35 36 515 516 525
VSYNC
For a complete list of timing parameters and diagrams, refer to the CEA-861-E specification.
The SDR video sample input format is illustrated in Figure 2-3.
Figure 2-3 Video Sample Timing Interface for RGB, YCbCr SDR Format
idataen
ipclk
idata Data N Data N+1

2.3 Supported Video Modes

Table 2-2 shows examples of the supported video modes.
Table 2-2 Supported Video Modes
2D 3D Structure
L+depth+gr
Frame Side-by- aphics+gra Side-by- Top-and-
Packing Field Alt. Line Alt. Side (full) L+depth phics- Side (Half) Bottom
Pixel Rate Pixel Rate Pixel Rate Pixel Rate Pixel Rate depth Pixel Pixel Rate Pixel Rate
HxV (Mp/s) (Mp/s) (Mp/s) (Mp/s) (Mp/s) Rate (Mp/s) (Mp/s) (Mp/s)
Active
Resolution Refresh 2D Pixel Interlaced
Video Mode Mode (pixel) Rate (Hz) Rate (Mp/s) ALL CEA Only Progr. Only ALL CEA Progr. Only Progr. Only ALL CEA ALL CEA
Primary HDMI Video Format Timings (CEA-861-F)
1 640x480p 59.94 25.175 50.35 50.35 50.35 50.35 100.7 25.175 25.175
640 x 480
1 (EDTV) 60 25.2 50.4 50.4 50.4 50.4 100.8 25.2 25.2
19 50 74.25 148.5 148.5 148.5 148.5 297 74.25 74.25
1280x720p
4 1280 x 720 60 74.25 148.5 148.5 148.5 148.5 297 74.25 74.25
(HDTV)
4 59.94 74.176 148.352 148.352 148.352 148.352 296.704 74.176 74.176
20 25 74.25 148.5 148.5 148.5 74.25 74.25
1920x1080i
5 1920 x 1080 30 74.25 148.5 148.5 148.5 74.25 74.25
(HDTV)
5 29.97 74.176 148.352 148.352 148.352 74.176 74.176
2 59.94 27 54 54 54 54 108 27 27
2 720x480p 60 27.027 54.054 54.054 54.054 54.054 108.108 27.027 27.027
720 x 480
3 (EDTV) 59.94 27 54 54 54 54 108 27 27
3 60 27.027 54.054 54.054 54.054 54.054 108.108 27.027 27.027
6 29.97 27 54 54 54 27 27
6 720(1440)x4 30 27.027 54.054 54.054 54.054 27.027 27.027
1440 x 480
7 80i (SDTV) 29.97 27 54 54 54 27 27
7 30 27.027 54.054 54.054 54.054 27.027 27.027
17 720x576p 50 27 54 54 54 54 108 27 27
720 x 576
18 (EDTV) 50 27 54 54 54 54 108 27 27
21 720(1440)x5 25 27 54 54 54 27 27
1440 x 576
22 76i (SDTV) 25 27 54 54 54 27 27

Table 2-2 Supported Video Modes (Continued)
2D 3D Structure
L+depth+gr
Active
Secondary HDMI video format timings (CEA-861-F)
41 100 148.5 297 297 297 297 594 148.5 148.5
47 120 148.5 297 297 297 297 594 148.5 148.5
47 119.88 148.352 296.704 296.704 296.704 296.704 593.408 148.352 148.352
60 24 59.4 118.8 118.8 118.8 118.8 237.6 59.4 59.4
60 23.976 59.341 118.682 118.682 118.682 118.682 237.364 59.341 59.341
61 25 74.25 148.5 148.5 148.5 148.5 297 74.25 74.25
62 30 74.25 148.5 148.5 148.5 148.5 297 74.25 74.25
62 29.97 74.176 148.352 148.352 148.352 148.352 296.704 74.176 74.176
65 24 59.4 118.8 118.8 118.8 118.8 237.6 59.4 59.4
1280x720p
65 1280 x 720 23.976 59.341 118.682 118.682 118.682 118.682 237.364 59.341 59.341
(HDTV)
66 25 74.25 148.5 148.5 148.5 148.5 297 74.25 74.25
67 30 74.25 148.5 148.5 148.5 148.5 297 74.25 74.25
67 29.97 74.176 148.352 148.352 148.352 148.352 296.704 74.176 74.176
68 50 74.25 148.5 148.5 148.5 148.5 297 74.25 74.25
69 60 74.25 148.5 148.5 148.5 148.5 297 74.25 74.25
69 59.94 74.176 148.352 148.352 148.352 148.352 296.704 74.176 74.176
70 100 148.5 297 297 297 297 594 148.5 148.5
71 120 148.5 297 297 297 297 594 148.5 148.5
71 119.88 148.352 296.704 296.704 296.704 296.704 593.408 148.352 148.352

2D 3D Structure
L+depth+gr
Active
8 60.054 27 54 54 54 54 108 27 27
8 59.826 27 54 54 54 54 108 27 27
8 60.115 27.027 54.054 54.054 54.054 54.054 108.108 27.027 27.027
8 59.886 27.027 54.054 54.054 54.054 54.054 108.108 27.027 27.027
1440x240p 1440 x 240
9 60.054 27 54 54 54 54 108 27 27
9 59.826 27 54 54 54 54 108 27 27
9 60.115 27.027 54.054 54.054 54.054 54.054 108.108 27.027 27.027
9 59.886 27.027 54.054 54.054 54.054 54.054 108.108 27.027 27.027
23 50.08 27 54 54 54 54 108 27 27
23 49.92 27 54 54 54 54 108 27 27
23 49.761 27 54 54 54 54 108 27 27
1440x288p 1440 x 288
24 50.08 27 54 54 54 54 108 27 27
24 49.92 27 54 54 54 54 108 27 27
24 49.761 27 54 54 54 54 108 27 27
50 59.94 54 108 108 108 54 54
50 60 54.054 108.108 108.108 108.108 54.054 54.054
51 59.94 54 108 108 108 54 54
51 60 54.054 108.108 108.108 108.108 54.054 54.054
1440x480i 1440 x 480
58 119.88 108 216 216 216 108 108
58 120 108.108 216.216 216.216 216.216 108.108 108.108
59 119.88 108 216 216 216 108 108
59 120 108.108 216.216 216.216 216.216 108.108 108.108

2D 3D Structure
L+depth+gr
Active
14 59.94 54 108 108 108 108 216 54 54
14 60 54.054 108.108 108.108 108.108 108.108 216.216 54.054 54.054
1440x480p 1440 x 480
15 59.94 54 108 108 108 108 216 54 54
15 60 54.054 108.108 108.108 108.108 108.108 216.216 54.054 54.054
44 50 54 108 108 108 54 54
45 50 54 108 108 108 54 54
54 100 108 216 216 216 108 108
1440x576i 1440 x 576
55 100 108 216 216 216 108 108
29 50 54 108 108 108 54 54
30 50 54 108 108 108 54 54

2D 3D Structure
L+depth+gr
Active
79 24 59.4 118.8 118.8 118.8 118.8 237.6 59.4 59.4
79 23.976 59.341 118.682 118.682 118.682 118.682 237.364 59.341 59.341
80 25 59.4 118.8 118.8 118.8 118.8 237.6 59.4 59.4
81 30 59.4 118.8 118.8 118.8 118.8 237.6 59.4 59.4
81 29.97 59.341 118.682 118.682 118.682 118.682 237.364 59.341 59.341
1680x720p
82 1680 x 720 50 82.5 165 165 165 165 330 82.5 82.5
(HDTV)
83 60 99 198 198 198 198 396 99 99
83 59.94 98.901 197.802 197.802 197.802 197.802 395.604 98.901 98.901
84 100 165 330 330 330 330 165 165
85 120 198 396 396 396 396 198 198
85 119.88 197.802 395.604 395.604 395.604 395.604 197.802 197.802
39 25 72 144 144 144 72 72
40 1920x1080 1920 x 50 148.5 297 297 297 148.5 148.5
46 i (HDTV) 1080 60 148.5 297 297 297 148.5 148.5
46 59.94 148.352 296.704 296.704 296.704 148.352 148.352

2D 3D Structure
L+depth+gr
Active
16 60 148.5 297 297 297 297 594 148.5 148.5
16 59.94 148.352 296.704 296.704 296.704 296.704 593.408 148.352 148.352
31 50 148.5 297 297 297 297 594 148.5 148.5
32 24 74.25 148.5 148.5 148.5 148.5 297 74.25 74.25
32 23.976 74.176 148.352 148.352 148.352 148.352 296.704 74.176 74.176
33 25 74.25 148.5 148.5 148.5 148.5 297 74.25 74.25
34 30 74.25 148.5 148.5 148.5 148.5 297 74.25 74.25
34 29.97 74.176 148.352 148.352 148.352 148.352 296.704 74.176 74.176
63 120 297 594 594 594 594 297 297
63 119.88 296.703 593.406 593.406 593.406 593.406 296.703 296.703
64 1920x1080 1920 x 100 297 594 594 594 594 297 297
72 p (HDTV) 1080 24 74.25 148.5 148.5 148.5 148.5 297 74.25 74.25
72 23.976 74.176 148.352 148.352 148.352 148.352 296.704 74.176 74.176
73 25 74.25 148.5 148.5 148.5 148.5 297 74.25 74.25
74 30 74.25 148.5 148.5 148.5 148.5 297 74.25 74.25
74 29.97 74.176 148.352 148.352 148.352 148.352 296.704 74.176 74.176
75 50 148.5 297 297 297 297 594 148.5 148.5
76 60 148.5 297 297 297 297 594 148.5 148.5
76 59.94 148.352 296.704 296.704 296.704 296.704 593.408 148.352 148.352
77 100 297 594 594 594 594 297 297
78 120 297 594 594 594 594 297 297
78 119.88 296.703 593.406 593.406 593.406 593.406 296.703 296.703

2D 3D Structure
L+depth+gr
Active
86 24 99 198 198 198 198 396 99 99
86 23.976 98.901 197.802 197.802 197.802 197.802 395.604 98.901 98.901
87 25 90 180 180 180 180 360 90 90
88 30 118.8 237.6 237.6 237.6 237.6 475.2 118.8 118.8
88 29.97 118.681 237.362 237.362 237.362 237.362 474.724 118.681 118.681
2560x1080 2560 x
89 50 185.625 371.25 371.25 371.25 371.25 185.625 185.625
p (HDTV) 1080
90 60 198 396 396 396 396 198 198
90 59.94 197.802 395.604 395.604 395.604 395.604 197.802 197.802
91 100 371.25 371.25 371.25
92 120 495 495 495
92 119.88 494.505 494.505 494.505
12 60.054 54 108 108 108 108 216 54 54
12 59.826 54 108 108 108 108 216 54 54
12 60.115 54.054 108.108 108.108 108.108 108.108 216.216 54.054 54.054
12 59.886 54.054 108.108 108.108 108.108 108.108 216.216 54.054 54.054
2880x240p 2880 x 240
13 60.054 54 108 108 108 108 216 54 54
13 59.826 54 108 108 108 108 216 54 54
13 60.115 54.054 108.108 108.108 108.108 108.108 216.216 54.054 54.054
13 59.886 54.054 108.108 108.108 108.108 108.108 216.216 54.054 54.054

2D 3D Structure
L+depth+gr
Active
27 50.08 54 108 108 108 108 216 54 54
27 49.92 54 108 108 108 108 216 54 54
27 49.761 54 108 108 108 108 216 54 54
2880x288p 2880 x 288
28 50.08 54 108 108 108 108 216 54 54
28 49.92 54 108 108 108 108 216 54 54
28 49.761 54 108 108 108 108 216 54 54
10 29.97 54 108 108 108 54 54
10 30 54.054 108.108 108.108 108.108 54.054 54.054
2880x480i 2880 x 480
11 29.97 54 108 108 108 54 54
11 30 54.054 108.108 108.108 108.108 54.054 54.054
35 59.94 108 216 216 216 216 432 108 108
35 60 108.108 216.216 216.216 216.216 216.216 432.432 108.108 108.108
2880x480p 2880 x 480
36 59.94 108 216 216 216 216 432 108 108
36 60 108.108 216.216 216.216 216.216 216.216 432.432 108.108 108.108
25 25 54 108 108 108 54 54
2880x576i 2880 x 576
26 25 54 108 108 108 54 54
37 50 108 216 216 216 216 432 108 108
2880x576p 2880 x 576
38 50 108 216 216 216 216 432 108 108

2D 3D Structure
L+depth+gr
Active
93 24 297 594 594 594 594 297 297
93 23.976 296.703 593.406 593.406 593.406 593.406 296.703 296.703
94 25 297 594 594 594 594 297 297
95 30 297 594 594 594 594 297 297
95 29.97 296.703 593.406 593.406 593.406 593.406 296.703 296.703
96 50 594 594 594
97 60 594 594 594
97 3840x2160 3840 x 59.94 593.407 593.407 593.407
103 p (4K) 2160 24 297 594 594 594 594 297 297
103 23.976 296.703 593.406 593.406 593.406 593.406 296.703 296.703
104 25 297 594 594 594 594 297 297
105 30 297 594 594 594 594 297 297
105 29.97 296.703 593.406 593.406 593.406 593.406 296.703 296.703
106 50 594 594 594
107 60 594 594 594
107 59.94 593.407 593.407 593.407

2D 3D Structure
L+depth+gr
Active
98 24 297 594 594 594 594 297 297
98 23.976 296.703 593.406 593.406 593.406 593.406 296.703 296.703
99 25 297 594 594 594 594 297 297
100 4096x2160 4096 x 30 297 594 594 594 594 297 297
100 p (4K) 2160 29.97 296.703 593.406 593.406 593.406 593.406 296.703 296.703
101 50 594 594 594
102 60 594 594 594
102 59.94 593.407 593.407 593.407
48 119.88 54 108 108 108 108 216 54 54
48 120 54.054 108.108 108.108 108.108 108.108 216.216 54.054 54.054
49 119.88 54 108 108 108 108 216 54 54
49 120 54.054 108.108 108.108 108.108 108.108 216.216 54.054 54.054
720x480p 720 x 480
56 239.76 108 216 216 216 216 432 108 108
56 240 108.108 216.216 216.216 216.216 216.216 432.432 108.108 108.108
57 239.76 108 216 216 216 216 432 108 108
57 240 108.108 216.216 216.216 216.216 216.216 432.432 108.108 108.108
42 100 54 108 108 108 108 216 54 54
43 100 54 108 108 108 108 216 54 54
720x576p 720 x 576
52 200 108 216 216 216 216 432 108 108
53 200 108 216 216 216 216 432 108 108

2D 3D Structure
L+depth+gr
Active
HDMI Video modes (HDMI VIC)
0x01 4K x 2K 3840 x 2160 30 297
0x02 4K x 2K 3840 x 2160 25 297
0x03 4K x 2K 3840 x 2160 24 297
0x04 4K x 2K 3840 x 2160 24 297

2.4 Video Packetizer

This block is responsible for the following:
■ Pixel repetition (if not already performed in the input video stream and needed by the user)
This is an optional feature that can be configured in coreConsultant.
■ 10-, 12-, and 16-bit packing when in deep color modes
■ YCC 422 remapping according to the HDMI specification
■ Clock rate transformation from pixel or repetition clock to the final TMDS clock domain (by means of
FIFOs)
Figure 2-4 depicts a functional diagram of the Video Packetizer block. For more information about the
Video Packetizer registers, refer to Section 6.4 on page 226.
Figure 2-4 Video Packetizer Functional Diagram (with DWC_HDMI_TX_PREP_EN)
Video Packetizer Functional Diagram

(With DWC_HDMI_TX_PREP_EN)
VP_REMAP [1:0]
VP_CONF[3]
YCC422
16, 20, 24
YCC 422
Input
Data remap
Output
Pixel Packing Data
Pixel 8, 10, 12, 16

Repeater Packing Phase
FSM
VP_CONF[2] VP_CONF[0]
VP_CD_PR[3:0]
VP_CONF[4]
VP_CD_PR[7:4]
VP_STUFF[5:3], VP_STUFF[1]
VP_CONF[5]
2.5 HDMI 2.0 TMDS Scrambling Feature

The DWC_hdmi_tx supports the TMDS data scrambling required for transmitting 2160p@60 Hz in RGB
4:4:4, YCbCr 4:4:4, or YCbCr 4:2:2 video formats. This feature is only available when the
DWC_HDMI_TX_20 parameter is enabled in coreConsultant. The fc_scrambler_ctrl register controls the
Scrambler feature. For more information about enabling this feature, see Section 6.5.134 on page 319.
When the HDMI 2.0 support feature is enabled, all output video modes with a TMDS frequency higher than
340 MHz require the Scrambler feature be activated by setting the fc_invidconf.HDCP_keepout register
field to 1‘b1 and fc_scrambler_ctrl.scrambler_en to 1‘b1. For video modes at frequencies equal or below 340
MHz, activating the Scrambler feature is optional and depends on the connected HDMI Sink device and on
your design requirements.

2.6 Color Space Conversion

The Color Space Converter (CSC) is an optional feature that can be configured in coreConsultant. This block
is responsible for carrying out the following video color space conversion functions:
■ RGB to/from YCbCr
■ 4:2:2 to/from 4:4:4 up (pixel repetition or linear interpolation)/down-converter
■ Limited to/from full quantization range conversion
Figure 2-5 Color Space Converter Simplified Block Diagram
g_y_data[15:0] Color Space Converter g_y_data_csc[15:0]

r_cr_data[15:0] r_cr_data_csc[15:0]
b_cb_data[15:0] YCbCr YCbCr YCbCr RGB YCbCr YCbCr b_cb_data_csc[15:0]
4:2:2 4:4:4 4:4:4 4:4:4 4:4:4 4:2:2
de Chroma Color Chroma
de_csc
hsync Interpolation Space Decimation hsync_csc
vsync vsync_csc
pixelclk pixelclk_csc
The CSC supports all the timings reported in the CEA-861-D specification and the following pixel modes:
■ RGB 444 and YCbCr 444: 24, 30, 36, and 48 bits
■ YCbCr 422: 16, 20, and 24 bits
The color space conversion matrix is ruled by the following equations listed in Figure 2-6. The color space
conversion registers base address is 0x4100. For more detailed information about the color space conversion
register, refer to Section 6.13 on page 419.
Figure 2-6 Color Space Conversion Matrix Equations

out1= (X1×in1/4096 + X2×in2/4096 + X3×in3/4096 + X4)×2(scale–2)
out2= (Y1×in1/4096 + Y2×in2/4096 + Y3×in3/4096 + Y4)×2(scale–2)
out3= (Z1×in1/4096 + Z2×in2/4096 + Z3×in3/4096 + Z4)×2(scale–2)
Color Space Conversion to and from YCrCb 4:2:0 is not supported. The color space
Note conversion block with the default clock uncertainty does not meet timing in all technology
nodes at 600 MHz. Only technology nodes at 40nm or lower are supported.

2.7 Audio Interfaces

The DWC_hdmi_tx controller supports four audio interfaces as described in this section. No lipsync
support is available inside the DWC_hdmi_tx. If necessary, this feature can be performed at the system
audio processor side. From the DWC_hdmi_tx, no audio/video delay or skew is added.
The audio sampler registers base address is 0x3100. For more detailed information about these registers,
refer to Section 6.7 on page 374.
This section includes the following topics:
■ “Supported Audio Formats”
■ “I2S interface” on page 64
■ “S/PDIF Interface” on page 66
■ “Generic Parallel Audio (GPA) Interface” on page 67
■ “AHB Audio DMA Interface” on page 72
■ “CTS Calculation” on page 79
2.7.1 Supported Audio Formats

Table 2-3 provides the audio input interfaces and describes the supported audio formats. Previous versions
of the DWC_hdmi_tx controller included an HBR interface. This interface is now obsolete, however, the
interfaces described in Table 2-3 all support HBR:
■ Uncompressed audio formats: IEC60958 L-PCM audio samples
■ Compressed audio formats: IEC61937 compressed non-linear PCM (AC-3, MPEG-1/-2 Audio, DTS®,
MPEG-2/-4 AAC, ATRAC, WMA, MAT)
■ HBR audio formats: Dolby® True-HD and DTS-HD Master Audio, for example
■ Multi-stream Audio (L-PCM or IEC61937 compressed non-linear PCM)
Table 2-3 Supported Audio Formats
Uncompressed Compressed HBR

Interface (L-PCM) (NL-PCM) (High-Bit Rate) Multistream
I2S Supported (up to 8-channels) Supporteda Supporteda Supported
S/PDIF Supported (up to 8 channels) Supported Supportedb Supported
GPA Supported (up to 8-channels) Supported Supported Supported
AHB Audio DMA Supported (up to 8-channels) Supported Supported Supported
a. To support Compressed audio and HBR, you must map data on the I2S stream according to “HBR and NL-PCM
Support for I2S Interface” on page 65
b. For HBR support, you must enable HBR_ON_SPDIF and provide audio data at 768 kHz rate or 1536 kHz rate
(supported in HDMI 2.0b only).

2.7.2 I2S interface

The I2S interface uses the I2S audioclk input to sample Linear-PCM input data and stores it in an input
audio FIFO. There are four I2S data lines that support up to 192 kHz sampling rates (supports a maximum
theoretical audio rate of 768 kHz or 1536 kHZ (supported in HDMI 2.0 only) for a two-channel standard
I2S). The I2S interface is compliant with the I2S specification from NXP.
Each I2S interface supports two audio channels. The DWC_hdmi_tx has four I2S interfaces supporting up to
eight audio channels simultaneously at 192 kHz. Each audio sample width can be configured to be from 16
bits up to 24 bits. The I2S_width field of the aud_conf1 register selects the bit width for each right/left
sample. Each right/left channel can carry 1 to N bits (N=16 to 24).
The i2slrck input signal must have the same frequency as the Audio Sampling Rate fs, that is 32 kHz to 192
kHz. The INPUTCLKFS setting must be consistent with the frequency of i2sclk.
For example:
If INPUTCLKFS = 128fs, and fs=32 kHz,
Then i2sclk = 128 x 32 kHz=4096 kHz
In I2S mode (as depicted in Figure 2-7), the most significant bit of the sub-frame data (B bit) must be sent on
the second active edge of ii2sclk following an ii2slrclk transition. The other bits up to the least significant bit
(LSB) are then transmitted in order. Depending on word length, ii2sclk frequency, and sample rate, there
may be unused ii2sclk cycles between the LSB of one sample and the MSB of the next.
The sub-frame can as wide or larger than the sub-frame data size (such as, BPCUV+24bits audio sample = 29
clock periods). In a typical scenario, the sub-frame can be 32 clocks wide, and all clock periods after the
audio sample LSB are unused and i2sdata set to 0, regardless of audio sample width.
Figure 2-7 I2S Format
1 / fs
Left Channel Right Channel
i2slr ck
i 2sclk
i2sdata 1 2 3 N-2 N -1 N 1 2 3 N -2 N -1 N
1
MSB LSB MSB LSB
For configuration details, refer to the Audio Sampler Registers described in Section 6.7 on page 374.

Table 2-4 Data Mapping Examples – I2S Interface with PCUV
I2S Width 28 27 26 25 24 23 22 21 20 … 8 7 6 5 4 3 2 1 0
24 B P C U V MSB LSB
HBR and NL-PCM Support for I2S Interface

The I2S interface is not specifically designed for HBR and NL-PCM streaming. Hence, you need to manually
map the HBR streaming, by following these steps:
1. Split the stream in four sub-streams by sending the stream to a FIFO with four outputs each. Each
substream consists of a pair of samples.
2. Apply the i2sclk clock to the I2S interface with a frequency of 128*fs (for example, 49.152 MHz for a
1536 kHz input).
3. Set the I2S sample width to 21 bits by using the aud_conf1.i2s_width bit field register.
This sample is sampleI2S[20:0].
4. Configure the aud_conf2 register to HBR mode by using the HBR field (bit 0).
5. Configure the I2S interface by using the aud_conf0.i2s_in_en bit field register.
Enable all the four channels so that each channel carries a pair of samples.
6. Map the I2S data sample, sampleI2S[20:0], in the following way:
sampleI2S[20:0] = {B,P,C,U,V, dataHBR[15:0]}
(Where B,P,C,U,V are IEC61937 parameters, and dataHBR[15:0] is the actual HBR sample data.)
7. Ensure that the I2S_in_en[3:0] channels adhere to the following arrangement:
Left Channel Right Channel
I2S_in_en[0] Sample 1 Sample 2
(B or M associated samples for (W associated samples for
IEC61937 NL-PCM) IEC61937 NL-PCM)

8. The input sample sequence is such that the line transports frames (1 frame = 2 samples), as indicated
in the following table:
Frame Line
Sample 1, 2 I2S_in_en[0]
... ...
For NL-PCM streaming <= 192 kHz, it is expected that the BPCUV information is available on the
audio input stream and the controller is configured as L-PCM.
2.7.3 S/PDIF Interface

The S/PDIF audio input interface is compatible with the S/PDIF Linear and Non-linear (IEC90658 and
IEC61937) Digital Audio specification. The S/PDIF interface is a consumer version of the AES/EBU
interface; it is commonly used to move digital audio between pieces of consumer electronic equipment, such
as a DVD player and a surround-sound receiver.
The two data formats (S/PDIF and AES) and data rate are compatible with each other, differing only in the
electrical and physical connectors. The S/PDIF uses ispdifclk to sample the ispdifdata data and store it in a
29-bit width variable depth audio FIFO.
The S/PDIF interface with DRU present does not support the HBR rates above 768 kHz added by the HDMI
2.0b specification. If the DRU is not present, all audio frequencies are supported.
ispdifclk Input Clock Requirements

When the Data Recognition Unit (DRU) is present (HTX_SPDIFBYPDRU parameter is disabled), the
ispdifclk clock input must be a synchronous clock source with respect to the S/PDIF data at a rate of 512 fs.
When the DRU is not present (HTX_SPDIFBYPDRU is set), the ispdifclk at the input of the controller must
be synchronous with respect to the audio stream, and its frequency must be exactly 128 times the original
audio bit stream.

Table 2-5 Data Rate, Bi-Phase Channel Coding Rate, Required ispdifclk Rates
Synchronous Synchronous ispdifclk

Bi-Phase
S/PDIF Bit ispdifclk Rate Rate fs (MHz) with DRU
Audio Sample Mark Coding
Rate 64xfs (MHz) without Present
Rate fs (kHz) Rate 2x64xfs
(Mbps) DRU Present 4x2x64xfs=512xfs
(MHz) 2x64xfs (MHz) (MHz)
32 2.048 4.096 4.096 16.384
44.1 2.8224 5.6448 5.6448 22.5792
48 3.072 6.144 6.144 24.576
64 4.096 8.192 8.192 32.768
88.2 5.6448 11.2896 11.2896 45.1584
96 6.144 12.288 12.288 49.152
8.192 16.384 16.384 65.536

128
1.1536a 98.304 196.608 196.608
176.4 11.2896 22.5792 22.5792 90.3168
192 12.288 24.576 24.576 98.304
768a 49.152 98.304 98.304 -
a. Only available when HBR_ON_SPDIF is enabled.
2.7.4 Generic Parallel Audio (GPA) Interface

The Generic Parallel Audio interface fetches audio samples for the enabled channels approximately at the
configured audio rate. It supports L-PCM, NL-PCM, and HBR audio. No audio clock is required. Software
configures the ACR information, N, and CTS, and the samples are clocked with igpaclk, which can be tied to
the system clock.
When the audio source initiates a transfer (igpavalid = 1), it must contain enough samples to create at least
one full audio packet without interruption. For instance, if eight audio channels are enabled, the data source
(after signaling that it is ready to transfer data by setting igpavalid to a logic high) must provide eight
samples without interruption. Lowering igpavalid is not allowed until the end of the request.
If for any reason the source lowers the igpavalid during an audio transfer, the transmitted audio becomes
misaligned. Also, the first transmitted sample after reset must be the sample for Audio Channel 1, left
sample, and the audio source must maintain the alignment.
2.7.4.1 Timing information

The igpavalid signal must go low when no sample is required and remains high when the HDMI Tx
activates the ogpadatareq signal again. There is no restriction in terms of the cycle between the ogpadatareq
and the igpavalid. However, it must be assured that data can be transferred correctly; the maximum is two
cycles.

Figure 2-8 on page 68 and Figure 2-9 on page 68 show two-channel and eight-channel transfers, respectively, that are able to meet the HDMI audio
flow.
Figure 2-8 Generic Parallel Audio Interface Timing Diagram for 2-Channel Audio Transfer (LPCM or NLPCM <= 6.144Mbps)
approx.191 x (1/fs) approx. 1/fs
igpaclk
one or more 1 clock cycle

ogpadatareq clock cycles
igpadata[27:0] Channel 1 Channel 2 Channel 1 Channel 2 Channel 1 Channel 2

Frame 0 Frame 0 Frame 191 Frame 191 Frame 0 Frame 0
igpadata[28]
igpavalid
Figure 2-9 Generic Parallel Audio Interface Timing Diagram for 8-Channel Audio Transfer (LPCM Only)
approx. 1/fs
igpaclk
ogpadatareq one or more 1 clock cycle

clock cycles
igpadata[27:0] Channel 1 Channel 2 Channel 3 Channel 4 Channel 5 Channel 6 Channel 7 Channel 8 Channel 1
Frame 0 Frame 0 Frame 0 Frame 0 Frame 0 Frame 0 Frame 0 Frame 0 Frame 1
igpadata[28]
igpavalid

Figure 2-10 Generic Parallel Audio Interface Timing Diagram for HBR (NLPCM > 6.144Mbps) – Frame 0 Transmitted in Subpacket 0
approx. 1/fs
igpaclk

clock cycles
igpadata[27:0]
Data 382 Data 383 Data 0 Data 1 Data 2 Data 3 Data 4 Data 5 Data 6
igpadata[28]
igpavalid
Figure 2-11 Generic Parallel Audio Interface Timing Diagram for HBR (NLPCM > 6.144Mbps) – Frame 0 Transmitted in Subpacket 1
approx. 1/fs
igpaclk

clock cycles
igpadata[27:0] Data 382 Data 383 Data 0 Data 1 Data 2 Data 3 Data 4 Data 5 Data 6
igpadata[28]
igpavalid

2.7.4.2 Data Mapping Examples

The number of channels is configurable between 2 up to 8. Similar data mapping rules apply for 3, 4, …,8
channels.
In Table 2-6 and Table 2-7, the data from bits 28:24 can be omitted from the input and inserted
Note by the DWC_hdmi_tx controller. This functionality is only valid when the GP Audio interface is
selected (AUDIO_IF = GPAUD [6]) and for Linear PCM audio only.
Table 2-6 L-PCM Two-Channel Data Mapping
igpadata Bit
Sample No. 28 27 26 25 24 23 ... 8 7 ... 0
0 B.0. P C U V CHANNEL 1
0x00
L-PCM 16-bit sample
L-PCM 24-bit sample
Table 2-7 L-PCM Eight-Channel Data Mapping
igpadata Bit
Sample No. 28 27 26 25 24 23 ... 8 7 ... 0

Table 2-7 L-PCM Eight-Channel Data Mapping (Continued)
igpadata Bit
Sample No. 28 27 26 25 24 23 ... 8 7 ... 0
0x00
L-PCM 16-bit sample
L-PCM 24-bit sample
Table 2-8 NL-PCM Data Mapping
igpadata Bit
Sample No. 28 27 26 25 24 23 ... 8 7 ... 0
0 B.0. P C U V DATA 0 0x0000
1 B.0. P C U V DATA 1 0x0000
2 B.0. P C U V DATA 2 0x0000
3 B.0. P C U V DATA 3 0x0000
4 B.0. P C U V DATA 4 0x0000
5 B.0. P C U V DATA 5 0x0000
... B.0. P C U V ... 0x0000
n B.0. P C U V DATA n 0x0000
NL-PCM 16-bit sample

2.7.5 AHB Audio DMA Interface

The audio direct memory access (DMA) interface is intended for advanced systems running 32-bit CPU SoC
solutions with an AHB. This is useful in systems where a DSP handles audio processing. In these systems,
sending the incoming audio samples directly to the memory provides a cleaner architecture to the SoC,
without the overhead of converting several audio standards.
Figure 2-12 Audio DMA Block Diagram
Audio DMA BUFFER

DMA FIFO
(Fixed 16 samples
(Programmable depth) FIFO Sync
per channel)
29 29
8
AHB Master FIFO Empty
Interrupt
DMA
Engine
hclk tmdsclk
The audio DMA block combines an AHB master interface with a FIFO to perform direct memory access to
audio samples stored in a system memory.
The DMA engine is configurable through programmable software registers to perform autonomous burst
reading on a configured memory range.
For more information on the CTS/N values, see “CTS Calculation” on page 79.
2.7.5.1 AHB Master

The AHB master is compliant with the AMBA AHB Specification, Revision 2.0 from ARM. It supports the
following features:
■ Capable of operating on a bus with multiple masters and slaves
■ 32-bit data transfer
■ OKAY, ERROR, RETRY, and SPLIT slave responses
■ Rescheduling of burst requirements
■ IDLE, NONSEQ, and SEQ transfer types
■ Incremental burst modes: INCR, INCR4, INCR8, and INCR16 fixed-beat bursts
■ Configurable Master burst lock mechanism

The following features are not supported:

■ Write transaction
■ Protection control
■ BUSY transfer type
■ Wrapping burst
Data Organization in System Memory

The AHB master block fetches the samples from system memory. The Audio Samples are organized
according to the channel allocation. For example, channel 0, 1, 3, and 5 are enabled (0 and 1 are always
enabled). The Audio Samples must be organized in the system memory as presented in the following tables:
Table 2-9 Audio Sample Arrangement in System Memory
Position Sample Channel
0 n-1 0
1 n-1 1
2 n-1 3
3 n-1 5
4 n 0
5 n 1
6 n 3
7 n 5
... ... ...
Table 2-10 Data Arrangement in System Memory for L-PCM (24 bits)
Bit Description
28 B – IEC B Bit
27 P – Parity Bit
26 C – Channel Status Bit
25 U – User Data Bit
24 V – Validity Bit
[23:0] Audio Sample Data

Table 2-11 Data Arrangement in System Memory for L-PCM (16 bits) and NL-PCM (16 bits)
Bit Description
28 B – IEC B Bit
27 P – Parity Bit
26 C – Channel Status Bit
25 U – User Data Bit
24 V – Validity Bit
[23:8] Audio Sample Data
[7:0] 0x00
2.7.5.2 DMA Engine

The DMA engine is responsible for requesting burst transfers to the AHB master, taking into account the
FIFO threshold and register settings.
Functional Behavior
The engine:
■ Commands read requests to start the burst in the initial address with the size sufficient to fill the
FIFO (the size of the FIFO is a parameter in the audio DMA controller)
After this first request, the DMA engine performs subsequent burst requests (incrementing
accordingly ohaddr[31:0] and determining correct ohburst[2:0]) towards final_addr[31:0] configured
at the register bank and taking into account the FIFO depth and fifo_threshold[7:0] configuration.
■ Stops operation upon ERROR slave response, signaling ointerror interrupt and staterror signal
■ Issues ointdone interrupt when it reaches final address reading or is stopped upon user request
■ Automatically starts new burst requests until the final_addr[31:0] is reached
The DMA engine is either stopped by the user or an error condition appears at the slave response.

DMA Operation
Normal operation of the DMA engine is as follows:
1. The enable_hlock, incr_type[1:0], burst_mode, fifo_threshold[7:0], initial_addr[31:0], and
final_addr[31:0] are configured according to desired DMA operation.
Note The configured values must have the final_addr[31:0] value greater than the
initial_addr[31:0] value.
2. To start the audio DMA operation, a ‘1’ is written to start_dma_transaction.

3. The DMA engine starts the operation.
4. The DMA requests data either until enough audio samples are read to fill the FIFO, or until the
provided buffer is consumed. While DMA is reading samples from the AHB master and writing
samples to the Audio FIFO, a data fetch request from the internal frame composer block might
happen at the Audio FIFO interface, diminishing the number of samples in the FIFO.
5. When the number of samples in the Audio FIFO is lower than the configured fifo_threshold[7:0], the
DMA engine requests a new burst request to the AHB master interface with:
ohaddr[15:0] = last address in step 5);
ohburst[2:0] = INCR;
mburstlength[8:0] = 2^HDMI_TX_AHBDMAAUD_FIFO_ADDRWITH - fifo_threshold[7:0];
6. Steps 4 and 5 continue until the final_addr[31:0] is reached.
Note In the last burst request, the DMA engine calculates the mburstlength[10:0]
such that the last requested read position is the final_addr[31:0].
7. After completion of the DMA operation, the DMA engine issues the ointdone interrupt signaling end
of operation.
Variations of the DMA engine’s behavior occur when fixed-beat, incremental bursts are used by
INCR4/INCR8/INCR16 burst selects. When these burst modes are used, the DMA uses the selected transfer
size for the bulk of its transfers. It uses INCR transfers to resume from RETRY/SPLIT, and to finalize the
transfers if any one of the fields initial_addr[31:0], final_addr[31:0], or fifo_threshold are not aligned with
the selected burst size.
The following are exceptions to the described DMA behavior:
■ When a user requests end stop_dma_transaction, the DMA engine stops at the end of the current
burst operation and signals its completion with an ointdone interrupt.
■ When the AHB slave sends an error response, the DMA engine stops the current operation and
signals ointerror and ointdone interrupts.

Transfer Data, Package, and Word

One transfer data can be composed of several transfer packages, and one transfer package can be composed
of one or several transfer bursts. One transfer burst can be composed of several transfer words. Figure 2-13
shows the transfer data structure for a fixed-beat, incremental burst.
Figure 2-13 Transfer Data Constitution for Unspecified Length, Incremental Burst
Package 1 Package M
burst1 burst2 ... burstN ... burst1 burst2 ... burstN
word1 word2 ... wordL
L = 4(for INCR4), 8(INCR8), 16(INCR16)
Figure 2-14 on page 76 depicts the transfer data structure for an unspecified burst length.
Figure 2-14 Transfer Data Constitution for Fixed-Beat, Incremental Burst
Package 1 Package M
burst1 ... burst1
word1 word2 ... wordL
L = unspecified number for INCR

Figure 2-15 illustrates the DMA state machine.
Figure 2-15 DMA FSM Diagram
!s
DMA IDLE ta
n r t_
ctio dm
nsa a_
tra tra
a_ n
t_dm sa
r cti
sta ! start_dma_transaction on
!FIFO below threshold AND

stop_dma_transaction
DMA REQ DMA STOP DMA ERR
Final address reached

OR
FIFO below threshold: stop_dma_transaction
AND pack finish
AND HRESP != ERR
DMA XFER AHB Master receives HRESP=ERR
HRESP != ERR AND

!final address AND
!AHB DMA FIFO full* !stop_dma_transaction AND
AHB DMA FIFO full* pack finish
DMA DONE
In this diagram, the FSM assumes the following states.
FSM DMA IDLE

The transaction has not started.
■ The operation request is written into start_dma_transaction.
■ The state switches from DMA IDLE to DMA REQ.
DMA REQ
The DMA is waiting in this state for the HDMI interface to consume samples.
■ When DMA FIFO goes below threshold, DMA calculates a new start address and burst length, and
the state changes from DMA REQ to DMA XFER.
■ If stop_dma_transfer is received at DMA REQ, the state changes from DMA REQ to DMA STOP.

DMA XFER
The DMA commands the AHB Master to perform data transfers. There are three possible transitions that
can occur from this state:
■ If an error occurs in the AHB bus (HRESP=ERROR), the FSM goes to the DMA ERR state.
■ If the final address is reached or a stop_dma_transaction is received, the FSM goes to the DMA STOP
state.
■ If the AHB Master sends a pack finish signal, the FSM goes to state DMA DONE.
A pack is a block transfer of a maximum of 256 words. It can be lower due to the proximity of the 1K
address boundary, end of software buffer, or available headroom on the AHB DMA FIFO.
DMA DONE
The AHB DMA monitors the expected fill state of the AHB Audio DMA FIFO.
■ If the AHB Audio DMA FIFO is not full, the FSM goes to the DMA XFER state to request samples
from the AHB bus until enough samples are read to fill the FIFO.
■ If the AHB Audio DMA FIFO is full, the DMA FSM proceeds to the DMA REQ state to wait for a
below threshold event.
Note If samples are retrieved from the AHB Audio DMA FIFO during a sample read from the AHB
Bus, the AHB FIFO full event does not occur.
DMA STOP
A stop_dma_transaction signal is received.
■ The FSM waits for an inverted start_dma_transaction signal from the register bank as an
acknowledgment of a stop_dma_transaction signal.
■ When the start_dma_transaction signal inverts, the FSM goes to the state DMA IDLE.
2.7.5.3 Audio FIFO

This block contains a FIFO with a depth that can be configured through the “AHB Audio DMA FIFO
Address Width” option in coreConsultant (HDMI_TX_AHBDMAAUD_FIFO_ADDRWITH).
The statthrfiffoempty flag is a version of the FIFO empty, that is active whenever the amount of samples in
the FIFO is smaller than the number of audio channels enabled.

2.7.6 CTS Calculation

Because there is no audio clock carried through the HDMI link. Only the pixel clock is used. The CTS/N has to be set by software with value taken in
the following table. Table 2-12 shows the CTS and N value for the supported standard.
Table 2-12 N and CTS for 8-Bit Color Depth
TMDS Clock (MHz)
25.2 27 54 74.25 148.5 297 597
Fs (kHZ) N CTS N CTS N CTS N CTS N CTS N CTS N CTS
32 4096 25200 4096 27000 4096 54000 4096 74250 4096 148500 3072 222750 3072 445500
44.1 6272 28000 6272 30000 6272 60000 6272 82500 6272 165000 4704 247500 9408 990000
48 6144 25200 6144 27000 6144 54000 6144 74250 6144 148500 5120 247500 6144 495000
64 8192 25200 8192 27000 8192 54000 8192 74250 8192 148500 8192 247500 8192 594000
88.2 12544 28000 12544 30000 12544 60000 12544 82500 12544 165000 9408 247500 18816 990000
96 12288 25200 12288 27000 12288 54000 12288 74250 12288 148500 10240 247500 12288 495000
128 16384 25200 16384 27000 16384 54000 16384 74250 16384 148500 16384 247500 16384 594000
176.4 25088 28000 25088 30000 25088 60000 25088 82500 25088 165000 18816 247500 37632 990000
192 24576 25200 24576 27000 24576 54000 24576 74250 24576 148500 20480 247500 24576 4950000
256 32768 25200 32768 27000 32768 54000 32768 74250 32768 148500 32768 297000 32768 594000
352.8 50176 28000 50176 30000 50176 60000 50176 82500 50176 165000 37632 247500 75264 990000
384 49152 25200 49152 27000 49152 54000 49152 74250 49152 148500 40960 247500 49152 594000
For HBR audio, the N and CTS configured are set to 1/4th of the ACR value, as per HDMI specification.
To support the deep color mode and/or 3D video modes, the TMDS clock is multiplied by 4, 2, 1.5, or 1.25, depending on the mode. In this case, the
CTS value must also follow the same ratio.

The TMDS clocks divided or multiplied by 1,001 coefficients are supported by configuring the aud_cts_dither register with the corresponding ratio.
The CTS registers value configured are always the larger value of the interval. If the fractional portion of CTS values is:
■ 0.50 – aud_cts_dither register must be configured with 8'h12 (1/2 duty cycle)
■ 0.875 – aud_cts_dither register must be configured with 8'h7/8 (7/8 duty cycle, 7 with the larger value one with the smaller value).
Table 2-13 N and CTS for 8-Bit Color Depth with CTS Dithering
TMDS Clock (MHz)

25.2/1.001 27 54*1.001 54*1.001 74.25/1.001 148.5/1.001 297/1.001 594/1.001
Fs (kHz) N CTS N CTS N CTS N CTS N CTS N CTS N CTS
32 4576 28125 4096 27027 4096 54054 11648 210938a 11648 421875 5824 421875 5824 843750
44.1 7007 31250 6272 30030 6272 60060 17836 234375 8918 234375 4459 234375 8918 937500
48 6864 28125 6144 27027 6144 54054 11648 140625 5824 140625 5824 281250 5824 562500
64 9152 28125 8192 27027 8192 54054 23296 210938a 23296 421875 11648 421875 11648 843750
88.2 14014 31250 12544 30030 12544 60060 35672 234375 17836 234375 8918 234375 17836 937500
96 13728 28125 12288 27027 12288 54054 23296 140625 11648 140625 11648 281250 11648 562500
128 18304 28125 16384 27027 16384 54054 46592 210938a 46592 421875 23296 421875 23296 843750
176.4 28028 31250 25088 30030 25088 60060 71344 234375 35672 234375 17836 234375 35672 937500
192 27456 28125 24576 27027 24576 54054 46592 140625 23296 140625 23296 281250 23296 562500
256 36608 28125 32768 27027 32768 54054 93184 210938a 93184 421875 46592 421875 46592 843750
352.8 56056 31250 50176 30030 50176 60060 142688 234375 71344 234375 35672 234375 71144 937500
384 54912 28125 49152 27027 49152 54054 93184 140625 46592 140625 46592 281250 46592 562500
For HBR audio, the N and CTS configured are set to 1/4th of the ACR value, as per HDMI specification.
a. This value alternates because of the restriction on N.

2.7.6.1 Start-Stop, Auto-Start Mechanism

The HDMI audio transmission requires that a constant stream of audio samples is transmitted on the
DWC_hdmi_tx controller at the maximum rate of 1.536 Msamples/second (eight audio channels at 192
kHz). To achieve this worst-case constant stream, the DWC_hdmi_tx host system must be able to intercept
the done interruption, reconfigure the Start and Stop addresses, and re-issue a start_dma_transaction within
approximately 72μs.
The time gap between reconfigurations is obtained with the following formula:
HDMI_TX_AHBDMAAUD_FIFO_ADDRWITH
2 – 2 x Number of audio channels enabled
tfifo_hold = Number of audio channels enabled
Fs
The worst case scenario for safe operation (72μs) is achieved for an AHB audio DMA FIFO depth of 128
positions, an audio sampling frequency of 192 kHz, and eight audio channels enabled.
To increase this time gap, the DWC_hdmi_tx controller includes a mechanism for a dual buffer and for
auto-starting the audio transfer. To use the auto-start mechanism, it is required to set (1’b1) the
ahb_dma_conf2.autostart_enable bit field register and configure two sets of audio sample buffers on the
ahb_dma_straddr_set0_*, ahb_dma_stpaddr_set0_*, ahb_dma_straddr_set1_*, and
ahb_dma_stpaddr_set1_* registers.
This mechanism enables that the time required between reconfigurations be only limited by the size of the
provided buffer (final_address – initial_address + 1) and is calculated by the following formula:
Number of audio samples in provided buffer

treconfig_autostart = Number of audio channels enabled
Fs
Two operational modes are implemented and controlled through the ahb_dma_conf2.autostart_loop
register bit field. In the default mode (ahb_dma_conf2.autostart_loop set to 1‘b1), blind loop,
non-acknowledged operation is allowed. This mode targets a use case with static software buffers and
guaranteed audio samples throughput.
When autostart_loop is disabled (1’b0), you are required to acknowledge all buffer set usage, by updating at
least the LSB of the buffer stop address (ahb_dma_stpaddr_set0_0 or ahb_dma_stpaddr_set1_0). This flow
ensures that the hardware never uses a dirty buffer and targets use cases where the system is unable to
ensure the required audio data throughput at all times.
This bit has no effect if the autostart_enable is clear (1‘b0).
Figure 2-16 on page 82 and Figure 2-17 on page 83 shows the Set0 and Set1 audio sample buffers and the
auto-start mechanism.
Figure 2-18 on page 84 and Figure 2-19 on page 85 illustrate the programming flow for the auto-start
mechanism when Loop mode is enabled or disabled.

Figure 2-16 Dual Buffer, Auto-Starting Audio Transfer (Loop Mode Enabled)

Figure 2-17 Dual Buffer, Auto-Starting Audio Transfer (Loop Mode Disabled)

Figure 2-18 Auto-Start Programming Model – Loop Mode Enabled, Static Buffer Location
Write
ahb_dma_conf2.autostart_enable = 1‘b1
Write
ahb_dma_conf2.autostart_loop = 1‘b1
Define Set 0 Buffer

Write ahb_dma_straddr_set0_0 to
Define Set 1 Buffer

Issue start_dma_transaction
Yes ■ Software can trigger system to

Done Interrupt
received? update the consumed buffer content
■ Software can read ahb_dma_status
to find out which buffer has been
No consumed
You can use this flow using dynamic allocated software buffers, but you must ensure that you
Note update the start and stop addresses before the next done interruption as hardware is not
checking if the buffers have been updated.

Figure 2-19 Auto-Start Programming Model – Loop Mode Disabled
Write
ahb_dma_conf2.autostart_enable = 1‘b1
Write
ahb_dma_conf2.autostart_loop = 1‘b0
Define Set 0 Buffer

Define Set 1 Buffer

Issue start_dma_transaction
■ If ahb_dma_status.autostart_status is clear
(consuming buffer 0), update Set 1 Buffer
Yes (ahb_dma_straddr_set1_0 to
Done Interrupt ahb_dma_stpaddr_set1_3) — update at least
received? ahb_dma_stpaddr_set1_0
■ If ahb_dma_status.autostart_status is set
(consuming buffer 1), update Set 0 Buffer
No (ahb_dma_straddr_set0_0 to
ahb_dma_stpaddr_set0_3) — update at least
If the software is late updating the addresses of the Set 0 and/or Set 1 buffers, hardware
Note disables autostart_enable and the audio stream becomes lost. In this scenario, the AHB audio
DMA stops and requires a restart (clear the FIFOs through ahb_dma_conf0.sw_fifo_rst,
reconfigure autostart_enable, start/stop addresses, and issue a start_dma_transaction).
The following exception handling applies, when ahb_dma_conf2.autostart_enable is set (1'b1):

■ When an AHB error occurs, the auto-start automatically clears (1‘b0).
■ When a stop_dma_transaction command is received, the auto-start automatically clears (1‘b0).
■ When a software reset is requested through ahb_dma_conf0.sw_fifo_rst or
mc_swrstzreq_2.ahbdmaswrst_req, the auto-start auto clears (1‘b0).

■ If the autostart_loop is disabled (1'b0) and the controller detects that the next software buffer to be
used is not up to date (checked at the time of the done interruption), the autostart_enable
automatically clears (1'b0).
This feature reduces the overhead on the reconfiguration of the AHB audio DMA, but the
Note DWC_hdmi_tx host system must always ensure that samples reach the AHB audio DMA
master within the time gap determined tfifo_hold.
2.7.6.2 PCUV Insertion

The DWC_hdmi_tx controller can be configured through the ahb_dma_conf0.insert_pucv bit field register,
which inserts the PCUV (Parity, Channel status, User bit, Valid and B bits) data onto the outgoing audio
packets. When insert_pucv is active (1‘b1), any PCUV input data is ignored, and the parity and B pulse bits
are generated in run time, while the Channel status, User bit, and Valid bit are retrieved from the
fc_audschnls0 to fc_audschnls8, fc_audsu, and fc_audsv registers. When insert_pucv is inactive (1‘b0), the
data is sourced from the AHB audio DMA data stream.
This feature is only available only for Linear PCM audio transmission.

2.8 Frame Composer

This block is responsible for assembling video, audio, and data packets in a consistent frame that are
streamed to the HDCP cipher and then finally to the HDMI Tx PHY.
2.8.1 Data Island Packets

The HDMI standard precisely describes the packet insertion timing and distribution that must be followed
to correctly compose an HDMI TMDS (transition minimized differential signaling) stream. In this context,
there are data island packets that—when available (ready for insertion in output stream)—have higher
priority over others. Two packet descriptor queues are responsible for prioritizing packet insertion.
The higher priority packets are described in Table 2-14. These packets are inserted in the output stream as
soon as data to compose them is available (refer to the HDMI 1.3a standard).
Table 2-14 High Priority Data Island Packets
Packet Description
Audio Clock Regeneration (ACR) Indicates to sink device the N/CTS values that should be used in the ACR process
Audio Sample (AUDS) Transports L-PCM and IEC 61937 compressed audio
General Control (GCP) Indicates Color Depth, Pixel Packing phase, and AV mute information to sink
device
The packets described in Table 2-15 can be considered as low priority packets—even though they have
precise timing insertion—because their insertion timing is large (for example, one per frame or one per two
frames without specific location for some of the packet types and on user request transmit for others).
Table 2-15 Low Priority Data Island Packets
Packet Description
Audio Content Protection (ACP) Used to convey content-related information about the active audio stream
transmitted
Audio InfoFrame (AUDI) Indicates characteristics of the active audio stream by using IEC 60958
channel status bits, IEC 61937 burst info, and/or stream data (if present).
Null (NULL) Ignored by sink devices.
International Standard Recording Code Refer to HDMI 1.3a section 5.3.8.

(ISRC1/ISRC2)
Vendor Specific (VSD) InfoFrame According to CEA-861-E standard.
AVI infoFrame (AVI) Video information from source to sink.
Source Data Product Descriptor (SPD) Name and product type of the source device. MPEG (MPEG) Source
infoFrame InfoFrame packets (optional, implementation discouraged by CEA-861-E
Section 6.7). Describes several aspects of the compressed video stream
that were used to produce the uncompressed video.

The Frame Composer distributes and assembles the data island packets according to the module register
bank configuration. The block allows extended control periods to appear with a certain programmed
spacing. The Frame Composer uses two packet buffers that allow a packet to be composed while another is
being sent to the output HDMI stream.
Packet requests are inserted into the packet queues by a data island flexible scheduler. The HDMI
specification requires that packet distribution and insertion timing correctly compose an output HDMI
TMDS stream. In this context, there are data island packets that are sent on data availability, while others
are sent once per frame or once per two frames. and finally others that are sent on user request.
Classification of the packets according to this insertion timing is described in Table 2-16.
Table 2-16 Packet Classification
Packet Classification
Audio Clock Regeneration (ACR) Sent on data availability.
Audio Sample (AUDS) Sent on data availability (precede ACR if present).
Audio Content Protection (ACP) On user request or automatic insertion.
Audio InfoFrame (AUDI) Once per two frames.
Null (NULL) On user request or automatic insertion to fill Data Island period.
General Control (GCP) Once per frame.
International Standard Recording Code On user request.
(ISRC1/ISRC2)
Vendor Specific (VSD) InfoFrame On user request or automatic insertion.
AVI infoFrame (AVI) Once per frame.
Source Data Product Descriptor (SPD) infoFrame On user request or automatic insertion.
Data Island Scheduler

The Data Island Scheduler (DIS) handles packet distribution in the Frame Composer. The DIS is a round-
robin (RDRB) state machine that is able to schedule packet insertion on an input video frame or line basis.
The DIS is fully configurable and can schedule any packet type to be inserted at a given input video frame
rate or input video line rate.
While determining packet distribution on an input video frame or line basis, the DIS schedules the packets
to be inserted in the output HDMI stream by inserting the packet descriptor in the corresponding packet
priority queue, according to packet priority classification.
When activating auto packet scheduling, there is a possibility of sending multiple

Note vendor-specific infoframes and violating CEA-861F.
Data Island Packer

After the packet descriptor has been inserted in the packet priority queues, the Data Island Packer (DIP) is
responsible for assembling and sequencing the packets for output HDMI stream insertion. Dedicated ECC
generators and checksum byte-wide sum hardware generate the BCH ECC parity codes and info frames
checksums for all the data islands packets.

The content of GCP, ISRC1/2, VSD, AVI, and SPD packets are configured through the registers bank
starting at address 0x1000. For more detailed information about the Frame Composer registers, refer to
Section 6.5 on page 235.
2.9 HDCP Encryption Engine
Note This feature must be configured and requires a separate license.
2.9.1 HDCP 1.4

HDCP is designed to protect the transmission of audio-visual content between an HDCP Transmitter and
an HDCP Receiver. The system also allows for HDCP Repeaters that support downstream HDCP-protected
interface ports. The HDCP system allows up to seven levels of HDCP Repeaters and as many as 128 total
HDCP devices, including HDCP Repeaters, to be attached to an HDCP-protected interface port.
The authentication protocol enables the HDCP Transmitter to verify that a given HDCP Receiver is licensed.
With the legitimacy of the Receiver determined, encrypted HDCP content is transmitted between the two
based on shared secrets established during authentication. In the event that legitimate devices are
compromised to permit unauthorized use of the content, renewability allows an HDCP Transmitter to
identify such compromised devices and prevent the transmission of the content.
The implemented HDCP functionality is compliant with HDCP revision 1.4. The HDCP transmitter
implements the three layers of the HDCP cipher, including LFSR and other functions required to generate
the encryption key bytes that are then XORed with the data.
To perform the authentication steps of the HDCP protocol, the DWC_hdmi_tx includes a set of registers and
interrupts. It also includes AV mute capabilities via a mapped register configuration. HDCP keys and a
revocation list can be read from external ROM by a dedicated interface.
For more information about the HDCP authentication protocol, refer to the “HDCP Application Note” in
the DesignWare Cores HDMI Tx Controller User Guide.
Figure 2-20 on page 90 shows a block diagram of the DWC_hdmi_tx with HDCP.

Figure 2-20 Top-Level Diagram of HDMI Tx Controller with HDCP
H13CTRL
data, clk,
D Q de
Video In Video Sampler Color Space Video vsync
Converter Packetizer hsync
Register
Block
data, clk, dc
I2S hsync
S/PDIF Audio Frame vsync ck
Packetizer Composer
Audio In GPAUD ophytclk
PHY
DMA PHY
Test IF
Audio Sampler Test I/F
HDMI
I2C/DDC DDC
I2C
Master MUX DDC
Register
AMBA APB Bank
Control
CEC CEC
CEC
Controller
Configuration HPD
and Control HPD
rstz clk sfrhdcp
HDCP13TCTRL
KSV MEM MEM Access HDCP API

RAM Arbiter Interface
HDCP HDCP
DPK ROM* HDCP
Revocation Clocks & Timers Authentication
HDCP
Random HDCP I2C Register
HDCP
Generator Cipher Bank
DDC
data, clk, de
hsync
vsync
HDCP
Data Encryption
data, clk, de
hsync H13THDCPENCTRL
vsync
* The HDCP Device Private Keys are required when the “Enable Software Programmable Encrypted DPK
Embedded Storage” option in coreConsultant is not set (DWC_HDMI_HDCP_DPK_ROMLESS = 0).

2.9.1.1 Controller Unit

The DWC_hdmi_tx implements all the HDCP protocol defined by Digital Content Protection LLC
specification for the HDCP system.
The Controller Unit starts by authenticating the slave device through the I2C link after the system has been
properly configured and the RX detection command has been sent to the DWC_hdmi_tx.
The DWC_hdmi_tx must have its clock management block configured, and the HDCP configuration
variables should be set before the RX detection flag has been asserted. After authentication, the
DWC_hdmi_tx starts encrypting the TMDS channels and signals the slave device when it begins this
process. Periodically, the HDCP port is checked for integrity. This check ensures that the content is being
properly decrypted in the slave side.
2.9.1.2 OESS Window of Opportunity Generation

The HDCP controller is able to change the length of the HDCP window of opportunity in the OESS mode
through register 0x500a, a_oesswcfg.
Figure 2-21 OESS Window of Opportunity Programming
clk
dataen Signal polarity is active high
VSYNC Signal polarity is active high
wpesspffst[7:0] 8
OESS
OFFSET 0 32 .... 3 2 1 1
COUNTER
OESS
WINDOW
2.9.1.3 Random Number Generation Interface

This external interface is needed for a random number generation. You can bypass this interface by using
the configuration as described in Section 6.14.27 on page 458.
The random numbers should be in such a way that in 1 million power up cycles, there are no duplicate An
valuesa (as described in the HDCP Specification, page 53):
The bits of influence shall come from a source of reasonable variability or entropy. A reasonable level
of variability or entropy is established if, given 1,000,000 different power up cycles on the HDCP
transmitter logic such that the amount of time from power up to the initial authentication were
controlled precisely enough to eliminate any variability from the free running of the cipher before
initial authentication (such as, the number of pixel clocks applied to the cipher in State E0 remains
a. Pseudo-random values sent to HDCP Receiver/Repeater by the Transmitter.

unchanged between different tests), and the An values from the first authentication attempt after the
additional influence has been applied (using different content streams if this influence comes from
the content stream), the probability of there being any duplicates in this list of 1,000,000 An values
collected is less than 50%. This corresponds to about 40 (considering one million is about 2^20)
random bits out of the 64 (or equivalent if the bits are biased).
An (incomplete) list of sources of entropy might include:
a. A true Random Number Generator or analog noise source, even if a poor (biased) one
b. A pseudo-random number generator (PRNG), where the state is stored in non-volatile memory
after each use. (That is, every power on continues the sequence—it does not produce the same
sequence each time.) Flash memory or even disk is usable for this purpose as long as it is
reasonably secure from tampering. The hdcpRngCipher combined with tamper-resistant, non-
volatile memory is one such solution.
c. Timers, network statistics, error correction information, radio/cable television signals, disk seek
times, etc.
d. Since the random number An is not used for secret material, a reliable (not manipulated by the
user) calendar and time-of-day clock can be used as seed. For example, some broadcast content
sources may give reliable date and time information.
These “bits of influence” do not directly compose the 64-bit An value but directly influences its internal
generation inside the HDCP block (taken from the HDCP Cipher output function) as described in the HDCP
specification. These bits of influence that must be present at the random number generation interface must
follow the previous rules so that no duplicate An values are generated in 1 million power up cycles.
Options a and b (True Random Number Generators and pseudo-random number generators, respectively)
exist on the market and can be used as long as they follow the timing of Figure 2-22 on page 92. Other
options are described in item c listed previously. Or you can use LSFR with a random seed coming from an
unpredictable source.
You can also bypass this interface by using the configuration as described in Section 6.14 on page 438,
overriding the An value by software (the An bypass value must also follow the rule of no duplicate An
values in 1 million power-up cycles).
Figure 2-22 on page 92 depicts the HDCP DWC_hdmi_tx as an embedded random number generator with
timing interface. The clk in the diagram represents the TMDS clock.
Figure 2-22 Random Number Input Interface
clk
orndnumgenena
irndnum[3:0] x Random n Random n Random n Random n
2.9.1.4 DVI or HDMI

The DWC_hdmi_tx must be configured whether the slave device is HDMI capable or just DVI capable. This
information is received in advance after reading the slave’s EDID content.

2.9.1.5 Features 1.1

The DWC_hdmi_tx supports Features 1.1, although its application depends on the slave capabilities that are
read during the protocol initialization through the I2C link channel.
2.9.1.6 R Value Verification Method

The link integrity check method can be configured; the verification can be performed once every two
seconds or once on every 128th encrypted frame.
2.9.1.7 Bypass Encryption

After reading the EDID, the system might not require content protection where a bypass to the entire
encryption path is implemented.
2.9.1.8 I2C Fast Mode

The I2C master device can be programmed to support the fast mode protocol (400 kHz), although this
feature is dependent on the slave’s capabilities.
2.9.1.9 Enhanced Link Verification

The link verification method can support Enhanced Link Verification, once every 16 encrypted frames;
pixel 0 of Channel 0 is XORed with the current Pj key, and through I2C polling it is compared with the
slave’s resulting pixel.
2.9.1.10 Encryption Disable

The DWC_hdmi_tx can be forced to stop encryption through software request; this stall does not make the
link lose its authenticity.
2.9.1.11 Advance Cipher

The DWC_hdmi_tx supports the Advance Cipher; it is activated once the master and slave have both
enabled the Features 1.1.
2.9.1.12 Receiver or Repeater

As stated in the HDCP specification, the DWC_hdmi_tx supports connectivity with a Receiver or a
Repeater; in the Repeater's case, it is capable of receiving a KSV FIFO of 128 keys.
You can read the KSV from a repeater from hdcpreg_bksv0 to hdcpreg_bksv4. Use the KSV registers to read
KSV from downstream devices from the revocation/KSV memory and get the permission to access it
through the register a_ksvmemctrl (bits KSVMEMrequest and KSVMEMaccess).

2.9.1.13 Memory Requirements

This section discusses the external memory requirements for the HDMI Tx controller with an HDCP
Encryption Engine.
KSV MEM RAM – Revocation Memory

The DWC_hdmi_tx uses external memory to support repeaters. This section describes the memory
allocation, the revocation RAM interface, and two examples with the maximum and minimum memory
usage.
The external memory stores the values Bstatus (2 bytes), M0 (8 bytes), KSV List (5 bytes per KSV), VH, and a
Revocation List (5 bytes per KSV).
The DWC_hdmi_tx checks both lists to verify if there is any element in the KSV List that is black listed in the
Revocation List.
The size of the external memory is directly proportional to the number of downstream repeaters/receivers
that are attached to the repeater (maximum: 127), and to the number of KSVs in the Revocation List
(maximum: 1012).
The Revocation Period is the same as the SFR clock Period (must be 18 to 27 MHz), as illustrated in
Figure 2-23.
The HDCP revocation memory is obtained from the System Renewability Messages (SRM)
Note embedded on the source media, such as DVD. The HDCP revocation memory initial content
can also be found on the Digital-CP web site at http://www.digital-cp.com/resources in file
HDCP.SRM.
Figure 2-23 Revocation RAM Interface
Revoc Period
revocmemclk
revocmemaddress[12:0] x 14‘h0000 x 14‘h000 x
revocmemwen
revocmemcs
revocmemdataout[7:0] x valid
revocmemdatain[7:0] x valid x
Data is sampled at this clock edge

The revocmemclk signal defined in Figure 2-23 is the same as the SFR clock signal that is provided to the
DWC_hdmi_tx. For example, to support the maximum number of KSVs in the Revocation List, the external
memory is (10 + 127 * 5 + 20 + 2 + 1012 * 5) ~ 5.8 Kbytes.
In Figure 2-23, although the revocemclk clock is provided to the revocation memory, the revocation
memory is essentially an asynchronous read memory, and it does not work as a synchronous memory by
default.
To support a synchronous KSV memory, perform read access in the way described in the following table.
Table 2-17 Read access for Synchronous KSV Memory
Address Data Read access operation
addr 1 data 1 Read addr 1 and discard the data
addr 2 data 2 Read addr 2 to get data1
addr 3 data 3 Read addr 3 to get data2
... ... ...
addr n-1 data n-1 Read addr (n-1) to get data (n-2)
addr n data n Read addr n to get data (n-1)
... ... Read addr n to get data n
Hence, you must perform one extra read operation to get a full list of n positions from a synchronous KSV
memory, while write access can be performed on any position.

Table 2-18 provides the address mapping for System Renewability Messages (SRM) and for the Revocation
List exchange with the HDCP encryption engine.
Table 2-18 Address Mapping for Maximum Memory Allocation
SRM / Revocation
Address in Memory Address Mapping to Registers Bit Location mapping
13'h0000 0x5020 Bstatus[7:0]
13'h0001 0x5021 Bstatus[15:8]
13'h0002 0x5022 M0value[7:0]
... ... ...
13'h0009 0x5029 M0value[63:56]
13'h000A 0x502A KSV_LIST_1[7:0]
... ... ...
13'h000E 0x502E KSV_LIST_1[39:32]
13'h00036 ... ...
... ... ...
13'h0280 0x52A0 KSV_LIST_127[7:0]
... ... ...
13'h0284 0x52A4 KSV_LIST_127[39:32]

SRM
13'h0285 0x52A5 VH0[7:0]
... ... ...
13'h0288 0x52A8 VH0[31:24]
13'h0289 0x52A9 VH1[7:0]
... ... ...
13'h028C 0x52AC VH1[31:24]
13'h028D 0x52AD VH2[7:0]
... ... ...
13'h0290 0x52B0 VH2[31:24]
13'h0291 0x52B1 VH3[7:0]
... ... ...
13'h0294 0x52B4 VH3[31:24]
13'h0295 0x52B5 VH4[7:0]

Table 2-18 Address Mapping for Maximum Memory Allocation (Continued)
SRM / Revocation
... ... ...

SRM
13'h0298 0x52B8 VH4[31:24]
13'h0299 0x52B9 REVOC_LIST_SIZE[7:0]

Revocation List Size
13'h029A 0x52BA REVOC_LIST_SIZE[15:8]
13'h029B 0x52BB REVOC_KSV_0[7:0]
... ... ...
13'h029F 0x52BF REVOC_KSV_0[39:32]
... ... ... Revocation List
13'h165A 0x667A REVOC_KSV_1011[7:0]
... ... ...
13'h165E 0x667E REVOC_KSV_1011[39:32]
You can decrease the size of the memory by using a system that supports lesser repeaters and lesser KSVs in
the Revocation List.
For example, to a system that supports five repeaters and 250 KSVs in the Revocation List, the external
memory needs to have a size of (2+8+5*5+20+2+250*5) ~ 1.3 Kbytes. Alternatively, with the same number of
repeaters supported and without the Revocation List, the external memory needs to have a size of
(2+8+5*5+20+2)= 57 bytes.
Table 2-19 on page 98 provides the address mapping for System Renewability Messages (SRM) and for the
Revocation List exchange with the HDCP encryption engine for a system that supports five Repeaters and N
KSVs in the Revocation List.
The first VH byte address is always next to the last KSV address. The first REVOC_KSV byte
Note address is always 13'h029B, and the REVOC_LIST_SIZE[7:0] address is always 13'h0299.

Table 2-19 Address Mapping for Minimum Memory Allocation
SRM / Revocation
13'h0000 0x5020 Bstatus[7:0]
13'h0001 0x5021 Bstatus[15:8]
13'h0002 0x5022 M0value[7:0]
... ... ...
13'h0009 0x5029 M0value[63:56]
13'h000A 0x502A KSV_LIST_1[7:0]
... ... ...
13'h000E 0x502E KSV_LIST_1[39:32]
... ... ...
13'h001E 0x503E KSV_LIST_5[7:0]
... ... ...
13'h0022 0x5044 KSV_LIST_5[39:32]
13'h0023 0x5043 VH0[7:0]
... ... ... SRM
13'h0026 0x5046 VH0[31:24]
13'h0027 0x5047 VH1[7:0]
... ... ...
13'h002A 0x504A VH1[31:24]
13'h002B 0x504B VH2[7:0]
... ... ...
13'h002E 0x504E VH2[31:24]
13'h002F 0x504F VH3[7:0]
... ... ...
13'h0032 0x5052 VH3[31:24]
13'h0033 0x5053 VH4[7:0]
... ... ...
13'h0036 0x5056 VH4[31:24]

Table 2-19 Address Mapping for Minimum Memory Allocation (Continued)
SRM / Revocation
13'h0299 0x52B9 REVOC_LIST_SIZE[7:0]

Revocation List Size
13'h029A 0x52BA REVOC_LIST_SIZE[15:8]
13'h029B 0x52BB REVOC_KSV_0[7:0]
... ... ...
13'h029F 0x52BF REVOC_KSV_0[39:32]
... ... ... Revocation List
(Nr*5)h + 13'h029B (Nr*5)h + 13'h029B +13'h0020 REVOC_KSV_Nr[7:0]
... ... ...
(Nr*5)h + 13'h029B + 4 (Nr*5)h + 13'h029B + 4 + 13'h0020 REVOC_KSV_Nr[39:32]
Note In the table, Nr = N-1; and (Nr*5)h is the hexadecimal conversion for Nr * 5.
KEY ROM DEV – Device Private Keys ROM

This memory interface only exists when the DWC_HDMI_HDCP_DPK_ROMLESS is not set. This memory
is used to store the Device Private Keys (DPK). It is usually an OTP ROM, internal to the SoC.
Note It is very important to make sure that is not possible to read this memory once programmed.
Only the DWC_hdmi_tx can have a read access to it.
The DWC_hdmi_tx includes two options for this memory interface: a 56-bit memory interface or an 8-bit
memory interface.
56-Bit HDCP DPK Memory Interface

The odpkclk signal defined in Figure 2-25 on page 100 is the same as the SFR clock signal that is provided to
the DWC_hdmi_tx. The size is 41 words of 56 bits, 287 bytes. The Intclk period is the same as the SFR clock
period (which must be 18 to 27 MHz). This interface is included when the following hardware configuration
parameters are set:
■ “HDCP Support” option in coreConsultant is enabled (HDCP = 1)
■ “Enable DPK Memory 8-Bit Data Interface” option in coreConsultant is disabled
(DWC_HDMI_HDCP_DPK_8BIT = 0)

Figure 2-24 56-Bit External HDCP Keys
D Q Read
odpkreq
async logic
Q odpkaccess
HDMI Address
D Q
odpkaddr
Q
Data External
Q D
idpkdatain HDCP Keys
Q idpkack
odpkclk
Figure 2-25 56-bit Device Private Keys ROM Interface Timing

Intclk Period
odpkclk
odpkaccess
odpkreq
odpkack
odpkaddr[5:0] x 6‘h00 6‘h01 6‘h02
idpkdatain[55:0] x datakey0 datakey1 datakey2
The test DPKs are placed in the DPK memory of the DWC_hdmi_tx verification environment as follows
(note that DWC_hdmi_tx has the transmitter1 and transmitter2 DPKs placed in the ROM memory and each
set occupies 41 positions of 56 bit):
In a production environment, ROM memory must be filled with production DPKs. Otherwise,
Note the system does not work with other Receiver or Repeater devices. Each device must have its
own secret non-sharable DPKs.
To receive the DPKs, sign the HDCP agreement and purchase it from Digital Content
Protection LLC (DCP) (http://www.digital-cp.com/).
Place the received secret DPKs and KSV from DCP the way the test DPKs are placed, as
described previously. Typically, DCP sends one set of DPKs and the KSV; you should place
them on the 41 positions of 56 bits of the DPK ROM.

Table 2-20 HDCP DPK 56-bit Memory Mapping
Example value (Test key)

Offset Size Description (Replace them with your own Device Private Keys)
0 56-bit KSV 0x0000b70361f714
1 56-bit KEY #1 0x4da4588f131e69
2 56-bit KEY #2 0x1f823558e65009
3 56-bit KEY #3 0x8a6a47abb9980d
4 56-bit KEY #4 0xf3181b52cbc5ca
5 56-bit KEY #5 0xfb147f6896d8b4
6 56-bit KEY #6 0xe08bc978488f81
7 56-bit KEY #7 0xa0d064c8112c41
8 56-bit KEY #8 0xb39d5a28242044
9 56-bit KEY #9 0xb928b2bdad566b
10 56-bit KEY #10 0x91a47b4a6ce4f6
11 56-bit KEY #11 0x5600f8205e9d58
12 56-bit KEY #12 0x8c7fb706ee3fa0
13 56-bit KEY #13 0xc02d8c9d7cbc28
14 56-bit KEY #14 0x561261e54b9f05
15 56-bit KEY #15 0x74f0de8ccac1cb
16 56-bit KEY #16 0x3bb8f60efcdb6a
17 56-bit KEY #17 0xa02bbb16b22fd7
18 56-bit KEY #18 0x482f8e46785498
19 56-bit KEY #19 0x66ae2562274738
20 56-bit KEY #20 0x3d4952a323ddf2
21 56-bit KEY #21 0xe2d231767b3a54
22 56-bit KEY #22 0x4d581aede66125
23 56-bit KEY #23 0x326082bf7b22f7
24 56-bit KEY #24 0xf61b463530ce6b
25 56-bit KEY #25 0x360409f0d7976b
26 56-bit KEY #26 0xa1e105618d49f9
27 56-bit KEY #27 0xc98e9dd1053406
28 56-bit KEY #28 0x20c36794426190
29 56-bit KEY #29 0x964451ceac4fc3
30 56-bit KEY #30 0x3e904504e18c8a

Table 2-20 HDCP DPK 56-bit Memory Mapping (Continued)

31 56-bit KEY #31 0x290010579c2dfc
32 56-bit KEY #32 0xd7943b69e5b180
33 56-bit KEY #33 0x54c7ea5bdd7b43
34 56-bit KEY #34 0x74fb5887c790ba
35 56-bit KEY #35 0x935cfa364e1de0
36 56-bit KEY #36 0x03075e159a11ae
37 56-bit KEY #37 0x05d3408a78fb01
38 56-bit KEY #38 0x0059a5d7a04db3
39 56-bit KEY #39 0x373b634a2c9e40
40 56-bit KEY #40 0x2573bbb4562041
8-Bit HDCP DKP Memory Interface

The DWC_hdmi_tx controller used the HDCP interface to access the HDCP keys stored in an external
memory, as illustrated in Figure 2-26. The size is 289 words of 8 bits, 289 bytes. This interface is included
when the following hardware configuration parameters are set:
■ “HDCP Support” option in coreConsultant is enabled (HDCP = 1)
■ “Enable DPK Memory 8-Bit Data Interface” option in coreConsultant is enabled
(DWC_HDMI_HDCP_DPK_8BIT = 1)
Figure 2-26 8-Bit External HDCP Keys
D Q Read
odpkmemreq
async logic
HDMI Address
D Q
odpkmemaddr
Q
Data External
Q D
idpkmemdata HDCP Keys
Q
odpkclk
The HDCP interface requires only three signals: two output signals (odpkmemreq, odpkmemaddr to the
memory) and one input signal (idpkmemdata from the memory). Figure 2-27 shows the expected timing
behavior for the 8-bit memory interface (maximum frequency is 27 MHz). For more information about these
signals, refer to sections 5.10 on page 145 and 5.11 on page 148.

Figure 2-27 8-bit Device Private Keys ROM Interface timing
odpkclk
odpkmemreq
odpkmemaddr [8:0] valid
idpkmemdatai[7:0] valid
The HDCP DPK mapping into the external memory is defined in Table 2-21.
Table 2-21 HDCP DPK 8-bit Memory Mapping

0 8-bit Reserved
1 8-bit KSV[7:0] 0x14
2 8-bit KSV[15:8] 0xF7
3 8-bit KSV[23:16] 0x61
4 8-bit KSV[31:24] 0x03
5 8-bit KSV[39:32] 0xB7
6 8-bit Reserved
7 8-bit Reserved
8 8-bit Reserved
9 8-bit KEY#1[7:0] 0x69
10 8-bit KEY#1[15:8] 0x1e
11 8-bit KEY#1[23:16] 0x13
12 8-bit KEY#1[31:24] 0x8f
13 8-bit KEY#1[39:32] 0x58
14 8-bit KEY#1[47:40] 0xa4
15 8-bit KEY#1[55:48] 0x4d
... 8-bit ... ...
... 8-bit ... ...
... 8-bit ... ...
282 8-bit KEY#40[7:0] 0x41

Table 2-21 HDCP DPK 8-bit Memory Mapping (Continued)

283 8-bit KEY#40[15:8] 0x20
284 8-bit KEY#40[23:16] 0x56
285 8-bit KEY#40[31:24] 0xb4
286 8-bit KEY#40[39:32] 0xbb
287 8-bit KEY#40[47:40] 0x73
288 8-bit KEY#40[55:48] 0x25
Figure 2-28 Color Configuration When Sending Unecrypted Video Data

2.9.2 HDCP 2.2

The current HDMI 2.0b specification mandates the use of an HDCP 1.4 encryption system; however, it does
not limit the usage of other encryption methods such as HDCP 2.2. The HDCP 2.2 specification includes a
more powerful authentication protocol and a locality check that ensures the sink and source are close
together. HDCP 2.2 is not backward compatible with HDCP 1.4, which means that both protection systems
must co-exist.
The DWC_hdmi_tx controller provides support for an external HDCP 2.2 interface, allowing the
pre-selection of a Synopsys ESM 2.2 wrapper or an External (third party) HDCP 2.2 encryption engine.
2.10 AMBA APB 3.0 Slave Interface

The system interface (the interface that connects to the processor bus) is an AMBA APB 3.0 slave interface.
The AMBA APB slave interface module is compatible with the AMBA 3 APB Protocol Specification, revision
1.0. The APB slave interface is used in the DWC_hdmi_tx for register configuration. According to the APB
specification, all signal transitions are only related to the rising edge of the clock to enable the integration of
APB peripherals easily into any design flow. Every transfer takes at least two cycles. This interface supports
write and read transactions with wait cycles, which allow transposition to internal registers’ clock domain.
2.11 HDMI Tx PHY Support

The DWC_hdmi_tx supports Synopsys and non-Synopsys HDMI Tx PHYs. To enable your Synopsys PHY
deliverable, you must set the HDMITX_PHY_PATH and HDMITX_PHY_LIBPATH environment variables.
For example:
% setenv HDMITX_PHY_PATH /u/hdmi_phys/tsmc_040lp_hdmi_tx_14_phy_1.0a
% setenv HDMITX_PHY_LIBNAME /u/hdmi_phys/tsmc_040lp_hdmi_tx_14_phy_1.0a/lib/
hdmi_tx_phy_ss1p08v125c.lib
If you want to use a non-Synopsys PHY, you must set the PHY_EXTERNAL configuration parameter to
True (1).

2.12 E-DID/HDCP/SCDC I2C E-DDC Interface

The E-DDC channel is a dedicated I2C master interface that allows the read of a Sink E-EDID based on
system needs. Through this interface, it is possible to access the Sink EDID and the SCDC structure in an
HDMI 2.0 subsystem.
The I2C master included in DWC_hdmi_tx complies with the version 2.1 of the I2C Bus Specification and
can be accessed through the APB interface starting at address 0x7E00.
The following I2C operations are provided:
■ Single data byte write
■ Single data byte read
■ Sequential data byte read (8 bytes)
■ Single data byte extended read
■ Sequential data byte extended read (8 bytes)
■ SCDC update read
■ SCDC read request detection
■ SCDC polling mechanism
■ Bus Clear mechanism
The SCDC operations are only present if the DWC_HDMI_TX_20 configuration parameter is enabled.
The SCDC read request detection operates by detecting when a device external to DWC_hdmi_tx drives the
SDA line low. This detection functions correctly as long as the DWC_hdmi_tx I2C master is the only one
driving the I2C DDC bus.
2.12.1 I2C Master Interface Normal Mode

This operation implements a single read or write operation using the Special Function Register
configuration. The I2C data transfer protocol used is the 7-bit addressed, as defined in Section 9 of the
I2C-bus Specification, version 2.1.
Figure 2-29 Data Write Transaction

_ _
S slaveaddr[6:0] W A addr[7:0] A datao[7:0] A/A PA/A
Legend:
Transaction from master to slave. _
A – Acknowledge (sdao low)
A – not Acknowledge (sdao high)
Transaction from slave to master.
S – Start condition
_
P – Stop condition
W – Write indication

Figure 2-30 Data Read Transaction

_ _ _
S slaveaddr[6:0] W A addr[7:0] A/A Sr slaveaddr[6:0] R A datai[7:0] A P
Legend:
Transaction from master to slave. A
_ – Acknowledge (sdao low)
Transaction from slave to master. S – Start condition
Sr – Repeated start condition
P
_ – Stop condition
R – Read indication
The data read using the sequential operation is stored in the i2cm_read_buff0 to i2cm_read_buff7 registers.
The data read from at I2C register address “add” is stored in the i2cm_read_buff0 register.
Figure 2-31 Data Read Sequential Transactions
_ _ _
S slaveaddr[6:0] W A addr[7:0] A/A Sr slaveaddr[6:0] R A datai[7:0] A P
Legend:
8 * (bytes + ACK)
Transaction from master to slave. A – Acknowledge
_ (sdao low)
Transaction from slave to master. S – Start condition
P – Stop
_ condition
2.12.2 I2C Master Interface Extended Read Mode

This I2C extended read mode operation implements a segment pointer-based read operation using the
Special Register configuration.
Figure 2-32 Extended Data Read Operation

_ _
S segaddr[6:0] W X segpointer[7:0] X Sr slaveaddr[6:0] W A addr[7:0] A/A Sr slaveaddr[6:0] R A datai[7:0] A P
Legend:
Transaction from master to slave.
A
S
_ – Start condition
X – Don't care

The data read using the sequential operation is stored in the i2cm_read_buff0 to i2cm_read_buff7 registers.
The data read from at I2C register address “addr” is stored in the i2cm_read_buff0 register.
Figure 2-33 Extended Data Sequential Read Operation

_ _
S segaddr[6:0] W X segpointer[7:0] X Sr slaveaddr[6:0] W A addr[7:0] A/A Sr slaveaddr[6:0] R A datai[7:0] A P
Legend:
Transaction from master to slave. 8 * (bytes + ACK)
A
S
_ – Start condition
X – Don't care
2.12.3 I2C Master Interface SCDC Read Update

The data read using the SCDC read update is stored in the i2cm_scdc_update0 and i2cm_scdc_update1
registers.
Figure 2-34 SCDC Update Read
_
Slave Address = 0x54 R/W = 1 Update_0 Update_1
S (7 Bits) (Read) A (8 Bits) A (8 Bits) /A P
Legend:
From Source (Master) to Sink (Slave) A – Acknowledge
_ (sdao low)
/A – not Acknowledge (sdao high)
From Sink (Slave) to Source (Master) S – Start condition

2.12.4 I2C Clock Configuration

The following *CNT registers must be set before any I2C bus transaction can take place to ensure proper I/O
timing. The *CNT registers are:
■ *_I2CM_SS_SCL_HCNT
■ *_I2CM_SS_SCL_LCNT
■ *_I2CM_FS_SCL_HCNT
■ *_I2CM_FS_SCL_LCNT
Setting the *_LCNT registers, configures the number of SFR_CLKs that are required for setting the low time
of the SCL clock in each speed mode. For more information about these registers, refer to
“PHYConfiguration Registers” on page 348 and “EDDC Registers” on page 489.
Setting the *_HCNT* registers, configures the number of IC_CLKs that are required for setting the high time
of the SCL clock in each speed mode.
Setting the registers to the correct value is described as follows. The equation to calculate the proper number
of SFR_CLKs required for setting the proper SCL clocks high and low times is as follows:
IC_xCNT = (ROUNDUP(MIN_SCL_xxxtime*SFRFREQ,0))
ROUNDUP is an explicit Microsoft Excel® function call that is used to roundup the results of the division to
an integer.
Table 2-22 Minimum High and Minimum Low @100 kbps
MIN_SCL_*time Variable Specification Value Compliance Valuea

MIN_SCL_HIGHtime 4000 ns 4500 ns
MIN_SCL_LOWtime 4700 ns 5200 ns
a. The values included in this column are used in Synopsys HDMI compliance testing of
the DWC_hdmi_tx controller. It is strongly recommended that you use these values to
avoid issues with existing compliance test equipment.
Example 2-1 SFR_CLK Frequency Example 1

SFR Clock Frequency (Hz) = SFRFREQ
SFRFREQ = 27 MHz
I2Cmode = fast, 400 kbit/s
MIN_SCL_HIGHtime = 600 ns.
MIN_SCL_LOWtime = 1300 ns.
IC_xCNT = (ROUNDUP(MIN_SCL_HIGH_LOWtime*SFRFREQ,0))
IC_HCNT = (ROUNDUP(600 ns * 27 MHz,0))
IC_HCNTSCL PERIOD = 17
IC_LCNT = (ROUNDUP(1300 ns * 27 MHz,0))

IC_LCNTSCL PERIOD = 36

Example 2-2 SFR_CLK Frequency Example 2

SFR Clock Frequency (Hz) = SFRFREQ
SFRFREQ = 27 MHz
I2Cmode = standard, 100 kbit/s
MIN_SCL_HIGHtime = 4000 ns.
MIN_SCL_LOWtime = 4700 ns.
IC_xCNT = (ROUNDUP(MIN_SCL_HIGH_LOWtime*SFRFREQ,0))
IC_HCNT = (ROUNDUP(4000 ns * 27 MHz,0))
IC_HCNTSCL PERIOD = 108
IC_LCNT = (ROUNDUP(4700 ns * 27 MHz,0))

IC_LCNTSCL PERIOD = 127
The minimum value for *_LCNT is 8 and the minimum *_HCNT is 6. Also, because of the digital filtering on
the receiver, the actual SCL high and low times are slightly longer than the specified count value 8.
The final values calculated in the equation for IC_*_HCNT and IC_*_LCNT (where * represents SS or FS) are
decimal values. For programming the actual registers, the values must be converted to hexadecimal. The
16-bit range on these registers allows a wide range of input clock frequencies to be used.
By default, the *CNT registers are configured to work with the SFR clock at 27 MHz. The SS*CNT and
FS*CNT registers are required to set the SFR clock frequency.

2.13 CEC Hardware Engine

Consumer Electronics Control (CEC) is a protocol that provides high-level control functions between all of
the various audiovisual products in a user’s environment. It is an optional feature in the HDMI
Specification. It uses only one bidirectional line for transmission and reception.
All transactions on the CEC line consist of an initiator and one or more followers. The initiator is responsible
for sending the message structure and the data. The follower is the recipient of any data and is responsible
for setting any acknowledgement bits.
Figure 2-35 CEC Engine Simplified Block Diagram
ocecout
icecin CEC
Engine
Register configuration
Bank
There are two operation modes for a CEC controller.

■ Initiator Mode
In this mode, the CEC controller sends messages out and waits for a follower to feedback. The CEC
controller works in this mode when it starts to send a frame. After the transmission is done, it
automatically returns to the follower mode (no software control involved).
■ Follower Mode
In this mode, the CEC controller receives messages and feeds back the initiator with appropriate
signals. The CEC controller always works in the follower mode whenever it is not transmitting any
data.
For correct CEC controller interface operation, initial reset is required in order to set internal registers to a
known state. After this reset, the interface is in an IDLE state, waiting for a read or write request coming
from the register configuration.
When you apply a software reset to CEC using the register mc_swrstzreq, set the value of the
Note bit cecclk_disable of the register mc_clkdis to 1, 0, and then 1 again.

A specific CEC API is provided that implements all necessary low-level register configuration to send and
receive CEC messages. For more information, see the CEC API documentation.
The CEC engine registers base address is 0x7D00. For more information about these registers, refer to
Section 6.16 on page 478. For more information about CEC, refer to the Consumer Electronics Control (CEC)
Application Note.

3
Parameter Descriptions
This chapter details all the configuration parameters. You can use the coreConsultant GUI configuration
reports to determine the complete configuration state of the core. Some expressions might refer to TCL
functions or procedures (sometimes identified as <functionof>) that coreConsultant uses to make
calculations. The exact formula used by these TCL functions is not provided in this chapter. However, when
you configure the core in coreConsultant, all TCL functions and parameters are evaluated completely; and
the resulting values are displayed where appropriate in the coreConsultant GUI reports.
These tables define all of the user configuration options for this component.
■ Interfaces on page 114
■ Feature Definition on page 115
■ FPGA Prototyping Definition on page 119
■ Metastability Option on page 120

Parameter Descriptions HDMI Transmitter Controller Databook
3.1 Interfaces Parameters
Table 3-1 Interfaces Parameters
Label Description
Audio Interface Selects the desired DWC_hdmi_tx audio Interface(s):

1 - I2S interface
2 - S/PDIF interface
4 - I2S and SPDIF audio interfaces (designated as DOUBLE interface)
6 - Generic Purpose (GP) Audio (AUD) interface
7 - Combines both the GP Audio and the I2S interfaces (designated as GDOUBLE
interface)
8 - AHB DMA Audio
Values:
■ I2S (1)
■ SPDIF (2)
■ DOUBLE (4)
■ GPAUD (6)
■ GDOUBLE (7)
■ AHBAUDDMA (8)
Default Value: I2S
Enabled: Always
Parameter Name: AUDIO_IF
AHB Audio DMA FIFO Address This parameter sets the Audio DMA FIFO address width (number of bits). The FIFO
Width size depends on this parameter because FIFO_size = 2 ^
HDMI_TX_AHBDMAAUD_FIFO_ADDRWITH.
Values: 7, 8, 9, 10
Default Value: 7
Enabled: ((AUDIO_IF == 8) ? 1 : 0)
Parameter Name: HDMI_TX_AHBDMAAUD_FIFO_ADDRWITH
Bypass SPDIF Data Recovery This parameter allows the S/PDIF Data Recovery Unit (DRU) to be bypassed. This
Unit (DRU) implies that ispdifclk must always be at 128xfs and that ispdifdata must be a BMC
stream synchronous with ispdifclk.
Values: 0, 1
Default Value: 0
Enabled: ((AUDIO_IF == 2 || AUDIO_IF == 4) ? 1 : 0)
Parameter Name: HTX_SPDIFBYPDRU
Support for HBR over SPDIF This parameter allows for High Bit Rate (HBR) audio reception through the existing
S/PDIF interface.
Values: 0, 1
Default Value: 0
Enabled: ((AUDIO_IF == 2 || AUDIO_IF == 4) ? 1 : 0)
Parameter Name: HBR_ON_SPDIF

HDMI Transmitter Controller Databook Parameter Descriptions
3.2 Feature Definition Parameters
Table 3-2 Feature Definition Parameters
Label Description
Support HDMI 2.0 Features When selected, the DWC_hdmi_tx includes the HDMI 2.0 specification features.
License Dependencies: To use this feature, you must have both DWC-HDMI-13-
TX and DWC-HDMI-20-TX-HDCP licenses.
Values: 0, 1
Default Value: 0
Enabled: Always
Parameter Name: DWC_HDMI_TX_20
Support HDMI 1.4 Features When selected, the DWC_hdmi_tx includes the HDMI 1.4b specification features.
License Dependencies: To use this feature, you must have both DWC-HDMI-13-
TX and DWC-HDMI-14-TX licenses.
Values: 0, 1
Default Value: DWC_HDMI_TX_20==1
Enabled: DWC_HDMI_TX_20==0
Parameter Name: DWC_HDMI_TX_14
Support HDCP This parameter enables High-bandwidth Digital Content Protection (HDCP) system
support:
1: True - HDCP hardware present in DWC_hdmi_tx using dedicated port
connections
0: False - HDCP hardware not present in DWC_hdmi_tx (dedicated ports are
automatically removed)
License Dependencies: To generate a DWC_hdmi_tx core with HDCP capabilities,
you must have a DWC-HDMI-13-TX-HDCP or a DWC-HDMI-HDCP license.
Values: 0, 1
Default Value: 0
Enabled: Always
Parameter Name: HDCP
Enable SHA-1 Calculation by When set to True (1), this parameter enables software SHA-1 Calculation.
Software 1: True - SHA-1 Calculated by software;
0: False - SHA-1 Calculated by hardware;
For more information refer to Section 3.2.4 in the DesignWare Cores HDMI
Transmitter Controller User Guide.
License Dependencies: This feature is only available if you have an HDCP license.
Values: 0, 1
Default Value: 0
Enabled: ((HDCP==1) ? 1 : 0)
Parameter Name: HTX_HDCP_SW_SHA1CALC

Table 3-2 Feature Definition Parameters (Continued)
Label Description
Enable Software When set to True (1), this parameter enables software programmable encrypted
Programmable Encrypted DPK DPK embedded storage. No external OTP ROM/NVM is required.
Embedded Storage 1: True - Encrypted DPK programmed by software; no external OTP ROM/NVM
memory
0: False - External OTP ROM/NVM memory with pre-programmed DPK
For information on how to configure these encrypted DPK, refer to Step 6 in Section
3.2.4 in the DesignWare Cores HDMI Transmitter Controller User Guide.
Values: 0, 1
Default Value: 0
Enabled: ((HDCP==1) ? 1 : 0)
Parameter Name: DWC_HDMI_HDCP_DPK_ROMLESS
Enable DPK Memory 8-Bit When set to True (1), this parameter supports the external ROM/NVM DPK memory
Data Interface 8-bit data interface.
1: True - External ROM/NVM DPK memory 8-bit data interface available
0: False - External ROM/NVM DPK memory 56-bit data interface available
Values: 0, 1
Default Value: 0
Enabled: ((HDCP==1&&DWC_HDMI_HDCP_DPK_ROMLESS==0) ? 1 : 0)
Parameter Name: DWC_HDMI_HDCP_DPK_8BIT
Support Color Space When selected, this parameter enables CSC support:
Converter 1: True - Hardware instance of color space converter and corresponding filters
present at DWC_hdmi_tx
0: False - Not available at DWC_hdmi_tx (instance automatically removed from
hardware configuration)
Values: 0, 1
Default Value: 1
Enabled: Always
Parameter Name: CSC
Support Consumer Electronics When selected, this parameter enables CEC the interface:
Control 1: True - CEC hardware present in DWC_hdmi_tx using dedicated port connections
0: False - CEC hardware not present in DWC_hdmi_tx (dedicated ports
automatically removed)
Values: 0, 1
Default Value: 1
Enabled: Always
Parameter Name: CEC

Label Description
Support Internal Pixel When selected, this parameter enables the internal pixel repetition support:
Repetition 1: True - DWC_hdmi_tx has dedicated hardware to perform internal pixel repetition
0: False - DWC_hdmi_tx does not support internal pixel repetition
NOTE: If your input video stream (to DWC_hdmi_tx) is purely CEA-compliant, then
pixel repetition is already present at the video stream and you may not want this
internal pixel repetition feature.
Values: 0, 1
Default Value: 1
Enabled: Always
Parameter Name: DWC_HDMI_TX_INTPREPEN
Support For Custom PHY When enabled, the DWC_hdmi_tx uses a non-Synopsys, external PHY.
(Non-Synopsys) Note: To enable your Synopsys PHY deliverable, you must set the
HDMITX_PHY_PATH variable.
For example:
% setenv HDMITX_PHY_PATH /u/hdmi_phys/tsmc_040lp_hdmi_tx_14_phy_1.0a
% setenv HDMITX_PHY_LIBNAME
/u/hdmi_phys/tsmc_040lp_hdmi_tx_14_phy_1.0a/lib/hdmi_tx_phy_ss1p08v125c.lib
Values: 0, 1
Default Value: 0
Enabled: Always
Parameter Name: PHY_EXTERNAL
Support for Synopsys HEAC When enabled, the DWC_hdmi_tx uses the SNPS HEAC PHY:
PHY 1: True - Synopsys HEAC PHY hardware present at the DWC_hdmi_tx core using
dedicated port connections
0: False - No HEAC PHY hardware present at the DWC_hdmi_tx core
Note:
To enable your PHY deliverable, you must set the HDMITX_HEAC_PHY and
HDMITX_PHY_LIBNAME environment variables to the location of the PHY
behavioral models and PHY .lib files.
% setenv HDMITX_HEAC_PHY_PATH
/u/hdmi_phys/tsmc_040lp_hdmi_tx_14_heac_phy_1.0a
% setenv HDMITX_HEAC_PHY_LIBNAME
/u/hdmi_phys/tsmc_040lp_hdmi_tx_14_heac_phy_1.0a/lib/hdmi_heac_phy_tt1p1v2
5c.lib
Values: 0, 1
Default Value: 0
Enabled: ((PHY_EXTERNAL == 1) ? 0 : 1)
Parameter Name: HDMI_HEAC_PHY_EN

Label Description
HDCP Version This parameter selects the HDCP versions supported by the core:
HDCP 1.4 (0): Synopsys HDCP 1.4
HDCP 1.4 and External HDCP 2.2 (2): This parameter allows you to select the type
of External HDCP 2.2.
The HDCP 2.2 feature is not supported when an HDMI 1.3 TX PHY is selected.
License Dependencies:
This feature is only available if you have an HDCP license.
Values:
■ HDCP1.4 (0)
■ HDCP1.4 and HDCP 2.2 External Type (2)
Default Value: HDCP1.4
Enabled: HDCP == 1
Parameter Name: HTX_HDCP_TYPE
HDCP 2.2 Wrapper External This parameter allows you to select the type of External HDCP 2.2
Type NONE (0): No external HDCP 2.2 only DWC_hdmi_tx with external HDCP2.2
interface will be used.
ESM for HDCP2.2 (1): sim/hdcp_ext/DWC_hdmi_tx_hdcp_ellp.v will be used as
HDMITX+ESM for HDCP2.2 wrapper.
Note: If you set this parameter to ESM for HDCP2.2 (1), you must define the
HDMITX_HDCP22_EXTERNAL_PATH and
HDMITX_HDCP22_EXTERNAL_TBLIST environment variables.
For example:
% setenv HDMITX_HDCP22_EXTERNAL_PATH “<your Elliptic install
path>/elliptic/esm_heron_verilog.f”
% setenv HDMITX_HDCP22_EXTERNAL_TBLIST "esm_heron_verilog_tb.f"
License Dependencies: None
Values:
■ NONE (0)
■ ESM for HDCP2.2 (1)
Default Value: NONE
Enabled: HTX_HDCP_TYPE==2
Parameter Name: HTX_HDCP22_EXTERNAL_TYPE

3.3 FPGA Prototyping Definition Parameters
Table 3-3 FPGA Prototyping Definition Parameters
Label Description
Support for FPGA Prototyping When enabled, the prototyping environment is assembled and used for synthesis
and simulation. For more information, refer to the DesignWare Cores HDMI
Transmitter User Guide.
Values: 0, 1
Default Value: 0
Enabled: PHY_EXTERNAL == 1
Parameter Name: HDMITX_FPGA_SYNTHESIS
Support for Internal This parameter allows you to add Audio and Video Generators to the prototyping
Audio/Video Generators assembly.
Values: 0, 1
Default Value: 1
Enabled: HDMITX_FPGA_SYNTHESIS == 1
Parameter Name: FPGA_INTERNAL_AV_GENERATOR
HDCP Memories Location This parameter allows you to select the location of the HDCP memories in the
prototyping assembly:
EXTERNAL (1): External memories
INTERNAL (2): Internal memories
Values:
■ EXTERNAL (1)
■ INTERNAL (2)
Default Value: EXTERNAL
Enabled: HDMITX_FPGA_SYNTHESIS == 1 && HDCP == 1
Parameter Name: HDMITX_FPGA_HDCP_MEM

3.4 Metastability Option Parameters
Table 3-4 Metastability Option Parameters
Label Description
Number of Flop Stages in Number of synchronizing flip-flop stages in reset synchronizers:

Reset Synchronizers 2: Two-stage flop synchronization with both stages positive-edge capturing
3: Three-stage flop synchronization with all stages positive-edge capturing
4: Four-stage flop synchronization with all stages positive-edge capturing
Values: 2, 3, 4
Default Value: 2
Enabled: Always
Parameter Name: HDMIRSYNCDEPTH
Number of Flop Stages in Data Number of synchronizing flip-flop stages in data synchronizers:
Synchronizers 2: Two-stage flop synchronization with both stages positive-edge capturing
3: Three-stage flop synchronization with all stages positive-edge capturing
4: Four-stage flop synchronization with all stages positive-edge capturing
Values: 2, 3, 4
Default Value: 2
Enabled: Always
Parameter Name: HDMIDATASYNCDEPTH

4
Signal Interfaces
Chapter 5, “Signal Descriptions” provides detail descriptions of each signal. This chapter describes the
naming conventions and other details of the various interfaces.
The topics include:
■ “Naming and Description Conventions” on page 122
■ “Signal Interfaces” on page 123
❑ “Video Input Interface Signals” on page 123
❑ “Audio Input Interface Signals” on page 123
❑ “System and Slave Register Interface Signals” on page 123
❑ “E-DDC Interface Signals” on page 123
❑ “CEC Interface Signals” on page 124
❑ “HDCP 1.4 Encryption Engine Signals” on page 124
❑ “HDCP 2.2 Encryption Engine Interface Signals” on page 124
❑ “Scan Test Interface Signals” on page 124
❑ “HDMI Tx PHY Interface Signals” on page 124
❑ “HDMI 3-D TX PHY (PHY GEN 2) Interface Signals” on page 124
❑ “HDMI HEAC PHY Interface Signals” on page 124
❑ “HDMI-MHL TX PHY Interface Signals” on page 125
❑ “HDMI 2.0 TX PHY Interface Signals” on page 125
❑ “HDMI Tx External PHY Signals” on page 125

Signal Interfaces HDMI Transmitter Controller Databook
4.1 Naming and Description Conventions

This section provides conventions that are used for the DWC_hdmi_tx signal names and descriptions.
4.1.1 Signal Name

The signal name begins with the letter i when the signal is an input signal, with the letter o when the signal
is an output signal, and with the letters io when the signal is an I/O signal.
4.1.2 Signal Name Prefix

The signal name prefix indicates the interface to which the signal belongs.
4.1.3 Signal Name Description

The signal name description describes the function of each signal, and the type, that can be
■ Synchronous: The signal is asserted or deasserted with respect to a clock edge.
■ Asynchronous: The signal is not asserted or deasserted with respect to a clock edge.
■ Registered: The signal is captured (or launched) directly at the macro boundary with no intermediate
logic between the controller boundary and the capturing (or launching) flip-flop.
Figure 4-1 Synchronous and Asynchronous signals
Inputs Outputs
Synchronous Registered boundary Synchronous Registered boundary
input output
clk clk
Synchronous Non-Registered Synchronous Non-Registered
input output
clk clk
Asynchronous Asynchronous
input output

HDMI Transmitter Controller Databook Signal Interfaces
4.2 Signal Interfaces

The following are the interfaces of the DWC_hdmi_tx:
■ “Video Input Interface Signals”
■ “Audio Input Interface Signals” on page 123
■ “System and Slave Register Interface Signals” on page 123
■ “E-DDC Interface Signals” on page 123
■ “CEC Interface Signals” on page 124
■ “HDCP 1.4 Encryption Engine Signals” on page 124
■ “HDCP 2.2 Encryption Engine Interface Signals” on page 124
■ “Scan Test Interface Signals” on page 124
■ “HDMI Tx PHY Interface Signals” on page 124
■ “HDMI 3-D TX PHY (PHY GEN 2) Interface Signals” on page 124
■ “HDMI HEAC PHY Interface Signals” on page 124
■ “HDMI-MHL TX PHY Interface Signals” on page 125
■ “HDMI Tx External PHY Signals” on page 125
4.2.1 Video Input Interface Signals

The Video Input Interface signals include the basic signals like the pixel clock, data input, data enable,
horizontal, and vertical sync signals. Dependencies are always present in such signals.
4.2.2 Audio Input Interface Signals

The Audio Input Interface signals include the basic signals like the data pixel clock, audio data input, and
signals for data sample buses. These signals work on various interfaces like I2S, S/PDIF, and General Parallel
Audio (GPA) interfaces.
4.2.3 System and Slave Register Interface Signals

The system interface (the interface that connects to the processor bus) is an AMBA APB 3.0 slave interface.
The AMBA APB slave interface module is compatible with the AMBA 3 APB Protocol Specification,
revision 1.0.
The System and Slave Interface Signals include various clock signals, master interrupt signals, and master
and slave transfer signals.
4.2.4 E-DDC Interface Signals

To use the HDCP module, the isfrclk input clock must be 18 to 27 MHz for the HDCP timers to operate
correctly. These timers include the time-outs used for the authentication protocol, and for the I2C bus used
for DDC operation.

4.2.5 CEC Interface Signals

Use a 32.768 kHz clock to feed the icecclk input of the HDMI Tx controller. The main reason is the
optimization handled for this frequency regarding bit timing tolerances, and robustness to detect CEC line
errors.
The following are clarifications for the CEC bit-time recovery uncertainty:
Note
■ The CEC protocol uses one single line to transmit and receive data. The clock is not
transmitted.
■ On the CEC receiver side, to recover data an oversampling scheme at 30.5μs
(32.768 KHz) of the CEC line is used.
The sampling rate of 30.5µs represents a total uncertainty of ±1 CECCLK (2x30.5μs) = 71µs,
lower than maximum allowed per specification of 100µs.
4.2.6 HDCP 1.4 Encryption Engine Signals

To use the HDCP encryption engine module, the isfrclk input clock must be 18 to 27 MHz so that the HDCP
timers operate correctly. These timers include time-outs used for the authentication protocol and for the I2C
bus to handle DDC operations.
4.2.7 HDCP 2.2 Encryption Engine Interface Signals

To include an external HDCP 2.2 interface in your design (build your own or use a third-party HDCP 2.2
decryption engine), you must set the HTX_HDCP_TYPE parameter to EXT22 (2).
4.2.8 Scan Test Interface Signals

The Scan Test Interface Signals include the scan mode clock, scan test mode enable, and HDMI controller
scan chain input signals. The dependencies are always present.
4.2.9 HDMI Tx PHY Interface Signals

The HDMI Tx PHY Interface Signals include hot plug detect input, analog and digital power supply signals.
4.2.10 HDMI 3-D TX PHY (PHY GEN 2) Interface Signals

HDMI 3-D TX PHY (phy_gen2) Interface Signals include the analog power supply, reference resistors, and
TMDS differential line driver data output signals. The following signals are only written to the
DWC_hdmi_tx top-level interface when the controller is configured to use with the HDMI 3-D TX PHY.
4.2.11 HDMI HEAC PHY Interface Signals

The HDMI HEAC PHY Interface Signals include digital power supply, digital and analog ground, and
termination analog power supply signals. The following signals are only written to the DWC_hdmi_tx top-
level interface when the controller is configured to use the HDMI 3D TX PHY (phy_gen2) AND when the
HDMI_HEAC_PHY_EN hardware configuration option is set to True (1).

Note HEAC PHY is only available with the phy_gen2 interface.
4.2.12 HDMI-MHL TX PHY Interface Signals

HDMI-MHL TX PHY interface signals include the analog power supply, reference resistors, and TMDS
differential line driver data output signals. The following signals are only written to the DWC_hdmi_tx
top-level interface when the controller is configured to be used with the HDMI 3D TX PHY.
For more information about these signals, refer to the HDMI-MHL TX PHY databook.
4.2.13 HDMI 2.0 TX PHY Interface Signals

The HDMI 2.0 TX PHY interface is identical to the HDMI-MHL TX PHY.
For more information about the signals defined in the interface, refer to the HDMI 2.0 TX PHY databook.
4.2.14 HDMI Tx External PHY Signals

The HDMI Tx External PHY Interface Signals include the encoded data port, clock inputs, and a PHY
configuration interface. The following signals are only written to the DWC_hdmi_tx top-level interface
when the controller is configured for use with the External PHY when the “Support for Custom PHY (Non-
Synopsys)” option is set in coreConsultant (PHY_EXTERNAL = 1).
The signals that are described as optional in descriptions are not mandatory when the PHY configuration
and status pooling is done by other means.
The Synopsys HDMI Transmit API Low-Level Driver does not support non-Synopsys PHY.
The interruption mechanism set by registers PHY_STAT0, PHY_INT0, PHY_MASK0 and PHY_POL0 is
operational when the “Support for Custom PHY (Non-Synopsys)” option is set in coreConsultant
(PHY_EXTERNAL = 1), and the inputs iphyext_lock, iphyext_hpd and iphyext_rxsense are connected.
I2C Interface for PHY Configuration

An I2C interface is provided to be used for PHY configuration and status reading. This I2C implementation
has a 16-bit data interface (two data words) with the transmission structure shown here. This structure is
controlled by the “PHYConfiguration Registers” on page 348.

Figure 4-2 I2C Interface for PHY Configuration

Figure 4-3 shows the standard connection of the PHY I2C Master to an I2C bus.
Figure 4-3 Connection of External PHY I2C Master to I2C Bus
iphyext_i2c_sdain I2C SDA Line
ophyext_i2c_sdaout
DWC_hdmi_tx
iphyext_i2c_sclin I2C SCL Line
ophyext_i2c_sdout
JTAG Interface for PHY Configuration

DWC_hdmi_tx includes a JTAG Interface for PHY configuration, using direct register-to-pin assignment.
For more information, refer to “PHYConfiguration Registers” on page 348.


5
Signal Descriptions
This chapter details all possible I/O signals in the core. For configurable IP titles, your actual configuration
might not contain all of these signals.
Inputs are on the left of the signal diagrams; outputs are on the right.
For configurable IP titles, do not use this document to determine the exact I/O footprint of the
Note core. It is for reference purposes only.
When you configure the core in coreConsultant, you must access the I/O signals for your actual
configuration at workspace/report/IO.html or workspace/report/IO.xml after you have completed the
report creation activity. That report comes from the exact same source as this chapter but removes all the
I/O signals that are not in your actual configuration. This does not apply to non-configurable IP titles. In
addition, all parameter expressions are evaluated to actual values. Therefore, the widths might change
depending on your actual configuration.
Some expressions might refer to TCL functions or procedures (sometimes identified as <functionof>) that
coreConsultant uses to make calculations. The exact formula used by these TCL functions is not provided in
this chapter. However, when you configure the core in coreConsultant, all TCL functions and parameters
are evaluated completely; and the resulting values are displayed where appropriate in the coreConsultant
GUI reports.
The I/O signals are grouped as follows:
■ System and Slave Register Interface Signals on page 131
■ Video Input Interface Signals on page 133
■ I2S Interface Signals on page 134
■ S/PDIF Interface Signals on page 135
■ Generic Parallel Audio (GPA) Interface Signals on page 136
■ AHB Audio DMA Input Interface Signals on page 137
■ CEC Interface Signals on page 140
■ HDMI TX PHY Interface Signals on page 141
■ E-DDC Interface Signals on page 144
■ HDCP 1.4 Encryption Engine Interface Signals on page 145

Signal Descriptions HDMI Transmitter Controller Databook
■ HDCP 2.2 Encryption Engine Interface Signals on page 148

■ HDMI 3-D TX PHY (PHY GEN 2) Interface Signals on page 157
■ HDMI-MHL or HDMI 2.0 TX PHY Interface Signals on page 159
■ HDMI TX External PHY Signals on page 164
■ Scan Test Interface Signals on page 169
■ HDMI HEAC PHY Interface Signals on page 181

HDMI Transmitter Controller Databook Signal Descriptions
5.1 System and Slave Register Interface Signals
irstz - - oapbrdata
isfrclk - - oapbready
iapbclk -
iapbrstz -
iapbaddr - - ointerrupt
iapbsel -
iapbenable -
iapbwrite -
iapbwdata -
Table 5-1 System and Slave Register Interface Signals
Port Name I/O Description
irstz I Active low asynchronous, master reset input (minimum duration of 4

cycles of your slowest clock in the HDMI system).
Exists: Always
Active State: Low
Synchronous to: Asynchronous
Registered: No
isfrclk I Internal register configuration clock (must be in the range 18-27

MHz).
Exists: Always
Active State: N/A
Synchronous to: N/A
Registered: No
iapbclk I APB bus clock (APB:PCLK).

Exists: Always
Active State: N/A
Synchronous to: N/A
Registered: No
iapbrstz I APB bus asynchronous reset (APB:PRESETn). Not synchronized

inside the controller.
Exists: Always
Active State: Low
Registered: No
iapbaddr[15:0] I APB address bus (APB:PADDR).

Exists: Always
Active State: N/A
Synchronous to: iapbclk
Registered: No

Table 5-1 System and Slave Register Interface Signals (Continued)
iapbsel I APB Slave select signal (APB:PSEL).

Exists: Always
Active State: High
Registered: No
iapbenable I APB enable (APB:PENABLE).

Exists: Always
Active State: High
Registered: No
iapbwrite I APB write/read indication signal (APB:PWRITE).

Exists: Always
Active State: High
Registered: No
iapbwdata[7:0] I APB Write data bus (APB:PWDATA).

Exists: Always
Active State: N/A
Registered: No
oapbrdata[7:0] O APB Read data bus (APB:PRDATA).

Exists: Always
Active State: N/A
Registered: Yes
oapbready O APB Slave interface ready (APB:PREADY). The controller inserts

wait states per transfer.
Exists: Always
Active State: High
Registered: Yes
ointerrupt O Master interrupt signal.

Exists: Always
Active State: High
Synchronous to: isfrclk
Registered: No

5.2 Video Input Interface Signals
ipixelclk -
ivdata -
idataen -
ihsync -
ivsync -
Table 5-2 Video Input Interface Signals
ipixelclk I Data pixel clock.

Exists: Always
Active State: N/A
Synchronous to: N/A
Registered: No
ivdata[47:0] I Video data input.

Exists: Always
Active State: N/A
Synchronous to: ipixelclk
Registered: Yes
idataen I Video data enable. Signal polarity is configurable.

Exists: Always
Active State: N/A
Registered: Yes
ihsync I Video horizontal sync signal. Signal polarity is configurable.

Exists: Always
Active State: N/A
Registered: Yes
ivsync I Video vertical sync input. Signal polarity is configurable.

Exists: Always
Active State: N/A
Registered: Yes

5.3 I2S Interface Signals
ii2sclk -
ii2slrclk -
ii2sdata -
Table 5-3 I2S Interface Signals
ii2sclk I I2S bit clock.

Exists: I2SPORTS
Active State: N/A
Synchronous to: N/A
Registered: No
ii2slrclk I I2S word clock.

Exists: I2SPORTS
Active State: N/A
Synchronous to: ii2sclk
Registered: No
ii2sdata[3:0] I Audio data input. The following bits inputs audio data to sent in the
specified channels.
■ Bit 0 - Channel 1 and 2
Exists: I2SPORTS
Active State: N/A
Synchronous to: ii2sclk
Registered: Yes

5.4 S/PDIF Interface Signals
ispdifclk -
ispdifdata -
Table 5-4 S/PDIF Interface Signals
ispdifclk I S/PDIF audio input clock (DRU/HBR_ON_SPDIF dependent).

Exists: SPDIFPORTS
Active State: N/A
Synchronous to: N/A
Registered: No
ispdifdata[3:0] I S/PDIF digital audio input. The following bits inputs audio data to
sent in the specified channels.
NOTE: HBR only uses Bit 0
Exists: SPDIFPORTS
Active State: N/A
Synchronous to: ispdifclk
Registered: {(@HTX_SPDIFBYPDRU) ? "No" : "Yes"}

5.5 Generic Parallel Audio (GPA) Interface Signals
igpaclk - - ogpadatareq
igpavalid -
igpadata -
Table 5-5 Generic Parallel Audio (GPA) Interface Signals
igpaclk I System clock, used to capture the audio sample bus. It can be same
as the system bus clock, or any other clock above 4.096 MHz.
Exists: GPAUDPORTS
Active State: N/A
Synchronous to: N/A
Registered: No
igpavalid I Indicates when a valid sample is available at the igpadata input

interface.
Exists: GPAUDPORTS
Active State: High
Synchronous to: igpaclk
Registered: No
igpadata[28:0] I General Parallel audio data

■ [28] = B flag. Equals 1 if the Sub-packet contains the first frame in
a 192 frame IEC 60958 Channel Status block, otherwise 0.
■ [27] = P flag (IEC 60958 Parity)
■ [26] = C flag (IEC 60958 Channel Status)
■ [25] = U flag (IEC 60958 User bit)
■ [24] = V flag (IEC 60958 Validity)
■ [23:0] = Input data sample bus
Exists: GPAUDPORTS
Active State: N/A
Registered: No
ogpadatareq O Active when audio data is required.

Exists: GPAUDPORTS
Active State: High
Registered: No

5.6 AHB Audio DMA Input Interface Signals
idmahresetn - - odmahaddr
idmahclk - - odmahtrans
idmahrdata - - odmahsize
idmahresp - - odmahburst
idmahready - - odmahwdata
idmahgrant - - odmahwrite
- odmahlock
- odmahbusreq
Table 5-6 AHB Audio DMA Input Interface Signals
idmahresetn I AHB bus asynchronous reset (AHB:HRESETn). Not synchronized

inside the controller.
Exists: AHBAUDDMAIF
Active State: Low
Registered: No
idmahclk I AHB bus clock (AHB:HCLK).

Exists: AHBAUDDMAIF
Active State: N/A
Synchronous to: N/A
Registered: No
idmahrdata[31:0] I AHB read data bus (AHB:HRDATA[31:0]).

Exists: AHBAUDDMAIF
Active State: N/A
Synchronous to: idmahclk
Registered: Yes
idmahresp[1:0] I AHB bus transfer status response. All responses codes are
supported (AHB:HRESP[1:0]).
Exists: AHBAUDDMAIF
Active State: N/A
Registered: No
idmahready I AHB bus ready response (AHB:HREADY).

Exists: AHBAUDDMAIF
Active State: High
Registered: No

Table 5-6 AHB Audio DMA Input Interface Signals (Continued)
idmahgrant I AHB bus access grant. (AHB:HGRANT).

Exists: AHBAUDDMAIF
Active State: High
Registered: No
odmahaddr[31:0] O AHB address bus (AHB:HADDR[31:0]).

Exists: AHBAUDDMAIF
Active State: N/A
Registered: Yes
odmahtrans[1:0] O AHB bus transfer type. The controller supports NONSEQUENTIAL,

SEQUENTIAL and IDLE transfer types (AHB:HTRANS[1:0]).
Exists: AHBAUDDMAIF
Active State: N/A
Registered: Yes
odmahsize[2:0] O AHB bus transfer size. The controller only supports Word transfers
(32-bit) (AHB:HSIZE[1:0]).
Exists: AHBAUDDMAIF
Active State: N/A
Synchronous to: N/A
Registered: No
odmahburst[2:0] O AHB bus burst transfer type. The controller supports INCR, INCR4,
INCR8 and INCR16 transfer types (AHB:HBURST[2:0]).
Exists: AHBAUDDMAIF
Active State: N/A
Registered: Yes
odmahwdata[31:0] O AHB write data bus (AHB:HWDATA[31:0]). Not used by the controller
- output hardcoded to 32'd0.
Exists: AHBAUDDMAIF
Active State: N/A
Synchronous to: N/A
Registered: No
odmahwrite O AHB bus write enable (AHB:HWRITE). Not used by the controller -
output hardcoded to 1'b0.
Exists: AHBAUDDMAIF
Active State: High
Synchronous to: N/A
Registered: No

Table 5-6 AHB Audio DMA Input Interface Signals (Continued)
odmahlock O AHB bus locked transfer control (AHB:HLOCK). Not used by

controller by default - AHB locked transfers can be enabled by
software.
Exists: AHBAUDDMAIF
Active State: High
Registered: Yes
odmahbusreq O AHB bus access request (AHB:HBUSREQ).

Exists: AHBAUDDMAIF
Active State: High
Registered: Yes

5.7 CEC Interface Signals
icecclk - - ocecout
icecin - - ointerruptwakeup
Table 5-7 CEC Interface Signals
icecclk I CEC controller main clock input (Fixed frequency 32.768 kHz).
Exists: CEC
Active State: N/A
Synchronous to: N/A
Registered: No
icecin I CEC input data from CEC bus.

Exists: CEC
Active State: N/A
Registered: No
ocecout O CEC output data to CEC bus.

Exists: CEC
Active State: N/A
Registered: Yes
ointerruptwakeup O CEC engine dedicated interrupt signal raised by a wake-up event.

Exists: CEC
Active State: High
Registered: No

5.8 HDMI TX PHY Interface Signals
- ihpd
- ioavdd18
- ioavdd10
- iovdd
- ioagnd18
- ioagnd10
- iovss
- iorref
- ioatestmon
- otmdsdatap
- otmdsdatan
- otmdsclkp
- otmdsclkn
Table 5-8 HDMI TX PHY Interface Signals
ihpd IO Hot Plug Detect input.

Exists: !PHY_EXTERNAL
Active State: Refer to PHY databook
Synchronous to: Refer to PHY databook
Registered: N/A
ioavdd18 IO Analog power supply. For more information about port ioavdd18,
refer to the PHY databook.
Exists: !PHY_EXTERNAL && !PHY_GEN2
Registered: N/A
ioavdd10 IO Analog power supply. For more information about port ioavdd10,
Registered: N/A
iovdd IO Digital power supply. For more information about port iovdd, refer to
the PHY databook.
Registered: N/A

Table 5-8 HDMI TX PHY Interface Signals (Continued)
ioagnd18 IO Analog supply ground return. For more information about port
ioagnd18, refer to the PHY databook.
Registered: N/A
ioagnd10 IO Analog supply ground return. For more information about port
ioagnd10, refer to the PHY databook.
Registered: N/A
iovss IO Digital supply ground return. For more information about port iovss,
Registered: N/A
iorref IO Current reference input. Used to connect to an external resistance for

bias current generation.
Registered: N/A
ioatestmon[1:0] IO Analog probing nodes for test debugging.

Registered: N/A
otmdsdatap[2:0] O Positive TMDS differential line driver data output.

Registered: N/A
otmdsdatan[2:0] O Negative TMDS differential line driver data output.

Registered: N/A

Table 5-8 HDMI TX PHY Interface Signals (Continued)
otmdsclkp O Positive TMDS differential line driver clock output.

Registered: N/A
otmdsclkn O Negative TMDS differential line driver clock output.

Registered: N/A

5.9 E-DDC Interface Signals
ii2c_msth13tddc_sclin - - oi2c_msth13tddc_sclout
ii2c_msth13tddc_sdain - - oi2c_msth13tddc_sdaout
Table 5-9 E-DDC Interface Signals
ii2c_msth13tddc_sclin I HDMI DDC I2C slave clock input for HDCP and E-EDID
communication with transmitter.
Exists: Always
Active State: N/A
Registered: No
oi2c_msth13tddc_sclout O HDMI DDC I2C slave clock output.

Exists: Always
Active State: N/A
Registered: Yes
ii2c_msth13tddc_sdain I HDMI DDC I2C slave data input for E-EDID access HDCP and ID
communication with transmitter.
Exists: Always
Active State: N/A
Registered: No
oi2c_msth13tddc_sdaout O HDMI DDC I2C slave data output for E-EDID access.
Exists: Always
Active State: N/A
Registered: Yes

5.10 HDCP 1.4 Encryption Engine Interface Signals
idpkmemdatai - - odpkclk
idpkack - - odpkmemreq
idpkdatain - - odpkmemaddr
irndnum - - odpkaccess
irevocmemdatain - - odpkreq
- odpkaddr
- orndnumgenena
- orevocmemclk
- orevocmemaddress
- orevocmemdataout
- orevocmemcs
- orevocmemwen
Table 5-10 HDCP 1.4 Encryption Engine Interface Signals
odpkclk O Device Private Keys access clock signal (same as isfrclk clock).
Exists: (HDCP) && (!DWC_HDMI_HDCP_DPK_ROMLESS)
Active State: N/A
Synchronous to: N/A
Registered: No
odpkmemreq O DPKs read enable.

Exists: (HDCP) && (!DWC_HDMI_HDCP_DPK_ROMLESS) &&
(DWC_HDMI_HDCP_DPK_8BIT)
Active State: High
Synchronous to: odpkclk
Registered: Yes
odpkmemaddr[8:0] O DPKs Address bus.

Active State: N/A
Registered: Yes
idpkmemdatai[7:0] I DPKs input data bus.

Active State: N/A
Registered: No

Table 5-10 HDCP 1.4 Encryption Engine Interface Signals (Continued)
odpkaccess O DPKs access notification signal, active high.

(!DWC_HDMI_HDCP_DPK_8BIT)
Active State: High
Registered: Yes
odpkreq O DPKs read access request signal, active high.

Active State: High
Registered: Yes
odpkaddr[5:0] O Device Private Keys address bus.

Active State: N/A
Registered: No
idpkack I Device Private Keys (DPKs) read access acknowledge signal, active
high.
Active State: High
Registered: No
idpkdatain[55:0] I Device Private Keys data input bus.

Active State: N/A
Registered: No
orndnumgenena O Random Number Generation enable, active high.

Exists: HDCP
Active State: High
Synchronous to: itmdsclk
Registered: No

irndnum[3:0] I Random Number input bus.

Exists: HDCP
Active State: N/A
Synchronous to: itmdsclk
Registered: No
orevocmemclk O KSV MEM clock signal (same as isfrclk clock).

Exists: HDCP
Active State: N/A
Registered: No
orevocmemaddress[12:0] O KSV MEM address bus.

Exists: HDCP
Active State: N/A
Registered: No
orevocmemdataout[7:0] O KSV MEM write data bus.

Exists: HDCP
Active State: N/A
Synchronous to: orevocmemclk
Registered: No
irevocmemdatain[7:0] I KSV MEM read data bus.

Exists: HDCP
Active State: N/A
Registered: No
orevocmemcs O KSV MEM chip select signal, active high.

Exists: HDCP
Active State: High
Registered: No
orevocmemwen O KSV MEM write enable, active low.

Exists: HDCP
Active State: Low
Registered: No

5.11 HDCP 2.2 Encryption Engine Interface Signals
ist_hdcp2_capable - - ohdcptmdsclk
ist_hdcp2_not_capable - - ohdcptmdsrstz
ist_hdcp_authentication_lost - - ohdcpsfrrstz
ist_hdcp_authenticated - - ohdmi_hpd
ist_hdcp_authentication_fail - - ohdcp_i2c_grant
ist_hdcp_decrypted - - ohdcp_i2c_mst_activity
ihdcp_i2c_req - - ohdcp_i2c_byte_xferd_p
ihdcp_i2c_write - - ohdcp_i2c_lostarb
ihdcp_i2c_read - - ohdcp_i2c_nack
ihdcp_i2c_addr - - ohdcp_i2c_datai
ihdcp_i2c_slvaddr - - ohdmi_avmute
ihdcp_i2c_datao - - ovsync
ihdcp_i2c_short_read - - ohsync
ihdcp_i2c_seq_access - - ovideoen
ihdcp_i2c_fastmode - - odataislen
ihdcp_avmute - - ohdmi_color_depth
ihdcp_vsync - - octl
ihdcp_hsync - - otmdsch0
ivideoen - - otmdsch1
idataislen - - otmdsch2
ictl - - oldgbvideoen
itmdsch0 - - octlen
itmdsch1 - - oldgbdataen
itmdsch2 - - otlgben
ildgbvideoen - - oscrambler_en
ictlen -
ildgbdataen -
itlgben -
iscrambler_en -
Table 5-11 HDCP 2.2 Encryption Engine Interface Signals
ohdcptmdsclk O TMDS clock 25-600 MHz.

Exists: (HDCP) && (HTX_HDCP22_EXTERNAL)
Active State: N/A
Synchronous to: tmds_clk
Registered: No
ohdcptmdsrstz O TMDS asynchronous active low reset.

Active State: Low
Synchronous to: tmds_clk
Registered: No

ohdcpsfrrstz O Configuration asynchronous active low reset.

Active State: Low
Registered: No
ohdmi_hpd O HDMI HPD signal indication.

Active State: High
Registered: Yes
ist_hdcp2_capable I Active high indication that the opposite device is HDCP 2.2 capable.
Active State: High
Registered: No
ist_hdcp2_not_capable I Active high indication that the opposite device is not HDCP 2.2
capable.
Active State: High
Registered: No
ist_hdcp_authentication_lost I Active high indication that HDCP 2.2 device has lost authentication
and HDCP 2.2 will restart.
Active State: High
Registered: No
ist_hdcp_authenticated I Active high indication that HDCP 2.2 device is authenticated with
opposite device.
Active State: High
Registered: No
ist_hdcp_authentication_fail I Active high indication that HDCP 2.2 device has failed to authenticate
with opposite device.
Active State: High
Registered: No

ist_hdcp_decrypted I HDCP 2.2 device has started decrypting data. This signal is not
useful for an HDCP TX implementation, and is provided for debug
purposes only.
Active State: High
Registered: Yes
ihdcp_i2c_req I I2C operation request signal.

Active State: High
Registered: No
ohdcp_i2c_grant O I2C access granted.

Active State: High
Registered: No
ohdcp_i2c_mst_activity O I2C Master activity marker.

Active State: High
Registered: Yes
ohdcp_i2c_byte_xferd_p O I2C byte transfer finish.

Active State: High
Registered: No
ohdcp_i2c_lostarb O I2C arbitration lost.

Active State: High
Registered: Yes
ohdcp_i2c_nack O I2C received NACK to packet.

Active State: High
Registered: Yes

ohdcp_i2c_datai[7:0] O I2C received data.

Active State: N/A
Registered: Yes
ihdcp_i2c_write I I2C write request.

Active State: High
Registered: No
ihdcp_i2c_read I I2C read request.

Active State: High
Registered: No
ihdcp_i2c_addr[7:0] I I2C register offset.

Active State: N/A
Registered: No
ihdcp_i2c_slvaddr[6:0] I I2C Slave address.

Active State: N/A
Registered: No
ihdcp_i2c_datao[7:0] I I2C send data.

Active State: N/A
Registered: No
ihdcp_i2c_short_read I I2C short read request (for fixed offsets).

Active State: High
Registered: No

ihdcp_i2c_seq_access I I2C sequential read/write access.

Active State: High
Registered: No
ihdcp_i2c_fastmode I I2C fast mode selection.

Active State: High
Registered: No
ohdmi_avmute O Audio/Video Mute indication signal.

Active State: High
Synchronous to: ohdcptmdsclk
Registered: Yes
ovsync O Video vertical synchronization signal.

Active State: High
Registered: Yes
ohsync O Video horizontal synchronization signal.

Active State: High
Registered: Yes
ovideoen O Active video marker.

Active State: High
Registered: Yes
odataislen O Data island marker.

Active State: High
Registered: Yes

ohdmi_color_depth[3:0] O Color depth encoded as per HDMI Specification.

Active State: High
Registered: Yes
octl[3:0] O HDMI control period indication signals.

Active State: N/A
Registered: Yes
otmdsch0[7:0] O HDMI TMDS Data Channel 0 (Control + Data Island + Video).

Active State: N/A
Registered: Yes

Active State: N/A
Registered: Yes

Active State: N/A
Registered: Yes
oldgbvideoen O Video leading guard band marker.

Active State: High
Registered: Yes
octlen O Control period marker.

Active State: High
Registered: Yes

oldgbdataen O Data island leading guard band marker.

Active State: High
Registered: Yes
otlgben O Data island trailing guard band marker.

Active State: High
Registered: Yes
oscrambler_en O Scrambler enable.

Active State: High
Registered: Yes
ihdcp_avmute I HDCP in AVMUTE state status indication.

Active State: High
Registered: Yes
ihdcp_vsync I Delayed version of ovsync (by ohdcptmdsclk cycles) of

corresponding signals.
Active State: High
Registered: Yes
ihdcp_hsync I Delayed version of ohsync (by ohdcptmdsclk cycles) of

Active State: High
Registered: Yes
ivideoen I Delayed version of ovideoen (by ohdcptmdsclk cycles) of

Active State: High
Registered: Yes

idataislen I Delayed version of odataislen (by ohdcptmdsclk cycles) of

Active State: High
Registered: Yes
ictl[3:0] I Delayed version of octl (by ohdcptmdsclk cycles) of corresponding

signals.
Active State: N/A
Registered: Yes
itmdsch0[7:0] I Encrypted HDMI TMDS Data Channel 0.

Active State: N/A
Registered: Yes

Active State: N/A
Registered: Yes

Active State: N/A
Registered: Yes
ildgbvideoen I Delayed version of oldgbvideoen (by ohdcptmdsclk cycles) of

Active State: High
Registered: Yes
ictlen I Delayed version of octlen (by ohdcptmdsclk cycles) of corresponding

signals.
Active State: High
Registered: Yes

ildgbdataen I Delayed version of oldgbdataen (by ohdcptmdsclk cycles) of

Active State: High
Registered: Yes
itlgben I Delayed version of otlgben (by ohdcptmdsclk cycles) of

Active State: High
Registered: Yes
iscrambler_en I Delayed version of oscrambler_en (by ohdcptmdsclk cycles) of

Active State: High
Registered: Yes

5.12 HDMI 3-D TX PHY (PHY GEN 2) Interface Signals
- iovp
- iovp_filt0
- iovp_filt1
- iovp_filt2
- iovph
- iogd
- ioresref_f
- ioresref_s
- ophydtb
- ioddccec
Table 5-12 HDMI 3-D TX PHY (PHY GEN 2) Interface Signals
iovp IO Analog power supply. For more information about port iovp, refer to
the PHY databook.
Exists: !PHY_EXTERNAL && PHY_GEN2
Registered: N/A
iovp_filt0 IO Analog power supply. For more information about port iovp_filt0, refer
to the PHY databook.
Exists: (!PHY_EXTERNAL && PHY_GEN2) &&
(!PHY_MHL_COMBO)
Registered: N/A
(!PHY_MHL_COMBO)
Registered: N/A
(!PHY_MHL_COMBO)
Registered: N/A

Table 5-12 HDMI 3-D TX PHY (PHY GEN 2) Interface Signals (Continued)
iovph IO Analog power supply. For more information about port iovph, refer to
the PHY databook.
Registered: N/A
iogd IO Analog ground. For more information about port iogd, refer to the
PHY databook.
Registered: N/A
ioresref_f IO Reference resistor connection. For more information, refer to the

PHY databook.
Registered: N/A
ioresref_s IO Precision resistor to ground. For more information, refer to the PHY
databook.
Registered: N/A
ophydtb[1:0] O PHY digital test bus. For more information, refer to the PHY
databook.
Registered: N/A
ioddccec IO Ground reference for the Hot Plug Detect signal. For more
information, refer to the PHY databook.
Registered: N/A

5.13 HDMI-MHL or HDMI 2.0 TX PHY Interface Signals
iphyctl_external - - ophyctl_jtag_tdo
iphyctl_jtag_trst_n - - ophyctl_jtag_tdo_en
iphyctl_jtag_tck - - ophyctl_i2c_sda_pdn_n
iphyctl_jtag_tms - - ophyctl_cont_data
iphyctl_jtag_tdi - - ophyctl_bistdone
iphyctl_jtag_addr - - ophyctl_bistok
iphyctl_i2c_jtagz - - ophyctl_tx_ready
iphyctl_i2c_sda - - ophyctl_snk_det
iphyctl_i2c_scl - - ophyctl_rxsense
iphyctl_i2c_slv_addr -
iphyctl_cont_en -
iphyctl_bisten -
iphyctl_phy_reset -
iphyctl_ppdq -
iphyctl_tx_pwron -
iphyctl_svsret_modez -
iphyctl_enhpdrxsense -
Table 5-13 HDMI-MHL or HDMI 2.0 TX PHY Interface Signals
iphyctl_external I Enables external control of the PHY. Must be tied low (1'b0) for
normal operational mode.
Exists: PHY_MHL_COMBO
Registered: N/A
iphyctl_jtag_trst_n I Connected to PHY JTAG_TRST_N. For more information about PHY

JTAG_TRST_N functionality, refer to the PHY databook.
Registered: N/A
iphyctl_jtag_tck I Connected to PHY JTAG_TCK. For more information about PHY

JTAG_TCK functionality, refer to the PHY databook.
Registered: N/A

Table 5-13 HDMI-MHL or HDMI 2.0 TX PHY Interface Signals (Continued)
iphyctl_jtag_tms I Connected to PHY JTAG_TMS. For more information about PHY

JTAG_TMS functionality, refer to the PHY databook.
Registered: N/A
iphyctl_jtag_tdi I Connected to PHY JTAG_TDI. For more information about PHY

JTAG_TDI functionality, refer to the PHY databook.
Registered: N/A
ophyctl_jtag_tdo O Connected to PHY JTAG_TDO. For more information about PHY

JTAG_TDO functionality, refer to the PHY databook.
Registered: N/A
ophyctl_jtag_tdo_en O Connected to PHY JTAG_TDO_EN. For more information about PHY

JTAG_TDO_EN functionality, refer to the PHY databook.
Registered: N/A
iphyctl_jtag_addr[7:0] I Connected to PHY JTAG_ADDR. For more information about PHY

JTAG_ADDR functionality, refer to the PHY databook.
Registered: N/A
iphyctl_i2c_jtagz I Connected to PHY I2C_JTAGZ when iphyctl_external = 1. For more

information about PHY I2C_JTAGZ functionality, refer to the PHY
databook.
Registered: N/A

iphyctl_i2c_sda I Connected to PHY I2C_SDA when iphyctl_external = 1. For more

information about PHY I2C_SDA functionality, refer to the PHY
databook.
Registered: N/A
iphyctl_i2c_scl I Connected to PHY I2C_SCL when iphyctl_external = 1. For more

information about PHY I2C_SCL functionality, refer to the PHY
databook.
Registered: N/A
ophyctl_i2c_sda_pdn_n O Connected to PHY I2C_SDA_PULL_DN_N when iphyctl_external =

1 and driven high (1'b1) when iphyctl_external=0. For more
information about PHY I2C_SDA_PULL_DN_N functionality, refer to
the PHY databook.
Registered: N/A
iphyctl_i2c_slv_addr[6:0] I Connected to PHY I2C_SLAVE_ADDR when iphyctl_external = 1.

For more information about PHY I2C_SLAVE_ADDR functionality,
Registered: N/A
ophyctl_cont_data[9:0] O Connected to PHY CONT_DATA. For more information about PHY

CONT_DATA functionality, refer to the PHY databook.
Registered: N/A

iphyctl_cont_en I Connected to PHY CONT_EN when iphyctl_external = 1. For more

information about PHY CONT_EN functionality, refer to the PHY
databook.
Registered: N/A
iphyctl_bisten I Connected to PHY BISTEN when iphyctl_external = 1. For more

information about PHY BISTEN functionality, refer to the PHY
databook.
Registered: N/A
ophyctl_bistdone O Connected to PHY BISTDONE. For more information about PHY

BISTDONE functionality, refer to the PHY databook.
Registered: N/A
ophyctl_bistok O Connected to PHY BISTOK. For more information about PHY

BISTOK functionality, refer to the PHY databook.
Registered: N/A
iphyctl_phy_reset I Connected to PHY PHY_RESET when iphyctl_external = 1. For

more information about PHY PHY_RESET functionality, refer to the
PHY databook.
Registered: N/A
iphyctl_ppdq I Connected to PHY PPDQ when iphyctl_external = 1. For more

information about PHY PPDQ functionality, refer to the PHY
databook.
Registered: N/A

iphyctl_tx_pwron I Connected to PHY TX_PWRON when iphyctl_external = 1. For more

information about PHY TX_PWRON functionality, refer to the PHY
databook.
Registered: N/A
iphyctl_svsret_modez I Connected to PHY SVSRET_MODEZ when iphyctl_external = 1. For

more information about PHY SVSRET_MODEZ functionality, refer to
the PHY databook.
Registered: N/A
iphyctl_enhpdrxsense I Connected to PHY ENVBUSHPDRXSENSE when iphyctl_external =

1. For more information about PHY ENVBUSHPDRXSENSE
functionality, refer to the PHY databook.
Registered: N/A
ophyctl_tx_ready O Connected to PHY TX_READY. For more information about PHY

TX_READY functionality, refer to the PHY databook.
Registered: N/A
ophyctl_snk_det O Connected to PHY SNK_DET. For more information about PHY

SNK_DET functionality, refer to the PHY databook.
Registered: N/A
ophyctl_rxsense O Connected to PHY RXSENSEP. For more information about PHY

RXSENSEP functionality, refer to the PHY databook.
Registered: N/A

5.14 HDMI TX External PHY Signals
iphyext_tclk - - ophyext_rstz
iphyext_prepclk - - ophyext_dataencoded
iphyext_lock - - ophyext_ppdq
iphyext_hpd - - ophyext_sparectl
iphyext_rxsense - - ophyext_txpwron
iphyext_jtag_tdo - - ophyext_enhpdrxsense
iphyext_jtag_tdo_en - - ophyext_jtag_trst_n
iphyext_i2c_sclin - - ophyext_jtag_tck
iphyext_i2c_sdain - - ophyext_jtag_tms
- ophyext_jtag_tdi
- ophyext_jtag_addr
- ophyext_i2c_jtagz
- ophyext_i2c_sdaout
- ophyext_i2c_sclout
Table 5-14 HDMI TX External PHY Signals
iphyext_tclk I TMDS clock for controller (symbol clock).

Exists: PHY_EXTERNAL
Active State: N/A
Synchronous to: N/A
Registered: No
iphyext_prepclk I Pixel repetition clock controller.

Exists: (PHY_EXTERNAL) && (DWC_HDMI_TX_INTPREPEN)
Active State: N/A
Synchronous to: N/A
Registered: No
ophyext_rstz O Software controlled PHY reset. Mapped to register MC_PHYRSTZ,

bit 0.
Active State: active low
Registered: Yes
iphyext_lock I PHY status: PLL lock. Mapped to register PHY_STAT0, bit 0.

Active State: Logic high when locked
Registered: Yes

Table 5-14 HDMI TX External PHY Signals (Continued)
iphyext_hpd I HDMI link status: Hot Plug Detect signal. Mapped to register
PHY_STAT0, bit 1.
Active State: logic high when HPD present
Registered: Yes
ophyext_dataencoded[29:0] O Encoded data vector by TERC4, 2b10b and 8b10b as per the HDMI.
1.4a Specification
Channel 0 - ophyext_dataencoded [ 9: 0] Channel 1 -
ophyext_dataencoded [19:10] Channel 2 - ophyext_dataencoded
[29:20]
Active State: N/A
Synchronous to: iphyext_tclk
Registered: Yes
iphyext_rxsense I HDMI link status: Sink detected signal. Mapped to register

PHY_STAT0, bit 4.
Active State: logic high when HDMI RX present
Registered: Yes
ophyext_ppdq O PHY configuration: Power down control. Mapped to register

PHY_CONF0, bit 4.
Active State: N/A
Registered: Yes
ophyext_sparectl O PHY configuration: Spare control bit. Mapped to register

PHY_CONF0, bit 5.
Active State: N/A
Registered: Yes
ophyext_txpwron O PHY configuration: transmitter power. Mapped to register

PHY_CONF0, bit 3
Active State: N/A
Registered: Yes

ophyext_enhpdrxsense O PHY configuration: HPD and RX sense enable; Mapped to register

PHY_CONF0, bit 2.
Active State: N/A
Registered: Yes
ophyext_jtag_trst_n O PHY configuration: JTAG TRST N output.

Active State: active low
Registered: Yes
ophyext_jtag_tck O PHY configuration: JTAG TCK.

Active State: N/A
Registered: Yes
ophyext_jtag_tms O PHY configuration: JTAG TMS.

Active State: N/A
Registered: Yes
ophyext_jtag_tdi O PHY configuration: JTAG TDI.

Active State: N/A
Registered: Yes
iphyext_jtag_tdo I PHY configuration: JTAG TDO input.

Active State: N/A
Registered: Yes
iphyext_jtag_tdo_en I PHY configuration: JTAG TDO EN input.

Active State: N/A
Registered: Yes

ophyext_jtag_addr[7:0] O PHY configuration: JTAG Address.

Active State: N/A
Registered: Yes
ophyext_i2c_jtagz O PHY configuration: I2C/JTAG selector.

Active State: high for selecting I2C interface
Registered: Yes
ophyext_i2c_sdaout O PHY configuration: I2C SDA output.

Active State: N/A
Registered: Yes
ophyext_i2c_sclout O PHY configuration: I2C SCL output.

Active State: N/A
Registered: No
iphyext_i2c_sclin I PHY configuration: I2C SCL input.

Active State: N/A
Registered: Yes
iphyext_i2c_sdain I PHY configuration: I2C SDA input.

Active State: N/A
Registered: Yes

5.15 Scan Test Interface Signals
iscan_phy_in - - oscan_phy_out
iscan_40m_clk - - oscan_ck_ref_out
iscan_40m_in - - oscan_rx_word_clk0_div2_out
iscan_40m_luctrl - - oscan_rx_word_clk1_div2_out
iscan_cko_word_clk - - oscan_rx_word_clk2_div2_out
iscan_cko_word_in - - oscan_tx_ck_out0_out
iscan_cko_word_luctrl - - oscan_tmdsclkin_out
iscan_ck_ref_clk - - oscan_jtag_tck_out
iscan_pclk_in - - oscan_40m_out
iscan_pclk_luctrl - - oscan_cko_word_out
iscan_rx_word_clk0_clk - - oscan_pclk_out
iscan_rx_word_clk0_div2_clk - - oscan_rx_word_clk0_out
iscan_rx_word_clk0_in - - oscan_rx_word_clk1_out
iscan_rx_word_clk0_luctrl - - oscan_rx_word_clk2_out
iscan_rx_word_clk1_clk - - oscan_scl_out
iscan_rx_word_clk1_div2_clk - - oscan_tx_ck_20b_out
iscan_rx_word_clk1_in - - oscan_tx_ck_out1_out
iscan_rx_word_clk1_luctrl - - oscan_tx_ck_out2_out
iscan_rx_word_clk2_clk - - oscan_ctrl_out
iscan_rx_word_clk2_div2_clk -
iscan_rx_word_clk2_in -
iscan_rx_word_clk2_luctrl -
iscan_scl_in -
iscan_scl_luctrl -
iscan_set_rst -
iscan_tx_ck_20b_clk -
iscan_tx_ck_20b_in -
iscan_tx_ck_20b_luctrl -
iscan_tx_ck_out0_clk -
iscan_tx_ck_out1_in -
iscan_tx_ck_out1_luctrl -
iscan_ck_ref_in -
iscan_ck_ref_luctrl -
iscan_rx_word_clk0_div2_in -
iscan_rx_word_clk0_div2_luctrl -
iscan_tmdsclkin_clk -
iscan_tmdsclkin_in -
iscan_tmdsclkin_luctrl -
iscan_jtag_tck_in -
iscan_jtag_tck_luctrl -
iscanclk -
iscanrstz -
iscanen -
iscanmode -
iscan_ctrl_in -

Table 5-15 Scan Test Interface Signals
iscan_phy_in[HTX_SCAN_PORT_WIDT I HDMI PHY scan chain input.

H:0] Exists: !PHY_EXTERNAL && PHY_NO_AT_SPEEDSCAN
Active State: N/A
Synchronous to: iscanclk
Registered: Yes
oscan_phy_out[HTX_SCAN_PORT_WI O HDMI PHY Scan chain output.

DTH:0] Exists: !PHY_EXTERNAL && PHY_NO_AT_SPEEDSCAN
Active State: N/A
Registered: Yes
iscan_40m_clk I HDMI PHY Scan 40m clock. Clock source for scan mode.
Exists: !PHY_EXTERNAL && !PHY_NO_AT_SPEEDSCAN
Registered: Refer to PHY databook
iscan_40m_in I HDMI PHY Scan input. Serial 40m data stream input when macro is
in Scanmode.
iscan_40m_luctrl I HDMI PHY Scan input. Select 40m Lockup Latch at chain output
iscan_cko_word_clk I HDMI PHY Scan cko word clock. Clock source for scan mode.
iscan_cko_word_in I HDMI PHY Scan input. Serial ck0 word data stream input when
macro is in Scanmode.

Table 5-15 Scan Test Interface Signals (Continued)
iscan_cko_word_luctrl I HDMI PHY Scan input. Select ck0 word Lockup Latch at chain output
iscan_ck_ref_clk I HDMI PHY Scan ck ref clock. Clock source for scan mode.
iscan_pclk_in I HDMI PHY Scan input. Serial pclk data stream input when macro is
in Scanmode.
iscan_pclk_luctrl I HDMI PHY Scan input. Select pclk Lockup Latch at chain output
iscan_rx_word_clk0_clk I HDMI PHY Scan rx word clk0 clock. Clock source for scan mode.
iscan_rx_word_clk0_div2_clk I HDMI PHY Scan rx clk0 word div2 clock. Clock source for scan
mode.
iscan_rx_word_clk0_in I HDMI PHY Scan input. Serial rx word clk0 data stream input when

iscan_rx_word_clk0_luctrl I HDMI PHY Scan input. Select rx clk0 word Lockup Latch at chain
output
iscan_rx_word_clk1_clk I HDMI PHY Scan rx clk1 word clock. Clock source for scan mode.
iscan_rx_word_clk1_div2_clk I HDMI PHY Scan rx clk1 div2 word clock. Clock source for scan
mode.
iscan_rx_word_clk1_in I HDMI PHY Scan input. Serial rx clk1 word data stream input when
iscan_rx_word_clk1_luctrl I HDMI PHY Scan input. Select rx clk1 word Lockup Latch at chain
output
iscan_rx_word_clk2_clk I HDMI PHY Scan rx word clk2 clock. Clock source for scan mode.
iscan_rx_word_clk2_div2_clk I HDMI PHY Scan rx word clk2 div2 clock. Clock source for scan
mode.

iscan_rx_word_clk2_in I HDMI PHY Scan input. Serial rx clk2 in data stream input when
iscan_rx_word_clk2_luctrl I HDMI PHY Scan input. Select rx clk2 div2 word Lockup Latch at
chain output.
iscan_scl_in I HDMI PHY Scan input. Serial scl in data stream input when macro is
in Scanmode.
iscan_scl_luctrl I HDMI PHY Scan input. Select scl Lockup Latch at chain output.
iscan_set_rst I HDMI PHY Scan reset

iscan_tx_ck_20b_clk I HDMI PHY Scan tx ck 20b clock. Clock source for scan mode.
iscan_tx_ck_20b_in I HDMI PHY Scan input. Serial tx ck 20b data stream input when

iscan_tx_ck_20b_luctrl I HDMI PHY Scan input. Select tx ck 20b Lockup Latch at chain
output.
iscan_tx_ck_out0_clk I HDMI PHY Scan tx ck out0 clock. Clock source for scan mode.
iscan_tx_ck_out1_in I HDMI PHY Scan input. Serial tx ck out1 data stream input when
iscan_tx_ck_out1_luctrl I HDMI PHY Scan input. Select ck out1 Lockup Latch at chain output.
iscan_tx_ck_out2_in I HDMI PHY Scan input. Serial ck out2 data stream input when macro
is in Scanmode.

iscan_tx_ck_out2_luctrl I HDMI PHY Scan input. Select ck out2 Lockup Latch at chain output.
iscan_ck_ref_in[1:0] I HDMI PHY Scan input. Serial ck ref data stream input when macro is
in Scan mode.
iscan_ck_ref_luctrl[1:0] I HDMI PHY Scan input. Select ck ref Lockup Latch at chain output.
iscan_rx_word_clk0_div2_in[1:0] I HDMI PHY Scan input. Serial clk0 div2 data stream input when
macro is in Scan mode.
iscan_rx_word_clk0_div2_luctrl[1:0] I HDMI PHY Scan input. Select clk0 div2 Lockup Latch at chain
output.
iscan_rx_word_clk1_div2_in[1:0] I HDMI PHY Scan input. Serial clk1 div2 data stream input when
iscan_rx_word_clk1_div2_luctrl[1:0] I HDMI PHY Scan input. Select clk1 div2 Lockup Latch at chain
output.

iscan_rx_word_clk2_div2_in[1:0] I HDMI PHY Scan input. Serial rx clk2 div2 data stream input when
iscan_rx_word_clk2_div2_luctrl[1:0] I HDMI PHY Scan input. Select rx clk2 word div2 Lockup Latch at
chain output
iscan_tx_ck_out0_in[1:0] I HDMI PHY Scan input. Serial tx ck out0 data stream input when
iscan_tx_ck_out0_luctrl[1:0] I HDMI PHY Scan input. Select tx ck out0 Lockup Latch at chain
output
iscan_tmdsclkin_clk I HDMI PHY Scan tmdsclkin clock. Clock source for scan mode.
iscan_tmdsclkin_in[2:0] I HDMI PHY Scan input. Serial tmdsclkin data stream input when

iscan_tmdsclkin_luctrl[2:0] I HDMI PHY Scan input. Select tmdsclkin Lockup Latch at chain
output
iscan_jtag_tck_in[4:0] I HDMI PHY Scan input. Serial jtag tck data stream input when macro
is in Scan mode.
iscan_jtag_tck_luctrl[4:0] I HDMI PHY Scan input. Select jtag tck Lockup Latch at chain output
oscan_ck_ref_out[1:0] O HDMI PHY Scan out. Serial ck ref data stream output when macro is
in Scan mode.
oscan_rx_word_clk0_div2_out[1:0] O HDMI PHY Scan out. Serial rx word clk0 div2 data stream output
when macro is in Scan mode.

oscan_tx_ck_out0_out[1:0] O HDMI PHY Scan out. Serial tx ck out0 data stream output when
oscan_tmdsclkin_out[2:0] O HDMI PHY Scan out. Serial tmdsclkin data stream output when
oscan_jtag_tck_out[4:0] O HDMI PHY Scan out. Serial jtag tck data stream output when macro
is in Scan mode.
oscan_40m_out O HDMI PHY Scan out. Serial 40m data stream output when macro is
in Scan mode.
oscan_cko_word_out O HDMI PHY Scan out. Serial ck0 word data stream output when
macro is in Scan mode..

oscan_pclk_out O HDMI PHY Scan out. Serial pclk data stream output when macro is in
Scan mode.
oscan_rx_word_clk0_out O HDMI PHY Scan out. Serial rx word clk0 data stream output when
oscan_scl_out O HDMI PHY Scan out. Serial scl data stream output when macro is in
Scan mode.
oscan_tx_ck_20b_out O HDMI PHY Scan out. Serial tx ck 20b data stream output when

oscan_tx_ck_out1_out O HDMI PHY Scan out. Serial tx ck out1 data stream output when
oscan_tx_ck_out2_out O HDMI PHY Scan out. Serial tx ck out2 data stream output when
iscanclk I Scan mode clock.

Exists: Always
Active State: N/A
Synchronous to: N/A
Registered: N/A
iscanrstz I Scan reset input (active low).

Exists: Always
Active State: Low
Synchronous to: N/A
Registered: N/A
iscanen I Scan enable signal (must be low for normal operation).

Exists: Always
Active State: High
Registered: N/A
iscanmode I Scan test mode enable (must be low for normal operation).
Exists: Always
Active State: High
Registered: N/A
iscan_ctrl_in I HDMI controller scan chain input.

Exists: Always
Active State: N/A
Registered: N/A

oscan_ctrl_out O HDMI controller scan chain output.

Exists: Always
Active State: N/A
Synchronous to: N/A
Registered: N/A

5.16 HDMI HEAC PHY Interface Signals
iscanin_heac - - iovdd_heac
ihectxdatan - - iovss_heac
ihectxdatap - - iogd_heac
- iovph_heac
- oheacphy_dtb
- oscanout_heac
- oarcrxdata
- ioheacn
- ioheacp
- iohecrxdatan
- iohecrxdatap
- ioresext
- ioresextv
Table 5-16 HDMI HEAC PHY Interface Signals
iovdd_heac IO Digital power supply. For more information about port iovdd_heac,
Exists: HDMI_HEAC_PHY_EN
Registered: N/A
iovss_heac IO Digital ground return. For more information about port iovss_heac,
Registered: N/A
iogd_heac IO Analog ground return. For more information about port iogd_heac,
Registered: N/A
iovph_heac IO Analog power supply. For more information about port iovph_heac,
Registered: N/A

Table 5-16 HDMI HEAC PHY Interface Signals (Continued)
oheacphy_dtb[1:0] O Digital Test Bus.

Registered: N/A
iscanin_heac I Scan in. Serial data stream input when core is in Scan mode.
Registered: N/A
oscanout_heac O Scan out. Serial data stream output when core is in Scan mode.
Registered: N/A
ihectxdatan I Input data for HEAC- (negative pulse).

Registered: N/A
ihectxdatap I HEAC PHY, Input data for HEAC+ (positive pulse).

Registered: N/A
oarcrxdata O Output from ARC RX.

Registered: N/A
ioheacn IO Analog HEAC- (negative pulse).

Registered: N/A

Table 5-16 HDMI HEAC PHY Interface Signals (Continued)
ioheacp IO Analog HEAC+ (positive pulse).

Registered: N/A
iohecrxdatan IO Analog negative output for the modified 100BaseTX PHY.

Registered: N/A
iohecrxdatap IO Analog positive output for the modified 100BaseTX PHY.

Registered: N/A
ioresext IO Analog external reference resistor.

Registered: N/A
ioresextv IO Analog external reference resistor ground.

Registered: N/A


6
Register Descriptions
This chapter details all possible registers in the core. They are arranged hierarchically into maps and blocks
(banks). For configurable IP titles, your actual configuration might not contain all of these registers.
For configurable IP titles, do not use this document to determine the exact attributes of your
Note register map. It is for reference purposes only.
When you configure the core in coreConsultant, you must access the register attributes for your actual
configuration at workspace/report/ComponentRegisters.html or
workspace/report/ComponentRegisters.xml after you have completed the report creation activity. That
report comes from the exact same source as this chapter but removes all the registers that are not in your
actual configuration. This does not apply to non-configurable IP titles. In addition, all parameter
expressions are evaluated to actual values. Therefore, the Offset and Memory Access values might change
depending on your actual configuration.
Some expressions might refer to TCL functions or procedures (sometimes identified as <functionof>) that
GUI reports.
Exists Expressions
The Exist expressions indicate the combination of configuration parameters required for a register, field, or
block to exist in the memory map. The expression is only valid in the local context and does not indicate the
conditions for existence of the parent. For example, the Exists expression for a bit field in a register assumes
that the register exists and does not include the conditions for existence of the register.
Offset
The term Offset is synonymous with Address.
Memory Access Attributes
The Memory Access attribute is defined as <ReadBehavior>/<WriteBehavior> which are defined in the
following table.

Register Descriptions HDMI Transmitter Controller Databook
Table 6-1 Possible Read and Write Behaviors
Read (or Write) Behavior Description
RC A read clears this register field.
RS A read sets this register field.
RM A read modifies the contents of this register field.
Wo You can only write to this register once field.
W1C A write of 1 clears this register field.
W1S A write of 1 sets this register field.
W1T A write of 1 toggles this register field.
W0C A write of 0 clears this register field.
W0S A write of 0 sets this register field.
W0T A write of 0 toggles this register field.
WC Any write clears this register field.
WS Any write sets this register field.
WM Any write toggles this register field.
no Read Behavior attribute You cannot read this register. It is Write-Only.
no Write Behavior attribute You cannot write to this register. It is Read-Only.
Table 6-2 Memory Access Examples
Memory Access Description
R Read-only register field.
W Write-only register field.
R/W Read/write register field.
R/W1C You can read this register field. Writing 1 clears it.
RC/W1C Reading this register field clears it. Writing 1 clears it.
R/Wo You can read this register field. You can only write to it once.

HDMI Transmitter Controller Databook Register Descriptions
Special Optional Attributes

Some register fields might use the following optional attributes.
Table 6-3 Optional Attributes
Attribute Description
Volatile As defined by the IP-XACT specification. If true, indicates in the

case of a write followed by read, or in the case of two consecutive
reads, there is no guarantee as to what is returned by the read on
the second transaction or that this return value is consistent with the
write or read of the first transaction. The element implies there is
some additional mechanism by which this field can acquire new
values other than by reads/writes/resets and other access methods
known to IP-XACT. For example, when the core updates the register
field contents.
Testable As defined by the IP-XACT specification. Possible values are

unconstrained, untestable, readOnly, writeAsRead, restore.
Untestable means that this field is untestable by a simple automated
register test. For example, the read-write access of the register is
controlled by a pin or another register. readOnly means that you
should not write to this register; only read from it. This might apply
for a register that modifies the contents of another register.
Reset Mask As defined by the IP-XACT specification. Indicates that this register
field has an unknown reset value. For example, the reset value is set
by another register or an input pin; or the register is implemented
using RAM.
* Varies Indicates that the memory access (or reset) attribute (read, write
behavior) is not fixed. For example, the read-write access of the
register is controlled by a pin or another register. Or when the
access depends on some configuration parameter; in this case the
post-configuration report in coreConsultant gives the actual access
value.

Component Banks/Blocks
The following table shows the address blocks for each memory map. Follow the link for an address block to
see a table of its registers.
Table 6-4 Address Banks/Blocks for Memory Map: hdmi_memmap
Address Block Description

Identification on page 189 Identification Registers
Exists: Always
Interrupt on page 196 Interrupt Registers
Exists: Always
VideoSampler on page 219 Video Sampler Registers
Exists: Always
VideoPacketizer on page 226 Video Packetizer Registers
Exists: Always
FrameComposer on page 235 Frame Composer Registers
Exists: Always
PHYConfiguration on page 348 PHY Configuration Registers
Exists: Always
AudioSample on page 374 Audio Sample Registers
Exists: Always
AudioPacketizer on page 380 Audio Packetizer Registers
Exists: Always
AudioSampleSPDIF on page 387 Audio Sample SPDIF Registers
Exists: Always
AudioSampleGP on page 392 Audio Sample GP Registers
Exists: Always
AudioDMA on page 396 Audio DMA Registers
Exists: Always
MainController on page 411 Main Controller Registers
Exists: Always
ColorSpaceConverter on page 419 Color Space Converter Registers
Exists: Always
HDCP on page 438 HDCP Registers
Exists: Always
HDCP22 on page 469 HDCP22 Registers
Exists: Always
CEC on page 478 CEC Registers
Exists: Always
EDDC on page 489 E-DDC Registers
Exists: Always

6.1 Identification Registers

Identification Registers. Follow the link for the register to see a detailed description of the register.
Table 6-5 Registers for Address Block: Identification
Register Offset Description

design_id on page 190 0x0 Design Identification Register
revision_id on page 190 0x1 Revision Identification Register
product_id0 on page 191 0x2 Product Identification Register 0
product_id1 on page 191 0x3 Product Identification Register 1
config0_id on page 192 0x4 Configuration Identification Register 0

6.1.1 design_id
■ Description: Design Identification Register
■ Size: 8 bits
■ Offset: 0x0
■ Exists: Always
Table 6-6 Fields for Register: design_id
Memory
Bits Name Access Description
7:0 design_id R Design ID code fixed by Synopsys that Identifies the
instantiated DWC_hdmi_tx controller. For example,
DWC_hdmi_tx 2.10a, DESIGN_ID = 21
Value After Reset: 0x21
Exists: Always
6.1.2 revision_id
■ Description: Revision Identification Register
■ Size: 8 bits
■ Offset: 0x1
■ Exists: Always
Table 6-7 Fields for Register: revision_id
Memory
7:0 revision_id R Revision ID code fixed by Synopsys that Identifies the
instantiated DWC_hdmi_tx controller. For example,
DWC_hdmi_tx 2.12a, REVISION_ID = 2Ah
Value After Reset: 0x2a
Exists: Always

6.1.3 product_id0
■ Description: Product Identification Register 0
■ Size: 8 bits
■ Offset: 0x2
■ Exists: Always
Table 6-8 Fields for Register: product_id0
Memory
7:0 product_id0 R This one byte fixed code Identifies Synopsys's product line
("A0h" for DWC_hdmi_tx products).
Value After Reset: 0xa0
Exists: Always
6.1.4 product_id1
■ Description: Product Identification Register 1
■ Size: 8 bits
■ Offset: 0x3
■ Exists: Always
Table 6-9 Fields for Register: product_id1
Memory
7:6 product_id1_hdcp R These bits identify a Synopsys's HDMI Controller with HDCP
encryption according to Synopsys product line.
Value After Reset: "(HDCP== 1) ? 3 : 0"
Exists: Always
5:2 Reserved for future use.
1 product_id1_rx R This bit Identifies Synopsys's DWC_hdmi_rx Controller
according to Synopsys product line.
Exists: Always
0 product_id1_tx R This bit Identifies Synopsys's DWC_hdmi_tx Controller
according to Synopsys product line.
Exists: Always

6.1.5 config0_id
■ Description: Configuration Identification Register 0
■ Size: 8 bits
■ Offset: 0x4
■ Exists: Always
Table 6-10 Fields for Register: config0_id
Memory
7 prepen R Indicates if it is possible to use internal pixel repetition
Value After Reset: "(DWC_HDMI_TX_INTPREPEN== 1) ?
1 : 0"
Exists: Always
6 Reserved for future use.
5 audspdif R Indicates if the SPDIF audio interface is present
Value After Reset: "(SPDIFPORTS== 1) ? 1 : 0"
Exists: Always
4 audi2s R Indicates if I2S interface is present
Value After Reset: "(I2SPORTS== 1) ? 1 : 0"
Exists: Always
3 hdmi14 R Indicates if HDMI 1.4 features are present
Value After Reset: "(DWC_HDMI_TX_14== 1) ? 1 : 0"
Exists: Always
2 csc R Indicates if Color Space Conversion block is present
Value After Reset: "(CSC== 1) ? 1 : 0"
Exists: Always
1 cec R Indicates if CEC is present
Value After Reset: "(CEC== 1) ? 1 : 0"
Exists: Always
0 hdcp R Indicates if HDCP is present
Value After Reset: "(HDCP== 1) ? 1 : 0"
Exists: Always

6.1.6 config1_id
■ Size: 8 bits
■ Offset: 0x5
■ Exists: Always
Memory
6 hdcp22_ext R Indicates if external HDCP 2.2 interface support is present
Value After Reset: "(HTX_HDCP22_EXTERNAL== 1) ? 1 :
0"
Exists: Always
5 hdmi20 R Indicates if HDMI 2.0 features are present
Exists: Always
1 confapb R Indicates that configuration interface is APB interface
Exists: Always

6.1.7 config2_id
■ Size: 8 bits
■ Offset: 0x6
■ Exists: Always
Memory
7:0 phytype R Indicates the type of PHY interface selected:
0x00: Legacy PHY (HDMI TX PHY)
0xF2: PHY GEN2 (HDMI 3D TX PHY)
0xE2: PHY GEN2 (HDMI 3D TX PHY) + HEAC PHY
0xC2: PHY MHL COMBO (MHL+HDMI 2.0 TX PHY)
0xB2: PHY MHL COMBO (MHL+HDMI 2.0 TX PHY) + HEAC
PHY
0xF3: PHY HDMI 20 (HDMI 2.0 TX PHY)
0xE3: PHY HDMI 20 (HDMI 2.0 TX PHY) + HEAC PHY
0xFE: External PHY
Value After Reset: "(PHY_HDMI20==1) ?
((HDMI_HEAC_PHY_EN==1)? 0xE3 : 0xF3) :
(PHY_MHL_COMBO==1) ? ((HDMI_HEAC_PHY_EN==1)?
0xB2 : 0xC2) : (PHY_GEN2==1) ?
((HDMI_HEAC_PHY_EN==1)? 0xE2 : 0xF2) :
(PHY_EXTERNAL==1)? 0xFE : 0x00"
Exists: Always

6.1.8 config3_id
■ Size: 8 bits
■ Offset: 0x7
■ Exists: Always
Memory
1 confahbauddma R Indicates that the audio interface is AHB AUD DMA
Value After Reset: "(AHBAUDDMAIF== 1) ? 1 : 0"
Exists: Always
0 confgpaud R Indicates that the audio interface is Generic Parallel Audio
(GPAUD)
Value After Reset: "(GPAUDPORTS== 1) ? 1 : 0"
Exists: Always

6.2 Interrupt Registers

Interrupt Registers. Follow the link for the register to see a detailed description of the register.
Table 6-14 Registers for Address Block: Interrupt

ih_fc_stat0 on page 197 0x100 Frame Composer Interrupt Status Register 0 (Packet Interrupts)
ih_as_stat0 on page 200 0x103 Audio Sampler Interrupt Status Register (FIFO Threshold,
Underflow and Overflow Interrupts)
ih_phy_stat0 on page 201 0x104 PHY Interface Interrupt Status Register (RXSENSE, PLL Lock
and HPD Interrupts)
ih_i2cm_stat0 on page 202 0x105 E-DDC I2C Master Interrupt Status Register (Done and Error
Interrupts)
ih_cec_stat0 on page 203 0x106 CEC Interrupt Status Register (Functional Operation Interrupts)
ih_vp_stat0 on page 204 0x107 Video Packetizer Interrupt Status Register (FIFO Full and Empty
Interrupts)
ih_i2cmphy_stat0 on page 205 0x108 PHY GEN2 I2C Master Interrupt Status Register (Done and Error
Interrupts)
ih_ahbdmaaud_stat0 on page 206 0x109 AHB Audio DMA Interrupt Status Register (Functional Operation,
Buffer Full and Empty...
ih_decode on page 207 0x170 Interruption Handler Decode Assist Register
ih_mute_fc_stat0 on page 208 0x180 Frame Composer Interrupt Mute Control Register 0
ih_mute_as_stat0 on page 211 0x183 Audio Sampler Interrupt Mute Control Register
ih_mute_phy_stat0 on page 212 0x184 PHY Interface Interrupt Mute Control Register
ih_mute_i2cm_stat0 on page 213 0x185 E-DDC I2C Master Interrupt Mute Control Register
ih_mute_cec_stat0 on page 214 0x186 CEC Interrupt Mute Control Register
ih_mute_vp_stat0 on page 215 0x187 Video Packetizer Interrupt Mute Control Register
ih_mute_i2cmphy_stat0 on page 216 0x188 PHY GEN2 I2C Master Interrupt Mute Control Register
ih_mute_ahbdmaaud_stat0 on page 217 0x189 AHB Audio DMA Interrupt Mute Control Register
ih_mute on page 218 0x1ff Global Interrupt Mute Control Register

6.2.1 ih_fc_stat0
■ Description: Frame Composer Interrupt Status Register 0 (Packet Interrupts)
■ Size: 8 bits
■ Offset: 0x100
■ Exists: Always
Table 6-15 Fields for Register: ih_fc_stat0
Memory
7 AUDI R/W1C Active after successful transmission of an Audio InfoFrame packet.
Exists: Always
6 ACP R/W1C Active after successful transmission of an Audio Content Protection
packet.
Exists: Always
5 HBR R/W1C Active after successful transmission of an Audio HBR packet.
Exists: Always
4 MAS R/W1C Active after successful transmission of an MultiStream Audio packet
Exists: DWC_HDMI_TX_20==1
3 NVBI R/W1C Active after successful transmission of an NTSC VBI packet
2 AUDS R/W1C Active after successful transmission of an Audio Sample packet. Due to
high number of audio sample packets transmitted, this interrupt is by
default masked at frame composer.
Exists: Always
1 ACR R/W1C Active after successful transmission of an Audio Clock Regeneration
(N/CTS transmission) packet.
Exists: Always
0 NULL R/W1C Active after successful transmission of an Null packet. Due to high
number of audio sample packets transmitted, this interrupt is by default
masked at frame composer.
Exists: Always

6.2.2 ih_fc_stat1
■ Size: 8 bits
■ Offset: 0x101
■ Exists: Always
Memory
7 GMD R/W1C Active after successful transmission of an Gamut metadata packet.
Exists: Always
6 ISCR1 R/W1C Active after successful transmission of an International Standard
Recording Code 1 packet.
Exists: Always
5 ISCR2 R/W1C Active after successful transmission of an International Standard
Recording Code 2 packet
Exists: Always
4 VSD R/W1C Active after successful transmission of an Vendor Specific Data
InfoFrame packet.
Exists: Always
3 SPD R/W1C Active after successful transmission of an Source Product Descriptor
InfoFrame packet.
Exists: Always
2 AMP R/W1C Active after successful transmission of an Audio Metadata packet
1 AVI R/W1C Active after successful transmission of an AVI InfoFrame packet.
Exists: Always
0 GCP R/W1C Active after successful transmission of an General Control Packet.
Exists: Always

6.2.3 ih_fc_stat2
■ Size: 8 bits
■ Offset: 0x102
■ Exists: Always
Memory
4 DRM R/W1C Active after successful transmission of an DRM packet
1 LowPriority_overflow R/W1C Frame Composer low priority packet queue descriptor
overflow indication
Exists: Always
0 HighPriority_overflow R/W1C Frame Composer high priority packet queue descriptor
overflow indication
Exists: Always

6.2.4 ih_as_stat0
■ Description: Audio Sampler Interrupt Status Register (FIFO Threshold, Underflow and Overflow
Interrupts)
■ Size: 8 bits
■ Offset: 0x103
■ Exists: Always
Table 6-18 Fields for Register: ih_as_stat0
Memory
4 fifo_underrun R/W1C Indicates an underrun on the audio FIFO
Exists: AHBAUDDMAIF== 1
3 fifo_overrun R/W1C Indicates an overrun on the audio FIFO.
Exists: Always
2 Aud_fifo_underflow_thr R/W1C Audio Sampler audio FIFO empty threshold (four samples)
indication for the legacy HBR audio interface.
For AHB_DMA, this bit indicates that the number of samples
in the FIFO is equal to (or less) than the number of active
audio channels.
This bit is not relevant for I2S, SPDIF, and GPA interfaces.
Exists: Always
1 Aud_fifo_underflow R/W1C Audio Sampler audio FIFO empty indication.
Exists: Always
0 Aud_fifo_overflow R/W1C Audio Sampler audio FIFO full indication.
Exists: Always

6.2.5 ih_phy_stat0
■ Description: PHY Interface Interrupt Status Register (RXSENSE, PLL Lock and HPD Interrupts)
■ Size: 8 bits
■ Offset: 0x104
■ Exists: Always
Table 6-19 Fields for Register: ih_phy_stat0
Memory
5 RX_SENSE_3 R/W1C TX PHY RX_SENSE indication for driver 3. You may need to
mask or change polarity of this interrupt after it has become
active.
Exists: Always
active.
Exists: Always
active.
Exists: Always
active.
Exists: Always
1 TX_PHY_LOCK R/W1C TX PHY PLL lock indication. For more information, refer to
the PHY databook. You may need to mask or change polarity
of this interrupt after it has become active.
Exists: Always
0 HPD R/W1C HDMI Hot Plug Detect indication. You may need to mask or
change polarity of this interrupt after it has become active.
Exists: Always

6.2.6 ih_i2cm_stat0
■ Description: E-DDC I2C Master Interrupt Status Register (Done and Error Interrupts)
■ Size: 8 bits
■ Offset: 0x105
■ Exists: Always
Table 6-20 Fields for Register: ih_i2cm_stat0
Memory
2 scdc_readreq R/W1C I2C Master SCDC read request indication.
1 I2Cmasterdone R/W1C I2C Master done indication
Exists: Always
0 I2Cmastererror R/W1C I2C Master error indication
Exists: Always

6.2.7 ih_cec_stat0
■ Description: CEC Interrupt Status Register (Functional Operation Interrupts)
■ Size: 8 bits
■ Offset: 0x106
■ Exists: CEC==1
Table 6-21 Fields for Register: ih_cec_stat0
Memory
6 WAKEUP R/W1C CEC Wake-up indication
Exists: Always
5 ERROR_FOLLOW R/W1C CEC Error Follow indication
Exists: Always
4 ERROR_INITIATOR R/W1C CEC Error Initiator indication
Exists: Always
3 ARB_LOST R/W1C CEC Arbitration Lost indication
Exists: Always
2 NACK R/W1C CEC Not Acknowledge indication
Exists: Always
1 EOM R/W1C CEC End of Message Indication
Exists: Always
0 DONE R/W1C CEC Done Indication
Exists: Always

6.2.8 ih_vp_stat0
■ Description: Video Packetizer Interrupt Status Register (FIFO Full and Empty Interrupts)
■ Size: 8 bits
■ Offset: 0x107
■ Exists: Always
Table 6-22 Fields for Register: ih_vp_stat0
Memory
7 fifofullrepet R/W1C Video Packetizer pixel repeater FIFO full interrupt
Exists: Always
6 fifoemptyrepet R/W1C Video Packetizer pixel repeater FIFO empty interrupt
Exists: Always
5 fifofullpp R/W1C Video Packetizer pixel packing FIFO full interrupt
Exists: Always
4 fifoemptypp R/W1C Video Packetizer pixel packing FIFO empty interrupt
Exists: Always
3 fifofullremap R/W1C Video Packetizer pixel YCC 422 re-mapper FIFO full
interrupt
Exists: Always
2 fifoemptyremap R/W1C Video Packetizer pixel YCC 422 re-mapper FIFO empty
interrupt
Exists: Always

6.2.9 ih_i2cmphy_stat0
■ Description: PHY GEN2 I2C Master Interrupt Status Register (Done and Error Interrupts)
■ Size: 8 bits
■ Offset: 0x108
■ Exists: PHY_GEN2==1 || PHY_EXTERNAL==1
Table 6-23 Fields for Register: ih_i2cmphy_stat0
Memory
1 I2Cmphydone R/W1C I2C Master PHY done indication
Exists: Always
0 I2Cmphyerror R/W1C I2C Master PHY error indication
Exists: Always

6.2.10 ih_ahbdmaaud_stat0
■ Description: AHB Audio DMA Interrupt Status Register (Functional Operation, Buffer Full and
Empty Interrupts)
■ Size: 8 bits
■ Offset: 0x109
■ Exists: AHBAUDDMAIF==1
Table 6-24 Fields for Register: ih_ahbdmaaud_stat0
Memory
6 ahbdmaaud_intbuffoverrun R/W1C AHB audio DMA Buffer overrun interruption
Exists: Always
5 ahbdmaaud_interror R/W1C AHB audio DMA error interrupt
Exists: Always
4 ahbdmaaud_intlostownership R/W1C AHB audio DMA lost ownership interrupt
Exists: Always
3 ahbdmaaud_intretrysplit R/W1C AHB audio DMA RETRY/SPLIT interrupt
Exists: Always
2 ahbdmaaud_intdone R/W1C AHB audio DMA done interrupt
Exists: Always
1 ahbdmaaud_intbufffull R/W1C AHB audio DMA Buffer full interrupt
Exists: Always
0 ahbdmaaud_intbuffempty R/W1C AHB audio DMA Buffer empty interrupt
Exists: Always

6.2.11 ih_decode
■ Description: Interruption Handler Decode Assist Register
■ Size: 8 bits
■ Offset: 0x170
■ Exists: Always
Table 6-25 Fields for Register: ih_decode
Memory
7 ih_fc_stat0 R Interruption active at the ih_fc_stat0 register
Exists: Always
6 ih_fc_stat1 R Interruption active at the ih_fc_stat1 register
Exists: Always
5 ih_fc_stat2_vp R Interruption active at the ih_fc_stat2 or ih_vp_stat0 register
Exists: Always
4 ih_as_stat0 R Interruption active at the ih_as_stat0 register
Exists: Always
3 ih_phy R Interruption active at the ih_phy_stat0 or ih_i2cmphy_stat0
register
Exists: Always
2 ih_i2cm_stat0 R Interruption active at the ih_i2cm_stat0 register
Exists: Always
1 ih_cec_stat0 R Interruption active at the ih_cec_stat0 register
Exists: Always
0 ih_ahbdmaaud_stat0 R Interruption active at the ih_ahbdmaaud_stat0 register
Exists: Always

6.2.12 ih_mute_fc_stat0
■ Description: Frame Composer Interrupt Mute Control Register 0
■ Size: 8 bits
■ Offset: 0x180
■ Exists: Always
Table 6-26 Fields for Register: ih_mute_fc_stat0
Memory
7 AUDI R/W When set to 1, mutes ih_fc_stat0[7]
Exists: Always
6 ACP R/W When set to 1, mutes ih_fc_stat0[6]
Exists: Always
5 HBR R/W When set to 1, mutes ih_fc_stat0[5]
Exists: Always
4 MAS R/W When set to 1, mutes ih_fc_stat0[4]. Otherwise, this field is a
"spare" bit with no associated functionality.
3 NVBI R/W When set to 1, mutes ih_fc_stat0[3]. Otherwise, this field is a
2 AUDS R/W When set to 1, mutes ih_fc_stat0[2]
Exists: Always
1 ACR R/W When set to 1, mutes ih_fc_stat0[1]
Exists: Always
0 NULL R/W When set to 1, mutes ih_fc_stat0[0]
Exists: Always

■ Size: 8 bits
■ Offset: 0x181
■ Exists: Always
Memory
7 GMD R/W When set to 1, mutes ih_fc_stat1[7]
Exists: Always
6 ISCR1 R/W When set to 1, mutes ih_fc_stat1[6]
Exists: Always
5 ISCR2 R/W When set to 1, mutes ih_fc_stat1[5]
Exists: Always
4 VSD R/W When set to 1, mutes ih_fc_stat1[4]
Exists: Always
3 SPD R/W When set to 1, mutes ih_fc_stat1[3]
Exists: Always
2 AMP R/W When set to 1, mutes ih_fc_stat1[2]. Otherwise, this field is a
1 AVI R/W When set to 1, mutes ih_fc_stat1[1]
Exists: Always
0 GCP R/W When set to 1, mutes ih_fc_stat1[0]
Exists: Always

■ Size: 8 bits
■ Offset: 0x182
■ Exists: Always
Memory
4 DRM R/W When set to 1, mutes ih_fc_stat2[4].
1 LowPriority_overflow R/W When set to 1, mutes ih_fc_stat2[1]
Exists: Always
0 HighPriority_overflow R/W When set to 1, mutes ih_fc_stat2[0]
Exists: Always

6.2.15 ih_mute_as_stat0
■ Description: Audio Sampler Interrupt Mute Control Register
■ Size: 8 bits
■ Offset: 0x183
■ Exists: Always
Table 6-29 Fields for Register: ih_mute_as_stat0
Memory
4 fifo_underrun R/W When set to 1, mutes ih_as_stat0[4]
Exists: AHBAUDDMAIF== 1
3 fifo_overrun R/W When set to 1, mutes ih_as_stat0[3]
Exists: Always
2 Aud_fifo_underflow_thr R/W When set to 1, mutes ih_as_stat0[2]
Exists: Always
1 Aud_fifo_underflow R/W When set to 1, mutes ih_as_stat0[1]
Exists: Always
0 Aud_fifo_overflow R/W When set to 1, mutes ih_as_stat0[0]
Exists: Always

6.2.16 ih_mute_phy_stat0
■ Description: PHY Interface Interrupt Mute Control Register
■ Size: 8 bits
■ Offset: 0x184
■ Exists: Always
Table 6-30 Fields for Register: ih_mute_phy_stat0
Memory
5 RX_SENSE_3 R/W When set to 1, mutes ih_phy_stat0[5]
Exists: Always
Exists: Always
Exists: Always
Exists: Always
1 TX_PHY_LOCK R/W When set to 1, mutes ih_phy_stat0[1]
Exists: Always
0 HPD R/W When set to 1, mutes ih_phy_stat0[0]
Exists: Always

6.2.17 ih_mute_i2cm_stat0
■ Description: E-DDC I2C Master Interrupt Mute Control Register
■ Size: 8 bits
■ Offset: 0x185
■ Exists: Always
Table 6-31 Fields for Register: ih_mute_i2cm_stat0
Memory
2 scdc_readreq R/W When set to 1, mutes ih_i2cm_stat0[2]
1 I2Cmasterdone R/W When set to 1, mutes ih_i2cm_stat0[1]
Exists: Always
0 I2Cmastererror R/W When set to 1, mutes ih_i2cm_stat0[0]
Exists: Always

6.2.18 ih_mute_cec_stat0
■ Description: CEC Interrupt Mute Control Register
■ Size: 8 bits
■ Offset: 0x186
■ Exists: CEC==1
Table 6-32 Fields for Register: ih_mute_cec_stat0
Memory
6 WAKEUP R/W When set to 1, mutes ih_cec_stat0[6]
Exists: Always
5 ERROR_FOLLOW R/W When set to 1, mutes ih_cec_stat0[5]
Exists: Always
4 ERROR_INITIATOR R/W When set to 1, mutes ih_cec_stat0[4]
Exists: Always
3 ARB_LOST R/W When set to 1, mutes ih_cec_stat0[3]
Exists: Always
2 NACK R/W When set to 1, mutes ih_cec_stat0[2]
Exists: Always
1 EOM R/W When set to 1, mutes ih_cec_stat0[1]
Exists: Always
0 DONE R/W When set to 1, mutes ih_cec_stat0[0]
Exists: Always

6.2.19 ih_mute_vp_stat0
■ Description: Video Packetizer Interrupt Mute Control Register
■ Size: 8 bits
■ Offset: 0x187
■ Exists: Always
Table 6-33 Fields for Register: ih_mute_vp_stat0
Memory
7 fifofullrepet R/W When set to 1, mutes ih_vp_stat0[7]
Exists: Always
6 fifoemptyrepet R/W When set to 1, mutes ih_vp_stat0[6]
Exists: Always
5 fifofullpp R/W When set to 1, mutes ih_vp_stat0[5]
Exists: Always
4 fifoemptypp R/W When set to 1, mutes ih_vp_stat0[4]
Exists: Always
3 fifofullremap R/W When set to 1, mutes ih_vp_stat0[3]
Exists: Always
2 fifoemptyremap R/W When set to 1, mutes ih_vp_stat0[2]
Exists: Always
1 spare_2 R/W Reserved as "spare" bit with no associated functionality.
Exists: Always
Exists: Always

6.2.20 ih_mute_i2cmphy_stat0
■ Description: PHY GEN2 I2C Master Interrupt Mute Control Register
■ Size: 8 bits
■ Offset: 0x188
Table 6-34 Fields for Register: ih_mute_i2cmphy_stat0
Memory
1 I2Cmphydone R/W When set to 1, mutes ih_i2cmphy_stat0[1]
Exists: Always
0 I2Cmphyerror R/W When set to 1, mutes ih_i2cmphy_stat0[0]
Exists: Always

6.2.21 ih_mute_ahbdmaaud_stat0
■ Description: AHB Audio DMA Interrupt Mute Control Register
■ Size: 8 bits
■ Offset: 0x189
Table 6-35 Fields for Register: ih_mute_ahbdmaaud_stat0
Memory
6 ahbdmaaud_intbuffoverrun R/W When set to 1, mutes ih_ahbdmaaud_stat0[6]
Exists: Always
5 ahbdmaaud_interror R/W When set to 1, mutes ih_ahbdmaaud_stat0[5]
Exists: Always
4 ahbdmaaud_intlostownership R/W When set to 1, mutes ih_ahbdmaaud_stat0[4]
Exists: Always
3 ahbdmaaud_intretrysplit R/W When set to 1, mutes ih_ahbdmaaud_stat0[3]
Exists: Always
2 ahbdmaaud_intdone R/W When set to 1, mutes ih_ahbdmaaud_stat0[2]
Exists: Always
1 ahbdmaaud_intbufffull R/W When set to 1, mutes ih_ahbdmaaud_stat0[1]
Exists: Always
0 ahbdmaaud_intbuffempty R/W When set to 1, mutes ih_ahbdmaaud_stat0[0]
Exists: Always

6.2.22 ih_mute
■ Description: Global Interrupt Mute Control Register
■ Size: 8 bits
■ Offset: 0x1ff
■ Exists: Always
Table 6-36 Fields for Register: ih_mute
Memory
1 mute_wakeup_interrupt R/W When set to 1, mutes the main interrupt output port. The
sticky bit interrupts continue with their state accessible
through the configuration bus, only the main interrupt line is
muted.
Exists: Always
0 mute_all_interrupt R/W When set to 1, mutes the main interrupt line (where all
interrupts are ORed). The sticky bit interrupts continue with
their state; only the main interrupt line is muted.
Exists: Always

6.3 VideoSampler Registers

Video Sampler Registers. Follow the link for the register to see a detailed description of the register.
Table 6-37 Registers for Address Block: VideoSampler

tx_invid0 on page 220 0x200 Video Input Mapping and Internal Data Enable Configuration
Register
tx_instuffing on page 222 0x201 Video Input Stuffing Enable Register
tx_gydata0 on page 223 0x202 Video Input gy Data Channel Stuffing Register 0
tx_gydata1 on page 223 0x203 Video Input gy Data Channel Stuffing Register 1
tx_rcrdata0 on page 224 0x204 Video Input rcr Data Channel Stuffing Register 0
tx_rcrdata1 on page 224 0x205 Video Input rcr Data Channel Stuffing Register 1
tx_bcbdata0 on page 225 0x206 Video Input bcb Data Channel Stuffing Register 0
tx_bcbdata1 on page 225 0x207 Video Input bcb Data Channel Stuffing Register 1

6.3.1 tx_invid0
■ Description: Video Input Mapping and Internal Data Enable Configuration Register
■ Size: 8 bits
■ Offset: 0x200
■ Exists: Always
Table 6-38 Fields for Register: tx_invid0
Memory
7 internal_de_generator R/W Internal data enable (DE) generator enable. If data enable is not
available for the input video, set this bit to one to activate the internal
data enable generator.
Attention: This feature only works for input video modes that have
native repetition (such as, all CEA videos). No desired pixel repetition
can be used with this feature because these configurations only affect
the Frame Composer and not this block.
The DE Generator does not work for the following conditions:
■ Transmission of video with CEA VIC 39
■ Transmission of 3D video using the field alternative structure
Exists: Always

Table 6-38 Fields for Register: tx_invid0 (Continued)
Memory
4:0 video_mapping R/W Video Input mapping (color space/color depth):
0x01: RGB 4:4:4/8 bits
0x03: RGB 4:4:4/10 bits
0x05: RGB 4:4:4/12 bits
0x07: RGB 4:4:4/16 bits
0x09: YCbCr 4:4:4 or 4:2:0/8 bits
0x0B: YCbCr 4:4:4 or 4:2:0/10 bits
0x0D: YCbCr 4:4:4 or 4:2:0/12 bits
0x0F: YCbCr 4:4:4 or 4:2:0/16 bits
0x16: YCbCr 4:2:2/8 bits
0x17: YCbCr 4:4:4 (IPI)/8 bits
0x1A: YCbCr 4:4:4 (IPI)/16 bits
0x1B: YCbCr 4:2:2 (IPI)/12 bits
0x1C: YCbCr 4:2:0 (IPI)/8 bits
0x1D: YCbCr 4:2:0 (IPI)/10 bits
0x1E: YCbCr 4:2:0 (IPI)/12 bits
0x1F: YCbCr 4:2:0 (IPI)/16 bits
Exists: Always

6.3.2 tx_instuffing
■ Description: Video Input Stuffing Enable Register
■ Size: 8 bits
■ Offset: 0x201
■ Exists: Always
Table 6-39 Fields for Register: tx_instuffing
Memory
2 bcbdata_stuffing R/W ■ 0b: When the dataen signal is low, the value in the
bcbdata[15:0] output is the one sampled from the
corresponding input data.
■ 1b: When the dataen signal is low, the value in the
bcbdata[15:0] output is given by the values in the
TX_BCBDTA0 and TX_BCBDATA1 registers.
Exists: Always
1 rcrdata_stuffing R/W ■ 0b: When the dataen signal is low, the value in the
rcrdata[15:0] output is the one sampled from the
rcrdata[15:0] output is given by the values in
TX_RCRDTA0 and TX_RCRDATA1 registers.
Exists: Always
0 gydata_stuffing R/W ■ 0b: When the dataen signal is low, the value in the
gydata[15:0] output is the one sampled from the
gydata[15:0] output is given by the values in TX_GYDTA0
and TX_GYDATA1 registers.
Exists: Always

6.3.3 tx_gydata0
■ Description: Video Input gy Data Channel Stuffing Register 0
■ Size: 8 bits
■ Offset: 0x202
■ Exists: Always
Table 6-40 Fields for Register: tx_gydata0
Memory
7:0 gydata R/W This register defines the value of gydata[7:0] when
TX_INSTUFFING[0] (gydata_stuffing) is set to 1b.
Exists: Always
6.3.4 tx_gydata1
■ Description: Video Input gy Data Channel Stuffing Register 1
■ Size: 8 bits
■ Offset: 0x203
■ Exists: Always
Table 6-41 Fields for Register: tx_gydata1
Memory
7:0 gydata R/W This register defines the value of gydata[15:8] when
TX_INSTUFFING[0] (gydata_stuffing) is set to 1b.
Exists: Always

6.3.5 tx_rcrdata0
■ Description: Video Input rcr Data Channel Stuffing Register 0
■ Size: 8 bits
■ Offset: 0x204
■ Exists: Always
Table 6-42 Fields for Register: tx_rcrdata0
Memory
7:0 rcrdata R/W This register defines the value of rcrydata[7:0] when
TX_INSTUFFING[1] (rcrdata_stuffing) is set to 1b.
Exists: Always
6.3.6 tx_rcrdata1
■ Description: Video Input rcr Data Channel Stuffing Register 1
■ Size: 8 bits
■ Offset: 0x205
■ Exists: Always
Table 6-43 Fields for Register: tx_rcrdata1
Memory
7:0 rcrdata R/W This register defines the value of rcrydata[15:8] when
TX_INSTUFFING[1] (rcrdata_stuffing) is set to 1b.
Exists: Always

6.3.7 tx_bcbdata0
■ Description: Video Input bcb Data Channel Stuffing Register 0
■ Size: 8 bits
■ Offset: 0x206
■ Exists: Always
Table 6-44 Fields for Register: tx_bcbdata0
Memory
7:0 bcbdata R/W This register defines the value of bcbdata[7:0] when
TX_INSTUFFING[2] (bcbdata_stuffing) is set to 1b.
Exists: Always
6.3.8 tx_bcbdata1
■ Description: Video Input bcb Data Channel Stuffing Register 1
■ Size: 8 bits
■ Offset: 0x207
■ Exists: Always
Table 6-45 Fields for Register: tx_bcbdata1
Memory
7:0 bcbdata R/W This register defines the value of bcbdata[15:8] when
TX_INSTUFFING[2] (bcbdata_stuffing) is set to 1b.
Exists: Always

6.4 VideoPacketizer Registers

Video Packetizer Registers. Follow the link for the register to see a detailed description of the register.
Table 6-46 Registers for Address Block: VideoPacketizer

vp_status on page 227 0x800 Video Packetizer Packing Phase Status Register
vp_pr_cd on page 228 0x801 Video Packetizer Pixel Repetition and Color Depth Register
vp_stuff on page 230 0x802 Video Packetizer Stuffing and Default Packing Phase
Register
vp_remap on page 232 0x803 Video Packetizer YCC422 Remapping Register
vp_conf on page 233 0x804 Video Packetizer Output and Enable Configuration Register
vp_mask on page 234 0x807 Video Packetizer Interrupt Mask Register

6.4.1 vp_status
■ Description: Video Packetizer Packing Phase Status Register
■ Size: 8 bits
■ Offset: 0x800
■ Exists: Always
Table 6-47 Fields for Register: vp_status
Memory
3:0 packing_phase R Read only register that holds the "packing phase" output of
the Video Packetizer block. For more information about
"packing" video data, refer to the HDMI 1.4b specification.
The register is updated at TMDS clock rate.
Exists: Always

6.4.2 vp_pr_cd
■ Description: Video Packetizer Pixel Repetition and Color Depth Register
■ Size: 8 bits
■ Offset: 0x801
■ Exists: Always
Table 6-48 Fields for Register: vp_pr_cd
Memory
7:4 color_depth R/W The Color depth configuration is described as the following,
with the action stated corresponding to color_depth[3:0]:
■ 0000b: 24 bits per pixel video (8 bits per component). 8-
bit packing mode.
■ 0001b-0011b: Reserved. Not used.
■ 0100b: 24 bits per pixel video (8 bits per component). 8-
bit packing mode.
■ 0101b: 30 bits per pixel video (10 bits per component).
10-bit packing mode.
■ Other: Reserved. Not used.
Exists: Always

Table 6-48 Fields for Register: vp_pr_cd (Continued)
Memory
3:0 desired_pr_factor R/W Desired pixel repetition factor configuration. The configured
value sets H13T PHY PLL to multiply pixel clock by the factor
in order to obtain the desired repetition clock. For the CEA
modes some are already defined with pixel repetition in the
input video. So for CEA modes this shall be always 0. Shall
only be used if the user wants to do pixel repetition using
H13TCTRL controller.
The action is stated corresponding to desired_pr_factor[3:0]:
■ 0000b: No pixel repetition (pixel sent only once)
■ 0001b: Pixel sent two times (pixel repeated once)
■ 0010b: Pixel sent three times
■ 0011b: Pixel sent four times
■ 0100b: Pixel sent five times
■ 0101b: Pixel sent six times
■ 0110b: Pixel sent seven times
■ 0111b: Pixel sent eight times
■ 1000b: Pixel sent nine times
■ 1001b: Pixel sent 10 times
■ Other: Reserved. Not used
Exists: Always

6.4.3 vp_stuff
■ Description: Video Packetizer Stuffing and Default Packing Phase Register
■ Size: 8 bits
■ Offset: 0x802
■ Exists: Always
Table 6-49 Fields for Register: vp_stuff
Memory
5 idefault_phase R/W Controls the default phase packing machine used according
to HDMI 1.4b specification:
“If the transmitted video format has timing such that the
phase of the first pixel of every Video Data Period
corresponds to pixel packing phase 0 (e.g. 10P0, 12P0,
16P0), the Source may set the Default_Phase bit in the GCP.
The Sink may use this bit to optimize its filtering or handling
of the PP field.”
This means that for 10-bit mode the Htotal must be dividable
by 4; for 12-bit mode, the Htotal must be divisible by 2.
Exists: Always
4 ifix_pp_to_last R/W Reserved. Controls packing machine strategy
Exists: Always
3 icx_goto_p0_st R/W Reserved. Controls packing machine strategy
Exists: Always
2 ycc422_stuffing R/W YCC 422 remap stuffing control. For horizontal blanking, the
action is stated corresponding to ycc422_stuffing:
0b: YCC 422 remap block in direct mode (input blanking data
goes directly to output).
1b: YCC 422 remap block in stuffing mode. When "de" goes
to low the outputs are fixed to 0x00.
Exists: Always

Table 6-49 Fields for Register: vp_stuff (Continued)
Memory
1 pp_stuffing R/W Pixel packing stuffing control. The action is stated
corresponding to pp_stuffing:
0b: Pixel packing block in direct mode (input blanking data
1b: Pixel packing block in stuffing mode. When "de_rep"
goes to low the outputs are fixed to 0x00.
Exists: Always
0 pr_stuffing R/W Pixel repeater stuffing control. The action is stated
corresponding to pp_stuffing:
0b: Pixel repeater block in direct mode (input blanking data
1b: Pixel repeater block in stuffing mode. When "de" goes to
low the outputs are fixed to 0x00.
Exists: Always

6.4.4 vp_remap
■ Description: Video Packetizer YCC422 Remapping Register
■ Size: 8 bits
■ Offset: 0x803
■ Exists: Always
Table 6-50 Fields for Register: vp_remap
Memory
1:0 ycc422_size R/W YCC 422 remap input video size
ycc422_size[1:0]
00b: YCC 422 16-bit input video (8 bits per component)
11b: Reserved. Not used
Exists: Always

6.4.5 vp_conf
■ Description: Video Packetizer Output and Enable Configuration Register
■ Size: 8 bits
■ Offset: 0x804
■ Exists: Always
Table 6-51 Fields for Register: vp_conf
Memory
6 bypass_en R/W When set to 1'b1, Pixel packing enable. When set to 1b'0,
the pixel packing block is controlled by pp_en.
Exists: Always
5 pp_en R/W Pixel packing enable. When set to 0, the pixel packing block
is disabled if bypass_en is 1'b0.
Exists: Always
4 pr_en R/W Pixel repeater enable. When set to 0, the pixel repetition
block is disabled.
Exists: Always
3 ycc422_en R/W YCC 422 select enable. Disabling forces bypass module to
output always zeros.
Exists: Always
2 bypass_select R/W bypass_select
0b: Data from pixel repeater block
1b: Data from input of Video Packetizer block
Exists: Always
1 output_selector_1 R/W When set to 1'b1, Data from pixel packing block
Exists: Always
0 output_selector_0 R/W Video Packetizer output selection
0b: Data from pixel packing block 1b: Data from YCC 422
remap block
Exists: Always

6.4.6 vp_mask
■ Description: Video Packetizer Interrupt Mask Register
■ Size: 8 bits
■ Offset: 0x807
■ Exists: Always
Table 6-52 Fields for Register: vp_mask
Memory
7 ointfullrepet R/W Mask bit for Video Packetizer pixel repeater FIFO full
Exists: Always
6 ointemptyrepet R/W Mask bit for Video Packetizer pixel repeater FIFO empty
Exists: Always
5 ointfullpp R/W Mask bit for Video Packetizer pixel packing FIFO full
Exists: Always
4 ointemptypp R/W Mask bit for Video Packetizer pixel packing FIFO empty
Exists: Always
3 ointfullremap R/W Mask bit for Video Packetizer pixel YCC 422 re-mapper FIFO
full
Exists: Always
2 ointemptyremap R/W Mask bit for Video Packetizer pixel YCC 422 re-mapper FIFO
empty
Exists: Always
Exists: Always
Exists: Always

6.5 FrameComposer Registers

Frame Composer Registers. Follow the link for the register to see a detailed description of the register.
Table 6-53 Registers for Address Block: FrameComposer

fc_invidconf on page 243 0x1000 Frame Composer Input Video Configuration and HDCP
Keepout Register
fc_inhactiv0 on page 244 0x1001 Frame Composer Input Video HActive Pixels Register 0
fc_inhactiv1 on page 245 0x1002 Frame Composer Input Video HActive Pixels Register 1
fc_inhblank0 on page 245 0x1003 Frame Composer Input Video HBlank Pixels Register 0
fc_inhblank1 on page 246 0x1004 Frame Composer Input Video HBlank Pixels Register 1
fc_invactiv0 on page 246 0x1005 Frame Composer Input Video VActive Pixels Register 0
fc_invactiv1 on page 247 0x1006 Frame Composer Input Video VActive Pixels Register 1
fc_invblank on page 247 0x1007 Frame Composer Input Video VBlank Pixels Register
fc_hsyncindelay0 on page 248 0x1008 Frame Composer Input Video HSync Front Porch Register 0
fc_hsyncindelay1 on page 248 0x1009 Frame Composer Input Video HSync Front Porch Register 1
fc_hsyncinwidth0 on page 249 0x100a Frame Composer Input Video HSync Width Register 0
fc_hsyncinwidth1 on page 249 0x100b Frame Composer Input Video HSync Width Register 1
fc_vsyncindelay on page 250 0x100c Frame Composer Input Video VSync Front Porch Register
fc_vsyncinwidth on page 250 0x100d Frame Composer Input Video VSync Width Register
fc_infreq0 on page 251 0x100e Frame Composer Input Video Refresh Rate Register 0
fc_infreq1 on page 251 0x100f Frame Composer Input Video Refresh Rate Register 1
fc_infreq2 on page 252 0x1010 Frame Composer Input Video Refresh Rate Register 2
fc_ctrldur on page 252 0x1011 Frame Composer Control Period Duration Register
fc_exctrldur on page 253 0x1012 Frame Composer Extended Control Period Duration Register
fc_exctrlspac on page 253 0x1013 Frame Composer Extended Control Period Maximum
Spacing Register
fc_ch0pream on page 254 0x1014 Frame Composer Channel 0 Non-Preamble Data Register
fc_aviconf3 on page 255 0x1017 Frame Composer AVI Packet Configuration Register 3
fc_gcp on page 256 0x1018 Frame Composer GCP Packet Configuration Register
fc_aviconf0 on page 257 0x1019 Frame Composer AVI Packet Configuration Register 0
fc_aviconf1 on page 258 0x101a Frame Composer AVI Packet Configuration Register 1

Table 6-53 Registers for Address Block: FrameComposer (Continued)

fc_aviconf2 on page 259 0x101b Frame Composer AVI Packet Configuration Register 2
fc_avivid on page 260 0x101c Frame Composer AVI Packet VIC Register
fc_avietb[0:1] on page 260 0x101d + Frame Composer AVI Packet End of Top Bar Register Array
(i * 0x1)
fc_avisbb[0:1] on page 261 0x101f + Frame Composer AVI Packet Start of Bottom Bar Register
(i * 0x1) Array
fc_avielb[0:1] on page 261 0x1021 + Frame Composer AVI Packet End of Left Bar Register Array
(i * 0x1)
fc_avisrb[0:1] on page 262 0x1023 + Frame Composer AVI Packet Start of Right Bar Register
(i * 0x1) Array
fc_audiconf0 on page 262 0x1025 Frame Composer AUD Packet Configuration Register 0
fc_vsdieeeid0 on page 264 0x1029 Frame Composer VSI Packet Data IEEE Register 0
fc_vsdsize on page 265 0x102a Frame Composer VSI Packet Data Size Register
fc_vsdpayload[0:23] on page 266 0x1032 + Frame Composer VSI Packet Data Payload Register Array
(i * 0x1)
fc_spdvendorname[0:7] on page 267 0x104a + Frame Composer SPD Packet Data Vendor Name Register
(i * 0x1) Array
fc_spdproductname[0:15] on page 267 0x1052 + Frame Composer SPD packet Data Product Name Register
(i * 0x1) Array
fc_spddeviceinf on page 268 0x1062 Frame Composer SPD Packet Data Source Product
Descriptor Register
fc_audsconf on page 268 0x1063 Frame Composer Audio Sample Flat and Layout
Configuration Register
fc_audsstat on page 269 0x1064 Frame Composer Audio Sample Flat and Layout Status
Register
fc_audsv on page 270 0x1065 Frame Composer Audio Sample Validity Flag Register
fc_audsu on page 271 0x1066 Frame Composer Audio Sample User Flag Register
fc_audschnl0 on page 272 0x1067 Frame Composer Audio Sample Channel Status
Configuration Register 0


fc_audschnl3 on page 273 0x106a Frame Composer Audio Sample Channel Status
fc_audschnl4 on page 274 0x106b Frame Composer Audio Sample Channel Status
fc_audschnl5 on page 274 0x106c Frame Composer Audio Sample Channel Status
fc_audschnl6 on page 275 0x106d Frame Composer Audio Sample Channel Status
fc_audschnl7 on page 275 0x106e Frame Composer Audio Sample Channel Status
fc_audschnl8 on page 276 0x106f Frame Composer Audio Sample Channel Status
fc_ctrlqhigh on page 276 0x1073 Frame Composer Number of High Priority Packets Attended
fc_ctrlqlow on page 277 0x1074 Frame Composer Number of Low Priority Packets Attended
fc_acp0 on page 277 0x1075 Frame Composer ACP Packet Type Configuration Register 0
fc_acp16 on page 278 0x1082 Frame Composer ACP Packet Body Configuration Register
16
15
14
13
12
11
10
fc_acp9 on page 281 0x1089 Frame Composer ACP Packet Body Configuration Register 9
fc_acp8 on page 282 0x108a Frame Composer ACP Packet Body Configuration Register 8
fc_acp7 on page 282 0x108b Frame Composer ACP Packet Body Configuration Register 7
fc_acp6 on page 283 0x108c Frame Composer ACP Packet Body Configuration Register 6


fc_acp5 on page 283 0x108d Frame Composer ACP Packet Body Configuration Register 5
fc_acp4 on page 284 0x108e Frame Composer ACP Packet Body Configuration Register 4
fc_acp3 on page 284 0x108f Frame Composer ACP Packet Body Configuration Register 3
fc_iscr1_0 on page 286 0x1092 Frame Composer ISRC1 Packet Status, Valid, and Continue
fc_iscr1_16 on page 286 0x1093 Frame Composer ISRC1 Packet Body Register 16
fc_iscr1_9 on page 290 0x109a Frame Composer ISRC1 Packet Body Register 9
fc_iscr1_8 on page 290 0x109b Frame Composer ISRC1 Packet Body Register 8
fc_iscr1_7 on page 291 0x109c Frame Composer ISRC1 Packet Body Register 7
fc_iscr1_6 on page 291 0x109d Frame Composer ISRC1 Packet Body Register 6
fc_iscr1_5 on page 292 0x109e Frame Composer ISRC1 Packet Body Register 5
fc_iscr1_4 on page 292 0x109f Frame Composer ISRC1 Packet Body Register 4
fc_iscr1_3 on page 293 0x10a0 Frame Composer ISRC1 Packet Body Register 3
fc_iscr2_8 on page 298 0x10aa Frame Composer ISRC2 Packet Body Register 8
fc_iscr2_7 on page 298 0x10ab Frame Composer ISRC2 Packet Body Register 7


fc_iscr2_6 on page 299 0x10ac Frame Composer ISRC2 Packet Body Register 6
fc_iscr2_5 on page 299 0x10ad Frame Composer ISRC2 Packet Body Register 5
fc_iscr2_4 on page 300 0x10ae Frame Composer ISRC2 Packet Body Register 4
fc_iscr2_3 on page 300 0x10af Frame Composer ISRC2 Packet Body Register 3
fc_iscr2_2 on page 301 0x10b0 Frame Composer ISRC2 Packet Body Register 2
fc_datauto0 on page 303 0x10b3 Frame Composer Data Island Auto Packet Scheduling
Register 0 Configures the Frame Composer
RDRB(1)/Manual(0)...
Register 1 Configures the Frame Composer (FC)...
fc_datauto2 on page 304 0x10b5 Frame Composer Data Island Auto packet scheduling
fc_datman on page 305 0x10b6 Frame Composer Data Island Manual Packet Request
Register Requests to the Frame Composer the data...
Register 3 Configures the Frame Composer
Automatic(1)/RDRB(0)...
fc_rdrb0 on page 307 0x10b8 Frame Composer Round Robin ACR Packet Insertion
Register 0 Configures the Frame Composer (FC) RDRB...
fc_rdrb1 on page 307 0x10b9 Frame Composer Round Robin ACR Packet Insertion
fc_rdrb2 on page 308 0x10ba Frame Composer Round Robin AUDI Packet Insertion
fc_rdrb3 on page 308 0x10bb Frame Composer Round Robin AUDI Packet Insertion
fc_rdrb4 on page 309 0x10bc Frame Composer Round Robin GCP Packet Insertion
fc_rdrb5 on page 309 0x10bd Frame Composer Round Robin GCP Packet Insertion
fc_rdrb6 on page 310 0x10be Frame Composer Round Robin AVI Packet Insertion
fc_rdrb7 on page 310 0x10bf Frame Composer Round Robin AVI Packet Insertion
fc_rdrb8 on page 311 0x10c0 Frame Composer Round Robin AMP Packet Insertion
Register 8


fc_rdrb9 on page 311 0x10c1 Frame Composer Round Robin AMP Packet Insertion
Register 9
fc_rdrb10 on page 312 0x10c2 Frame Composer Round Robin NTSC VBI Packet Insertion
Register 10
fc_rdrb11 on page 312 0x10c3 Frame Composer Round Robin NTSC VBI Packet Insertion
Register 11
fc_rdrb12 on page 313 0x10c4 Frame Composer Round Robin DRM Packet Insertion
Register 12
fc_rdrb13 on page 313 0x10c5 Frame Composer Round Robin DRM Packet Insertion
Register 13
fc_mask0 on page 314 0x10d2 Frame Composer Packet Interrupt Mask Register 0
fc_mask1 on page 315 0x10d6 Frame Composer Packet Interrupt Mask Register 1
fc_mask2 on page 316 0x10da Frame Composer High/Low Priority Overflow and DRM
Interrupt Mask Register 2
fc_prconf on page 317 0x10e0 Frame Composer Pixel Repetition Configuration Register
fc_scrambler_ctrl on page 319 0x10e1 Frame Composer Scrambler Control
fc_multistream_ctrl on page 320 0x10e2 Frame Composer Multi-Stream Audio Control
fc_packet_tx_en on page 321 0x10e3 Frame Composer Packet Transmission Control
fc_actspc_hdlr_cfg on page 323 0x10e8 Frame Composer Active Space Control
fc_invact_2d_0 on page 323 0x10e9 Frame Composer Input Video 2D VActive Pixels Register 0
fc_invact_2d_1 on page 324 0x10ea Frame Composer Input Video VActive pixels Register 1
fc_gmd_stat on page 325 0x1100 Frame Composer GMD Packet Status Register Gamut
metadata packet status bit information for no_current_gmd,...
fc_gmd_en on page 326 0x1101 Frame Composer GMD Packet Enable Register This register
enables Gamut metadata (GMD) packet transmission....
fc_gmd_up on page 327 0x1102 Frame Composer GMD Packet Update Register This register
performs an GMD packet content update according...
fc_gmd_conf on page 328 0x1103 Frame Composer GMD Packet Schedule Configuration
Register This register configures the number of...
fc_gmd_hb on page 329 0x1104 Frame Composer GMD Packet Profile and Gamut Sequence
Configuration Register This register configures...
fc_gmd_pb[0:27] on page 330 0x1105 + Frame Composer GMD Packet Body Register Array
(i * 0x1) Configures the GMD packet body of the GMD...
fc_amp_hb1 on page 330 0x1128 Frame Composer AMP Packet Header Register 1
fc_amp_hb2 on page 331 0x1129 Frame Composer AMP Packet Header Register 2


fc_amp_pb[0:27] on page 331 0x112a + Frame Composer AMP Packet Body Register Array
(i * 0x1)
fc_nvbi_hb1 on page 332 0x1148 Frame Composer NTSC VBI Packet Header Register 1
fc_nvbi_hb2 on page 332 0x1149 Frame Composer NTSC VBI Packet Header Register 2
fc_nvbi_pb[0:26] on page 333 0x114a + Frame Composer NTSC VBI Packet Body Register Array
(i * 0x1)
fc_drm_up on page 333 0x1167 Frame Composer DRM Packet Update Register This register
performs an DRM packet content update according...
fc_drm_hb[0:1] on page 334 0x1168 + Frame Composer DRM Packet Header Register Array
(i * 0x1)
fc_drm_pb[0:26] on page 334 0x116a + Frame Composer DRM Packet Body Register Array
(i * 0x1)
fc_dbgforce on page 335 0x1200 Frame Composer video/audio Force Enable Register This
register allows to force the controller to...
fc_dbgaud0ch0 on page 335 0x1201 Frame Composer Audio Data Channel 0 Register 0
Configures the audio fixed data to be used in channel...
fc_dbgaud0ch3 on page 340 0x120a Frame Composer Audio Data Channel 3 Register 0
fc_dbgaud1ch3 on page 340 0x120b Frame Composer Audio Data Channel 3 Register 1
fc_dbgaud2ch3 on page 341 0x120c Frame Composer Audio Data Channel 3 Register 2


fc_dbgaud0ch4 on page 341 0x120d Frame Composer Audio Data Channel 4 Register 0
fc_dbgaud1ch4 on page 342 0x120e Frame Composer Audio Data Channel 4 Register 1
fc_dbgaud2ch4 on page 342 0x120f Frame Composer Audio Data Channel 4 Register 2
fc_dbgtmds[0:2] on page 347 0x1219 + Frame Composer TMDS Data Channel Register Array
(i * 0x1) Configures the video fixed data to be used in TMDS...

6.5.1 fc_invidconf
■ Description: Frame Composer Input Video Configuration and HDCP Keepout Register
■ Size: 8 bits
■ Offset: 0x1000
■ Exists: Always
Table 6-54 Fields for Register: fc_invidconf
Memory
7 HDCP_keepout R/W Start/stop HDCP keepout window generation
1b: Active
Exists: Always
6 vsync_in_polarity R/W Vsync input polarity
1b: Active high
0b: Active low
Exists: Always
5 hsync_in_polarity R/W Hsync input polarity
1b: Active high
0b: Active low
Exists: Always
4 de_in_polarity R/W Data enable input polarity
1b: Active high
0b: Active low
Exists: Always
3 DVI_modez R/W Active low
0b: DVI mode selected
1b: HDMI mode selected
Exists: Always

Table 6-54 Fields for Register: fc_invidconf (Continued)
Memory
1 r_v_blank_in_osc R/W Used for CEA861-D modes with fractional Vblank (for
example, modes 5, 6, 7, 10, 11, 20, 21, and 22). For more
modes, see the CEA861-D specification.
Note: Set this field to 1 for video mode 39, although there is
no Vblank oscillation.
1b: Active high
Exists: Always
0 in_I_P R/W Input video mode:
1b: Interlaced
0b: Progressive
Exists: Always
6.5.2 fc_inhactiv0
■ Description: Frame Composer Input Video HActive Pixels Register 0
■ Size: 8 bits
■ Offset: 0x1001
■ Exists: Always
Table 6-55 Fields for Register: fc_inhactiv0
Memory
7:0 H_in_activ R/W Input video Horizontal active pixel region width. Number of
Horizontal active pixels [0...8191].
Exists: Always

6.5.3 fc_inhactiv1
■ Description: Frame Composer Input Video HActive Pixels Register 1
■ Size: 8 bits
■ Offset: 0x1002
■ Exists: Always
Table 6-56 Fields for Register: fc_inhactiv1
Memory
5 H_in_activ_13 R/W Input video Horizontal active pixel region width (0 .. 16383)
If the configuration parameter DWC_HDMI_TX_20 = True
(1), this bit field holds bit 13.
4 H_in_activ_12 R/W Input video Horizontal active pixel region width (0 . . 8191)
If configuration parameter DWC_HDMI_TX_14 = True (1),
this bit field holds bit 12.
3:0 H_in_activ R/W Input video Horizontal active pixel region width
Exists: Always
6.5.4 fc_inhblank0
■ Description: Frame Composer Input Video HBlank Pixels Register 0
■ Size: 8 bits
■ Offset: 0x1003
■ Exists: Always
Table 6-57 Fields for Register: fc_inhblank0
Memory
7:0 H_in_blank R/W Input video Horizontal blanking pixel region width. Number of
Horizontal blanking pixels [0...4095].
Exists: Always

6.5.5 fc_inhblank1
■ Description: Frame Composer Input Video HBlank Pixels Register 1
■ Size: 8 bits
■ Offset: 0x1004
■ Exists: Always
Table 6-58 Fields for Register: fc_inhblank1
Memory
4:2 H_in_blank_12 R/W Input video Horizontal blanking pixel region width
this bit field holds bit 12:10 of number of horizontal blanking
pixels.
1:0 H_in_blank R/W Input video Horizontal blanking pixel region width this bit field
holds bits 9:8 of number of Horizontal blanking pixels.
Exists: Always
6.5.6 fc_invactiv0
■ Description: Frame Composer Input Video VActive Pixels Register 0
■ Size: 8 bits
■ Offset: 0x1005
■ Exists: Always
Table 6-59 Fields for Register: fc_invactiv0
Memory
7:0 V_in_activ R/W Input video Vertical active pixel region width. This bit field
holds bits 7:0 of number of Vertical active pixels.
Exists: Always

6.5.7 fc_invactiv1
■ Description: Frame Composer Input Video VActive Pixels Register 1
■ Size: 8 bits
■ Offset: 0x1006
■ Exists: Always
Table 6-60 Fields for Register: fc_invactiv1
Memory
4:3 V_in_activ_12_11 R/W Input video Vertical active pixel region width.
If the configuration parameter DWC_HDMI_TX_14 = True
(1), this bit field holds bits 12:10 of number of Vertical active
pixels.
2:0 V_in_activ R/W Input video Vertical active pixel region width. This bit field
holds bits 9:8 of number of Vertical active pixels.
Exists: Always
6.5.8 fc_invblank
■ Description: Frame Composer Input Video VBlank Pixels Register
■ Size: 8 bits
■ Offset: 0x1007
■ Exists: Always
Table 6-61 Fields for Register: fc_invblank
Memory
7:0 V_in_blank R/W Input video Vertical blanking pixel region width. Number of
Vertical blanking lines [0...255].
Exists: Always

6.5.9 fc_hsyncindelay0
■ Description: Frame Composer Input Video HSync Front Porch Register 0
■ Size: 8 bits
■ Offset: 0x1008
■ Exists: Always
Table 6-62 Fields for Register: fc_hsyncindelay0
Memory
7:0 H_in_delay R/W Input video Hsync active edge delay. Integer number of pixel
clock cycles from "de" non active edge of the last "de" valid
period [0...4095].
Exists: Always
6.5.10 fc_hsyncindelay1
■ Description: Frame Composer Input Video HSync Front Porch Register 1
■ Size: 8 bits
■ Offset: 0x1009
■ Exists: Always
Table 6-63 Fields for Register: fc_hsyncindelay1
Memory
4:3 H_in_delay_12 R/W Input video Horizontal active edge delay.
this bit field holds bit 12. Integer number of pixel clock cycles
from "de" non-active edge of the last "de" valid period
[0...8191].
2:0 H_in_delay R/W Input video Horizontal active edge delay.
Exists: Always

6.5.11 fc_hsyncinwidth0
■ Description: Frame Composer Input Video HSync Width Register 0
■ Size: 8 bits
■ Offset: 0x100a
■ Exists: Always
Table 6-64 Fields for Register: fc_hsyncinwidth0
Memory
7:0 H_in_width R/W Input video Hsync active pulse width. Integer number of pixel
clock cycles [0...511].
Exists: Always
6.5.12 fc_hsyncinwidth1
■ Description: Frame Composer Input Video HSync Width Register 1
■ Size: 8 bits
■ Offset: 0x100b
■ Exists: Always
Table 6-65 Fields for Register: fc_hsyncinwidth1
Memory
1 H_in_width_9 R/W Input video Hsync active pulse width.
then this bit field holds bit 9. Number of Horizontal active
pixels [0...1024].
0 H_in_width R/W Input video Hsync active pulse width.
Exists: Always

6.5.13 fc_vsyncindelay
■ Description: Frame Composer Input Video VSync Front Porch Register
■ Size: 8 bits
■ Offset: 0x100c
■ Exists: Always
Table 6-66 Fields for Register: fc_vsyncindelay
Memory
7:0 V_in_delay R/W Input video Vsync active edge delay. Integer number of
Hsync pulses from "de" non active edge of the last "de" valid
period. [0...255].
Exists: Always
6.5.14 fc_vsyncinwidth
■ Description: Frame Composer Input Video VSync Width Register
■ Size: 8 bits
■ Offset: 0x100d
■ Exists: Always
Table 6-67 Fields for Register: fc_vsyncinwidth
Memory
5:0 V_in_width R/W Input video Vsync active pulse width. Integer number of
video lines [0...63].
Exists: Always

6.5.15 fc_infreq0
■ Description: Frame Composer Input Video Refresh Rate Register 0
■ Size: 8 bits
■ Offset: 0x100e
■ Exists: Always
Table 6-68 Fields for Register: fc_infreq0
Memory
7:0 infreq R/W Video refresh rate in Hz*1E3 format. This register is provided
for debug and informative purposes.
The DWC_hdmi_tx does not write any data to this register;
the data written by software is not used by the
DWC_hdmi_tx.
Exists: Always
6.5.16 fc_infreq1
■ Size: 8 bits
■ Offset: 0x100f
■ Exists: Always
Memory
DWC_hdmi_tx.
Exists: Always

6.5.17 fc_infreq2
■ Size: 8 bits
■ Offset: 0x1010
■ Exists: Always
Memory
DWC_hdmi_tx.
Exists: Always
6.5.18 fc_ctrldur
■ Description: Frame Composer Control Period Duration Register
■ Size: 8 bits
■ Offset: 0x1011
■ Exists: Always
Table 6-71 Fields for Register: fc_ctrldur
Memory
7:0 ctrlperiodduration R/W Configuration of the control period minimum duration
(minimum of 12 pixel clock cycles; refer to HDMI 1.4b
specification). Integer number of pixel clocks cycles [0..223].
Exists: Always

6.5.19 fc_exctrldur
■ Description: Frame Composer Extended Control Period Duration Register
■ Size: 8 bits
■ Offset: 0x1012
■ Exists: Always
Table 6-72 Fields for Register: fc_exctrldur
Memory
7:0 exctrlperiodduration R/W Configuration of the extended control period minimum
duration (minimum of 32 pixel clock cycles; refer to HDMI
1.4b specification). Integer number of pixel clocks cycles
[0..223].
Exists: Always
6.5.20 fc_exctrlspac
■ Description: Frame Composer Extended Control Period Maximum Spacing Register
■ Size: 8 bits
■ Offset: 0x1013
■ Exists: Always
Table 6-73 Fields for Register: fc_exctrlspac
Memory
7:0 exctrlperiodspacing R/W Configuration of the maximum spacing between consecutive
extended control periods (maximum of 50ms; refer to the
applicable HDMI specification).
When using the HDMI 2.0 supported features
(DWC_HDMI_TX_20 = 1):
■ generated spacing = (1/freq tmds
clock)*256*512*(extctrlperiodspacing +1)
else
■ generated spacing = (1/freq tmds
clock)*256*256*(extctrlperiodspacing +1)
Exists: Always

6.5.21 fc_ch0pream
■ Description: Frame Composer Channel 0 Non-Preamble Data Register
■ Size: 8 bits
■ Offset: 0x1014
■ Exists: Always
Table 6-74 Fields for Register: fc_ch0pream
Memory
7:0 ch0_preamble_filter R/W When in control mode, configures 8 bits that fill the channel 0
data lines not used to transmit the preamble (for more
clarification, refer to the HDMI 1.4b specification).
Exists: Always
6.5.22 fc_ch1pream
■ Size: 8 bits
■ Offset: 0x1015
■ Exists: Always
Memory
Exists: Always

6.5.23 fc_ch2pream
■ Size: 8 bits
■ Offset: 0x1016
■ Exists: Always
Memory
Exists: Always
6.5.24 fc_aviconf3
■ Description: Frame Composer AVI Packet Configuration Register 3
■ Size: 8 bits
■ Offset: 0x1017
■ Exists: DWC_HDMI_TX_14==1
Table 6-77 Fields for Register: fc_aviconf3
Memory
3:2 YQ R/W YCC Quantization range according to the CEA specification
Exists: Always
1:0 CN R/W IT content type according to CEA the specification
Exists: Always

6.5.25 fc_gcp
■ Description: Frame Composer GCP Packet Configuration Register
■ Size: 8 bits
■ Offset: 0x1018
■ Exists: Always
Table 6-78 Fields for Register: fc_gcp
Memory
2 default_phase R/W Value of "default_phase" in the GCP packet. This data must
be equal to the default phase used at Video Packetizer
packing machine.
Exists: Always
1 set_avmute R/W Value of "set_avmute" in the GCP packet
Once the AVmute is set, the frame composer schedules the
GCP packet with AVmute set in the packet scheduler to be
sent once (may only be transmitted between the active edge
of VSYNC and 384 pixels following this edge).
Exists: Always
0 clear_avmute R/W Value of "clear_avmute" in the GCP packet
Exists: Always

6.5.26 fc_aviconf0
■ Size: 8 bits
■ Offset: 0x1019
■ Exists: Always
Memory
7 rgc_ycc_indication_2 R/W Y2, Bit 2 of rgc_ycc_indication
6 active_format_present R/W Active format present
Exists: Always
5:4 scan_information R/W Scan information
Exists: Always
3:2 bar_information R/W Bar information data valid
Exists: Always
1:0 rgc_ycc_indication R/W Y1,Y0 RGB or YCC indicator
Exists: Always

6.5.27 fc_aviconf1
■ Size: 8 bits
■ Offset: 0x101a
■ Exists: Always
Memory
7:6 Colorimetry R/W Colorimetry
Exists: Always
5:4 picture_aspect_ratio R/W Picture aspect ratio
Exists: Always
3:0 active_aspect_ratio R/W Active aspect ratio
Exists: Always

6.5.28 fc_aviconf2
■ Size: 8 bits
■ Offset: 0x101b
■ Exists: Always
Memory
7 it_content R/W IT content
Exists: Always
6:4 extended_colorimetry R/W Extended colorimetry
Exists: Always
3:2 quantization_range R/W Quantization range
Exists: Always
1:0 non_uniform_picture_scaling R/W Non-uniform picture scaling
Exists: Always

6.5.29 fc_avivid
■ Description: Frame Composer AVI Packet VIC Register
■ Size: 8 bits
■ Offset: 0x101c
■ Exists: Always
Table 6-82 Fields for Register: fc_avivid
Memory
7 fc_avivid_7 R/W Bit 7 of fc_avivid register
6:0 fc_avivid R/W Configures the AVI InfoFrame Video Identification code. For
more information, refer to the CEA-861-E specification.
Exists: Always
6.5.30 fc_avietb[0:1]
■ Description: Frame Composer AVI Packet End of Top Bar Register Array
■ Size: 8 bits
■ Offset: 0x101d + (i * 0x1)
■ Exists: Always
Table 6-83 Fields for Register: fc_avietb[0:1]
Memory
7:0 fc_avietb R/W Defines the AVI InfoFrame End of Top Bar value. For more
information, refer to the CEA-861-E specification.
Exists: Always

6.5.31 fc_avisbb[0:1]
■ Description: Frame Composer AVI Packet Start of Bottom Bar Register Array
■ Size: 8 bits
■ Offset: 0x101f + (i * 0x1)
■ Exists: Always
Table 6-84 Fields for Register: fc_avisbb[0:1]
Memory
7:0 fc_avisbb R/W This register defines the AVI InfoFrame Start of Bottom Bar
value. For more information, refer to the CEA-861-E
specification.
Exists: Always
6.5.32 fc_avielb[0:1]
■ Description: Frame Composer AVI Packet End of Left Bar Register Array
■ Size: 8 bits
■ Offset: 0x1021 + (i * 0x1)
■ Exists: Always
Table 6-85 Fields for Register: fc_avielb[0:1]
Memory
7:0 fc_avielb R/W This register defines the AVI InfoFrame End of Left Bar
specification.
Exists: Always

6.5.33 fc_avisrb[0:1]
■ Description: Frame Composer AVI Packet Start of Right Bar Register Array
■ Size: 8 bits
■ Offset: 0x1023 + (i * 0x1)
■ Exists: Always
Table 6-86 Fields for Register: fc_avisrb[0:1]
Memory
7:0 fc_avisrb R/W This register defines the AVI InfoFrame Start of Right Bar
specification.
Exists: Always
6.5.34 fc_audiconf0
■ Description: Frame Composer AUD Packet Configuration Register 0
■ Size: 8 bits
■ Offset: 0x1025
■ Exists: Always
Table 6-87 Fields for Register: fc_audiconf0
Memory
6:4 CC R/W Channel count
Exists: Always
3:0 CT R/W Coding Type
Exists: Always

6.5.35 fc_audiconf1
■ Size: 8 bits
■ Offset: 0x1026
■ Exists: Always
Memory
5:4 SS R/W Sampling size
Exists: Always
2:0 SF R/W Sampling frequency
Exists: Always
6.5.36 fc_audiconf2
■ Size: 8 bits
■ Offset: 0x1027
■ Exists: Always
Memory
7:0 CA R/W Channel allocation
Exists: Always

6.5.37 fc_audiconf3
■ Size: 8 bits
■ Offset: 0x1028
■ Exists: Always
Memory
6:5 LFEPBL R/W LFE playback information
LFEPBL1, LFEPBL0 LFE playback level as compared to the
other channels.
4 DM_INH R/W Down mix enable
Exists: Always
3:0 LSV R/W Level shift value (for down mixing)
Exists: Always
6.5.38 fc_vsdieeeid0
■ Description: Frame Composer VSI Packet Data IEEE Register 0
■ Size: 8 bits
■ Offset: 0x1029
■ Exists: Always
Table 6-91 Fields for Register: fc_vsdieeeid0
Memory
7:0 IEEE R/W This register configures the Vendor Specific InfoFrame IEEE
registration identifier. For more information, refer to the CEA-
861-E specification.
Exists: Always

6.5.39 fc_vsdsize
■ Description: Frame Composer VSI Packet Data Size Register
■ Size: 8 bits
■ Offset: 0x102a
Table 6-92 Fields for Register: fc_vsdsize
Memory
4:0 VSDSIZE R/W Packet size as described in the HDMI Vendor Specific
InfoFrame (from the HDMI specification).
Value After Reset: 0x1b
Exists: Always
■ Size: 8 bits
■ Offset: 0x1030
■ Exists: Always
Memory
Exists: Always

■ Size: 8 bits
■ Offset: 0x1031
■ Exists: Always
Memory
Exists: Always
6.5.42 fc_vsdpayload[0:23]
■ Description: Frame Composer VSI Packet Data Payload Register Array
■ Size: 8 bits
■ Offset: 0x1032 + (i * 0x1)
■ Exists: Always
Table 6-95 Fields for Register: fc_vsdpayload[0:23]
Memory
7:0 fc_vsdpayload R/W Frame Composer VSI Packet Data Payload Register Array
Configures the Vendor Specific infoFrame 24 bytes specific
payload. For more information, refer to the CEA-861-E
specification.
Exists: Always

6.5.43 fc_spdvendorname[0:7]
■ Description: Frame Composer SPD Packet Data Vendor Name Register Array
■ Size: 8 bits
■ Offset: 0x104a + (i * 0x1)
■ Exists: Always
Table 6-96 Fields for Register: fc_spdvendorname[0:7]
Memory
7:0 fc_spdvendorname R/W Frame Composer SPD Packet Data Vendor Name Register
Array
Configures the Source Product Descriptor infoFrame 8 bytes
Vendor name. For more information, refer to the CEA-861-E
specification.
Exists: Always
6.5.44 fc_spdproductname[0:15]
■ Description: Frame Composer SPD packet Data Product Name Register Array
■ Size: 8 bits
■ Offset: 0x1052 + (i * 0x1)
■ Exists: Always
Table 6-97 Fields for Register: fc_spdproductname[0:15]
Memory
7:0 fc_spdproductname R/W Frame Composer SPD packet Data Product Name Register
Array
Configures the Source Product Descriptor infoFrame 16
bytes Product name. For more information, refer to the CEA-
Exists: Always

6.5.45 fc_spddeviceinf
■ Description: Frame Composer SPD Packet Data Source Product Descriptor Register
■ Size: 8 bits
■ Offset: 0x1062
■ Exists: Always
Table 6-98 Fields for Register: fc_spddeviceinf
Memory
7:0 fc_spddeviceinf R/W Frame Composer SPD Packet Data Source Product
Descriptor Register
Exists: Always
6.5.46 fc_audsconf
■ Description: Frame Composer Audio Sample Flat and Layout Configuration Register
■ Size: 8 bits
■ Offset: 0x1063
■ Exists: Always
Table 6-99 Fields for Register: fc_audsconf
Memory
7:4 aud_packet_sampflt R/W Set the audio packet sample flat value to be sent on the
packet.
Exists: Always
0 aud_packet_layout R/W Set the audio packet layout to be sent in the packet:
1b: layout 1
0b: layout 0
If DWC_HDMI_TX_20 is defined and register field
fc_multistream_ctrl.fc_mas_packet_en is active, this bit has
no effect.
Exists: Always

6.5.47 fc_audsstat
■ Description: Frame Composer Audio Sample Flat and Layout Status Register
■ Size: 8 bits
■ Offset: 0x1064
■ Exists: Always
Table 6-100 Fields for Register: fc_audsstat
Memory
3:0 packet_sampprs R Shows the data sample present indication of the last Audio
sample packet sent by the HDMI TX Controller. This register
information is at TMDS clock rate.
Exists: Always

6.5.48 fc_audsv
■ Description: Frame Composer Audio Sample Validity Flag Register
■ Size: 8 bits
■ Offset: 0x1065
■ Exists: Always
Table 6-101 Fields for Register: fc_audsv
Memory
7 V3r R/W Set validity bit "V" for Channel 3, Right
Exists: Always
Exists: Always
Exists: Always
Exists: Always
3 V3l R/W Set validity bit "V" for Channel 3, Left
Exists: Always
Exists: Always
Exists: Always
Exists: Always

6.5.49 fc_audsu
■ Description: Frame Composer Audio Sample User Flag Register
■ Size: 8 bits
■ Offset: 0x1066
■ Exists: Always
Table 6-102 Fields for Register: fc_audsu
Memory
7 U3r R/W Set user bit "U" for Channel 3, Right
Exists: Always
Exists: Always
Exists: Always
Exists: Always
3 U3l R/W Set user bit "U" for Channel 3, Left
Exists: Always
Exists: Always
Exists: Always
Exists: Always

6.5.50 fc_audschnl0
■ Description: Frame Composer Audio Sample Channel Status Configuration Register 0
■ Size: 8 bits
■ Offset: 0x1067
■ Exists: Always
Table 6-103 Fields for Register: fc_audschnl0
Memory
5:4 oiec_cgmsa R/W CGMS-A
Exists: Always
0 oiec_copyright R/W IEC Copyright indication
Exists: Always
6.5.51 fc_audschnl1
■ Size: 8 bits
■ Offset: 0x1068
■ Exists: Always
Memory
7:0 oiec_categorycode R/W Category code
Exists: Always

6.5.52 fc_audschnl2
■ Size: 8 bits
■ Offset: 0x1069
■ Exists: Always
Memory
6:4 oiec_pcmaudiomode R/W PCM audio mode
Exists: Always
3:0 oiec_sourcenumber R/W Source number
Exists: Always
6.5.53 fc_audschnl3
■ Size: 8 bits
■ Offset: 0x106a
■ Exists: Always
Memory
7:4 oiec_channelnumcr1 R/W Channel number for second right sample
Exists: Always
3:0 oiec_channelnumcr0 R/W Channel number for first right sample
Exists: Always

6.5.54 fc_audschnl4
■ Size: 8 bits
■ Offset: 0x106b
■ Exists: Always
Memory
7:4 oiec_channelnumcr3 R/W Channel number for fourth right sample
Exists: Always
3:0 oiec_channelnumcr2 R/W Channel number for third right sample
Exists: Always
6.5.55 fc_audschnl5
■ Size: 8 bits
■ Offset: 0x106c
■ Exists: Always
Memory
7:4 oiec_channelnumcl1 R/W Channel number for second left sample
Exists: Always
3:0 oiec_channelnumcl0 R/W Channel number for first left sample
Exists: Always

6.5.56 fc_audschnl6
■ Size: 8 bits
■ Offset: 0x106d
■ Exists: Always
Memory
7:4 oiec_channelnumcl3 R/W Channel number for fourth left sample
Exists: Always
3:0 oiec_channelnumcl2 R/W Channel number for third left sample
Exists: Always
6.5.57 fc_audschnl7
■ Size: 8 bits
■ Offset: 0x106e
■ Exists: Always
Memory
7:6 oiec_sampfreq_ext R/W Sampling frequency (channel status bits 31 and 30)
5:4 oiec_clkaccuracy R/W Clock accuracy
Exists: Always
3:0 oiec_sampfreq R/W Sampling frequency
Exists: Always

6.5.58 fc_audschnl8
■ Size: 8 bits
■ Offset: 0x106f
■ Exists: Always
Memory
7:4 oiec_origsampfreq R/W Original sampling frequency
Exists: Always
3:0 oiec_wordlength R/W Word length configuration
Exists: Always
6.5.59 fc_ctrlqhigh
■ Description: Frame Composer Number of High Priority Packets Attended Configuration Register
■ Size: 8 bits
■ Offset: 0x1073
■ Exists: Always
Table 6-112 Fields for Register: fc_ctrlqhigh
Memory
4:0 onhighattended R/W Configures the number of high priority packets or audio
sample packets consecutively attended before checking low
priority queue status. Valid range is from 5'd1 to 5'd31.
Value After Reset: 0xf
Exists: Always

6.5.60 fc_ctrlqlow
■ Description: Frame Composer Number of Low Priority Packets Attended Configuration Register
■ Size: 8 bits
■ Offset: 0x1074
■ Exists: Always
Table 6-113 Fields for Register: fc_ctrlqlow
Memory
4:0 onlowattended R/W Configures the number of low priority packets or null packets
consecutively attended before checking high priority queue
status or audio samples availability. Valid range is from 5'd1
to 5'd31.
Exists: Always
6.5.61 fc_acp0
■ Description: Frame Composer ACP Packet Type Configuration Register 0
■ Size: 8 bits
■ Offset: 0x1075
■ Exists: Always
Table 6-114 Fields for Register: fc_acp0
Memory
7:0 acptype R/W Configures the ACP packet type.
Exists: Always

6.5.62 fc_acp16
■ Description: Frame Composer ACP Packet Body Configuration Register 16
■ Size: 8 bits
■ Offset: 0x1082
■ Exists: Always
Memory
7:0 fc_acp16 R/W Frame Composer ACP Packet Body Configuration Register
16
Exists: Always
6.5.63 fc_acp15
■ Size: 8 bits
■ Offset: 0x1083
■ Exists: Always
Memory
15
Exists: Always

6.5.64 fc_acp14
■ Size: 8 bits
■ Offset: 0x1084
■ Exists: Always
Memory
14
Exists: Always
6.5.65 fc_acp13
■ Size: 8 bits
■ Offset: 0x1085
■ Exists: Always
Memory
13
Exists: Always

6.5.66 fc_acp12
■ Size: 8 bits
■ Offset: 0x1086
■ Exists: Always
Memory
12
Exists: Always
6.5.67 fc_acp11
■ Size: 8 bits
■ Offset: 0x1087
■ Exists: Always
Memory
11
Exists: Always

6.5.68 fc_acp10
■ Size: 8 bits
■ Offset: 0x1088
■ Exists: Always
Memory
10
Exists: Always
6.5.69 fc_acp9
■ Size: 8 bits
■ Offset: 0x1089
■ Exists: Always
Memory
7:0 fc_acp9 R/W Frame Composer ACP Packet Body Configuration Register 9
Exists: Always

6.5.70 fc_acp8
■ Size: 8 bits
■ Offset: 0x108a
■ Exists: Always
Memory
Exists: Always
6.5.71 fc_acp7
■ Size: 8 bits
■ Offset: 0x108b
■ Exists: Always
Memory
Exists: Always

6.5.72 fc_acp6
■ Size: 8 bits
■ Offset: 0x108c
■ Exists: Always
Memory
Exists: Always
6.5.73 fc_acp5
■ Size: 8 bits
■ Offset: 0x108d
■ Exists: Always
Memory
Exists: Always

6.5.74 fc_acp4
■ Size: 8 bits
■ Offset: 0x108e
■ Exists: Always
Memory
Exists: Always
6.5.75 fc_acp3
■ Size: 8 bits
■ Offset: 0x108f
■ Exists: Always
Memory
Exists: Always

6.5.76 fc_acp2
■ Size: 8 bits
■ Offset: 0x1090
■ Exists: Always
Memory
Exists: Always
6.5.77 fc_acp1
■ Size: 8 bits
■ Offset: 0x1091
■ Exists: Always
Memory
Exists: Always

6.5.78 fc_iscr1_0
■ Description: Frame Composer ISRC1 Packet Status, Valid, and Continue Configuration Register
■ Size: 8 bits
■ Offset: 0x1092
■ Exists: Always
Table 6-131 Fields for Register: fc_iscr1_0
Memory
4:2 isrc_status R/W ISRC1 Status signal
Exists: Always
1 isrc_valid R/W ISRC1 Valid control signal
Exists: Always
0 isrc_cont R/W ISRC1 Indication of packet continuation (ISRC2 will be
transmitted)
Exists: Always
6.5.79 fc_iscr1_16
■ Description: Frame Composer ISRC1 Packet Body Register 16
■ Size: 8 bits
■ Offset: 0x1093
■ Exists: Always
Memory
7:0 fc_iscr1_16 R/W Frame Composer ISRC1 Packet Body Register 16;
configures ISRC1 packet body of the ISRC1 packet
Exists: Always

6.5.80 fc_iscr1_15
■ Size: 8 bits
■ Offset: 0x1094
■ Exists: Always
Memory
7:0 fc_iscr1_15 R/W Frame Composer ISRC1 Packet Body Register 15
Exists: Always
6.5.81 fc_iscr1_14
■ Size: 8 bits
■ Offset: 0x1095
■ Exists: Always
Memory
Exists: Always

6.5.82 fc_iscr1_13
■ Size: 8 bits
■ Offset: 0x1096
■ Exists: Always
Memory
Exists: Always
6.5.83 fc_iscr1_12
■ Size: 8 bits
■ Offset: 0x1097
■ Exists: Always
Memory
Exists: Always

6.5.84 fc_iscr1_11
■ Size: 8 bits
■ Offset: 0x1098
■ Exists: Always
Memory
Exists: Always
6.5.85 fc_iscr1_10
■ Size: 8 bits
■ Offset: 0x1099
■ Exists: Always
Memory
Exists: Always

6.5.86 fc_iscr1_9
■ Size: 8 bits
■ Offset: 0x109a
■ Exists: Always
Memory
Exists: Always
6.5.87 fc_iscr1_8
■ Size: 8 bits
■ Offset: 0x109b
■ Exists: Always
Memory
Exists: Always

6.5.88 fc_iscr1_7
■ Size: 8 bits
■ Offset: 0x109c
■ Exists: Always
Memory
Exists: Always
6.5.89 fc_iscr1_6
■ Size: 8 bits
■ Offset: 0x109d
■ Exists: Always
Memory
Exists: Always

6.5.90 fc_iscr1_5
■ Size: 8 bits
■ Offset: 0x109e
■ Exists: Always
Memory
Exists: Always
6.5.91 fc_iscr1_4
■ Size: 8 bits
■ Offset: 0x109f
■ Exists: Always
Memory
Exists: Always

6.5.92 fc_iscr1_3
■ Size: 8 bits
■ Offset: 0x10a0
■ Exists: Always
Memory
Exists: Always
6.5.93 fc_iscr1_2
■ Size: 8 bits
■ Offset: 0x10a1
■ Exists: Always
Memory
Exists: Always

6.5.94 fc_iscr1_1
■ Size: 8 bits
■ Offset: 0x10a2
■ Exists: Always
Memory
Exists: Always
6.5.95 fc_iscr2_15
■ Size: 8 bits
■ Offset: 0x10a3
■ Exists: Always
Memory
7:0 fc_iscr2_15 R/W Frame Composer ISRC2 Packet Body Register 15;
configures the ISRC2 packet body of the ISRC2 packet
Exists: Always

6.5.96 fc_iscr2_14
■ Size: 8 bits
■ Offset: 0x10a4
■ Exists: Always
Memory
Exists: Always
6.5.97 fc_iscr2_13
■ Size: 8 bits
■ Offset: 0x10a5
■ Exists: Always
Memory
Exists: Always

6.5.98 fc_iscr2_12
■ Size: 8 bits
■ Offset: 0x10a6
■ Exists: Always
Memory
Exists: Always
6.5.99 fc_iscr2_11
■ Size: 8 bits
■ Offset: 0x10a7
■ Exists: Always
Memory
Exists: Always

6.5.100 fc_iscr2_10
■ Size: 8 bits
■ Offset: 0x10a8
■ Exists: Always
Memory
Exists: Always
6.5.101 fc_iscr2_9
■ Size: 8 bits
■ Offset: 0x10a9
■ Exists: Always
Memory
Exists: Always

6.5.102 fc_iscr2_8
■ Size: 8 bits
■ Offset: 0x10aa
■ Exists: Always
Memory
Exists: Always
6.5.103 fc_iscr2_7
■ Size: 8 bits
■ Offset: 0x10ab
■ Exists: Always
Memory
Exists: Always

6.5.104 fc_iscr2_6
■ Size: 8 bits
■ Offset: 0x10ac
■ Exists: Always
Memory
Exists: Always
6.5.105 fc_iscr2_5
■ Size: 8 bits
■ Offset: 0x10ad
■ Exists: Always
Memory
Exists: Always

6.5.106 fc_iscr2_4
■ Size: 8 bits
■ Offset: 0x10ae
■ Exists: Always
Memory
Exists: Always
6.5.107 fc_iscr2_3
■ Size: 8 bits
■ Offset: 0x10af
■ Exists: Always
Memory
Exists: Always

6.5.108 fc_iscr2_2
■ Size: 8 bits
■ Offset: 0x10b0
■ Exists: Always
Memory
Exists: Always
6.5.109 fc_iscr2_1
■ Size: 8 bits
■ Offset: 0x10b1
■ Exists: Always
Memory
Exists: Always

6.5.110 fc_iscr2_0
■ Size: 8 bits
■ Offset: 0x10b2
■ Exists: Always
Memory
Exists: Always

6.5.111 fc_datauto0
■ Description: Frame Composer Data Island Auto Packet Scheduling Register 0
Configures the Frame Composer RDRB(1)/Manual(0) data island packet insertion for SPD, VSD,
ISRC2, ISRC1 and ACP packets. On RDRB mode the described packet scheduling is controlled by
registers FC_DATAUTO1 and FC_DATAUTO2, while in Manual mode register FC_DATMAN
requests to FC the insertion of the requested packet. Note: When activating auto packet scheduling,
there is a possibility of sending multiple vendor-specific infoframes and violating CEA-861F.
■ Size: 8 bits
■ Offset: 0x10b3
■ Exists: Always
Table 6-164 Fields for Register: fc_datauto0
Memory
4 spd_auto R/W Enables SPD automatic packet scheduling
Exists: Always
3 vsd_auto R/W Enables VSD automatic packet scheduling
Exists: Always
2 iscr2_auto R/W Enables ISRC2 automatic packet scheduling
Exists: Always
1 iscr1_auto R/W Enables ISRC1 automatic packet scheduling
Exists: Always
0 acp_auto R/W Enables ACP automatic packet scheduling
Exists: Always

6.5.112 fc_datauto1
Configures the Frame Composer (FC) RDRB frame interpolation for SPD, VSD, ISRC2, ISRC1 and
ACP packet insertion on data island when FC is on RDRB mode for the listed packets. Note: When
activating auto packet scheduling, there is a possibility of sending multiple vendor-specific
infoframes and violating CEA-861F.
■ Size: 8 bits
■ Offset: 0x10b4
■ Exists: Always
Memory
3:0 auto_frame_interpolation R/W Packet frame interpolation for automatic packet scheduling
Exists: Always
6.5.113 fc_datauto2
■ Description: Frame Composer Data Island Auto packet scheduling Register 2
Configures the Frame Composer (FC) RDRB line interpolation and number of packets in frame for
SPD, VSD, ISRC2, ISRC1 and ACP packet insertion on data island when FC is on RDRB mode for the
listed packets.
■ Size: 8 bits
■ Offset: 0x10b5
■ Exists: Always
Memory
7:4 auto_frame_packets R/W Packets per frame, for automatic packet scheduling
Exists: Always
3:0 auto_line_spacing R/W Packets line spacing, for automatic packet scheduling
Exists: Always

6.5.114 fc_datman
■ Description: Frame Composer Data Island Manual Packet Request Register
Requests to the Frame Composer the data island packet insertion for NULL, SPD, VSD, ISRC2, ISRC1
and ACP packets when FC_DATAUTO0 bit is in manual mode for the packet requested.
■ Size: 8 bits
■ Offset: 0x10b6
■ Exists: Always
Table 6-167 Fields for Register: fc_datman
Memory
5 null_tx W Null packet
Exists: Always
4 spd_tx W SPD packet
Exists: Always
3 vsd_tx W VSD packet
Exists: Always
2 iscr2_tx W ISRC2 packet
Exists: Always
1 iscr1_tx W ISRC1 packet
Exists: Always
0 acp_tx W ACP packet
Exists: Always

6.5.115 fc_datauto3
Configures the Frame Composer Automatic(1)/RDRB(0) data island packet insertion for AVI, GCP,
AUDI and ACR packets. In Automatic mode, the packet is inserted on Vblanking when first line with
active Vsync appears.
■ Size: 8 bits
■ Offset: 0x10b7
■ Exists: Always
Memory
6 drm_auto R/W Enables DRM packet insertion
5 nvbi_auto R/W Enables NTSC VBI packet insertion
4 amp_auto R/W Enables AMP packet insertion
3 avi_auto R/W Enables AVI packet insertion
Exists: Always
2 gcp_auto R/W Enables GCP packet insertion
Exists: Always
1 audi_auto R/W Enables AUDI packet insertion
Exists: Always
0 acr_auto R/W Enables ACR packet insertion
Exists: Always

6.5.116 fc_rdrb0
■ Description: Frame Composer Round Robin ACR Packet Insertion Register 0
Configures the Frame Composer (FC) RDRB frame interpolation for ACR packet insertion on data
island when FC is on RDRB mode for this packet.
■ Size: 8 bits
■ Offset: 0x10b8
■ Exists: Always
Table 6-169 Fields for Register: fc_rdrb0
Memory
3:0 ACRframeinterpolation R/W ACR Frame interpolation
Exists: Always
6.5.117 fc_rdrb1
■ Description: Frame Composer Round Robin ACR Packet Insertion Register 1
the ACR packet insertion on data island when FC is on RDRB mode this packet.
■ Size: 8 bits
■ Offset: 0x10b9
■ Exists: Always
Memory
7:4 ACRpacketsinframe R/W ACR packets in frame
Exists: Always
3:0 ACRpacketlinespacing R/W ACR packet line spacing
Exists: Always

6.5.118 fc_rdrb2
■ Description: Frame Composer Round Robin AUDI Packet Insertion Register 2
Configures the Frame Composer (FC) RDRB frame interpolation for AUDI packet insertion on data
■ Size: 8 bits
■ Offset: 0x10ba
■ Exists: Always
Memory
3:0 AUDIframeinterpolation R/W Audio frame interpolation
Exists: Always
6.5.119 fc_rdrb3
■ Description: Frame Composer Round Robin AUDI Packet Insertion Register 3
the AUDI packet insertion on data island when FC is on RDRB mode this packet.
■ Size: 8 bits
■ Offset: 0x10bb
■ Exists: Always
Memory
7:4 AUDIpacketsinframe R/W Audio packets per frame
Exists: Always
3:0 AUDIpacketlinespacing R/W Audio packets line spacing
Exists: Always

6.5.120 fc_rdrb4
■ Description: Frame Composer Round Robin GCP Packet Insertion Register 4
Configures the Frame Composer (FC) RDRB frame interpolation for GCP packet insertion on data
■ Size: 8 bits
■ Offset: 0x10bc
■ Exists: Always
Memory
3:0 GCPframeinterpolation R/W Frames interpolated between GCP packets
Exists: Always
6.5.121 fc_rdrb5
■ Description: Frame Composer Round Robin GCP Packet Insertion Register 5
the GCP packet insertion on data island when FC is on RDRB mode this packet.
■ Size: 8 bits
■ Offset: 0x10bd
■ Exists: Always
Memory
7:4 GCPpacketsinframe R/W GCP packets per frame
Exists: Always
3:0 GCPpacketlinespacing R/W GCP packets line spacing
Exists: Always

6.5.122 fc_rdrb6
■ Description: Frame Composer Round Robin AVI Packet Insertion Register 6
Configures the Frame Composer (FC) RDRB frame interpolation for AVI packet insertion on data
■ Size: 8 bits
■ Offset: 0x10be
■ Exists: Always
Memory
3:0 AVIframeinterpolation R/W Frames interpolated between AVI packets
Exists: Always
6.5.123 fc_rdrb7
■ Description: Frame Composer Round Robin AVI Packet Insertion Register 7
the AVI packet insertion on data island when FC is on RDRB mode this packet.
■ Size: 8 bits
■ Offset: 0x10bf
■ Exists: Always
Memory
7:4 AVIpacketsinframe R/W AVI packets per frame
Exists: Always
3:0 AVIpacketlinespacing R/W AVI packets line spacing
Exists: Always

6.5.124 fc_rdrb8
■ Description: Frame Composer Round Robin AMP Packet Insertion Register 8
■ Size: 8 bits
■ Offset: 0x10c0
Memory
3:0 AMPframeinterpolation R/W AMP frame interpolation
Exists: Always
6.5.125 fc_rdrb9
■ Description: Frame Composer Round Robin AMP Packet Insertion Register 9
■ Size: 8 bits
■ Offset: 0x10c1
Memory
7:4 AMPpacketsinframe R/W AMP packets per frame
Exists: Always
3:0 AMPpacketlinespacing R/W AMP packets line spacing
Exists: Always

6.5.126 fc_rdrb10
■ Description: Frame Composer Round Robin NTSC VBI Packet Insertion Register 10
■ Size: 8 bits
■ Offset: 0x10c2
Memory
3:0 NVBIframeinterpolation R/W NTSC VBI frame interpolation
Exists: Always
6.5.127 fc_rdrb11
■ Description: Frame Composer Round Robin NTSC VBI Packet Insertion Register 11
■ Size: 8 bits
■ Offset: 0x10c3
Memory
7:4 NVBIpacketsinframe R/W NTSC VBI packets per frame
Exists: Always
3:0 NVBIpacketlinespacing R/W NTSC VBI packets line spacing
Exists: Always

6.5.128 fc_rdrb12
■ Description: Frame Composer Round Robin DRM Packet Insertion Register 12
■ Size: 8 bits
■ Offset: 0x10c4
Memory
3:0 DRMframeinterpolation R/W DRM frame interpolation
Exists: Always
6.5.129 fc_rdrb13
■ Description: Frame Composer Round Robin DRM Packet Insertion Register 13
■ Size: 8 bits
■ Offset: 0x10c5
Memory
7:4 DRMpacketsinframe R/W DRM packets per frame
Exists: Always
3:0 DRMpacketlinespacing R/W DRM packets line spacing
Exists: Always

6.5.130 fc_mask0
■ Description: Frame Composer Packet Interrupt Mask Register 0
■ Size: 8 bits
■ Offset: 0x10d2
■ Exists: Always
Table 6-183 Fields for Register: fc_mask0
Memory
7 AUDI R/W Mask bit for FC_INT0.AUDI interrupt bit
Exists: Always
6 ACP R/W Mask bit for FC_INT0.ACP interrupt bit
Exists: Always
5 HBR R/W Mask bit for FC_INT0.HBR interrupt bit
Exists: Always
4 MAS R/W Mask bit for FC_INT0.MAS interrupt bit. Otherwise, this field
is a "spare" bit with no associated functionality.
3 NVBI R/W Mask bit for FC_INT0.NVBI interrupt bit. Otherwise, this field
2 AUDS R/W Mask bit for FC_INT0.AUDS interrupt bit
Exists: Always
1 ACR R/W Mask bit for FC_INT0.ACR interrupt bit
Exists: Always
0 NULL R/W Mask bit for FC_INT0.NULL interrupt bit
Exists: Always

6.5.131 fc_mask1
■ Description: Frame Composer Packet Interrupt Mask Register 1
■ Size: 8 bits
■ Offset: 0x10d6
■ Exists: Always
Memory
7 GMD R/W Mask bit for FC_INT1.GMD interrupt bit
Exists: Always
6 ISCR1 R/W Mask bit for FC_INT1.ISRC1 interrupt bit
Exists: Always
5 ISCR2 R/W Mask bit for FC_INT1.ISRC2 interrupt bit
Exists: Always
4 VSD R/W Mask bit for FC_INT1.VSD interrupt bit
Exists: Always
3 SPD R/W Mask bit for FC_INT1.SPD interrupt bit
Exists: Always
2 AMP R/W Mask bit for FC_INT1.AMP interrupt bit. Otherwise, this field
1 AVI R/W Mask bit for FC_INT1.AVI interrupt bit
Exists: Always
0 GCP R/W Mask bit for FC_INT1.GCP interrupt bit
Exists: Always

6.5.132 fc_mask2
■ Description: Frame Composer High/Low Priority Overflow and DRM Interrupt Mask Register 2
■ Size: 8 bits
■ Offset: 0x10da
■ Exists: Always
Memory
4 DRM R/W Mask bit for FC_INT2.DRM interrupt bit.
1 LowPriority_overflow R/W Mask bit for FC_INT2.LowPriority_overflow interrupt bit
Exists: Always
0 HighPriority_overflow R/W Mask bit for FC_INT2.HighPriority_overflow interrupt bit
Exists: Always

6.5.133 fc_prconf
■ Description: Frame Composer Pixel Repetition Configuration Register
■ Size: 8 bits
■ Offset: 0x10e0
■ Exists: Always
Table 6-186 Fields for Register: fc_prconf
Memory
7:4 incoming_pr_factor R/W Configures the input video pixel repetition. For CEA modes, this value
must be extracted from the CEA specification for the video mode
being input.
incoming_pr_factor[3:0]
0000b: No action. Not used.
0001b: No pixel repetition (pixel sent only once)
0010b: Pixel sent two times (pixel repeated once)
0011b: Pixel sent three times
0100b: Pixel sent four times
0101b: Pixel sent five times
0110b: Pixel sent six times
0111b: Pixel sent seven times
1000b: Pixel sent eight times
1001b: Pixel sent nine times
1010b: Pixel sent 10 times
Other: Reserved. Not used
Exists: Always

Table 6-186 Fields for Register: fc_prconf (Continued)
Memory
3:0 output_pr_factor R/W Configures the video pixel repetition ratio to be sent on the AVI
InfoFrame. This value must be valid according to the HDMI
specification. The output_pr_factor = incoming_pr_factor *
(desired_pr_factor + 1) - 1.
output_pr_factor[3:0]
0000b: No action. Not used.
0001b: Pixel sent two times (pixel repeated once)
0010b: Pixel sent three times
0011b: Pixel sent four times
0100b: Pixel sent five times
0101b: Pixel sent six times
0110b: Pixel sent seven times
0111b: Pixel sent eight times
1000b: Pixel sent nine times
1001b: Pixel sent 10 times
Other: Reserved. Not used
Note: When working in YCC422 video, the actual repetition of the
stream is Incoming_pr_factor * (desired_pr_factor + 1). This
calculation is done internally in the H13TCTRL and no hardware
overflow protection is available. Care must be taken to avoid this
result passes the maximum number of 10 pixels repeated because
no HDMI support is available for this in the specification and the
H13TPHY does not support this higher repetition values.
Exists: Always

6.5.134 fc_scrambler_ctrl
■ Description: Frame Composer Scrambler Control
■ Size: 8 bits
■ Offset: 0x10e1
Table 6-187 Fields for Register: fc_scrambler_ctrl
Memory
4 scrambler_ucp_line R/W Debug register. When active (1'b1), the Unscrambled Control
Period is generated after each active video line (non-
compliant behavior). This is quasi-static field which requires
a a mc_swrstzreq.tmdsswrst_req reset request to be
performed after the change of this configuration bit.
Exists: Always
0 scrambler_on R/W When set (1'b1), this field activates the HDMI 2.0 scrambler
feature.
When disabled (1'b0) the scrambler feature is bypassed,
placing DWC_hdmi_tx in HDMI 1.4b compatible mode. To
activate the scrambler feature, you must ensure that the
quasi-static configuration bit fc_invidconf.HDCP_keepout is
set (1'b1) at configuration time, before the required
mc_swrstzreq.tmdsswrst_req reset request is issued.
This is field can be changed in runtime.
Exists: Always

6.5.135 fc_multistream_ctrl
■ Description: Frame Composer Multi-Stream Audio Control
■ Size: 8 bits
■ Offset: 0x10e2
Table 6-188 Fields for Register: fc_multistream_ctrl
Memory
0 fc_mas_packet_en R/W This field, when set (1'b1), activates the HDMI 2.0 Multi-
Stream support. The audio stream present at the input of the
DWC_hdmi_tx controller is transported using Multi-Stream
Audio Sample Packets.
Exists: Always

6.5.136 fc_packet_tx_en
■ Description: Frame Composer Packet Transmission Control
■ Size: 8 bits
■ Offset: 0x10e3
■ Exists: Always
Table 6-189 Fields for Register: fc_packet_tx_en
Memory
7 drm_tx_en R/W DRM transmission control
1b: Transmission enabled
0b: Transmission disabled
6 nvbi_tx_en R/W NTSC VBI transmission control
5 amp_tx_en R/W AMP transmission control
4 aut_tx_en R/W ACP, SPD, VSIF, ISRC1, and SRC2 packet transmission
control
Exists: Always
3 audi_tx_en R/W AUDI packet transmission control
Exists: Always
2 avi_tx_en R/W AVI packet transmission control
Exists: Always

Table 6-189 Fields for Register: fc_packet_tx_en (Continued)
Memory
1 gcp_tx_en R/W GCP transmission control
Exists: Always
0 acr_tx_en R/W ACR packet transmission control
Exists: Always

6.5.137 fc_actspc_hdlr_cfg
■ Description: Frame Composer Active Space Control
■ Size: 8 bits
■ Offset: 0x10e8
Table 6-190 Fields for Register: fc_actspc_hdlr_cfg
Memory
1 actspc_hdlr_tgl R/W Active Space handler control
1b: Active space 1 value is different from Active Space 2
value. Refer to Figure 8-4: 3D Structure of the HDMI 1.4b
specification.
0b: Active space not oscillating
Exists: Always
0 actspc_hdlr_en R/W Active Space Handler Control
1b: Fixed active space value mode enabled. During active
space, a fixed value of 0xAA is applied to all TMDS
channels.
0b: Fixed active space value mode disabled
Exists: Always
6.5.138 fc_invact_2d_0
■ Description: Frame Composer Input Video 2D VActive Pixels Register 0
■ Size: 8 bits
■ Offset: 0x10e9
Table 6-191 Fields for Register: fc_invact_2d_0
Memory
7:0 fc_invact_2d_0 R/W 2D Input video vertical active pixel region width. Number of
2D video vertical active lines [7:0].
Exists: Always

6.5.139 fc_invact_2d_1
■ Description: Frame Composer Input Video VActive pixels Register 1
■ Size: 8 bits
■ Offset: 0x10ea
Table 6-192 Fields for Register: fc_invact_2d_1
Memory
3:0 fc_invact_2d_1 R/W 2D Input video vertical active pixel region width. Number of
2D video vertical active lines [11:8].
Exists: Always

6.5.140 fc_gmd_stat
■ Description: Frame Composer GMD Packet Status Register
Gamut metadata packet status bit information for no_current_gmd, next_gmd_field,
gmd_packet_sequence and current_gamut_seq_num. For more information, refer to the HDMI 1.4b
specification.
■ Size: 8 bits
■ Offset: 0x1100
■ Exists: Always
Table 6-193 Fields for Register: fc_gmd_stat
Memory
7 igmdno_crnt_gbd R Gamut scheduling: No current gamut data
Exists: Always
6 igmddnext_field R Gamut scheduling: Gamut Next field
Exists: Always
5:4 igmdpacket_seq R Gamut scheduling: Gamut packet sequence
Exists: Always
3:0 igmdcurrent_gamut_seq_num R Gamut scheduling: Current Gamut packet sequence number
Exists: Always

6.5.141 fc_gmd_en
■ Description: Frame Composer GMD Packet Enable Register
This register enables Gamut metadata (GMD) packet transmission. Packets are inserted in the
incoming frame, starting in the line where active Vsync indication starts. After enable of GMD
packets the outgoing packet is sent with no_current_gmd active indication until update GMD request
is performed in the controller.
■ Size: 8 bits
■ Offset: 0x1101
■ Exists: Always
Table 6-194 Fields for Register: fc_gmd_en
Memory
0 gmdenabletx R/W Gamut Metadata packet transmission enable (1b)
Exists: Always

6.5.142 fc_gmd_up
■ Description: Frame Composer GMD Packet Update Register
This register performs an GMD packet content update according to the configured packet body
(FC_GMD_PB0 to FC_GMD_PB27) and packet header (FC_GMD_HB). This active high auto clear
register reflects the body and header configurations on the GMD packets sent arbitrating the
current_gamut_seq_num, gmd_packet_sequence and next_gmd_field bits on packet to correctly
indicate to source the Gamut change to be performed. After enable GMD packets the first update
request is also responsible for deactivating the no_current_gmd indication bit.
Attention packet update request must only be done after correct configuration of GMD packet body
and header registers. Correct affected_gamut_seq_num and gmd_profile configuration is user
responsibility and must convey with HDMI 1.4b standard gamut rules.
■ Size: 8 bits
■ Offset: 0x1102
■ Exists: Always
Table 6-195 Fields for Register: fc_gmd_up
Memory
0 gmdupdatepacket W Gamut Metadata packet update
Exists: Always

6.5.143 fc_gmd_conf
■ Description: Frame Composer GMD Packet Schedule Configuration Register
This register configures the number of GMD packets to be inserted per frame (starting always in the
line where the active Vsync appears) and the line spacing between the transmitted GMD packets.
Note that for profile P0 (refer to the HDMI 1.4b specification) this register should only indicate one
GMD packet to be inserted per video field.
■ Size: 8 bits
■ Offset: 0x1103
■ Exists: Always
Table 6-196 Fields for Register: fc_gmd_conf
Memory
7:4 gmdpacketsinframe R/W Number of GMD packets per frame or video field (profile P0)
Exists: Always
3:0 gmdpacketlinespacing R/W Number of line spacing between the transmitted GMD
packets
Exists: Always

6.5.144 fc_gmd_hb
■ Description: Frame Composer GMD Packet Profile and Gamut Sequence Configuration Register
This register configures the GMD packet header affected_gamut_seq_num and gmd_profile bits. For
more information, refer to the HDMI 1.4b specification.
■ Size: 8 bits
■ Offset: 0x1104
■ Exists: Always
Table 6-197 Fields for Register: fc_gmd_hb
Memory
6:4 gmdgbd_profile R/W GMD profile bits. DWC_hdmi_tx only supports Profile 0 (P0)
of the Gamut Boundary Description Metadata Profiles
described in the HDMI 1.4 Specification (which defines four
profiles, P0-P4).
Exists: Always
3:0 gmdaffected_gamut_seq_num R/W Affected gamut sequence number
Exists: Always

6.5.145 fc_gmd_pb[0:27]
■ Description: Frame Composer GMD Packet Body Register Array
Configures the GMD packet body of the GMD packet.
■ Size: 8 bits
■ Offset: 0x1105 + (i * 0x1)
■ Exists: Always
Table 6-198 Fields for Register: fc_gmd_pb[0:27]
Memory
7:0 fc_gmd_pb R/W Frame Composer GMD Packet Body Register Array
Exists: Always
6.5.146 fc_amp_hb1
■ Description: Frame Composer AMP Packet Header Register 1
■ Size: 8 bits
■ Offset: 0x1128
Table 6-199 Fields for Register: fc_amp_hb1
Memory
7:0 fc_amp_hb0 R/W Frame Composer AMP Packet Header Register 1
Exists: Always

6.5.147 fc_amp_hb2
■ Description: Frame Composer AMP Packet Header Register 2
■ Size: 8 bits
■ Offset: 0x1129
Table 6-200 Fields for Register: fc_amp_hb2
Memory
7:0 fc_amp_hb1 R/W Frame Composer AMP Packet Header Register 2
Exists: Always
6.5.148 fc_amp_pb[0:27]
■ Description: Frame Composer AMP Packet Body Register Array
■ Size: 8 bits
■ Offset: 0x112a + (i * 0x1)
■ Exists: Always
Table 6-201 Fields for Register: fc_amp_pb[0:27]
Memory
7:0 fc_amp_pb R/W Frame Composer AMP Packet Body Register Array
Exists: Always

6.5.149 fc_nvbi_hb1
■ Description: Frame Composer NTSC VBI Packet Header Register 1
■ Size: 8 bits
■ Offset: 0x1148
Table 6-202 Fields for Register: fc_nvbi_hb1
Memory
7:0 fc_nvbi_hb0 R/W Frame Composer NTSC VBI Packet Header Register 1
Exists: Always
6.5.150 fc_nvbi_hb2
■ Description: Frame Composer NTSC VBI Packet Header Register 2
■ Size: 8 bits
■ Offset: 0x1149
Table 6-203 Fields for Register: fc_nvbi_hb2
Memory
7:0 fc_nvbi_hb1 R/W Frame Composer NTSC VBI Packet Header Register 2
Exists: Always

6.5.151 fc_nvbi_pb[0:26]
■ Description: Frame Composer NTSC VBI Packet Body Register Array
■ Size: 8 bits
■ Offset: 0x114a + (i * 0x1)
■ Exists: Always
Table 6-204 Fields for Register: fc_nvbi_pb[0:26]
Memory
7:0 fc_nvbi_pb R/W Frame Composer NTSC VBI Packet Body Register Array
Exists: Always
6.5.152 fc_drm_up
■ Description: Frame Composer DRM Packet Update Register
This register performs an DRM packet content update according to the configured packet body
(FC_DRM_PB0 to FC_DRM_PB27) and packet header (FC_DRM_HB). This active high auto clear
register reflects the body and header configurations on the DRM packets change to be performed.
Attention packet update request must only be done after correct configuration of DRM packet body
and header registers.
■ Size: 8 bits
■ Offset: 0x1167
■ Exists: Always
Table 6-205 Fields for Register: fc_drm_up
Memory
0 drmpacketupdate W DRM packet update
Exists: Always

6.5.153 fc_drm_hb[0:1]
■ Description: Frame Composer DRM Packet Header Register Array
■ Size: 8 bits
■ Offset: 0x1168 + (i * 0x1)
■ Exists: Always
Table 6-206 Fields for Register: fc_drm_hb[0:1]
Memory
7:0 fc_drm_hb R/W Frame Composer DRM Packet Header Register Array
Exists: Always
6.5.154 fc_drm_pb[0:26]
■ Description: Frame Composer DRM Packet Body Register Array
■ Size: 8 bits
■ Offset: 0x116a + (i * 0x1)
■ Exists: Always
Table 6-207 Fields for Register: fc_drm_pb[0:26]
Memory
7:0 fc_drm_pb R/W Frame Composer DRM Packet Body Register Array
Exists: Always

6.5.155 fc_dbgforce
■ Description: Frame Composer video/audio Force Enable Register
This register allows to force the controller to output audio and video data the values configured in
the FC_DBGAUD and FC_DBGTMDS registers.
■ Size: 8 bits
■ Offset: 0x1200
■ Exists: Always
Table 6-208 Fields for Register: fc_dbgforce
Memory
4 forceaudio R/W Force fixed audio output with FC_DBGAUDxCHx register
contents.
Exists: Always
0 forcevideo R/W Force fixed video output with FC_DBGTMDSx register
contents.
Exists: Always
6.5.156 fc_dbgaud0ch0
■ Description: Frame Composer Audio Data Channel 0 Register 0
Configures the audio fixed data to be used in channel 0 when in fixed audio selection.
■ Size: 8 bits
■ Offset: 0x1201
■ Exists: Always
Table 6-209 Fields for Register: fc_dbgaud0ch0
Memory
7:0 fc_dbgaud0ch0 R/W Frame Composer Audio Data Channel 0 Register 0
Exists: Always

■ Size: 8 bits
■ Offset: 0x1202
■ Exists: Always
Memory
Exists: Always
■ Size: 8 bits
■ Offset: 0x1203
■ Exists: Always
Memory
Exists: Always

■ Size: 8 bits
■ Offset: 0x1204
■ Exists: Always
Memory
Exists: Always
■ Size: 8 bits
■ Offset: 0x1205
■ Exists: Always
Memory
Exists: Always

■ Size: 8 bits
■ Offset: 0x1206
■ Exists: Always
Memory
Exists: Always
■ Size: 8 bits
■ Offset: 0x1207
■ Exists: Always
Memory
Exists: Always

■ Size: 8 bits
■ Offset: 0x1208
■ Exists: Always
Memory
Exists: Always
■ Size: 8 bits
■ Offset: 0x1209
■ Exists: Always
Memory
Exists: Always

■ Size: 8 bits
■ Offset: 0x120a
■ Exists: Always
Memory
Exists: Always
■ Size: 8 bits
■ Offset: 0x120b
■ Exists: Always
Memory
Exists: Always

■ Size: 8 bits
■ Offset: 0x120c
■ Exists: Always
Memory
Exists: Always
■ Size: 8 bits
■ Offset: 0x120d
■ Exists: Always
Memory
Exists: Always

■ Size: 8 bits
■ Offset: 0x120e
■ Exists: Always
Memory
Exists: Always
■ Size: 8 bits
■ Offset: 0x120f
■ Exists: Always
Memory
Exists: Always

■ Size: 8 bits
■ Offset: 0x1210
■ Exists: Always
Memory
Exists: Always
■ Size: 8 bits
■ Offset: 0x1211
■ Exists: Always
Memory
Exists: Always

■ Size: 8 bits
■ Offset: 0x1212
■ Exists: Always
Memory
Exists: Always
■ Size: 8 bits
■ Offset: 0x1213
■ Exists: Always
Memory
Exists: Always

■ Size: 8 bits
■ Offset: 0x1214
■ Exists: Always
Memory
Exists: Always
■ Size: 8 bits
■ Offset: 0x1215
■ Exists: Always
Memory
Exists: Always

■ Size: 8 bits
■ Offset: 0x1216
■ Exists: Always
Memory
Exists: Always
■ Size: 8 bits
■ Offset: 0x1217
■ Exists: Always
Memory
Exists: Always

■ Size: 8 bits
■ Offset: 0x1218
■ Exists: Always
Memory
Exists: Always
6.5.180 fc_dbgtmds[0:2]
■ Description: Frame Composer TMDS Data Channel Register Array
Configures the video fixed data to be used in TMDS channel x (where x is 0 to 2) when in fixed video
selection.
❑ For Channel 0, this equals to set B pixel component value in RGB video or Cb pixel component
value in YCbCr.
❑ For Channel 1, this equals set G pixel component value in RGB video or Y pixel component value
in YCbCr.
❑ For Channel 2, this equals to set R pixel component value in RGB video or Cr pixel component
value in YCbCr.
■ Size: 8 bits
■ Offset: 0x1219 + (i * 0x1)
■ Exists: Always
Table 6-233 Fields for Register: fc_dbgtmds[0:2]
Memory
7:0 fc_dbgtmds R/W Frame Composer TMDS Data Channel 0 Register
Exists: Always

6.6 PHYConfiguration Registers

PHY Configuration Registers. Follow the link for the register to see a detailed description of the register.
Table 6-234 Registers for Address Block: PHYConfiguration

phy_conf0 on page 350 0x3000 PHY Configuration Register This register holds the power
down, data enable polarity, and interface...
phy_tst0 on page 351 0x3001 PHY Test Interface Register 0 PHY TX mapped test interface
(control). For more information, refer...
phy_tst1 on page 352 0x3002 PHY Test Interface Register 1 PHY TX mapped text interface
(data in). For more information, refer...
phy_tst2 on page 352 0x3003 PHY Test Interface Register 2 PHY TX mapped text interface
(data out). For more information, refer...
phy_stat0 on page 353 0x3004 PHY RXSENSE, PLL Lock, and HPD Status Register This
register contains the following active high...
phy_int0 on page 354 0x3005 PHY RXSENSE, PLL Lock, and HPD Interrupt Register This
register contains the interrupt indication...
phy_mask0 on page 355 0x3006 PHY RXSENSE, PLL Lock, and HPD Mask Register Mask
register for generation of PHY_INT0...
phy_pol0 on page 356 0x3007 PHY RXSENSE, PLL Lock, and HPD Polarity Register
Polarity register for generation of PHY_INT0...
PHY_PCLFREQ0 on page 357 0x3008 PHY Test Interface Register 0
PHY_PCLFREQ1 on page 357 0x3009 PHY Test Interface Register 1
PHY_PLLCFGFREQ0 on page 358 0x300a PHY PLL Test Interface Register 0
PHY_PLLCFGFREQ1 on page 358 0x300b PHY PLL Test Interface Register 1
PHY_PLLCFGFREQ2 on page 359 0x300c PHY PLL Test Interface Register 2
phy_i2cm_slave on page 359 0x3020 PHY I2C Slave Address Configuration Register
phy_i2cm_address on page 360 0x3021 PHY I2C Address Configuration Register This register writes
the address for read and write...
phy_i2cm_datao_1 on page 360 0x3022 PHY I2C Data Write Register 1
phy_i2cm_datao_0 on page 361 0x3023 PHY I2C Data Write Register 0
phy_i2cm_datai_1 on page 361 0x3024 PHY I2C Data Read Register 1
phy_i2cm_datai_0 on page 362 0x3025 PHY I2C Data Read Register 0
phy_i2cm_operation on page 362 0x3026 PHY I2C RD/RD_EXT/WR Operation Register This register
requests read and write operations from the...
phy_i2cm_int on page 363 0x3027 PHY I2C Done Interrupt Register This register contains and
configures I2C master PHY done...

Table 6-234 Registers for Address Block: PHYConfiguration (Continued)

phy_i2cm_ctlint on page 364 0x3028 PHY I2C error Interrupt Register This register contains and
configures the I2C master PHY error...
phy_i2cm_div on page 365 0x3029 PHY I2C Speed control Register This register wets the I2C
Master PHY to work in either Fast or...
phy_i2cm_softrstz on page 366 0x302a PHY I2C SW reset control register This register sets the I2C
Master PHY software reset.
phy_i2cm_ss_scl_hcnt_1_addr on 0x302b PHY I2C Slow Speed SCL High Level Control Register 1
page 366
phy_i2cm_ss_scl_hcnt_0_addr on 0x302c PHY I2C Slow Speed SCL High Level Control Register 0
page 367
phy_i2cm_ss_scl_lcnt_1_addr on 0x302d PHY I2C Slow Speed SCL Low Level Control Register 1
page 367
phy_i2cm_ss_scl_lcnt_0_addr on 0x302e PHY I2C Slow Speed SCL Low Level Control Register 0
page 368
phy_i2cm_fs_scl_hcnt_1_addr on 0x302f PHY I2C Fast Speed SCL High Level Control Register 1
page 368
phy_i2cm_fs_scl_hcnt_0_addr on 0x3030 PHY I2C Fast Speed SCL High Level Control Register 0
page 369
phy_i2cm_fs_scl_lcnt_1_addr on 0x3031 PHY I2C Fast Speed SCL Low Level Control Register 1
page 369
phy_i2cm_fs_scl_lcnt_0_addr on 0x3032 PHY I2C Fast Speed SCL Low Level Control Register 0
page 370
phy_i2cm_sda_hold on page 370 0x3033 PHY I2C SDA HOLD Control Register
jtag_phy_config on page 371 0x3034 PHY I2C/JTAG I/O Configuration Control Register
jtag_phy_tap_tck on page 372 0x3035 PHY JTAG Clock Control Register
jtag_phy_tap_in on page 372 0x3036 PHY JTAG TAP In Control Register
jtag_phy_tap_out on page 373 0x3037 PHY JTAG TAP Out Control Register
jtag_phy_addr on page 373 0x3038 PHY JTAG Address Control Register

6.6.1 phy_conf0
■ Description: PHY Configuration Register
This register holds the power down, data enable polarity, and interface control of the HDMI Source
PHY control. For more information, refer to the DesignWare Cores HDMI TX PHY Databook.
■ Size: 8 bits
■ Offset: 0x3000
■ Exists: Always
Table 6-235 Fields for Register: phy_conf0
Memory
7 PDZ R/W Power-down enable (active low 0b). Otherwise, this field is a "spare" bit
with no associated functionality.
Exists: (PHY_GEN2==0 && PHY_EXTERNAL==0)
6 ENTMDS R/W Enable TMDS drivers, bias, and TMDS digital logic. Otherwise, this field
5 svsret R/W PHY SVSRET signal. Otherwise, this field is a "spare" bit with no
associated functionality.
Exists: (PHY_MHL_COMBO==1)
4 pddq R/W PHY PDDQ signal. Otherwise, this field is a "spare" bit with no
Value After Reset: "(PHY_MHL_COMBO== 1) ? 1 : 0"
Exists: (PHY_GEN2==1 || PHY_EXTERNAL==1)
3 txpwron R/W PHY TXPWRON signal. Otherwise, this field is a "spare" bit with no
2 enhpdrxsense R/W PHY ENHPDRXSENSE signal. Otherwise, this field is a "spare" bit with
no associated functionality.
1 seldataenpol R/W Select data enable polarity.
Exists: Always
0 seldipif R/W Select interface control.
Exists: Always

6.6.2 phy_tst0
■ Description: PHY Test Interface Register 0
PHY TX mapped test interface (control). For more information, refer to the DesignWare Cores HDMI
TX PHY Databook.
■ Size: 8 bits
■ Offset: 0x3001
■ Exists: Always
Table 6-236 Fields for Register: phy_tst0
Memory
7:6 spare_2 R/W Reserved as "spare" bit with no associated functionality.
Exists: Always
5 testclr R/W Test Clear signal. Otherwise, this field is a "spare" bit with no
4 testen R/W Test Enable signal. Otherwise, this field is a "spare" bit with
3:1 spare_1 R/W Reserved as "spare" bit with no associated functionality.
Exists: Always
0 testclk R/W Test Clock signal. Otherwise, this field is a "spare" bit with no

6.6.3 phy_tst1
PHY TX mapped text interface (data in). For more information, refer to the DesignWare Cores HDMI
TX PHY Databook.
■ Size: 8 bits
■ Offset: 0x3002
■ Exists: Always
Memory
7:0 testdin R/W Test Data input Otherwise, this field is a "spare" bit with no
6.6.4 phy_tst2
PHY TX mapped text interface (data out). For more information, refer to the DesignWare Cores
HDMI TX PHY Databook.
■ Size: 8 bits
■ Offset: 0x3003
■ Exists: Always
Memory
7:0 testdout R Test Data output. Otherwise, this field is a "spare" bit with no

6.6.5 phy_stat0
■ Description: PHY RXSENSE, PLL Lock, and HPD Status Register
This register contains the following active high packet sent status indications. For more information,
refer to the DesignWare Cores HDMI TX PHY Databook.
■ Size: 8 bits
■ Offset: 0x3004
■ Exists: Always
Table 6-239 Fields for Register: phy_stat0
Memory
7 RX_SENSE_3 R Status bit. TX PHY RX_SENSE indication for TMDS channel 3 driver.
You may need to mask or change polarity of this interrupt after it has
became active.
Exists: Always
became active.
Exists: Always
became active.
Exists: Always
became active.
Exists: Always
1 HPD R Status bit. HDMI Hot Plug Detect indication. You may need to mask or
change polarity of this interrupt after it has became active.
Exists: Always
0 TX_PHY_LOCK R Status bit. TX PHY PLL lock indication. For more information, refer to
the PHY databook. You may need to mask or change polarity of this
interrupt after it has became active.
Exists: Always

6.6.6 phy_int0
■ Description: PHY RXSENSE, PLL Lock, and HPD Interrupt Register
This register contains the interrupt indication of the PHY_STAT0 status interrupts. Interrupt
generation is accomplished in the following way:
interrupt = (mask == 1'b0) && (polarity == status);
All these interrupts are forwarded to the Interrupt Handler sticky bit register ih_phy_stat0 and after
ORed to a single main interrupt line to micro controller. Assertion of this interrupt implies that data
related with the corresponding packet has been sent through the HDMI interface.
■ Size: 8 bits
■ Offset: 0x3005
■ Exists: Always
Table 6-240 Fields for Register: phy_int0
Memory
7 RX_SENSE_3 R Interrupt indication bit. TX PHY RX_SENSE indication
interruption for TMDS CLK driver.
Exists: Always
interruption for TMDS channel 2 driver.
Exists: Always
Exists: Always
Exists: Always
1 HPD R Interrupt indication bit. HDMI Hot Plug Detect indication
interrupt.
Exists: Always
0 TX_PHY_LOCK R Interrupt indication bit. TX PHY PLL lock indication interrupt.
Exists: Always

6.6.7 phy_mask0
■ Description: PHY RXSENSE, PLL Lock, and HPD Mask Register
Mask register for generation of PHY_INT0 interrupts.
■ Size: 8 bits
■ Offset: 0x3006
■ Exists: Always
Table 6-241 Fields for Register: phy_mask0
Memory
7 RX_SENSE_3 R/W Mask bit for PHY_INT0.RX_SENSE[3] interrupt bit
Exists: Always
Exists: Always
Exists: Always
Exists: Always
1 HPD R/W Mask bit for PHY_INT0.HPD interrupt bit
Exists: Always
0 TX_PHY_LOCK R/W Mask bit for PHY_INT0.TX_PHY_LOCK interrupt bit
Exists: Always

6.6.8 phy_pol0
■ Description: PHY RXSENSE, PLL Lock, and HPD Polarity Register
Polarity register for generation of PHY_INT0 interrupts.
■ Size: 8 bits
■ Offset: 0x3007
■ Exists: Always
Table 6-242 Fields for Register: phy_pol0
Memory
7 RX_SENSE_3 R/W Polarity bit for PHY_INT0.RX_SENSE[3] interrupt bit
Exists: Always
Exists: Always
Exists: Always
Exists: Always
1 HPD R/W Polarity bit for PHY_INT0.HPD interrupt bit
Exists: Always
0 TX_PHY_LOCK R/W Polarity bit for PHY_INT0.TX_PHY_LOCK interrupt bit
Exists: Always

6.6.9 PHY_PCLFREQ0
■ Size: 8 bits
■ Offset: 0x3008
■ Exists: PHY_CHRT65LPE==1
Table 6-243 Fields for Register: PHY_PCLFREQ0
Memory
7:0 pclk_freq R/W Pixel Clock Frequency (pclk_freq[7:0]). For more information,
Exists: Always
6.6.10 PHY_PCLFREQ1
■ Size: 8 bits
■ Offset: 0x3009
Table 6-244 Fields for Register: PHY_PCLFREQ1
Memory
1:0 pclk_freq R/W Pixel Clock Frequency (pclk_freq[9:8]). For more information,
Exists: Always

6.6.11 PHY_PLLCFGFREQ0
■ Description: PHY PLL Test Interface Register 0
■ Size: 8 bits
■ Offset: 0x300a
Table 6-245 Fields for Register: PHY_PLLCFGFREQ0
Memory
7:0 pllcfgfreq R/W PLL Configuration Frequency (pllcfgfreq[7:0]). For more
Exists: Always
■ Size: 8 bits
■ Offset: 0x300b
Memory
Exists: Always

■ Size: 8 bits
■ Offset: 0x300c
Memory
Exists: Always
6.6.14 phy_i2cm_slave
■ Description: PHY I2C Slave Address Configuration Register
■ Size: 8 bits
■ Offset: 0x3020
Table 6-248 Fields for Register: phy_i2cm_slave
Memory
6:0 slaveaddr R/W Slave address to be sent during read and write operations.
■ PHY Gen2 slave address: 7'h69
■ HEAC PHY slave address: 7'h49
Exists: Always

6.6.15 phy_i2cm_address
■ Description: PHY I2C Address Configuration Register
This register writes the address for read and write operations.
■ Size: 8 bits
■ Offset: 0x3021
Table 6-249 Fields for Register: phy_i2cm_address
Memory
7:0 address R/W Register address for read and write operations
Exists: Always
6.6.16 phy_i2cm_datao_1
■ Description: PHY I2C Data Write Register 1
■ Size: 8 bits
■ Offset: 0x3022
Table 6-250 Fields for Register: phy_i2cm_datao_1
Memory
7:0 datao R/W Data MSB (datao[15:8]) to be written on register pointed by
phy_i2cm_address [7:0].
Exists: Always

6.6.17 phy_i2cm_datao_0
■ Description: PHY I2C Data Write Register 0
■ Size: 8 bits
■ Offset: 0x3023
Table 6-251 Fields for Register: phy_i2cm_datao_0
Memory
7:0 datao R/W Data LSB (datao[7:0]) to be written on register pointed by
phy_i2cm_address [7:0].
Exists: Always
6.6.18 phy_i2cm_datai_1
■ Description: PHY I2C Data Read Register 1
■ Size: 8 bits
■ Offset: 0x3024
Table 6-252 Fields for Register: phy_i2cm_datai_1
Memory
7:0 datai R Data MSB (datai[15:8]) read from register pointed by
phy_i2cm_address[7:0].
Exists: Always

6.6.19 phy_i2cm_datai_0
■ Description: PHY I2C Data Read Register 0
■ Size: 8 bits
■ Offset: 0x3025
Table 6-253 Fields for Register: phy_i2cm_datai_0
Memory
7:0 datai R Data LSB (datai[7:0]) read from register pointed by
phy_i2cm_address[7:0].
Exists: Always
6.6.20 phy_i2cm_operation
■ Description: PHY I2C RD/RD_EXT/WR Operation Register
This register requests read and write operations from the I2C Master PHY. This register can only be
written; reading this register always results in 00h. Writing 1'b1 simultaneously to read and write
requests is considered a read request.
■ Size: 8 bits
■ Offset: 0x3026
Table 6-254 Fields for Register: phy_i2cm_operation
Memory
4 wr W Write operation request
Exists: Always
0 rd W Read operation request
Exists: Always

6.6.21 phy_i2cm_int
■ Description: PHY I2C Done Interrupt Register
This register contains and configures I2C master PHY done interrupt.
■ Size: 8 bits
■ Offset: 0x3027
Table 6-255 Fields for Register: phy_i2cm_int
Memory
3 done_pol R/W Done interrupt polarity configuration
Exists: Always
2 done_mask R/W Done interrupt mask signal
Exists: Always
1 done_interrupt R Operation done interrupt bit. Only lasts for 1 SFR clock cycle
and is auto cleared after it.
{done_interrupt = (done_mask==0b) &&
(done_status==done_pol)}
Exists: Always
0 done_status R Operation done status bit. Marks the end of a read or write
operation.
Exists: Always

6.6.22 phy_i2cm_ctlint
■ Description: PHY I2C error Interrupt Register
This register contains and configures the I2C master PHY error interrupts.
■ Size: 8 bits
■ Offset: 0x3028
Table 6-256 Fields for Register: phy_i2cm_ctlint
Memory
7 nack_pol R/W Not acknowledge error interrupt polarity configuration
Exists: Always
6 nack_mask R/W Not acknowledge error interrupt mask signal
Exists: Always
5 nack_interrupt R Not acknowledge error interrupt bit. Only lasts for one SFR clock
cycle and is auto cleared after it.
{nack_interrupt = (nack_mask==0b) && (nack_status==nack_pol)}.
Note: This bit field is read by the sticky bits present on the
ih_i2cmphy_stat0 register.
Exists: Always
4 nack_status R Not acknowledge error status bit. Error on I2C not acknowledge.
Exists: Always
3 arbitration_pol R/W Arbitration error interrupt polarity configuration.
Exists: Always
2 arbitration_mask R/W Arbitration error interrupt mask signal.
Exists: Always

Table 6-256 Fields for Register: phy_i2cm_ctlint (Continued)
Memory
1 arbitration_interrupt R Arbitration error interrupt bit
{arbitration_interrupt = (arbitration_mask==0b) &&
(arbitration_status==arbitration_pol)}
Exists: Always
0 arbitration_status R Arbitration error status bit. Error on master I2C protocol arbitration.
Only lasts for one SFR clock cycle and is auto cleared after it.
Exists: Always
6.6.23 phy_i2cm_div
■ Description: PHY I2C Speed control Register
This register wets the I2C Master PHY to work in either Fast or Standard mode.
■ Size: 8 bits
■ Offset: 0x3029
Table 6-257 Fields for Register: phy_i2cm_div
Memory
3 fast_std_mode R/W Sets the I2C Master to work in Fast Mode or Standard Mode:
1: Fast Mode
0: Standard Mode
Exists: Always
2:0 spare R/W Reserved as "spare" register with no associated functionality.
Exists: Always

6.6.24 phy_i2cm_softrstz
■ Description: PHY I2C SW reset control register
This register sets the I2C Master PHY software reset.
■ Size: 8 bits
■ Offset: 0x302a
Table 6-258 Fields for Register: phy_i2cm_softrstz
Memory
0 i2c_softrstz R/W I2C Master Software Reset. Active by writing a zero and auto
cleared to one in the following cycle.
Exists: Always
6.6.25 phy_i2cm_ss_scl_hcnt_1_addr
■ Description: PHY I2C Slow Speed SCL High Level Control Register 1
■ Size: 8 bits
■ Offset: 0x302b
Table 6-259 Fields for Register: phy_i2cm_ss_scl_hcnt_1_addr
Memory
7:0 i2cmp_ss_scl_hcnt1 R/W PHY I2C Slow Speed SCL High Level Control Register 1
Exists: Always

6.6.26 phy_i2cm_ss_scl_hcnt_0_addr
■ Description: PHY I2C Slow Speed SCL High Level Control Register 0
■ Size: 8 bits
■ Offset: 0x302c
Table 6-260 Fields for Register: phy_i2cm_ss_scl_hcnt_0_addr
Memory
7:0 i2cmp_ss_scl_hcnt0 R/W PHY I2C Slow Speed SCL High Level Control Register 0
Value After Reset: 0x6c
Exists: Always
6.6.27 phy_i2cm_ss_scl_lcnt_1_addr
■ Description: PHY I2C Slow Speed SCL Low Level Control Register 1
■ Size: 8 bits
■ Offset: 0x302d
Table 6-261 Fields for Register: phy_i2cm_ss_scl_lcnt_1_addr
Memory
7:0 i2cmp_ss_scl_lcnt1 R/W PHY I2C Slow Speed SCL Low Level Control Register 1
Exists: Always

6.6.28 phy_i2cm_ss_scl_lcnt_0_addr
■ Description: PHY I2C Slow Speed SCL Low Level Control Register 0
■ Size: 8 bits
■ Offset: 0x302e
Table 6-262 Fields for Register: phy_i2cm_ss_scl_lcnt_0_addr
Memory
7:0 i2cmp_ss_scl_lcnt0 R/W PHY I2C Slow Speed SCL Low Level Control Register 0
Value After Reset: 0x7f
Exists: Always
6.6.29 phy_i2cm_fs_scl_hcnt_1_addr
■ Description: PHY I2C Fast Speed SCL High Level Control Register 1
■ Size: 8 bits
■ Offset: 0x302f
Table 6-263 Fields for Register: phy_i2cm_fs_scl_hcnt_1_addr
Memory
7:0 i2cmp_fs_scl_hcnt1 R/W PHY I2C Fast Speed SCL High Level Control Register 1
Exists: Always

6.6.30 phy_i2cm_fs_scl_hcnt_0_addr
■ Description: PHY I2C Fast Speed SCL High Level Control Register 0
■ Size: 8 bits
■ Offset: 0x3030
Table 6-264 Fields for Register: phy_i2cm_fs_scl_hcnt_0_addr
Memory
7:0 i2cmp_fs_scl_hcnt0 R/W PHY I2C Fast Speed SCL High Level Control Register 0
Exists: Always
6.6.31 phy_i2cm_fs_scl_lcnt_1_addr
■ Description: PHY I2C Fast Speed SCL Low Level Control Register 1
■ Size: 8 bits
■ Offset: 0x3031
Table 6-265 Fields for Register: phy_i2cm_fs_scl_lcnt_1_addr
Memory
7:0 i2cmp_fs_scl_lcnt1 R/W PHY I2C Fast Speed SCL Low Level Control Register 1
Exists: Always

6.6.32 phy_i2cm_fs_scl_lcnt_0_addr
■ Description: PHY I2C Fast Speed SCL Low Level Control Register 0
■ Size: 8 bits
■ Offset: 0x3032
Table 6-266 Fields for Register: phy_i2cm_fs_scl_lcnt_0_addr
Memory
7:0 i2cmp_fs_scl_lcnt0 R/W PHY I2C Fast Speed SCL Low Level Control Register 0
Exists: Always
6.6.33 phy_i2cm_sda_hold
■ Description: PHY I2C SDA HOLD Control Register
■ Size: 8 bits
■ Offset: 0x3033
Table 6-267 Fields for Register: phy_i2cm_sda_hold
Memory
7:0 osda_hold R/W Defines the number of SFR clock cycles to meet tHD:DAT
(300 ns)
osda_hold = round_to_high_integer (300 ns /
(1/isfrclk_frequency))
Exists: Always

6.6.34 jtag_phy_config
■ Description: PHY I2C/JTAG I/O Configuration Control Register
■ Size: 8 bits
■ Offset: 0x3034
■ Exists: PHY_MHL_COMBO==1 || PHY_EXTERNAL==1
Table 6-268 Fields for Register: jtag_phy_config
Memory
4 i2c_jtagz R/W Configures the JTAG PHY interface output pin I2C_JTAGZ to
select the PHY configuration interface when in internal
control mode (iphy_ext_ctrl=1'b0) or ophyext_jtag_i2c_jtagz
when PHY_EXTERNAL=1.
■ 1'b0: JTAG configuration Interface
■ 1'b1: I2C configuration Interface
Exists: Always
0 jtag_trst_n R/W Configures the JTAG PHY interface output pin
JTAG_TRST_N when in internal control mode
(iphy_ext_ctrl=1'b0) or ophyext_jtag_trst_n when
PHY_EXTERNAL=1.
Exists: Always

6.6.35 jtag_phy_tap_tck
■ Description: PHY JTAG Clock Control Register
■ Size: 8 bits
■ Offset: 0x3035
Table 6-269 Fields for Register: jtag_phy_tap_tck
Memory
0 jtag_tck R/W Configures the JTAG PHY interface pin JTAG_TCK when in
internal control mode (iphy_ext_ctrl=1'b0) or
ophyext_jtag_tck when PHY_EXTERNAL=1.
Exists: Always
6.6.36 jtag_phy_tap_in
■ Description: PHY JTAG TAP In Control Register
■ Size: 8 bits
■ Offset: 0x3036
Table 6-270 Fields for Register: jtag_phy_tap_in
Memory
4 jtag_tms R/W Configures the JTAG PHY interface pin JTAG_TMS when in
ophyext_jtag_tms when PHY_EXTERNAL=1.
Exists: Always
0 jtag_tdi R/W Configures the JTAG PHY interface pin JTAG_TDI when in
ophyext_jtag_tdi when PHY_EXTERNAL=1.
Exists: Always

6.6.37 jtag_phy_tap_out
■ Description: PHY JTAG TAP Out Control Register
■ Size: 8 bits
■ Offset: 0x3037
Table 6-271 Fields for Register: jtag_phy_tap_out
Memory
4 jtag_tdo_en R Read JTAG PHY interface input pin JTAG_TDO_EN when in
iphyext_jtag_tdo_en when PHY_EXTERNAL=1
Exists: Always
0 jtag_tdo R Read JTAG PHY interface input pin JTAG_TDO when in
iphyext_jtag_tdo when PHY_EXTERNAL=1
Exists: Always
6.6.38 jtag_phy_addr
■ Description: PHY JTAG Address Control Register
■ Size: 8 bits
■ Offset: 0x3038
Table 6-272 Fields for Register: jtag_phy_addr
Memory
7:0 jtag_addr R/W Configures the JTAG PHY interface pin JTAG_ADDR[7:0]
when in internal control mode (iphy_ext_ctrl=1'b0) or
iphyext_jtag_addr[7:0] when PHY_EXTERNAL=1
Exists: Always

6.7 AudioSample Registers

Audio Sample Registers. Follow the link for the register to see a detailed description of the register.
Table 6-273 Registers for Address Block: AudioSample

aud_conf0 on page 375 0x3100 Audio I2S Software FIFO Reset, Select, and Enable Control
Register 0 This register configures the...
aud_conf1 on page 376 0x3101 Audio I2S Width Configuration Register 1 This register
configures the data width of the input...
aud_int on page 377 0x3102 I2S FIFO status and interrupts. This register configures the
I2S FIFO status and interrupts.
aud_conf2 on page 378 0x3103 Audio I2S PCUV, NLPCM and HBR configuration Register 2
This register configures the I2S Audio Data...
aud_int1 on page 379 0x3104 I2S Mask Interrupt Register This register masks the
interrupts present in the I2S module.

6.7.1 aud_conf0
■ Description: Audio I2S Software FIFO Reset, Select, and Enable Control Register 0
This register configures the I2S input enable that indicates which input I2S channels have valid data.
It also allows the system processor to reset audio FIFOs upon underflow/overflow error detection.
■ Size: 8 bits
■ Offset: 0x3100
■ Exists: I2SPORTS==1
Table 6-274 Fields for Register: aud_conf0
Memory
7 sw_audio_fifo_rst R/W Audio FIFOs software reset
■ Writing 0b: no action taken
■ Writing 1b: Resets all audio FIFOs
Reading from this register always returns 0b.
Note: If a FIFO reset request (via SFR command) lands in
the middle of an I2S transaction, the samples become
misaligned (left-right sequence lost). As a solution, for each
FIFO reset, an associated I2S reset must be issued (writing
8'hF7 to MC_SWRSTZ register).
Exists: Always
Exists: Always
5 i2s_select R/W 1b: Selects I2S Audio Interface 0b: Selects the second
(SPDIF/GPA) interface, in configurations with more that one
audio interface (DOUBLE/GDOUBLE)
Exists: Always
Exists: Always
3:0 I2S_in_en R/W Action
I2S_in_en[0] - I2Sdata[0] enable
Exists: Always

6.7.2 aud_conf1
■ Description: Audio I2S Width Configuration Register 1
This register configures the data width of the input data.
■ Size: 8 bits
■ Offset: 0x3101
Memory
4:0 I2S_width R/W I2S input data width
I2S_width[4:0] | Action
00000b-01111b | Not used
10000b | 16 bit data samples at input
11001b-11111b | Not Used
Exists: Always

6.7.3 aud_int
■ Description: I2S FIFO status and interrupts.
This register configures the I2S FIFO status and interrupts.
■ Size: 8 bits
■ Offset: 0x3102
Table 6-276 Fields for Register: aud_int
Memory
3 fifo_empty_mask R/W FIFO empty mask.
Exists: Always
2 fifo_full_mask R/W FIFO full mask.
Exists: Always

6.7.4 aud_conf2
■ Description: Audio I2S PCUV, NLPCM and HBR configuration Register 2
This register configures the I2S Audio Data mapping. By default, audio data mapping is the standard
I2S Linear PCM (L-PCM) mapping. You can choose to use the I2S interface to transport HBR or Non-
Linear PCM (NL-PCM) audio, by setting the relevant bit in this register.
■ Size: 8 bits
■ Offset: 0x3103
Memory
2 insert_pcuv R/W When set (1'b1), this bit enables the insertion of the PCUV
(Parity, Channel Status, User bit and Validity) bits on the
incoming audio stream (support limited to Linear PCM
audio). If disabled, the incoming audio stream must contain
the PCUV bits, mapped according to Databook.
Exists: Always
1 NLPCM R/W I2S NLPCM Mode Enable. When enabled, this bit assumes
that PCUV data is included on the I2S audio stream
according to the description located in the "I2S Interface"
section of Chapter 2, "Functional Description."
Exists: Always
0 HBR R/W I2S HBR Mode Enable. When enabled, the I2S audio stream
is transmitted using HBR packets.
Exists: Always

6.7.5 aud_int1
■ Description: I2S Mask Interrupt Register
This register masks the interrupts present in the I2S module.
■ Size: 8 bits
■ Offset: 0x3104
Table 6-278 Fields for Register: aud_int1
Memory
4 fifo_overrun_mask R/W FIFO overrun mask
Exists: Always

6.8 AudioPacketizer Registers

Audio Packetizer Registers. Follow the link for the register to see a detailed description of the register.
Table 6-279 Registers for Address Block: AudioPacketizer

aud_n1 on page 381 0x3200 Audio Clock Regenerator N Value Register 1 For N expected
values, refer to the HDMI 1.4b...
aud_cts1 on page 383 0x3203 Audio Clock Regenerator CTS Value Register 1 For CTS
expected values, refer to the HDMI 1.4b...
aud_cts2 on page 383 0x3204 Audio Clock Regenerator CTS Register 2 For CTS expected
aud_cts3 on page 384 0x3205 Audio Clock Regenerator CTS value Register 3. For CTS
expected values, refer to the HDMI 1.4b...
aud_inputclkfs on page 385 0x3206 Audio Input Clock FS Factor Register
aud_cts_dither on page 386 0x3207 Audio CTS Dither Register

6.8.1 aud_n1
■ Description: Audio Clock Regenerator N Value Register 1
For N expected values, refer to the HDMI 1.4b specification.
■ Size: 8 bits
■ Offset: 0x3200
■ Exists: Always
Table 6-280 Fields for Register: aud_n1
Memory
7:0 AudN R/W HDMI Audio Clock Regenerator N value
Exists: Always
6.8.2 aud_n2
■ Size: 8 bits
■ Offset: 0x3201
■ Exists: Always
Memory
Exists: Always

6.8.3 aud_n3
■ Size: 8 bits
■ Offset: 0x3202
■ Exists: Always
Memory
7 ncts_atomic_write R/W When set, the new N and CTS values are only used when
aud_n1 register is written. If clear, N and CTS data is
updated each time a new N or CTS byte is written.
The following write sequence is recommended:
1. aud_n3 (set bit ncts_atomic_write if desired)
2. aud_cts3 (set CTS_manual and CTS value if
desired/enabled)
3. aud_cts2 (required in CTS_manual)
4. aud_cts1 (required in CTS_manual)
5. aud_n3 (bit ncts_atomic_write with same value as in step
1.)
6. aud_n2
7. aud_n1
For dynamic N/CTS changes, perform only steps from 2-7 or
5-7 depending on the state of CTS_manual.
Exists: Always
Exists: Always

6.8.4 aud_cts1
■ Description: Audio Clock Regenerator CTS Value Register 1
For CTS expected values, refer to the HDMI 1.4b specification.
■ Size: 8 bits
■ Offset: 0x3203
■ Exists: Always
Table 6-283 Fields for Register: aud_cts1
Memory
7:0 AudCTS R/W HDMI Audio Clock Regenerator CTS calculated value. This
value can be manually set using the CTS_manual
(AUD_CTS3) mechanism.
Exists: Always
6.8.5 aud_cts2
■ Description: Audio Clock Regenerator CTS Register 2
For CTS expected values, refer to the HDMI 1.4b specification.
■ Size: 8 bits
■ Offset: 0x3204
■ Exists: Always
Memory
Exists: Always

6.8.6 aud_cts3
■ Description: Audio Clock Regenerator CTS value Register 3. For CTS expected values, refer to the
HDMI 1.4b specification.
■ Size: 8 bits
■ Offset: 0x3205
■ Exists: Always
Memory
7:5 spare R/W Reserved as "spare" bit with no associated functionality.
Exists: Always
4 CTS_manual R/W If the CTS_manual bit equals 0b, this registers contains
audCTS[19:0] generated by the Cycle time counter
according to the specified timing. If the CTS_manual bit
equals 1b, this register is configured with the audCTS[7:0]
value that is output by the Audio Packetizer.
Note: When the General Parallel Audio Interface (GPAUD) is
enabled (AUDIO_IF = 6) or the AHB DMA Audio Interface is
enabled (AUDIO_IF = 8), writing to these bits has no effect;
reading these bits always return 0.
Exists: Always
Exists: Always

6.8.7 aud_inputclkfs
■ Description: Audio Input Clock FS Factor Register
■ Size: 8 bits
■ Offset: 0x3206
■ Exists: Always
Table 6-286 Fields for Register: aud_inputclkfs
Memory
2:0 ifsfactor R/W Fs factor configuration:
ifsfactor[2:0] | Audio Clock | Action
0| 128xFs | If you select the Bypass SPDIF DRU unit in
coreConsultant, the input audio clock (either I2S or SPDIF according
to configuration) is used at the audio packetizer to calculate the CTS
value and ACR packet insertion rate.
1| 256xFs | The input audio clock (I2S only) is divided by 2 and
then used at audio packetizer to calculate the CTS value and ACR
packet insertion rate.
2 | 512xFs | The input audio clock (either I2S or SPDIF according to
configuration) used divided by 4 and then used at the audio
packetizer to calculate the CTS value and ACR packet insertion rate.
Note: When the SPDIF interface is receiving an HBR audio stream
("Support for HBR over SDPIF" parameter must be enabled), it is
required that the selected IFSFACTOR to be set at 512xFs in order to
comply with the HDMI ACR requirements for HBR audio streams.
3 | Reserved
4 | 64xFs | The input audio clock (I2S only) is multiplied by 2 and
then used at the audio packetizer to calculate the CTS value and ACR
packet insertion rate.
others | 128xFs | If you select the Bypass SPDIF DRU unit in
coreConsultant, the input audio clock (either I2S or SPDIF according
to configuration) is used at the audio packetizer to calculate the CTS
value and ACR packet insertion rate.
The SPDIF interface, for non HBR audio, requires that the configured
oversampling value to be 128xFs when HTX_SPDIFBYPDRU is
enabled and 512xFs if not. When the SPDIF interface is receiving
HBR audio (HBR_ON_SPDIF must be enabled), in order to comply
with the HDMI ACR requirements for HBR audio streams.
Exists: (GPAUDIF==0 && AHBAUDDMAIF==0)

6.8.8 aud_cts_dither
■ Description: Audio CTS Dither Register
■ Size: 8 bits
■ Offset: 0x3207
■ Exists: Always
Table 6-287 Fields for Register: aud_cts_dither
Memory
7:4 dividend R/W Dither dividend (4'd1 if no CTS Dither)
This field should be configured with the value of dividend
from the HDMI specification.
Note: This value is only meaningful when operating in N/CTS
manual mode. Value 4'd0 is not supported.
Exists: Always
3:0 divisor R/W Dither divisor (4'd1 if no CTS Dither). This field should be
configured with the value of divisor from the HDMI
specification.
Note: This value is only meaningful when operating in N/CTS
manual mode. Value 4'd0 is not supported.
Exists: Always

6.9 AudioSampleSPDIF Registers

Audio Sample SPDIF Registers. Follow the link for the register to see a detailed description of the register.
Table 6-288 Registers for Address Block: AudioSampleSPDIF

aud_spdif0 on page 388 0x3300 Audio SPDIF Software FIFO Reset Control Register 0 This
register allows the system processor to...
aud_spdif1 on page 389 0x3301 Audio SPDIF NLPCM and Width Configuration Register 1
This register configures the SPDIF data...
aud_spdifint on page 390 0x3302 Audio SPDIF FIFO Empty/Full Mask Register
aud_spdifint1 on page 391 0x3303 Audio SPDIF Mask Interrupt Register 1 This register masks
interrupts present in the SPDIF...
aud_spdif2 on page 391 0x3304 Audio SPDIF Enable Confiiguration Register 2 This register
configures the SPDIF input enable that...

6.9.1 aud_spdif0
■ Description: Audio SPDIF Software FIFO Reset Control Register 0
This register allows the system processor to reset audio FIFOs upon underflow/overflow error
detection.
■ Size: 8 bits
■ Offset: 0x3300
■ Exists: SPDIFPORTS==1
Table 6-289 Fields for Register: aud_spdif0
Memory
Writing 0b: no action taken
Writing 1b: Resets all audio FIFOs
Note: If a FIFO reset request (via register write command)
lands in the middle of an SPDIF audio transaction, the
samples become misaligned (left-right sequence lost). As a
solution, for each FIFO reset, an associated SPDIF reset
must be issued (writing 8'hEF to MC_SWRSTZ register).
Exists: Always
Exists: Always

6.9.2 aud_spdif1
■ Description: Audio SPDIF NLPCM and Width Configuration Register 1
This register configures the SPDIF data width.
■ Size: 8 bits
■ Offset: 0x3301
Memory
7 setnlpcm R/W Select Non-Linear (1b) / Linear (0b) PCM mode
Exists: Always
6 spdif_hbr_mode R/W When set to 1'b1, this bit field indicates that the input stream
has a High Bit Rate (HBR) to be transmitted in HDMI HBR
packets. When clear (1b'0), the audio is transmitted in HDMI
AUDS packets. Note: This bit overrides the setting defined in
bit setnlpcm and overrides the aud_spdif2.SPDIF_ch_en
using always ispdifdata[0]. This register field is functional
only when HBR_ON_SPDIF is selected. Otherwise, this field
Exists: HBR_ON_SPDIF==1
5 spare R/W Reserved as "spare" bit with no associated functionality.
Exists: Always
4:0 spdif_width R/W SPDIF input data width
SPDIF_width[4:0] | Action
00000b-01111b | Not used
10000b | 16-bit data samples at input
11001b-11111b | Not Used
Exists: Always

6.9.3 aud_spdifint
■ Description: Audio SPDIF FIFO Empty/Full Mask Register
■ Size: 8 bits
■ Offset: 0x3302
Table 6-291 Fields for Register: aud_spdifint
Memory
3 spdif_fifo_empty_mask R/W SPDIF FIFO empty mask
Exists: Always
2 spdif_fifo_full_mask R/W SPDIF FIFO full mask
Exists: Always

6.9.4 aud_spdifint1
■ Description: Audio SPDIF Mask Interrupt Register 1
This register masks interrupts present in the SPDIF module.
■ Size: 8 bits
■ Offset: 0x3303
Table 6-292 Fields for Register: aud_spdifint1
Memory
Exists: Always
6.9.5 aud_spdif2
■ Description: Audio SPDIF Enable Configuration Register 2
This register configures the SPDIF input enable that indicates which input SPDIF channels have valid
data.
■ Size: 8 bits
■ Offset: 0x3304
Memory
3:0 SPDIF_in_en R/W Action
SPDIF_in_en[0] - ispdifdata[0] enable
Exists: Always

6.10 AudioSampleGP Registers

Audio Sample GP Registers. Follow the link for the register to see a detailed description of the register.
Table 6-294 Registers for Address Block: AudioSampleGP

gp_conf0 on page 393 0x3500 Audio GPA Software FIFO Reset Control Register 0
gp_conf1 on page 393 0x3501 Audio GPA Channel Enable Configuration Register 1
gp_conf2 on page 394 0x3502 Audio GPA HBR Enable Register 2
gp_mask on page 395 0x3506 Audio GPA FIFO Full and Empty Mask Interrupt Register

6.10.1 gp_conf0
■ Description: Audio GPA Software FIFO Reset Control Register 0
■ Size: 8 bits
■ Offset: 0x3500
■ Exists: GPAUDPORTS==1
Table 6-295 Fields for Register: gp_conf0
Memory
■ Writing 0b: no action taken
■ Writing 1b: Resets all audio FIFOs
Note: If a FIFO reset request (via register write command) lands in
the middle of an GPAUD audio transaction, the samples become
misaligned (left-right sequence lost). As a solution, for each FIFO
reset, an associated SPDIF reset must be issued (writing 8'h7F to
MC_SWRSTZ register).
Exists: Always
6.10.2 gp_conf1
■ Description: Audio GPA Channel Enable Configuration Register 1
■ Size: 8 bits
■ Offset: 0x3501
Memory
7:0 ch_in_en R/W Each bit controls the enabling of the respective audio
channel. For instance, bit 1, when set (1'b1), the audio
Channel 1 is enabled. When cleared, the referred channel is
disabled.
Exists: Always

6.10.3 gp_conf2
■ Description: Audio GPA HBR Enable Register 2
■ Size: 8 bits
■ Offset: 0x3502
Memory
1 insert_pcuv R/W When set (1'b1), this bit enables the insertion of the PCUV (Parity,
Channel Status, User bit and Validity) bits on the incoming audio stream
(support limited to Linear PCM audio). If disabled, the incoming audio
stream must contain the PCUV bits, mapped according to 2.6.4.2 Data
Mapping Examples.
Exists: Always
0 HBR R/W HBR packets enable. The DWC_hdmi_tx sends the HBR packets. This bit
is enabled when the audio frequency is higher than 192 kHz. If this bit is
enabled, the number of channels configured in GP_CONF1 must be set to
8'hFF.
Exists: Always

6.10.4 gp_mask
■ Description: Audio GPA FIFO Full and Empty Mask Interrupt Register
■ Size: 8 bits
■ Offset: 0x3506
Table 6-298 Fields for Register: gp_mask
Memory
Exists: Always
1 fifo_empty_mask R/W FIFO empty flag mask
Exists: Always
0 fifo_full_mask R/W FIFO full flag mask
Exists: Always

6.11 AudioDMA Registers

Audio DMA Registers. Follow the link for the register to see a detailed description of the register.
Table 6-299 Registers for Address Block: AudioDMA

ahb_dma_conf0 on page 397 0x3600 Audio DMA SW FIFO reset and DMA Configuration Register
0 This register contains the software reset...
ahb_dma_start on page 399 0x3601 Audio DMA Start Register The start_dma_transaction bit
field signals the AHB audio DMA to start...
ahb_dma_stop on page 400 0x3602 Audio DMA Stop Register The stop_dma_transaction bit field
signals the AHB audio DMA to stop current...
ahb_dma_thrsld on page 401 0x3603 Audio DMA FIFO Threshold Register This register defines
the FIFO medium threshold occupation value....
ahb_dma_straddr_set0[0:3] on page 402 0x3604 + Audio DMA Start Address Set0 Register Array Address
(i * 0x1) offset: i = 0 to 3 These registers define...
ahb_dma_stpaddr_set0[0:3] on page 403 0x3608 + Audio DMA Stop Address Set0 Register Array Address
(i * 0x1) offset: i = 0 to 3 This registers define the...
ahb_dma_bstraddr[0:3] on page 404 0x360c + Audio DMA Burst Start Address Register Array Address
(i * 0x1) offset: i = 0 to 3 These read-only registers...
ahb_dma_mblength0 on page 404 0x3610 Audio DMA Burst Length Register 0 This registers holds the
length of the current burst operation....
ahb_dma_mblength1 on page 405 0x3611 Audio DMA Burst Length Register 1 This registers holds the
length of the current burst operation....
ahb_dma_mask on page 406 0x3614 Audio DMA Mask Interrupt Register This register masks
each of the interrupts present in the AHB...
ahb_dma_conf1 on page 407 0x3616 Audio DMA Channel Enable Configuration Register 1 In
AUDS packet configuration with layout 0 selected,...
ahb_dma_buffmask on page 407 0x3619 Audio DMA Buffer Mask Interrupt Register
ahb_dma_mask1 on page 408 0x361b Audio DMA Mask Interrupt Register 1 This register masks
interrupts present in the AHB audio DMA...
ahb_dma_status on page 408 0x361c Audio DMA Status
ahb_dma_conf2 on page 409 0x361d Audio DMA Configuration Register 2
ahb_dma_straddr_set1[0:3] on page 409 0x3620 + Audio DMA Start Address Set 1 Register Array Address
ahb_dma_stpaddr_set1[0:3] on page 410 0x3624 + Audio DMA Stop Address Set 1 Register Array Address

6.11.1 ahb_dma_conf0
■ Description: Audio DMA SW FIFO reset and DMA Configuration Register 0
This register contains the software reset bit for the audio FIFOs. It also configures operating modes of
the AHB master.
■ Size: 8 bits
■ Offset: 0x3600
Table 6-300 Fields for Register: ahb_dma_conf0
Memory
7 sw_fifo_rst R/W This is the software reset bit for the audio and FIFO clear.
■ Writing 0'b does not result in any action.
■ Writing 1'b to this register resets all audio FIFOs.
■ Reading from this register always returns 0'b.
Exists: Always
6 insert_pcuv R/W Enables the insertion of PCUV data
Exists: Always
4 hbr R/W HBR packet enable
The DWC_hdmi_tx sends the HBR packets. This bit must be
enabled when transmitting non-linear audio of frequency
higher than 192 kHz. If this bit is enabled, the number of
channels configured in AHB_DMA_CONF1 is always 8.
Exists: Always
3 enable_hlock R/W Enable request of locked burst AHB mechanism.
■ 1'b: Enables the usage of hlock for master request to
arbiter of a locked complete burst.
■ 0'b: Disables request of locked burst AHB mechanism
Exists: Always

Table 6-300 Fields for Register: ahb_dma_conf0 (Continued)
Memory
2:1 incr_type R/W Selects the preferred burst length size
■ 00'b: Corresponds to INCR4 fixed four beat, incremental
AHB burst mode. Only valid when burst_mode is high.
■ 01'b: Corresponds to INCR8 fixed eight beat incremental
■ 10'b: Corresponds to INCR16 fixed 16 beat incremental
■ 11'b: Corresponds to INCR16 fixed 16 beat incremental
Exists: Always
0 burst_mode R/W ■ 1'b: Forces the burst mode to be fixed beat, incremental
burst mode designated by the incr_type[1:0] signal.
■ 0'b: Normal operation is unspecified length, incremental
burst. It corresponds to INCR AHB burst mode.
Exists: Always

6.11.2 ahb_dma_start
■ Description: Audio DMA Start Register
The start_dma_transaction bit field signals the AHB audio DMA to start accessing system memory in
order to fetch data samples to store in the FIFO. After the operation starts, a new request for a DMA
start is ignored until the DMA is stopped or it reaches the end address. Only in one of these situations
is a new start request acknowledged.
The first DMA burst request after start_dma_transaction configuration uses initial_addr[31:0] as
ohaddr[31:0] value; mburstlength[8:0] is set to the maximum admissible value. This maximum value
is constrained by the size of buffer provided, the instantiated FIFO depth, or/and the number of
words up to the next 1 Kbyte boundary.
■ Size: 8 bits
■ Offset: 0x3601
Table 6-301 Fields for Register: ahb_dma_start
Memory
0 start_dma_transaction R/W Start DMA transaction
This register is auto-cleared when the transfer operation is
completed (done).
Exists: Always

6.11.3 ahb_dma_stop
■ Description: Audio DMA Stop Register
The stop_dma_transaction bit field signals the AHB audio DMA to stop current memory access. After
it stops, if a new start DMA operation is requested, the DMA engine restarts the memory access using
the initial_addr[31:0], which is programmed at ahb_dma_straddr0 to ahb_dma_straddr3.
■ Size: 8 bits
■ Offset: 0x3602
Table 6-302 Fields for Register: ahb_dma_stop
Memory
0 stop_dma_transaction R/W Stop DMA transaction
This register is auto-cleared when the transfer operation is
stopped (done).
Exists: Always

6.11.4 ahb_dma_thrsld
■ Description: Audio DMA FIFO Threshold Register
This register defines the FIFO medium threshold occupation value.
After the AHB master completes a burst transaction successfully, the FIFO may remain full till the
data fetch interface requests samples. Each data fetch operation reduces the number of samples
stored in the FIFO by the number of channels enabled.
Therefore, the fifo_threshold[7:0] is the medium number of samples that should be available in the
audio FIFO across the DMA operation.
As soon as the number of samples in the FIFO drops lower than the fifo_threshold[7:0], the DMA
engine requests a new burst of samples for the AHB master. The length is constrained by the size of
buffer provided, the instantiated FIFO depth minus fifo_threshold[7:0], and/or the number of words
up to the next 1 kbyte boundary.
■ Size: 8 bits
■ Offset: 0x3603
Table 6-303 Fields for Register: ahb_dma_thrsld
Memory
7:0 fifo_threshold R/W FIFO medium threshold occupation value
Exists: Always

6.11.5 ahb_dma_straddr_set0[0:3]
■ Description: Audio DMA Start Address Set0 Register Array
Address offset: i = 0 to 3
These registers define the initial_addr[31:0] used to initiate the DMA burst read transactions upon
start_dma_transaction configuration.
For more information on the configuration of address registers, refer to "Rules for Configuration of
Address Registers" in the databook.
■ Size: 8 bits
■ Offset: 0x3604 + (i * 0x1)
■ Exists: Always
Table 6-304 Fields for Register: ahb_dma_straddr_set0[0:3]
Memory
7:0 initial_addr R/W Defines init_addr[7:0] to initiate DMA burst transactions
Exists: Always

6.11.6 ahb_dma_stpaddr_set0[0:3]
■ Description: Audio DMA Stop Address Set0 Register Array
This registers define the final_addr[31:0] used as the final point to the DMA burst read transactions.
Upon start_dma_transaction configuration, the DMA engine starts requesting burst reads from the
external system memory. Each burst read can have a maximum theoretical length of 256 words (due
to the AMBA AHB specification 1 Kbyte boundary burst limitation).
The DMA engine is responsible for incrementing the burst starting address and defining its
corresponding burst length to reach the final_addr[31:0] address. The last burst request issued by the
DMA engine takes into account that it should only request data until the final_addr[31:0] address
(included) and for that should calculate the correct burst length.
After reaching the final_addr[31:0] address, the done interrupt is active to signal completion of DMA
operation.
■ Size: 8 bits
■ Offset: 0x3608 + (i * 0x1)
■ Exists: Always
Table 6-305 Fields for Register: ahb_dma_stpaddr_set0[0:3]
Memory
7:0 final_addr R/W Defines final_addr[7:0] to end DMA burst transactions
Exists: Always

6.11.7 ahb_dma_bstraddr[0:3]
■ Description: Audio DMA Burst Start Address Register Array
These read-only registers compose the start address of the current burst operation.
burst_start_addr[31:0] = haddr[31:0] = initial_addr[31:0] + 16.
■ Size: 8 bits
■ Offset: 0x360c + (i * 0x1)
■ Exists: Always
Table 6-306 Fields for Register: ahb_dma_bstraddr[0:3]
Memory
7:0 burst_addr R Start address for the current burst operation
Exists: Always
6.11.8 ahb_dma_mblength0
■ Description: Audio DMA Burst Length Register 0
This registers holds the length of the current burst operation. As an example, if the first burst
transaction of the AHB audio DMA is a length of 8, then the second burst should start at address
ohaddr[31:0] = initial_addr[31:0] + 32.
■ Size: 8 bits
■ Offset: 0x3610
Table 6-307 Fields for Register: ahb_dma_mblength0
Memory
7:0 mburstlength R Requested burst length (mburstlength[7:0])
Exists: Always

6.11.9 ahb_dma_mblength1
■ Description: Audio DMA Burst Length Register 1
This registers holds the length of the current burst operation. As an example, if the first burst
transaction of the AHB audio DMA is a length of 8, then the second burst should start at address
ohaddr[31:0] = initial_addr[31:0] + 32.
■ Size: 8 bits
■ Offset: 0x3611
Table 6-308 Fields for Register: ahb_dma_mblength1
Memory
0 mburstlength R Requested burst length
Exists: Always

6.11.10 ahb_dma_mask
■ Description: Audio DMA Mask Interrupt Register
This register masks each of the interrupts present in the AHB audio DMA module.
■ Size: 8 bits
■ Offset: 0x3614
Table 6-309 Fields for Register: ahb_dma_mask
Memory
7 done_mask R/W DMA end of operation interrupt mask. Active when DMA
engine reaches final_addr[15:0] or when stop DMA operation
is activated.
Exists: Always
6 retrysplit_mask R/W Retry/split interrupt mask. Active when AHB master receives
a RETRY or SPLIT response from slave.
Exists: Always
5 lostownership_mask R/W Master lost ownership interrupt mask when in burst transfer.
Active when AHB master loses BUS ownership within the
course of a burst transfer.
Exists: Always
4 error_mask R/W Error interrupt mask. Active when slave indicates error
through the isresp[1:0].
Exists: Always
2 fifo_thrempty_mask R/W Audio FIFO empty interrupt mask when audio FIFO has less
than the number of enabled audio channels.
Exists: Always
1 fifo_full_mask R/W Audio FIFO full interrupt mask.
Exists: Always
0 fifo_empty_mask R/W Audio FIFO empty interrupt mask.
Exists: Always

■ Description: Audio DMA Channel Enable Configuration Register 1
In AUDS packet configuration with layout 0 selected, the maximum number of active channels is 2.
■ Size: 8 bits
■ Offset: 0x3616
Memory
7:0 ch_in_en R/W Each bit controls the enabling of the respective audio
channel. For instance, when bit 1 is set (1'b1) the audio
Channel 1 is enabled. When cleared, the referred channel is
disabled.
Exists: Always
6.11.12 ahb_dma_buffmask
■ Description: Audio DMA Buffer Mask Interrupt Register
■ Size: 8 bits
■ Offset: 0x3619
Table 6-311 Fields for Register: ahb_dma_buffmask
Memory
4 mask_fifo_overrun R/W Buffer overrun flag mask
Exists: Always
1 mask_buff_full R/W Buffer full flag mask
Exists: Always
0 mask_buff_empty R/W Buffer empty flag mask
Exists: Always

6.11.13 ahb_dma_mask1
■ Description: Audio DMA Mask Interrupt Register 1
This register masks interrupts present in the AHB audio DMA module.
■ Size: 8 bits
■ Offset: 0x361b
Table 6-312 Fields for Register: ahb_dma_mask1
Memory
1 fifo_underrun_mask R/W AHB DMA FIFO underrun mask
Exists: Always
0 fifo_overrun_mask R/W AHB DMA FIFO overrun mask
Exists: Always
6.11.14 ahb_dma_status
■ Description: Audio DMA Status
■ Size: 8 bits
■ Offset: 0x361c
Table 6-313 Fields for Register: ahb_dma_status
Memory
0 autostart_status R Indicates the set of start and stop addresses currently used
by the AHB audio DMA.
If cleared (1'b0), the start and stop addresses configured in
the address range 0x3604 to 0x360B are being used. When
set (1'b1), the configurations at address range 0x3620 to
0x3627 are being used.
This bit is always at zero when autostart_enable is cleared
(1'b0).
Exists: Always

■ Description: Audio DMA Configuration Register 2
■ Size: 8 bits
■ Offset: 0x361d
Memory
1 autostart_loop R/W Enables the AHB audio DMA auto-start loop mode
Exists: Always
0 autostart_enable R/W Enables the AHB audio DMA auto-start feature
Exists: Always
6.11.16 ahb_dma_straddr_set1[0:3]
■ Description: Audio DMA Start Address Set 1 Register Array
These registers define the initial_addr_1[31:0] used to initiate the DMA burst read transactions upon
start_dma_transaction configuration.
■ Size: 8 bits
■ Offset: 0x3620 + (i * 0x1)
■ Exists: Always
Table 6-315 Fields for Register: ahb_dma_straddr_set1[0:3]
Memory
7:0 initial_addr_1 R/W Defines init_addr_1[7:0] to initiate DMA burst transactions
Exists: Always

6.11.17 ahb_dma_stpaddr_set1[0:3]
■ Description: Audio DMA Stop Address Set 1 Register Array
These registers define the final_addr_1[31:0] used as the final point to the DMA burst read
transactions. Upon start_dma_transaction configuration, the DMA engine starts requesting burst
reads from the external system memory. Each burst read can have a maximum theoretical length of
256 words (due to the AMBA AHB specification 1 Kbyte boundary burst limitation).
The DMA engine is responsible for incrementing the burst starting address and defining its
corresponding burst length to reach the final_addr[31:0] address. The last burst request issued by the
DMA engine takes into account that it should only request data until the final_addr[31:0] address
(included) and for that should calculate the correct burst length.
After reaching the final_addr_1[31:0] address, the done interrupt is active to indicate completion of
the DMA operation.
■ Size: 8 bits
■ Offset: 0x3624 + (i * 0x1)
■ Exists: Always
Table 6-316 Fields for Register: ahb_dma_stpaddr_set1[0:3]
Memory
7:0 final_addr_1 R/W Defines final_addr_1[7:0] to end DMA burst transactions
Exists: Always

6.12 MainController Registers

Main Controller Registers. Follow the link for the register to see a detailed description of the register.
Table 6-317 Registers for Address Block: MainController

mc_clkdis on page 412 0x4001 Main Controller Synchronous Clock Domain Disable
Register
mc_swrstzreq on page 413 0x4002 Main Controller Software Reset Register Main controller
software reset request per clock domain....
mc_opctrl on page 414 0x4003 Main Controller HDCP Bypass Control Register
mc_flowctrl on page 415 0x4004 Main Controller Feed Through Control Register
mc_phyrstz on page 415 0x4005 Main Controller PHY Reset Register
mc_lockonclock on page 416 0x4006 Main Controller Clock Present Register
mc_heacphy_rst on page 417 0x4007 Main Controller HEAC PHY Reset Register
mc_lockonclock_2 on page 417 0x4009 Main Controller Clock Present Register 2
mc_swrstzreq_2 on page 418 0x400a Main Controller Software Reset Register 2 Main controller
software reset request per clock domain....

6.12.1 mc_clkdis
■ Description: Main Controller Synchronous Clock Domain Disable Register
■ Size: 8 bits
■ Offset: 0x4001
■ Exists: Always
Table 6-318 Fields for Register: mc_clkdis
Memory
6 hdcpclk_disable R/W HDCP clock synchronous disable signal. When active (1b),
simultaneously bypasses HDCP.
Exists: HDCP==1
5 cecclk_disable R/W CEC Engine clock synchronous disable signal.
Exists: Always
4 cscclk_disable R/W Color Space Converter clock synchronous disable signal.
Exists: Always
3 audclk_disable R/W Audio Sampler clock synchronous disable signal.
Exists: Always
2 prepclk_disable R/W Pixel Repetition clock synchronous disable signal.
Exists: Always
1 tmdsclk_disable R/W TMDS clock synchronous disable signal.
It is required to perform a write action on one of the following
registers:
■ fc_invidconf, fc_inhactiv0, fc_inhactiv1, fc_inhblank0,
fc_inhblank1, fc_invactiv0
■ fc_invactiv1, fc_invblank, fc_hsyncindelay0,
fc_hsyncindelay1, fc_hsyncinwidth0
■ fc_hsyncinwidth1, fc_vsyncindelay, fc_vsyncinwidth,
fc_ctrldur, fc_exctrldur, fc_exctrlspac
Exists: Always
0 pixelclk_disable R/W Pixel clock synchronous disable signal.
Exists: Always

6.12.2 mc_swrstzreq
■ Description: Main Controller Software Reset Register
Main controller software reset request per clock domain. Writing zero to a bit of this register results
in an NRZ signal toggle at sfrclk rate to an output signal that indicates a software reset request. This
toggle must be used to generate a synchronized reset to de corresponding domain, with at least 1
clock cycle.
■ Size: 8 bits
■ Offset: 0x4002
■ Exists: Always
Table 6-319 Fields for Register: mc_swrstzreq
Memory
7 igpaswrst_req R/W GPAUD interface soft reset request. This bit is enabled when the
Generic Parallel Audio (GPAUD) interface is enabled (AUDIO_IF = 6).
Otherwise, this bit returns zero.
Exists: Always
6 cecswrst_req R/W CEC software reset request. Defaults back to 1b after reset request.
Note: After you configure cecswrst_req, set the value of the bit
csc_clk_disable of the register mc_clkdis to 1, 0, and then 1 again.
Exists: Always
4 ispdifswrst_req R/W SPDIF audio software reset request.
Exists: Always
3 ii2sswrst_req R/W I2S audio software reset request.
Exists: Always
2 prepswrst_req R/W Pixel Repetition software reset request.
Exists: Always

Table 6-319 Fields for Register: mc_swrstzreq (Continued)
Memory
1 tmdsswrst_req R/W TMDS software reset request.
It is required to perform a write action on one of the following registers:
■ fc_invidconf, fc_inhactiv0, fc_inhactiv1, fc_inhblank0, fc_inhblank1,
fc_invactiv0
■ fc_invactiv1, fc_invblank, fc_hsyncindelay0, fc_hsyncindelay1,
fc_hsyncinwidth0
■ fc_hsyncinwidth1, fc_vsyncindelay, fc_vsyncinwidth, fc_ctrldur,
fc_exctrldur, fc_exctrlspac
Exists: Always
0 pixelswrst_req R/W Pixel software reset request.
Exists: Always
6.12.3 mc_opctrl
■ Description: Main Controller HDCP Bypass Control Register
■ Size: 8 bits
■ Offset: 0x4003
■ Exists: Always
Table 6-320 Fields for Register: mc_opctrl
Memory
0 hdcp_block_byp R/W Block HDCP bypass mechanism
■ 1'b0: This is the default value. You can write to the
hdcp_clkdisable bit of the register mc_clkdis and bypass HDCP
by acting on the register mc_clkdis bit 6 (hdcp_clkdisable)
■ 1'b1: You can still write to the hdcp_clkdisable bit of the register
mc_clkdis but this action disables the HDCP module and blocks
the bypass mechanism. The output data is frozen and the HDMI
TX and RX fail authentication.
Once you set the value to 1'b1, you can change the value back to
1'b0 only by issuing a master reset to the DWC_hdmi_tx. Otherwise,
this field is a "spare" bit with no associated functionality.
Exists: HDCP==1

6.12.4 mc_flowctrl
■ Description: Main Controller Feed Through Control Register
■ Size: 8 bits
■ Offset: 0x4004
■ Exists: Always
Table 6-321 Fields for Register: mc_flowctrl
Memory
0 Feed_through_off R/W Video path Feed Through enable bit:
■ 1b: Color Space Converter is in the video data path.
■ 0b: Color Space Converter is bypassed (not in the video
data path).
Exists: Always
6.12.5 mc_phyrstz
■ Description: Main Controller PHY Reset Register
■ Size: 8 bits
■ Offset: 0x4005
■ Exists: Always
Table 6-322 Fields for Register: mc_phyrstz
Memory
0 phyrstz R/W HDMI Source PHY active low reset control for PHY GEN1,
active high reset control for PHY GEN2.
Value After Reset: "(PHY_GEN2== 1) ? 1 : 0"
Exists: Always

6.12.6 mc_lockonclock
■ Description: Main Controller Clock Present Register
■ Size: 8 bits
■ Offset: 0x4006
■ Exists: Always
Table 6-323 Fields for Register: mc_lockonclock
Memory
7 igpaclk R/W1C GPAUD interface clock status. This bit is enabled when the
Generic Parallel Audio (GPAUD) interface is enabled
(AUDIO_IF = 6). Otherwise, this bit returns zero.
This bit indicates the clock is present in the system. It is
cleared by writing 1 to this bit.
Exists: Always
6 pclk R/W1C Pixel clock status. Indicates that the clock is present in the
system. Cleared by WR 1 to this position.
Exists: Always
5 tclk R/W1C TMDS clock status. Indicates that the clock is present in the
Exists: Always
4 prepclk R/W1C Pixel Repetition clock status. Indicates that the clock is
present in the system. Cleared by WR 1 to this position.
Exists: Always
3 i2sclk R/W1C I2S clock status. Indicates that the clock is present in the
Exists: Always
2 audiospdifclk R/W1C SPDIF clock status. Indicates that the clock is present in the
Exists: Always
0 cecclk R/W1C CEC clock status. Indicates that the clock is present in the
Exists: Always

6.12.7 mc_heacphy_rst
■ Description: Main Controller HEAC PHY Reset Register
■ Size: 8 bits
■ Offset: 0x4007
■ Exists: HDMI_HEAC_PHY_EN==1
Table 6-324 Fields for Register: mc_heacphy_rst
Memory
0 heacphyrst R/W HEAC PHY reset (active high)
Exists: Always
6.12.8 mc_lockonclock_2
■ Description: Main Controller Clock Present Register 2
■ Size: 8 bits
■ Offset: 0x4009
Table 6-325 Fields for Register: mc_lockonclock_2
Memory
0 ahbdmaclk R/W1C AHB audio DMA clock status. Indicates that the clock is
present in the system. Cleared by WR 1 to this position.
Exists: Always

6.12.9 mc_swrstzreq_2
■ Description: Main Controller Software Reset Register 2
Main controller software reset request per clock domain. Writing zero to a bit of this register results
in a signal toggle that indicates a software reset request. This toggle is used to generate a
synchronized reset to the corresponding domain, with one or more clock cycles.
■ Size: 8 bits
■ Offset: 0x400a
Table 6-326 Fields for Register: mc_swrstzreq_2
Memory
0 ahbdmaswrst_req R/W AHB audio DMA software reset request.
■ Writing 1'b1 does not result in any action.
■ Writing 1'b0 to this register resets all AHB audio logic.
Exists: Always

6.13 ColorSpaceConverter Registers

Color Space Converter Registers. Follow the link for the register to see a detailed description of the register.
Table 6-327 Registers for Address Block: ColorSpaceConverter

csc_cfg on page 421 0x4100 Color Space Converter Interpolation and Decimation
csc_scale on page 422 0x4101 Color Space Converter Scale and Deep Color Configuration
Register
csc_coef_a1_msb on page 423 0x4102 Color Space Converter Matrix A1 Coefficient Register MSB
Notes: - The coefficients used in the...
csc_coef_a1_lsb on page 424 0x4103 Color Space Converter Matrix A1 Coefficient Register LSB
Notes: - The coefficients used in the...
Color Space Conversion A2...
csc_coef_b1_msb on page 428 0x410a Color Space Converter Matrix B1 Coefficient Register MSB
Color Space Conversion B1...
csc_coef_b1_lsb on page 428 0x410b Color Space Converter Matrix B1 Coefficient Register LSB
csc_coef_b2_msb on page 429 0x410c Color Space Converter Matrix B2 Coefficient Register MSB
csc_coef_b2_lsb on page 429 0x410d Color Space Converter Matrix B2 Coefficient Register LSB
csc_coef_b3_msb on page 430 0x410e Color Space Converter Matrix B3 Coefficient Register MSB
csc_coef_b3_lsb on page 430 0x410f Color Space Converter Matrix B3 Coefficient Register LSB
csc_coef_b4_msb on page 431 0x4110 Color Space Converter Matrix B4 Coefficient Register MSB

Table 6-327 Registers for Address Block: ColorSpaceConverter (Continued)

csc_coef_b4_lsb on page 431 0x4111 Color Space Converter Matrix B4 Coefficient Register LSB
csc_coef_c1_msb on page 432 0x4112 Color Space Converter Matrix C1 Coefficient Register MSB
Color Space Conversion C1...
csc_coef_c1_lsb on page 432 0x4113 Color Space Converter Matrix C1 Coefficient Register LSB
csc_limit_up_msb on page 436 0x411a Color Space Converter Matrix Output Up Limit Register MSB
For more details, refer to the HDMI 1.4...
csc_limit_up_lsb on page 436 0x411b Color Space Converter Matrix output Up Limit Register LSB
For more details, refer to the HDMI 1.4...
csc_limit_dn_msb on page 437 0x411c Color Space Converter Matrix output Down Limit Register
MSB For more details, refer to the HDMI...
csc_limit_dn_lsb on page 437 0x411d Color Space Converter Matrix output Down Limit Register
LSB For more details, refer to the HDMI...

6.13.1 csc_cfg
■ Description: Color Space Converter Interpolation and Decimation Configuration Register
■ Size: 8 bits
■ Offset: 0x4100
■ Exists: CSC==1
Table 6-328 Fields for Register: csc_cfg
Memory
7 csc_limit R/W When set (1'b1), the range limitation values defined in
registers csc_mat_uplim and csc_mat_dnlim are applied to
the output of the Color Space Conversion matrix. This
feature ensures that the video output range is always
respected, independently of the matrix coefficient
configuration or of the video input stream.
Exists: Always
6 spare_2 R/W Reserved as "spare" register with no associated functionality.
Exists: Always
5:4 intmode R/W Chroma interpolation configuration:
intmode[1:0] | Chroma Interpolation
00 | interpolation disabled
01 | Hu (z) =1 + z^(-1)
10 | Hu(z)=1/ 2 + z^(-11)+1/2 z^(-2)
11 | interpolation disabled
Exists: Always
3:2 spare_1 R/W Reserved as "spare" register with no associated functionality.
Exists: Always
1:0 decmode R/W Chroma decimation configuration:
decmode[1:0] | Chroma Decimation
00 | decimation disabled
01 | Hd (z) =1
10 | Hd(z)=1/ 4 + 1/2z^(-1 )+1/4 z^(-2)
11 | Hd(z)x2^(11)= -5+12z^(-2) - 22z^(-4)+39z^(-8)
+109z^(-10) -204z^(-12)+648z^(-14) + 1024z^(-15) +648z^(-
16) -204z^(-18) +109z^(-20)- 65z^(-22) +39z^(-24) -22z^(-
26) +12z^(-28)-5z^(-30)
Exists: Always

6.13.2 csc_scale
■ Description: Color Space Converter Scale and Deep Color Configuration Register
■ Size: 8 bits
■ Offset: 0x4101
■ Exists: CSC==1
Table 6-329 Fields for Register: csc_scale
Memory
7:4 csc_color_depth R/W Color space converter color depth configuration:
csc_colordepth[3:0] | Action
0000 | 24 bit per pixel video (8 bit per component).
0001-0011 | Reserved. Not used.
other | Reserved. Not used.
Exists: Always
3:2 spare R/W The is a Reserved as "spare" register with no associated
functionality.
Exists: Always
1:0 cscscale R/W Defines the cscscale[1:0] scale factor to apply to all
coefficients in Color Space Conversion. This scale factor is
expressed in the number of left shifts to apply to each of the
coefficients, ranging from 0 to 2.
Exists: Always

6.13.3 csc_coef_a1_msb
■ Description: Color Space Converter Matrix A1 Coefficient Register MSB
Notes:
❑ The coefficients used in the CSC matrix use only 15 bits for the internal computations.
❑ Coefficients are represented in 2's complementary format and stored in two registers:
❑ csc_coef_*_lsb[7:0]: coefficient bits 7 to 0
❑ csc_coef_*_msb[7]: spare bit
❑ csc_coef_*_msb[6:0]: coefficient bits 14 to 8
❑ Examples for standard ITU601 and ITU709 RGB/YCC conversion CSC coefficients exist in the
Video Datapath Application Note (available from the Synopsys web site).
■ Size: 8 bits
■ Offset: 0x4102
■ Exists: CSC==1
Table 6-330 Fields for Register: csc_coef_a1_msb
Memory
7:0 csc_coef_a1_msb R/W Color Space Converter Matrix A1 Coefficient Register MSB
Exists: Always

6.13.4 csc_coef_a1_lsb
■ Description: Color Space Converter Matrix A1 Coefficient Register LSB
Notes:
❑ The coefficients used in the CSC matrix use only 15 bits for the internal computations.
❑ Coefficients are represented in 2's complementary format and stored in two registers:
❑ - csc_coef_*_lsb[7:0]: coefficient bits 7 to 0
❑ - csc_coef_*_msb[7]: spare bit
❑ - csc_coef_*_msb[6:0]: coefficient bits 14 to 8
❑ Examples for standard ITU601 and ITU709 RGB/YCC conversion CSC coefficients exist in the
Video Datapath Application Note (available from the Synopsys web site).
■ Size: 8 bits
■ Offset: 0x4103
■ Exists: CSC==1
Table 6-331 Fields for Register: csc_coef_a1_lsb
Memory
7:0 csc_coef_a1_lsb R/W Color Space Converter Matrix A1 Coefficient Register LSB
Exists: Always

Color Space Conversion A2 coefficient.
■ Size: 8 bits
■ Offset: 0x4104
■ Exists: CSC==1
Memory
Exists: Always
■ Size: 8 bits
■ Offset: 0x4105
■ Exists: CSC==1
Memory
Exists: Always

■ Size: 8 bits
■ Offset: 0x4106
■ Exists: CSC==1
Memory
Exists: Always
■ Size: 8 bits
■ Offset: 0x4107
■ Exists: CSC==1
Memory
Exists: Always

■ Size: 8 bits
■ Offset: 0x4108
■ Exists: CSC==1
Memory
Exists: Always
■ Size: 8 bits
■ Offset: 0x4109
■ Exists: CSC==1
Memory
Exists: Always

6.13.11 csc_coef_b1_msb
■ Description: Color Space Converter Matrix B1 Coefficient Register MSB
Color Space Conversion B1 coefficient.
■ Size: 8 bits
■ Offset: 0x410a
■ Exists: CSC==1
Table 6-338 Fields for Register: csc_coef_b1_msb
Memory
7:0 csc_coef_b1_msb R/W Color Space Converter Matrix B1 Coefficient Register MSB
Exists: Always
6.13.12 csc_coef_b1_lsb
■ Description: Color Space Converter Matrix B1 Coefficient Register LSB
■ Size: 8 bits
■ Offset: 0x410b
■ Exists: CSC==1
Table 6-339 Fields for Register: csc_coef_b1_lsb
Memory
7:0 csc_coef_b1_lsb R/W Color Space Converter Matrix B1 Coefficient Register LSB
Exists: Always

■ Size: 8 bits
■ Offset: 0x410c
■ Exists: CSC==1
Memory
Exists: Always
■ Size: 8 bits
■ Offset: 0x410d
■ Exists: CSC==1
Memory
Exists: Always

■ Size: 8 bits
■ Offset: 0x410e
■ Exists: CSC==1
Memory
Exists: Always
■ Size: 8 bits
■ Offset: 0x410f
■ Exists: CSC==1
Memory
Exists: Always

■ Size: 8 bits
■ Offset: 0x4110
■ Exists: CSC==1
Memory
Exists: Always
■ Size: 8 bits
■ Offset: 0x4111
■ Exists: CSC==1
Memory
Exists: Always

6.13.19 csc_coef_c1_msb
■ Description: Color Space Converter Matrix C1 Coefficient Register MSB
Color Space Conversion C1 coefficient.
■ Size: 8 bits
■ Offset: 0x4112
■ Exists: CSC==1
Table 6-346 Fields for Register: csc_coef_c1_msb
Memory
7:0 csc_coef_c1_msb R/W Color Space Converter Matrix C1 Coefficient Register MSB
Exists: Always
6.13.20 csc_coef_c1_lsb
■ Description: Color Space Converter Matrix C1 Coefficient Register LSB
■ Size: 8 bits
■ Offset: 0x4113
■ Exists: CSC==1
Table 6-347 Fields for Register: csc_coef_c1_lsb
Memory
7:0 csc_coef_c1_lsb R/W Color Space Converter Matrix C1 Coefficient Register LSB
Exists: Always

■ Size: 8 bits
■ Offset: 0x4114
■ Exists: CSC==1
Memory
Exists: Always
■ Size: 8 bits
■ Offset: 0x4115
■ Exists: CSC==1
Memory
Exists: Always

■ Size: 8 bits
■ Offset: 0x4116
■ Exists: CSC==1
Memory
Exists: Always
■ Size: 8 bits
■ Offset: 0x4117
■ Exists: CSC==1
Memory
Exists: Always

■ Size: 8 bits
■ Offset: 0x4118
■ Exists: CSC==1
Memory
Exists: Always
■ Size: 8 bits
■ Offset: 0x4119
■ Exists: CSC==1
Memory
Exists: Always

6.13.27 csc_limit_up_msb
■ Description: Color Space Converter Matrix Output Up Limit Register MSB
For more details, refer to the HDMI 1.4 specification, paragraph 6.6 Video Quantization Ranges. For
an RGB output of 8 bits, the expected limit is 254 (valid range column of Table 6-3), and this register
must be configured with 0x00.
■ Size: 8 bits
■ Offset: 0x411a
■ Exists: CSC==1
Table 6-354 Fields for Register: csc_limit_up_msb
Memory
7:0 csc_limit_up_msb R/W Color Space Converter Matrix Output Upper Limit Register
MSB
Value After Reset: 0xff
Exists: Always
6.13.28 csc_limit_up_lsb
■ Description: Color Space Converter Matrix output Up Limit Register LSB
must be configured with 0xFE.
■ Size: 8 bits
■ Offset: 0x411b
■ Exists: CSC==1
Table 6-355 Fields for Register: csc_limit_up_lsb
Memory
7:0 csc_limit_up_lsb R/W Color Space Converter Matrix Output Upper Limit Register
LSB
Exists: Always

6.13.29 csc_limit_dn_msb
■ Description: Color Space Converter Matrix output Down Limit Register MSB
■ Size: 8 bits
■ Offset: 0x411c
■ Exists: CSC==1
Table 6-356 Fields for Register: csc_limit_dn_msb
Memory
7:0 csc_limit_dn_msb R/W Color Space Converter Matrix output Down Limit Register
MSB
Exists: Always
6.13.30 csc_limit_dn_lsb
■ Description: Color Space Converter Matrix output Down Limit Register LSB
■ Size: 8 bits
■ Offset: 0x411d
■ Exists: CSC==1
Table 6-357 Fields for Register: csc_limit_dn_lsb
Memory
7:0 csc_limit_dn_lsb R/W Color Space Converter Matrix Output Down Limit Register
LSB
Exists: Always

6.14 HDCP Registers

HDCP Registers. Follow the link for the register to see a detailed description of the register.
Table 6-358 Registers for Address Block: HDCP

a_hdcpcfg0 on page 440 0x5000 HDCP Enable and Functional Control Configuration Register 0
a_hdcpcfg1 on page 441 0x5001 HDCP Software Reset and Functional Control Configuration
Register 1
a_hdcpobs0 on page 442 0x5002 HDCP Observation Register 0
a_apiintclr on page 445 0x5006 HDCP Interrupt Clear Register Write only register, active high and
auto cleared, cleans the respective...
a_apiintstat on page 446 0x5007 HDCP Interrupt Status Register Read only register, reports the
interruption which caused the activation...
a_apiintmsk on page 447 0x5008 HDCP Interrupt Mask Register The configuration of this register
mask a given setup of interruption,...
a_vidpolcfg on page 448 0x5009 HDCP Video Polarity Configuration Register
a_oesswcfg on page 449 0x500a HDCP OESS WOO Configuration Register Pulse width of the
encryption enable (CTL3) signal in the...
a_coreverlsb on page 449 0x5014 HDCP Controller Version Register LSB Design ID number.
a_corevermsb on page 450 0x5015 HDCP Controller Version Register MSB Revision ID number.
a_ksvmemctrl on page 451 0x5016 HDCP KSV Memory Control Register The KSVCTRLupd bit is a
notification flag. This flag changes polarity...
hdcp_bstatus[0:1] on page 452 0x5020 + HDCP BStatus Register Array
(i * 0x1)
hdcp_m0[0:7] on page 452 0x5022 + HDCP M0 Register Array
(i * 0x1)
hdcp_ksv[0:634] on page 453 0x502a + HDCP KSV Registers
(i * 0x1)
hdcp_vh[0:19] on page 454 0x52a5 + HDCP SHA-1 VH Registers
(i * 0x1)
hdcp_revoc_size_0 on page 454 0x52b9 HDCP Revocation KSV List Size Register 0
hdcp_revoc_size_1 on page 455 0x52ba HDCP Revocation KSV List Size Register 1
hdcp_revoc_list[0:5059] on page 455 0x52bb + HDCP Revocation KSV Registers
(i * 0x1)
hdcpreg_bksv0 on page 456 0x7800 HDCP KSV Status Register 0

Table 6-358 Registers for Address Block: HDCP (Continued)

hdcpreg_anconf on page 458 0x7805 HDCP AN Bypass Control Register
hdcpreg_an0 on page 459 0x7806 HDCP Forced AN Register 0
hdcpreg_an2 on page 460 0x7808 HDCP forced AN Register 2
hdcpreg_an4 on page 461 0x780a HDCP Forced AN Register 4
hdcpreg_an5 on page 461 0x780b HDCP Forced AN Register 5
hdcpreg_an6 on page 462 0x780c HDCP Forced AN Register 6
hdcpreg_an7 on page 462 0x780d HDCP Forced AN Register 7
hdcpreg_rmlctl on page 463 0x780e HDCP Encrypted Device Private Keys Control Register This
register is the control register for the...
hdcpreg_rmlsts on page 463 0x780f HDCP Encrypted DPK Status Register The required software
configuration sequence is documented in...
hdcpreg_seed0 on page 464 0x7810 HDCP Encrypted DPK Seed Register 0 This register contains a
byte of the HDCP Encrypted DPK seed...
hdcpreg_seed1 on page 464 0x7811 HDCP Encrypted DPK Seed Register 1 This register contains a
byte of the HDCP Encrypted DPK seed...
hdcpreg_dpk0 on page 465 0x7812 HDCP Encrypted DPK Data Register 0 This register contains an
HDCP DPK byte. The required software...

6.14.1 a_hdcpcfg0
■ Description: HDCP Enable and Functional Control Configuration Register 0
■ Size: 8 bits
■ Offset: 0x5000
■ Exists: HDCP==1
Table 6-359 Fields for Register: a_hdcpcfg0
Memory
7 ELVena R/W Enables the Enhanced Link Verification from the transmitter's
side
Exists: Always
6 I2Cfastmode R/W Enable the I2C fast mode option from the transmitter's side.
Exists: Always
5 bypencryption R/W Bypasses all the data encryption stages
Value After Reset: "(DWC_HDMI_HDCP_BYPASS== 1) ? 1
: 0"
Exists: Always
4 syncricheck R/W Configures if the Ri check should be done at every 2s even
or synchronously to every 128 encrypted frame.
Exists: Always
3 avmute R This register holds the current AVMUTE state of the
DWC_hdmi_tx controller, as expected to be perceived by the
connected HDMI/HDCP sink device.
Exists: Always
2 rxdetect R/W Information that a sink device was detected connected to the
HDMI port
Exists: Always
1 en11feature R/W Enable the use of features 1.1 from the transmitter's side
Exists: Always
0 hdmidvi R/W Configures the transmitter to operate with a HDMI capable
device or with a DVI device.
Exists: Always

6.14.2 a_hdcpcfg1
■ Description: HDCP Software Reset and Functional Control Configuration Register 1
■ Size: 8 bits
■ Offset: 0x5001
■ Exists: HDCP==1
Table 6-360 Fields for Register: a_hdcpcfg1
Memory
7:5 spare R/W Reserved as "spare" register with no associated functionality.
Exists: Always
4 hdcp_lock R/W Lock the HDCP bypass and encryption disable mechanisms:
■ 1'b0: The default 1'b0 value enables you to bypass HDCP
through bit 5 (bypencryption) of the A_HDCPCFG0
register or to disable the encryption through bit 1
(encryptiondisable) of A_HDCPCFG1.
■ 1'b1: You can still write to the bit bypencryption of
A_HDCPCFG0 or encryptiondisable bit of A_HDCPCFG1
but you cannot enable the bypass.
Once you set the value to 1'b1, you can change the value
back to 1'b0 only by issuing a master reset to the
DWC_hdmi_tx.
Exists: Always
3 dissha1check R/W Disables the request to the API processor to verify the SHA1
message digest of a received KSV List
Exists: Always
2 ph2upshftenc R/W Enables the encoding of packet header in the tmdsch0 bit[0]
with cipher[2] instead of the tmdsch0 bit[2]
Note: This bit must always be set to 1 for all PHYs (PHY
GEN1, PHY GEN2, and non-Synopsys PHY).
Exists: Always
1 encryptiondisable R/W Disable encryption without losing authentication
Exists: Always
0 swreset R/W Software reset signal, active by writing a zero and auto
cleared to 1 in the following cycle.
Exists: Always

6.14.3 a_hdcpobs0
■ Description: HDCP Observation Register 0
■ Size: 8 bits
■ Offset: 0x5002
■ Exists: HDCP==1
Table 6-361 Fields for Register: a_hdcpobs0
Memory
7:4 STATEA R Observability register informs in which state the authentication machine
is on.
Exists: Always
3:1 SUBSTATEA R Observability register informs in which sub-state the authentication is on.
Exists: Always
0 hdcpengaged R Informs that the current HDMI link has the HDCP protocol fully engaged.
Exists: Always
6.14.4 a_hdcpobs1
■ Size: 8 bits
■ Offset: 0x5003
■ Exists: HDCP==1
Memory
6:4 STATEOEG R Observability register informs in which state the OESS machine is on.
Exists: Always
3:0 STATER R Observability register informs in which state the revocation machine is
on.
Exists: Always

6.14.5 a_hdcpobs2
■ Size: 8 bits
■ Offset: 0x5004
■ Exists: HDCP==1
Memory
5:3 STATEE R Observability register informs in which state the cipher
machine is on.
Exists: Always
2:0 STATEEEG R Observability register informs in which state the EESS
machine is on.
Exists: Always

6.14.6 a_hdcpobs3
■ Size: 8 bits
■ Offset: 0x5005
■ Exists: HDCP==1
Memory
7 HDMI_RESERVED_1 R Register read from attached sink device: Bcap(0x40) bit 7.
Exists: Always
6 REPEATER R Register read from attached sink device: Bcap(0x40) bit 6.
Exists: Always
5 KSV_FIFO_READY R Register read from attached sink device: Bcap(0x40) bit 5.
Exists: Always
4 FAST_I2C R Register read from attached sink device: Bcap(0x40) bit 4.
Exists: Always
3 HDMI_RESERVED_2 R Register read from attached sink device: Bstatus(0x41) bit
13.
Exists: Always
2 HDMI_MODE R Register read from attached sink device: Bstatus(0x41) bit
12.
Exists: Always
1 FEATURES_1_1 R Register read from attached sink device: Bcap(0x40) bit 1.
Exists: Always
0 FAST_REAUTHENTICATION R Register read from attached sink device: Bcap(0x40) bit 0.
Exists: Always

6.14.7 a_apiintclr
■ Description: HDCP Interrupt Clear Register
Write only register, active high and auto cleared, cleans the respective interruption in the interrupt
status register.
■ Size: 8 bits
■ Offset: 0x5006
■ Exists: HDCP==1
Table 6-365 Fields for Register: a_apiintclr
Memory
7 HDCP_engaged W Clears the interruption related to HDCP authentication
process successful.
Exists: Always
6 HDCP_failed W Clears the interruption related to HDCP authentication
process failed.
Exists: Always
5 KSVsha1calcdoneint W Clears the interruption related to SHA1 verification has been
done
Exists: HTX_HDCP_SW_SHA1CALC==0
4 I2Cnack W Clears the interruption related to I2C NACK reception.
Exists: Always
3 Lostarbitration W Clears the interruption related to I2C arbitration lost.
Exists: Always
2 Keepouterrorint W Clears the interruption related to keep out window error.
Exists: Always
1 KSVsha1calcint W Clears the interruption related to KSV list update in memory
that needs to be SHA1 verified.
0 KSVaccessint W Clears the interruption related to KSV memory access grant
for Read-Write access.
Exists: Always

6.14.8 a_apiintstat
■ Description: HDCP Interrupt Status Register
Read only register, reports the interruption which caused the activation of the interruption output
pin.
■ Size: 8 bits
■ Offset: 0x5007
■ Exists: HDCP==1
Table 6-366 Fields for Register: a_apiintstat
Memory
7 HDCP_engaged R Notifies that the HDCP authentication process was successful
Exists: Always
6 HDCP_failed R Notifies that the HDCP authentication process was failed.
Exists: Always
5 KSVsha1calcdoneint R Notifies that the HDCP13TCTRL block SHA1 verification has
been done. The status ready to be read.
4 I2Cnack R Notifies that the I2C received a NACK from slave device.
Exists: Always
3 Lostarbitration R Notifies that the I2C lost the arbitration to communicate. Another
master gained arbitration.
Exists: Always
2 Keepouterrorint R Notifies that during the keep out window, the ctlout[3:0] bus was
used besides control period.
Exists: Always
1 KSVsha1calcint R Notifies that the HDCP13TCTRL block as updated a KSV list in
memory that needs to be SHA1 verified.
0 KSVaccessint R Notifies that the KSV memory access as been guaranteed for
Read-Write access.
Exists: Always

6.14.9 a_apiintmsk
■ Description: HDCP Interrupt Mask Register
The configuration of this register mask a given setup of interruption, disabling them from generating
interruption pulses in the interruption output pin.
■ Size: 8 bits
■ Offset: 0x5008
■ Exists: HDCP==1
Table 6-367 Fields for Register: a_apiintmsk
Memory
7 HDCP_engaged R/W Masks the interruption related to HDCP authentication process
successful.
Exists: Always
6 HDCP_failed R/W Masks the interruption related to HDCP authentication process
failed.
Exists: Always
5 KSVsha1calcdoneint R/W Masks the interruption related to SHA1 verification has been done
Otherwise, this field is a "spare" bit with no associated functionality.
4 I2Cnack R/W Masks the interruption related to I2C NACK reception.
Exists: Always
3 Lostarbitration R/W Masks the interruption related to I2C arbitration lost.
Exists: Always
2 Keepouterrorint R/W Masks the interruption related to keep out window error.
Exists: Always
1 KSVsha1calcint R/W Masks the interruption related to KSV list update in memory that
needs to be SHA1 verified. Otherwise, this field is a "spare" bit with
0 KSVaccessint R/W Masks the interruption related to KSV memory access grant for
Read-Write access.
Exists: Always

6.14.10 a_vidpolcfg
■ Description: HDCP Video Polarity Configuration Register
■ Size: 8 bits
■ Offset: 0x5009
■ Exists: HDCP==1
Table 6-368 Fields for Register: a_vidpolcfg
Memory
6:5 unencryptconf R/W Configuration of the color sent when sending unencrypted
video data
For a complete table showing the color results (RGB), refer
to the "Color Configuration When Sending Unencrypted
Video Data" figure in Chapter 2, "Functional Description."
Exists: Always
4 dataenpol R/W Configuration of the video data enable polarity
Exists: Always
3 vsyncpol R/W Configuration of the video Vertical synchronism polarity
Exists: Always
Exists: Always
1 hsyncpol R/W Configuration of the video Horizontal synchronism polarity.
Exists: Always
Exists: Always

6.14.11 a_oesswcfg
■ Description: HDCP OESS WOO Configuration Register
Pulse width of the encryption enable (CTL3) signal in the HDCP OESS mode. The window of
opportunity for the Original Encryption Status Signaling starts at the active edge of the Vertical
synchronism and stops after oesswindowoffset[7:0]*4 clock cycles of TMDS clock. According to the
HDCP specification, the CTL3 signal must be asserted at least for eight TMDS clock cycles
(oesswindowoffset[7:0] must be greater than 1), and it is recommended to transmit a larger pulse
width for enhanced link reliability.
■ Size: 8 bits
■ Offset: 0x500a
■ Exists: HDCP==1
Table 6-369 Fields for Register: a_oesswcfg
Memory
7:0 a_oesswcfg R/W HDCP OESS WOO Configuration Register
Exists: Always
6.14.12 a_coreverlsb
■ Description: HDCP Controller Version Register LSB
Design ID number.
■ Size: 8 bits
■ Offset: 0x5014
■ Exists: HDCP==1
Table 6-370 Fields for Register: a_coreverlsb
Memory
7:0 a_coreverlsb R HDCP Controller Version Register LSB
Exists: Always

6.14.13 a_corevermsb
■ Description: HDCP Controller Version Register MSB
Revision ID number.
■ Size: 8 bits
■ Offset: 0x5015
■ Exists: HDCP==1
Table 6-371 Fields for Register: a_corevermsb
Memory
7:0 a_corevermsb R HDCP Controller Version Register MSB
Exists: Always

6.14.14 a_ksvmemctrl
■ Description: HDCP KSV Memory Control Register
The KSVCTRLupd bit is a notification flag. This flag changes polarity whenever the register is
written. This flag acts as a trigger to other blocks that processes this data. Upon reset the flag returns
to low default value.
■ Size: 8 bits
■ Offset: 0x5016
■ Exists: HDCP==1
Table 6-372 Fields for Register: a_ksvmemctrl
Memory
4 KSVsha1status R Notification whether the KSV list message digest is correct
from the controller: 1'b1 if digest message verification failed
1'b0 if digest message verification succeeded
3 SHA1fail R/W Notification whether the KSV list message digest is correct.
2 KSVCTRLupd R/W Set to inform that the KSV list in memory has been analyzed
and the response to the Message Digest has been updated if
on configurations on software SHA-1 calculation.
Exists: Always
1 KSVMEMaccess R Notification that the KSV memory access as been
guaranteed.
Exists: Always
0 KSVMEMrequest R/W Request access to the KSV memory; must be de-asserted
after the access is completed by the system.
Exists: Always

6.14.15 hdcp_bstatus[0:1]
■ Description: HDCP BStatus Register Array
■ Size: 8 bits
■ Offset: 0x5020 + (i * 0x1)
■ Exists: Always
Table 6-373 Fields for Register: hdcp_bstatus[0:1]
Memory
7:0 bstatus R/W HDCP BSTATUS[15:0]. If memory access has not been
granted (see register a_ksvmemctrl), the value read will be
8'hff.
Exists: Always
6.14.16 hdcp_m0[0:7]
■ Description: HDCP M0 Register Array
■ Size: 8 bits
■ Offset: 0x5022 + (i * 0x1)
■ Exists: Always
Table 6-374 Fields for Register: hdcp_m0[0:7]
Memory
7:0 M0 R/W HDCP M0[32:0]. If memory access has not been granted
(see register a_ksvmemctrl) , the value read will be 8'hff.
These values are only available on a configuration that has
the SHA1 calculation by software(refer to DesignWare
Cores HDMI Transmitter User Guide in the "Programming"
chapter, Section 3.2.4, "Configure HDCP.").
Exists: Always

6.14.17 hdcp_ksv[0:634]
■ Description: HDCP KSV Registers.
■ Size: 8 bits
■ Offset: 0x502a + (i * 0x1)
■ Exists: Always
Table 6-375 Fields for Register: hdcp_ksv[0:634]
Memory
7:0 hdcp_ksv_byte R/W Sink KSV FIFO byte, ordered in little endian (byte at address
0x502a belongs to byte 0 of KSV0). If memory access has
not been granted (see register a_ksvmemctrl), the value
read is 8'hff.
In this address space, 635 KSV FIFO bytes are mapped,
which allow for 127 KSV values, each with 5 bytes (40 bits).
For a detailed memory map, refer to "Address Mapping for
Maximum Memory Allocation" table in the "Functional
Description" chapter.
Exists: Always

6.14.18 hdcp_vh[0:19]
■ Description: HDCP SHA-1 VH Registers.
■ Size: 8 bits
■ Offset: 0x52a5 + (i * 0x1)
■ Exists: Always
Table 6-376 Fields for Register: hdcp_vh[0:19]
Memory
7:0 hdcp_vh_byte R/W Sink VH' byte, ordered in little endian (byte at address
0x525a belongs to byte 0 of VH0). If memory access has not
been granted (see register a_ksvmemctrl), the value read is
8'hff.
In this address space 20 VH bytes are mapped, which allow
for 5 VH values, each with 4 bytes (32bits). For a detailed
memory map, refer to "Address Mapping for Maximum
Memory Allocation" table in the "Functional Description"
chapter.
Exists: Always
6.14.19 hdcp_revoc_size_0
■ Description: HDCP Revocation KSV List Size Register 0
■ Size: 8 bits
■ Offset: 0x52b9
■ Exists: HDCP==1
Table 6-377 Fields for Register: hdcp_revoc_size_0
Memory
7:0 hdcp_revoc_size_0 R/W Register containing the LSB of KSV list size
(ksv_list_size[7:0]). If memory access has not been granted
(see register a_ksvmemctrl), the value read is 8'hff.
Exists: Always

6.14.20 hdcp_revoc_size_1
■ Description: HDCP Revocation KSV List Size Register 1
■ Size: 8 bits
■ Offset: 0x52ba
■ Exists: HDCP==1
Table 6-378 Fields for Register: hdcp_revoc_size_1
Memory
7:0 hdcp_revoc_size_1 R/W Register containing the MSB of KSV list size
(ksv_list_size[15:8]). If memory access has not been granted
(see register a_ksvmemctrl), the value read is 8'hff.
Exists: Always
6.14.21 hdcp_revoc_list[0:5059]
■ Description: HDCP Revocation KSV Registers.
■ Size: 8 bits
■ Offset: 0x52bb + (i * 0x1)
■ Exists: Always
Table 6-379 Fields for Register: hdcp_revoc_list[0:5059]
Memory
7:0 hdcp_revoc_list_ksv_byte R/W Revocation KSV byte, ordered in little endian (byte at
address 0x52bb belongs to byte 0 of the first revoked KSV).
If memory access has not been granted (see register
a_ksvmemctrl), the value read is 8'hff.
In this address space 5060 revoked KSV bytes are mapped,
which allow for 1012 KSV values, each with 5 bytes (40 bits).
For a detailed memory map, refer to "Address Mapping for
Maximum Memory Allocation" table in the "Functional
Description" chapter
Exists: Always

6.14.22 hdcpreg_bksv0
■ Description: HDCP KSV Status Register 0
■ Size: 8 bits
■ Offset: 0x7800
■ Exists: HDCP==1
Table 6-380 Fields for Register: hdcpreg_bksv0
Memory
7:0 hdcpreg_bksv0 R Contains the value of BKSV[7:0].
Exists: Always
■ Size: 8 bits
■ Offset: 0x7801
■ Exists: HDCP==1
Memory
Exists: Always

■ Size: 8 bits
■ Offset: 0x7802
■ Exists: HDCP==1
Memory
Exists: Always
■ Size: 8 bits
■ Offset: 0x7803
■ Exists: HDCP==1
Memory
Exists: Always

■ Size: 8 bits
■ Offset: 0x7804
■ Exists: HDCP==1
Memory
Exists: Always
6.14.27 hdcpreg_anconf
■ Description: HDCP AN Bypass Control Register
■ Size: 8 bits
■ Offset: 0x7805
■ Exists: HDCP==1
Table 6-385 Fields for Register: hdcpreg_anconf
Memory
0 oanbypass R/W
■ When oanbypass=1, the value of AN used in the HDCP
engine comes from the hdcpreg_an0 to hdcpreg_an7
registers.
■ When oanbypass=0, the value of AN used in the HDCP
engine comes from the random number input. For more
information, refer to "Random Number Generation
Interface" on page 79.
Exists: Always

6.14.28 hdcpreg_an0
■ Description: HDCP Forced AN Register 0
■ Size: 8 bits
■ Offset: 0x7806
■ Exists: HDCP==1
Table 6-386 Fields for Register: hdcpreg_an0
Memory
7:0 hdcpreg_an0 R/W Contains the value of AN[7:0]
Exists: Always
6.14.29 hdcpreg_an1
■ Size: 8 bits
■ Offset: 0x7807
■ Exists: HDCP==1
Memory
Exists: Always

6.14.30 hdcpreg_an2
■ Description: HDCP forced AN Register 2
■ Size: 8 bits
■ Offset: 0x7808
■ Exists: HDCP==1
Memory
Exists: Always
6.14.31 hdcpreg_an3
■ Size: 8 bits
■ Offset: 0x7809
■ Exists: HDCP==1
Memory
Exists: Always

6.14.32 hdcpreg_an4
■ Size: 8 bits
■ Offset: 0x780a
■ Exists: HDCP==1
Memory
Exists: Always
6.14.33 hdcpreg_an5
■ Size: 8 bits
■ Offset: 0x780b
■ Exists: HDCP==1
Memory
Exists: Always

6.14.34 hdcpreg_an6
■ Size: 8 bits
■ Offset: 0x780c
■ Exists: HDCP==1
Memory
Exists: Always
6.14.35 hdcpreg_an7
■ Size: 8 bits
■ Offset: 0x780d
■ Exists: HDCP==1
Memory
7:0 hdcpreg_an7 R/W Contains the value of BKSV[63:56]
Exists: Always

6.14.36 hdcpreg_rmlctl
■ Description: HDCP Encrypted Device Private Keys Control Register
This register is the control register for the software programmable encrypted DPK embedded storage
feature. The required software configuration sequence is documented in the DesignWare Cores
HDMI Transmitter User Guide in the "Programming" chapter, Section 3.2.4, "Configure HDCP."
■ Size: 8 bits
■ Offset: 0x780e
■ Exists: DWC_HDMI_HDCP_DPK_ROMLESS==1
Table 6-394 Fields for Register: hdcpreg_rmlctl
Memory
0 odpk_decrypt_enable R/W When set (1'b1), this bit activates the decryption of the
Device Private keys.
Exists: Always
6.14.37 hdcpreg_rmlsts
■ Description: HDCP Encrypted DPK Status Register
The required software configuration sequence is documented in the DesignWare Cores HDMI
Transmitter User Guide in the "Programming" chapter, Section 3.2.4, "Configure HDCP."
■ Size: 8 bits
■ Offset: 0x780f
Table 6-395 Fields for Register: hdcpreg_rmlsts
Memory
6 idpk_wr_ok_sts R When high (1'b1), it indicates that a DPK write is allowed.
Exists: Always
5:0 idpk_data_index R Current Device Private Key being written plus one. Position 0
is occupied by the AKSV.
Exists: Always

6.14.38 hdcpreg_seed0
■ Description: HDCP Encrypted DPK Seed Register 0
This register contains a byte of the HDCP Encrypted DPK seed value used to encrypt the Device
Private Keys. The required software configuration sequence is documented in the DesignWare Cores
■ Size: 8 bits
■ Offset: 0x7810
Table 6-396 Fields for Register: hdcpreg_seed0
Memory
7:0 hdcpreg_seed0 W Least significant byte of the decryption seed value
(dpk_decrypt_seed[7:0]).
Exists: Always
6.14.39 hdcpreg_seed1
■ Description: HDCP Encrypted DPK Seed Register 1
This register contains a byte of the HDCP Encrypted DPK seed value used to encrypt the Device
Private Keys. The required software configuration sequence is documented in the DesignWare Cores
■ Size: 8 bits
■ Offset: 0x7811
Table 6-397 Fields for Register: hdcpreg_seed1
Memory
7:0 hdcpreg_seed1 W Most significant byte of the decryption seed value
(dpk_decrypt_seed[15:8]).
Exists: Always

6.14.40 hdcpreg_dpk0
■ Description: HDCP Encrypted DPK Data Register 0
This register contains an HDCP DPK byte. The required software configuration sequence is
documented in the DesignWare Cores HDMI Transmitter User Guide in the "Programming" chapter,
Section 3.2.4, "Configure HDCP."
■ Size: 8 bits
■ Offset: 0x7812
Table 6-398 Fields for Register: hdcpreg_dpk0
Memory
7:0 dpk_data W Byte of the encrypted DPK value. dpk[7:0]
When this byte is written, a strobe signal is generated that
triggers the decryption and/or storage of the DPK word on
the DPK internal RAM memory.
Exists: Always
■ Size: 8 bits
■ Offset: 0x7813
Memory
Exists: Always

■ Size: 8 bits
■ Offset: 0x7814
Memory
Exists: Always
■ Size: 8 bits
■ Offset: 0x7815
Memory
Exists: Always

■ Size: 8 bits
■ Offset: 0x7816
Memory
Exists: Always
■ Size: 8 bits
■ Offset: 0x7817
Memory
7:0 dpk_data W Contains the value of DPK[x][47:40]
Exists: Always

■ Size: 8 bits
■ Offset: 0x7818
Memory
7:0 dpk_data W Contains the value of DPK[x][55:48]
Exists: Always

6.15 HDCP22 Registers

HDCP22 Registers. Follow the link for the register to see a detailed description of the register.
Table 6-405 Registers for Address Block: HDCP22

hdcp22reg_id on page 470 0x7900 HDCP 2.2 Identification Register
hdcp22reg_ctrl on page 471 0x7904 HDCP 2.2 Control Register
hdcp22reg_ctrl1 on page 473 0x7905 HDCP 2.2 Control Register 1
hdcp22reg_sts on page 474 0x7908 HDCP 2.2 Status Register
hdcp22reg_mask on page 475 0x790c HDCP 2.2 Interrupt Mask Register
hdcp22reg_stat on page 476 0x790d HDCP 2.2 interrupt Sticky Bit Status Register
hdcp22reg_mute on page 477 0x790e HDCP 2.2 Interrupt Mute Vector

6.15.1 hdcp22reg_id
■ Description: HDCP 2.2 Identification Register
■ Size: 8 bits
■ Offset: 0x7900
■ Exists: HTX_HDCP22_EXTERNAL==1
Table 6-406 Fields for Register: hdcp22reg_id
Memory
2 hdcp22_3rdparty R Indicates that External HDCP 2.2 interface is present and 3rd party
HDCP 2.2 module is connected to this interface.
Value After Reset: "(HTX_HDCP22_EXTERNAL_ELLP== 1) ? 1 : 0"
Exists: Always
1 hdcp22_externalif R Indicates that External HDCP 2.2 interface is present.
Value After Reset: "(HTX_HDCP22_EXTERNAL_NONE== 1) ? 1 :
0"
Exists: Always

6.15.2 hdcp22reg_ctrl
■ Description: HDCP 2.2 Control Register
■ Size: 8 bits
■ Offset: 0x7904
Table 6-407 Fields for Register: hdcp22reg_ctrl
Memory
5 hpd_ovr_val R/W HPD Override Value
■ 1'b0: If hpd_ovr_en is 1'b1 the HPD value to the HDCP 2.2 external
interface is set to 1'b0.
■ 1'b1: If hpd_ovr_en is 1'b1 the HPD value to the HDCP 2.2 external
interface is set to 1'b1.
Exists: Always
4 hpd_ovr_en R/W HPD Override enable
■ 1'b0: The HPD value to the HDCP 2.2 external interface comes from
the PHY as in phy_stat0.HPD.
■ 1'b1: The HPD value to the HDCP 2.2 external interface comes from
hpd_ovr_val bit field.
Exists: Always
2 hdcp22_ovr_val R/W HDCP 2.2 versus 1.4 switch override value
■ 1'b0: The switch is routed to HDCP 1.4 signals when hdcp22_ovr_en
is 1'b1 and hdcp22_switch_lock is not set to 1'b1.
■ 1'b1: The switch is routed to HDCP 2.2 signals when hdcp22_ovr_en
is 1'b1 and hdcp22_switch_lock is not set to 1'b1.
Exists: Always

Table 6-407 Fields for Register: hdcp22reg_ctrl (Continued)
Memory
1 hdcp22_ovr_en R/W HDCP 2.2 versus 1.4 switch override enable
■ 1'b0: The switch is automatically controlled by the HDCP 2.2
controller using the ist_hdcp2_capable and ist_hdcp2_not_capable
status level indications. If the HDCP 2.2 controller indicates
ist_hdcp2_capable at 1'b1, the switch is routed to HDCP 2.2 signals.
If the HDCP 2.2 controller indicates ist_hdcp2_not_capable at 1'b1,
the switch is routed to HDCP 1.4 signals.
■ 1'b1: The HDCP 2.2 ist_hdcp2_capable and ist_hdcp2_not_capable
values are ignored, and the direction of the HDCP 2.2 versus 1.4
switch is directly controlled by the hdcp22_ovr_val.
Exists: Always
0 hdcp22_switch_lck R/W HDCP 2.2 switch lock
■ 1'b0: Enables you to change the direction of the HDCP 2.2 versus 1.4
switch by using the hdcp22_ovr_en and hdcp22_ovr_val.
■ 1'b1: You can still write to hdcp22_ovr_en and hdcp22_ovr_val but
has no effect over the HDCP 2.2 versus 1.4 switch, that keeps as it
was configured by hdcp22_ovr_en and hdcp22_ovr_val at the time
the 1'b1 was written to this bit field.
Once you set the value to 1'b1, you can change the value back to 1'b0
only by issuing a master reset to the DWC_hdmi_tx.
Exists: Always

6.15.3 hdcp22reg_ctrl1
■ Description: HDCP 2.2 Control Register 1
■ Size: 8 bits
■ Offset: 0x7905
Table 6-408 Fields for Register: hdcp22reg_ctrl1
Memory
7:4 hdcp22_cd_ovr_val R/W HDCP color depth override value, which is sent through the
HDCP 2.2 external interface when
hdcp22reg_ctrl1.hdcp22_cd_ovr_en is set.
For reference on the HDMI allowed values consult the HDMI 1.4b
specification, Table 6-1.
Exists: Always
3 hdcp22_cd_ovr_en R/W HDCP 2.2 versus 1.4 color depth override enable:
■ 1'b0: The default 1'b0 value indicates that the color depth sent
to the external interface is the one configured in the
vp_pr_cd.color_depth register field.
■ 1'b1: Although the used color depth for pixel encoding is
defined by the field vp_pr_cd.color_depth register, the color
depth sent to the external interface is the one defined in
register field hdcp22reg_ctrl1.hdcp22_cd_ovr_val.
Exists: Always
1 hdcp22_avmute_ovr_val R/W HDCP AV_MUTE override value, which is sent through the HDCP
2.2 external interface when
hdcp22reg_ctrl1.hdcp22_avmute_ovr_en is set.
Exists: Always
0 hdcp22_avmute_ovr_en R/W HDCP 2.2 versus 1.4 avmute override enable
■ 1'b0: The default 1'b0 value indicates that the AVMUTE sent
to the external interface is the one configured through register
fields fc_gcp.set_avmute and fc_gcp.clear_avmute.
■ 1'b1: Although the GCP packet sends the set_avmute or
clear_avmute as configured in register fc_gcp, the AV_MUTE
sent to the external interface is the one defined in register field
hdcp22reg_ctrl1.hdcp22_avmute_ovr_val.
Exists: Always

6.15.4 hdcp22reg_sts
■ Description: HDCP 2.2 Status Register
■ Size: 8 bits
■ Offset: 0x7908
Table 6-409 Fields for Register: hdcp22reg_sts
Memory
3 hdcp_decrypted_sts R Value of HDCP 2.2 ist_hdcp_decrypted line. Provided for
debug only
Exists: Always
2 hdcp22_switch_sts R HDCP 2.2 HDCP 2.2 versus 1.4 switch status after lock
mechanism (hdcp22reg_ctrl.hdcp22_switch_lock,
hdcp22reg_ctrl.hdcp22_ovr_en and
hdcp22reg_ctrl.hdcp22_ovr_val).
■ 1'b0: HDCP 1.4 selected
■ 1'b1: HDCP 2.2 selected
Exists: Always
1 hdcp_avmute_sts R HDCP 2.2 AVMUTE external interface status.
■ 1'b0: External HDCP used AVMUTE is clear
■ 1'b1: External HDCP AVMUTE is set (audio/video should
be muted)
Exists: Always
0 hdmi_hpd_sts R HDCP 2.2 HPD external interface status after lock
mechanism (hdcp22reg_ctrl.hdcp22_switch_lock,
hdcp22reg_ctrl.hdcp22_ovr_en and
hdcp22reg_ctrl.hdcp22_ovr_val).
■ 1'b0: Sink not detected (HPD line clear )
■ 1'b1: Sink detected (HPD line set)
Exists: Always

6.15.5 hdcp22reg_mask
■ Description: HDCP 2.2 Interrupt Mask Register
■ Size: 8 bits
■ Offset: 0x790c
Table 6-410 Fields for Register: hdcp22reg_mask
Memory
5 mask_hdcp_decrypted_chg R/W Active high interrupt mask to HDCP 2.2 decrypted value
change interrupt status
Exists: Always
4 mask_hdcp_authentication_fail R/W Active high interrupt mask to HDCP 2.2 authentication fail
interrupt status
Exists: Always
3 mask_hdcp_authenticated R/W Active high interrupt mask to HDCP 2.2 authenticated
interrupt status
Exists: Always
2 mask_hdcp_authentication_lost R/W Active high interrupt mask to HDCP 2.2 authentication lost
interrupt status
Exists: Always
1 mask_hdcp2_not_capable R/W Active high interrupt mask to HDCP 2.2 not capable rise
interrupt status
Exists: Always
0 mask_hdcp2_capable R/W Active high interrupt mask to HDCP 2.2 capable rise interrupt
status
Exists: Always

6.15.6 hdcp22reg_stat
■ Description: HDCP 2.2 interrupt Sticky Bit Status Register
■ Size: 8 bits
■ Offset: 0x790d
Table 6-411 Fields for Register: hdcp22reg_stat
Memory
5 st_hdcp_decrypted_chg R/W1C HDCP 2.2 decrypted value change interrupt status sticky bit.
Clear by Write 1 to this bit field
Exists: Always
4 st_hdcp_authentication_fail R/W1C HDCP 2.2 authentication fail interrupt status sticky bit. Clear
by Write 1 to this bit field
Exists: Always
3 st_hdcp_authenticated R/W1C HDCP 2.2 authenticated interrupt status sticky bit. Clear by
Write 1 to this bit field
Exists: Always
2 st_hdcp_authentication_lost R/W1C HDCP 2.2 authentication lost interrupt status sticky bit. Clear
Exists: Always
1 st_hdcp2_not_capable R/W1C HDCP 2.2 not capable rise interrupt status sticky bit. Clear
Exists: Always
0 st_hdcp2_capable R/W1C HDCP 2.2 capable rise interrupt status sticky bit. Clear by
Write 1 to this bit field
Exists: Always

6.15.7 hdcp22reg_mute
■ Description: HDCP 2.2 Interrupt Mute Vector
■ Size: 8 bits
■ Offset: 0x790e
Table 6-412 Fields for Register: hdcp22reg_mute
Memory
5 mute_hdcp_decrypted_chg R/W Active high interrupt mute to HDCP 2.2 decrypted value
change interrupt status
Exists: Always
4 mute_hdcp_authentication_fail R/W Active high interrupt mute to HDCP 2.2 authentication fail
interrupt status
Exists: Always
3 mute_hdcp_authenticated R/W Active high interrupt mute to HDCP 2.2 authenticated
interrupt status
Exists: Always
2 mute_hdcp_authentication_lost R/W Active high interrupt mute to HDCP 2.2 authentication lost
interrupt status
Exists: Always
1 mute_hdcp2_not_capable R/W Active high interrupt mute to HDCP 2.2 not capable rise
interrupt status
Exists: Always
0 mute_hdcp2_capable R/W Active high interrupt mute to HDCP 2.2 capable rise interrupt
status
Exists: Always

6.16 CEC Registers

CEC Registers. Follow the link for the register to see a detailed description of the register.
Table 6-413 Registers for Address Block: CEC

cec_ctrl on page 479 0x7d00 CEC Control Register This register handles the main control
of the CEC initiator.
cec_mask on page 481 0x7d02 CEC Interrupt Mask Register This read/write register
masks/unmasks the interrupt events. When the...
cec_addr_l on page 482 0x7d05 CEC Logical Address Register Low This register indicates
the logical address(es) allocated to the...
cec_addr_h on page 483 0x7d06 CEC Logical Address Register High This register indicates
the logical address(es) allocated to...
cec_tx_cnt on page 484 0x7d07 CEC TX Frame Size Register This register indicates the size
of the frame in bytes (including header...
cec_rx_cnt on page 485 0x7d08 CEC RX Frame Size Register This register indicates the size
of the frame in bytes (including header...
cec_tx_data[0:15] on page 485 0x7d10 + CEC TX Data Register Array Address offset: i = 0 to 15
(i * 0x1) These registers (8 bits each) are the buffers...
cec_rx_data[0:15] on page 486 0x7d20 + CEC RX Data Register Array Address offset: i =0 to 15
(i * 0x1) These registers (8 bit each) are the buffers...
cec_lock on page 486 0x7d30 CEC Buffer Lock Register
cec_wakeupctrl on page 487 0x7d31 CEC Wake-up Control Register After receiving a message in
the CEC_RX_DATA1 (OPCODE) registers,...

6.16.1 cec_ctrl
■ Description: CEC Control Register
This register handles the main control of the CEC initiator.
■ Size: 8 bits
■ Offset: 0x7d00
■ Exists: CEC==1
Table 6-414 Fields for Register: cec_ctrl
Memory
4 standby R/W ■ 1: CEC controller responds with a NACK to all messages
and generates a wakeup status for opcode. It only
responds with a NACK when the EOM is received. This
means only the last block of a frame responds with
NACK. The follower sends an ACK to the message when
there is only one head block pointed to the follower, if the
follower is in the standby mode.
■ 0: CEC controller responds the ACK to all messages.
Exists: Always
3 bc_nack R/W ■ 1'b1: Set by software to NACK the received broadcast
message. This bit holds until software resets. The
broadcasts is answered with 1'b0, indicating the follower
reject the message.
■ 1'b0: Reset by software to ACK the received broadcast
message.
Exists: Always
2:1 frame_typ R/W ■ 2'b00: Signal Free Time = 3-bit periods. Previous attempt
to send frame is unsuccessful.
■ 2'b01: Signal Free Time = 5-bit periods. New initiator
wants to send a frame.
■ 2'b10: Signal Free Time = 7-bit periods. Present initiator
wants to send another frame immediately after its
previous frame. (specification CEC 9.1).
■ 2'b11: Illegal value. If software writes this value, hardware
sets the value to the default 2'b01.
Exists: Always

Table 6-414 Fields for Register: cec_ctrl (Continued)
Memory
0 send R/W ■ 1'b1: Set by software to trigger CEC sending a frame as
an initiator. This bit keeps at 1'b1 while the transmission
is going on.
■ 1'b0: Reset to 1'b0 by hardware when the CEC
transmission is done (no matter successful or failed). It
can also work as an indicator checked by software to see
whether the transmission is finished.
Exists: Always

6.16.2 cec_mask
■ Description: CEC Interrupt Mask Register
This read/write register masks/unmasks the interrupt events. When the bit is set to 1 (masked), the
corresponding event does not trigger an interrupt signal at the system interface. When the bit is reset
to 0, the interrupt event is unmasked.
■ Size: 8 bits
■ Offset: 0x7d02
■ Exists: CEC==1
Table 6-415 Fields for Register: cec_mask
Memory
6 wakeup R/W Follower wake-up signal mask
Exists: Always
5 error_flow R/W An error is notified by a follower. Abnormal logic data bit error
(for follower)
Exists: Always
4 error_initiator R/W An error is detected on a CEC line (for initiator only).
Exists: Always
3 arb_lost R/W The initiator losses the CEC line arbitration to a second
initiator. (specification CEC 9)
Exists: Always
2 nack R/W A frame is not acknowledged in a directly addressed
message. Or a frame is negatively acknowledged in a
broadcast message (for initiator only)
Exists: Always
1 eom R/W EOM is detected so that the received data is ready in the
receiver data buffer (for follower only)
Exists: Always
0 done R/W The current transmission is successful (for initiator only)
Exists: Always

6.16.3 cec_addr_l
■ Description: CEC Logical Address Register Low
This register indicates the logical address(es) allocated to the CEC device.
This register is written by software when the logical allocation is finished. Bit value 1 means the
corresponding logical address is allocated to this device. Bit value 0 means the corresponding logical
address is not allocated to this device.
■ Size: 8 bits
■ Offset: 0x7d05
■ Exists: CEC==1
Table 6-416 Fields for Register: cec_addr_l
Memory
7 cec_addr_l_7 R/W Logical address 7 - Tuner 3
Exists: Always
Exists: Always
5 cec_addr_l_5 R/W Logical address 5 - Audio System
Exists: Always
4 cec_addr_l_4 R/W Logical address 4 - Playback Device 1
Exists: Always
Exists: Always
2 cec_addr_l_2 R/W Logical address 2 - Recording Device 2
Exists: Always
1 cec_addr_l_1 R/W Logical address 1 - Recording Device 1
Exists: Always
0 cec_addr_l_0 R/W Logical address 0 - Device TV
Exists: Always

6.16.4 cec_addr_h
■ Description: CEC Logical Address Register High
This register indicates the logical address(es) allocated to the CEC device.
This register is written by software when the logical allocation is finished. Bit value 1 means the
corresponding logical address is allocated to this device. Bit value 0 means the corresponding logical
address is not allocated to this device.
■ Size: 8 bits
■ Offset: 0x7d06
■ Exists: CEC==1
Table 6-417 Fields for Register: cec_addr_h
Memory
7 cec_addr_h_7 R/W Logical address 15 - Unregistered (as initiator address),
Broadcast (as destination address)
Exists: Always
6 cec_addr_h_6 R/W Logical address 14 - Free use
Exists: Always
5 cec_addr_h_5 R/W Logical address 13 - Reserved
Exists: Always
4 cec_addr_h_4 R/W Logical address 12 - Reserved
Exists: Always
3 cec_addr_h_3 R/W Logical address 11 - Playback Device 3
Exists: Always
2 cec_addr_h_2 R/W Logical address 10 - Tuner 4
Exists: Always
Exists: Always
Exists: Always

6.16.5 cec_tx_cnt
■ Description: CEC TX Frame Size Register
This register indicates the size of the frame in bytes (including header and data blocks), which are
available in the transmitter data buffer.
Note: When the value is zero, the CEC controller ignores the send command triggered by software.
When the transmission is done (no matter success or not), the current value is held until it is
overwritten by software.
■ Size: 8 bits
■ Offset: 0x7d07
■ Exists: CEC==1
Table 6-418 Fields for Register: cec_tx_cnt
Memory
4:0 cec_tx_cnt R/W CEC Transmitter Counter register
5'd0: No data needs to be transmitted
5'd1: Frame size is 1 byte
...
5'd16: Frame size is 16 bytes
Exists: Always

6.16.6 cec_rx_cnt
■ Description: CEC RX Frame Size Register
This register indicates the size of the frame in bytes (including header and data blocks), which are
available in the receiver data buffer.
Note: Only after the whole receiving process is finished successfully, the counter is refreshed to the
value which indicates the total number of data bytes in the Receiver Data Register.
■ Size: 8 bits
■ Offset: 0x7d08
■ Exists: CEC==1
Table 6-419 Fields for Register: cec_rx_cnt
Memory
4:0 cec_rx_cnt R CEC Receiver Counter register:
5'd0: No data received
5'd1: 1-byte data is received
...
5'd16: 16-byte data is received
Exists: Always
6.16.7 cec_tx_data[0:15]
■ Description: CEC TX Data Register Array
These registers (8 bits each) are the buffers used for storing the data waiting for transmission
(including header and data blocks).
■ Size: 8 bits
■ Offset: 0x7d10 + (i * 0x1)
■ Exists: Always
Table 6-420 Fields for Register: cec_tx_data[0:15]
Memory
7:0 databyte R/W Data byte[x], where x is 0 to 15
Exists: Always

6.16.8 cec_rx_data[0:15]
■ Description: CEC RX Data Register Array
Address offset: i =0 to 15
These registers (8 bit each) are the buffers used for storing the received data (including header and
data blocks).
■ Size: 8 bits
■ Offset: 0x7d20 + (i * 0x1)
■ Exists: Always
Table 6-421 Fields for Register: cec_rx_data[0:15]
Memory
7:0 databyte R Data byte[x], where x is 0 to 15
Exists: Always
6.16.9 cec_lock
■ Description: CEC Buffer Lock Register
■ Size: 8 bits
■ Offset: 0x7d30
■ Exists: CEC==1
Table 6-422 Fields for Register: cec_lock
Memory
0 locked_buffer R/W When a frame is received, this bit would be active. The CEC
controller answers to all the messages with NACK until the
CPU writes it to '0'.
Exists: Always

6.16.10 cec_wakeupctrl
■ Description: CEC Wake-up Control Register
After receiving a message in the CEC_RX_DATA1 (OPCODE) registers, the CEC engine verifies the
message opcode[7:0] against one of the previously defined values to generate the wake-up status:
Wakeupstatus is 1 when:
received opcode is 0x04 and opcode0x04en is 1 or
received opcode is 0x0D and opcode0x0Den is 1 or
received opcode is 0x86 and opcode0x86en is 1
Wakeupstatus is 0 when none of the previous conditions are true.
This formula means that the wake-up status (on CEC_STAT[6] register) is only '1' if the opcode[7:0]
received is equal to one of the defined values and the corresponding enable bit of that defined value
is set to '1'.
■ Size: 8 bits
■ Offset: 0x7d31
■ Exists: CEC==1
Table 6-423 Fields for Register: cec_wakeupctrl
Memory
7 opcode0x86en R/W OPCODE 0x86 wake up enable
Exists: Always
Exists: Always
Exists: Always
Exists: Always

Table 6-423 Fields for Register: cec_wakeupctrl (Continued)
Memory
Exists: Always
Exists: Always
1 opcode0x0Den R/W OPCODE 0x0D wake up enable
Exists: Always
Exists: Always

6.17 EDDC Registers

E-DDC Registers. Follow the link for the register to see a detailed description of the register.
Table 6-424 Registers for Address Block: EDDC

i2cm_slave on page 490 0x7e00 I2C DDC Slave address Configuration Register
i2cm_address on page 491 0x7e01 I2C DDC Address Configuration Register
i2cm_datao on page 491 0x7e02 I2C DDC Data Write Register
i2cm_datai on page 492 0x7e03 I2C DDC Data read Register
i2cm_operation on page 493 0x7e04 I2C DDC RD/RD_EXT/WR Operation Register Read and
write operation request. This register can only...
i2cm_int on page 494 0x7e05 I2C DDC Done Interrupt Register This register configures
the I2C master interrupts.
i2cm_ctlint on page 495 0x7e06 I2C DDC error Interrupt Register This register configures the
I2C master arbitration lost and not...
i2cm_div on page 496 0x7e07 I2C DDC Speed Control Register This register configures
the division relation between master and...
i2cm_segaddr on page 496 0x7e08 I2C DDC Segment Address Configuration Register This
register configures the segment address for...
i2cm_softrstz on page 497 0x7e09 I2C DDC Software Reset Control Register This register
resets the I2C master.
i2cm_segptr on page 497 0x7e0a I2C DDC Segment Pointer Register This register configures
the segment pointer for extended RD/WR...
i2cm_ss_scl_hcnt_1_addr on page 498 0x7e0b I2C DDC Slow Speed SCL High Level Control Register 1
i2cm_ss_scl_hcnt_0_addr on page 498 0x7e0c I2C DDC Slow Speed SCL High Level Control Register 0
i2cm_ss_scl_lcnt_1_addr on page 499 0x7e0d I2C DDC Slow Speed SCL Low Level Control Register 1
i2cm_ss_scl_lcnt_0_addr on page 499 0x7e0e I2C DDC Slow Speed SCL Low Level Control Register 0
i2cm_fs_scl_hcnt_1_addr on page 500 0x7e0f I2C DDC Fast Speed SCL High Level Control Register 1
i2cm_fs_scl_hcnt_0_addr on page 500 0x7e10 I2C DDC Fast Speed SCL High Level Control Register 0
i2cm_fs_scl_lcnt_1_addr on page 501 0x7e11 I2C DDC Fast Speed SCL Low Level Control Register 1
i2cm_fs_scl_lcnt_0_addr on page 501 0x7e12 I2C DDC Fast Speed SCL Low Level Control Register 0
i2cm_sda_hold on page 502 0x7e13 I2C DDC SDA Hold Register
i2cm_scdc_read_update on page 502 0x7e14 SCDC Control Register This register configures the SCDC
update status read through the I2C master...
i2cm_read_buff0 on page 503 0x7e20 I2C Master Sequential Read Buffer Register 0

Table 6-424 Registers for Address Block: EDDC (Continued)

i2cm_scdc_update0 on page 507 0x7e30 I2C SCDC Read Update Register 0
i2cm_scdc_update1 on page 507 0x7e31 I2C SCDC Read Update Register 1
6.17.1 i2cm_slave
■ Description: I2C DDC Slave address Configuration Register
■ Size: 8 bits
■ Offset: 0x7e00
■ Exists: Always
Table 6-425 Fields for Register: i2cm_slave
Memory
6:0 slaveaddr R/W Slave address to be sent during read and write normal
operations.
Exists: Always

6.17.2 i2cm_address
■ Description: I2C DDC Address Configuration Register
■ Size: 8 bits
■ Offset: 0x7e01
■ Exists: Always
Table 6-426 Fields for Register: i2cm_address
Memory
7:0 address R/W Register address for read and write operations
Exists: Always
6.17.3 i2cm_datao
■ Description: I2C DDC Data Write Register
■ Size: 8 bits
■ Offset: 0x7e02
■ Exists: Always
Table 6-427 Fields for Register: i2cm_datao
Memory
7:0 datao R/W Data to be written on register pointed by address[7:0].
Exists: Always

6.17.4 i2cm_datai
■ Description: I2C DDC Data read Register
■ Size: 8 bits
■ Offset: 0x7e03
■ Exists: Always
Table 6-428 Fields for Register: i2cm_datai
Memory
7:0 datai R Data read from register pointed by address[7:0].
Exists: Always

6.17.5 i2cm_operation
■ Description: I2C DDC RD/RD_EXT/WR Operation Register
Read and write operation request. This register can only be written; reading this register always
results in 00h. Writing 1'b1 simultaneously to rd, rd_ext and wr requests is considered as a read (rd)
request.
■ Size: 8 bits
■ Offset: 0x7e04
■ Exists: Always
Table 6-429 Fields for Register: i2cm_operation
Memory
5 busclear W bus clear operation request.
Exists: Always
4 wr W Single byte write operation request.
Exists: Always
3 rd8_ext W Extended sequential read operation request. Eight bytes are
read starting at the address defined in register field
i2cm_address.address and stored in registers
i2cm_read_buffx. For more information on the extended read
operation, refer to "I2C Master Interface Extended Read
Mode" in the "Functional Description" chapter.
Exists: Always
2 rd8 W Sequential read operation request. Eight bytes are read
starting at the address defined in the i2cm_address.address
register field and stored in the i2cm_read_buffx registers.
Exists: Always
1 rd_ext W After writing 1'b1 to rd_ext bit a extended data read operation
is started (E-DDC read operation). For more information on
the extended read operation, refer to "I2C Master Interface
Extended Read Mode" in the "Functional Description"
chapter.
Exists: Always
0 rd W Single byte read operation request
Exists: Always

6.17.6 i2cm_int
■ Description: I2C DDC Done Interrupt Register
This register configures the I2C master interrupts.
■ Size: 8 bits
■ Offset: 0x7e05
■ Exists: Always
Table 6-430 Fields for Register: i2cm_int
Memory
6 read_req_mask R/W Read request interruption mask signal.
2 done_mask R/W Done interrupt mask signal.
Exists: Always

6.17.7 i2cm_ctlint
■ Description: I2C DDC error Interrupt Register
This register configures the I2C master arbitration lost and not acknowledge error interrupts.
■ Size: 8 bits
■ Offset: 0x7e06
■ Exists: Always
Table 6-431 Fields for Register: i2cm_ctlint
Memory
6 nack_mask R/W Not acknowledge error interrupt mask signal.
Exists: Always
2 arbitration_mask R/W Arbitration error interrupt mask signal.
Exists: Always

6.17.8 i2cm_div
■ Description: I2C DDC Speed Control Register
This register configures the division relation between master and scl clock.
■ Size: 8 bits
■ Offset: 0x7e07
■ Exists: Always
Table 6-432 Fields for Register: i2cm_div
Memory
3 fast_std_mode R/W Sets the I2C Master to work in Fast Mode or Standard Mode:
1: Fast Mode
0: Standard Mode
Exists: Always
Exists: Always
6.17.9 i2cm_segaddr
■ Description: I2C DDC Segment Address Configuration Register
This register configures the segment address for extended R/W destination and is used for EDID
reading operations, particularly for the Extended Data Read Operation for Enhanced DDC.
■ Size: 8 bits
■ Offset: 0x7e08
■ Exists: Always
Table 6-433 Fields for Register: i2cm_segaddr
Memory
6:0 seg_addr R/W I2C DDC Segment Address Configuration Register
Exists: Always

6.17.10 i2cm_softrstz
■ Description: I2C DDC Software Reset Control Register
This register resets the I2C master.
■ Size: 8 bits
■ Offset: 0x7e09
■ Exists: Always
Table 6-434 Fields for Register: i2cm_softrstz
Memory
0 i2c_softrstz R/W I2C Master Software Reset. Active by writing a zero and auto
cleared to one in the following cycle.
Exists: Always
6.17.11 i2cm_segptr
■ Description: I2C DDC Segment Pointer Register
This register configures the segment pointer for extended RD/WR request.
■ Size: 8 bits
■ Offset: 0x7e0a
■ Exists: Always
Table 6-435 Fields for Register: i2cm_segptr
Memory
7:0 segptr R/W I2C DDC Segment Pointer Register
Exists: Always

6.17.12 i2cm_ss_scl_hcnt_1_addr
■ Description: I2C DDC Slow Speed SCL High Level Control Register 1
■ Size: 8 bits
■ Offset: 0x7e0b
■ Exists: Always
Table 6-436 Fields for Register: i2cm_ss_scl_hcnt_1_addr
Memory
7:0 i2cmp_ss_scl_hcnt1 R/W I2C DDC Slow Speed SCL High Level Control Register 1
Exists: Always
6.17.13 i2cm_ss_scl_hcnt_0_addr
■ Description: I2C DDC Slow Speed SCL High Level Control Register 0
■ Size: 8 bits
■ Offset: 0x7e0c
■ Exists: Always
Table 6-437 Fields for Register: i2cm_ss_scl_hcnt_0_addr
Memory
7:0 i2cmp_ss_scl_hcnt0 R/W I2C DDC Slow Speed SCL High Level Control Register 0
Value After Reset: 0x6c
Exists: Always

6.17.14 i2cm_ss_scl_lcnt_1_addr
■ Description: I2C DDC Slow Speed SCL Low Level Control Register 1
■ Size: 8 bits
■ Offset: 0x7e0d
■ Exists: Always
Table 6-438 Fields for Register: i2cm_ss_scl_lcnt_1_addr
Memory
7:0 i2cmp_ss_scl_lcnt1 R/W I2C DDC Slow Speed SCL Low Level Control Register 1
Exists: Always
6.17.15 i2cm_ss_scl_lcnt_0_addr
■ Description: I2C DDC Slow Speed SCL Low Level Control Register 0
■ Size: 8 bits
■ Offset: 0x7e0e
■ Exists: Always
Table 6-439 Fields for Register: i2cm_ss_scl_lcnt_0_addr
Memory
7:0 i2cmp_ss_scl_lcnt0 R/W I2C DDC Slow Speed SCL Low Level Control Register 0
Value After Reset: 0x7f
Exists: Always

6.17.16 i2cm_fs_scl_hcnt_1_addr
■ Description: I2C DDC Fast Speed SCL High Level Control Register 1
■ Size: 8 bits
■ Offset: 0x7e0f
■ Exists: Always
Table 6-440 Fields for Register: i2cm_fs_scl_hcnt_1_addr
Memory
7:0 i2cmp_fs_scl_hcnt1 R/W I2C DDC Fast Speed SCL High Level Control Register 1
Exists: Always
6.17.17 i2cm_fs_scl_hcnt_0_addr
■ Description: I2C DDC Fast Speed SCL High Level Control Register 0
■ Size: 8 bits
■ Offset: 0x7e10
■ Exists: Always
Table 6-441 Fields for Register: i2cm_fs_scl_hcnt_0_addr
Memory
7:0 i2cmp_fs_scl_hcnt0 R/W I2C DDC Fast Speed SCL High Level Control Register 0
Exists: Always

6.17.18 i2cm_fs_scl_lcnt_1_addr
■ Description: I2C DDC Fast Speed SCL Low Level Control Register 1
■ Size: 8 bits
■ Offset: 0x7e11
■ Exists: Always
Table 6-442 Fields for Register: i2cm_fs_scl_lcnt_1_addr
Memory
7:0 i2cmp_fs_scl_lcnt1 R/W I2C DDC Fast Speed SCL Low Level Control Register 1
Exists: Always
6.17.19 i2cm_fs_scl_lcnt_0_addr
■ Description: I2C DDC Fast Speed SCL Low Level Control Register 0
■ Size: 8 bits
■ Offset: 0x7e12
■ Exists: Always
Table 6-443 Fields for Register: i2cm_fs_scl_lcnt_0_addr
Memory
7:0 i2cmp_fs_scl_lcnt0 R/W I2C DDC Fast Speed SCL Low Level Control Register 0
Exists: Always

6.17.20 i2cm_sda_hold
■ Description: I2C DDC SDA Hold Register
■ Size: 8 bits
■ Offset: 0x7e13
■ Exists: Always
Table 6-444 Fields for Register: i2cm_sda_hold
Memory
7:0 osda_hold R/W Defines the number of SFR clock cycles to meet tHD;DAT (300 ns)
osda_hold = round_to_high_integer (300 ns / (1 / isfrclk_frequency))
Exists: Always
6.17.21 i2cm_scdc_read_update
■ Description: SCDC Control Register
This register configures the SCDC update status read through the I2C master interface.
■ Size: 8 bits
■ Offset: 0x7e14
Table 6-445 Fields for Register: i2cm_scdc_read_update
Memory
5 updtrd_vsyncpoll_en R/W Update read polling enabled. When active (1'b1), an SCDC Update
Read is performed at the fall of the active edge of the vertical sync
pulse.
Exists: Always
4 read_request_en R/W Read request enabled. When active (1'b1) an SCDC Update Read
shall be performed whenever a SCDC read request is detected.
Exists: Always
0 read_update W When set to 1'b1, a SCDC Update Read is performed and the read
data loaded into registers i2cm_scdc_update0 and
i2cm_scdc_update1.
Exists: Always

6.17.22 i2cm_read_buff0
■ Description: I2C Master Sequential Read Buffer Register 0
■ Size: 8 bits
■ Offset: 0x7e20
■ Exists: Always
Table 6-446 Fields for Register: i2cm_read_buff0
Memory
7:0 i2cm_read_buff0 R Byte 0 of a I2C read buffer sequential read (from address
i2cm_address)
Exists: Always
■ Size: 8 bits
■ Offset: 0x7e21
■ Exists: Always
Memory
i2cm_address+1)
Exists: Always

■ Size: 8 bits
■ Offset: 0x7e22
■ Exists: Always
Memory
i2cm_address+2)
Exists: Always
■ Size: 8 bits
■ Offset: 0x7e23
■ Exists: Always
Memory
i2cm_address+3)
Exists: Always

■ Size: 8 bits
■ Offset: 0x7e24
■ Exists: Always
Memory
i2cm_address+4)
Exists: Always
■ Size: 8 bits
■ Offset: 0x7e25
■ Exists: Always
Memory
i2cm_address+5)
Exists: Always

■ Size: 8 bits
■ Offset: 0x7e26
■ Exists: Always
Memory
i2cm_address+6)
Exists: Always
■ Size: 8 bits
■ Offset: 0x7e27
■ Exists: Always
Memory
i2cm_address+7)
Exists: Always

6.17.30 i2cm_scdc_update0
■ Description: I2C SCDC Read Update Register 0
■ Size: 8 bits
■ Offset: 0x7e30
Table 6-454 Fields for Register: i2cm_scdc_update0
Memory
7:0 i2cm_scdc_update0 R Byte 0 of a SCDC I2C update sequential read
Exists: Always
6.17.31 i2cm_scdc_update1
■ Description: I2C SCDC Read Update Register 1
■ Size: 8 bits
■ Offset: 0x7e31
Table 6-455 Fields for Register: i2cm_scdc_update1
Memory
7:0 i2cm_scdc_update1 R Byte 1 of a SCDC I2C update sequential read
Exists: Always


A
Internal Parameter Descriptions
Provides a description of the internal parameters that might be indirectly referenced in expressions in the
Signals, Parameters, or Registers chapters. These parameters are not visible in the coreConsultant GUI and
most of them are derived automatically from visible parameters. You must not set any of these parameters
directly.
Some expressions might refer to TCL functions or procedures (sometimes identified as function_of) that
GUI reports.
Table A-1 Internal Parameters
Parameter Name Equals To
AHBAUDDMAIF (AUDIO_IF ==8)
DOUBLEIF (AUDIO_IF ==4)
DWC_HDMI_HDCP_BYPASS 0
GDOUBLEIF (AUDIO_IF ==7)
GPAUDIF (AUDIO_IF ==6)
GPAUDPORTS (GPAUDIF || GDOUBLEIF)
HDMITX_HEAC_PHY_LIBNAME =get_env_heac_phy_lib
HDMITX_HEAC_PHY_PATH =get_env_heac_phy_path
HDMITX_PHY_LIBNAME =get_env_phy_lib
HDMITX_PHY_PATH =get_env_phy_path
HTX_HDCP22_EXTERNAL ((HTX_HDCP_TYPE == 2) ? 1 : 0)
HTX_HDCP22_EXTERNAL_ELLP ((HTX_HDCP_TYPE ==2) ?

((HTX_HDCP22_EXTERNAL_TYPE == 1) ? 1 : 0) : 0)

Internal Parameter Descriptions HDMI Transmitter Controller Databook
Table A-1 Internal Parameters (Continued)
Parameter Name Equals To
HTX_HDCP22_EXTERNAL_NONE ((HTX_HDCP_TYPE ==2) ?

((HTX_HDCP22_EXTERNAL_TYPE == 0) ? 1 : 0) : 0)
HTX_SCAN_PORT_WIDTH ((PHY_TYPE ==7 || PHY_TYPE ==8) ? 8 : (PHY_TYPE

==6 ) ? 4 :(PHY_TYPE ==5 ) ? 12 : (PHY_TYPE ==4 ) ?
12: (PHY_TYPE ==3 ) ? 12 : (PHY_TYPE ==2 ) ? 12 :
(PHY_TYPE ==1 ) ? 12 : 0)
I2SIF (AUDIO_IF ==1)
I2SPORTS (I2SIF || DOUBLEIF || GDOUBLEIF)
PHY_CHRT65LPE (PHY_TYPE ==2)
PHY_GEN2 (PHY_TYPE ==6 || PHY_TYPE ==7 || PHY_TYPE ==8)
PHY_HDMI20 (PHY_TYPE ==8)
PHY_MHL_COMBO (PHY_TYPE ==7 || PHY_TYPE ==8)
PHY_NO_AT_SPEEDSCAN ([function])
PHY_TYPE ([function])
SPDIFIF (AUDIO_IF ==2)
SPDIFPORTS (SPDIFIF || DOUBLEIF)

Index
A DMA
Advance Cipher 93 Engine 74
AHB Master 72 FSM 77
Operation 75
AMBA
APB slave interface 105, 123 DPK
56-Bit HDCP 99
An value 91
8-Bit HDCP 102
Audio
DPK (Device Private Keys 99
input interfaces 63
DSD 35
Audio DMA 72
DST 35
Audio stream
HBR 37 DVI 92
IEC 61937 compressed 37 DWC_hdmi_tx
L-PCM 37 block diagram 46
description 45
B I/O signals 121
Bypass Encryption 93 standards compliance 35
C E
CEC 111 ECC generators 88
clock EDID/HDCP I2C E-DDC 106
frequencies 42 E-EDID 37
ispdifclk 66
Encryption Disable 93
clock channels 36
Enhanced Link Verification 93
Color Space Conversion 62
Ethernet traffic 37
matrix 62
Controller with HDCP 90 F
Features 1.1 93
D
Follower Mode 111
Data Island
Packer 88 Frame Composer 87
Scheduler 88 Functional description, of DWC_hdmi_tx 45
Data Island Packets G
high priority 87 GPA 67
low priority 87 Data Mapping Examples 70
Device Private Keys 99 Timing 67
Display H
format configuration 36
HDCP 36, 46
Display Channel (DDC) 36
HDMI
SolvNet
April 2016 Synopsys, Inc. DesignWare.com 511
Index HDMI Transmitter Controller Databook
applications 35 Repeater 93
block diagram 36 revocmemclk 95
features 40
functional architecture 45 S
operational model 36 S/PDIF 66
product description 34 SCART 36
standards 35 Signals
System on Chip 34 Audio Input Interface 123
HEAC 37 Video Input Interface 123
I Standards compliance, of DWC_hdmi_tx 35
I2C System Memory
Fast Mode 93 data organization 73
Master Interface 106 T
I2S TMDS data 36
Format 64 Transfer Data Constitution 76
interface 64
V
Initiator Mode 111
Video
Interfaces 39
data 37
L data synchronization 47
L-PCM Packetizer 61
Eight-Channel Data Mapping 70 pixel rates 36
pixel sampler 47
M
supported modes 50
manual configuration 46
Memory
allocation 96
requirements 94
Revocation 94
N
NL-PCM
Data Mapping 71
O
OESS 91
Window of Opportunity Programming 91
P
Packet Classification 88
Period
Control 37
Data Island 37
Video Data 37
Pixel repetition 61
R
R Value Verification 93
Random Number Generation Interface 91
Receiver 93
SolvNet 2.12a
512 Synopsys, Inc.

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DesignWare® Cores HDMI Transmitter Controller

HDMI 1.3 TX Controller (without HDCP) – Product Code: 6934-0

Copyright Notice and Proprietary Information

2 SolvNet Synopsys, Inc. Version 2.12a

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2.11 HDMI Tx PHY Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105

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5.12 HDMI 3-D TX PHY (PHY GEN 2) Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157

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6.4 VideoPacketizer Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226

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6.5.42 fc_vsdpayload[0:23] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266

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6.5.91 fc_iscr1_4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 292

8 SolvNet Synopsys, Inc. Version 2.12a

6.5.140 fc_gmd_stat . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 325

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6.6.8 phy_pol0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 356

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6.9.3 aud_spdifint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 390

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6.13.13 csc_coef_b2_msb . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 429

12 SolvNet Synopsys, Inc. Version 2.12a

6.14.31 hdcpreg_an3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 460

Version 2.12a Synopsys, Inc. SolvNet 13

6.17.14 i2cm_ss_scl_lcnt_1_addr . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 499

14 SolvNet Synopsys, Inc. Version 2.12a

Date Version Description

Version 2.12a Synopsys, Inc. SolvNet 15

- Synchronous to: field for following signals:

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32 SolvNet Synopsys, Inc. Version 2.12a

This chapter includes the following topics:

Version 2.12a Synopsys, Inc. SolvNet 33

1.1 General Product Description

Figure 1-1 DWC_hdmi_tx in System on Chip Example

MIPI DigRF PCIe USB Link HDMI

34 SolvNet Synopsys, Inc. Version 2.12a

1.1.2 Standards Compliance

1.1.3 Unsupported Features and Exceptions

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1.1.4 HDMI Operational Model Overview

Figure 1-2 HDMI Block Diagram

TMDS Channel 0 Video