Analog Crash Course Workbook Ga

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Q.1 The function of the following circuit if the input is a sine wave
R
+ +
D1 D2
Vi V0
8V 4V
– –
(A) Transmits that part of sine wave, which is above + 8 V and below + 4 V.
(B) Transmits that part of sine wave, which lies between + 4 V and + 8 V.
(C) Transmit that part of sine wave, which lies above – 4 V and below + 8 V.
(D) Transmit that part of sine wave, which lies below + 4 V and above – 8 V.
Q.2 Two silicon diodes with a forward voltage drop of 0.7 V are used in the circuit shown in the figure. The
range of input voltage Vi for which the output voltage V0 = Vi , is
R
D1 D2
Vi V0
-1V +- +
- 2V
(A) − 0.3 V < Vi < 1.3 V (B) − 0.3 V < Vi < 2.0 V
(C) − 1.0 V < Vi < 2.0 V (D) −1.7 V < Vi < 2.7 V
Q.3 The equivalent circuits of a diode, during forward biased and reverse biased conditions, are shown in the
figure.
10 kΩ
0.7 V Rf
10sin wt V0 10 kΩ
5V
Fig. (a) Fig. (b)

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If such a diode is used in clipper circuit of figure given above, the output voltage (V0 ) of the circuit will
be
(A) (B)
+5 V +10 V
0 p 2p wt 0 p 2p wt
-5.7 V
-5 V
(C) (D)
+5.7 V +5.7 V
0 p 2p wt 0 p 2p wt
-10 V -5 V
Q.4 For the circuit with ideal diodes shown in the figure, the shape of the output (Vout ) for the given sine wave
input (Vin ) will be
+
+
0 0.5 T T Vin V out
−
−
(A) (B)
0 0.5 T T 0 0.5 T T
(C) (D)
0 0.5 T T
0 0.5 T T
Q.5 Assuming the diodes to be ideal in the figure, for the output to be clipped, the input voltage Vi must be
outside the range
10 kW
D1 D2
Vi 10 kW V0
1V 2V
(A) – 1 V and – 2 V (B) – 2 V to – 4 V (C) + 1 V to – 2 V (D) + 2V to – 4 V

Q.6 For the circuit shown below, assume that the Zener diode is ideal with a breakdown voltage of 6 volts.
The waveform observed across R is

6V
12sin wt ~ R VR
6V
6V
(A) (B)
-12 V
12 V
(C) (D)
-6 V
-6 V
Q.7 For the circuit shown below, vi is a sinusoidal voltage of 60 V.
+ 20 k 15 k +
D1 D2
Vi V0
15 V 35 V
– –
Assuming ideal diodes, the output waveform is given by

(A) (B)
V0 V0
60V 60V
35 V 35 V
15V
t t
−6 0 V −6 0 V
(C) (D)
V0
60 V V0
60V
t
– 15 V t
– 60 V
−6 0 V
Q.8 In the question a circuit and a waveform for the input voltage is given. The diode in circuit has cutin
voltage Vγ = 0. Choose the option for the waveform of output voltage v0 .

vi
20
2.2 kW
t vi v0
5V
-5
v0 vi
(A) (B)
15 20
t t
-10 -5
vi vi
(C) (D)
20 20
5
t t
Q.9 If the circuit shown has to function as a clamping circuit then which one of the following conditions should
be satisfied for the sinusoidal signal of period T ?
C
V ~ R
(A) RC << T (B) RC = T (C) RC = 0.35T (D) RC >> T

Q.10 The circuit shown in the figure is best described as a
Output
Vi ~
(A) bridge rectifier (B) ring modulator

(C) frequency discriminatory (D) voltage doubler
Q.11 The diodes and capacitors in the circuit shown are ideal. The voltage v(t) across the diode D1 is
C1
v(t ) D2
+
cos(wt ) D1 C2
-
(A) cos(ωt ) − 1 (B) sin(ωt ) (C) 1 − cos(ωt ) (D) 1 − sin(ωt )

Q.12 In the circuit shown, assume that diodes D1 and D2 are ideal. In the steady-state condition, the average
voltage V ab (in Volts) across the 0.5 μF capacitor is ______.
1 μF
D1 D2
50 sin ωt ~
0.5 μF
b a
Vab
Q.13 What will be the voltage reading of DC Voltmeter placed across the terminals of the Diode in the circuit
below,
− DC +
voltmeter
D1
Vi ( t) R L = 50 Ω
1: 2
having the following periodical input signal Vi (t )

+Vm
( + 5.2 V)
π 3π/2 2π
0
π/2
−Vm
( − 5.2V)
(Assume cut-in voltage of the Diode = 0 V; Forward resistance of the Diode = 2 Ω)
(A) 1.25 V (B) 2.5 V (C) 0 V (D) 0.1 V
Q.14 The output voltage V0 for the clamper circuit shown below is
Vi C
15 V 1μF
Vin 100 kW V0
t
t1 t2 t3 t4 4V
- 25 V
(A) V0 (B) V0
44 V 44 V
4V 4V
t t
t1 t2 t3 t4 t1 t2 t3 t4

(C) V0 (D) V0
4V 15 V
t 4V
t1 t2 t3 t4 t5
t
- 36 V t1 t2 t3 t4
Q.15 In the figure, the ideal moving iron voltmeter M will read
M
Ideal diode
10sin 314t 100 mF
(A) 7.07 V (B) 12.24 V (C) 14.214 V (D) 20.0 V

Q.16 In the circuit shown below, the average value of V0 (t ) will be
Vm sin wt V0 (t )
(A) 0 (B) − Vm / π (C) − Vm / 2 (D) − Vm

Q.17 The voltage V0 for the network given below is
12 V
Vγ = 0.7 V Si Ge Vγ = 0.3V
V0
2.2 kΩ
(A) 11.7 V (B) 11.3 V (C) 11 V (C) None of these

Q.18 In the circuit shown below diodes has cut-in voltage of 0.6 V. The diode in ON states are
D1 12Ω 6Ω D2
5.4V 18 Ω 5V
(A) Only D1 (B) Only D2

(C) Both D1 and D2 (D) None of these

Q.19 Assume that D1 and D2 in figure are ideal diodes. The value of current I is
D1 2 kΩ
1mA
(DC)
I
2 kΩ
D2
(A) 0 mA (B) 0.5 mA (C) 1 mA (D) 2 mA

Q.20 In the circuit below, the diode is ideal. The voltage V is given by
V
1W 1W
Vi D 1A
(A) min ( Vi ,1) (B) max ( Vi ,1) (C) min ( −Vi ,1) (D) max ( − Vi ,1)
Q.21 The diode in the circuit shown has Von = 0.7 V but is ideal otherwise. If Vi = 5sin(ωt )V , the minimum
and maximum values of V0 (in Volts) are, respectively,
1kW
Vi V0
R1
R2 1kW
+ 2V
-
(A) –5 and 2.7 (B) 2.7 and 5 (C) –5 and 3.85 (D) 1.3 and 5
Q.22 In the circuit shown in below figure. The value of e0 is ____________V.
D1
D2
D3
1.5 V +
- e3
5V +
- e2
+
1V +
- e1 e0
2V -
Q.23 In the circuit shown in below figure. The value of I2 is _______________mA.

3 kΩ Ge
0.2V
+10 V V0
Si
I2 1kΩ
0.7 V
Q.24 For the circuit in the figure below. The values of I D and VD are
+8V +4V
10 kW ID 10 kW
VD
10 kW 10 kW
(A) 0 A, 2.5 V (B) 2.5 mA, – 2 V

(C) 0 A, – 2 V (D) 4.5 mA, 2.5 V
Q.25 For the circuit shown the range of I L such that Zener diode is in break down condition is ______________
mA. (Assume I Z max = 32 mA)
1kΩ
R
IL
50 V
10 V RL
Q.26 A Zener diode in the circuit shown in the figure is has a knee current of 5 mA and a maximum allowed
power dissipation of 300 mW. What are the minimum and maximum load currents that can be drawn
safely from the circuit, keeping the output voltage V0 constant at 6 V?
50 Ω
L
O V0
9V 6V A
– D
(A) 0 mA, 180 mA (B) 5 mA, 110 mA

(C) 10 mA, 55 mA (D) 60 mA, 180 mA
Q.27 In the voltage regulator shown in the figure, the load current can vary from 100 mA to 500 mA. Assuming
that the Zener diode is ideal (i.e., the Zener knee current is negligibly small and Zener resistance is zero
in the breakdown region), the value of R is

12 V 5V Variable 100
to 500 mA
70
(A) 7 Ω (B) 70 Ω (C) Ω (D) 14 Ω
3
Q.28 In the circuit shown below, the knee current of the ideal Zener diode is 10 mA. To maintain 5 V across RL ,
the minimum value of RL in Ω and the minimum power rating of the Zener diode in mW, respectively, are
100 W
I Load
10 V
VZ = 5 V RL
(A) 125 and 125 (B) 125 and 250 (C) 250 and 125 (D) 250 and 250
20
Q.29 The sinusoidal AC source in the figure has an rms value of V . Considering all possible values of RL
2
, the minimum value of Rs in Ω to avoid burnout of the Zener diode is _________.
Rs
20 5V
V RL
2 1/4 W
Q.30
The correct waveform for output ( V0 ) for the above network is:
(A) (B)

(C) (D)
Q.31 In a two diode FWR circuit, the voltage across each half of the transformer secondary is 100 V. The load
resistance is 950 Ω and each diode has a forward resistance of 50 Ω . The load rms value of the input
current is ____________ Amp.
Q.32 A diode with VF = 0.7 V is connected as a half wave rectifier. The load resistance is 600 Ω and the (rms)
ac input is 24 V . The diode reverse voltage is __________ V.
Q.33 When a junction diode is used as a half-wave rectifier with purely resistive load and sinusoidal input
voltage, what is the value of diode conduction angle (where φi is the ignition angle corresponding to the
cut-in voltage)?
(A) π (B) π − φi
(C) π − 2φi (D) Slightly greater than π
Q.34 Compute the ripple factor of a single phase full wave rectifier with load resistance RL = 10 kΩ . Forward
bias dynamic resistance of diodes used is 100 Ω . The rms voltage across secondary winding is 330 V
(A) 4.82 (B)1.21 (C) 0.482 (D) 0.812
Q.35 Assume that the operational amplifier in figure is ideal the current I through the 1 kΩ resistor is
_____________.
2 kW
2 mA 1 kW
2 kW
Q.36 The approximate input impedance of the Op - Amp circuit shown in given figure is
100 kW
10 kW
V0
Vi
10 kW
(A) Infinite (B) 120 kΩ (C) 110 kΩ (D) 10 kΩ

Q.37 The Op-Amp of figure shown below has a very poor open loop voltage gain of 45 but is otherwise ideal.
The gain of the amplifier equals
8 kW
2 kW
Vout
Vin
(A) 5 (B) 20 (C) 4 (D) 4.5

Q.38 Assuming the operational amplifier to be ideal, the gain Vout / Vin for the circuit shown in the given figure
is
10 kW 10 kW
1 kW
1 kW _
Vin
Vout
+
(A) –1 (B) – 20 (C) – 100 (D) – 120

Q.39 The input resistance RIN ( = Vx / ix ) of the circuit in figure is
R1 = 10 kΩ R2 = 100 kW
_
Vy
+
Vx
ix R3 = 1 MW
(A) +100 kΩ (B) −100 kΩ (C) +1 MΩ (D) −1 MΩ

V 
Q.40 The gain  0  of the amplifier circuit shown in below figure is
 Vi 
R 3R
_
+ RL
+
RL V0
R 4R _
_
Vi
+
3R L
(A) 8 (B) 4 (C) – 4 (D)
R

Q.41 The input resistance of the circuit shown in the figure, assuming an ideal Op-Amp is
2R
R 3R
Vi
_
+ V0
R 2R 4R
(A) (B) (C) R (D)
3 3 3
Q.42 Assuming that the Op-Amp in the circuit shown below is ideal, the output voltage V0 (in volts) is ____.
2 kΩ
+12 V
1 kΩ -
V0
+
1V -12 V
Q.43 For the circuit shown below, assume that the Op-Amp is ideal.
R
R R
R
–
+ v0
2R
vs
2R
Which one of the following is TRUE?
(A) v0 = vs (B) v0 = 1.5 vs (C) v0 = 2.5 vs (D) v0 = 5 vs
Q.44 In the circuit shown, assume that the Op-Amp is ideal. The bridge output voltage V0 (in mV) for δ = 0.05
is______________.
100W
+ 1V
-
250(1 + d)Ω 250(1 - d)Ω
- +
V0
250(1 - d)Ω 250(1+d)Ω
100W 50W

Q.45 If the input to the ideal comparator shown in the figure is a sinusoidal signal of 8V (peak to peak) without
any DC component, then the output of the comparator has a duty cycle of
Input
Output
Vref = 2 V
1 1
(A) (B)
2 3
1 1
(C) (D)
6 12
Q.46 Given the ideal operational amplifier circuit shown in the figure indicate the correct transfer characteristics
assuming ideal diodes with zero cut-in voltage.
+10 V
Vi _
V0
+
- 10 V
2 kΩ
0.5 kΩ
2 kΩ
V0 V0
+ 10 V +10 V
(A) –8 V +5 V
Vi (B) –5 V +8V
Vi
–10 V –10 V
V0
+5 V V0
+ 10 V
(C) –5 V +5 V
Vi (D)
–5 V +5 V
Vi
–10 V –5V
. Statement for Linked Answer Questions 47 and 48 .
In the Schmitt trigger circuit shown below, the Zener diodes have VZ (reverse saturation voltage) = 6 V
and VD (forward voltage drop) = 0.7 V.

+12 V
+ - R
Vi +
- + Vo
R1 -
-12 V
R2
+1.5 V
R1
Q.47 If the circuit has the input lower trip point (LTP) = 0 V, then value of is given as
R2
(A) 0.223 (B) 2.67 (C) 4.67 (D) ∞
Q.48 The input upper trip point (UTP) of the Schmitt trigger is
(A) 1.5 V (B) 2.1 V (C) 2.42 V (D) 6.7 V
Q.49 The components in the circuit shown below are ideal. If the op-amp is in positive feedback and the input
voltage Vi is a sine wave of amplitude 1 V, the output voltage V0 is
1kΩ
1V 1kΩ +5V
0 Vi
−1V V0
−5 V
(A) a constant of either +5V or –5V. (B) a non-inverted sine wave of 2 V amplitude.
(C) an inverted sine wave of 1 V amplitude. (D) a square wave of 5 V amplitude.
Q.50 An oscillator circuit using ideal Op-Amp and diodes is shown in the figure.
R
+5V
V0
C -5V
D1
3kW
1kW
D2
1kW
The time duration for +ve part of the cycle is Δ t1 and for –ve part is Δ t 2 .
Δt1 − Δt2
The value of e RC
will be ________.

Q.51 The saturation voltage of the ideal Op-Amp shown below is ±10 V. The output voltage V0 of the following
circuit in the steady-state is
1 kW
+10 V
0.25 mF
V0
2 kW
-10 V
2 kW
(A) Square wave of period 0.55 ms (B) Triangular wave of period 0.55 ms
(C) Square wave of period 0.25 ms (D) Triangular wave of period 0.25 ms
Q.52 The switch S in the circuit of the figure is initially closed. It is opened at time t = 0. You may neglect the
Zener diode forward voltage drops. What is the behavior of Vout for t > 0 ?
+10 V +10 V
_
1 kΩ
Vout
S + + 10 kΩ 5.0 V
0.01
mF –10 V 5.0 V
100 kΩ
–10 V
(A) It makes a transition from – 5 V to + 5 V at t = 12.98μs
(B) It makes a transition from – 5 V to + 5 V at t = 2.57 μs
(C) It makes a transition from + 5 V to – 5 V at t = 12.98μs
(D) It makes a transition from + 5 V to – 5 V at t = 2.57 μs
Q.53 In the circuit shown in below figure, if Vi = sin t , the voltage V0 is
10 kW 10 kW
V0
100 kW
Vi 10 mF
 π 1  π
(A) 2 sin  t −  (B) sin  t + 
 4 2  4
1  π  π
(C) sin  t −  (D) 2 sin  t + 
2  4  4
Q.54 In the circuit shown in the given figure, V0 is given by

10 kW 4.14 kW
1MW V0
sin t
1mF
 π  π
(A) sin  t −  (B) sin  t + 
 4  4
(C) sin t (D) cos t
Q.55 For the circuit shown, with an ideal operational amplifier, the maximum phase shift of the output Vout with
reference to the input Vin is
R1
R1
_
Vin Vout
+
R
C
(A) 00 (B) −900 (C) + 900 (D) ± 1800

Q.56 The circuit in below figure is a
1 1
(A) band-pass filter with lower cut-off ωl = and higher cut-off ωH = .
R1 C1 R2 C2
1 1
(B) band-reject filter with lower cut-off ωl = and higher cut-off ωH = .
R1 C1 R2 C2
1 1
(C) band-pass filter with lower cut-off ωl = and higher cut-off ωH = .
R2 C2 R1 C1
1 1
(D) band-reject filter with lower cut-off ωl = and higher cut-off ωH = .
R2 C2 R1 C1

Q.57 Consider the Op-Amp circuit shown in the figure.

R
R _
Vi V0
+
C
R
The transfer function V0 (s) / Vi (s) is

1 − sRC 1 + sRC 1 1
(A) (B) (C) (D)
1 + sRC 1 − sRC 1 − sRC 1 + sRC
. Statement for Linked Answer Questions 58 and 59 .
A general filter circuit is shown in the figure.
R2
R1 C
_
Vi V0
R3 +
R4
Q.58 If R1 = R2 = RA and R3 = R4 = RB , the circuit acts as a

(A) All pass filter (B) Band pass filter (C) High pass filter (D) Low pass filter
Q.59 The output of the filter is given to the circuit shown in below figure
The gain vs frequency characteristic of the output (V0 ) will be

(A) (B)
Gain Gain
0 w 0 w
(C) (D)
Gain Gain
0 w 0 w

Q.60 The Op-Amp shown in the figure has a finite gain A = 1000 and an infinite input resistance. A step-voltage
Vi = 1mV is applied at the input at time t = 0 as shown. Assuming that the operational amplifier is not
saturated, the time constant (in millisecond) of the output voltage V0 is
C
1mF
R
-
1kW
+
1mV + Vi +
- V0
A = 1000
-
t = 0s
(A) 1001 (B) 101 (C) 11 (D) 1

Q.61 The operational amplifier shown in the figure is ideal. The input voltage (in Volt) is Vi = 2sin(2π× 2000t )
.The amplitude of the output voltage V0 (in Volt) is _______.
0.1mF
1 kW
1 kW
Vi -
V0
+
Q.62 The filters F1 and F2 having characteristics as shown in figure (a) and (b) are connected as shown in
figure (c).
F1 F2
V0 V0
Vi Vi
Vi V0 Vi V0
f f
f1 f2
(a) (b)
R
2
+Vsat
R
F1 –
Vi +
V0
F2 -Vsat
R
(c)
The cut-off frequencies of F1 and F2 are f1 and f 2 respectively. If f1 < f 2 , the resultant circuit exhibits
the characteristic of a
(A) Band-pass filter (B) Band-stop filter (C) All pass filter (D) High-Q filter
Q.63 For the circuit shown in the following figure, the capacitor C is initially uncharged. At t = 0 the switch S
is closed. The voltage VC across the capacitor at t = 1msec is
S C = 1μF
_V
c +
1 kW
_
V0
+
10 V
In the figures shown the OP-AMP is supplied with ± 15 V .

(A) 0 V (B) 6.3 V (C) 9.45 V (D) 10 V
Q.64 The approximate transfer characteristic for the circuit shown below with an ideal operational amplifier
and diode will be
Vss
Vin +
D
–Vss
V0
(A) V0 (B) V0 (C) V0 (D) V0
Vin Vin Vin Vin
Q.65 The transfer characteristic of the Op-Amp circuit shown in figure is

R
R +Vsat R
Vi –
R +Vsat
–
+
-Vsat + V0
R -Vsat
R
V0 V0
(A) (B)
-1 1
Vi Vi

(C) V0 (D) V0
Vi Vi
1
-1
Q.66 The transfer characteristic for the precision rectifier circuit shown below is (assume ideal Op-Amp and
practical diodes)
+ 20 V R
4R D2
Vi _
R V0
+ D1
(A) V0 (B) V0
10
Vi Vi
– 10 – 5 0 – 10 – 5 0
(C) V0 (D) V0
10
Vi Vi
0 5 0 5
Q.67 The block diagrams types of half wave rectifiers are shown in the figure. The transfer characteristics of
the rectifiers are also shown within the block.
P Q
v0 v0
vin v0 vin v0
0
vin
0 vin
It is desired to make full wave rectifier using above two half-wave rectifiers. The resultant circuit will be
(A) R (B) R
Vin R
Vin R _ P
_
P
V0 V0
R
R + QP +
Q R

(C) R (D) R R
Vin R _
Q _
V0 V0
R Vin R
PP + P +
R
R
Q
Q.68 In the circuit shown, the Op-Amp has finite input impedance, infinite voltage gain and zero input offset
voltage. The output voltage Vout is
R2
R1 I1
Vout
I2
(A) − I 2 ( R1 + R2 ) (B) I 2 R2 (C) I1R2 (D) − I1 ( R1 + R2 )
Q.69 For the Op-Amp shown in the figure, the bias currents are I b1 = 450 nA and I b 2 = 350 nA .The values of
the input bias current ( I B ) and the input offset current ( I f ) are
Ib1
–
+
Ib2
(A) I B = 800 nA, I f = 50nA (B) I B = 800 nA, I f = 100nA
(C) I B = 400 nA, I f = 50nA (D) I B = 400 nA, I f = 100nA
Q.70 The output of an Op-Amp whose input is a 2.5 MHz square wave is shown in below figure. The slew
rate of the Op-Amp is
V0
4V
-4V
0.4 ms
(A) 0.8 V/ μs (B) 8.0 V/ μs (C) 20.0 V/ μs (D) 40.0 V/ μs

Q.71 An ideal OP-AMP is used to realize a difference amplifier circuit given below having a gain of 10. If
x = 0.025, the CMRR of the circuit in dB is ________

100(1 + x) kW
10(1 - x)kW
V1
10(1 + x) kW V0
V2
100(1 - x) k W
Q.72 The output voltage V0 in the circuit in below figure is

+V
R2
R1 R1
_ _
V0
+ R (1 + d ) R +
R2 R2 R2 R2
(A) Vδ (B) Vδ (C) V (D) V
R R1 R1δ R (1 + δ )
Q.73 For a given sinusoidal input voltage, the voltage waveform at point P of the clamper circuit shown in
figure will be
+12V
Vin C _
RL
t + P
+
_ Vin
~
-12V
V V
(A) (B) t
V V
(C) (D)
12 V 0.7 V
t
t
-0.7 V -12 V
Q.74 Assume that the β of the transistor is extremely large and VBE = 0.7 V, IC and VCE in the circuit shown in
figure are
5V
4 kW IC 2.2 kW
+
VCE
–
1kW 300 W
(A) I C = 1mA, VCE = 4.7 V (B) I C = 0.5 mA, VCE = 3.75 V

(C) I C = 1mA, VCE = 2.5 V (D) I C = 0.5 mA, VCE = 3.9 V
Q.75 In the following circuit, the transistor is in active mode and VC = 2 V. To get VC = 4 V, we replace RC with
RC' . Then the ratio RC' / RC is ________.
+ 10 V
RC
RB VC
Q.76 In the circuit shown below, the silicon npn transistor Q has a very high value of β . The required value of
R2 in kΩ to produce IC = 1 mA is
VCC = 3V
IC
R1 60 kW
R2
RE 500 W
(A) 20 (B) 30 (C) 40 (D) 50

Q.77 If the transistor in figure has high value of β and VBE of 0.65 the current I flowing through the 2 kΩ
resistance will be __________mA.

I
6.5 kW 2 kW
1.85 kW 10 V
1.65 kW
1 kW
Q.78 Consider the circuit shown in the figure. Assuming VBE1 = VEB2 = 0.7 V, the value of the dc voltage VC2
(in volt) is __________.
VCC = 2.5 V
b1 = 100
Q1 Q2
b2 = 50
10 kW
VC 2
1V
1 kW
Q.79 In the circuit shown, the PNP transistor has VBE = 0.7 V and β = 50 . Assume that RB = 100kΩ . For V0 to
be 5 V, the value of RC (in kΩ ) is ____________.
RC
V0
RB
VEE = 10 V

Q.80 In the circuit shown below, VBE = 0.7 V .
The β of the transistor and VCE are, respectively

(A) 19 and 2.8 V (B) 19 and 4.7 V
(C) 38 and 2.8 V (D) 38 and 4.7 V
Q.81 The common emitter forward current gain of the transistor shown is βF = 100
The transistor is operating in

(A) Saturation region (B) Cut-off region
(C) Reverse active region (D) Forward active region
Q.82 The transistor used in the circuit shown below has a β of 30 and ICBO is negligible
2.2 kW
15 kW
1 kW D VBE = 0.7 V
VCE (sat) = 0.2 V
Vz = 5V
–12 V
If the forward voltage drop of diode is 0.7 V, then the current through collector will be
(A) 168 mA (B) 108 mA
(C) 20.54 mA (D) 5.36 mA
Q.83 For the BJT Q1 in the circuit shown below, β = ∞ , VBE ( on ) = 0.7 V , VCE ( sat ) = 0.7 V . The switch is initially
closed. At time t = 0 , the switch is opened . The time t at which Q1 leaves the active region is

(A) 10 ms (B) 25 ms (C) 50 ms (D) 100 ms

Q.84 Two perfectly matched silicon transistors are connected as shown in the figure. Assuming the β of the
transistors to be very high and the forward voltage drop in diodes to be 0.7 V, the value of current I is
(A) 0 mA (B) 3.6 mA (C) 4.3 mA (D) 5.7 mA

Q.85 The three transistors in the circuit shown below are identical with VBE = 0.7 V and β = 100 . The voltage
V0 is
2V 10 V
1kW
1kW
V0
(A) 0.2 V (B) 2 V (C) 7.4 V (D) 10 V

Q.86 The matched transistors Q1 and Q2 shown in the adjoining figure have β =100. Assuming the base-emitter
voltages to be 0.7 V, the collector-emitter voltage V2 of the transistor Q2 is
12 V 50 V
10 kW 20 kW
Q1 Q2
V2
–
(A) 33.9 V (B) 27.8 V (C) 16.2 V (D) 0.7 V
Q.87 In the silicon BJT circuit shown below, assume that the emitter area of transistor Q1 is half that of
transistor Q2 .
R = 9.3kW I0
Q1 Q2
(b1 = 700) 0.7 V (b2 = 715)
-10 V
The value of current I0 is approximately

(A) 0.5 mA (B) 2 mA (C) 9.3 mA (D) 15 mA
. Statement for Linked Question 88 and 89 .
In the following transistor circuit, VBE = 0.7 V , re = 25m V / I E , β and all the capacitance are very large.
VCC = 9 V
3 kW
20 kW
CC1 CC 2
IE 3 kW
10 kW
2.3 kW CE
Q.88 The Value of DC current I E is

(A) 1 mA (B) 2 mA (C) 5 mA (D) 10 mA
Q.89 The mid-band voltage gain of the amplifier is approximately
(A) –180 (B) –120 (C) –90 (D) –60
Q.90 An amplifier circuit is shown is below. Assume that the transistor works in active region. The low
frequency small-signal parameters for the transistor are g m = 20 mS , β0 = 50 , r0 = ∞ , rb = 0
VCC
1kW
+
~V i V0
2 kW

V 
What is the voltage gain AV =  0  of the amplifier?
 Vi 
(A) 0.967 (B) 0.976 (C) 0.983 (D) 0.998
Q.91 For the DC analysis of the Common-Emitter amplifier shown, neglect the base current and assume that
the emitter and collector currents are equal. Given that VT = 25 mV, VBE = 0.7 V, and the BJT output
resistance r0 is practically infinite. Under these conditions, the midband voltage gain magnitude
V0 V
Av = , is _________.
Vi V
VCC = 12 V
RC 2 kW
73 kW R1 10 mF
10 mF C2
C1
RL = 8 kW V0
Vi 47 kW R2
RE 2 kW CE = 100 mF
Q.92 The feedback used in the circuit shown figure can be described as
VCC
RC
RF C=a
V0
C
RL
RS RB
CE
(A) Shunt - Series feedback (B) Shunt - Shunt feedback

(C) Series - Shunt feedback (D) Series - Series feedback
Q.93 The feedback topology in the amplifier circuit (the base bias circuit is not shown for simplicity) in the
figure is
VCC
RC Io
vo
RS
RE
va

(A) Voltage shunt feedback (B) Current series feedback

(C) Current shunt feedback (D) Voltage series feedback
Q.94 The enhancement type MOSFET in the circuit below operates according to the square law.
μ n Cox = 100 μA/V 2 , the threshold voltage (VT ) is 500 mV. Ignore channel length modulation. The output
voltage Vout is
VDD = 2V
5 mA
Vout
W 10 mm
=
L 1 mm
(A) 500 mV (B) 600 mV (C) 100 mV (D) 2 V

Q.95 Using the incremental low frequency small - signal model of the MOS device, the Norton equivalent
resistance of the following circuit is
VDD
g m , rds
rds + R 1
(A) rds + R (B) (C) rds + R + g m rds R (D) rds + +R
1 + g m rds gm
Q.96 The parameters of the JFET are g m = 1 mA/V , rd = 15 kΩ . Neglecting effect of the capacitor for AC
analysis the AC signal voltage gain for the circuit is
12 V
60 kW
+
C
+
60 kW V0
~ Vi
-
VGG
-
(A) – 30 (B) – 10 (C) 4 (D) 60

Q.97 A voltage amplifier is constructed using enhancement mode MOSFETs labeled M1 , M 2 , M 3 and M 4 in
the figure below. M1 , M 2 and M 4 are n-channel MOSFETs and M 3 is a p-channel MOSFET. All
MOSFETs operate in saturation mode and channel length modulation can be ignored. The low frequency,
small signal input and output voltages are vin and vout respectively and the dc power supply voltage is
VDD . All n-channel MOSFETs have identical transconductance gmn while the p-channel MOSFET has
transconductance g mp . The expressions for the low frequency small signal voltage gain vout / vin is
VDD
M1 M3
Vout
Vin M2 M4
g mn g mn
(B) − g mn ( g mn + g mp ) (D) g mn ( g mn + g mp )
−1 −1
(A) − (C) +
g mp g mp
μ n CoxW
Q.98 Consider a MOSFET amplifier shown in the below figure, if λ = 0.1 Volt −1 and = 100 μA/V 2 .
L
10 V
10 K
C
V0
Io ut
10 K
1 kΩ I in
VS
I out
The current gain = AI is given by
I in
(A) 0.5 (B) 1.0 (C) 0 (D) None of the above
Q.99 Consider source follower MOSFET amplifier shown in the below figure with r0 = 100 kΩ, g m = 1 mS .
10 V
V0
VS 1 MΩ
1 kΩ
R0
−10 V
The value of R0 is ____________ Ω .
Q.100 In the circuit shown in the figure, the channel length modulation of all transistors is non-zero (λ ≠ 0).
Also, all transistors operate in saturation and have negligible body effect. The ac small signal voltage
gain (V0 /Vin ) of the circuit is
VDD
M3 M2
VG
V0
Vin M1
  1  
(A) − g m1 (r01 r02 r03 ) (B) − g m1  r01   r03 
  g m3  
  1     1  
(C) − g m1  r01   r02 r03  (D) − g m1  r01   r03 r02 
  g m 2     g m3  


ANSWERS
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Fig. (a) Fig. (b)

(A) – 1 V and – 2 V (B) – 2 V to – 4 V (C) + 1 V to – 2 V (D) + 2V to – 4 V

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Q.7 For the circuit shown below, vi is a sinusoidal voltage of 60 V.

Assuming ideal diodes, the output waveform is given by

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(A) RC << T (B) RC = T (C) RC = 0.35T (D) RC >> T

(A) bridge rectifier (B) ring modulator

(A) cos(ωt ) − 1 (B) sin(ωt ) (C) 1 − cos(ωt ) (D) 1 − sin(ωt )

having the following periodical input signal Vi (t )

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(A) 7.07 V (B) 12.24 V (C) 14.214 V (D) 20.0 V

(A) 0 (B) − Vm / π (C) − Vm / 2 (D) − Vm

(A) 11.7 V (B) 11.3 V (C) 11 V (C) None of these

(A) Only D1 (B) Only D2

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(A) 0 mA (B) 0.5 mA (C) 1 mA (D) 2 mA

Q.23 In the circuit shown in below figure. The value of I2 is _______________mA.

(A) 0 A, 2.5 V (B) 2.5 mA, – 2 V

(A) 0 mA, 180 mA (B) 5 mA, 110 mA

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(A) Infinite (B) 120 kΩ (C) 110 kΩ (D) 10 kΩ

(A) 5 (B) 20 (C) 4 (D) 4.5

(A) –1 (B) – 20 (C) – 100 (D) – 120

(A) +100 kΩ (B) −100 kΩ (C) +1 MΩ (D) −1 MΩ

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250(1 - d)Ω 250(1+d)Ω

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Q.54 In the circuit shown in the given figure, V0 is given by

(A) 00 (B) −900 (C) + 900 (D) ± 1800

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Q.57 Consider the Op-Amp circuit shown in the figure.

The transfer function V0 (s) / Vi (s) is

Q.58 If R1 = R2 = RA and R3 = R4 = RB , the circuit acts as a

The gain vs frequency characteristic of the output (V0 ) will be

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(A) 1001 (B) 101 (C) 11 (D) 1

In the figures shown the OP-AMP is supplied with ± 15 V .

(A) V0 (B) V0 (C) V0 (D) V0

Vin Vin Vin Vin

Q.65 The transfer characteristic of the Op-Amp circuit shown in figure is

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(A) − I 2 ( R1 + R2 ) (B) I 2 R2 (C) I1R2 (D) − I1 ( R1 + R2 )

(A) I B = 800 nA, I f = 50nA (B) I B = 800 nA, I f = 100nA

(C) I B = 400 nA, I f = 50nA (D) I B = 400 nA, I f = 100nA

(A) 0.8 V/ μs (B) 8.0 V/ μs (C) 20.0 V/ μs (D) 40.0 V/ μs

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Q.72 The output voltage V0 in the circuit in below figure is

(A) I C = 1mA, VCE = 4.7 V (B) I C = 0.5 mA, VCE = 3.75 V

(A) 20 (B) 30 (C) 40 (D) 50

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