AS384x

SEMICONDUCTOR Current Mode Controller

Features Description
• 2.5 V bandgap reference trimmed to The AS3842 family of control ICs provide pin-for-pin replacement of the
1.0% and temperature-compensated industry standard UC3842 series of devices. The devices are
redesigned to provide significantly improved tolerances in power supply
• Standard temperature range extended manufacturing. The 2.5 V reference has been trimmed to 1.0%
to 105°C tolerance. The oscillator discharge current is trimmed to provide guar-
anteed duty cycle clamping rather than specified discharge current. The
• AS3842/3 oscillations trimmed for
circuit is more completely specified to guarantee all parameters impact-
precision duty cycle clamp
ing power supply manufacturing tolerances.
• AS3844/5 have exact 50% max duty
In addition, the oscillator and flip-flop sections have been enhanced to
cycle clamp
provide additional performance. The RT/CT pin now doubles as a syn-
• Advanced oscillator design simplifies chronization input that can be easily driven from open collector/open
synchronization drain logic outputs. This sync input is a high impedance input and can
easily be used for externally clocked systems. The new flip-flop topol-
• Improved specs on UVLO and ogy allows the duty cycle on the AS3844/5 to be guaranteed between
hysteresis provide more predictable 49 and 50%. The AS3843/5 requires less than 0.5 mA of start-up cur-
start-up and shutdown rent over the full temperature range.
• Improved 5 V regulator provides better
AC noise immunity
• Guaranteed performance with current
sense pulled below ground

Pin Configuration — Top view

PDIP (N) 8L SOIC (8D) 14L SOIC (14D)

COMP 1 8 VREG COMP 1 8 VREG COMP 1 14 VREG

VFB 2 7 VCC VFB 2 7 VCC NC 2 13 NC

ISENSE 3 6 OUT ISENSE 3 6 OUT VFB 3 12 VCC

RT/CT 4 5 GND RT/CT 4 5 GND NC 4 11 VC

ISENSE 5 10 OUT

NC 6 9 PWR GND

RT/CT 7 8 GND

Ordering Information
AS384X 8D N
Circuit Type: Packaging Option:
Current Mode Controller (See Table A) N = Tape and Reel (13" Reel Dia)
T = Tube
Table A
Package Style
8D = 8 Pin Plastic SOIC Duty Cycle
14D = 14 Pin Plastic SOIC Model VCC(min) VCC(on) Typ. ICC
N = 8 Pin Plastic DIP AS3842 10 16 97% 0.5 mA
AS3843 7.6 8.4 97% 0.3 mA
AS3844 10 16 49.5% 0.5 mA
AS3845 7.6 8.4 49.5% 0.3 mA

www.ptcc.com.tw 61
This datasheet has been downloaded from http://www.digchip.com at this page
AS384x Current Mode Controller

Functional Block Diagram

(5.0 V)
5V (5.0 V)
REGULATOR 8
1
(2.5 V) VREG
COMP
REF OK
7
+ VCC
(4 V)
2 –
2R
VFB ERROR AMP UVLO
(1.0 V) (6 V)
R

PWM FF
–
COMPARATOR S PWM LOGIC
+
R 6
3 OUTPUT
(5 V)
CURRENT
SENSE
–
(3.0 V) CLK ÷ 2 [3844/45]
+
–
4 FF CLK [3842/43] 5
+
(1.3 V)
RT/CT S GND
– FF
R
+ T
(0.6 V)
OSCILLATOR

OVER
TEMPERATURE

Figure 1. Block Diagram of the AS3842/3/4/5

Pin Function Description

Pin Number Function Description
1 COMP This pin is the error amplifier output. Typically used to provide loop compensation to
maintain VFB at 2.5 V.
2 VFB Inverting input of the error amplifier. The non-inverting input is a trimmed 2.5 V
bandgap reference.
3 Current A voltage proportional to inductor current is connected to the input. The PWM uses
Sense this information to terminate the gate drive of the output.
4 RT/CT Oscillator frequency and maximum output duty cycle are set by connecting a resistor
(RT) to VREG and a capacitor (CT) to ground. Pulling this pin to ground or to VREG will
accomplish a synchronization function.
5 GND Circuit common ground, power ground, and IC substrate.
6 Output This output is designed to directly drive a power MOSFET switch. This output can sink
or source peak currents up to 1A. The output for the AS3844/5 switches at one-half
the oscillator frequency.
7 VCC Positive supply voltage for the IC.
8 VREG This 5 V regulated output provides charging current for the capacitor CT through the
resistor RT.

www.ptcc.com.tw 62
AS384x Current Mode Controller

Electrical Characteristics (cont’d)

Electrical characteristics are guaranteed over full junction temperature range (0 to 105°C). Ambient temperature must be derated
based on power dissipation and package thermal characteristics. The conditions are: VCC = 15 V, RT = 10 kΩ, and CT = 3.3 nF, unless
otherwise stated. To override UVLO, VCC should be raised above 17 V prior to test.

Parameter Symbol Test Condition Min. Typ. Max. Unit

PWM
Maximum Duty Cycle Dmax 3842/3 94 97 100 %
Minimum Duty Cycle Dmin 3842/3 0 %
Maximum Duty Cycle Dmax 3844/5 49 49.5 50 %
Minimum Duty Cycle Dmin 3844/5 0 %
Supply Current
Start-up Current ICC 3842/4, VFB = VSENSE = 0 V, VCC = 14 V 0.5 1.0 mA
3843/5, VFB = VSENSE = 0 V, VCC = 7 V 0.3 0.5 mA
Operating Supply Current ICC 9 17 mA
VCC Zener Voltage VZ ICC = 25 mA 30 V
Notes:
1. This parameter is not 100% tested in production.
2. Parameter measured at trip point of PWM latch.
3. Transfer gain is the relationship between current sense input and corresponding error amplifier output at the PWM latch trip point
and is mathematically expressed as follows:

∆ I COMP
A= ; – 0.2 ≤ V SENSE ≤ 0.8 V
∆VSENSE

4. At the over-temperature threshold, TOT, the oscillator is disabled. The 5 V reference and the PWM stages, including the PWM latch,
remain powered.

www.ptcc.com.tw 66
Current Mode Controller AS384x

Typical Performance Curves

Supply Current vs Supply Voltage Output Voltage vs Supply Voltage

25 25

20 20
ICC – Supply Current (mA)

VOUT – Output Voltage (V)

15 15

10 10

5 5
AS3842/4
AS3843/5

AS3843/5

AS3842/4
0 0
0 5 10 15 20 25 30 35 0 5 10 15 20 25 30
VCC – Supply Voltage (V) VCC – Supply Voltage (V)

Figure 2 Figure 3

Regulator Output Voltage vs Ambient Temperature Regulator Short Circuit Current vs Ambient Temperature
5.04 160

5.02
140
IREG – Regulator Short Circuit (mA)

5.00
VREG – Regulator Output (V)

120

4.98
100
4.96

80
4.94

60
4.92

4.90 40
–60 –30 0 30 60 90 120 150 –60 –30 0 30 60 90 120 150
TA – Ambient Temperature (°C) TA – Ambient Temperature (°C)

Figure 4 Figure 5

www.ptcc.com.tw 67
AS384x Current Mode Controller

Typical Performance Curves

Regulator Load Regulation Maximum Duty Cycle vs Timing Resistor

0 100

–4
∆VREG – Regulator Voltage Change (mV)

80

Maximum Duty Cycle (%)

–8

–12 60

150°C 25°C –55°C

–16

40
–20

–24 20
0 20 40 60 80 100 120 140 0.3 1 3 10
ISC – Regulator Source Current (mA) RT – Timing Register (kΩ)

Figure 6 Figure 7

Timing Capacitor vs Oscillator Frequency Maximum Duty Cycle Temperature Stability

100 100

RT = 10 kΩ
90
RT = 680 Ω
CT – Timing Capacitor (nF)

Maximum Duty Cycle (%)

80 RT = 2.2 kΩ
10

RT = 2.2 kΩ 70

RT = 4.7 kΩ RT = 1 kΩ
1 60
RT = 1 kΩ

50
RT = 680 Ω
RT = 10 kΩ
0.1 40
10 100 1M –55 –35 –15 5 25 45 65 85 105 125
TA – Ambient Temperature (°C)
FOSC – Oscillator Frequency (kHz)

Figure 8 Figure 9

www.ptcc.com.tw 68
Current Mode Controller AS384x

Typical Performance Curves

Current Sense Input Threshold vs Error Amp Output Voltage Error Amp Input Voltage vs Ambient Temperature
1.2 2.51

1.0
VSENSE – Current Sense Input Threshold (V)

TA = 25°C 2.50

VFB – Error Amp Input Voltage (V)

0.8

TA = 125°C
0.6 2.49

0.4

2.48
0.2
TA = –55°C
0
2.47
–0.2 VFB = VCOMP
VCC = 15 V
–0.4 2.46
0 1 2 3 4 5 6 –60 –30 0 30 60 90 120 15
VCOMP – Error Amp Output Voltage (V) TA – Ambient Temperature (°C)

Figure 10 Figure 11

Output Sink Capability in Under-Voltage Mode Output Saturation Voltage

1A 0
VCC = 6 V Source Saturation
TJ = 125°C
TA = 25°C VOUT – VCC
–1
VSAT – Output Saturation Voltage (V)
IOUT _ Output Sink Current (mA)

–2
100

TJ = –55°C

3 TJ = 25°C

10 2

Sink Saturation
1
TJ = 125°C

1 0
0 0.5 1.0 1.5 2.0 2.5 10 100 500
VOUT – Output Voltage (V) IOUT – Output Saturation Current (mA)

Figure 12 Figure 13

www.ptcc.com.tw 69
AS384x Current Mode Controller

Application Information Section 1 – Theory of Operation

The AS3842/3/4/5 family of current-mode control The functional block diagram of the AS3842 is
ICs are low cost, high performance controllers shown in Figure 1. The IC is comprised of the six
which are pin compatible with the industry stan- basic functions necessary to implement current
dard UC3842 series of devices. Suitable for mode control; the under-voltage lockout; the refer-
many switch mode power supply applications, ence; the oscillator; the error amplifier; the current
these ICs have been optimized for use in high sense comparator/PWM latch; and the output.
frequency off-line and DC-DC converters. The The following paragraphs will describe the theory
AS3842 has been enhanced to provide signifi- of operation of each of the functional blocks.
cantly improved performance, resulting in excep-
1.1 Under-voltage lockout (UVLO)
tionally better tolerances in power supply
manufacturing. In addition, all electrical charac- The under-voltage lockout function of the
teristics are guaranteed over the full 0 to 105°C AS3842 holds the IC in a low quiescent current
temperature range. Among the many enhance- (≤ 1 mA) “standby” mode until the supply voltage
ments are: a precision trimmed 2.5 volt reference (VCC) exceeds the upper UVLO threshold volt-
(+/– 1% of nominal at the error amplifier input), a age. This guarantees that all of the IC’s internal
significantly reduced propagation delay from cur- circuitry are properly biased and fully functional
rent sense input to the IC output, a trimmed oscil- before the output stage is enabled. Once the IC
lator for precise duty-cycle clamping, a modified turns on, the UVLO threshold shifts to a lower
flip-flop scheme that gives a true 50% duty ratio level (hysteresis) to prevent VCC oscillations.
clamp on 3844/45 types, and an improved 5 V The low quiescent current standby mode of the
regulator for better AC noise immunity. Further- AS3842 allows “bootstrapping”–—a technique
more, the AS3842 provides guaranteed perfor- used in off-line converters to start the IC from the
mance with current sense input below ground. rectified AC line voltage initially, after which power
The advanced oscillator design greatly simplifies to the IC is provided by an auxiliary winding off the
synchronization. The device is more completely power supply’s main transformer. Figure 14 shows
specified to guarantee all parameters that impact a typical bootstrap circuit where capacitor (C) is
power supply manufacturing tolerances.
VDC

>1 mA
R AS384x
VDC MIN PRI SEC
R< 7 VCC
1 mA
IC ENABLE
AC LINE 6
OUT
5 16 V/10 V (3842/4)
GND
8.4 V/7.8 V (3843/5)

+ +
C AUX

Figure 14. Bootstrap Circuit

www.ptcc.com.tw 70
AS384x Current Mode Controller

the following paragraphs. The basic operation of The nature of the AS3842 oscillator circuit is such
the oscillator is as follows: that, for a given frequency, many combinations of
RT and CT are possible. However, only one value
A simple RC network is used to program the fre-
of RT will yield the desired maximum duty ratio at
quency and the maximum duty ratio of the
a given frequency. Since a precise maximum
AS3842 output. See Figure 15. Timing capacitor
duty ratio clamp is critical for many power supply
(CT) is charged through timing resistor (RT) from
designs, the oscillator discharge current is
the fixed 5.0 V at VREG. During the charging time,
trimmed in a unique manner which provides sig-
the OUT (pin 6) is high. Assuming that the output
nificantly improved tolerances as explained later
is not terminated by the PWM latch, when the
in this section. In addition, the AS3844/5 options
voltage across CT reaches the upper oscillator
have an internal flip-flop which effectively blanks
trip point (≈3.0 V), an internal current sink from
every other output pulse (the oscillator runs at
pin 4 to ground is turned on and discharges CT
twice the output frequency), providing an
towards the lower trip point. During this dis-
absolute maximum 50% duty ratio regardless of
charge time, an internal clock pulse blanks the
discharge time.
output to its low state. When the voltage across
CT reaches the lower trip point (≈1.3 V), the cur- 1.3.1 Selecting timing components RT
rent sink is turned off, the output goes high, and and CT
the cycle repeats. Since the output is blanked The values of RT and CT can be determined
during the discharge of CT, it is the discharge mathematically by the following expressions:
time which controls the output deadtime and
hence, the maximum duty ratio. D 1.63D
CT = = (1)
K  R T ƒOSC
R T ƒOSC ln  L 
 KH 

7 VCC

CT
8
5 V REG

OUTPUT
PWM
RT 6 OUTPUT
CLOCK
Large RT/Small CT
4
OSCILLATOR
CT
ID

CT AS3842 OUTPUT

Small RT/ Large CT

5 GND

Figure 15. Oscillator Set-up and Waveforms

www.ptcc.com.tw 72
Current Mode Controller AS384x

1 1 Table 1. RT vs Maximum Duty Ratio

V (KL) D
– (KH) D

RT = REG • (2)
ID (KL)
1–D
D
– (KH)
1–D
D
RT (Ω) Dmax
470 22%
1
− (0.432)
1 560 37%
(0.736) D D
= 582 • 1–D
− (0.432)
1–D 683 50%
(0.736) D D

750 54%
820 58%
VREG − V L
KL = ≈ 0.736 (3)
VREG 910 63%
1,000 66%
VREG − VH 1,200 72%
KH = ≈ 0.432 (4)
VH 1,500 77%
1,800 81%
where fosc is the oscillator frequency, D is the
maximum duty ratio, VH is the oscillator’s upper 2,200 85%
trip point, VL is the lower trip point, VR is the Ref- 2,700 88%
erence voltage, ID is the discharge current.
3,300 90%
Table 1 lists some common values of RT and the 3,900 91%
corresponding maximum duty ratio. To select the
timing components; first, use Table 1 or equation 4,700 93%
(2) to determine the value of RT that will yield the 5,600 94%
desired maximum duty ratio. Then, use equation
6,800 95%
(1) to calculate the value of CT. For example, for
a switching frequency of 250 kHz and a maxi- 8,200 96%
mum duty ratio of 50%, the value of RT, from 10,000 97%
Table 1, is 683 Ω. Applying this value to equation
18,000 98%
(1) and solving for CT gives a value of 4700 pF. In
practice, some fine tuning of the initial values that compensates for all of the tolerances within
may be necessary during design. However, due the device (such as the tolerances of VREG, prop-
to the advanced design of the AS3842 oscillator, agation delays, the oscillator trip points, etc.)
once the final values are determined, they will which have an effect on the frequency and max-
yield repeatable results, thus eliminating the imum duty ratio. For example, if the combined
need for additional trimming of the timing compo- tolerances of a particular device are 0.5% above
nents during manufacturing. nominal, then ID is trimmed to 0.5% above nomi-
1.3.2 Oscillator enhancements nal. This method of trimming virtually eliminates
the need to trim external oscillator components
The AS3842 oscillator is trimmed to provide
during power supply manufacturing. Standard
guaranteed duty ratio clamping. This means that
3842 devices specify or trim only for a specific
the discharge current (ID ) is trimmed to a value
value of discharge current. This makes precise

www.ptcc.com.tw 73
AS384x Current Mode Controller

and repeatable duty ratio clamping virtually 1.4 Error amplifier (COMP)
impossible due to other IC tolerances. The The AS3842 error amplifier is a wide bandwidth,
AS3844/5 provides true 50% duty ratio clamping internally compensated operational amplifier
by virtue of excluding from its flip-flop scheme, which provides a high DC open loop gain (90
the normal output blanking associated with the dB). The input to the amplifier is a PNP differen-
discharge of CT. Standard 3844/5 devices tial pair. The non-inverting (+) input is internally
include the output blanking associated with the connected to the 2.5 V reference, and the invert-
discharge of CT, resulting in somewhat less than ing (–) input is available at pin 2 (VFB). The out-
a 50% duty ratio. put of the error amplifier consists of an active
1.3.3 Synchronization pull-down and a 0.8 mA current source pull-up as
shown in Figure 17. This type of output stage
The advanced design of the AS3842 oscillator
allows easy implementation of soft start, latched
simplifies synchronizing the frequency of two or
shutdown and reduced current sense clamp
more devices to each other or to an external
functions. It also permits wire “OR-ing” of the
clock. The RT/CT doubles as a synchronization
error amplifier outputs of several 3842s, or com-
input which can easily be driven from any open
plete bypass of the error amplifier when its output
collector logic output. Figure 16 shows some
is forced to remain in its “pull-up” condition.
simple circuits for implementing synchronization.

8
VREG 5V
Open Open
Collector RT AS3842 Collector 3K
Output Output CMOS
4 3K
RT/CT RT/CT
GND RT/CT
5
CT 2K 2K

SYNC EXTERNAL CLOCK

Figure 16. Synchronization

1 COMP

COMPENSATION 0.8 mA
NETWORK E/A
VOUT

–
2 VFB
TO
PWM
+

2.50 V

Figure 17. Error Amplifier Compensation

www.ptcc.com.tw 74
Current Mode Controller AS384x

In most typical power supply designs, the con- and in particular, the characteristics of the major
verter’s output voltage is divided down and moni- functional blocks within the supply — i.e. the error
tored at the error amplifier’s inverting input, VFB. amplifier, the modulator/switching circuit, and the
A simple resistor divider network is used and is output filter. In general, the network is designed
scaled such that the voltage at VFB is 2.5 V when such that the converter’s overall gain/phase
the converter’s output is at the desired voltage. response approaches that of a single pole with a
The voltage at VFB is then compared to the inter- –20 dB/decade rolloff, crossing unity gain at the
nal 2.5 V reference and any slight difference is highest possible frequency (up to fSW/4) for good
amplified by the high gain of the error amplifier. dynamic response, with adequate phase margin
The resulting error amplifier output is level shifted (> 45°) to ensure stability.
by two diode drops and is then divided by three to
Figure 18 shows the Gain/Phase response of the
provide a 0 to 1 V reference (VE) to one input of
error amplifier. The unity gain crossing is at
the current sense comparator. The level shifting
1.2 MHz with approximately 57°C of phase mar-
reduces the input voltage range of the current
gin. This information is useful in determining the
sense input and prevents the output from going
configuration and characteristics required for the
high when the error amplifier output is forced to its
compensation network.
low state. An internal clamp limits VE to 1.0 V. The
purpose of the clamp is discussed in Section 1.5. One of the simplest types of compensation net-
works is shown in Figure 19. An RC network pro-
1.4.1 Loop compensation vides a single pole which is normally set to
Loop compensation of a power supply is neces- compensate for the zero introduced by the output
sary to ensure stability and provide good line/load capacitor’s ESR. The frequency of the pole (fP) is
regulation and dynamic response. It is normally determined by the formula;
provided by a compensation network connected
1
between the error amplifier’s output (COMP) and ƒP = (5
inverting input as shown in Figure 17. The type of 2π Rƒ Cƒ
network used depends on the converter topology
80 240

210
Gain
60 180 CF
Phase
150
Phase (Degrees)

VOUT RF
40 120
Gain (dB)

90 RI
–
20 60 E/A To PWM
RBIAS +
30

0 0

–30 2.50 V
–20 –60
101 102 103 104 105 106 107
Frequency (Hz)

Figure 18. Gain/Phase Response of the AS3842 Figure 19. A Typical Compensation Network

www.ptcc.com.tw 75
Current Mode Controller AS384x

AS3842/3/4/5
VIN
COMP
1 VREG
ERROR AMP 8
+
2.5 V VCC PRI SEC
2 – 5 V REG 7
VFB 2R

PWM
1V COMPARATOR R PWM LOGIC
VE FF CLOCK
– OUTPUT
3 S 6 VE
+ R
CURRENT VS
CLOCK GND 5
SENSE
4
RT/CT OUTPUT
IS
VS
R
C RS
Leading Edge Filter

Figure 20. Current Sense/PWM Latch Circuit and Waveforms

The current sense comparator’s inverting input 1.6 Output (OUT)

is internally clamped to a level of 1.0 V to The output stage of the AS3842 is a high current
provide a current limit (or power limit for multiple totem-pole configuration that is well suited for
output supplies) function. The value of RS is directly driving power MOSFETs. It is capable of
selected to produce 1.0 V at the maximum sourcing and sinking up to 1 A of peak current.
allowed current. For example, if 1.5 A is the Cross conduction losses in the output stage have
maximum allowed peak inductor current, then been minimized resulting in lower power dissipa-
RS is selected to equal 1 V/1.5 A = 0.66 Ω. In tion in the device. This is particularly important
for high frequency operation. During under-
high power applications, power dissipation in
voltage shutdown conditions, the output is active
the current sense resistor may become
low. This eliminates the need for an external pull-
intolerable. In such a case, a current down resistor.
transformer can be used to step down the
current seen by the sense resistor. See 1.7 Over-temperature shutdown
Figure 21. The AS3842 has a built-in over-temperature
shutdown which will limit the die temperature to
N:1 130°C typically. When the over-temperature con-
VS dition is reached, the oscillator is disabled. All
other circuit blocks remain operational. There-
IS RS
VS = RS IS fore, when the oscillator stops running, output
N
pulses terminate without losing control of the
supply or losing any peripheral functions that
may be running off the 5 V regulator. The output
Figure 21. Optional Current Transformer may go high during the final cycle, but the PWM

www.ptcc.com.tw 77
AS384x Current Mode Controller

latch is still fully operative, and the normal termi- A simple RC filter is used to suppress the spike.
nation of this cycle by the current sense com- The time constant should be chosen such that it
parator will latch the output low until the approximately equals the duration of the spike. A
over-temperature condition is rectified. Cycling good choice for R1 is 1 kΩ, as this value is opti-
the power will reset the over-temperature disable mum for the filter and at the same time, it simpli-
mechanism, or the chip will re-start after cooling fies the determination of RSLOPE (Section 2.2). If
through a nominal hysteresis band. the duration of the spike is, for example, 100 ns,
then C is determined by:
Section 2 – Design Considerations
2.1 Leading edge filter Time Constant
C = (6)
The current sensed by RS contains a leading 1 kΩ
edge spike as shown in Figure 20. This spike is 100 ns
=
caused by parasitic elements within the circuit 1 kΩ
including the interwinding capacitance of the = 100 pF
power transformer and the recovery characteris-
tics of the rectifier diode(s). The spike, if not prop- 2.2 Slope compensation
erly filtered, can cause stability problems by
Current-mode controlled converters can experi-
prematurely terminating the output pulse.
ence instabilities or subharmonic oscillations

Ve IPK Ve
IAVG 2
IL2 ∆I
∆I'
IAVG 1
m m
1

2
1
m

2
m

IL1

T0 D1 D2 T1 T0 D1 D2 T1

(a) (b)

VCOMP VCOMP
m=m m=m
2 /2 2 /2
1
m

1
m

IL2 ∆I ∆I'
IAVG 1 = IAVG 2 m m
2 2
IL1

T0 D1 D2 T1 T0 D1 D2 T1

(c) (d)

Figure 22. Slope Compensation

www.ptcc.com.tw 78
Current Mode Controller AS384x

when operated at duty ratios greater than 50%. the oscillator at pin 4, it is more practical to add
Two different phenomena can occur as shown the slope compensation to the current waveform.
graphically in Figure 22. This can be implemented quite simply with the
addition of a single resistor, RSLOPE, between pin
First, current-mode controllers detect and control
4 and pin 3 as shown in Figure 23(a). RSLOPE, in
the peak inductor current, whereas the con-
conjunction with the leading edge filter resistor,
verter’s output corresponds to the average induc-
R1 (Section 2.1), forms a divider network which
tor current. Figure 22(a) clearly shows that the
determines the amount of slope added to the
average inductor current (I1 & I2) changes as the
waveform. The amount of slope added to the cur-
duty ratio (D1 & D2) changes. Note that for a fixed
rent waveform is inversely proportional to the
control voltage, the peak current is the same for
value of RSLOPE. It has been determined that the
any duty ratio. The difference between the peak
amount of slope (m) required is equal to or
and average currents represents an error which
greater than 1/2 the downslope (m2) of the induc-
causes the converter to deviate from true
tor current. Mathematically stated:
current-mode control.
Second, Figure 22(b) depicts how a small pertur- m2
m ≥ (7)
bation of the inductor current (∆I) can result in an 2
unstable condition. For duty ratios less than 50%,
the disturbance will quickly converge to a steady
state condition. For duty ratios greater than 50%, In some cases the required value of RSLOPE may
∆I progressively increases on each cycle, caus- be low enough to affect the oscillator circuit and
ing an unstable condition. thus cause the frequency to shift. An emitter fol-
lower circuit can be used as a buffer for RSLOPE
Both of these problems are corrected simultane- as depicted in Figure 23(b).
ously by injecting a compensating ramp into
either the control voltage (VE) as shown in Figure Slope compensation can also be used to improve
22(c) & (d), or to the current sense waveform at noise immunity in current mode converters oper-
pin 3. Since VE is not directly accessible, and, a ating at less than 50% duty ratio. Power supplies
positive ramp waveform is readily available from operating under very light load can experience

8 8
VREG VREG

RT RT
4 4
RT/CT OPTIONAL RT/CT
BUFFER
AS3842 AS3842
CT CT
IS RSLOPE IS RSLOPE
R1 R1
3 3
ISENSE ISENSE
GND GND
RS RS
5 5

(a) (b)

Figure 23. Slope Compensation

www.ptcc.com.tw 79