DSP Processor Implementation of A Modem For Narrow Bandwidth Channel

DSP PROCESSOR IMPLEMENTATION OF A MODEM FOR NARROW BANDWIDTH CHANNEL
CHAPTER-1 AN OVERVIEW
ECE Department, Gitam University
INTRODUCTION
A typical communication system will input data, perform some form of processing and frequency translation, transmit the data, and perform the converse operations at the receiver. The transmission of data is done using Public Switched Telephone Network (PSTN). Traditionally, the PSTN has been viewed as an analog network. In reality, however, the PSTN as we presently know it has become an almost entirely digital network. In most of cases, the only part of the PSTN that has remained analog (and will likely remain so far many years to come) is the local loop, which represents relatively short connection from a home to central office. The modem contraction of the term modulator-demodulator is a conversion device that facilities the transmission and reception of data over a public switched telephone network (PSTN). The data of interest may be digital signals generated by computers and service providers. In such application, the modulator portion of the modem converts the incoming digital signal into a standard form suitable for transmission over a telephone channel in the PSTN. The demodulator portion of the modem receives the channel output and reconverts it into original digital signal format.
1.1 DEVELOPMENT OF MODEMS

In the beginning there was a decided lack of any good way to communicate between small computers. The big guys, mainframes and such, could communicate but they were very expensive and the leased lines they used cost a fortune. The modem had been around for a long time, since the old Teletype days in fact, but it was not readily available to small computer users. The first small computer modems were built from diagrams in Popular Electronics and other related magazines.
What exactly is a modem? A modem is simply a device that takes a stream of data and turns it into sound. It operates, in its simplest form like a speaker and a microphone. If a bit of data from your computer is on, or high, then the tone the modem produces is of one pitch. If the data bit is low or off, then the modem produces another sound. The modem on the other end of the phone line simply listens to the line and re-converts the tones back to the 1s and 0s that make up the letters that make up words. At first the fastest modem you could buy was 300 baud. The 300 baud transmission protocol is called V.21 or Bell 103. That means it could send and receive 300 bits a second. Since a letter is made up of 8 bits this means we could send about 37 letters a second. Actually since there is a little overhead in the form of start and stop bits, the bits that tell the computer that this is the beginning and end of a character, we end up with 30 characters a second. Thats characters, not words. If you think about it most people can read much faster than that. Most of us have seen this kind of modem on TV and in movies. They were the kind you actually put the handset from a phone on a cradle that had cups for the earpiece and mouthpiece. These modems were call acoustically coupled. Just plain sound with a microphone and speaker built into the cradle. It took a long time for computer engineers to make affordable modems that could go faster than 300 baud. Eventually they did however and the 1200 baud modem was born. The 1200 baud protocol is called V.22 or Bell 212. When the math is done that comes out to about 120 characters a second or twenty four five letter words. At nearly the same time simple compression was beginning to be used. Compression is the ability to smash data down to a smaller number of bits and bytes. The first data compression was very simple. It squeezes out the blank spaces and unused bits and puts them back in on the other end. This scheme works ok on text but is not very good for binary programs or pictures. This kind of compression was also done on the computer before it was sent to the modem. As a result the overall time it took to send data from one computer to another did not decrease too much since the computers of the day had to work fairly hard to compress the data.
It did not take long for the 2400 baud modems to hit the market. The 2400 baud protocol is called V.22 BIS. This doubled our transfer rate and later models of these modems came with new data compression and error correction scheme, called V.42 or the Auto Reliable Protocol. The speed increase was great. Now we could actually receive at about the speed you could comfortably read. V.42 was a great boon too. Now, for the first time, we had almost error free data transmissions that were compressed fairly well at 4 to 1 and greatly reduced the overall time needed to transmit data and thus lowering long distance charges. At the same time all this speed was increasing the computer users were treated to another big development. Most 2400 baud modems also had fax send and receive capabilities. At first only at 4800 baud, in a very short time the electronics in the modems could run 9600 baud and take advantage of the newer faster fax machines. Youre probably wondering why they didnt just make modems transfer data at 9600 baud too. Fax machines use a different kind of tone recognition than modems do. Faxes use more than just two tones so the speed could be increased by the multiple of the number of tones. Also if you drop a bit on a fax you end up with a white spot on the page about the size of a pin head or 1/100th of an inch. If you drop a bit in a data stream you end up with a whole new letter or character. The next advance in modems was the short lived 4800 baud variety. There were not very many of these sold since the 9600 baud modems came bounding onto the market. Both 4800 and 9600 baud protocols are called V.32.
1.2 DESCRIPTION OF MODEMS

What is Modem? The Modem a contraction of the term modulator, demodulator, is a conversion device that facilities the transmission and reception of data over PSTN. The analog signal is converted into digital format and is passed through modulator and demodulator reconverts the digital format signal and channel output. In digital communication system the modem input signal will be a digital stream from a digital source or channel encoder. However the modem input signal generated
from an analogue information source, the signal must be band limited to a bandwidth B before sampling takes place. According to the nyquist rate the sampling frequency should be equal to or higher than twice the band limited signal(fs>_2B). the energy of the voice signal is concentrated at frequencies below 4khz, hence the speech signals are typically lowpass filtered in order to accurately reconstruct the actually signal. In practice most of the voice communication system uses the sampling rate of 8kHz.
1.3 MODEM CONFIGURATIONS

There are two distinct classes of modem configuration:1. symmetric modem configuration
2.
Asymmetric modem configuration.
Symmetric modem configuration:The simplest approach for design of modems is to treat the entire PSTN as a linear network. In such a setting, analog to digital and digital to analog conversions are needed whenever the modems send the signals to and receive the signals from PSTN.
Figure:1.1 Modem configuration: the upstream and down stream data rates is equal. The modem configuration exhibits symmetry in that both modems are identical and the data rate downstream is exactly same as the data rate upstream.
Asymmetric modem configuration:For a more efficient use of PSTN, we should treat it as what it really is an almost entirely digital network that is nonlinear. In particular, the ISP is digitally implemented;
the digital to analog conversion at the ISP modem is eliminated. This means that the communication between the ISP and PSTN can be entirely digital. The users modem has to remain analog because local loop is analog. This in turn requires the analog to digital and digital to analog conversions each time the user modem sends the signals to and receives the signals from the PSTN.
Figure:1.2 modem configuration of upstream and downstream for asymmetric network. In general the popular V.32 modem standards that has the following characteristics: Carrier frequency: 1,800 Hz Modulation rate= 2,400 baud Data rate= 9,600 b/s. In the modems we can use different modulations technique for the coding and decoding of the information and get the data transfer from transmitter to receiver sections. We are going to implement the BSPK, QPSK, QAM modulation techniques in the mat lab for data transmission and reception.
CHAPTER-2 INTRODUCTION
INTRODUCTION
2.1 BACKGROUND
This project deals with voice transmission over a channel. For this purpose, some modulation schemes and voice coders are to be implemented. Voice coding and transmission is an important and pervasive task in any telecommunication system. A simple transmission/reception scheme intended for voice transmission is proposed in the figure below consisting of: one microphone; a DSP board for voice acquisition, sampling, coding and modulation; a channel emulator; a second DSP board for voice processing or signal decoding, demodulation and voice reconstruction; a loudspeaker; and finally two PCs that control each DSP. Voice coding and transmission is an important and pervasive task in any telecommunication system. Actually, voice transmission has been spread out from the classical telephone oriented network (POTS) to the packet oriented networks like the Internet (VoIP).
Figure 2.1 BLOCK DIAGRAM OF VOICE BASEBANDMODEM SYSTEM
This voice transmission scheme represents the basis of this project. The transmitter and the receiver have to be synchronized. At the transmitter the input voice is parameterized (codified) and modulated; while at the receiver is synthesized (decodified) and demodulated. The output data of the transmitter is sent though the base-band channel of the emulator, which emulates a realistic wireless channel with fading and noise. The voice processing is done in real-time, and the recovered voice is displayed on the loudspeaker.
2.2 SPECIFICATIONS
The implementation of the voice transmission system in real time is done using two standard PCs with one DSP board each. All processing is performed in the DSP except presentation of results and loading of files, which are done on the PC. In addition to the implementation on the DSPs, a Matlab simulation will be done. In this project the Matlab prototype is able to transfer a segment of pre-recorded voice or digital sequence, which is encoded and modulated, and sent over the wireless channel. At the receiver, the data is captured and processed off-line. The offline processing consists of synchronization, demodulation and re-generation of the output.
2.3 RESOURCES
2.3.1 Hardware Two DSK boards Two standard PCs Microphone Loud speaker Oscilloscope Function Generator
2.3.2 Software
Mat lab software Code Composer studio
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CHAPTER-3 ARCHITECTURE OF THE SYSTEM
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ARCHITECTURE OF THE SYSTEM

3.1 SYSTEM OVERVIEW
The main blocks of the voice transmission system implemented during this project are represented at Figure 2.1. The microphone records the speech data to be transmitted; while the main purposes of the transmitter are to encode the speech to minimize its bit rate, and modulate the data in such a way as to produce electromagnetic signals that can be transmitted across the channel. The channel is transmits the signal. Regarding the receiver, the output of the channel is first synchronized; then the influence of the channel over the signal is estimated to correct the errors of the received data; finally, the data is demodulated and decoded, and the reconstructed speech displayed by a loudspeaker.
Fig 3.1 Voice Base band system diagram
Each section of the block diagram explanation is done below: Transmitter Receiver
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3.2 TRANSMITTER
The input of the transmitter is the recorded speech by the microphone. An A/D converter samples the voice to obtain digital data from this input signal. The data is then down-sampled and encoded. The encoder performs speech coding aiming to reduce the bit rate of the data sequence. The data bits are multiplexed dividing them into frames and adding guard, training and estimation bits to form the packet. A modulator is in charge of convert the digital packet into waveforms that are compatible with the nature of the channel. Pulse-shaping and up-sampling is applied to this modulated sequence. Finally, up-conversion is used to transmit through the physical channel.
Fig 3.2 BLOCK DIAGRAM OF TRANSMITTER
3.2.1 A/D CONVERTER

An analog-to-digital converter is a device which converts continuous signals to discrete digital numbers. The speech signal recorded by microphone is sampled by the DSP. The input signal is analog is represented in samples per second. Everything is done in digital format.
3.2.2 DECIMATION
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After A/D conversion, the digital signal is filtered using low pass filter in order to prevent the aliasing effect in decimator. Thus Down sampling is applied in order to omit the high frequency components and consider the necessary information.
3.2.3 ENCODER
By preprocessing the input signal, now the signal will be encoded in order to reduce the bit-rate required for the transmission. The transmission of bits is done by adding the extra bits like guard bits, parity bits etcin order to avoid the bits loss of transmission.
3.2.4 MULTIPLEXER
The output of encoder is a stream of data bits which are obtained. These data bits have the extra bits that added in order to avoid the loss of transmission and its length may of 36 bits per frame.
Fig 3.3 Packet Structure
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3.2.5 MODULATION
The multiplexed binary data is digitally modulated to transform it into waveforms that are compatible with the nature of the communication channel. There are different modulators with different constellation points that are used in the modulation.
3.2.6 PULSE SHAPING OR UPSAMPLING:After modulation, the symbols cannot be transmitted right away. They need to be up-sampled and shaped. The pulse shaping is, in fact, an amplitude modulation.
3.2.7 UP CONVERSION:Sub-sequent to pulse-shaping is carrier modulation. The output of the modulator is a base-band signal that has to be up-converted to the desired carrier frequency in order to better suit the characteristics of the channel.
3.3 CHANNEL
Fig 3.4 BLOCK DIAGRAM OF CHANNEL
In the channel the message signal g(t) and the carrier signal w(t) is added and passed through the channel. r (t) signal is obtained is the transmitted signal which is passed towards the receiver section.
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3.4 RECEIVER
\
Figure 3.5
BLOCK DIAGRAM OF RECEVIER
The input of the receiver is the received signal from the channel. This signal is first down-converted and low-pass filtered. Then matched filtering is applied taking into account the pulse-shape used at the transmitter. The received signal has to be synchronized and this is done based on the cross-correlation between this signal and known training sequence at the receiver. After knowing the correct position when the sequence starts, the signal is down-sampled. Finally, the data is demodulated, decoded, up-sampled to the original frequency, and D/A converted to display the reconstructed speech using a loudspeaker.
3.4.1 DOWN CONVERSION

The downconversion block converts the received signal to the baseband, resulting in a complexvalued baseband signal. The input signal is multiplied with the
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local oscillator signal, followed by a lowpass filter to remove terms of frequency 2fc and fulfill the sampling theorem when sampling and converting into a discretetime signal.
3.4.2 DOWN SAMPLING

The signal can be properly sampled. The down-sampling factor is the same as the up-sampling factor. When the signal is correctly synchronized, so that after downsampling, the result obtained is a sequence of peaks corresponding to a certain modulation scheme, and therefore it can be decoded accordingly.
3.4.3 DEMODULATION
The purpose of the demodulator is to map the symbols back to sequences of bits, which can be then processed by the voice decoder. Three different modulation schemes have to been implemented.
3.4.4 UP SAMPLING
Reconstructed speech signal was a downsampled version of the original signal. Therefore, it is upsampled by a factor of 8, so that an estimate of the original digital signal is obtained. After up-sampling, the signal is filtered using a low-pass filter (interpolation filter) in order to avoid aliasing.
3.4.5 D/A Conversion

Resulting signal is converted from digital to analog using the D/A converter implemented in the DSP. Speaker is fed by this analog signal and the voice transmission is completed.
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For the transmission and reception of the signals in mat lab that are implemented using different modulation techniques of BPSK, QPSK, QAM which are explained in next chapters.
CHAPTER-4 BPSK TECHNIQUE
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BPSK TECHNIQUE
In the project we are using modulation techniques of BPSK, QPSK, and QAM. In this we are going to explain the theory part of BPSK, QPSK and mat lab output theoretically which have to be obtained.
4.1 BPSK THEORY

In this project we are first implementing BPSK modulation technique for the transmission and reception of the voice signal at the output. Let has have a brief look on the BPSK Transmitter/Receiver simulation in mat lab. What is meant by BPSK? BPSK is a digital modulation technique that separates bits by shifting the carrier 180 degrees. A carrier frequency signal is chosen that is known by both the transmitter and the receiver. Each bit is encoded as a phase shift in the carrier at some predetermined period. When a 0 is sent, the carrier is transmitted with no phase shift, and when a 1 is sent, the carrier is phase-shifted by 180 degrees. When a sequence is given which changes the value from a 0 to a 1 or from a 1 to a 0, a change of phase is indicated in the positive and negative y axis.
Digital modulation technique is classified into two types coherent and Non coherent techniques depending on the phase recovery circuit or not. The phase recovery ensures that the oscillator supplying the local generated carrier wave in the receiver is synchronized (in both frequency and phase) to the oscillator supplying carrier wave used to originally modulate the incoming data stream in the transmitter.
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Figure 4.1 For the digital information transferring and receiving internal block diagram is shown below In the digital information where the speech in digital encoded form with a bit rate of 16 kbit/s, and after Forward Error correction(FEC) coding the data rate becomes 32 kbits/s. we can keep the channel about 1 Ghz, range which is better to transmit the 32 kb/s. if the phase of the carrier is switched between 32kbits/s, being at 0 deg and 180 deg for bits having logic 0 and 1 then there are 31,250 radio frequency oscillations per bit transmitted. The output waveform shown below for the logic 0 and 1 is shown below for the 0 deg and 180 deg.
Figure 4.2 BPSK output waveform For logical 0 the phasor diagram is shown along the positive axis and logical 1 the phasor diagram is shown along the negative axis. For the sequence of the bits the modulator output of the BPSK is shown below, which is the combination of the above diagram:
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Figure 4.3 BPSK waveform II BPSK modulation technique the constellation diagram shown below which are transmitting binary data there are only two points. As these two points are at equal distance from origin we would expect them to represent equal magnitude carriers.
Figure 4.4 BPSK Constellation Diagram In Binary Phase shift keying (BPSK), determining the phase of transmitted signal and decoding the transmitted information. This problem is also known as the carrier recovery attempt is made to recover the phase of the carrier. When a phase point at, say, 180 deg is selected to reflect the information being transmitted, the phase of the transmitted carrier is set to 180 deg. However the phase of the carrier is often changed by the transmission channel with result that the receiver measure a different phase. In order to overcome this problem there are two ways: Coherent detection Non coherent detection.
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In coherent detection we have to measure the phase change imposed by the channel and then the receiver determine the transmitted phase. This is known as the coherent detection. In Non coherent detection we have transmit the phase difference rather than actual phase. The receiver merely compares the actual phase with current phase and the phase changed is removed. This is known as Non coherent detection.
4.2 BPSK GENERATION IN EQNs

In a coherent binary PSK system, the pair of signals a (t) and b (t) used to represent binary symbols 1 and 0 respectively, a(t) = root(2Eb/Tb) cos (2*pi*f*t) b(t) = - root(2Eb/Tb) cos (2*pi*f*t) (4.1) (4.2)
a pair of sinusoidal waves that differ only in a relative phase shift of 180 degrees. From pair of equations it is clear that, in the case of binary PSK, there is only one basis equation of unit energy namely, c(t) = root(2/Tb) cos(2*pi*f*t) we express the transmitted signals as a(t) = root(Eb)*c(t) ; b(t) = -root(Eb)*c(t) ; 0<t<Tb 0<t<Tb (4.4) (4.5) (4.3)
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Figure 4.5 QPSK Waveform In this way you will get the transmitted waveforms with message points of Eb theoretically. In BPSK the signal bandwidth for the communications channel needed depends on the symbol rate, not on the bit rate. In this symbol rate is equal to bit rate because only two bits are transmitted. The actual formula for the symbol rate is given as: Symbol rate = bit rate/ The number of bits transmitted with each symbol (4.6)
For the BPSK modulation technique that is to be implemented in the project where we are giving the random bit stream with SNR = 0.5 or 5 and obtain the output in the MATLAB. In the below we had shown the output of the BPSK that is to be obtained in MATLAB:
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Figure 4.6 MATLAB plots for random bit stream shown the transmitted and received waveforms with SNR = 0.5
Figure 4.7 MATLAB plots for random bit stream shown the transmitted and received waveforms with SNR = 5
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Figure 4.8 MATLAB plots displaying decision regions and detection for (a) SNR =0.5
Figure 4.9 MATLAB plots displaying decision regions and detection for (b) SNR = 5.0. In the received signal fall out of the decision region resulting in errors. The received signal is noisier and resulting in false detection. These are the mat lab plots that are to be obtained in BPSK.
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4.3 QPSK THEORY

Now in the project we are going to implement another modulation technique QPSK in mat lab where to check the digital bit sequence is transmitted or received perfectly or not.
4.3.1 QUADRATURE PHASE SHIFT KEYING

Quadrature Phase shift keying has a reliable performance, and has a very low probability of error, is one of the important goal in the digital communication. It has the efficient utilization of bandwidth. In this we have bandwidth conserving scheme known as quadri phase shift keying. In quadri phase shift keying (QPSK), as with binary PSK, information is carried by the transmitted signal contained in the phase. The phase of the carrier takes the one of the value of the four equally spaced phases, such as 45,135,225,315 degrees. We can define the transmitted signal as: S(t)= root(2E/T) cos[ 2* pi* fc*t + (2*i-1) *pi/4] , (4.7)
Where i=1, 2, 3, 4; E is the transmitted signal energy per symbol and T is the duration symbol. The carrier frequency fc equals to nc/T some fixed integer nc. Each possible value of phase corresponds to a unique dibit. For example if we have chosen the set of phase values to represent the Gray-encoded dibits: 10, 00, 01 and 11, where only a single bit is changed from one dibit to the next.
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Signal space diagram of QPSK

We can define the transmitted signal s(t) for the given interval above in the equivalent form:S (t) = root (2E/T) cos [(2i-1)* pi/4] cos (2*pi*fc*t) root (2E/T) sin [(2i-1)*pi/4] sin (2*pi*fc*t) (4.8)
There are two orthogonal functions explained as A (t) and B (t) defined as a quadrature carriers:
A (t) = root(2/T) cos (2*pi*fc*t) B (t) = root(2/T) sin (2*pi*fc*t) Gray encoded input dibit
10 00 01 11
(4.9) (4.10)
Phase of QPSK signal co-ordinates of message points

pi/4 3*pi/4 5*pi/4 7*pi/4 + root(E/2) - root (E/2) - root (E/2) + root (E/2) - root(E/2) - root (E/2) + root (E/2) + root (E/2)
There are four message points and signal vector are explained in the below diagram:-
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Figure 4.10 Signal space QPSK diagram According to Quadrature Phase shift keying (QPSK) signal has a two dimensional signal constellation i.e.., N=2 and four message points i.e.., M=4 whose phase angle increases in a counter clockwise directions. We can explain QPSK with an example by taking a sequence and plotting the waveforms for the generation of the signal. The input bit sequence 01101000 is shown in the figure below. The sequence is divided into two other sequences, consisting of odd and even numbered bits of input sequence. The waveforms representing the two components of the QPSK signal, namely, S(t)* A(t) and S(t) * B(t). These two waveforms can be individually shown and adding both we get the QPSK waveform.
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Figure 4.11(a) Input binary sequence; (b) odd numbered bits of input sequence (c) Even numbered bits of input sequence (d) QPSK waveform.
Error probability of QPSK:In the coherent QPSK system, the received signal x (t) is defined by, X (t) = S (t) + W (t) (4.11)
Where W (t) is the white Gaussian Noise process of zero mean and power spectral density No/2. For the incoming bit sequence the bit error rate formula is given as:BER = erfc (root [Eb /No]) Generation and detection of QPSK signals:Consider the generation of the QPSK signals. We had shown the block diagram of the QPSK transmitter. The incoming binary data sequence is first transformed into polar form by Noreturn to zero level encoder. Thus the symbol 1 and 0 are represented by +root (Eb) and root (Eb). This binary wave is next divide by means of a demultiplexer into two separate binary waves consisting of odd and even numbered sequences of input bits. These two binary waves are denoted by a1 (t) and a2 (t) depending on the particular
(4.12)
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dibit that is transmitted. These two binary waves are modulated a pair of quadrature carriers.
Figure 4.12 The above block diagrams show the Quadrature Phase shift keying (QPSK) transmitter and receiver sections.
Phase Shift Keying (PSK) is a method of transmitting and receiving signals in which the phase of the transmitted signal is varied to convey the information. A common type of PSK is Quadrature Phase Shift Keying (QPSK). It is used extensively in applications including CDMA (Code Division Multiple Access) cellular service, wireless local loop, Iridium (a voice/data satellite system) and DVB-S (Digital Video Broadcasting-Satellite).
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In QPSK, the data bits to be modulated are grouped into symbols, each containing two bits, and each symbol can take on one of four possible values: 00, 01, 10 and 11. The signal shifts in intervals of /2 radians from /4 to 3/4, 5/4 or 7/4 radians, such that the signal constellation matches the configuration shown in Figure 2.6 [5]. The symbol rate for QPSK is half the bit rate, therefore exhibits the same performance but twice the bandwidth efficiency compared to BPSK.
Figure 4.13 QPSK Constellation
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CHAPTER-5 QAM THEORY
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QAM THEORY
Now in the project we are going to implement another modulation technique QAM in mat lab where to check the information transmitted or received perfectly or not.
5.1 QUADRATURE AMPLITUDE MODULATION

In the Quadrature Amplitude Modulation we have different constellation points. If we decrease the signalling rate to 16Kb/s the bandwidth of the modulating signal will decrease. If the data rate is 32Kb/s, and the signalling rate becomes 16Kb/s, then every symbol transmitted must carry two bits of information. This means that we must have four points on the constellation. The two bits of information are associated with every constellation point. These have the two orthogonal co-ordinate axes, each passing through origin. The orthogonal co-ordinate axes have a phase rotation of 90 degrees with respect to each other, and hence they have a so called quadrature relationship. The pair of co-ordinates axes can be associated with a pair of quadrature carriers, normally a sine and a cosine waveform. In the constellation representation we have constant amplitude signal, but the carrier phase values at the beginning of each symbol period. The phase values would be of either 45deg, 135deg, 225deg and 315deg.
Figure 5.1 QAM Constellation Diagram
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In general, grouping n bits into one signalling symbol yields constellation points, which are often referred to as phasors, or complex vectors. The phasors are associated with these points may have different amplitude and phase values and these type of modulation referred to as multi-level modulation, where the number levels is equal to the number of constellation points. After the transmission through the channel the receiver must identify the phasor transmitted, and in doing so can determine the constellation points and hence the bits associated with these points. In this way data is recovered. There are many problems with attempting to recover data transmitted over fixed channels such as telephone lines and radio channels and many of these problems are rectified. In the ends of 1950s there was a considerable amount of interest digital phase modulation transmission schemes as an alternative to digital amplitude modulation. Digital phase modulation schemes are those whereby the amplitude of the transmitted carrier is held constant but the phase changed in the response to the modulating signal. All the fundamental problems in PSK is that transmitting the phase of the transmitted signal and hence decoding the transmitted signal. When a phase point, say 90 degrees is selected to reflect the information being transmitted, the phase of transmitted signal is set to 90 degrees. However, the phase of the carrier is often changed by the transmission channel with the result that the receiver measure a different phase. This means that unless the receiver knew that the phase change imposed by the channel was it would be unable to determine the encoded information. This problem is overcome by two ways. Coherent Detection and Non Coherent detection.
5.2 QAM TYPES OF CONSTELLATIONS:In the QAM w have different type of constellations. Those are: Type-I constellation Type-II constellation Type-III constellation
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Using these different constellations the performance of the circular type constellation could be improved by having more points on the ring formation. The rationale for this was that errors were caused when noise introduced into the signal moved the receiver phasor from the transmitted constellation point to different one. In Type-I conceded that a system with unequal number of points on each amplitude ring would be more complicated to implement, particularly in the case of non coherent detection. There is improvement in Type-II from Type-I where 3db in mathematical approach. In the Type-III has better performance than Type-II where new constellation the square QAM system has been obtained. They described this system as essentially amplitude modulation and demodulation of two carriers that have same frequency but are in quadrature with each other- the first time that combined amplitude and phase modulation had been thought of as amplitude modulation on quadrature carriers. But in problem in Type-III is that it can used in Coherent Detection and not possible in Non coherent detection. Theoretical analysis is performed on Gaussian noise channels and came to conclusion that the Type-III has small improvement in performance than Type-I and Type-II.
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Figure 5.2 Different Types of constellations
5.3 QAM MODULATION AND TRANSMISSION

In general the modulated signal can be represented by:s(t) = a(t) cos[2fct+(t)] = Re (a(t) e j [jwct+ (t)])
(5.1)
where the carrier cos (Wct) is said to be amplitude modulated if its amplitude a(t) is adjusted in accordance with the modulating signal, and is said to be phase modulated if (t) is varied in accordance with the modulating signal. In QAM the amplitude of the baseband modulating signal is determined by a(t) and the phase by (t). The in-phase component I is given by:I = a(t) cos (t) And the quadrature component Q by Q = a(t) sin (t) (5.3) (5.2)
The signal is corrupted by the channel. Here we will only consider Additive White Gaussian Noise (AWGN). The received signal is then given by r(t) = a(t) cos[2fct+(t)]+ n(t) (5.4)
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Where n (t) represents the AWGN, which has both in-phase and quadrature component. It is received signal which we will attempt to demodulate. In the QAM technique for high transmission has implied relatively simple equalisers if they are implemented with the existing circuitry. In general two equalisers frequently used are the linear and the decision feedback equalizer. In the next following sections, we consider the aspects of specific equalizers to QAM, and consider some of the actual implementations. We consider different equalizers of algorithms like Trained LMS, Decision Directed Equalizer.
5.4 QAM TRANSMITTER

In the QAM technique transmitter input is a serial binary data stream that is passed number off bits per second. The serial to parallel converter group the input bits. As is PAM the T=1/fs will be used to denote the symbol period. The alphabet consists of pair of real numbers representing points in 2- dimensional space and is called signal constellation. It will be convenient to consider the 2- dimensional space to be the complex plane and represent the channel symbol sequence in complex numbers Cn = An +j Bn. part,Bn, the quadrature (Q) component.
(5.5)
It is customary to call the real part, A n, the in phase or I component and the imaginary
5.5 QAM RECEIVER

The input signal r0(t) represents the signal at the receiver input which is the transmitted QAM signal distorted by the non-ideal frequency response of the channel and additive noise. This signal is passed through the Receive Filter which is a band pass filter that passes the QAM signal and eliminates out-of-band noise. The Receive Filter can also be used in combination with the transmitter filters to perform the spectral shaping required for no intersymbol interference with a perfect channel.Intransmission through a communications channel like a voice band telephone circuit, the signal often significantly attenuated.
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5.6 LEAST MEAN SQUARE EQUALIZER

Adaptive filters are best used in cases where signal conditions or system parameters are slowly changing and the filter is to be adjusted to compensate for this change. A very simple but powerful filter is called the linear combiner, which is nothing more than an adjustable FIR filter. The LMS criterion is a search algorithm that can be used to provide the strategy for adjusting the filter coefficients. Programming examples are included to give a basic intuitive understanding of adaptive filters. Least Mean Square equalizer is used because they can minimize the joint effects of Inter Symbol Interference (ISI) and noise of the equalizer output over their memory length. LMS equalizer in general can tolerate higher ISI and have faster convergence. In the optimum estimation technique the required signal properties for which we have to use the adaptive filters algorithms presented in the following and to guarantee the convergence and stability of the algorithms, it is necessary to make some assumptions about the nature of our input signals and make them to obtain at the output.
5.7 DECISION DIRECTED ADAPTIVE EQUALIZER

The simplified schematic of a decision directed automatic adaptive equalizer is where the term decision directed implies that after a training period the equalizer is required to update its coefficients on the basis of the signal at the output of the receiver decision device which is not always an error free signal. Initially training sequence known to both transmitter and the receiver is sent, allowing the equalizer to derive the error signal from the transmitted signal x (n) and the equalized signal y (n) and the error signal is:E (n) = x (n) y (n) (5.6)
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CHAPTER 6 IMPLEMENTATION OF PROJECT IN DSK
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IMPLEMENTATION OF PROJECT IN DSK

6.1 INTRODUCTION
The TMS320C6x are the first processors to use TI architecture, having implemented the VLIW architecture. The TMS320C62x is a 16-bit fixed point processor and the 67x is a floating point processor, with 32-bit integer support. The discussion in this chapter is focused on the TMS320C67x processor. The architecture and programming associated with this processor are also discussed. The C6713 DSK is a low-cost standalone development platform that enables users to evaluate and develop applications for the TI C67xx DSP family. The DSK also serves as a hardware reference design for the TMS320C6713 DSP. Schematics, logic equations and application notes are available to ease hardware development and reduce time to market.
6.2 DIAGRAM OF TMS320C6713 DSK
Figure 6.1:Block diagram of TMS320C6713 DSK

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Features
The DSK comes with a full compliment of on-board devices that suit a wide variety of application environments. Key features include: A Texas Instruments TMS320C6713 DSP operating at 225 MHz. An AIC23 stereo codec 16 Mbytes of synchronous DRAM 512 Kbytes of non-volatile Flash memory (256 Kbytes usable in default configuration) 4 user accessible LEDs and DIP switches Software board configuration through registers implemented in CPLD Configurable boot options Standard expansion connectors for daughter card use JTAG emulation through on-board JTAG emulator with USB host interface or external emulator Single voltage power supply (+5V)
6.3 FUNCTIONAL OVERVIEW

The DSP on the 6713 DSK interfaces to on-board peripherals through a 32-bit wide EMIF (External Memory Interface). The SDRAM, Flash and CPLD are all connected to the bus. EMIF signals are also connected daughter card expansion connectors which are used for third party add-in boards. The DSP interfaces to analog audio signals through an on-board AIC23 codec and four 3.5 mm audio jacks (microphone input, line input, line output, and headphone output). The codec can select the microphone or the line input as the active input. The analog output is driven to both theline out (fixed gain) and headphone (adjustable gain) connectors. McBSP0 is used to send commands to the codec control interface while McBSP1 is used for digital audio data. McBSP0 and expansion connectors in software.
McBSP1 can be re-routed to the
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The DSK includes 4 LEDs and a 4 position DIP switch as a simple way to provide the user with interactive feedback. Both are accessed by reading and writing to the CPLD registers.An included 5V external power supply is used to power the board. On-board switching voltage regulators provide the +1.26V DSP core voltage and +3.3V I/O supplies. The board is held in reset until these supplies are within operating specifications. Code Composer communicates with the DSK through an embedded JTAG emulator with a USB host interface. The DSK can also be used with an external emulator through the external JTAG connector.
6.4 ARCHITECTURE
The simplified architecture of TMS320C6713 is shown in the Figure below. The processor consists of three main parts: CPU, peripherals and memory.
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Figure 6.2: Simplified block diagram of TMS320C67XX Family
6.4.1 CENTRAL PROCESSING UNIT

The CPU contains program fetch unit, Instruction dispatch unit, instruction decode unit. The CPU fetches advanced very-long instruction words (VLIW) (256 bits wide) to supply up to eight 32-bit instructions to the eight functional units during every clock cycle. The VLIW architecture features controls by which all eight units do not have to be supplied with instructions if they are not ready to execute. The first bit of every 32bit instruction determines if the next instruction belongs to the same execute packet as the previous instruction, or whether it should be executed in the following clock as a part of the next execute packet. Fetch packets are always 256 bits wide; however, the execute
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packets can vary in size. The variable-length execute packets are a key memory-saving feature, distinguishing the C67x CPU from other VLIW architectures. The CPU also contains two data paths (Containing registers A and B respectively) in which the processing takes place. Each data path has four functional units (.L, .M, .S and .D).
6.4.2 GENERAL PURPOSE REGISTER FILES

The CPU contains two general purpose register files A and B. These can be used for data or as data address pointers. Each file contains sixteen 32-bit registers (A0-A15 for file A and B0- B15 for file B). The registers A1, A2, B0, B1, B2 can also be used as condition registers. The registers A4-A7 and B4-B7 can be used for circular addressing. These registers provide 32-bit and 40-bit fixed-point data. The 32-bit data can be stored in any register. For 40-bit data, processor stores least significant 32 bits in an even register and remaining 8 bits in upper (odd) register.
6.4.3 FUNCTIONAL UNITS

The CPU features two sets of functional units. Each set contains four units and a register file. One set contains functional units .L1, .S1, .M1, and .D1; the other set contains units .D2, .M2, .S2, and .L2. The two register files each contain sixteen 32-bit registers for a total of 32 general-purpose registers. The two sets of functional units, along with two register files, compose sides A and B of the CPU. Each functional unit has two 32-bit read ports for source operands and one 32-bit write port into a general purpose register file. The functional units . L1, .S1, .M1, and .D1 write to register file A and the functional units .L2, .S2, .M2, and .D2 write to register file B. As each unit has its own 32-bit write port, all eight ports can be used in parallel in every cycle. The .L, .S, and .M functional units are ALUs. They perform 32-bit/40-bit arithmetic and logical operations. .S unit also performs branching operations and .D units perform linear and circular address calculations. Only .S2 unit performs accesses to control register file.
6.5 PERIPHERALS OF TMS320C6713
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The TMS320C67x devices contain peripherals for communication with off-chip memory, co-processors, host processors and serial devices. The following subsections discuss the peripherals of C6713 processor.
6.5.1 ENHANCED DMA

The enhanced direct memory access (EDMA) controller transfers data between regions in the memory map without interference by the CPU. The EDMA provides transfers of data to and from internal memory, internal peripherals, or external devices in the background of CPU operation. The EDMA has sixteen independently programmable channels allowing sixteen different contexts for operation. The EDMA can read or write data element from source or destination location respectively in memory. EDMA also provides combined transfers of data elements such as frame transfer and block transfer. Each EDMA channel has an independently programmable number of data elements per frame and number of frames per block.
6.5.2 HOST POST INTERFACE

The Host-Port Interface (HPI) is a 16-bit wide parallel port through which a host processor can directly access the CPUs memory space. The host device functions as a master to the interface, which increases ease of access. The host and CPU can exchange information via internal or external memory. The host also has direct access to memorymapped peripherals. The HPI is connected to the internal memory via a set of registers. Either the host or the CPU may use the HPI Control register (HPIC) to configure the interface. The host can access the host address register (HPIA) and the host data register (HPID) to access the internal memory space of the device. The host accesses these registers using external data and interface control signals. The HPIC is a memorymapped register, which allows the CPU access.
6.5.3 EXTERNAL MEMORY INTERFACE
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The external memory interface (EMIF) supports an interface to several external devices, allowing additional data and program memory space beyond that which is included on-chip. The types of memories supported include: Synchronous burst SRAM (SBSRAM) Synchronous DRAM (SDRAM) Asynchronous devices, including asynchronous SRAM, ROM, and FIFOs. The EMIF provides highly programmable timings to these interfaces. External shared-memory devices
6.5.4 MULTICHANNEL BUFFERED SERIAL PORT

The C62x/C67x multichannel buffered serial port (McBSP) is based on the standard serial port interface found on the TMS320C2000 and C5000 platforms. The standard serial port interface provides: Full-duplex communication Double-buffered data registers, which allow a continuous data stream Independent framing and clocking for reception and transmission Direct interface to industry-standard codecs, analog interface chips (AICs), and other serially connected A/D and D/A devices External shift clock generation or an internal programmable frequency shift clock Multichannel transmission and reception of up to 128 channels. An element sizes of 8-, 12-, 16-, 20-, 24-, or 32-bit. -Law and A-Law companding. 8-bit data transfers with LSB or MSB first. Programmable polarity for both frame synchronization and data clocks. Highly programmable internal clock and frame generation.
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Data communication between MCBSP and the devices interfaced takes place via two different pins for transmission and reception data transmit (DX) and data receive (RX) respectively. Control information in the form of clocking and frame synchronization is communicated via CLKX, CLKR, FSX, and FSR. 32-bit wide control registers are used to communicate MCBSP with peripheral devices through internal peripheral bus. CPU or DMA write the DATA to be transmitted to the Data transmit register (DXR) which is shifted out to DX via the transmit shift register (XSR). Similarly, receive data on the DR pin is shifted into the receive shift register (RSR) and copied into the receive buffer register (RBR). RBR is then copied to DRR, which can be read by the CPU or the DMA controller. This allows internal data movement and external data communications simultaneously.
6.5.5 TIMERS
The C62x/C67x has two 32-bit general-purpose timers that can be used to: Time events Count events Generate pulses Interrupt the CPU Send synchronization events to the DMA controller The timer works in one of the two signaling modes depending on whether clocked by an internal or an external source. The timer has an input pin (TINP) and an output pin (TOUT). The TINP pin can be used as a general purpose input, and the TOUT pin can be used as a general-purpose output. When an internal clock is provided, the timer generates timing sequences to trigger peripheral or external devices such as DMA controller or A/D converter respectively. When an external clock is provided, the timer can count external events and interrupt the CPU after a specified number of events.
6.5.6 MULTICHANNEL AUDIO SERIAL PORT
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The C6713 processor includes two Multichannel Audio Serial Ports (MCASP). The MCASP interface modules each support one transmit and one receive clock zone. Each of the MCASP has eight serial data pins which can be individually allocated to any of the two zones. The serial port supports time-division multiplexing on each pin from 2 to 32 time slots. The C6713B has sufficient bandwidth to support all 16 serial data pins transmitting a 192 kHz stereo signal. Serial data in each zone may be transmitted and received on multiple serial data pins simultaneously and formatted in a multitude of variations on the Philips Inter-IC Sound (I2S) format. In addition, the MCASP transmitter may be programmed to output multiple S/PDIF IEC60958, AES-3, CP-430 encoded data channels simultaneously, with a single RAM containing the full implementation of user data and channel status fields. The MCASP also provides extensive error-checking and recovery features, such as the bad clock detection circuit for each high-frequency master clock which verifies that the master clock is within a programmed frequency range.
6.5.7 POWER DOWN LOGIC

Most of the operating power of CMOS logic is dissipated during circuit switching, from one logic state to another. By preventing some or all of the chips logic from switching, significant power savings can be realized without losing any data or operational context. Power-down mode PD1 blocks the internal clock inputs at the boundary of the CPU, preventing most of its logic from switching, effectively shutting down the CPU. Additional power savings are accomplished in power-down mode PD2, in which the entire on chip clock structure (including multiple buffers) is halted at the output of the PLL. Power-down mode PD3 shuts down the entire internal clock tree (like PD2) and also disconnects the external clock source (CLKIN) from reaching the PLL. Wake-up from PD3 takes longer than wake-up from PD2 because the PLL needs to be relocked, just as it does following power up.
6.6 BPSK SIGNAL IN CODE COMPOSER STUDIO (CCS):-
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Binary Phase Shift Keying (BPSK) is implemented in C-programming in Code Composer Studio. In the BPSK the transmitter/ voice encoder section is implemented in real time signal. In the real time voice signal is given as input from microphone connected to mic input or through .Wav file which is given to appropriate DSK kit. In the BPSK technique all the necessary files are added to the C-code of the transmitter in order get activated of the transmission section. While transmitter section of the BPSK signal is created some of the files get created:1. File.pjt: to create and build a project named file 2. File.c: C source program 3. File.asm: assembly source program created by the user, by the C compiler, or by the linear optimizer 4. File.sa: linear assembly source program. The linear optimizer uses file.sa as input to produce an assembly program file.asm 5. File.h: header support file 6. File.lib: library file, such as the run-time support library file rts6700.lib 7. File.cmd: linker command file that maps sections to memory 8. File.obj: object file created by the assembler 9. File.out: executable file created by the linker to be loaded and run on the C6713 processor.
Some of the supporting files have to be added to C-code in order to get the code activated those are:ECE Department, Gitam University
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1. C6713dskinit.c: contains functions to initialize the DSK, the codec, the serial ports, and for I/O. It is not included with CCS. 2. C6713dskinit.h: header files with function prototypes. Features such as those used to select the mic input in lieu of line input (by default), input gain, and so on are obtained from this header file (modified from a similar file included with CCS). 3. C6713dsk.cmd: sample linker command file. This generic file can be changed when using external memory in lieu of internal memory. 4. Vectors_intr.asm: a modified version of a vector file included with CCSto handle interrupts. Twelve interrupts, INT4 through INT15, are available, and INT11 is selected within this vector file.They are used for interrupt-driven programs. 5. Vectors_poll.asm: vector file for programs using polling. 6. Rts6700.lib,dsk6713bsl.lib,csl6713.lib: run-time, board, and chip support library files, respectively. These files are included with CCSand are located in C6000\cgtools\lib, C6000\dsk6713\lib, and c6000\bios\lib, respectively.
Figure 6.3 Code Composer Studio I
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Figure 6.4 Code Composer Studio II
In BPSK the voice signal is passed through Mic input or Line IN input through one DSK kit and a stereo cable is used to pass the signal from one DSK kit of Transmitter section to another DSK Kit of the receiver section. At the same time Ccode is dumped into the DSK kit of the transmitter section from the system.
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In the receiver section side a C-Code is implemented and through DSK kit it is passed. At the same time the transmitted signal is passed to the receiver DSK kit. The receiver output is connected to the speaker. The input is low pass-filtered, decimated, and converted to an 8-bit stream. The bit stream is then modulated as a BPSK signal, and four output samples are generated for each bit. Each sample of the voice is a 16-bit integer. Because of sampling rate limitations, only the most significant 8 bits are used for transmission. This yields a resolution of 256 sample levels for the amplitude of the voice, which results in some degradation in the fidelity of the received signal. The procedure is to sample the voice, get the most significant 8 bits, then transmit one period of a sine wave for each bit. Each period of a sine wave is constructed by out putting to the D/A converter four values of the sine wave. Therefore, for one voice sample, 30 output samples are necessary. This is a severe limitation since the maximum sampling rate is 96kHz.The maximum sampling rate of the voice that we can implement is then 96 kHz/32, or 3kHz. The receiver uses eight samples to determine the phase of the phase-locked loop component allowing for a 48-kHz sampling rate by the transmitter. It can be verified that the receivers voice bandwidth is approximately 3kHz. To reconstruct a byte, the receiver must know where the frame starts for each byte. The transmitter periodically sends a synchronization sequence that is 1 byte long. This occurs once every 100 bytes. To achieve frame synchronization, a synchronization sequence is sent periodically by the transmitter. This sequence is 8 bits long and is detected by the receiver by correlating the incoming bits with the expected sequence. A trigger variable looks over the previously received 8 bits and counts the number of bits that match the synchronization sequence. If the trigger variable is equal to 8, then the synchronization sequence was detected. With 8 bits in the synchronization sequence, there are 256 possible values, so that there is a 1/256 possibility that the sequence will occur randomly. This is too high a probability, and since we are receiving bits at 12kHz (96kHz/eight
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samples per bit), we would expect the sequence to occur randomly about 47 times a second (12 kHz/256). To lower this rate, we make sure that successive synchronization sequences are separated by the expected interval before declaring that the sequence has actually been received. When a correlation is detected, the frame index is reset to zero. Since the receiver is reconstructing voice samples at a rate of 64kHz, it needs to interpolate received voice samples to provide the DAC with a sample every time and the original signal is obtained.
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RESULTS AND CONCLUSION
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RESULTS
In the project DSP PROCESSOR IMPLEMENTATION OF A MODEM FOR NARROW BANDWIDTH CHANNEL we had implemented different techniques and obtained results for them in mat lab and Code Composer Studio (CCS). In mat lab simulation are done for different techniques those are Binary Phase shift Keying (BPSK), Quadrature Phase Shift Keying (QPSK) and Quadrature Amplitude Modulation (QAM). For each technique outputs are shown above. Quadrature Phase shift keying (QPSK) technique simulation which are shown by taking digital bits and obtain the outputs for them and the same time for random bits also simulation has been done. For Quadrature Amplitude Modulation (QAM) technique simulation are done by taking all the internal blocks and obtained the output. Simulations which are done for 4QAM technique and outputs are shown for them. Simulations are shown in mat lab for this technique. In DSP Processor implementation we had done the Binary Phase Shift Keying (BPSK) technique. We had implemented the technique in C-Code which is done in Code Composer Studio (CCS) and it is implemented in DSK kit and obtained the output. Finally, I conclude that we had obtained the required outputs in both mat lab and Code Composer Studio (CCS).
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Results for BPSK modulation/demodulation technique for random bit stream in MATLAB. The plot shows the transmitted and received waveform of the BPSK technique. The Blue color signal shows the transmitted signal and Red color signal shows the received signal.
Transmitted and Received signals 3 Transmitted Waveform Received Waveform
-1
-2
-3
-4 0
10
20
30
40
50
60
70
80
90
100
Figure 7.1: BPSK Output waveform
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This plot shows the false and error detection region of the BPSK technique which is present. In the region the blue dots shows there are no errors in the region which means that the above obtained BPSK output waveform is correct.
Detections and decision regions 30
20
10
-10
-20
-30 -30
-20
-10
10
20
30
Figure 7.2: False and Error correction detection
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Results for BPSK modulation technique for random bit stream in MATLAB for .Wav file. This plot shows the received waveform and BPSK signal waveform in Amplitude versus Sample. In the received waveform graph it shows the variation in Amplitude with change in sample value.
R e c e ive d W a ve fo rm 100 Amplitude 50 0 -5 0 -1 0 0 -4 0 -3 0 -2 0 -1 0 10 20 30 40 S a m p le B P S K s ig n a l o f t h e fo rc e . w a v 0 50
1 0.5 Amplitude 0 -0 . 5 -1
Tra n s m it t e d B it s 1 1 1 0 1 0 0 0
1460 1470 1480 1490 1500 1510 1520 1530 1540 1550 1560 S a m p le
Figure 7.3: BPSK output waveform for Wav file
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Results for QPSK modulation technique for digital bit stream in MATLAB. The outputs which are shown for digital bits stream. The input waveform shows the digital bits in terms of Amplitude form. The In-Phase channel waveform shows the real part of the signal. The Quadrature channel waveform shows the imaginary part of the signal. This plot shows the input, in phase and quadrature waveform in terms of Amplitude versus Time.
I p t Wv f r n u aeom Amplitude 1 0 1
00 .0 2
00 .0 4
00 .0 6
00 .0 8
01 .0
01 .0 2
01 .0 4
01 .0 6
01 .0 8
02 .0
I - h s Ca n l Wv f r np a e h n e aeom Amplitude 1 0 1
00 .0 2
00 .0 4
00 .0 6
00 .0 8
01 .0
01 .0 2
01 .0 4
01 .0 6
01 .0 8
02 .0
Qa r tueCa n l Wv fom u da r h n e ae r Amplitude 1 0 1
00 .0 2
00 .0 4
00 .0 6
00 .0 8
01 .0 T e im
01 .0 2
01 .0 4
01 .0 6
01 .0 8
02 .0
Figure 7.4: QPSK Waveform
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This plot shows the in phase, quadrature and QPSK waveform for analog form in terms of Amplitude versus Time. The In-Phase channel modulated waveform in analog form. Quadrature channel modulated waveform shown in analog form. The QPSK waveform which is shown from the digital bits which are given.
Inphase Channel Modulated Waveform 1 Amplitude 0 -1
0.002
0.004
0.006
0.008
0.01
0.012
0.014
0.016
0.018
0.02
Quadrature Channel Modulated Waveform 1 Amplitude 0 -1
0.002
0.004
0.006
0.008
0.01
0.012
0.014
0.016
0.018
0.02
QPSK Waveform 2 Amplitude 0 -2
0.002
0.004
0.006
0.008
0.01 Time
0.012
0.014
0.016
0.018
0.02
Figure 7.5: I and Q Output Waveforms
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This plot shows the QPSK spectrum in terms of linear and Db form in terms of Magnitude and Fequency. In QPSK spectrum in linear form which shows the rise in magnitude at 1 KHz range and in the same way the QPSK spectrum in Db form there is a rise in lobe in magnitude at 1 KHz range.
-3
2 1.5 1 0.5 0
x 10
QPSK Spectrum (Linear)
Magnitude
500
1000
1500
2000 2500 Frequency QPSK Spectrum (dB)
3000
3500
4000
-50
Magnitude
-100
-150
-200
500
1000
1500
2000 Frequency
2500
3000
3500
4000
Figure 7.6: QPSK Spectrum Output
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This plot shows the digital and analog form of input data, in phase, Quadrature channel waveform and QPSK waveform. The QPSK output waveforms for random bit streams in digital and analog format. The input which are given in terms of signals. The input data, In-phase channel data and Q-channel data which is shown in digital form. The I channel modulated, Q channel modulated and QPSK waveform which are shown in digital form. The waveforms are shown in terms of Amplitude versus Time.
Input Data 2 Amplitude 0 -2 0 0.5 1 Amplitude 2 0
I Channel Modulated W aveform
-2 0.498
Time I Channel(one bit/symbol(phase)) Data 2 2 Amplitude 0 -2 0 0.5 1 Amplitude 0
0.502 Time Q Channel Modulated W aveform
0.499
0.5
0.501
-2 0.498
0.499
0.5
0.501
Time Q Channel(one bit/symbol(phase)) Data 2 2 Amplitude 0 -2 0 0.5 1 Time Amplitude 0 -2 0.498
0.502 Time
QPSK Output W aveform
0.499
0.5
0.501
0.502 Time
Figure 7.7: I and Q Waveforms of QPSK
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This plot shows the frequency domain plots and modulated carrier of QPSK in terms of Amplitude and Frequency. The frequency domain plot of the signal where it is the carrier signal of the QPSK technique. The same QPSK carrier modulated technique shown in terms of Db.
F re q u e n c y d o m a in p lo t s 1 A M P LIT U D E 0 .5 0 -0 .5 4 5 0 04 6 0 04 7 0 04 8 0 04 9 0 05 0 0 05 1 0 05 2 0 05 3 0 05 4 0 05 5 0 0 M o d u la t e d Q P S K c a rrie r 0 -2 0 -4 0 -6 0 -8 0 4 0 0 04 2 0 04 4 0 04 6 0 04 8 0 05 0 0 05 2 0 05 4 0 05 6 0 05 8 0 06 0 0 0 F R E Q U E N C Y (H z )
DB
Figure 7.8: Carrier Waveform
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This plot shows the received data, filtered I, Q channels and unfiltered I,Q channels of data in terms of Time. The received data of signal, unfiltered I,Q channel outputs where some internal noise or errors are present in the signal. The I,Q channel data outputs are filtered to some extent in order to avoid errors. The output phase deviation signal is also shown.
R eceiv output data ed 2 0 -2 1 0 -1
U nfiltered I C hannel O utput
0.5 Filtered I C hannel D ata
0.5 U nfiltered Q C hannel O utput
0.2 0 -0.2
1 0 -1
0.5 Filtered QC hannel D ata
0.5
0.2 0 -0.2 Radians 0 0.5 1
O utput phase dev iation(radians) lev els 5 0 -5
0.5 T e im
Figure 7.9: Received Output and filtered Waveforms
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This plot shows the Bit Error Rate (BER) for QPSK and BPSK techniques where the error rate is seen whether it is altered or not due to noise and distortions. The Bit Error Rate of the two modulation techniques where the error rate is seen whether it is altered or not due to noise and distortions. In figure we can seen the QPSK simulated output and QPSK theoretical output and BPSK theoretical output.
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Simulation of symbol and bit BER for QPSK and BPSK QPSK Simulated QPSKsymbol Theoretical BPSKbit Theoretical
10
-2
10 BER 10
-4
-6
10
-8
10
-10
6 SNR(dB)
10
12
Figure 7.10:Simulation BER for QPSK and BPSK
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Results for QAM technique for random sequence in MATLAB. This plot shows the 4-QAM constellation diagram. The 4-QAM signal constellation diagram. In the result total 8 bits of information is obtained. The bits are 00,01,10,11 are obtained.
The Signal Constellation 0.8 0.6 0.4 0.2 0 -0.2 -0.4 -0.6 -0.8 -0.8
-0.6
-0.4
-0.2
0.2
0.4
0.6
0.8
Figure 7.11: QAM Constellation Waveform
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This plot shows the pulse shaped signal of real part of sequence and power spectral density (PSD) is shows the power carried out by wave in terms of frequency. The symbols cannot be transmitted in right way. In order to transmit they need to be up sampled. The pulse shaping is in fact amplitude modulation. The spectral density represents the power carried out by the wave by multiplying with appropriate factor. The real part of pulse shaped signal represented in terms of Time and power spectral density of pulse shaped signal is represented in terms of PSD and Frequency.
R e a l P a rt o f s o m e o f th e P u ls e S h a p e d S ig n a l 1 0.5 0 -0 . 5 -1 0.0 5
0.1
0.25 0.3 0.35 0 .4 0 .4 5 Tim e (s e c ) P o w e r S p e c t ra l D e n s it y o f P u ls e S h a p e d S ig n a l
0.15
0.2
2 PSD
100
200
300 400 500 F re q u e n c y (H z )
600
700
800
Figure 7.12: Pulse shaped signal Waveform
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This plot shows the error over time of the signal and output of equalizer which is obtained. If the signal has slow decrease as there is change in frequency to low value shows the error over time is getting reduced. The output of equalizer shows the 4-QAM constellation signal output which shows there is no error in the equalizer.
E rro r o ve r t im e 0 .8 0 .6 0 .4 0 .2 0
500
1000
1500
2000
2500
3000
3500
O u t p u t o f E q u a liz e r 1 0.5 0 -0 . 5 -1 -1
Figure 7.13: Error over time waveform
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This plot shows the error of the signal and constellation waveform of technique. The result shows the rise value for spectrum and also the constellation diagram is obtained.
0.5
-0 . 5 1
1.5
2.5 1.5 1 0.5 0 -0 . 5 -1 -1 . 5
3.5
4.5
5 .5
-1
Figure 7.14: Constellation Waveform
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This plot shows the timing offset and the signal and convergent eye diagram of the technique which is obtained. The timing offset signal where for particular time signal is transmitted after the time offset signal cannot get transmitted. The convergent diagram shows the 4-QAM constellation diagram of the signal.
T im in g O ffs e t 0 .6 0 .4 0 .2 0 -0 . 2 0
500
1000
1500
2000
2500
3000
3500
4000
C o n ve rg e n t E y e D ia g ra m 1 0.5 0 -0 . 5 -1 -1
Figure 7.15: Timing Offset Waveform
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This plot shows the jitter waveform of the signal whether any noise or distortion is obtained. The Power Spectral Density of jitter shows the no distortions in the signal. The jitter waveform represents the whether there is noise or distortion in the signal. The waveform shows the signal at zero level which represents there is no distortion in the signal.
P S D o f t h e t im in g J it t e r 1 0 .8 0 .6 0 .4 0 .2 0 -0 .2 -0 .4 -0 .6 -0 .8 -1 0
50
100
150
200
250
300
350
400
Figure 7.16: Jitter Waveform
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This plot shows the received signal and decision device recovery signal which shows there is no error in the signal for transmitted and received signal. The signal is obtained at zero level. The decision recovery represents the there is no error in the transmitted signal and received signal when difference is taken between them. The optimal equalizer shows the output of equalizer whether there are errors or not.
re c e ive d s ig n a l 2 1 0 -1 -2 2 1 0 -1 -2
o p t im a l e q u a liz e r o u t p u t
1000 2000 3000 4000
1000 2000 3000 4000
c o m b in e d c h a n a n d o p t e q im p re s p d e c is io n d e vic e re c o ve ry e rro r 1 1 0 .5 0 0 -0 . 5 -1
0 .5
-0 . 5 0
1000 2000 3000 4000
Figure 7.17: Received signal and Decision device recovery error Waveform
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This plot shows the BPSK Technique output which is obtained in CCS where the display size, sampling rate values are changed. the C code output of BPSK technique represented in Code Composer Studio (CCS). The C-code is dumped in DSK kit TMS320c6713.The Line out pin through which the signal output is given to Line In with the help of stereo cable and demodulation takes place. In the Graphical display unit we will change the values of size, acquisition display, sampling rate of the technique. We obtained the required output for BPSK technique.
Figure 7.18: BPSK CCS OUTPUT
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CONCLUSION
Finally, The project DSP PROCESSOR IMPLEMENTATION OF A MODEM FOR NARROW BANDWIDTH CHANNEL is done using different techniques in mat lab and Code Composer Studio (CCS). In mat lab we had implemented in Binary Phase shift Keying (BPSK), Quadrature Phase shift keying (QPSK) and Quadrature Amplitude Modulation (QAM). In Code Composer Studio (CCS) we had implemented in C code. The C-code is implemented in DSK processor in TMS320C6713 and obtained required outputs. In the project we implemented different techniques for obtaining the outputs in mat lab and Code Composer Studio (CCS). For each technique we had done the simulation in mat lab and check the performance of the technique. All the techniques are done by considering the internal blocks and obtain the simulation for them. In mat lab we simulated the different techniques for getting the outputs for modulation and demodulation side. Simulation are done in mat lab and shown above for random bits operation of signals.
A simple transmission/reception scheme intended for voice transmission is consists of one microphone; a DSP board for voice acquisition, sampling, coding and modulation; a channel; a second DSP board for voice processing or signal decoding, demodulation and voice reconstruction; a loudspeaker; and finally two PCs that control each DSP. DSP processor TMS320c6713 used for obtaining of the output for C code of BPSK technique.
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APPENDIX
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APPENDIX I
This appendix serves the information about the formulas and the coding or programming section implementation that are accessed in mat lab. In this section I am going to show the mat lab code of BSPK modulation technique that is implemented for getting the output.
MAT LAB CODE

%BPSK_sim.m BPSK modulation and demodulation of a random bit stream clear; close all SNR = 0.5; %Signal to noise ratio E_s = 1; %Signal Power No = E_s^2/SNR; %Noise Power sig_n = sqrt(No/2); %Noise standard deviation w=2*pi*5; %Frequency t=0.01:0.01:0.2; %Time Vector N=200; %Number of Bits for ii=1:2 s(ii,:) = E_s*cos(w*t-2*pi*ii/2); end %Modulate a random bit stream signal = ceil(2*rand(1,N)); m_sig = []; for ii=1:N m_sig = [m_sig s(signal(ii),:)]; end plot(m_sig(1:100),':') %plot the transmitted signal n = sig_n*randn(1,length(m_sig)); %Create a noise vector r = m_sig + n; %Received Signal = s + n hold on; plot(r(1:100),'r') %Plot the received signal title('Transmitted and Received signals') legend('Transmitted Waveform', 'Received Waveform') sigma1 = E_s*cos(w*t); %Create basis functions sigma2 = E_s*sin(w*t); index = 1:length(t); for ii=0:N-1 %detect the signal X(ii+1) = sum(sigma1.*r(ii*length(t) + index)); Y(ii+1) = sum(sigma2.*r(ii*length(t) + index)); currFig = figure; %double buffer so window set(currFig,'DoubleBuffer','on'); %does not flash
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title('Detections and decision regions') hold on; axlim = 30; axis([-axlim axlim -axlim, axlim]) plot([0 0],[-axlim axlim], 'k') x=received_sig - signal; n_errors = sum(and(x,1)) p_error = n_errors / N wavwrite(m_sig,5500,16,'bpsk.wav') wavwrite(r,5500,16,'bpsk_n.wav')
%Plot the detections
%Calculate the percentage error %write the wav files
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APPENDIX II MATLAB CODE FOR WAV FILE

function bpskms() clear; close all [Y,FS,nbits]=wavread('theforce.wav'); %read the file Y = Y(length(Y)/2:length(Y)); sample_rate = 1000; %new sample rate X = decimate(Y,round(FS/sample_rate)); %resample at sample_rate X=round(X*128); %integers between -127/128 w=2*pi*5; %omega t=0.01:0.01:0.2; %time for ii=1:2 %BPSK signals s(ii,:) = sin(w*t-2*pi*ii/2); end for i=1:length(X) %create/output BPSK waveform if X(i)<0 bits=xor(num2bin(-X(i),8),[1 1 1 1 1 1 1 1]); %bits of each sample else bits=num2bin(X(i),8); end subplot(2,1,1) %plot voice signal if(i<50) hold off; plot(((-50:49)+i),[zeros(1,51-i) X(1:49+i)']); hold on; plot(i,X(i),'ro') else title('Received Waveform') %title of decimated voice ylabel('Amplitude') %y axis label xlabel('Sample') %x axis label axis([(-50 + i) (49 + i) min(X) max(X)]) for ii=1:8 %output BPSK waveform to plot->scope m_sig = [m_sig s(bits(ii)+1,:)]; %m_sig((i-1)*8*length(t) + ii*ti) = s(bits(ii)+1,:); subplot(2,1,2) %oscilloscope plot title('BPSK signal of theforce.wav') %title of plot ylabel('Amplitude') %y axis label xlabel('Sample') %x axis label legend(['Transmitted Bits ' sprintf('%d', bits)]) plot(length(m_sig)-100:length(m_sig),m_sig(length(m_sig)-100:length(m_sig))); axis([length(m_sig)-100 length(m_sig) -1.2 1.2]) %shift axis hold on; pause(0.01); %update @0.01s rate(plot last 100 bpsk samples) end end function s=num2bin(d,n) %creates array of bits if (nargin<2) %based on positive input d and length n n=1; end; a=dec2bin(d,n); s=zeros(1,n); for k=1:n s(k)=str2num(a(k)); end;
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APPENDIX III
This appendix serves the information about the next modulation technique QPSK that is used and the mat lab outputs that are obtained.
B.1 QPSK Simulation

In this section we will see the outputs of the QPSK mat lab code and the program. d=[1 1 0 0 1 0 1 0 1 1]; fb=500; fc=1000; Ac=1 ; fstart=0; fend=4000; N=size(d,2); if rem(N,2) == 1 N=N+1 d(N)=0 0 end N2=N/2; M=32; tb=1/fb;tc=1/fc; Nc=floor(M*tc/tb); %Nc=16 step=tb/M; for j = 1:N if d(j) == 1 for i = 1:M m((j-1)*M+i)=1; end else for i = 1:M m((j-1)*M+i)=-1; end end end for j = 1:N2 if d(j*2-1) == 1
%N = number of data bits. %N=10 %Ans=0 %N=11 % d(N)= 1 1 0 0 1 0 1
%M = number of samples per bit duration. %tb=0.0020;tc=1.000e-003 %Nc = number of samples per period of carrier. %step = sampling interval. %step=6.2500e-005 % 10 positions % 1 1 0 0 1 0 1 0 1 1 % 32 columns
% -1
-1
-1
-1
-1
%5 positions % odd numbers 1
1
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for i = 1:2*M % 64 columns for samples mi((j-1)*2*M+i)=1; si((j-1)*2*M+i)=Ac*cos(2*pi*(i-1)/Nc); end else for i = 1:2*M mi((j-1)*2*M+i)=-1; % 32 96 160 224 288 si((j-1)*2*M+i)=Ac*cos(2*pi*(i-1)/Nc+pi); end end if d(j*2) == 1
% (2 4 6 8 10 positions; 1
1)
for i = 1:2*M % 64 coulmns mq((j-1)*2*M+i)=1; sq((j-1)*2*M+i)=Ac*sin(2*pi*(i-1)/Nc); end else for i = 1:2*M mq((j-1)*2*M+i)=-1; sq((j-1)*2*M+i)=Ac*sin(2*pi*(i-1)/Nc+pi); end end end for k=1:M*N t(k)=(k-1)*step; % s(k)=si(k)+sq(k); end figure subplot(3,1,1) plot(t,m,'LineWidth',3) grid %xlabel('Time') ylabel('Amplitude') title('Input Waveform') subplot(3,1,2) plot(t,mi,'LineWidth',3) grid %xlabel('Time') ylabel('Amplitude') title('In-phase Channel Waveform') subplot(3,1,3) plot(t,mq,'LineWidth',3) grid xlabel('Time') ylabel('Amplitude')
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title('Quadrature Channel Waveform') figure subplot(3,1,1) plot(t,si) grid %xlabel('Time') ylabel('Amplitude') title('Inphase Channel Modulated Waveform') subplot(3,1,2) plot(t,sq) grid %xlabel('Time') ylabel('Amplitude') title('Quadrature Channel Modulated Waveform') subplot(3,1,3) plot(t,s) grid xlabel('Time') ylabel('Amplitude') title('QPSK Waveform') %Spectrum of QPSK M1=64; %M1 = number of points per lobe. fstep=fb/M1; %fstep = freq. step. %7.8125 Nf=floor((fend-fstart)/fstep); %Nf = total number of freq. points computed. Nf=512 for i = 1:Nf f(i)=(i-1)*fstep+fstart; %fi= 1.0e+003 if f(i) == fc S(i)=Ac^2*tb; %0.0020 else S(i)=(Ac^2*tb)*(sin(pi*(f(i)-fc)*2*tb)/(pi*(f(i)-fc)*2*tb))^2; %0.0020*0 end end for i = 1:Nf dBS(i) = 10*log(S(i)); %62.1461 DB value is obtained if dBS(i) < -200 dBS(i)=-200; end end figure subplot(2,1,1) plot(f,S) grid xlabel('Frequency') ylabel('Magnitude') title('QPSK Spectrum (Linear)') subplot(2,1,2) plot(f,dBS) grid xlabel('Frequency')
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ylabel('Magnitude') title('QPSK Spectrum (dB)') end
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APPENDIX IV
MATLAB CODE FOR QPSK:clear; fcarr=5e3; N=8; fs=20*1e3; Fn=fs/2; Ts=1/fs; T=1/N; randn('state',0); td=[0:Ts:(N*T)-Ts]'; data=sign(randn(N,1))'; data1=ones(T/Ts,1)*data; data2=data1(:); -------------------------------------------------------------------------------------------%display input data bits in command window -------------------------------------------------------------------------------------------data_2=data2'; data_2=data_2 >0; Transmitted_data_bits=data_2(1:(fs)/N:end) ------------------------------------------------------------------------------------------%Serial to parallel (alternating) ------------------------------------------------------------------------------------------tiq = [0:Ts*2:(N*T)-Ts]'; symbols(transpose) bs1=data(1:2:length(data)); symbols=ones(T/Ts,1)*bs1; Isymbols=symbols(:); bs2=data(2:2:length(data)); symbols1=ones(T/Ts,1)*bs2; Qsymbols=symbols1(:);
% Carrier frequency(Hz) % Number of data bits(bit rate) % Sampling frequency % Nyquist frequency % Sampling time = 1/fs % Bit time % Keeps PRBS from changing on reruns % Time vector(data)(transpose) %transpose
%transpose
Time
vector
for
and
%odd %I_waveform %even %Q_waveform

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%generate carrier waves twopi_fc_t=(1:fs/2)*2*pi*fcarr/fs; a=1; %phi=45*(pi/180) phi=0; cs_t = a * cos(twopi_fc_t + phi); sn_t = a * sin(twopi_fc_t + phi); cs_t=cs_t';%transpose sn_t=sn_t';%transpose si=cs_t.*Isymbols; sq=sn_t.*Qsymbols; sumiq=si+sq; sumiq=.7*sumiq; ht=(1/rc).*exp(-tiq/rc); ycfo=filter(sig_rx,1,ht)/fs; Bit_rate=N QFilterfreg_3dB=1/(2*pi*rc) pt1=1.7e-8; triggers H=5;%(volts) L=0;%(volts) LEN=length(ycfo); for ii=1:LEN; if ycfo(ii)>=pt1; setting pv1i(ii)=H; else; pv1i(ii)=L; end; end ; po1i=pv1i; %pulse out=pulse voltage %I pulse voltage %correlated output(ycfo) going above pt1 threshold %sets level where threshhold device comparator %multiply I bitstream with cosine %multiply Q bitstream with sine %transmitter output %reduce gain to keep output at +/- one %impulse response %phase error
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pt2=1.7e-8; triggers H=5;%(volts) L=0; LEN=length(ycfo1); for ii=1:LEN; if ycfo1(ii)>=pt2; setting pv2q(ii)=H; else; pv2q(ii)=L; end; end ; po1q=pv2q; bit1=sign(po1q); bit2=sign(po1i); bit3=bit1 >0; bit4=bit2 >0; bitout=[bit3]; bitout1=[bit4]; bitout2=[bitout]; x=1128;%x=fs/N; . fs:x=(8*2641)-20000=1128 bitout2=bitout2(1:(fs+x)/N:end); bitout2=[bitout2]; bitout3=[bitout1]; bitout3=bitout3(1:(fs+x)/N:end); bitout3=[bitout3]; bitfinalout=[bitout2;bitout3]; bitfinalout=bitfinalout(1:end);
%sets level where threshhold device comparator
%(volts)
%correlated output(ycfo1) going above pt2 threshold % Q pulse voltage
%pulse out=pulse voltage %0 and 1 %0 and 1 %0 and 1 %0 and 1
-----------------------------------------------------------------------------------ECE Department, Gitam University
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%display received output data bits in command window ----------------------------------------------------------------------------------Received_data_bits=bitfinalout %Received data output data1a=ones(T/Ts,1)*bitfinalout; bitfinal1=data1a(:); bitfinal1=bitfinal1-mean(bitfinal1); bitfinal1=2*bitfinal1;%get to +/- 1 figure(1) subplot(3,2,1) plot(td,data2) axis([0 1 -2 2]); grid on xlabel('Time') ylabel('Amplitude') title('Input Data') subplot(3,2,3) plot(tiq,Isymbols) axis([0 1 -2 2]); grid on xlabel(' Time') ylabel('Amplitude') title('I Channel(one bit/symbol(phase)) Data') subplot(3,2,5) plot(tiq,Qsymbols) axis([0 1 -2 2]); grid on xlabel(' Time') ylabel('Amplitude') title('Q Channel(one bit/symbol(phase)) Data') subplot(3,2,2) plot(tiq,si)
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axis([.498 .502 -2 2]); grid on xlabel(' Time') ylabel('Amplitude') title('I Channel Modulated Waveform') subplot(3,2,4) plot(tiq,sq) axis([.498 .502 -2 2]);
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APPENDIX V
This appendix serves the information about the next modulation technique QAM that is used and the mat lab outputs that are obtained. In this section we will see the QAM Matlab code:clear all close all n=input('enter largest equalizer delay (try 3)= '); el=n+1; --------------------------------------------------------------------------------------------%maximum delay candidate (> ch dim + eq max delay); --------------------------------------------------------------------------------------------alph=chdim+n+1; --------------------------------------------------------------------------------------------%select training sequence length --------------------------------------------------------------------------------------------p=input('enter training/source sequence length (try 4000) = '); --------------------------------------------------------------------------------------------%set up time vector --------------------------------------------------------------------------------------------time=[1:p]; --------------------------------------------------------------------------------------------%make Toeplitz input matrix for channel --------------------------------------------------------------------------------------------toprowc=fliplr(s(1:chdim)); lcolc=s(chdim:p).'; Ach=toeplitz(lcolc,toprowc); sg=input('enter sinusoidal interferer gain (try 0.1) = '); om=input('enter sinusoidal interferer frequency (try 1.4) = '); ng=input('enter uniform channel noise -/+ max magnitude (try 0.04) ='); tpars=sqrt((1-ng*(ng/3)-0.5*sg*sg)/(rawtp'*rawtp))*rawtp;
88
rsig=Ach*tpars; d=zeros(size(rsig)); for i=1:length(rsig), d(i,1)=sg*sin(om*(i-1))+ng*2*(rand-0.5); end r=(rsig+d)'; --------------------------------------------------------------------------------------------%calculate MMSE equqlizer --------------------------------------------------------------------------------------------cosvec=cos(om*[0:(el-1)])'; V=toeplitz(cosvec); isnr=(ng^2)/3; C=convmtx(tpars,el); %interference matrix %inverse of source to noise variance ratio %channel convolution matrix
CC=C'*C+isnr*eye(el)+0.5*(sg^2)*V; foptmat=pinv(CC)*C'; %pseudoinverse of (C'C+ isnr*I) [mmse,optind]=min(diag(eye(size(C*foptmat))-C*foptmat)); %value and index of min entry of I - C*foptmat mmse_w_opt_delay=mmse delt=optind-1; optimum_delay=delt fopt=foptmat(:,optind); combo=conv(fopt,tpars); %channel and MMSE equalizer combination toprowrbar=fliplr(r(alph-chdim-n+2:alph-chdim+2)); lcolrbar=r(alph-chdim+2:p-chdim+1); Rbar=toeplitz(lcolrbar,toprowrbar); y=Rbar*fopt; subplot(2,2,4) axis('normal') ww=[0:pi/100:pi]; [fradin]=freqz(conv(tpars,thet(:,strt)),1,ww); [fras]=freqz(conv(tpars,thet(:,itno)),1,ww); plot(ww,20*log10(abs(fras)),'.', ww,20*log10(abs(frcod)),'-',...
89
ww,20*log10(abs(fradin)),'--') title('Combo Freq Resp Magnitude') ylabel('db') xlabel('radians') figure(3) hold on axis equal plot(thet(1,strt:itno-1),thet(2,strt:itno-1)) plot(thet(1,strt),thet(2,strt),'o') plot(thet(1,itno),thet(2,itno),'s') xlabel('f0') ylabel('f1') hold off adapt=input('enter 0 to stop or 1 to adaptively equalize = '); end %adap fin: dot, adap init: dash, opt:solid
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APPENDIX VI
This appendix serves the information about C Code of BPSK technique in Code Composer studio (CCS) software.
C CODE OF BPSK TECHNIQUE

//BPSK_sim.c BPSK simulation Mod/Demod. DSK Output sequence-->Input #include "dsk6713_aic23.h" //codec-DSK support file #include <math.h> #include <stdio.h> Uint32 fs=DSK6713_AIC23_FREQ_16KHZ; //set sampling rate #define PI 3.1415926 #define N 16 //# samples per symbol #define MAX_DATA_LENGTH 10 //size of mod/demod vector #define STABILIZE_LEN 10000 //# samples for stabilization float phi_1[N]; //basis function 1 short r[N] = {0}; //received signal int rNum=0, beginDemod=0; //# of received samples/demod flag short encSeqNum=0, decSeqNum=0; //# encoded/decoded bits short encSymbolVal=0,decSymbolVal=0; //encoder/decoder Symbol Index short encodeSeq[MAX_DATA_LENGTH]={1,0,1,1,0,0,0,1,0,1};//encoded sequence short decodeSeq[MAX_DATA_LENGTH]; //decoded sequence short sigAmp[2] = {-10000, 10000}; //signal amplitude short buffer[N*(MAX_DATA_LENGTH+3)]; //received vector for debugging short buflen=0, stabilizeOutput=0; interrupt void c_int11() //interrupt service routine { int i, outval= 0; short X = 0; if(stabilizeOutput++ < STABILIZE_LEN) //delay start to Stabalize { r[0] = input_sample(); output_sample(0); return; } if(encSeqNum < MAX_DATA_LENGTH) //modulate data sequence { outval = (int) sigAmp[encodeSeq[encSeqNum]]*phi_1[encSymbolVal++]; if(encSymbolVal>=N) {encSeqNum++; encSymbolVal=0; } output_sample(outval); }
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else output_sample(0); //0if MAX_DATA_LENGTH exceeded r[rNum++] = (short) input_sample(); //input signal buffer[buflen++] = r[rNum - 1]; if(beginDemod) //demod received signal { if(decSeqNum<2 && rNum==N) { //account for delay in signal decSeqNum ++; rNum = 0; } if(rNum == N) //synchronize to symbol length { rNum = 0; for(i=0; i<N; i++) //correlate with basis function X += r[i]*phi_1[i]; decodeSeq[decSeqNum-2] = (X >= 0) ? 1: 0; //do detection if(++decSeqNum == MAX_DATA_LENGTH+2) //print received sequence { for(i=0; i<decSeqNum-2; i++) printf("Received Value: %d\n", decodeSeq[i]); exit(0); } } } else { beginDemod = 1; rNum = 0; } } void main() { int i; comm_intr(); //init DSK, codec, McBSP for(i=0; i<=N; i++) phi_1[i] = sin(2*PI*i/N); //basis function while(1); //infinite loop }
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DSP Processor Implementation of A Modem For Narrow Bandwidth Channel

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DSP PROCESSOR IMPLEMENTATION OF A MODEM FOR NARROW BANDWIDTH CHANNEL

ECE Department, Gitam University