J Mater Sci: Mater Electron (2017) 28:12617–12629

DOI 10.1007/s10854-017-7086-0

Solid-state growth kinetics of intermetallic compounds

in Cu pillar solder flip chip with ENEPIG surface finish
under isothermal aging
Kelvin P. L. Pun1,2 · M. N. Islam1 · Chee Wah Cheung1 · Alan H. S. Chan2 

Received: 9 December 2016 / Accepted: 5 May 2017 / Published online: 17 May 2017
© Springer Science+Business Media New York 2017

Abstract  Electroless Ni/electroless Pd/immersion Au 1 Introduction

(ENEPIG) constitutes a promising metallization to replace
the conventional ENIG or Ni/Au for 3D IC integrated The flip chip market is mainly driven by the emerging Inter-
module and optoelectronic packaging. Different ENE- net of Things (IoT): a network of physical devices, vehicles,
PIG plating thicknesses with copper pillar solder joints buildings, and other physical objects that include embed-
are subjected to thermal aging at 150 °C to investigate the ded electronics, software, sensors, actuators, and network
intermetallic compounds (IMCs) formation and growth. connectivity. With the increase in packaging technology
Due to low temperature solid-state bonding, both Pd and solutions from standard package types to advanced ones,
Au layers do not completely diffused into Sn matrix and such as fan in and fan out WLP, POP, MCM and SiP, the
participated in the interfacial reactions to form (Pd,Au)Sn4 flip chip constitutes a particularly promising technology.
IMCs phase. (Pd,Au)Sn4 IMCs based on ­PdSn4 phase with As semiconductor technology advances, the compo-
dissolved Au, exhibits high growth rate and substantial nent size is inevitably miniaturizing. As a result, buss-less
consumption of Sn from solder. Upon increasing the aging design and electro-less plating processes are the emerg-
time, it is found that (Cu,Ni)6Sn5 IMCs and (Pd,Cu,Au) ing technologies to fulfill the requirement of high routing
Sn4 phase form at interface and follows a diffusion control density [1]. Electro-less nickel/immersion gold (ENIG) is
mechanism, which weakened the solder joint and caused commonly used in microelectronic packaging industries
brittle fracture in a die peel test. (Cu,Ni)6Sn5 IMCs growth due to process simplification, slow IMCs growth rate, and
rate increases with decreases Pd thickness. Therefore, the good solder wetting behavior. Although ENIG with devel-
types of IMCs formation, growth rate, and reliability of Cu oped thickness of gold is a viable finish for wire bonding,
pillar joint strongly depend on bonding temperature, Au concerns remain regarding issues of corrosion of nickel and
and Pd thicknesses, and solder volume. Based on this study, impact resistance [2]. Recently, surface finish by the ENE-
the authors recommend suitable ranges of Au and Pd layer PIG process has gained popularity in the electronic indus-
thicknesses for reliable Cu pillar solder joints. tries due to the electro-less plating process, lower cost, and
high reliability in both wire bonding and soldering appli-
cations [3, 5]. Ratzker et al. [4] reported that compared to
ENIG and Ni/Au, ENEPIG/solder joint has been shown to
constitute a stronger solder interconnection. Specifically, a
minimum 5% higher pull and shear force is needed for the
failure of the ENEPIG/solder (SAC3xx) joint than the Ni/
* Kelvin P. L. Pun Au and ENIG solder joint.
polpun2222‑[email protected]
Cu pillar solders are currently being adopted for 3D IC
1
Compass Technology Company Limited, Suite 10, Chiaphua integration modules. Figure 1 shows the application of Cu
Centre, 12 Siu Lek Yuen Rd., Shatin, NT, Hong Kong pillar solders in 3D IC integration modules. Cu pillar sol-
2
Department of SEEM, City University of Hong Kong, 83 Tat ders with different sizes (10–80  μm) are utilized for the
Chee Avenue, Kowloon, Hong Kong interconnection between chip to chip, chip to interposer,

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12618 J Mater Sci: Mater Electron (2017) 28:12617–12629

Fig. 2  Schematic sketch of the substrate and Cu pillar solder

immersion Ag surface finish layer exhibits very differ-

ent interfacial reactions in comparison with that undergo-
ing the reflow process [14]. ENEPIG surface finish is used
in UBM of the package substrate. Therefore, smaller sol-
der volume and different thicknesses of Au, Pd, and Ni in
Fig. 1  Chip connection (C2) with micro-bumps in 3D IC integration ENEPIG should induce a significant effect on the interfa-
packages using: a laminated rigid substrate; and b flexible substrate cial microstructure during solid-state bonding, as well as
mechanical properties and reliability of solder joints, which
and interposer to packaging substrate. This is considered to has not yet been evaluated.
constitute the next generation approach because of several ENEPIG surface finish with different Au and Pd thick-
excellent properties, such as high thermal conductivity, fine nesses were selected and used as test vehicles for this
pitch, low electro-migration effect, high standoff height, study. Observations of microstructure evolution and IMCs
and high input/output (I/O) density. Chip connection (C2) growth at interfaces between ENEPIG/flip chip Cu pillar
with Cu pillar solders started being used in flip chip pack- solder systems were thoroughly investigated after isother-
ages a few years ago due to their good electrical and ther- mal aging. The key to achieving this is to determine the
mal performance [6, 7], which allows for finer bond pitch major factors influencing the interfacial microstructure and
down to 50  μm. Several researchers have reported the mechanical properties of Cu pillar solder joints. The aims
excellent electro-migration performance of copper pillar are to: (1) identify a suitable range of ENEPIG plating
bump flip chip packages [8, 9]. Electrical reliability issues thicknesses for the Cu pillar solder /ENEPIG system; and
can also be solved with this structure because Cu pillars (2) determine the key elements that significantly dominate
exhibit superior electrical and thermal conductivity [10, the microstructure and properties of solder joints during
11]. However, with the shrinking dimension of bumps and isothermal aging.
solders, the concentration of metallization elements in the
solder joint increases and becomes influential in the IMCs
formation. Therefore, the small amount of solder used, as 2 Experimental procedures
compared with conventional solder bumps, severely dimin-
ishes the electrical–mechanical properties and reliability of To replicate the future miniaturization of modules, the die
the joint. Low-temperature solid-state thermal-compression with Cu pillar solder at 80 μm pitch was selected in all test
bonding, rather than reflow, is a commonly used method vehicles. The die size is 3.28  mm × 3.28  mm. The copper
in flexible printed-circuit-boards and opto-electronic pack- pillar and solder cap height were measured to be 15–20 and
aging [12, 13]. During solid-state bonding, the solders do 15–20  μm, respectively, prior to bonding (Fig.  2). A flex-
not melt, and consequently the surface finish layers do not ible substrate pattern (Fig.  3) was designed to match the
dissolve and remain on the Cu layer. This means that the die bump to facilitate the study of high density flip chip
surface finish layers participate in the interfacial reactions interconnections.
during bonding and subsequent solid-state aging. Lin et al. The solder mask define pad on flexible substrate was
has reported that this kind of solder joint with an existing used for ENEPIG surface finish. Different Au and Pd

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J Mater Sci: Mater Electron (2017) 28:12617–12629 12619

Fig. 3  Test vehicle pattern

design. a Flexible substrate; and
b sample after die was attached

Table 1  Average Au and Pd thickness on Ni layer of the pad flux. Indium POP flux was utilized for a good solder con-
Sample Au thickness (μm) Pd thickness (μm)
nection. Flip chip bonder FC3000 with a placement accu-
racy of ±2  μm was used. During the process of bonding,
A Low Au (0.04) Low Pd (0.05) a chip was picked up and aligned face-down to bumps on
B Medium Au (0.07) Low Pd (0.05) a heated substrate. When the bonding attachments press
C High Au (0.2) Low Pd (0.05) down, the solder micro-bump deforms and makes intense
D Medium Au (0.07) Medium Pd (0.2) contact with the pads of bonding, causing wetting of the
E High Au (0.2) Medium Pd (0.2) solder. For bonding, a bonder is required that is capable
F Medium Au (0.07) High Pd (0.4) of generating a greater peak temperature with a force of
G High Au (0.2) High Pd (0.4) approximately 100 N/bumps and a greater extent of paral-
lelism between substrate and chip. This is the reason that
we selected the solid-state bonding process instead of the
thicknesses were designed to elucidate the interfacial reac- global reflow process to eliminate the factor due to sub-
tions and IMCs formations during isothermal aging. ENE- strate flatness. For greater yield of bonding, the tempera-
PIG chemical is provided by Dow Chemical. A nickel- ture and bonding force are required to be well controlled.
phosphorus layer was electrolessly plated on the top and In order to avoid damaging the semiconductor material, the
side surfaces of the plurality of copper traces. The electro- bonding force must be graduated, since excessive bond-
less Ni-P deposit on all test vehicles was amorphous and ing force may cause cracks in the passivation of the chip
non-crystalline with a non-magnetic structure. A palladium and sometimes bridging of the bumps in fine pitch due to
layer was electrolessly plated on the nickel-phosphorus over-deformation of the micro-bumps. The actual bonding
layer, and a gold layer was immersion plated on the pal- temperature between the die solder bump and flex substrate
ladium layer. interfaces was measured by using NR-500 Series. Figure 4
The average thicknesses of Au and Pd are shown in shows the actual bonding temperature of 207 °C, which was
Table  1, which are measured using XRF (Fischercope used for bonding of all samples.
X-ray, Model: XDVM-uSD). After 0.07 μm immersion Au Figure 5 shows the assembly of the C2 process flow of
plating on the Pd layer, a set of samples were subjected to all samples. Samples were prepared for this study, as shown
thick Au plating to increase the Au thickness up to 0.2 μm in DOE Table  1. The die-attached samples after bonding
to discern the effect of Au in the Cu pillar solder joint. The were inspected using an X-Ray machine to check for mis-
average electro-less Ni(P) thickness was measured to be alignment and other visual anomalies. Underfill dispensing
1 μm for this study. and curing were performed to avoid any damage of joints.
In the experiment, samples were aligned onto an alu- Samples were subjected to isothermal aging at 150 °C up to
minum carrier with the assistance of a specifically designed 1000 h according to JEDEC standard test method A 103-A
jig, and firmly secured by adhesive tape. The aim was to (JESD22-A103-A) to elucidate the effect of the new Pd-
maintain a good flatness of substrate during bonding. The containing interfacial IMCs during isothermal aging.
flatness of the unit is measured to below 10 μm. Here, interfacial reaction and micro-structure analysis of
A 50-μm thick stencil was designed to be used on a the solder joints were investigated thoroughly after isother-
momentum screen printing machine for the application of mal aging. Samples were cut after the test and cross-section

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12620 J Mater Sci: Mater Electron (2017) 28:12617–12629

by using a normal grinding and polishing procedure. Cross-

section samples were Au coated, and SEM/EDAX analy-
sis was performed for microstructural analysis. A die peel
test was also conducted to verify the failure mode of solder
joints between the die and the substrate.

3 Results and discussion

3.1 Microstructure immediately after bonding

Figure  6 shows the microstructure of the C2 bump solder

joints of each ENEPIG leg as bonded just after solid-state
bonding. We analyzed the microstructure of intermetallic
growth on the Cu pillar solder interconnection from both
Fig. 4  An actual bonding temperature of 207 °C was used for bond-
ing of all samples the packaging substrate side and the chip side.
On the substrate side, the Pd–Au–Sn IMCs phase is
formed at the interface in all ENEPIG thickness legs,
due to the short time solid-state reaction during low tem-
perature bonding, which does not allow the Pd and Au
layer to be fully diffused into the solders. For the high Pd
(0.4  μm) sample, the unreacted Pd layer still remained on

Fig. 6  SEM images show the IMCs formation after bonding. a Sam-

ple A, low Au (0.04 μm) and low Pd (0.05 μm); b sample B, medium
Au (0.07 μm) and low Pd (0.05 μm); c sample C, high Au (0.2 μm)
and low Pd (0.05  μm); d sample D, medium Au (0.07  μm) and
medium Pd (0.2 μm); and e sample G, high Au (0.2 μm) and high Pd
Fig. 5  Process flow of chip connection (C2) (0.4 μm)

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top of the Ni(P) layer (Fig.  6e). The composition of this

phase is determined to be 10–18 at.% Pd, 5–8 at.% Au and
76–81  at.% Sn according to EDX analysis. Since ­AuSn4
and ­PdSn4 produce the same orthorhombic crystal [15] and
base on the elemental ratio of EDX, the composition of this
phase is identified as (Pd,Au)Sn4. In the case of low Pd
thickness samples A and B, a trace amount of Ni (2–4 at.%)
is found within the IMCs near the Ni(P) layer, because of
the presence of the Ni(P) layer underneath the thin (Pd,Au)
Sn4 IMCs. It is important to note here that no (Pd,Ni)Sn4
IMCs and (Cu,Au)6Sn5 IMCs are identified at the inter-
face immediately after the solid-state reaction. (Pd,Au)
Sn4 IMCs is a new IMCs phase with high growth rate and
consumes more Sn from solder. The isothermal section
of the ternary Pd-Sn-Au system is shown in Fig.  7. The
Pd–Au–Sn phase containing higher at% of Sn is formed at
the left corner (Sn).
The layer type (Pd,Au)Sn4 IMCs exhibit a good bonding
to Cu pillar solder for the interconnection between the chip Fig. 8  Isothermal section of the Sn–Cu–Au ternary system at 200 °C
and the packaging substrate, and also protect the underlying [18]
Ni(P) and Cu layer from chemical reaction during bonding.
Therefore, the remaining Ni(P) and Cu thicknesses on all ­Cu6Sn5 IMCs is found on all medium—high Au thickness
ENEPIG samples are found to be intact after bonding. samples (Fig. 6b–e). The phase comprises 10–15 at.% Au,
Some Au atoms have partially diffused into the solder 37–45  at.% Cu and 44–49  at.% Sn, which is likely to be
within a short time and formed ­AuSn4 IMCs, and uni- ­Cu6Sn5 phase containing Au. Yen et al. [18] reported a ter-
formly distributed into the tiny solder bump. On the chip nary Sn–Cu–Au ternary system, there exists two complete
side, scallop-type ­Cu6Sn5 IMCs formed at the Cu pillar/sol- solid solubility phases such as A ­ u5xCu6(1−x)Sn5, (x: 0–1)
der interface because ­Cu6Sn5 has a lower activation energy and (Cu,Au) phase, where A ­ u5xCu6(1−x)Sn5 is the com-
compared to ­Cu3Sn IMCs [16, 17]. The IMCs phase is plete solid solution of AuSn and ­Cu6Sn5 IMCs phases and
composed of 1–3 at.% Au, 43–46 at.% Sn, and 52–56 at.% is marked as χ IMCs phase (Fig.  8). Similar results also
Cu, which is defined as ­Cu6Sn5 IMCs (Fig. 8). In addition, reported by Karlsen’s et al. [19]. The thicknesses of ­Cu6Sn5
the presence of thin layer Au containing IMCs adjacent to IMCs (2.01  μm, average) are similar in all ENEPIG sam-
ples. For the high Pd (0.4  μm) sample, thicker (Pd,Au)
Sn4 IMCs thickness (2.61 μm) is observed after solid-state
reaction (Fig.  6e). Therefore, the growth rate of (Pd,Au)
Sn4 IMCs is higher than that of the C ­ u6Sn5 IMCs. For the
low Pd sample, ­Cu6Sn5 IMCs thickness is higher than the
(Pd,Au)Sn4 IMCs (1.15  μm) thickness because of thin Pd
(0.05 μm) thickness (Fig. 6a).
The Au atomic percentage in both sides of IMCs has
increased due to thicker Au. For example, when the Au
thickness is increased from 0.04 to 0.2 μm, the Au atomic
percentage in Cu–Au–Sn IMCs on the chip side is increased
from 7 to 18%. However, the Au percentage in (Pd,Au)Sn4
IMCs at the packaging substrate side did not change signifi-
cantly. The needle-like ­AuSn4 IMCs with a small amount
of Cu are formed within the solder and on top of interfacial
IMCs on the thick Au (0.2 μm) sample (Fig. 6c). Therefore,
the faster diffusion of Au from the substrate pad is respon-
sible for promoting brittle IMCs on the chip side.
As bonded, interfacial (Pd,Au)Sn4 IMCs thickness is
Fig. 7  Isothermal section of the Au–Pd–Sn system at room tempera- increased linearly with the increase of Pd thickness. As
ture [20] shown in Fig.  6a, e, the IMCs thickness of the low Pd

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12622 J Mater Sci: Mater Electron (2017) 28:12617–12629

(0.05  μm) sample is two times thinner than the high Pd For high Pd (0.4  μm) and medium Au (0.07  μm) sam-
(0.4  μm) sample after bonding. The formation of (Pd,Au) ples, failure occurs within the (Pd,Au)Sn4 IMCs on the sub-
Sn4 IMCs is mainly dominated by the Pd layer, due to the strate side. The fracture surface is smooth, indicating brit-
smaller activation energy necessary for the growth of the tle IMCs failure (Fig.  9b). Generally, brittle IMCs failure
(Pd,Au)Sn4 IMCs phase in the Sn-Ag-Cu solder /Au/Pd/ degrades the strength and reliability of the solder joints.
Ni(P) system. Based on this fracture surface analysis, it can be concluded
The absence of (Pd,Ni)Sn4 and (Cu,Ni)6Sn5 IMCs at the that the shear strength of the high Pd sample is lower than
interface of all ENEPIG samples is also noted. This is due the low Pd thickness sample [21, 22].
to the (Pd,Au)Sn4 IMCs layer preventing diffusion of Sn
and Cu from solder to react with the Ni(P) layer. No Kirk- 3.3 Microstructure after isothermal aging
endall void or spalling of interfacial IMCs is observed in
all ENEPIG thickness samples after solid-state bonding. Figure  10 shows the microstructure of the C2 bump solder
However, the change in IMCs thickness and morphology joints of each ENEPIG leg after 200 h of isothermal aging.
depends significantly on Pd and Au thickness (Fig. 6c, e). On the substrate side, it is important to note that new addi-
tional (Cu,Ni)6Sn5 IMCs have formed and are clearly vis-
3.2 Failure mode after die peel test ible on top of the Ni(P) layer in all ENEPIG thickness sam-
ples, indicating that the Ni(P) layer has started a solid-state
For die peel test, flex substrate is attached on the fixed chemical reaction with Sn and Cu during 200  h of isother-
plate, and then the die is peeled off from the substrate. mal aging. The (Cu,Ni)6Sn5 is composed of 15–20 at.% Ni,
After the die is peeled off, fracture surfaces are analyzed by 35–47  at.% Cu, and 42–46  at.% Sn. Young et  al. [21] also
EDX analysis. Die shear strength is not presented here due reported similar results. Due to the diffusion of Cu and Sn
to using underfill encapsulation just after die bonding to atoms from solder, the interfacial (Pd,Au)Sn4 IMCs have
avoid any damage. Figure 8 shows the backscattered elec- been transformed into more stable (Pd,Cu,Au)Sn4 IMCs
tron SEM images of fracture surface on the die side. In the on top of (Cu,Ni)6Sn5 IMCs in all samples (Table  2). The
case of low Pd (0.05 μm) and low Au (0.05 μm) samples, composition of (Pd,Cu,Au)Sn4 IMCs phase is 3–7  at.%
a mixed mode of failure is observed on the fracture sur- Au, 7–13  at.% Pd, 4–7  at.% Cu, and 74–82  at.% Sn. More
face. Mainly, (Pd,Au,Ni)Sn4 IMCs and (Pd,Au)Sn4 IMCs importantly, the low Pd sample (0.05  μm) exhibits a thin-
are identified by EDAX analysis on the fracture surface. ner (Pd,Cu,Au)Sn4 IMCs and thicker (Cu,Ni)6Sn5 IMCs
Therefore, failure occurs within the solder and Ni(P) layer because the low Pd layer is consumed shortly and formed
on the substrate side (Fig. 9a). In addition, some cracks are thinner (Pd,Cu,Au)Sn4 IMCs, which allowed the diffusion of
observed in the fracture surface, which have formed during more Sn and Cu atoms to react with the underlying Ni(P) for
the die peel test. forming a more stable (Cu,Ni)6Sn5 IMCs at the early stage

Fig. 9  SEM/EDAX analysis
of fracture surface after the
die peel test. a Low Pd sample
failure interface; and b high Pd
sample failure interface after the
die peel test

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Fig. 10  SEM images showing

IMCs formation after 200 h
of thermal stress. a Sample
B, medium Au (0.07 μm) and
low Pd (0.05 μm); b sample
D, medium Au (0.07 μm) and
medium Pd (0.2 μm); c sample
F, medium Au (0.07 μm) and
high Pd (0.4 μm); d sample
C, high Au (0.2 μm) and low
Pd (0.05 μm); e sample E,
high Au (0.2 μm) and medium
Pd (0.2 μm); and f sample G,
high Au (0.2 μm) and high Pd
(0.4 μm)

Table 2  IMCs phases based on experimental results after solid-state bonding at 207 °C and aging at 150 oC
Interfacial IMCs phases Atomic percentage (EDAX)
After reflow During aging Au Cu Sn Pd Ni

Die side Cu3Sn 74–76 23–26

Cu6Sn5 Cu6Sn5 1–3 52–56 43–46
Cu6(1−x)Au5xSn5 IMCs in Cu6(1−x)Au5xSn5 IMCs in 10–18 37–46 44–49 2–3
medium–high Au medium–high Au
Solder
 Substrate side (Pd,Cu,Au)Sn4 3–7 4–7 74–82 7–13
(Pd,Au)Sn4 5–8 76–81 10–18 2–4 at.% found in low
Au/Pd thickness, A
and B
(Cu,Ni)6Sn5 1–3 35–50 42–46 1–3 15–20

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12624 J Mater Sci: Mater Electron (2017) 28:12617–12629

of 200 h isothermal aging (Fig. 10a). On the other hand, the and ii) when the supply of Sn atoms is limited from the sol-
high Pd sample (0.4  μm) exhibits thicker (Pd,Cu,Au)Sn4 der through C ­ u6Sn5 IMCs, then the limited amount of Sn
IMCs and thinner (Cu,Ni)6Sn5 IMCs with a small amount atoms reacts with Cu atoms that are available from the Cu
of Pd during isothermal aging. Since aging takes a longer pillar and form ­Cu3Sn IMCs on the Cu pillar.
time to consume the entire Pd layer to form thicker layer type Therefore, three layers of IMCs, including ­ Cu3Sn,
interfacial (Pd,Cu,Au)Sn4 IMCs at the interface, Cu and Sn ­Cu6Sn5 and Cu–Au–Sn IMCs, are observed on the Cu pil-
atoms cannot diffuse to react with underlying Ni(P) layer dur- lar side. In addition, Kirkendall voids are observed after
ing this solid-state chemical reaction. Interfacial (Cu,Ni)6Sn5 200  h of thermal aging on all samples. These voids not
IMCs thicknesses decrease gradually with the increasing of only occurred in the Cu/Cu3Sn interface, but also within
Pd thickness (Fig. 10a–c). the ­Cu3Sn IMCs close to the chip side. Possible reason
In the case of high Au (0.2 μm) and low Pd (0.05 μm) for the formation of Kirkendall voids that the diffusion of
samples, during 200  h of isothermal aging, resettlements Cu is faster than Sn diffusion in solid-state aging, result-
of Au are also observed and form more stable IMCs con- ing in a net vacancy flux of Cu at the interface or inside
taining higher Au on top of both sides of interfacial IMCs ­Cu3Sn IMCs [29]. Chiu et al. [30] reported that Kirkend-
(Fig. 10d). Due to the first dissolution rate of Au in solder, all voids formed when electroplated Cu was reacted with
and the greater thermodynamic stability of the (Pd,Cu,Au) Sn–Ag–Cu solder. Kirkendall voids are attributed to the
Sn4 IMCs, the reconfiguration of ­AuSn4 to (Pd,Cu,Au)Sn4 formation of C ­ u3Sn IMCs, while the growth of C ­ u6Sn5
IMCs occurs at the interface where Cu and Pd are avail- IMCs is not [31, 32]. These voids degraded the mechani-
able [23–25]. This phase is based on (Pd,Au)Sn4 IMCs. cal strength, which affects the reliability of solder joints.
The bright resettlement (Pd,Cu,Au)Sn4 IMCs phase com- It is important to note that no Kirkendall void is found on
position is 75–81 at.% Sn, 3–5 at.% Pd, 5–7 at.% Cu, and the substrate side, which is due to the Ni diffusion bar-
12–16 at.% Au (Fig. 10d). rier. Normally, the Ni diffusion rate is much slower than
It is found the percentage of Au in solder is ~4 wt% on the Cu, which inhibits the reaction of Sn and Cu, because
all thick Au (0.2  μm) samples, which is higher than the it is an interstitial solute with a very low solubility of
normal conventional solder joint. Many researchers have 10 ppm [33].
reported that the quantity of Au that is dissolved in solder Figures 11 and 12 show the IMCs thickness and micro-
must remain below a critical value of 3–4 wt%, in order to structure of solder joints after 500 h of aging. On the sub-
prevent embrittlement of the solder joint [24, 25]. There- strate side, the (Cu,Ni)6Sn5 IMCs and (Pd,Cu,Au)Sn4 IMCs
fore, due to embrittlement of solder and brittle IMCs, some thicknesses have increased with the increase of aging time
voids are created between the interfacial IMCs during in all samples. During 500  h isothermal aging, Ni atoms
grinding and polishing. The degree of Au embrittlement in from the Ni(P) layer react with Sn and Cu, and form inter-
all thick Au samples is very substantial (Fig. 10d–f). facial (Cu,Ni)6Sn5 IMCs. On the other hand, P accumulates
In the case of high Au (0.2  μm) and high Pd (0.4  μm) and forms a very thin P-rich Ni layer on top of the Ni(P)
samples G, most of the pure Sn from the solder bump layer. For the low Pd (0.05 μm) sample, ~75% solder still
has been consumed with a IMCs thickness of 5.27  μm remains intact and exhibits a good connection with both
(Fig.  10f). This is because of the high consumption rate sides of interfacial IMCs (Fig.  11a). The thin (Pd,Cu,Au)
of Sn to form Pd containing (Pd,Cu,Au)Sn4 IMCs, and the Sn4 IMCs layer has started to break due to no unreacted Pd
formation of other IMCs at solder and interfaces, which layer for solid-state reaction. Thus, more Cu and Sn diffuse
gradually consumes more Sn from the solder and promotes through this thin IMCs to form more thermodynamically
embrittlement of solder joint. Consequently, voids and stable (Cu,Ni)6Sn5 IMCs at the interface.
cracks (Fig. 10f) are found on both sides of the interfacial In contrast, on the high Pd (0.4  μm) sample, approxi-
IMCs interface. Therefore, it is suggested that the IMCs in mately 95% of solder has been consumed, and forms
high Au (0.2 μm) and high Pd samples (0.4 μm) are quite 5.71  μm IMCs during 500  h of thermal aging (Fig.  11c).
brittle and consumed more Sn from solder. This indicates that the Pd thickness causes a significant
On the Cu pillar side, during aging, the C ­ u6Sn5 IMCs effect on solder consumption due to the faster formation
layer grows by inter-diffusion of Cu and Sn, and reacts with of (Pd,Cu,Au)Sn4 IMCs. The remaining solder acts as a
each other. An additional layer of ­Cu3Sn IMCs has formed binding material between both sides of brittle IMCs. The
underneath the scallop-type ­Cu6Sn5 IMCs. There are two (Cu,Ni)6Sn5 IMCS thickness decreases with increases of
possible ways to form ­Cu3Sn IMCs on Cu pillars:i) during Pd thickness. No new IMCs formation is found after 500 h,
aging, ­Cu6Sn5 IMCs react with Cu atoms that are continu- as compared to 200  h, of isothermal aging. Similarly, on
ously supplied from the Cu pillar, as shown in Eq. (1) [27, the chip side, no new IMCs formation is found, and all
28]: IMCs thicknesses increased as compared to 200 h isother-
mal aging.
9Cu + Cu6 Sn5 = 5Cu3 Sn (1)

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Fig. 12  Comparison of overall IMCs thicknesses during bonding and

isothermal aging

vital role in interfacial IMCs growth and reliability of Cu

pillar solder joints.

3.4 Growth behavior of IMCs layer

The IMCs are an indication of chemical bonding at the sub-

strate/solder interface. An initial IMCs (­ Ti) layer forms dur-
ing the solid-state bonding process, and continues to grow
during solid-state aging. If the intermetallic growth process
is controlled by volume diffusion, the isothermal growth of
the intermetallic layer should follow the square root time
law. Generally the growth of the IMCs layer follows a para-
bolic growth equation, as expressed by Eq. (2) [26, 34]:
Fig. 11  SEM image shows the IMCs formation after 500  h of iso-
thermal stress, at medium Au with different Pd thickness samples. a Tf = (kt)n + Ti (2)
Sample A, low Pd (0.05 μm); b sample D, medium Pd (0.2 μm); and
c sample F, high Pd (0.4 μm) where ­Tf is the total thickness of the intermetallic layer;
­Ti is the initial IMCs thickness just after bonding; k is the
growth rate constant; n is the time exponent (=0.5); and
Higher IMCs thickness is found at the substrate side t is the aging time. Generally, the IMCs layer thickness
in the high Pd thickness sample after bonding (Fig.  12). increased linearly with the square root of aging time and
IMCs thickness increases linearly with increasing of grows faster at higher aging temperature. Equation (1) can
aging time. The overall IMCs thickness of the low Pd be re-written as Eq. (3):
thickness sample is two times lower than high Pd thick-
ness. It can be seen that almost all solder has been con- Tf − Ti = k1∕2 .t1∕2
sumed during 200 h aging of high Pd and high Au thick-
ness sample G (Fig.  10f), due to tiny solder and high Ta = k1∕2 .t1∕2 (3)
growth rate of IMCs. where ­Ta is the IMCs thickness which increases with aging
As compared to the die side IMCs growth, the high Pd time t; and k depends on the atomic diffusion coefficient,
thickness sample shows higher overall IMCs thickness than and can be obtained from the linear regression line. The
the die side Cu–Sn IMCs (Fig.  12). This is due to higher average measured intermetallic thickness ­(Tf –Ti) was plot-
growth of (Pd,Au)Sn4 IMCs during solid-state bonding and ted against the aging time t­0.5, as shown in Figs. 13 and 14.
at the beginning of aging. Therefore, Pd thickness plays a

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12626 J Mater Sci: Mater Electron (2017) 28:12617–12629

formation of interfacial IMCs at the substrate side. On the

die side, a continuous supply of Sn and Cu atoms to form
Cu–Sn IMCs and one additional process for bump forma-
tion was performed to form solder micro-bumps, which
increases the overall Cu–Sn IMCs thickness. A much
slower growth rate is observed in sample B because of the
lower Pd thickness and lower growth rate of (Cu,Ni)6Sn5
IMCs, as compared to Cu–Sn IMCs.
Figure 15 shows the backscattered electron SEM images
of Cu pillar solder joints after 800  h of aging. All IMCs
thickness increases with the increase of aging time. Only
low—medium Au (0.04–0.07  μm) and low—medium
Pd (0.05–0.02  μm) thickness samples (A, B, and D) with

Fig. 13  Relationship between Ta and aging time ­(t1/2) for ­Cu3Sn and

­Cu6Sn5 IMCs on the Cu pillar side

Fig. 14  Relationship between IMCs thickness Ta and aging time

­(t1/2) for (Pd,Cu,Au)Sn4 IMCs and (Cu,Ni)6Sn5 IMCs on the substrate
side

From Figs.  13 and 14, it can be seen that the growth

of IMCs follows parabolic growth kinetics. Thus,
the growth of the intermetallic layer is shown to be
diffusion-controlled.
It is also seen that the IMCs thickness increases linearly
on both sides with aging time. The slope of the line in
Figs. 13 and 14 shows the rate of IMCs growth. The slope
of the curve in Fig. 13 indicates that the growth rate (k) of
­Cu6Sn5 and ­Cu3Sn IMCs is 6.01 × 10−14cm2/s. On the other
hand, the slopes of the curves in Fig.  14 indicate that the
k values of the total (Pd,Cu,Au)Sn4 and (Cu,Ni)6Sn5 IMCs
growth during aging of 0.05, 0.2 and 0.4 μm Pd thickness
samples are 8.54 × 10−15, 1.49 × 10−14 and 5.51 × 10−14cm2/
s, respectively. The growth rates of Cu–Sn IMCs thickness
are slightly higher than (Pd,Cu,Au)Sn4 and (Cu,Ni)6Sn5 Fig. 15  SEM image shows the IMCs formation after 800  h of ther-
mal stress. a Sample A, low Au (0.04 μm) and low Pd (0.05 μm); b
IMCs of the high Pd (0.4  μm) thickness sample because sample B, medium Au (0.07 μm) and low Pd (0.05 μm); and c sample
of the limited supply of Pd, Au, and Cu atoms for the D, medium Au (0.07 μm) and medium Pd (0.2 μm)

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solder joint are able to withstand 800 h of high temperature on top of the scallop-type C ­ n6Sn5 IMCs. It can be seen
isothermal aging. In addition, more than 40% solder and that Cu–Sn–Au IMCs with a higher percentage of Au
0.85 μm Ni(P) layer still remain intact to maintain a good (~18  at.%) create a very weak interface with solder.
interconnection between copper pillar micro-bump and Moreover, at the edge of the die bump, Cu with a very
substrate after 800 h of isothermal aging. In the Pd 0.05 and small amount of Sn is observed, which indicates that fail-
0.2  μm thickness samples, the (Pd,Cu,Au)Sn4 IMCs layer ure also occurs within the ­Cu3Sn IMCs. During aging,
started to break and form island-like structure during a long Kirkendall voids formed within this ­Cn3Sn IMCs region,
time of aging due to the formation of thinner (Pd,Cu,Au) which also creates a weaker interface. Therefore, frac-
Sn4 IMCs and more diffusion of Sn and Cu atoms through tures propagate more easily at the ­Cu3Sn IMCs and Cu-
this IMCs layer (Fig. 15a, b), which enhanced the interfa- Sn-Au IMCs interface during the die peel test.
cial reaction and increase the (Cu,Ni)6Sn5 IMCs thickness. As compared to time zero, the fracture surface has
On the chip side, no new IMCs are found, and all IMCs been changed from the substrate side to the die side after
thicknesses increase with isothermal aging time. aging of the high Pd thickness sample. The reasons for
the changing of the fracture side is due to the formation
3.5 Failure mode after die peel test of high Au containing Cu–Au–Sn IMCs and Kirkendall
voids, which create a very weak interface with tiny sol-
Figure 16 shows the backscattered electron SEM images on der. For the low Pd samples, fracture occurs through the
the die side fracture surface after the peel test. In the case substrate side IMCs similar to time zero (Fig. 9a), and no
of low Pd (0.05 μm) and low Au (0.05 μm) samples, failure significant change is observed during isothermal aging
occurs within the solder and IMCs interface at the substrate because of the lower IMCs thickness and presence of
side (Fig.  16a). Mainly, (Pd,Cu,Au)Sn4 IMCs and solder more solder for interconnection. It is well known that,
are identified at the fracture surface. In addition, some since IMCs are brittle and have densities that are different
cracks are found on fracture surface, which formed during from solder alloys, IMCs that are too thick degrade the
the die peel test. strength and reliability of the solder joints [26]. Based on
For high Pd (0.4  μm) and medium Au (0.07  μm) the above fracture surface analysis after isothermal aging,
samples, failure occurs at the die side IMCs (Fig.  16b). it can be concluded that the mechanical strength of the
Cu–Sn–Au IMCs are identified on the fracture surface. low Pd and low Au samples will be higher than that of the
The SEM image on the fracture surface appears as a high Pd and medium–high Au thickness samples, which
scallop-type due to the formation of Cu–Sn–Au IMCs is not suitable for long-term reliable interconnections.

Fig. 16  SEM/EDAX analysis
after 800 h of isothermal aging.
a Sample A, low Pd layer thick-
ness sample failure interface;
and b sample F, high Pd layer
thickness sample failure inter-
face after the die peel test

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12628 J Mater Sci: Mater Electron (2017) 28:12617–12629

4 IMCs growth mechanism

For the low Pd sample, during bonding, Au atoms from

the substrate side partially diffuse into the solder and form
­AuSn4 and Au–Sn–Cu IMCs within the solder. Sn reacts
with the remaining Au and Pd to form (Pd,Au)Sn4 IMCs
at the interface (Fig. 17a). For low Pd thickness, all Pd lay-
ers are consumed within a short time. However, for high Pd
thickness, thick (Pd,Au)Sn4 IMCs form and a few microns
of the Pd layer remain intact on the Ni(P) layer due to a
solid-state bonding for shorter time (Fig. 17b).
Sn atoms from solder also react with die side Cu and
form ­Cu6Sn5 IMCs. Thus, Sn from solder is consumed by Fig. 18  Schematic diagram of interfacial IMCs growth during iso-
both sides of interfacial IMCs. Since more Sn is consumed thermal aging
by the (Pd,Au)Sn4 IMCs, the consumption rate of Sn is
very high in the solder micro-bump /ENEPIG system with
high Pd. Cu–Au–Sn IMCs on top of C ­ u6Sn5 IMCs. Due to uneven
During isothermal aging, Sn atoms from solder and Cu diffusion of Sn and Cu atoms, new additional C ­ u3Sn IMCs
atoms from Cu pillar diffuse and react with (Pd,Au)Sn4 form on Cu pillar. Since Cu and Sn atoms continuously
IMCs to form (Pd,Cu,Au)Sn4 IMCs and new additional diffuse through the ­Cu6Sn5 IMCs, overall IMCs thickness
(CuNi)6Sn5 IMCs on top of the Ni(P) layer on the sub- increases with aging time at the die side.
strate side in all samples (Fig. 18). On the die side, Au and Therefore, different types of IMCs thickness increase
Sn atoms diffuse from the solder during isothermal aging from both sides with decreases in solder volume during
and form new additional ­Cu3Sn IMCs on Cu pillar and isothermal aging. These types of solid-state chemical reac-
tions will occur during isothermal aging, and all solder will
finally be consumed. This results in the creation of a weak
interface between both sides of IMCs for high Pd thickness
samples. For low Pd thickness samples, solder still remains
between both sides of interfacial IMCs, and good solder
interconnection is maintained. Thus, for the ENEPIG/sol-
der micro-bump system, Pd thickness should not be greater
than 0.2 μm to make a robust solder joint.

5 Conclusions

Based on the extensive microstructural characterization and

failure analysis prior and subsequent to isothermal aging
test, the following are the findings:

• High Au (1.0–0.2 μm) thickness creates different types

of interfacial IMCs containing Au, and enhances the
embrittlement of tiny solder joints. Thus, Au thickness
should be lower than 0.1 µm.
• The effect of Pd thickness on interfacial IMCs forma-
tion depends on bonding temperature and time. At
lower temperature (207 °C) and shorter time of solid-
state bonding (~3  s), the (Pd,Au)Sn4 phase is the pre-
dominant IMCs which forms at the interface. (Pd,Au)
Sn4 IMCs prevent the formation of (Pd,Ni)Sn4 and
Fig. 17  Schematic diagrams of interfacial IMCs formation during
solid-state bonding. a Low Pd (0.05  μm), and b high Pd (0.4  μm) (Cu,Ni)6Sn5 interfacial IMCs, and interrupt the interdif-
sample fusion of Sn, Cu, and Ni.

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J Mater Sci: Mater Electron (2017) 28:12617–12629 12629

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