1 2 8 K × 8 BIT HIGH SPEED CMOS STATIC

RAM
A REPORT ON THE DESIGN AND PERFORMANCE OF A HIGH SPEED STATIC CMOS RAM

Submitted by:
Shashank Varshney (2017JVL2507)
Vijay Sharma (2017JVL2508)
Saurabh Mathur (2017JVL2502)
Srishti Gupta (2017JVL2503)
Ramyani Mukherjee (2017EEN2247)

Completed under the guidance of

DR. KAUSHIK SAHA

Department of Electrical Engineering

INDIAN INSTITUTE OF TECHNOLOGY DELHI

NEW DELHI, INDIA- 110016
 128K × 8 bit CMOS Static RAM designed for High Speed

ABSTRACT
During the course of this project, a 128K × 8 bit CMOS Static RAM (SRAM) was designed with focus on
achieving maximum speed. The target specifications are those of CY7C1019CV33 IC manufactured by Cypress
Semiconductors. The maximum read and write access times are 7ns and 8 ns respectively.
Using UMC65nm technology, a 6T SRAM cell was designed for high speed, obtained area was 1.387um2. The
various components of an SRAM were studied in detail along with their different configurations. The best
configurations for the respective components were designed with the aim of achieving minimum delay. A Charge
Transfer Sense Amplifier (CTSA) was designed because it is inherently faster than other types of sense
amplifiers.

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 128K × 8 bit CMOS Static RAM designed for High Speed

ACRONYMS

SRAM Static Random Access Memory

SNM Static Noise Margin
CR Cell Ratio
PR Pull up Ratio
RSNM Read Static Noise Margin
HSNM Hold Static Noise Margin
WSNM Write Static Noise Margin
TT Typical NMOS and Typical PMOS corner
SS Slow NMOS and Slow PMOS Corner
FF Fast NMOS and Fast PMOS Corner
SNFP Slow NMOS and Fast PMOS Corner
FNSP Fast NMOS and Slow NMOS Corner
HS High Speed Transistor
LL Low Leakage Transistor
ATD Address Transition Detector
CTSA Charge Transfer Sense Amplifier
PD Power Dissipation
PDP Power Delay Product
SA Sense Amplifier
LVS Layout versus Schematic
DRC Design Rule Check
PEX Parasitic Extraction
PVT Process Voltage Temperature

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 128K × 8 bit CMOS Static RAM designed for High Speed

CONTENTS

Abstract .................................................................................................................................... 2
Acronyms ................................................................................................................................. 3
List of Figures .......................................................................................................................... 7
List of Tables ........................................................................................................................... 9
1. Introduction........................................................................................................................ 10
1.1. Design Specifications ............................................................................................................. 10
2. Background Information ................................................................................................... 11
2.1. Process Technology ............................................................................................................... 11
2.1.1. Device Model ..................................................................................................................................... 11
2.1.2. SPICE control Parameters ................................................................................................................ 11
2.2. Design Flow Chart ................................................................................................................... 12
2.3. Timeline and Work Division .................................................................................................... 13
2.4. Literature survey ..................................................................................................................... 13
2.5. Simulation Tools Used ............................................................................................................ 13
3. Architecture ....................................................................................................................... 14
3.1. Array Partitioning .................................................................................................................... 14
3.2. RC Extraction .......................................................................................................................... 14
3.3. Metal Planning ......................................................................................................................... 15
3.4. Memory Division...................................................................................................................... 15
3.5. Address Lines Division ........................................................................................................... 16
3.6. Floorplan .................................................................................................................................. 17
3.6.1. Address Routing ................................................................................................................................ 18
3.6.2. Data Routing ...................................................................................................................................... 19

4. Detailed Design .................................................................................................................. 20

4.1. Cell and Core Design .............................................................................................................. 20
4.1.1. Cell Type ............................................................................................................................................ 20
4.1.2. Cell Schematic ................................................................................................................................... 20
4.1.3. Cell Schematic Simulations ............................................................................................................... 21
4.1.3.1. Static Noise Margin..................................................................................................................... 21
4.1.3.2. Write Noise Margin ..................................................................................................................... 22
4.1.3.3. Read Noise Margin ..................................................................................................................... 23
4.1.3.4. Transient Simulations ................................................................................................................. 25
4.1.4. Core Layout ...................................................................................................................................... 26
4.1.4.1. Cell Layout (unoptimized) ........................................................................................................... 26
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4.1.4.2. Optimizations Incorporated ......................................................................................................... 27

4.1.4.3. Optimized Cell Layout ................................................................................................................ 28
4.1.4.4 Core Assembly ............................................................................................................................ 28
4.2. Buffers and Drivers .................................................................................................................................... 30
4.2.1. Pass Transistor Logic ........................................................................................................................ 30
4.2.1.1. Circuit Schematic ........................................................................................................................ 31
4.2.1.2. Sizing of Gates ........................................................................................................................... 31
4.2.1.3. Layout ......................................................................................................................................... 31
4.2.2. Word line Driver ................................................................................................................................. 32
4.2.2.1. Schematic ................................................................................................................................... 33
4.3. ATD Scheme................................................................................................................................................ 34
4.3.1. ATD Inputs ......................................................................................................................................... 34
4.3.2. ATD Outputs ...................................................................................................................................... 34
4.3.3. Conventional ATD Circuit: ................................................................................................................. 34
4.3.4. Pulse stretching Circuit: ..................................................................................................................... 35
4.3.5. Pulse Width Analysis ......................................................................................................................... 36
4.3.6. ATD Layout ........................................................................................................................................ 37
4.3.7. Monostable Multivibrator Layout ........................................................................................................ 38
4.3.8.. ATD Simulations ............................................................................................................................... 39
4.3.9.. Monostable Multivibrator Simulations ............................................................................................... 39
4.4. Decoding scheme ....................................................................................................................................... 40
4.4.1. Block Decoding .................................................................................................................................. 40
4.4.1.1. Scheme used .............................................................................................................................. 40
4.4.1.2. Block Decoder circuitry with schematic ...................................................................................... 41
4.4.1.3. Block Decoder inputs and outputs .............................................................................................. 41
4.4.1.4. Block Decoder circuit schematic simulation ............................................................................... 42
4.4.1.5. Block Decoder circuit layout ....................................................................................................... 42
4.4.1.6. Block Decoder Post Extraction Simulation ................................................................................ 43
4.4.1.7. Block Decoder Timing ................................................................................................................ 43
4.4.2. Row Decoding ................................................................................................................................... 44
4.4.2.1. Scheme used .............................................................................................................................. 44
4.4.2.2. Row decoder circuitry with schematic ........................................................................................ 44
4.4.2.3. Row Decoder inputs and outputs .............................................................................................. 44
4.4.2.4. Row Decoder circuit schematic simulation ................................................................................ 45
4.4.2.5. Row Decoder circuit layout ......................................................................................................... 45
4.4.2.6. Row Decoder Post Extraction Simulation .................................................................................. 46
4.4.2.7. Row Decoder Timing .................................................................................................................. 47
4.4.3. Column Decoding .............................................................................................................................. 47
4.4.3.1. Scheme used .............................................................................................................................. 47
4.4.3.2. Column decoder circuitry with schematic ................................................................................... 47
4.4.3.3. Column Decoder inputs and outputs ......................................................................................... 48
4.4.3.4. Column Decoder circuit schematic simulation ........................................................................... 48
4.4.3.5. Column Decoder circuit layout .................................................................................................... 49
4.4.3.6. Column Decoder Post Extraction Simulation ............................................................................ 50
4.4.3.7. Column Decoder Timing ............................................................................................................. 50

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4.5. Core I/O ........................................................................................................................................................ 51

4.5.1. Precharge Circuitry ............................................................................................................................ 51
4.5.1.1. Scheme Used ............................................................................................................................. 51
4.5.1.2. Inputs and Outputs Used ............................................................................................................ 51
4.5.1.3. Precharge Circuitry Routing ....................................................................................................... 51
4.5.1.4. Estimated Load Capacitance on Outputs ................................................................................... 51
4.5.1.5. Precharge Circuit Simulation ...................................................................................................... 52
4.5.1.6. Precharge Circuit Layout ............................................................................................................ 52
4.5.2. Sense Amplifier.................................................................................................................................. 53
4.5.2.1. Different Topologies ................................................................................................................... 53
Voltage mode Sense Amplifier ................................................................................................... 53
Current mode Sense Amplifier ................................................................................................... 54
Charge Transfer Sense Amplifier ............................................................................................... 55
4.5.2.2. Inputs used ................................................................................................................................. 55
4.5.2.3. CTSA Outputs............................................................................................................................. 55
4.5.2.4. CTSA Schematic ........................................................................................................................ 56
4.5.2.5. CTSA Schematic Simulation ...................................................................................................... 56
4.5.2.6. Reference Voltage Generator Schematic ................................................................................... 57
4.5.2.7. CTSA Layout .............................................................................................................................. 58

5. Integration ....................................................................................................................... 60
5.1. Critical Path Simulation .......................................................................................................................... 60
5.1.1 Critical Path Block Diagram ........................................................................................................... 60
5.1.2 Critical Path Timing ....................................................................................................................... 60
5.1.3 Full Chip Layout Integration .......................................................................................................... 61
5.2. Summary of Area Distribution ................................................................................................................. 65
5.3. Complete Summary ................................................................................................................................ 65

References .......................................................................................................................... 66

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LIST OF FIGURES
FIGURE 1: DESIGN FLOWCHART ................................................................................................................................. 12
FIGURE 2: GANTT CHART ........................................................................................................................................... 13
FIGURE 3: PIN DESCRIPTION OF CHIP ......................................................................................................................... 16
FIGURE 4: FLOORPLAN OF THE CHIP........................................................................................................................... 17
FIGURE 5: ADDRESS ROUTING ................................................................................................................................... 18
FIGURE 6: DATA ROUTING ......................................................................................................................................... 19
FIGURE 7: CELL SCHEMATIC ...................................................................................................................................... 21
FIGURE 8: SCHEMATIC FOR STATIC NOISE MARGIN .................................................................................................... 21
FIGURE 9: BUTTERFLY CURVE FOR HSNM ................................................................................................................. 22
FIGURE 10: BUTTERFLY CURVE FOR WNM ................................................................................................................ 22
FIGURE 11: BUTTERFLY CURVE FOR RNM ................................................................................................................. 23
FIGURE 12: W RITE DELAY ANALYSIS .......................................................................................................................... 25
FIGURE 13: READ DELAY ANALYSIS ........................................................................................................................... 25
FIGURE 14: LAYOUT OF SRAM CELL ......................................................................................................................... 26
FIGURE 15: BITLINE TWISTING ................................................................................................................................... 27
FIGURE 16: OPTIMIZED CELL LAYOUT ........................................................................................................................ 28
FIGURE 17: OPTIMIZED 4 BY 4 SRAM CELL ............................................................................................................... 29
FIGURE 18: OPTIMIZED 16 BY 16 SRAM CELL ........................................................................................................... 29
FIGURE 19: CORE LAYOUT ....................................................................................................................................... 30
FIGURE 20: SCHEMATIC OF PASS TRANSISTOR ............................................................................................................ 31
FIGURE 21: LAYOUT OF SINGLE PASS TRANSISTOR CELL ........................................................................................ 31
FIGURE 22: LAYOUT OF PASS TRANSISTOR ARRAY .................................................................................................. 32
FIGURE 23: SCHEMATIC OF W ORD LINE DRIVER ......................................................................................................... 33
FIGURE 24: LAYOUT OF W ORD LINE DRIVER .............................................................................................................. 33
FIGURE 25: CONVENTIONAL ATD SCHEMATIC ........................................................................................................... 35
FIGURE 26: MONOSTABLE MULTIVIBRATOR SCHEMATIC ........................................................................................ 35
FIGURE 27: ATD LAYOUT .......................................................................................................................................... 37
FIGURE 28: ATD ARRAY LAYOUT .............................................................................................................................. 37
FIGURE 29: MONOSTABLE MULTIVIBRATOR LAYOUT ............................................................................................... 38
FIGURE 30: ATD SIMULATIONS ................................................................................................................................. 39
FIGURE 31: MONOSHOT SIMULATION ...................................................................................................................... 39
FIGURE 32: BLOCK DECODER ................................................................................................................................... 40
FIGURE 33: GATE LEVEL IMPLEMENTATION................................................................................................................. 41
FIGURE 34: BLOCK DECODER SCHEMATIC SIMULATION ......................................................................................... 42
FIGURE 35: BLOCK DECODER LAYOUT ..................................................................................................................... 42
FIGURE 36: BLOCK DECODER POST EXTRACTION SIMULATION ............................................................................. 43
FIGURE 37: ROW DECODER GATE LEVEL IMPLEMENTATION ...................................................................................... 44
FIGURE 38: ROW DECODER SCHEMATIC SIMULATION ............................................................................................ 45
FIGURE 39: ROW DECODER LAYOUT ........................................................................................................................ 45
FIGURE 40: PART OF ROW DECODER LAYOUT SHOWING METALS ......................................................................... 46
FIGURE41: ROW DECODER POST EXTRACTION SIMULATION ................................................................................. 46
FIGURE 42: COLUMN DECODER GATE LEVEL IMPLEMENTATION ................................................................................ 47
FIGURE 43: COLUMN DECODER SCHEMATIC SIMULATION ...................................................................................... 48
FIGURE 44: COLUMN DECODER LAYOUT .................................................................................................................. 49
FIGURE 45: PART OF COLUMN DECODER LAYOUT SHOWING METALS ................................................................... 49
FIGURE 46: COLUMNDECODER POST EXTRACTION SIMULATION ........................................................................... 50

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 128K × 8 bit CMOS Static RAM designed for High Speed

FIGURE 47: PRECHARGE CIRCUIT SCHEMATIC ....................................................................................................... 52

FIGURE 48: PRECHARGE CIRCUIT LAYOUT.............................................................................................................. 52
FIGURE 50: CROSS COUPLED VOLTAGE MODE SENSE AMPLIFIER ......................................................................... 53
FIGURE 50: CURRENT MODE SENSE AMPLIFIER...................................................................................................... 54
FIGURE 51: CHARGE TRANSFER SENSE AMPLIFIER ................................................................................................ 56
FIGURE 52: CTSA SIMULATION WAVEFORMS .......................................................................................................... 56
FIGURE 53: SCHEMATIC OF REFERENCE VOLTAGE REGULATOR CIRCUIT ............................................................. 57
FIGURE 54: CTSA LAYOUT ....................................................................................................................................... 58
FIGURE 55: LAYOUT OF CTSA ARRAY ...................................................................................................................... 59
FIGURE 56: LAYOUT OF REFERENCE VOLTAGE CIRCUIT ....................................................................................... 59
FIGURE 57: BLOCK DIAGRAM OF CRITICAL PATH .............................................................................................................. 60
FIGURE 58: INTEGRATION OF CTSA ......................................................................................................................... 61
FIGURE 59: INTEGRATION OF REFERENCE VOLTAGE GENERATOR ........................................................................ 61
FIGURE 60: INTEGRATION OF WORD LINE DRIVER .................................................................................................. 62
FIGURE 61: INTEGRATION OF WORD LINE DRIVER SHOWING METALS ................................................................... 62
FIGURE 62: INTEGRATION OFCOLUMN DECODER ................................................................................................... 63
FIGURE 63: INTEGRATION OF PASS TRANSISTORS ................................................................................................. 63
FIGURE 64: TOP LEVEL CHIP LAYOUT ...................................................................................................................... 64

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 128K × 8 bit CMOS Static RAM designed for High Speed

LIST OF TABLES
TABLE 1: METAL PLANNING ................................................................................................................................................... 15
TABLE 2: WSNM AT DIFFERENT PULL-UP RATIOS ............................................................................................................. 23
TABLE 3: RNM AT DIFFERENT CELL RATIOS ...................................................................................................................... 24
TABLE 4: SNM VALUES FOR SS CORNER ........................................................................................................................... 24
TABLE 5: SUMMARY OF UNOPTIMIZED CELL LAYOUT ...................................................................................................... 26
TABLE 6: SUMMARY OF OPTIMIZED CELL LAYOUT ........................................................................................................... 28
TABLE 7: SUMMARY OF OPTIMIZED CORE LAYOUT .......................................................................................................... 30
TABLE 8: SUMMARY OF LAYOUT OF PASS TRANSISTOR ARRAY....................................................................................32
TABLE 9: SUMMARY OF WORD LINE DRIVER LAYOUT ...................................................................................................... 33
TABLE 10 ATD INPUTS ........................................................................................................................................................... 34
TABLE 11: ATD OUTPUTS ...................................................................................................................................................... 34
TABLE 12 ATD PULSE WIDTH ANALYSIS AT VARIOUS PROCESS CORNERS AT 27 C ................................................... 36
TABLE 13: ATD PULSE WIDTH ANALYSIS AT TT CORNER AT VARIOUS TEMPERATURES ............................................ 36
TABLE 14 SUMMARY OFATD CELL LAYOUT ...................................................................................................................... 38
TABLE 15 SUMMARY OF MONOSTABLE MULTIVIBRATOR LAYOUT ................................................................................. 38
TABLE 16 BLOCK DECODER INPUTS AND OUTPUTS ........................................................................................................ 41
TABLE 17 BLOCK DECODER TIMING ................................................................................................................................... 43
TABLE 18 ROW DECODER INPUTS AND OUTPUTS ............................................................................................................ 44
TABLE 19 ROW DECODER TIMING ....................................................................................................................................... 47
TABLE 20 COLUMN DECODER INPUTS AND OUTPUTS ..................................................................................................... 48
TABLE 21 COLUMN DECODER TIMING ................................................................................................................................ 50
TABLE 22 INPUT AND OUTPUT OF PRECHARGE CIRCUIT ................................................................................................ 51
TABLE 23 CTSA INPUTS ........................................................................................................................................................ 55
TABLE 24 CTSA OUTPUTS .................................................................................................................................................... 55
TABLE 25 DELAY ANALYSIS OF SENSE AMPLIFIER ........................................................................................................... 57
TABLE 26 VOLTAGE VARIATIONS OF REFERENCE VOLTAGE GENERATOR WITH TEMPERATURE ............................ 58
TABLE 27 CRITICAL PATH TIMING ANALYSIS ...................................................................................................................... 60
TABLE 28 SUMMARY OF AREA DISTRIBUTION .................................................................................................................... 65

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 128K × 8 bit CMOS Static RAM designed for High Speed

1. INTRODUCTION

In today’s world, applications drive the need for improving upon the existing technology. With heavier
applications wanting to run on the smallest of devices, utilizing minimum area and power and at the
same time running as fast as possible calls for innovation in the area of device engineering, system
architecture, circuits and the intuition of the designer. A major component driving the semiconductor
industry is the fast SRAM- which provides for high speed memory access required by fast processors
and applications. <Traditionally, an SRAM macro is mainly formed by an array of cells consisting of
four or six transistors and a number of periphery circuits such as row decoder, column decoder, sense
amplifier, write buffer, etc. Information access from/to this macro consumes power in both dynamic and
static ways.> A major challenge today is to reduce the access time of the SRAM in the worst case. This
becomes particularly interesting because of the continuously shrinking technology node (since it brings
with it a lot of parasitic and higher order phenomena of the device and wire models). This report deals
with the design of a high-speed SRAM.

1.1. DESIGN SPECIFICATIONS

Memory Type SRAM

Memory Size 128x8k
Data Width 8 bits
Address Width 17 bits
Operating Voltage 1.2 V
Cycle Time 15 ns
Read Access Time 2 ns
Write Access Time 2 ns
Process Technology Node UMC 65 nm
No. of Metals 8
No. of Polys 1
Cell Size 1.387 μm2
Core Efficiency 83.06% without I/O Pad
Logic Used Static
Sense Amplifier Type Charge Transfer
Decoding Style Hierarchical
ATD used 1

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 128K × 8 bit CMOS Static RAM designed for High Speed

2. BACKGROUND INFORMATI ON

2.1. PROCESS TECHNOLOGY

Technology Information: The SRAM is designed in UMC 65nm technology node. The minimum
length of the transistors in this node is 60nm and minimum width is 80nm. The technology used is the
LLL (Low Leakage Logic). For this particular logic family there are three transistors available: HVT
(High Threshold Voltage); LVT (Low Threshold Voltage) and SVT (Standard Threshold Voltage). The
transistors used were N_12_LLLVT (NMOS) and P_12_LLLVT (PMOS) to achieve low leakage
current.

2.1.1. DEVICE MODEL

Threshold voltage of NMOS: 0.316 V

Threshold voltage of PMOS: -0.274 V

Gate capacitance of Minimum sized NMOS: 0.139 fF (approx.)

Gate capacitance of Minimum sized PMOS: 0.176 fF (approx.)

2.1.2. SPICE CONTROL PARAMETERS

Relative Tolerance (reltol): 1e-3

VAbsolute Tolerance (V abstol): 1e-6 V

IAbsolute Tolerance (Iabstol): 1e-6 V

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2.2. DESIGN FLOW CHART

FIGURE 1: DESIGN FLOWCHART

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 128K × 8 bit CMOS Static RAM designed for High Speed

2.3. TIMELINE AND WORK DIVISION

FIGURE 2: GANTT CHART

2.4. LITERATURE SURVEY

We did an intensive literature survey for basic understanding of SRAM. 6T SRAM cell was chosen over other
variants of SRAM cell design keeping in mind the advantages of 6T design discussed in Section 4.1.1. Noise
margin analysis and basic understanding of read write ability of the cell was understood after going through [1],
[2] and values of CR and PR were decided. We went through [3]-[4] for basic understanding of SRAM design and
practical challenges in the design. Standard latch based sense amplifier was used in the design. ATD was used
with a latch [8] to suppress variations with respect to different address transitions.

2.5. SIMULATION TOOLS USED

Schematic Cadence Design Toolkit-Schematic Editor

Layout Cadence Design Toolkit-Virtuoso

Design Rule Check Mentor Graphics Calibre DRC

Layout vs Schematic Mentor Graphics Calibre LVS

Parasitic Extraction Mentor Graphics Calibre PEX

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 128K × 8 bit CMOS Static RAM designed for High Speed

3. ARCHITECTURE

3.1. ARRAY PARTITIONING

It must be made clear in the beginning that the bitlines run horizontally and wordlines run vertically in our
design. This is done to keep the design square shaped for better core utilization. The entire memory is
divided into 8 banks each of 128 Kb. In order to reduce the bit line capacitance, it was decided to have 512
rows and 256 columns per bank. The motive behind such a fine division is to reduce the power dissipation by
keeping all the other memory blocks in retention mode and enable sharing of the peripherals.

3.2. RC EXTRACTION

Bitline Resistance(sheet) (mΩ) = 150

Poly - Metal Via Resistance(sheet) (Ω) = 30

Wordline Resistance (Ω) = 30.15 (including the Via Resistance)

Bitline Capacitance (aF/μm) = 86

Wordline Capacitance (aF/μm) =103.7

According to the specifications,

Worst case Access Time ≤ 10 ns

Dividing the delay across 5 major components of the

memory Worst case Read or Write Cycle time ≤ 2 ns

Using the Elmore Delay model for Bitline, we calculate the maximum no. of columns possible in a Memory Bank

2ns = 0.69*RC*(N + 1)*N/2

Where R, C are resistance and capacitance values corresponding to height of 1 cell, N is no. of columns.

Solving for N gives

N = 264 Columns

Procedure is repeated for maximum no. of rows possible

N = 1150 Rows

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Possible Configurations of the Memory Bank:

1024 Rows x 128 Columns

512 Rows x 256 Columns

256 Rows x 512 Columns

The 512 Rows x 256 Columns configuration is chosen for better Aspect Ratio, as our package is square.

We have 8 banks, arranged in 4 rows and 2 columns, thus, 4 x 512 = 2048 bitlines and 2 x 256 = 512
wordlines.

3.3. METAL PLANNING

Layers Application Sheet Resistance (mΩ) Capacitance (aF/µm)

Metal 1 Local Routing 170 130.8
Metal 2 Word line strapping 150 103.7
Metal 3 Bitline 150 86
Metal 4 Bitline complement 150 76.5
Metal 5 Address Routing 150 69.4
Metal 6 Control Routing 150 69.4
Metal 7 VSS 70 62.7
Metal 8 VDD 70 68.3

TABLE 1: METAL PLANNING

3.4. MEMORY DIVISION

No. of Banks = 8

Bank Size = 512 x 256 = 128 Kb

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3.5. ADDRESS LINES DIVISION

The total 17 address lines are divided as follows for decoding:
• A16 to A14 for memory bank decoding
• A13 to A9 for row decoding
• A8 to A0 for column decoding

Considering temporal and spatial locality, MSB address lines are allocated to block decoder, so
that memory blocks need not to be switched frequently.
Total Address bits = 5+9+3 = 17

FIGURE 3: PIN DESCRIPTION OF CHIP

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3.6. FLOORPLAN

FIGURE 4: FLOORPLAN OF THE CHIP

The figure above shows the initial floor plan of the SRAM. Memory is divided in 16 blocks.
These blocks are arranged such that row decoder, column decoder, sense amplifier, write buffer are shared
between two memories blocks.

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3.6.1. ADDRESS ROUTING

The address routing is shown below. The address pins are fed to the ATD and the column and row decoders.

FIGURE 5: ADDRESS ROUTING

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3.6.2. DATA ROUTING

The data routing is shown below for Read and Write cycles.
During Read, the data is fed into the sense amplifiers and then into the I/O pads.
During Write, the data is fed from the I/O pads to the write buffers and then into the memory cells.

FIGURE 6: DATA ROUTING

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4. DETAILED DESIGN

4.1. CELL AND CORE DESIGN

4.1.1. CELL TYPE

Static 6-T cell is chosen for SRAM cell design. This topology has the following advantages over 8T or 9T SRAM
cell.

• Lower power dissipation - 6T SRAM cell has less leakage current because less number of transistors are
 being used compared to 7T, 8T, and 9T SRAM cell architecture.
• Good stability - 6T SRAM cell has good stability as compared to 4T SRAM cell. As 4T SRAM cell has
 lower value of SNM (Static Noise Margin) in low voltage operation.
 • Relaxed area constraints.
• Symmetric structure - Helps during fabrication of device.

4.1.2. CELL SCHEMATIC

MATLAB simulations were carried out to find the bounds on pull -up ratio and cell ratio. We have tried to keep the
transistor sizes as small as possible while maintaining the cell ratio and pull up ratio. Considering acceptable noise
margins pull-up ratio was chosen to be 1.5 and cell ratio was 1. Accordingly sizes chosen were as given below. The
access transistors were chosen to be of minimum size so as to minimize the bitline capacitance. Sizing of transistors of
cell, CR /PR and transistor models are given below:

• Optimum CR = 2.0 & PR = 1.0

•Sizing of Transistors : L= 60 nm
o Pull-up Transistors : W = 160 nm
o Access Transistors : W = 80 nm
o Drive Transistors : W = 160 nm
• Transistor Model :
LLLVT (Low Leakage Low Threshold Voltage)

o N_12_LLLVT
o P_12_LLLVT

The following figure shows the schematic of the 6T cell used. M2 and M4 are pull-up transistors, M1 and M3 are
pull-down transistors while M5 and M6 are access transistors.

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FIGURE 7: CELL SCHEMATIC

4.1.3. CELL SCHEMATIC SIMULATIONS

4.1.3.1. STATIC NOISE MARGIN

FIGURE 8: SCHEMATIC FOR STATIC NOISE MARGIN

Static noise margin is the maximum noise voltage VN that can come simultaneously on both the voltage sources as
shown in the figure above and will not be able to flip the contents of the cell. The cell is in hold mode during this
time. Inverter characteristic is taken and is flipped and Maximum Square is determined as shown below:

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The following figure shows the butterfly curves for different values of cell ratio to calculate the HSNM

FIGURE 9: BUTTERFLY CURVE FOR HSNM

Hold Static Noise Margin = 353.6mV

4.1.3.2. WRITE NOISE MARGIN

Write noise margin is the maximum noise voltage V N that can come simultaneously on both the voltage
sources as shown in above section that will prevent write operation to flip the content of the cell. Cell is put
in write mode with word lines enabled and one of the bit lines pulled to ground. The worst case write margin
is shown below.

FIGURE 10: BUTTERFLY CURVE FOR WNM

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Thus, Write Noise Margin= 464mV

The following table shows the value of WSNM calculated for different values of PR. From these values, the
appropriate value of PR is found to be 1.0

PR WSNM (V)

2 0.744

1.5 0.66
1 0.464

0.5 0.445

TABLE 2: WSNM AT DIFFERENT PULL-UP RATIOS

4.1.3.3. READ NOISE MARGIN

Read noise margin is the maximum noise voltage VN that can come simultaneously on both the voltage sources
that will flip the content of a cell during a read operation. Cell is put in read mode with word line enabled and bit
lines tied to VDD. The worst case read margin is shown below.

FIGURE 11: BUTTERFLY CURVE FOR RNM

Thus, Write Noise Margin= 265mV

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The following table shows the value of RNM calculated for different values of CR. From these values, the
appropriate value of CR is found to be 2.0

CR RSNM (V)
3 0.36
2.5 0.314
2 0.265
1.5 0.224
1 0.158

TABLE 3: RNM AT DIFFERENT CELL RATIOS

The above values of SNM have been calculated at the tt corner. In order to check the performance in worst case,
simulations were carried out in the ss corner for CR=2.0 and PR=1.0, the results of which have been tabulated
below:

SNM Type Value (mV)

HSNM 353.6

RSNM 293

WSNM 432

TABLE 4: SNM VALUES FOR SS CORNER

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4.1.3.4. TRANSIENT SIMULATIONS

Write Delay of our cell is 82.53 psec. Simulation for write delay analysis is given below:

FIGURE 12: WRITE DELAY ANALYSIS

Read delay of our cell is 146.677 psec. Simulation results of our read delay analysis are shown:

FIGURE 13: READ DELAY ANALYSIS

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4.1.4. CORE LAYOUT

4.1.4.1. CELL LAYOUT (UNOPTIMIZED)

FIGURE 14: LAYOUT OF SRAM CELL

Single SRAM CELL Layout is shown in the Figure above. At the top, the VDD contacts are shared with transistor
above and the adjacent column transistors. The ground contacts are also shared between the adjacent column
transistors. The BIT and BIT_B lines are long lines running from one end of the core to the other; in horizontal
direction; in metal 3. Word line is drawn using metal 2; in vertical direction and runs along the core. The bit lines
and word lines are shared with adjacent cells in respective directions.

TABLE 5: SUMMARY OF UNOPTIMIZED CELL LAYOUT

Parameter Value

Length of the cell (um) 1.98 µm

Width of the cell (um) 1.87 µm

Area of the cell (um2) 3.70 um sq

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4.1.4.2. OPTIMIZATIONS INCORPORATED

Following techniques were used to optimize the layout of cell array and subsequently the core:

• The cell was flattened to further reduce the dimensions according to the DRC rules.

• The cells were further hierarchically abutted to form higher arrays and core

• The body contacts were shared as one contact for 16 cells for both Pmos and Nmos.

• Bit-Line twisting was incorporated as described below

Bitline Twisting:
We have done following steps in the bit line twisting idea:

• Bit line twisting scheme, where bit line is twisted after every 16 columns (or after every 16 th Word
 Line).
• Bit line twisting will make sure that effect of coupling noise will be symmetric on both BL and
 BL_BAR, and thus effect of coupling noise will be reduced.
• There are total 512 columns. Bit line is twisted 32 times in each core.
Next, we have shown bit line twisting scheme:

FIGURE 15: LAYOUT OF BITLINE TWISTING

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4.1.4.3. OPTIMIZED CELL LAYOUT

FIGURE 16: OPTIMIZED CELL LAYOUT

Summary of Optimized layout of cell is given below:

Parameter Value

Length of the cell (um) 1.55 µm

Width of the cell (um) 0.895 µm

Area of the cell (um2) 1.387 um sq

TABLE 6: SUMMARY OF OPTIMIZED CELL LAYOUT

4.1.4.4. CORE ASSEMBLY

The 6t cells have been abutted to with contact sharing to make a 4X4 layout and 16X16 layout
as shown in the figure below:

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FIGURE 17: 4X4 CELL LAYOUT

Area of 4X4 layout= 26.84um sq.

FIGURE 18: 16X16 CELL LAYOUT

Area of 16X16 layout= 406.17um sq.

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These 16X16 cells have been abutted to give a block of size 512 X 256 as shown in the figure below:

FIGURE 19: CORE LAYOUT

Summary of the block layout size has been tabulated below:

Parameter Value

Length of the cell (um) 794.54 µm

Width of the cell (um) 244.68 µm

Area of the cell (um2) 0.194 mm sq

TABLE 7: SUMMARY OF OPTIMIZED CORE LAYOUT

4.2. DRIVERS

4.2.1. PASS TRANSISTOR LOGIC

The pass transistor logic is used to drive the bit line. This bank of pass transistors will receive input from the
output of row decoder logic. The output of this logic will select particular bit line and complementary bit line
according to the row selection using decoder logic. The pass transistors terminate in sense amplifiers which have
the bit lines connected to it.

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4.2.1.1. CIRCUIT SCHEMATIC:

FIGURE 20: SCHEMATIC OF PASS TRANSISTOR LOGIC

4.2.1.2. SIZING OF GATES:

Sizing of gates was decided upon by calculating the load the transistor has to drive. This contains the load of the
complete bit line running along the row and the sense amplifier. The transistor used was NMOS (N_12_LLLVT)
since NMOS is faster owing to the higher mobility of electrons.
Using the calculated load, the size of the transistor was determined as:
L=60nm
W=400nm

4.2.1.3. LAYOUT:

FIGURE 21: LAYOUT OF A SINGLE PASS TRANSISTOR CELL

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FIGURE 22: LAYOUT OF PASS TRANSISTOR ARRAY

Parameter Value

Length (um) 486.275 µm

Width (um) 0.79 µm

Area(um2) 384.95 um sq

TABLE 8: SUMMARY OF LAYOUT OF PASS TRANSISTOR ARRAY

4.2.2. WORD LINE DRIVER

There should be an inverter chain to drive the long word line.
• We calculated f=3.47
• Value chosen f=4

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4.2.2.1. SCHEMATIC:

FIGURE 23: SCHEMATIC OF WORD LINE DRIVER

4.2.2.2. LAYOUT:

FIGURE 24: LAYOUT OF WORD LINE DRIVER

Parameter Value

Length (um) 6.06 µm

Width (um) 1.38 µm

Area (um2) 8.36 um sq

TABLE 9: SUMMARY OF WORD LINE DRIVER LAYOUT

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4.3. ATD SCHEME

The ATD (Address Transition Detector) circuit is heart of the asynchronous SRAM memory chip. It decides
total operation of the memory chip. Unlike the synchronous SRAM design which suffers from clock skew,
synchronization with external inputs etc., whereas an asynchronous SRAM design responds to any address
transition in the signal. This operation is very fast but it also suffers from problems which lead to undesired
operation due to change in the address signal because of noise. To overcome this problems ATD circuit was
used, which will check for address transition and generate a stretched pulse for the internal circuit to perform
its operation. Until the pulse generated we can keep the rest of the circuit of memory chip can be in non-
operating mode. ATD is used to generate a tile level control signal that is used to generate the required
signals such as enable for the block decoders, sense amplifiers, precharge, etc.

4.3.1. ATD INPUTS

S. No. Inputs Sources

1 A0-A16 Input buffers

2 CS_bar I/O

TABLE 10: ATD INPUTS

4.3.2. ATD OUTPUTS

S. No. Inputs Sources

Tile Level
1 ATD_OUT
Control Circuit

TABLE 11: ATD OUTPUTS

4.3.3. CONVENTIONAL ATD CIRCUIT:

ATD pulses coming from different XOR gates are finally OR-ed to obtain and a small pulse is generated.
This would require a 18 input OR gate. To avoid such a large fan-in gate, OR-ing is done in bunches of three.
This circuit has the drawback of changing pulse width with respect to different address transitions, and the
width is not controllable. There will also be significant variation across the process corners and a delay in the
pulse generation once an address change occurs. In order to get a uniform pulse of the desired pulse width, a
monostable multivibrator is used.

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FIGURE 25: SCHEMATIC OF A CONVENTIONAL ATD CIRCUIT

4.3.4. PULSE STRETCHING CIRCUIT:

A pulse stretching circuit is used along with a conventional ATD to control the pulse width. The operation of
memory chip depends upon the ATD pulse. The ATD pulse in turn depends upon operation of delay circuit.
Hence this delay circuit operation is critical in our design. The delay circuit operation should be PVT invariant to
generate proper ATD pulse width. A monostable multivibrator is used for this purpose. It provides a pulse width
of 200ps.

FIGURE 26: SCHEMATIC OF MONOSTABLE MULTIVIBRATOR

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• Capacitor (MIMCAP) (5x5 um sq) value used is 51.6fF

• Resistance (RNHR_LL) (480nm x 5 um x 7) value used is 74.6 KΩ

4.3.5. PULSE WIDTH ANALYSIS:

Process Corner Pulse Width (in ns)

tt 2.02

ff 1.93

ss 1.97

snfp 2.22

fnsp 1.78

TABLE 12: PULSE WIDTH ANALYSIS AT VARIOUS PROCESS CORNERS AT 27 C

TEMPERATURE (deg C) PULSE WIDTH (ns)

-20 2.0990

0 2.0689

27 2.0330

40 2.0176

80 1.9844

TABLE 13: PULSE WIDTH ANALYSIS AT TT CORNER AT VARIOUS TEMPERATURES

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4.3.6. ATD LAYOUT:

FIGURE 27: ATD CELL LAYOUT

FIGURE 28: ATD ARRAY LAYOUT

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Parameter Value

Length (um) 5.99 µm

Width (um) 1.975 µm

Area (um2) 11.83 um sq

TABLE 14: SUMMARY OF ATD CELL LAYOUT

4.3.7. MONOSTABLE MULTIVIBRATOR LAYOUT:

FIGURE 29: MONOSTABLE MULTIVIBRATOR LAYOUT

Parameter Value

Length (um) 27 µm

Width (um) 13.1 µm

Area (um2) 353.7 um sq

TABLE 15: SUMMARY OF MONOSTABLE MULTIVIBRATOR LAYOUT

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4.3.8. ATD SIMULATIONS:

FIGURE 30: ATD SIMULATION

4.3.9. MONOSTABLE MULTIVIBRATOR SIMULATIONS:

FIGURE 31: MONOSHOT SIMULATION

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4.4. DECODING SCHEME

4.4.1. BLOCK DECODING

4.4.1.1. SCHEME USED

• A 3:8 static CMOS decoder is used as a block decoder to select the row and column decoders of one of
the 8 memory banks at any given time.
• An active high control signal from the ATD is used as the enable “EN” signal of the block decoder.
• Using the enable signal at the input stage reduces the fan-out and minimizes power.
• The block decoder has been progressively sized for minimum path delay and proper driving capability for
low power design.
• The 3 MSBs of the address bus are the inputs to the block decoder.
• The outputs are used to select the row and column decoder of any one memory bank.

FIGURE 32: BLOCK DECODER

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4.4.1.2. ADDRESS DECODE CIRCUITRY WITH SCHEMATIC

FIGURE 33: GATE LEVEL IMPLEMENTATION

4.4.1.3. BLOCK DECODER INPUTS AND OUTPUTS

Destination
Inputs Outputs Sources

Row and
Column
A16-14 D0-D7 ATD circuit Decoder

TABLE 16: BLOCK DECODER INPUTS AND OUTPUTS

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4.4.1.4. BLOCK DECODER CIRCUIT SCHEMATIC SIMULATION

A, B, C are the 3 MSBs of the address bus, “en” is the enable signal and D0-D7 are the output signals of the
Block decoder.

FIGURE 34: BLOCK DECODER SCHEMATIC SIMULATION

4.4.1.5. BLOCK DECODER CIRCUIT LAYOUT

FIGURE 35: BLOCK DECODER LAYOUT

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• Length of layout = 7.92um

• Width of layout = 3.62um
• Area of layout = 28.67 um sq

4.4.1.6. BLOCK DECODER POST EXTRACTION SIMULATION

FIGURE 36: BLOCK DECODER POST EXTRACTION SIMULATION

4.4.1.7. BLOCK DECODER TIMING

Delay before extraction (ps) Delay after extraction (ps)

90 139

TABLE 17: BLOCK DECODER TIMING

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4.4.2. ROW DECODING

4.4.2.1. SCHEME USED

• A hierarchical decoding scheme has been used for row decoding to select the bitlines.
• A 6:64 static CMOS row decoder has been made using two 3:8 static CMOS decoders.
• The next 6 MSB’s after the first 3 MSBs of the address bus are the inputs to the row decoder.
• The enable signal is obtained from one of the output signals of the block decoder.
• The output signals of the row decoder is active low to aid in the subsequent circuitry.

4.4.2.2. ROW DECODE CIRCUITRY WITH SCHEMATIC

FIGURE 37: GATE LEVEL IMPLEMENTATION

4.4.2.3. ROW DECODER INPUTS AND OUTPUTS

Inputs Outputs Sources Destination

A13-A8 R0-R63 Block Decoder Pass Transistor

TABLE 18: ROW DECODER INPUTS AND OUTPUTS

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4.4.2.4. ROW DECODER CIRCUIT SCHEMATIC SIMULATION

FIGURE 38: ROW DECODER SCHEMATIC SIMULATION

4.4.2.5. ROW DECODER CIRCUIT LAYOUT

FIGURE 39: ROW DECODER LAYOUT

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• Length of layout = 91.075 um

• Width of layout = 14.025 um
• Area of layout = 1277.32 um sq

FIGURE 40: PART OF THE ROW DECODER LAYOUT SHOWING METALS

4.4.2.6. ROW DECODER POST EXTRACTION SIMULATION

FIGURE 41: ROW DECODER POST EXTRACTION SIMULATION

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4.4.2.7. ROW DECODER TIMING

Delay before Delay after

extraction (ps) extraction (ps)

192.5 205.5

TABLE 19: ROW DECODER TIMING

4.4.3. COLUMN DECODING

4.4.3.1. SCHEME USED

• A hierarchical decoding scheme has been used for column decoding to select the wordlines.
• An 8:256 static CMOS decoder is used as a column decoder.
• It is made using a 6:64 and a 2:4 static CMOS decoder.
• The last 8 bits of the address bus are the inputs of this decoder.
• The enable signal is obtained from one of the 8 outputs of the block decoder.
• A 3 stage buffer is used at the output of 2:4 decoder to be able to drive 64 NOR gates and also to be able
to be combined with the active low outputs of the 6:64 decoder using NOR gates.

4.4.3.2. COLUMN DECODER CIRCUITRY WITH SCHEMATIC

FIGURE 42: GATE LEVEL IMPLEMENTATION

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4.4.3.3. COLUMN DECODER INPUTS AND OUTPUTS

Inputs Outputs Sources Destination

Wordline
A7-A0 C0-C255 Block Decoder driver

TABLE 20: COLUMN DECODER INPUTS AND OUTPUTS

4.4.3.4. COLUMN DECODER SCHEMATIC SIMULATION

FIGURE 43: COLUMN DECODER SCHEMATIC SIMULATION

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4.4.3.5. COLUMN DECODER CIRCUIT LAYOUT

FIGURE 44: LAYOUT OF COLUMN DECODER

• Length of layout = 396.455um

• Width of layout = 28.185 um
• Area of layout = 11,174.0842 um sq.

FIGURE 45: PART OF THE LAYOUT OF COLUMN DECODER SHOWING METALS

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4.4.3.6. COLUMN DECODER POST EXTRACTION SIMULATION

FIGURE 46: COLUMN DECODER POST EXTRACTION SIMULATION

4.4.3.7. COLUMN DECODER TIMING

Delay before extraction Delay after extraction

(ps) (ps)

198 218

TABLE 21: COLUMN DECODER TIMING

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4.5. CORE I/O

4.5.1. PRECHARGE CIRCUITRY

4.5.1.1. SCHEME USED

• Precharging is done at the end of every clock cycle.
 • A static precharge scheme is used.
• Static precharge transistors are used to avoid the bit-lines floating, when the core is not in use.
 Also, they do not affect the normal operation of the core in any way.
• Equalization transistor is also used to ensure the BL and BL_BAR lines equal at the start of read
operation.

4.5.1.2. INPUTS AND OUTPUTS USED

Signal Type Source input

PRE_EN IN From control signal generation circuit followed by buffers
BL OUT Connected to the bit line of the SRAM cell
BL_BAR OUT Connected the bit line bar of SRAM cell

TABLE 22: INPUT AND OUTPUT OF PRECHARGE CIRCUIT

4.5.1.3. PRECHARGE CIRCUITRY ROUTING

• Every row of SRAM Core has a precharge circuit at the right / left. We have 64 rows in a bank and each
row has 8 bit lines so one bank contain 512 precharge circuits and there are 8 such banks. All have same
 scheme.
• PMOS in the middle are controlled by PRE_SEL control signal. The corner PMOS (static PMOS) whose
 gates are grounded, are always ON.
 • The Drains of the above PMOS are connected to BL and BL_BAR of the SRAM Core.
• When PRE_SEL is low, BL and BL_BAR are pulled high, this is done usually when the SRAM is not in
 operation, after a Read / Write is performed in the core.
• PMOS at the bottom is an equalization transistor, added in order to equalize the BL and BL_BAR
whenever precharge is done.

4.5.1.4. ESTIMATED LOAD CAPACITANCE ON OUTPUTS

• Bit-Line load Capacitance = 200 fF
• Bit-Line resistance (Pex Extracted) = 600 ohms



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4.5.1.5. PRECHARGE CIRCUIT SCHEMATIC

FIGURE 47: PRECHARGE CIRCUIT SCHEMATIC

4.5.1.6. PRECHARGE CIRCUIT LAYOUT

FIGURE 48: LAYOUT OF PRECHARGE CIRCUIT

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• Length of layout = 0.785 um

• Width of layout = 0.765 um
• Area of layout = 0.6 um sq

4.5.2. SENSE AMPLIFIER

In memory design, it is imperative to design robust and highly sensitive sense amplifiers to improve the speed of
the memory and thus, they are one of the primary building blocks in the memory design. The large bit-line
capacitance due to lengthy bitlines, is one of the main bottlenecks to the performance of on-chip caches. The
speed of the overall design is heavily stunted by the signal delay over long and highly loaded interconnects due to
increased capacitance and resistance, which also limits the signal swing.

4.5.2.1. DIFFERENT TOPOLOGIES

VOLTAGE MODE SENSE AMPLIFIER
The VSA detects the voltage difference on the bit lines and gives the output. The possible voltage mode sense
amplifiers are like single ended sense amplifiers, Cross-coupled sense amplifiers and differential amplifiers.
Based on the requirements of the design different types of VSA are used.

FIGURE 49: CROSS COUPLED VOLTAGE MODE SENSE AMPLIFIER

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CURRENT MODE SENSE AMPLIFIER

In advanced memories, due to technology scaling the number of cells attached to the bit lines increases. This
results in increase in the bit line capacitance. In such schemes, using the voltage mode SA will not help in keeping
the high performance. Thus to read the bit lines with such large capacitance we need faster sensing scheme like
current mode sense amplifier. The CSA reduces the delay, as they apply provide very low common input/output
impedances, which result in reduced voltage swing, substrate current and cross talk.

FIGURE 50: CURRENT MODE SENSE AMPLIFIER

CHARGE TRANSFER SENSE AMPLIFIER

Charge Transfer Sense Amplifier (CTSA) works on the principle of charge redistribution from higher capacitance
bit lines to lower capacitance sense amplifier output node. This results in high speed operation and lower power
consumption due to low voltage swing on the bit-lines. The basic concept behind charge-transfer amplification is
to produce voltage gain by exploiting charge conservation among capacitive devices. For a series connection of
two capacitive elements in a system for which charge is conserved, the product of the voltage across the first
element and its capacitance must be equal the product of the voltage across the second element and its capacitance
as shown in the following equation.

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Charge Transfer Sense Amplifier (CTSA) overcomes most of these problems and is emerging as an efficient
sensing technique for low power memories. The CTSA offers better performance and has lower power
consumption than other topologies, namely the voltage sense amplifier and current sense amplifier. The basic
working principle of the CTSA is to produce voltage gain by exploiting charge conservation amongst capacitive
devices, viz. distribution from the high capacitance node to the low capacitance node. This allows detection of
extremely low bit-line swing, resulting in higher sensitivity, along with lower sense delay.

4.5.2.2. INPUTS USED

TABLE 23: INPUTS TO SENSE AMPLIFIER

S. No. Inputs Sources

1 Sense Control Circuit
2 Y_sel Control circuit
3 Pre_ch Control circuit
4 Bit line Memory array
5 Bit line’ Memory array

4.5.2.3. CTSA OUTPUTS

TABLE 24: CTSA OUTPUTS

S. No. Inputs Routed to

1 DATA_OUT DATA I/O

The output of the CTSA can drive load capacitance up to 200 fF.

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4.5.2.4. CTSA CIRCUIT SCHEMATIC

FIGURE 51: CHARGE TRANSFER SENSE AMPLIFIER

4.5.2.5. CTSA SCHEMATIC SIMULATION RESULTS

FIGURE 52: SCHEMATIC SIMULATION WAVEFORM OF CTSA

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Bias Voltage Bit(ps) Bit bar (ps)

0 23.59 28.1

0.4 49 20

0.6 132 67

0.8 132 132

TABLE 25: DELAY ANALYSIS OF SENSE AMPLIFIER

4.5.2.6. REFERENCE VOLTAGE CIRCUIT SCHEMATIC FOR CTSA

FIGURE 53: SCHEMATIC OF REFERENCE VOLTAGE CIRCUIT

Monte Carlo simulation was done on this circuit to check for PVT variations. The PVT readings have been shown
in the next figure

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Temperature (degree C) Voltage (mV)

-25 560
0 556
10 554
20 552
40 548
60 545

TABLE 26: VOLTAGE VARIATIONS WITH TEMPERATURE

4.5.2.7. CTSA LAYOUT

FIGURE 54: LAYOUT OF CTSA

• Length of layout = 6.135 um
• Width of layout = 1 um
• Area of layout = 6.135 um sq

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FIGURE 55: LAYOUT OF ARRAY OF 16 CTSA

FIGURE 56: LAYOUT OF REFERENCE VOLTAGE CIRCUIT

• Length of layout = 1.845 um

• Width of layout = 1.845 um
• Area of layout = 1.54 um sq

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5. INTEGRATION

5.1 CRITICAL PATH SIMULATION

5.1.1 CRITICAL PATH BLOCK DIAGRAM

FIGURE 57: BLOCK DIAGRAM OF CRITICAL PATH

5.1.2 CRITICAL PATH TIMING

CORNER READ DELAY (ns) WRITE DELAY (ps)

tt 3.8 40
ss 4.2 51
ff 3.4 30

TABLE 27: CRITICAL PATH TIMING ANALYSIS

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5.1.3 FULL CHIP LAYOUT INTEGRATION

FIGURE 58: INTEGRATION OF CTSA WITH CORE

FIGURE 59: INTEGRATION OF CORE WITH REFERENCE VOLTAGE GENERATOR

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FIGURE 60: INTEGRATION OF CORE WORD LINE DRIVER

FIGURE 61: INTEGRATION OF CORE WORD LINE DRIVER SHOWING METALS

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FIGURE 62: INTEGRATION OF COLUMN DECODER WITH CORE

FIGURE 63: INTEGRATION OF PASS TRANSISTORS WITH CORE

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FIGURE 64: TOP LEVEL CHIP LAYOUT

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5.2 SUMMARY OF AREA DISTRIBUTION

Components Area of single No. of components in Total Area

component chip
SRAM Core Array 194,000 um sq. 8 1.552 mm sq.
Precharge circuitry 307.2 um sq. 8 0.0024 mm sq.
Sense Amplifier and 2889.104 um sq. 8 0.023 mm sq.
Reference Voltage
Generator
Pass Transistor Logic 384.95 um sq. 8 0.003 mm sq.
Block Decoder 28.67 um sq. 1 0.000028 mm sq.
Row Decoder 1,277.32 um sq. 8 0.01 mm sq.
Column Decoder 11,174.0842 um sq. 8 0.089 mm sq.
ATD 410.71 um sq. 1 0.0032 mm sq.

TABLE 28: SUMMARY

5.3 COMPLETE SUMMARY

Achieved Specifications
Total Chip Area : 2.1 mm2 (taking 30% overhead for IO pads)
• Die Area : 1.682 mm2
• Core Area : 1.55 mm2
• Core Efficiency : 77.6% (without IO Pads)

Estimated Specifications

• Total Chip Area : 2.8 mm2

• Core Efficiency : > 65%

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REF ERENCES

[1] “Low-Leakage asymmetric SRAM Cell”, Azizi et.al. IEEE TVLSI vol.11 no.-4, 2003.
[2] “Static noise margin analysis of SRAM cell”; Seevnick et.al. IEEE JSSC vol.-22 no.-5, 1987.
[3] “Robust low power CMOS Precharge Logic”, Berg et.al. IEEE 2013.
[4] Rabaey, Chandrakasan and Nikolic, “Designing Memory Array Structures” in Digital Integrated Circuits a
Design Perspective, 2nd ed.,vol. 1. Noida, Pearson India, 2016, pp. 657-662.
[5] “Gain-Enhancement Differential Amplifier Using Positive Feedback”, Phuoc T. Tran et. al. in MWSCAS,
IEEE, 2012.
[6] “Novel Design Technique of Address Decoder for SRAM”, Arvind Kumar Mishra , Debiprasad Priyabrata
Acharya , Pradip Kumar Patra, 2014 IEEE International Conference on Advanced Communication Control and
Computing Technologies (ICACCCT).
[7] Betty Prince, “Basic Memory Architecture and Cell Structure” in Semiconductor Memory: Design and
Application 2nd ed.
[8] “A word-line boost driver designed for Low Operating Voltage 6T- SRAMs” Shakir et.al. MWSCAS- IEEE
2012.

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