NXP - PHGL S A0002809956 1 1750376

NXP Semiconductors Document Number T4240
Data Sheet: Technical Data Rev. 1, 05/2016
T4240
QorIQ T4240 Data Sheet
Features • 32 SerDes lanes at up to 10 Gb/s
• 12 e6500 cores built on Power Architecture® • Ethernet interfaces
technology and arranged as clusters of four e6500 – Up to four 10 Gbps Ethernet MACs
cores sharing a 2 MB L2 cache – Up to sixteen 1 Gbps Ethernet MACs
– Combinations of 1 Gbps and 10 Gbps Ethernet
• 1.5 MB CoreNet platform cache (CPC)
MACs
• Hierarchical interconnect fabric – IEEE Std 1588™ support
– CoreNet fabric supporting coherent and non-
• High-speed peripheral interfaces
coherent transactions with prioritization and
– Four PCI Express 2.0/3.0 controllers running at up
bandwidth allocation amongst CoreNet end-points
to 8 GT/s with one controllers supporting end-point,
– 1.6 Tbps coherent read bandwidth
single-root I/O virtualization (SR-IOV)
• Three 64-bit DDR3 SDRAM memory controllers – Two Serial RapidIO 2.0 controllers running at up to
– DDR3 and DDR3L with ECC and interleaving 5 Gbaud
support – Interlaken look-aside interface for TCAM
connection
• Data Path Acceleration Architecture (DPAA)
incorporating acceleration for the following functions: • Additional peripheral interfaces
– Packet parsing, classification, and distribution – Two Serial ATA (SATA 2.0) controllers
(Frame Manager 1.1) – Two high-speed USB 2.0 controllers with integrated
– Queue management for scheduling, packet PHY
sequencing, and congestion management (Queue – Enhanced secure digital host controller (SD/MMC/
Manager 1.1) eMMC)
– Hardware buffer management for buffer allocation – Enhanced Serial peripheral interface (eSPI)
and de-allocation (Buffer Manager 1.1) – Four I2C controllers
– Cryptography Acceleration (SEC 5.0) – Four 2-pin UARTs or two 4-pin DUARTs
– RegEx Pattern Matching Acceleration (PME 2.0) – Integrated flash controller supporting NAND and
– Decompression/Compression Acceleration (DCE NOR flash
1.0)
• Three 8-channel DMA engines
– DPAA chip-to-chip interconnect via RapidIO
Message Manager (RMan 1.0) • 1932 FC-PBGA package, 45 mm x 45 mm, 1mm pitch
NXP reserves the right to change the production detail specifications as may be
required to permit improvements in the design of its products.
© 2014–2016 NXP B.V.
Table of Contents
1 Overview.............................................................................................. 3 3.16 JTAG controller.........................................................................124
2 Pin assignments.................................................................................... 3 3.17 I2C interface.............................................................................. 127
2.1 1932 ball layout diagrams......................................................... 4 3.18 GPIO interface...........................................................................130
2.2 Pinout list...................................................................................10 3.19 High-speed serial interfaces (HSSI).......................................... 132
3 Electrical characteristics.......................................................................73 4 Hardware design considerations...........................................................188
3.1 Overall DC electrical characteristics......................................... 73 4.1 System clocking........................................................................ 188
3.2 Power sequencing......................................................................80 4.2 Power supply design..................................................................204
3.3 Power-down requirements.........................................................82 4.3 Decoupling recommendations................................................... 213
3.4 Power characteristics................................................................. 83 4.4 SerDes block power supply decoupling recommendations.......213
3.5 Power-on ramp rate................................................................... 90 4.5 Connection recommendations................................................... 214
3.6 Input clocks............................................................................... 91 4.6 Thermal......................................................................................225

3.7 RESET initialization..................................................................96 4.7 Recommended thermal model...................................................226
3.8 DDR3 and DDR3L SDRAM controller.................................... 97 4.8 Thermal management information............................................ 226
3.9 eSPI interface.............................................................................103 5 Package information.............................................................................229
3.10 DUART interface...................................................................... 106 5.1 Package parameters for the FC-PBGA......................................229
3.11 Ethernet interface, Ethernet management interface 1 and 2, 5.2 Mechanical dimensions of the FC-PBGA................................. 229
IEEE Std 1588........................................................................... 107 6 Security fuse processor.........................................................................231
3.12 USB interface............................................................................ 116 7 Ordering information............................................................................231
3.13 Integrated flash controller..........................................................118 7.1 Part numbering nomenclature....................................................231
3.14 Enhanced secure digital host controller (eSDHC).....................121 7.2 Orderable part numbers addressed by this document................232
3.15 Multicore programmable interrupt controller (MPIC).............. 123 8 Revision history....................................................................................234
QorIQ T4240 Data Sheet, Rev. 1, 05/2016

2 NXP Semiconductors
Overview
1 Overview
The T4240 QorIQ integrated multicore communications processor combines 12 dual-
threaded cores built on Power Architecture® technology with high-performance data path
acceleration and network and peripheral bus interfaces required for networking, telecom/
datacom, wireless infrastructure, and military/aerospace applications.
This chip can be used for combined control, data path, and application layer processing in
routers, switches, gateways, and general-purpose embedded computing systems. Its high
level of integration offers significant performance benefits compared to multiple discrete
devices, while also simplifying board design.
This figure shows the block diagram of the chip.
Power Architecture Power Architecture Power Architecture Power Architecture

e6500 e6500 e6500 e6500
512 KB 64-bit DDR3/3L

32 KB 32 KB 32 KB 32 KB 32 KB 32 KB 32 KB 32 KB Plat Cache with ECC
D-Cache I-Cache D-Cache I-Cache D-Cache I-Cache D-Cache I-Cache
Plat Cache with ECC
2 MB Banked L2
Plat Cache with ECC
MPIC
CoreNet TM
PreBoot Loader
Coherency Fabric
Security Monitor PAMU PAMU PAMU (peripheral access management unit)
Internal BootROM
Power mgmt FMan FMan

Real-time
SEC QMan debug
InterlakenLA-1
SD/MMC Parse, classify, Parse, classify, 3x DMA Watch point

distribute distribute
SATA 2.0
SATA 2.0
eSPI cross-
PME BMan trigger
Buffer Buffer
4 x UART Perf Trace
Monitor
DCE RMan 1G 1G 1G 1G 1G 1G
4x I2C 1/10G 1/10G
sRIO
sRIO
1/10G 1/10G
PCle
PCle
PCle
PCle
Aurora
1G 1G 1G 1G 1G 1G
IFC
2 x USB2.0 w/PHY
16 lanes up to 10 GHz SerDes 16 lanes up to 10 GHz SerDes
Clocks/Reset
GPIO
CCSR
Figure 1. Block diagram
2 Pin assignments

NXP Semiconductors 3
Pin assignments
2.1 1932 ball layout diagrams

This table shows the complete view of the T4240 ball map. Figure 3, Figure 4, Figure 5,
and Figure 6 show quadrant views of the ballmap.

Pin assignments
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44
A A
B B
C C
D D
E E
F F
G G
H H
J SEE DETAIL A SEE DETAIL B J
K K
L L
M M
N N
P P
R R
T T
U U
V V
W W
Y Y
AA AA
AB AB
AC AC
AD AD
AE AE
AF AF
AG AG
AH AH
AJ AJ
AK AK
AL SEE DETAIL C SEE DETAIL D AL
AM AM
AN AN
AP AP
AR AR
AT AT
AU AU
AV AV
AW AW
AY AY
BA BA
BB BB
BC BC
BD BD
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44
DDR Interface 1 DDR Interface 2 DDR Interface 3 IFC DUART
I2C eSPI eSDHC MPIC LP Trust
Trust System Control ASLEEP Clocking DDR Clocking
Debug DFT JTAG SerDes 1 SerDes 2
SerDes 3 SerDes 4 USB PHY 1 and 2 USB CLK IEEE1588
Ethernet MI 1 Ethernet MI 2 Ethernet Cont. 1 Ethernet Cont. 2 DMA
Analog signals Power Ground No Connects
Figure 2. Complete BGA Map for the T4240

Pin assignments
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22
D1_ D1_ D1_ D1_ D1_ EC2_ EC2_ EC1_ EC1_ TSEC_C SD1_ SD1_ SD1_ SD1_
A A
G1VDD G1VDD G1VDD S1GND S1GND S1GND S1GND
MA MAPAR_ MBA MCKE MCKE RXD RXD RXD RX_ RX RX RX RX
[01] [02] [03] [01] [02] [03] [04]
[12] ERR_B [2] [0] [3] [0] [1] [2] DV LK_IN [1] [3] [5] [7]
D1_ D1_ D1_ D1_ D1_ D1_ EC2_ EC1_ SD1_ SD1_ SD1_ SD1_
B B
G1VDD G1VDD G1VDD GND GND S1GND S1GND S1GND S1GND S1GND
MA MA MA MA MCKE MCKE RX_ RX_ RX RX RX RX
[04] [05] [06] [002] [003] [05] [06] [07] [08] [09]
[11] [09] [14] [15] [2] [1] CLK CLK _B[1] _B[3] _B[5] _B[7]
D1_ D1_ GND_ EC2_ EC2_ EC1_ EC1_ SD1_ SD1_ SD1_ SD1_
C C
GND GND GND GND GND GND S1GND S1GND S1GND S1GND S1GND
MA MA DET RX_ RXD RXD TX_ RX RX RX RX
[009] [010] [011] [012] [013] [014] [10] [11] [12] [13] [14]
[08] [07] [1] DV [2] [0] EN [0] [2] [4] [6]
D1_ D1_ D1_ D1_ D1_ D1_ EC2_ EC2_ EC1_ SD1_ SD1_ SD1_ SD1_
D D
G1VDD GND GND EMI2_ S1GND S1GND S1GND S1GND S1GND
MA MDQ MDQ MDQS MDM MDQ RXD TXD GTX_ RX RX RX RX
[07] [015] [016] MDC [15] [16] [17] [18] [19]
[06] [02] [06] _B[09] [0] [05] [3] [0] CLK125 _B[0] _B[2] _B[4] _B[6]
D1_ D1_ D1_ D1_ D1_ D1_ EC2_ EC1_
E E
GND GND GND GND EMI2_ S1GND S1GND S1GND S1GND S1GND S1GND S1GND S1GND S1GND
MA MA MDQ MDQ MDQ MDQ GTX_ RXD
[021] [022] [023] [024] MDIO [20] [21] [22] [23] [24] [25] [26] [27] [28]
[04] [05] [03] [07] [01] [04] CLK125 [1]
D1_ D1_ D1_ D1_ EC2_ EC2_ EC1_ TSEC_C SD1_ SD1_ SD1_ SD1_
F F
G1VDD GND GND GND GND GND X1GND X1GND X1GND X1GND
MA MDQS MDQS MDQ TXD TXD GTX_ LK_OUT TX TX TX TX
[08] [025] [026] [027] [028] [029] [01] [02] [03] [04]
[03] [00] _B[00] [00] [1] [2] CLK [1] [3] [5] [7]
D1_ D1_ D1_ D1_ D1_ D1_ EC2_ EC2_ EC1_ SD1_ SD1_ SD1_ SD1_
G G
GND GND GND EMI1_ X1GND X1GND X1GND X1GND X1GND
MA MA MDQ MDQS MDQ MDQ TX_ TXD RXD TX TX TX TX
[034] [035] [036] MDC [05] [06] [07] [08] [09]
[01] [02] [10] [01] [09] [13] EN [3] [3] _B[1] _B[3] _B[5] _B[7]
D1_ D1_ D1_ D1_ D1_ D1_ EC2_ EC1_ SD1_ SD1_ SD1_ SD1_
H H
G1VDD GND GND GND EMI1_ X1GND X1GND X1GND X1GND X1GND
MDIC MDQ MDQS MDQS MDM MDQ GTX_ TXD TX TX TX TX
[09] [038] [039] [040] MDIO [10] [11] [12] [13] [14]
[1] [11] _B[01] _B[10] [1] [12] CLK [0] [0] [2] [4] [6]
D1_ D1_ D1_ D1_ D1_ TSEC_A SD1_ SD1_ SD1_ SD1_
J J
GND GND GND GND UART2_ UART2_ GND X1GND X1GND X1GND X1GND X1GND
MCK MCK MDQ MDQ MDQ LARM_O TX TX TX TX
[044] [045] [046] [047] SOUT SIN [048] [15] [16] [17] [18] [19]
_B[3] [3] [15] [14] [08] UT2 _B[0] _B[2] _B[4] _B[6]
D1_ D1_ D1_ D1_ D1_ EC1_ TSEC_A
K K
G1VDD GND GND GND UART2_ UART2_ X1GND X1VDD X1VDD X1VDD X1VDD X1VDD X1VDD X1VDD X1VDD
MCK MDQ MDQ MDQ MDQ TXD LARM_O
[10] [051] [052] [053] RTS_B CTS_B [20] [1] [2] [3] [4] [5] [6] [7] [8]
[0] [29] [28] [21] [20] [1] UT1
D1_ D1_ D1_ D1_ D1_ D1_ EC1_ TSEC_P SD1_ AVDD_ AGND_ AGND_ AVDD_ SD1_
L L
GND GND GND UART1_ GND LVDD X1GND X1GND
MCK MCK MDQ MDQ MDQ MDQ TXD ULSE_O PLL1_ SD1_ SD1_PLL SD1_PLL SD1_ PLL2_
[057] [058] [059] SOUT [060] [1] [21] [22]
[1] _B[0] [25] [24] [17] [16] [2] UT2 TPD PLL1 1 2 PLL2 TPD
D1_ D1_ D1_ D1_ D1_ EC1_ TSEC_P SD1_ SD1_ SD1_ SD1_
M M
G1VDD GND GND GND UART1_ UART1_ GND S1GND X1GND S1GND X1GND
MCK MDQS MDM MDQS MDM TXD ULSE_O IMP_ PLL1_ PLL2_ IMP_
[11] [062] [063] [064] RTS_B SIN [065] [29] [23] [30] [24]
_B[1] _B[12] [3] _B[11] [2] [3] UT1 CAL_RX TPA TPA CAL_TX
D1_ D1_ D1_ D1_ D1_ D1_ TSEC_T TSEC_T SD1_
N N
GND GND GND IIC2_ UART1_ IIC4_ IIC3_ S1GND S1VDD S1GND S1GND S1GND S1GND
MCK MCK MDQS MDQS MDQS MDQS RIG_IN RIG_IN REF_
[069] [070] [071] SCL CTS_B SCL SCL [31] [1] [32] [33] [34] [35]
_B[2] [2] [03] _B[03] [02] _B[02] 2 1 CLK2_B
D1_ D1_ D1_ D1_ D1_ SD1_ SD1_ SD1_
P P
G1VDD GND GND GND IIC2_ GND IIC4_ IIC3_ GND GND GND S1GND S1VDD S1VDD
MDIC MDQ MDQ MDQ MDQ REF_ REF_ REF_
[12] [074] [075] [076] SDA [077] SDA SDA [078] [079] [080] [36] [2] [3]
[0] [31] [30] [23] [22] CLK1 CLK1_B CLK2
D1_ D1_ D1_ D1_ D1_ D1_ SENSE SENSE
R R
GND GND GND IIC1_ IIC1_ DVDD DVDD LVDD LVDD S1GND S1GND S1GND S1GND S1GND
MAPAR_ MA MDQ MDQ MDQ MDQ VDD_ GND_
[083] [084] [085] SCL SDA [1] [2] [2] [3] [37] [38] [39] [40] [41]
OUT [00] [27] [26] [19] [18] CA CA
D1_ D1_ D1_ D1_ D1_
T T
G1VDD GND GND GND GND GND GND AVDD_ GND G1VDD VDD GND NC S1VDD S1VDD S1VDD S1VDD
MA MECC MECC MDQ MDQ
[13] [088] [089] [090] [091] [092] [093] D1 [094] [14] [01] [095] [45] [4] [5] [6] [7]
[10] [5] [4] [36] [37]
D1_ D1_ D1_ D1_ D1_ D1_ D1_ D1_ D1_ D1_
U U
GND GND GND GND G1VDD GND VDD GND VDD GND VDD GND
MBA MBA MECC MECC MDQ MDQ MDQ MDQ MDQ MDQ
[099] [100] [101] [102] [15] [103] [02] [104] [03] [105] [04] [106]
[0] [1] [1] [0] [32] [33] [44] [45] [40] [41]
D1_ D1_ D1_ D1_ D1_ D1_
V V
G1VDD D1_ GND GND GND GND D1_ GND G1VDD VDD GND VDD GND VDD GND VDD
MDQS MDM MDM MDQS MDM MDQS
[16] MRAS_B [113] [114] [115] [116] MVREF [117] [17] [09] [118] [10] [119] [11] [120] [12]
_B[17] [8] [4] _B[13] [5] _B[14]
D1_ D1_ D1_ D1_ D1_ D1_ D1_
W W
D1_ GND GND GND GND GND GND G1VDD GND VDD GND VDD GND VDD GND
MCS MDQS MDQS MDQS MDQS MDQS MDQS
MWE_B [128] [129] [130] [131] [132] [133] [18] [134] [16] [135] [17] [136] [18] [137]
_B[2] [08] _B[08] _B[04] [04] _B[05] [05]
D1_ D1_ D1_ D1_ D1_ D1_ D1_ D1_ D1_
Y Y
G1VDD GND GND GND GND G1VDD VDD GND VDD GND VDD GND VDD
MCS MECC MECC MDQ MDQ MDQ MDQ MDQ MDQ
[19] [145] [146] [147] [148] [20] [23] [149] [24] [150] [25] [151] [26]
_B[0] [7] [6] [38] [39] [46] [47] [42] [43]
D1_ D1_ D1_ D1_ D1_ D1_
AA AA
D1_ GND GND GND GND GND GND GND G1VDD GND VDD GND VDD GND VDD GND
MODT MECC MECC MDQ MDQ MDQ
MCAS_B [165] [166] [167] [168] [169] [170] [171] [21] [172] [30] [173] [31] [174] [32] [175]
[0] [3] [2] [34] [35] [61]
D1_ D1_ D1_ D1_ D1_ D1_ D1_ D1_ D1_
AB AB
G1VDD GND GND GND GND G1VDD VDD GND VDD GND VDD GND VDD
MODT MDQ MDQ MDQ MDQ MDM MDQS MDQ MDQ
[22] [182] [183] [184] [185] [23] [37] [186] [38] [187] [39] [188] [40]
[2] [52] [53] [48] [60] [7] _B[07] [62] [58]
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22
Figure 3. Detail A

Pin assignments
23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44
SD2_ SD2_ SD2_ SD2_ USB2_ SDHC_ SPI_ IFC_ IFC_ IFC_ IFC_
A A
S2GND S2GND S2GND S2GND S2GND SDHC_ SDHC_ SPI_ IFC_ GND
RX RX RX RX DRV DAT CS A A CS CS
[01] [02] [03] [04] [05] CLK CD_B MOSI CLK2 [001]
[1] [3] [5] [7] VBUS [2] _B[1] [30] [27] _B[6] _B[3]
SD2_ SD2_ SD2_ SD2_ USB2_ SDHC_ SDHC_ IFC_ IFC_ IFC_
B B
S2GND S2GND S2GND S2GND S2GND GND GND SPI_ IFC_ GND GND GND
RX RX RX RX PWR DAT DAT A CS CS
[06] [07] [08] [09] [10] [004] [005] CLK CLK0 [006] [007] [008]
_B[1] _B[3] _B[5] _B[7] FAULT [0] [3] [26] _B[5] _B[2]
SD2_ SD2_ SD2_ SD2_ USB2_ SDHC_ SPI_ SPI_ IFC_ IFC_ IFC_ IFC_ IFC_ IFC_
C C
S2GND S2GND S2GND S2GND S2GND SDHC_ SPI_ NC_
RX RX RX RX VBUS DAT CS CS A A CS CS CS CS
[11] [12] [13] [14] [15] WP MISO DET
[0] [2] [4] [6] CLMP [1] _B[0] _B[2] [31] [29] _B[7] _B[4] _B[0] _B[1]
SD2_ SD2_ SD2_ SD2_ USB_ USB_ SPI_ IFC_ IFC_ IFC_ IFC_ IFC_
D D
S2GND S2GND S2GND S2GND SDHC_ GND HRESET_ GND GND GND
RX RX RX RX IBIAS_ AGND CS PAR A AD WE WE
[16] [17] [18] [19] CMD [017] B [018] [019] [020]
_B[0] _B[2] _B[4] _B[6] REXT [1] _B[3] [1] [28] [31] _B[2] _B[3]
USB1_ IFC_ IFC_ IFC_ IFC_ IFC_
E E
S2GND S2GND S2GND S2GND S2GND S2GND S2GND S2GND X2GND SCAN_ TMP_ IFC_ IFC_ IFC_ IFC_
DRV USBCLK PAR AD AD AD WE
[20] [21] [22] [23] [24] [25] [26] [27] [01] MODE_B DETECT_B NDDQS PERR_B OE_B CLE
VBUS [0] [30] [29] [28] _B[0]
SD2_ SD2_ SD2_ SD2_ USB1_ IFC_ IFC_ IFC_ IFC_ IFC_ IFC_
F F
X2GND X2GND X2GND X2GND X2GND GND TEST_ PORESET_ GND GND GND
TX TX TX TX PWR PAR PAR AD RB RB WP
[02] [03] [04] [05] [06] [030] SEL_B B [031] [032] [033]
[1] [3] [5] [7] FAULT [3] [2] [27] _B[1] _B[0] _B[0]
SD2_ SD2_ SD2_ SD2_ USB1_ IFC_ IFC_ IFC_
G G
X2GND X2GND X2GND X2GND X2GND RESET_ NC NC NC NC IFC_ GND
TX TX TX TX VBUS ASLEEP AD AD AD IFC_BCTL
[07] [08] [09] [10] [11] REQ_B [01] [02] [03] [04] TE [037]
_B[1] _B[3] _B[5] _B[7] CLMP [26] [24] [25]
SD2_ SD2_ SD2_ SD2_ IFC_ IFC_ IFC_
H H
X2GND X2GND X2GND X2GND X2GND USB2_ NC GND NC NC GND NC GND IFC_ IFC_
TX TX TX TX AD AD NDDDR_
[12] [13] [14] [15] [16] UID [05] [041] [06] [07] [042] [08] [043] CLK1 AVD
[0] [2] [4] [6] [22] [23] CLK
SD2_ SD2_ SD2_ SD2_ USB_ IFC_ IFC_
J J
X2GND X2GND X2GND X2GND USB1_ NC NC NC NC NC NC GND GND
TX TX TX TX AGND AD AD TRST_B TDI
[17] [18] [19] [20] UDM [09] [10] [11] [12] [13] [14] [049] [050]
_B[0] _B[2] _B[4] _B[6] [2] [20] [21]
USB_ IFC_ IFC_
K K
X2VDD X2VDD X2VDD X2VDD X2VDD X2VDD X2VDD X2VDD USB1_ GND NC NC GND NC NC GND
HVDD AD AD TMS TDO TCK
[1] [2] [3] [4] [5] [6] [7] [8] UDP [054] [15] [16] [055] [17] [18] [056]
[1] [18] [19]
SD2_ AVDD_ AGND_ AGND_ AVDD_ SD2_ USB_ IFC_ IFC_
L L
X2GND X2GND USB1_ NC NC NC NC NC NC GND EVT_B EVT_B CKSTP_
PLL1_ SD2_ SD2_PLL SD2_PLL SD2_ PLL2_ AGND AD AD
[21] [22] UID [19] [20] [21] [22] [23] [24] [061] [4] [3] OUT_B
TPD PLL1 1 2 PLL2 TPD [3] [16] [17]
SD2_ SD2_ SD2_ SD2_ USB_ IFC_ IFC_
M M
X2GND S2GND X2GND X2VDD USB2_ NC GND NC NC NC NC GND EVT_B EVT_B GND
IMP_ PLL1_ PLL2_ IMP_ AGND AD AD
[23] [28] [24] [9] UDM [25] [066] [26] [27] [28] [29] [067] [2] [1] [068]
CAL_RX TPA TPA CAL_TX [4] [14] [15]
SD2_ USB_ USB_ IFC_ IFC_ DMA2_
N N
S2GND S2GND S2GND S2GND S2GND X2GND USB2_ NC NC NC NC GND NC EVT_B GND CLK_
REF_ AGND HVDD AD AD DREQ
[29] [30] [31] [32] [33] [25] UDP [30] [31] [32] [33] [072] [34] [0] [073] OUT
CLK1_B [5] [2] [12] [13] _B[0]
SD2_ SD2_ SD2_ USB_ USB_ USB_ USB_ IFC_ IFC_ DMA2_ DMA1_ DMA2_
P P
S2VDD S2VDD S2GND GND NC NC NC NC NC GND
REF_ REF_ REF_ SVDD SVDD OVDD OVDD AD AD DDONE DREQ DACK
[1] [2] [34] [081] [35] [36] [37] [38] [39] [082]
CLK1 CLK2_B CLK2 [1] [2] [1] [2] [10] [11] _B[0] _B[0] _B[0]
FA_ IFC_ IFC_ DMA1_ DMA1_
R R
S2GND S2GND S2GND S2GND S2GND VDD_ PROG_ OVDD GND FA_ NC NC NC NC NC GND IRQ
ANALOG_ AD AD DACK DDONE
[35] [36] [37] [38] [39] LP SFP [1] [086] VL [40] [41] [42] [43] [44] [087] [05]
G_V [08] [09] _B[0] _B[0]
LP_ FA_ IFC_ IFC_
T T
S2VDD S2VDD S2VDD S2VDD AVDD_ PROG_ OVDD GND NC NC NC NC GND NC IRQ_ IRQ GND IRQ
TMP_ ANALOG_ AD AD
[3] [4] [5] [6] PLAT MTR [2] [096] [46] [47] [48] [49] [097] [50] OUT_B [07] [098] [08]
DETECT_B PIN [06] [07]
IFC_ IFC_
U U
VDD GND VDD GND VDD GND VDD OVDD GND NC GND NC NC NC NC GND IRQ IRQ IRQ
SYSCLK AD AD
[05] [107] [06] [108] [07] [109] [08] [3] [110] [51] [111] [52] [53] [54] [55] [112] [11] [02] [04]
[04] [05]
IFC_ IFC_
V V
GND VDD GND VDD GND VDD GND OVDD GND TH_ GND NC NC NC NC GND IRQ IRQ IRQ
RTC AD AD
[121] [13] [122] [14] [123] [15] [124] [4] [125] VDD [126] [56] [57] [58] [59] [127] [09] [00] [01]
[02] [03]
IFC_ IFC_
W W
VDD GND VDD GND VDD GND VDD OVDD GND TH_ GND NC NC NC GND NC IRQ IRQ GND IRQ
AD AD
[19] [138] [20] [139] [21] [140] [22] [5] [141] TPA [142] [60] [61] [62] [143] [63] [06] [03] [144] [10]
[00] [01]
SENSE SENSE
Y Y
GND VDD GND VDD GND VDD GND OVDD GND TD1_ GND GND GND GND GND GND GND GND G3VDD G3VDD
VDD_ VDD_
[152] [27] [153] [28] [154] [29] [155] [6] [156] CATHODE [157] [158] [159] [160] [161] [162] [163] [164] [01] [02]
PL CC
SENSE SENSE D3_ D3_ D3_ D3_ D3_ D3_ D3_ D3_
AA AA
VDD GND VDD GND VDD GND VDD OVDD GND TD1_ GND GND
GND_ GND_ MDQ MDQ MDQS MDQS MDQ MDQ MODT MODT
[33] [176] [34] [177] [35] [178] [36] [7] [179] ANODE [180] [181]
PL CC [59] [63] [07] _B[16] [57] [61] [1] [3]
D3_ D3_ D3_ D3_ D3_ D3_ D3_
AB AB
GND VDD GND VDD GND VDD GND G3VDD GND GND GND GND GND GND G3VDD
MDQ MDQ MDQS MDM MDQ MDQ MA
[189] [41] [190] [42] [191] [43] [192] [03] [193] [194] [195] [196] [197] [198] [04]
[58] [62] _B[07] [7] [56] [60] [13]
23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44
Figure 4. Detail B

Pin assignments
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22
D1_ D1_ D1_ D1_ D1_ D1_ D1_ D1_ D1_ D1_
AC MCS
_B[3]
MCS
_B[1]
GND
[199]
MDM
[6]
MDQS
_B[15]
GND
[200]
MDQ
[49]
GND
[201]
MDQ
[56]
MDQS
_B[16]
MDQS
[07]
MDQ
[63]
MDQ
[59]
GND
[202]
G2VDD
[01]
GND
[203]
VDD
[44]
GND
[204]
VDD
[45]
GND
[205]
VDD
[46]
GND
[206] AC
D1_ D1_ D1_ D1_ D1_
AD MA
[13]
G1VDD
[24]
GND
[219]
MDQS
_B[06]
GND
[220]
MDQ
[55]
MDQ
[51]
GND
[221]
MDQ
[57]
GND
[222]
GND
[223]
GND
[224]
GND
[225]
GND
[226]
G2VDD
[02]
VDD
[51]
GND
[227]
VDD
[52]
GND
[228]
VDD
[53]
GND
[229]
VDD
[54] AD
D1_ D1_ D1_ D1_ D1_ D2_ D2_ D2_ D2_ D2_
AE MODT
[1]
MODT
[3]
GND
[239]
MDQS
[06]
MDQ
[54]
MDQ
[50]
GND
[240]
MDQ
[51]
GND
[241]
MDQS
_B[07]
MDQS
[07]
MDQ
[63]
MDQ
[59]
GND
[242]
G2VDD
[03]
GND
[243]
VDD
[58]
GND
[244]
VDD
[59]
GND
[245]
VDD
[60]
GND
[246] AE
D2_ D2_ D2_ D2_ D2_ D2_
AF G1VDD
[25]
G1VDD
[26]
GND
[255]
GND
[256]
GND
[257]
GND
[258]
MDQ
[54]
MDQ
[50]
GND
[259]
MDM
[7]
MDQS
_B[16]
MDQ
[62]
MDQ
[58]
GND
[260]
G2VDD
[04]
VDD
[65]
GND
[261]
VDD
[66]
GND
[262]
VDD
[67]
GND
[263]
VDD
[68] AF
D2_ D2_ D2_ D2_ D2_ D2_ D2_
AG G2VDD
[05]
MODT
[1]
GND
[273]
MDQS
_B[15]
MDQS
_B[06]
MDQS
[06]
MDQ
[55]
GND
[274]
MDQ
[56]
MDQ
[57]
GND
[275]
GND
[276]
GND
[277]
GND
[278]
G2VDD
[06]
GND
[279]
VDD
[72]
GND
[280]
VDD
[73]
GND
[281]
VDD
[74]
GND
[282] AG
D2_ D2_ D2_ D2_ D2_ D2_ D2_ D2_ D2_
AH MODT
[3]
MCS
_B[1]
GND
[291]
MDM
[6]
MDQ
[49]
MDQ
[48]
MDQ
[53]
MDQ
[52]
GND
[292]
MDQ
[60]
MDQ
[61]
GND
[293]
D2_
MVREF
GND
[294]
G2VDD
[07]
VDD
[79]
GND
[295]
VDD
[80]
GND
[296]
VDD
[81]
GND
[297]
VDD
[82] AH
D2_
AJ MCS
_B[3]
G2VDD
[08]
GND
[307]
GND
[308]
GND
[309]
GND
[310]
GND
[311]
GND
[312]
GND
[313]
GND
[314]
GND
[315]
GND
[316]
AVDD_
D2
GND
[317]
G2VDD
[09]
GND
[318]
VDD
[86]
GND
[319]
VDD
[87]
GND
[320]
VDD
[88]
S3VDD
[1] AJ
D2_ D2_ D2_ D2_ D2_ D2_ D2_ D2_
AK MODT
[2]
MA
[13]
GND
[328]
MDQ
[42]
MDQ
[43]
GND
[329]
MDQ
[35]
MDQ
[34]
GND
[330]
MECC
[3]
MECC
[2]
GND
[331]
GND
[332]
OVDD
[8]
GND
[333]
VDD
[89]
GND
[334]
VDD
[90]
GND
[335]
VDD
[91]
S3GND
[01]
S3GND
[02] AK
D2_ D2_ D2_ D2_ D2_ D2_ D2_ SD3_ SD3_
AL G2VDD
[10]
MODT
[0]
GND
[344]
MDQ
[46]
MDQ
[47]
GND
[345]
MDQ
[39]
MDQ
[38]
GND
[346]
MECC
[7]
MECC
[6]
GND
[347]
D1_
TPA
DDRCLK
NC
[71]
TD2_ TD2_
ANODE CATHODE
NC
[72]
NC
[73]
S3GND
[06]
REF_
CLK1
REF_
CLK1_B
AL
D2_ D2_ D2_ D2_ D2_ D2_ SENSE SENSE
AM D2_
MWE_B
D2_
MCAS_B
GND
[352]
MDQS
_B[05]
MDQS
[05]
GND
[353]
MDQS
[04]
MDQS
_B[04]
GND
[354]
MDQS
[08]
MDQS
_B[08]
GND
[355]
D2_
TPA
NC
[75]
NC
[76]
VDD_
CB
GND_
CB
NC
[77]
S3GND
[07]
S3VDD
[7]
S3GND
[08]
S3GND
[09] AM
D2_ D2_ D2_ D2_ D2_ D2_ D2_ SD3_ SD3_
AN MCS
_B[2]
G2VDD
[11]
GND
[360]
MDM
[5]
MDQS
_B[14]
GND
[361]
MDQS
_B[13]
MDM
[4]
GND
[362]
MDQS
_B[17]
MDM
[8]
GND
[363]
NC
[78]
NC
[79]
NC
[80]
NC
[81]
NC
[82]
S3GND
[12]
IMP_
CAL_RX
X3GND
[01]
PLL1_
TPA
S3GND
[13] AN
D2_ D2_ D2_ D2_ D2_ D2_ D2_ SD3_ AVDD_ AGND_
AP D2_
MRAS_B
MCS
_B[0]
GND
[369]
MDQ
[40]
MDQ
[41]
GND
[370]
MDQ
[33]
MDQ
[32]
GND
[371]
MECC
[1]
MECC
[0]
GND
[372]
AVDD_
CGA1
GND
[373]
GND
[374]
GND
[375]
NC
[83]
X3GND
[03]
PLL1_
TPD
SD3_
PLL1
SD3_PLL
1
X3GND
[04] AP
D2_ D2_ D2_ D2_ D2_ D2_ D2_
AR G2VDD
[12]
MBA
[0]
GND
[379]
MDQ
[44]
MDQ
[45]
GND
[380]
MDQ
[37]
MDQ
[36]
GND
[381]
MECC
[5]
MECC
[4]
GND
[382]
AVDD_
CGA2
AVDD_
CGA3
AVDD_
CGB2
AVDD_
CGB1
X3GND
[05]
X3VDD
[1]
X3VDD
[2]
X3VDD
[3]
X3VDD
[4]
X3VDD
[5] AR
D2_ D2_ SD3_ SD3_ SD3_
AT MBA
[1]
MA
[10]
GND
[385]
GND
[386]
GND
[387]
GND
[388]
GND
[389]
GND
[390]
GND
[391]
GND
[392]
GND
[393]
GND
[394]
GND
[395]
GND
[396]
GND
[397]
GND
[398]
X3GND
[06]
TX
_B[0]
X3GND
[07]
TX
_B[2]
X3GND
[08]
TX
_B[4]
AT
D2_ D2_ D2_ D2_ D2_ D2_ D2_ D2_ D2_ D2_ D2_ D2_ D2_ SD3_ SD3_ SD3_
AU MA
[00]
G2VDD
[13]
GND
[404]
MDQ
[18]
MDQ
[22]
MDQS
_B[02]
MDM
[2]
MDQ
[16]
MDQ
[20]
GND
[405]
MDQ
[10]
MDQ
[14]
MDQS
_B[01]
MDM
[1]
MDQ
[08]
MDQ
[12]
X3GND
[11]
TX
[0]
X3GND
[12]
TX
[2]
X3GND
[13]
TX
[4]
AU
D2_ D2_ D2_ D2_ D2_ D2_ D2_ D2_ D2_ D2_ D2_ D2_ D2_ D2_ SD3_ SD3_
AV MAPAR_
OUT
MDIC
[0]
GND
[410]
MDQ
[19]
MDQ
[23]
MDQS
[02]
MDQS
_B[11]
MDQ
[17]
MDQ
[21]
GND
[411]
MDQ
[11]
MDQ
[15]
MDQS
[01]
MDQS
_B[10]
MDQ
[09]
MDQ
[13]
X3GND
[16]
X3GND
[17]
TX
_B[1]
X3GND
[18]
TX
_B[3]
X3GND
[19] AV
D2_ SD3_ SD3_
AW G2VDD
[14]
MCK
_B[2]
GND
[414]
GND
[415]
GND
[416]
GND
[417]
GND
[418]
GND
[419]
GND
[420]
GND
[421]
GND
[422]
GND
[423]
GND
[424]
GND
[425]
GND
[426]
GND
[427]
NC
[84]
X3GND
[21]
TX
[1]
X3GND
[22]
TX
[3]
X3GND
[23] AW
D2_ D2_ D2_ D2_ D2_ D2_ D2_ D2_ D2_ D2_ D2_ D2_ D2_ D2_
AY MCK
_B[0]
MCK
[2]
GND
[433]
MDQ
[26]
MDQ
[30]
MDQS
_B[03]
MDM
[3]
MDQ
[24]
MDQ
[28]
GND
[434]
MDQ
[02]
MDQ
[06]
MDQS
_B[00]
MDM
[0]
MDQ
[00]
MDQ
[04]
S3GND
[14]
S3GND
[15]
S3GND
[16]
S3GND
[17]
S3GND
[18]
S3GND
[19] AY
D2_ D2_ D2_ D2_ D2_ D2_ D2_ D2_ D2_ D2_ D2_ D2_ D2_ SD3_ SD3_ SD3_
BA MCK
[0]
G2VDD
[15]
GND
[437]
MDQ
[27]
MDQ
[31]
MDQS
[03]
MDQS
_B[12]
MDQ
[25]
MDQ
[29]
GND
[438]
MDQ
[03]
MDQ
[07]
MDQS
[00]
MDQS
_B[09]
MDQ
[01]
MDQ
[05]
S3GND
[23]
RX
_B[0]
S3GND
[24]
RX
_B[2]
S3GND
[25]
RX
_B[4]
BA
D2_ D2_ GND_ SD3_ SD3_ SD3_
BB MCK
[1]
MCK
_B[1]
DET
[2]
GND
[442]
GND
[443]
GND
[444]
GND
[445]
GND
[446]
GND
[447]
GND
[448]
GND
[449]
GND
[450]
GND
[451]
GND
[452]
GND
[453]
GND
[454]
S3GND
[28]
RX
[0]
S3GND
[29]
RX
[2]
S3GND
[30]
RX
[4]
BB
D2_ D2_ D2_ D2_ D2_ D2_ D2_ D2_ D2_ D2_ D2_ SD3_ SD3_
BC G2VDD
[16]
MCK
[3]
MCK
_B[3]
G2VDD
[17]
MA
[01]
MA
[04]
MA
[05]
G2VDD
[18]
MA
[07]
MA
[09]
MA
[12]
G2VDD
[19]
MA
[14]
MA
[15]
MCKE
[3]
G2VDD
[20]
S3GND
[33]
S3GND
[34]
RX
_B[1]
S3GND
[35]
RX
_B[3]
S3GND
[36] BC
D2_ D2_ D2_ D2_ D2_ D2_ D2_ D2_ D2_ D2_ D2_ SD3_ SD3_
BD G2VDD
[21]
MDIC
[1]
MA
[02]
MA
[03]
G2VDD
[22]
MA
[06]
MA
[08]
MA
[11]
G2VDD
[23]
MAPAR_
ERR_B
MBA
[2]
MCKE
[2]
G2VDD
[24]
MCKE
[0]
MCKE
[1]
G2VDD
[25]
S3GND
[38]
RX
[1]
S3GND
[39]
RX
[3]
S3GND
[40] BD
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22
Figure 5. Detail C

Pin assignments
23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44
D3_ D3_ D3_ D3_
AC VDD
[47]
GND
[207]
VDD
[48]
GND
[208]
VDD
[49]
GND
[209]
VDD
[50]
G3VDD
[05]
GND
[210]
AVDD_
D3
GND
[211]
MDQ
[51]
MDQ
[50]
GND
[212]
GND
[213]
GND
[214]
GND
[215]
GND
[216]
GND
[217]
GND
[218]
MCS
_B[3]
MCS
_B[1]
AC
D3_ D3_ D3_ D3_ D3_ D3_ D3_
AD GND
[230]
VDD
[55]
GND
[231]
VDD
[56]
GND
[232]
VDD
[57]
GND
[233]
G3VDD
[06]
GND
[234]
D3_
MVREF
GND
[235]
MDQ
[55]
MDQ
[54]
GND
[236]
MDQ
[43]
MDQ
[42]
GND
[237]
MDQ
[34]
MDQ
[35]
GND
[238]
MODT
[2]
G3VDD
[07] AD
D3_ D3_ D3_ D3_ D3_ D3_ D3_
AE VDD
[61]
GND
[247]
VDD
[62]
GND
[248]
VDD
[63]
GND
[249]
VDD
[64]
G3VDD
[08]
GND
[250]
NC
[64]
GND
[251]
MDQS
[06]
MDQS
_B[06]
GND
[252]
MDQ
[47]
MDQ
[46]
GND
[253]
MDQ
[38]
MDQ
[39]
GND
[254]
MODT
[0]
D3_
MCAS_B AE
D3_ D3_ D3_ D3_ D3_ D3_ D3_
AF GND
[264]
VDD
[69]
GND
[265]
VDD
[70]
GND
[266]
VDD
[71]
GND
[267]
G3VDD
[09]
GND
[268]
D3_
TPA
GND
[269]
MDQS
_B[15]
MDM
[6]
GND
[270]
MDQS
[05]
MDQS
_B[05]
GND
[271]
MDQS
_B[04]
MDQS
[04]
GND
[272]
G3VDD
[10]
MCS
_B[0]
AF
D3_ D3_ D3_ D3_ D3_ D3_ D3_
AG VDD
[75]
GND
[283]
VDD
[76]
GND
[284]
VDD
[77]
GND
[285]
VDD
[78]
G3VDD
[11]
GND
[286]
NC
[65]
GND
[287]
MDQ
[49]
MDQ
[48]
GND
[288]
MDQS
_B[14]
MDM
[5]
GND
[289]
MDM
[4]
MDQS
_B[13]
GND
[290]
MCS
_B[2]
D3_
MWE_B AG
D3_ D3_ D3_ D3_ D3_ D3_
AH GND
[298]
VDD
[83]
GND
[299]
VDD
[84]
GND
[300]
VDD
[85]
GND
[301]
G3VDD
[12]
GND
[302]
NC
[66]
GND
[303]
MDQ
[53]
MDQ
[52]
GND
[304]
MDQ
[41]
MDQ
[40]
GND
[305]
MDQ
[32]
MDQ
[33]
GND
[306]
D3_
MRAS_B
G3VDD
[13] AH
D3_ D3_ D3_ D3_ D3_ D3_
AJ S3VDD
[2]
S3VDD
[3]
S3VDD
[4]
S4VDD
[1]
S4VDD
[2]
S4VDD
[3]
S4VDD
[4]
GND
[321]
GND
[322]
NC
[67]
NC
[68]
GND
[323]
GND
[324]
GND
[325]
MDQ
[45]
MDQ
[44]
GND
[326]
MDQ
[36]
MDQ
[37]
GND
[327]
MBA
[0]
MBA
[1]
AJ
D3_ D3_ D3_
AK S3GND
[03]
S3GND
[04]
S3GND
[05]
S4GND
[01]
S4GND
[02]
S4GND
[03]
S4GND
[04]
S4GND
[05]
NC
[69]
NC
[70]
GND
[336]
MECC
[3]
MECC
[2]
GND
[337]
GND
[338]
GND
[339]
GND
[340]
GND
[341]
GND
[342]
GND
[343]
G3VDD
[14]
MA
[10]
AK
SD3_ SD4_ SD4_ SD4_ D3_ D3_ D3_ D3_ D3_ D3_ D3_ D3_
AL S3VDD
[5]
REF_
CLK2
S3VDD
[6]
S4VDD
[5]
REF_
CLK1
S4VDD
[6]
REF_
CLK2_B
REF_
CLK2
S4GND
[06]
NC
[74]
GND
[348]
GND
[349]
MECC
[7]
MECC
[6]
MDQS
_B[08]
MDQS
[08]
GND
[350]
MDQ
[26]
MDQ
[27]
GND
[351]
MAPAR_
OUT
MA
[00]
AL
SD3_ SD4_ D3_ D3_ D3_ D3_ D3_ D3_ D3_
AM S3GND
[10]
REF_
CLK2_B
S3GND
[11]
S4GND
[07]
REF_
CLK1_B
S4GND
[08]
S4GND
[09]
S4GND
[10]
S4GND
[11]
X4GND
[01]
GND
[356]
MECC
[4]
MECC
[5]
GND
[357]
MDM
[8]
MDQS
_B[17]
GND
[358]
MDQ
[30]
MDQ
[31]
GND
[359]
MDIC
[0]
G3VDD
[15] AM
SD3_ SD3_ SD4_ SD4_ SD4_ SD4_ D3_ D3_ D3_ D3_ D3_ D3_
AN PLL2_
TPA
X3GND
[02]
IMP_
CAL_TX
IMP_
CAL_RX
X4GND
[02]
PLL1_
TPA
S4GND
[12]
PLL2_
TPA
X4GND
[03]
IMP_
CAL_TX
X4VDD
[1]
GND
[364]
GND
[365]
GND
[366]
MECC
[0]
MECC
[1]
GND
[367]
MDQS
_B[03]
MDQS
[03]
GND
[368]
MCK
_B[2]
MCK
[2]
AN
AGND_ AVDD_ SD3_ SD4_ AVDD_ AGND_ AGND_ AVDD_ SD4_ D3_ D3_ D3_ D3_ D3_ D3_ D3_
AP SD3_PLL
2
SD3_
PLL2
PLL2_
TPD
PLL1_
TPD
SD4_
PLL1
SD4_PLL
1
X4GND
[04]
SD4_PLL
2
SD4_
PLL2
PLL2_
TPD
X4GND
[05]
MDQ
[12]
MDQ
[08]
MDM
[1]
GND
[376]
MDQ
[11]
GND
[377]
MDM
[3]
MDQS
_B[12]
GND
[378]
G3VDD
[16]
MCK
_B[1]
AP
D3_ D3_ D3_ D3_ D3_ D3_ D3_ D3_ D3_
AR X3VDD
[6]
X3VDD
[7]
X3VDD
[8]
X4VDD
[2]
X4VDD
[3]
X4VDD
[4]
X4VDD
[5]
X4VDD
[6]
X4VDD
[7]
X4VDD
[8]
X4VDD
[9]
MDQ
[13]
MDQ
[09]
MDQS
_B[10]
MDQS
_B[01]
MDQ
[10]
GND
[383]
MDQ
[24]
MDQ
[25]
GND
[384]
MCK
_B[0]
MCK
[1]
AR
SD3_ SD4_ SD4_ SD4_ SD4_ D3_ D3_ D3_ D3_ D3_
AT X3GND
[09]
TX
_B[6]
X3GND
[10]
TX
_B[0]
X4GND
[06]
TX
_B[2]
X4GND
[07]
TX
_B[4]
X4GND
[08]
TX
_B[6]
X4GND
[09]
GND
[399]
GND
[400]
GND
[401]
MDQS
[01]
MDQ
[14]
GND
[402]
MDQ
[28]
MDQ
[29]
GND
[403]
MCK
[0]
G3VDD
[17] AT
SD3_ SD4_ SD4_ SD4_ SD4_ D3_ D3_ D3_ D3_ D3_ D3_
AU X3GND
[14]
TX
[6]
X3GND
[15]
TX
[0]
X4GND
[10]
TX
[2]
X4GND
[11]
TX
[4]
X4GND
[12]
TX
[6]
X4GND
[13]
X4GND
[14]
MDQ
[04]
MDM
[0]
GND
[406]
MDQ
[15]
GND
[407]
MDQ
[19]
GND
[408]
GND
[409]
MCK
_B[3]
MCK
[3]
AU
SD3_ SD3_ SD4_ SD4_ SD4_ SD4_ D3_ D3_ D3_ D3_ D3_ D3_ D3_
AV TX
_B[5]
X3GND
[20]
TX
_B[7]
X4GND
[15]
TX
_B[1]
X4GND
[16]
TX
_B[3]
X4GND
[17]
TX
_B[5]
X4GND
[18]
TX
_B[7]
X4GND
[19]
MDQ
[05]
MDQS
_B[09]
MDQ
[03]
GND
[412]
MDQS
[02]
MDQ
[18]
MDQ
[23]
GND
[413]
G3VDD
[18]
MDIC
[1]
AV
SD3_ SD3_ SD4_ SD4_ SD4_ SD4_ D3_ D3_ D3_ D3_ D3_
AW TX
[5]
X3GND
[24]
TX
[7]
X4GND
[20]
TX
[1]
X4GND
[21]
TX
[3]
X4GND
[22]
TX
[5]
X4GND
[23]
TX
[7]
X4GND
[24]
GND
[428]
GND
[429]
MDQ
[02]
GND
[430]
MDQS
_B[02]
GND
[431]
MDQ
[22]
GND
[432]
MA
[01]
MA
[02]
AW
D3_ D3_ D3_ D3_ D3_ D3_ D3_
AY S3GND
[20]
S3GND
[21]
S3GND
[22]
S4GND
[13]
S4GND
[14]
S4GND
[15]
S4GND
[16]
S4GND
[17]
S4GND
[18]
S4GND
[19]
S4GND
[20]
X4GND
[25]
MDQ
[00]
MDQS
[00]
MDQ
[07]
GND
[435]
MDQ
[21]
MDQ
[17]
MDQS
_B[11]
GND
[436]
MA
[03]
G3VDD
[19] AY
SD3_ SD4_ SD4_ SD4_ SD4_ D3_ D3_ D3_ D3_ D3_ D3_ D3_ D3_
BA S3GND
[26]
RX
_B[6]
S3GND
[27]
RX
_B[0]
S4GND
[21]
RX
_B[2]
S4GND
[22]
RX
_B[4]
S4GND
[23]
RX
_B[6]
S4GND
[24]
GND
[439]
MDQ
[01]
MDQS
_B[00]
MDQ
[06]
GND
[440]
MDQ
[20]
MDQ
[16]
MDM
[2]
GND
[441]
MA
[04]
MA
[05]
BA
SD3_ SD4_ SD4_ SD4_ SD4_ GND_ D3_
BB S3GND
[31]
RX
[6]
S3GND
[32]
RX
[0]
S4GND
[25]
RX
[2]
S4GND
[26]
RX
[4]
S4GND
[27]
RX
[6]
S4GND
[28]
S4GND
[29]
GND
[455]
GND
[456]
GND
[457]
GND
[458]
GND
[459]
GND
[460]
GND
[461]
DET
[3]
G3VDD
[20]
MA
[06]
BB
SD3_ SD3_ SD4_ SD4_ SD4_ SD4_ D3_ D3_ D3_ D3_ D3_ D3_ D3_
BC RX
_B[5]
S3GND
[37]
RX
_B[7]
S4GND
[30]
RX
_B[1]
S4GND
[31]
RX
_B[3]
S4GND
[32]
RX
_B[5]
S4GND
[33]
RX
_B[7]
S4GND
[34]
MCKE
[1]
MCKE
[2]
G3VDD
[21]
MBA
[2]
MA
[14]
MA
[12]
G3VDD
[22]
MA
[08]
MA
[07]
G3VDD
[23] BC
SD3_ SD3_ SD4_ SD4_ SD4_ SD4_ D3_ D3_ D3_ D3_ D3_ D3_
BD RX
[5]
S3GND
[41]
RX
[7]
S4GND
[35]
RX
[1]
S4GND
[36]
RX
[3]
S4GND
[37]
RX
[5]
S4GND
[38]
RX
[7]
S4GND
[39]
G3VDD
[24]
MCKE
[3]
MCKE
[0]
MA
[15]
G3VDD
[25]
MAPAR_
ERR_B
MA
[09]
MA
[11]
G3VDD
[26] BD
23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44
Figure 6. Detail D

Pin assignments
2.2 Pinout list

This table provides the pinout listing for the T4240 by bus. Primary functions are bolded
in the table.
Table 1. Pinout list by bus
Signal Signal description Package Pin Power supply Notes
pin type
number
DDR SDRAM Memory Interface 1
D1_MA00 Address R2 O G1V DD ---
D1_MA01 Address G1 O G1V DD ---
D1_MA02 Address G2 O G1V DD ---
D1_MA03 Address F2 O G1V DD ---
D1_MA04 Address E1 O G1V DD ---
D1_MA05 Address E2 O G1V DD ---
D1_MA06 Address D1 O G1V DD ---
D1_MA07 Address C2 O G1V DD ---
D1_MA08 Address C1 O G1V DD ---
D1_MA09 Address B3 O G1V DD ---
D1_MA10 Address T1 O G1V DD ---
D1_MA12 Address A3 O G1V DD ---
D1_MA13 Address AD1 O G1V DD ---
D1_MAPAR_ERR_B Address Parity Error A4 I G1V DD 1, 18
D1_MAPAR_OUT Address Parity Out R1 O G1V DD ---
D1_MBA0 Bank Select U1 O G1V DD ---
D1_MBA1 Bank Select U2 O G1V DD ---
D1_MBA2 Bank Select A5 O G1V DD ---
D1_MCAS_B Column Address Strobe AA2 O G1V DD ---
D1_MCK0 Clock K2 O G1V DD ---
D1_MCK0_B Clock Complements L2 O G1V DD ---
D1_MCK1 Clock L1 O G1V DD ---
D1_MCK1_B Clock Complements M1 O G1V DD ---
D1_MCK2 Clock N2 O G1V DD ---
D1_MCK2_B Clock Complements N1 O G1V DD ---
D1_MCK3 Clock J2 O G1V DD ---
D1_MCK3_B Clock Complements J1 O G1V DD ---
D1_MCKE0 Clock Enable A7 O G1V DD 2
Table continues on the next page...

Pin assignments
Table 1. Pinout list by bus (continued)

pin type
number
D1_MCKE1 Clock Enable B8 O G1V DD 2
D1_MCKE2 Clock Enable B7 O G1V DD 2
D1_MCKE3 Clock Enable A8 O G1V DD 2
D1_MCS0_B Chip Select Y1 O G1V DD ---
D1_MCS1_B Chip Select AC2 O G1V DD ---
D1_MCS2_B Chip Select W1 O G1V DD ---
D1_MDIC0 Driver Impedence Calibration P2 IO G1V DD 3
D1_MDIC1 Driver Impedence Calibration H1 IO G1V DD 3
D1_MDM0/D1_MDQS09 Data Mask D7 O G1V DD 1
D1_MDM1/D1_MDQS10 Data Mask H7 O G1V DD 1
D1_MDM2/D1_MDQS11 Data Mask M8 O G1V DD 1
D1_MDM3/D1_MDQS12 Data Mask M5 O G1V DD 1
D1_MDM4/D1_MDQS13 Data Mask V7 O G1V DD 1
D1_MDM6/D1_MDQS15 Data Mask AC4 O G1V DD 1
D1_MDM7/D1_MDQS16 Data Mask AB10 O G1V DD 1
D1_MDQ00 Data F7 IO G1V DD ---
D1_MDQ01 Data E7 IO G1V DD ---
D1_MDQ02 Data D4 IO G1V DD ---
D1_MDQ08 Data J8 IO G1V DD ---
D1_MDQ09 Data G7 IO G1V DD ---
D1_MDQ11 Data H4 IO G1V DD ---
D1_MDQ12 Data H8 IO G1V DD ---
D1_MDQ16 Data L8 IO G1V DD ---
D1_MDQ18 Data R8 IO G1V DD ---

Pin assignments

pin type
number
D1_MDQ20 Data K8 IO G1V DD ---
D1_MDQ22 Data P8 IO G1V DD ---
D1_MDQ32 Data U7 IO G1V DD ---
D1_MDQ34 Data AA7 IO G1V DD ---
D1_MDQ36 Data T7 IO G1V DD ---
D1_MDQ37 Data T8 IO G1V DD ---
D1_MDQ38 Data Y7 IO G1V DD ---
D1_MDQ48 Data AB7 IO G1V DD ---
D1_MDQ49 Data AC7 IO G1V DD ---
D1_MDQ50 Data AE6 IO G1V DD ---
D1_MDQ51 Data AD7 IO G1V DD ---

Pin assignments

pin type
number
D1_MDQS00 Data Strobe F5 IO G1V DD ---
D1_MDQS00_B Data Strobe F6 IO G1V DD ---
D1_MDQS01 Data Strobe G5 IO G1V DD ---
D1_MDQS01_B Data Strobe H5 IO G1V DD ---
D1_MDQS02 Data Strobe N7 IO G1V DD ---
D1_MDQS02_B Data Strobe N8 IO G1V DD ---
D1_MDQS03 Data Strobe N4 IO G1V DD ---
D1_MDQS03_B Data Strobe N5 IO G1V DD ---
D1_MDQS04 Data Strobe W8 IO G1V DD ---
D1_MDQS04_B Data Strobe W7 IO G1V DD ---
D1_MDQS06 Data Strobe AE4 IO G1V DD ---
D1_MDQS06_B Data Strobe AD4 IO G1V DD ---
D1_MDQS07 Data Strobe AC11 IO G1V DD ---
D1_MDQS07_B Data Strobe AB11 IO G1V DD ---
D1_MDQS09/D1_MDM0 Data Strobe (x4 support) D7 IO G1V DD ---
D1_MDQS09_B Data Strobe (x4 support) D6 IO G1V DD 28
D1_MDQS10/D1_MDM1 Data Strobe (x4 support) H7 IO G1V DD ---
D1_MDQS10_B Data Strobe (x4 support) H6 IO G1V DD 28
D1_MDQS11/D1_MDM2 Data Strobe (x4 support) M8 IO G1V DD ---
D1_MDQS11_B Data Strobe (x4 support) M7 IO G1V DD 28
D1_MDQS12/D1_MDM3 Data Strobe (x4 support) M5 IO G1V DD ---
D1_MDQS12_B Data Strobe (x4 support) M4 IO G1V DD 28
D1_MDQS13/D1_MDM4 Data Strobe (x4 support) V7 IO G1V DD ---
D1_MDQS13_B Data Strobe (x4 support) V8 IO G1V DD 28
D1_MDQS15/D1_MDM6 Data Strobe (x4 support) AC4 IO G1V DD ---
D1_MDQS15_B Data Strobe (x4 support) AC5 IO G1V DD 28

Pin assignments

pin type
number
D1_MDQS16/D1_MDM7 Data Strobe (x4 support) AB10 IO G1V DD ---
D1_MDQS16_B Data Strobe (x4 support) AC10 IO G1V DD 28
D1_MECC0 Error Correcting Code U5 IO G1V DD ---
D1_MECC1 Error Correcting Code U4 IO G1V DD ---
D1_MECC2 Error Correcting Code AA5 IO G1V DD ---
D1_MECC3 Error Correcting Code AA4 IO G1V DD ---
D1_MECC4 Error Correcting Code T5 IO G1V DD ---
D1_MECC5 Error Correcting Code T4 IO G1V DD ---
D1_MECC6 Error Correcting Code Y5 IO G1V DD ---
D1_MECC7 Error Correcting Code Y4 IO G1V DD ---
D1_MODT0 On Die Termination AA1 O G1V DD 2
D1_MODT1 On Die Termination AE1 O G1V DD 2
D1_MODT2 On Die Termination AB2 O G1V DD 2
D1_MRAS_B Row Address Strobe V2 O G1V DD ---
D1_MWE_B Write Enable W2 O G1V DD ---
D2_MA00 Address AU1 O G2V DD ---
D2_MA01 Address BC5 O G2V DD ---
D2_MA02 Address BD4 O G2V DD ---
D2_MA10 Address AT2 O G2V DD ---
D2_MA13 Address AK2 O G2V DD ---
D2_MAPAR_ERR_B Address Parity Error BD11 I G2V DD 1, 18
D2_MAPAR_OUT Address Parity Out AV1 O G2V DD ---
D2_MBA0 Bank Select AR2 O G2V DD ---

Pin assignments

pin type
number
D2_MBA1 Bank Select AT1 O G2V DD ---
D2_MBA2 Bank Select BD12 O G2V DD ---
D2_MCAS_B Column Address Strobe AM2 O G2V DD ---
D2_MCK0 Clock BA1 O G2V DD ---
D2_MCK0_B Clock Complements AY1 O G2V DD ---
D2_MCK1 Clock BB1 O G2V DD ---
D2_MCK1_B Clock Complements BB2 O G2V DD ---
D2_MCK2 Clock AY2 O G2V DD ---
D2_MCK2_B Clock Complements AW2 O G2V DD ---
D2_MCK3 Clock BC2 O G2V DD ---
D2_MCK3_B Clock Complements BC3 O G2V DD ---
D2_MCKE0 Clock Enable BD15 O G2V DD 2
D2_MCKE3 Clock Enable BC15 O G2V DD 2
D2_MCS0_B Chip Select AP2 O G2V DD ---
D2_MCS1_B Chip Select AH2 O G2V DD ---
D2_MCS2_B Chip Select AN1 O G2V DD ---
D2_MCS3_B Chip Select AJ1 O G2V DD ---
D2_MDIC0 Driver Impedence Calibration AV2 IO G2V DD 3
D2_MDIC1 Driver Impedence Calibration BD3 IO G2V DD 3
D2_MDM0/D2_MDQS09 Data Mask AY14 O G2V DD 1
D2_MDM1/D2_MDQS10 Data Mask AU14 O G2V DD 1
D2_MDM2/D2_MDQS11 Data Mask AU7 O G2V DD 1
D2_MDM3/D2_MDQS12 Data Mask AY7 O G2V DD 1
D2_MDM4/D2_MDQS13 Data Mask AN8 O G2V DD 1
D2_MDM6/D2_MDQS15 Data Mask AH4 O G2V DD 1
D2_MDM7/D2_MDQS16 Data Mask AF10 O G2V DD 1
D2_MDQ00 Data AY15 IO G2V DD ---
D2_MDQ01 Data BA15 IO G2V DD ---

Pin assignments

pin type
number
D2_MDQ08 Data AU15 IO G2V DD ---
D2_MDQ09 Data AV15 IO G2V DD ---
D2_MDQ32 Data AP8 IO G2V DD ---
D2_MDQ34 Data AK8 IO G2V DD ---
D2_MDQ36 Data AR8 IO G2V DD ---
D2_MDQ38 Data AL8 IO G2V DD ---

Pin assignments

pin type
number
D2_MDQ48 Data AH6 IO G2V DD ---
D2_MDQ50 Data AF8 IO G2V DD ---
D2_MDQ55 Data AG7 IO G2V DD ---
D2_MDQS00 Data Strobe BA13 IO G2V DD ---
D2_MDQS00_B Data Strobe AY13 IO G2V DD ---
D2_MDQS01 Data Strobe AV13 IO G2V DD ---
D2_MDQS01_B Data Strobe AU13 IO G2V DD ---
D2_MDQS02_B Data Strobe AU6 IO G2V DD ---
D2_MDQS03 Data Strobe BA6 IO G2V DD ---
D2_MDQS03_B Data Strobe AY6 IO G2V DD ---
D2_MDQS04 Data Strobe AM7 IO G2V DD ---
D2_MDQS04_B Data Strobe AM8 IO G2V DD ---
D2_MDQS06 Data Strobe AG6 IO G2V DD ---
D2_MDQS06_B Data Strobe AG5 IO G2V DD ---
D2_MDQS07_B Data Strobe AE10 IO G2V DD ---
D2_MDQS09/D2_MDM0 Data Strobe (x4 support) AY14 IO G2V DD ---
D2_MDQS09_B Data Strobe (x4 support) BA14 IO G2V DD 28

Pin assignments

pin type
number
D2_MDQS10/D2_MDM1 Data Strobe (x4 support) AU14 IO G2V DD ---
D2_MDQS10_B Data Strobe (x4 support) AV14 IO G2V DD 28
D2_MDQS12/D2_MDM3 Data Strobe (x4 support) AY7 IO G2V DD ---
D2_MDQS12_B Data Strobe (x4 support) BA7 IO G2V DD 28
D2_MDQS13/D2_MDM4 Data Strobe (x4 support) AN8 IO G2V DD ---
D2_MDQS13_B Data Strobe (x4 support) AN7 IO G2V DD 28
D2_MDQS15/D2_MDM6 Data Strobe (x4 support) AH4 IO G2V DD ---
D2_MDQS15_B Data Strobe (x4 support) AG4 IO G2V DD 28
D2_MDQS16/D2_MDM7 Data Strobe (x4 support) AF10 IO G2V DD ---
D2_MDQS16_B Data Strobe (x4 support) AF11 IO G2V DD 28
D2_MECC0 Error Correcting Code AP11 IO G2V DD ---
D2_MECC1 Error Correcting Code AP10 IO G2V DD ---
D2_MECC2 Error Correcting Code AK11 IO G2V DD ---
D2_MECC4 Error Correcting Code AR11 IO G2V DD ---
D2_MECC5 Error Correcting Code AR10 IO G2V DD ---
D2_MECC6 Error Correcting Code AL11 IO G2V DD ---
D2_MODT0 On Die Termination AL2 O G2V DD 2
D2_MODT1 On Die Termination AG2 O G2V DD 2
D2_MODT2 On Die Termination AK1 O G2V DD 2
D2_MODT3 On Die Termination AH1 O G2V DD 2
D2_MRAS_B Row Address Strobe AP1 O G2V DD ---
D2_MWE_B Write Enable AM1 O G2V DD ---
D3_MA00 Address AL44 O G3V DD ---
D3_MA01 Address AW43 O G3V DD ---
D3_MA02 Address AW44 O G3V DD ---
D3_MA03 Address AY43 O G3V DD ---
D3_MA04 Address BA43 O G3V DD ---
D3_MA05 Address BA44 O G3V DD ---
D3_MA06 Address BB44 O G3V DD ---

Pin assignments

pin type
number
D3_MA10 Address AK44 O G3V DD ---
D3_MA13 Address AB44 O G3V DD ---
D3_MAPAR_ERR_B Address Parity Error BD40 I G3V DD 1, 18
D3_MAPAR_OUT Address Parity Out AL43 O G3V DD ---
D3_MBA0 Bank Select AJ43 O G3V DD ---
D3_MBA1 Bank Select AJ44 O G3V DD ---
D3_MBA2 Bank Select BC38 O G3V DD ---
D3_MCAS_B Column Address Strobe AE44 O G3V DD ---
D3_MCK0 Clock AT43 O G3V DD ---
D3_MCK0_B Clock Complements AR43 O G3V DD ---
D3_MCK1 Clock AR44 O G3V DD ---
D3_MCK1_B Clock Complements AP44 O G3V DD ---
D3_MCK2 Clock AN44 O G3V DD ---
D3_MCK2_B Clock Complements AN43 O G3V DD ---
D3_MCK3 Clock AU44 O G3V DD ---
D3_MCK3_B Clock Complements AU43 O G3V DD ---
D3_MCS0_B Chip Select AF44 O G3V DD ---
D3_MCS2_B Chip Select AG43 O G3V DD ---
D3_MDIC0 Driver Impedence Calibration AM43 IO G3V DD 3
D3_MDIC1 Driver Impedence Calibration AV44 IO G3V DD 3
D3_MDM0/D3_MDQS09 Data Mask AU36 O G3V DD 1, 28
D3_MDM1/D3_MDQS10 Data Mask AP36 O G3V DD 1, 28
D3_MDM2/D3_MDQS11 Data Mask BA41 O G3V DD 1, 28
D3_MDM3/D3_MDQS12 Data Mask AP40 O G3V DD 1, 28
D3_MDM4/D3_MDQS13 Data Mask AG40 O G3V DD 1, 28

Pin assignments

pin type
number
D3_MDM5/D3_MDQS14 Data Mask AG38 O G3V DD 1, 28
D3_MDM6/D3_MDQS15 Data Mask AF35 O G3V DD 1, 28
D3_MDM7/D3_MDQS16 Data Mask AB39 O G3V DD 1, 28
D3_MDM8/D3_MDQS17 Data Mask AM37 O G3V DD 1, 28
D3_MDQ02 Data AW37 IO G3V DD ---
D3_MDQ14 Data AT38 IO G3V DD ---
D3_MDQ22 Data AW41 IO G3V DD ---
D3_MDQ30 Data AM40 IO G3V DD ---
D3_MDQ31 Data AM41 IO G3V DD ---

Pin assignments

pin type
number
D3_MDQ36 Data AJ40 IO G3V DD ---
D3_MDQS00 Data Strobe AY36 IO G3V DD ---
D3_MDQS00_B Data Strobe BA36 IO G3V DD ---
D3_MDQS01 Data Strobe AT37 IO G3V DD ---
D3_MDQS01_B Data Strobe AR37 IO G3V DD ---
D3_MDQS02_B Data Strobe AW39 IO G3V DD ---
D3_MDQS03 Data Strobe AN41 IO G3V DD ---
D3_MDQS03_B Data Strobe AN40 IO G3V DD ---

Pin assignments

pin type
number
D3_MDQS04 Data Strobe AF41 IO G3V DD ---
D3_MDQS04_B Data Strobe AF40 IO G3V DD ---
D3_MDQS05 Data Strobe AF37 IO G3V DD ---
D3_MDQS05_B Data Strobe AF38 IO G3V DD ---
D3_MDQS06_B Data Strobe AE35 IO G3V DD ---
D3_MDQS07 Data Strobe AA38 IO G3V DD ---
D3_MDQS07_B Data Strobe AB38 IO G3V DD ---
D3_MDQS08 Data Strobe AL38 IO G3V DD ---
D3_MDQS08_B Data Strobe AL37 IO G3V DD ---
D3_MDQS10/D3_MDM1 Data Strobe (x4 support) AP36 IO G3V DD ---
D3_MDQS10_B Data Strobe (x4 support) AR36 IO G3V DD 28
D3_MDQS11/D3_MDM2 Data Strobe (x4 support) BA41 IO G3V DD ---
D3_MDQS11_B Data Strobe (x4 support) AY41 IO G3V DD 28
D3_MDQS12/D3_MDM3 Data Strobe (x4 support) AP40 IO G3V DD ---
D3_MDQS12_B Data Strobe (x4 support) AP41 IO G3V DD 28
D3_MDQS13/D3_MDM4 Data Strobe (x4 support) AG40 IO G3V DD ---
D3_MDQS14/D3_MDM5 Data Strobe (x4 support) AG38 IO G3V DD ---
D3_MDQS15/D3_MDM6 Data Strobe (x4 support) AF35 IO G3V DD ---
D3_MDQS15_B Data Strobe (x4 support) AF34 IO G3V DD 28
D3_MDQS16/D3_MDM7 Data Strobe (x4 support) AB39 IO G3V DD ---
D3_MDQS16_B Data Strobe (x4 support) AA39 IO G3V DD 28
D3_MDQS17/D3_MDM8 Data Strobe (x4 support) AM37 IO G3V DD ---
D3_MDQS17_B Data Strobe (x4 support) AM38 IO G3V DD 28
D3_MECC0 Error Correcting Code AN37 IO G3V DD ---
D3_MECC1 Error Correcting Code AN38 IO G3V DD ---
D3_MECC4 Error Correcting Code AM34 IO G3V DD ---
D3_MECC5 Error Correcting Code AM35 IO G3V DD ---

Pin assignments

pin type
number
D3_MODT2 On Die Termination AD43 O G3V DD 2
D3_MRAS_B Row Address Strobe AH43 O G3V DD ---
D3_MWE_B Write Enable AG44 O G3V DD ---
Integrated Flash Controller
IFC_A26/GPIO2_18 IFC Address B40 O OV DD 1
IFC_A27/GPIO2_19 IFC Address A40 O OV DD 1
IFC_A28/GPIO2_20 IFC Address D39 O OV DD 1
IFC_A29/GPIO2_21 IFC Address C39 O OV DD 1
IFC_A30/GPIO2_22 IFC Address A39 O OV DD 1
IFC_A31/GPIO2_23 IFC Address C38 O OV DD 1
IFC_AD00/cfg_gpinput0 IFC Address/Data W39 IO OV DD 4, 21
IFC_AD01/cfg_gpinput1 IFC Address/Data W40 IO OV DD 4, 21
IFC_AD02/cfg_gpinput2 IFC Address/Data V39 IO OV DD 4, 21
IFC_AD03/cfg_gpinput3 IFC Address/Data V40 IO OV DD 4, 21
IFC_AD04/cfg_gpinput4 IFC Address/Data U40 IO OV DD 4, 21
IFC_AD05/cfg_gpinput5 IFC Address/Data U41 IO OV DD 4, 21
IFC_AD06/cfg_gpinput6 IFC Address/Data T39 IO OV DD 4, 21
IFC_AD07/cfg_gpinput7 IFC Address/Data T40 IO OV DD 4, 21
IFC_AD08/cfg_rcw_src0 IFC Address/Data R39 IO OV DD 4, 21
IFC_AD09/cfg_rcw_src1 IFC Address/Data R40 IO OV DD 4, 21
IFC_AD10/cfg_rcw_src2 IFC Address/Data P40 IO OV DD 4, 21
IFC_AD11/cfg_rcw_src3 IFC Address/Data P41 IO OV DD 4, 21
IFC_AD12/cfg_rcw_src4 IFC Address/Data N39 IO OV DD 4, 21
IFC_AD13/cfg_rcw_src5 IFC Address/Data N40 IO OV DD 4, 21
IFC_AD14/cfg_rcw_src6 IFC Address/Data M39 IO OV DD 4, 21
IFC_AD15/cfg_rcw_src7 IFC Address/Data M40 IO OV DD 4, 21
IFC_AD16 IFC Address/Data L40 IO OV DD 29
IFC_AD17 IFC Address/Data L41 IO OV DD 5, 20
IFC_AD18 IFC Address/Data K39 IO OV DD 5, 20
IFC_AD19 IFC Address/Data K40 IO OV DD 5, 20
IFC_AD20 IFC Address/Data J39 IO OV DD 5, 20
IFC_AD21/cfg_dram_type IFC Address/Data J40 IO OV DD 4, 21
IFC_AD22 IFC Address/Data H40 IO OV DD 20
IFC_AD23 IFC Address/Data H41 IO OV DD 20
IFC_AD24 IFC Address/Data G40 IO OV DD 20
IFC_AD25/GPIO2_25/ IFC Address/Data G41 IO OV DD 20
IFC_WP1_B

Pin assignments

pin type
number
IFC_AD26/GPIO2_26/ IFC Address/Data G39 IO OV DD 20
IFC_WP2_B
IFC_AD27/GPIO2_27/ IFC Address/Data F40 IO OV DD 20
IFC_WP3_B
IFC_AD28/GPIO2_28 IFC Address/Data E41 IO OV DD 20
IFC_AD29/GPIO2_29/ IFC Address/Data E40 IO OV DD 20
IFC_RB2_B
IFC_AD30/GPIO2_30/ IFC Address/Data E39 IO OV DD 20
IFC_RB3_B
IFC_AD31/GPIO2_31/ IFC Address/Data D41 IO OV DD 20
IFC_RB4_B
IFC_AVD IFC Address Valid H44 O OV DD 1, 5
IFC_BCTL IFC Buffer Control G44 O OV DD 1
IFC_CLE/cfg_rcw_src8 IFC Command Latch Enable E43 O OV DD 1, 4, 25
IFC_CLK0 IFC Clock B38 O OV DD 1
IFC_CLK1 IFC Clock H42 O OV DD 1
IFC_CLK2 IFC Clock A38 O OV DD 1
IFC_CS0_B IFC Chip Select C43 O OV DD 1, 6
IFC_CS1_B/GPIO2_10 IFC Chip Select C44 O OV DD 1, 6
IFC_CS2_B/GPIO2_11 IFC Chip Select B43 O OV DD 1, 6
IFC_CS3_B/GPIO2_12 IFC Chip Select A42 O OV DD 1, 6
IFC_CS5_B/GPIO1_10 IFC Chip Select B41 O OV DD 1, 6
IFC_CS6_B/GPIO1_11 IFC Chip Select A41 O OV DD 1, 6
IFC_NDDDR_CLK IFC NAND DDR Clock H43 O OV DD 1
IFC_NDDQS IFC DQS Strobe E36 IO OV DD 20
IFC_OE_B IFC Output Enable E42 O OV DD 1, 5
IFC_PAR0/GPIO2_13 IFC Address and Data Parity E38 IO OV DD 20
IFC_PAR1/GPIO2_14 IFC Address and Data Parity D38 IO OV DD 20
IFC_PAR2/GPIO2_16 IFC Address and Data Parity F38 IO OV DD 20
IFC_PAR3/GPIO2_17 IFC Address and Data Parity F37 IO OV DD 20
IFC_PERR_B/GPIO2_15 IFC Parity Error E37 I OV DD 1, 18
IFC_RB0_B IFC Ready / Busy CS0 F43 I OV DD 8
IFC_RB1_B IFC Ready / Busy CS1 F42 I OV DD 8
IFC_RB2_B/IFC_AD29/ IFC Ready / Busy CS 2 E40 I OV DD 1
GPIO2_29
IFC_RB3_B/IFC_AD30/ IFC Ready / Busy CS 3 E39 I OV DD 1
GPIO2_30

Pin assignments

pin type
number
IFC_RB4_B/IFC_AD31/ IFC Ready / Busy CS 4 D41 I OV DD 1
GPIO2_31
IFC_TE/cfg_ifc_te IFC External Transceiver G42 O OV DD 1, 4
Enable
IFC_WE0_B IFC Write Enable E44 O OV DD 1, 5
IFC_WE2_B IFC Write Enable D42 O OV DD 1
IFC_WE3_B IFC Write Enable D44 O OV DD 1
IFC_WP0_B IFC Write Protect F44 O OV DD 1, 5
IFC_WP1_B/IFC_AD25/ IFC Write Protect G41 O OV DD 1
GPIO2_25
IFC_WP2_B/IFC_AD26/ IFC Write Protect G39 O OV DD 1
GPIO2_26
IFC_WP3_B/IFC_AD27/ IFC Write Protect F40 O OV DD 1
GPIO2_27
DUART
UART1_CTS_B/GPIO1_21/ Clear To Send N11 I DV DD 1
UART3_SIN
UART1_RTS_B/GPIO1_19/ Ready to Send M10 O DV DD 1
UART3_SOUT
UART1_SIN/GPIO1_17 Receive Data M11 I DV DD 1
UART1_SOUT/GPIO1_15 Transmit Data L10 O DV DD 1
UART2_CTS_B/GPIO1_22/ Clear To Send K11 I DV DD 1
UART4_SIN
UART2_RTS_B/GPIO1_20/ Ready to Send K10 O DV DD 1
UART4_SOUT
UART2_SIN/GPIO1_18 Receive Data J11 I DV DD 1
UART2_SOUT/GPIO1_16 Transmit Data J10 O DV DD 1
UART3_SIN/UART1_CTS_B/ Receive Data N11 I DV DD 1
GPIO1_21
UART3_SOUT/ Transmit Data M10 O DV DD 1
UART1_RTS_B/GPIO1_19
UART4_SIN/UART2_CTS_B/ Receive Data K11 I DV DD 1
GPIO1_22
UART4_SOUT/ Transmit Data K10 O DV DD 1
UART2_RTS_B/GPIO1_20
I2C
IIC1_SCL Serial Clock (supports PBL) R10 IO DV DD 7, 8
IIC1_SDA Serial Data (supports PBL) R11 IO DV DD 7, 8
IIC2_SCL Serial Clock N10 IO DV DD 7, 8
IIC2_SDA Serial Data P10 IO DV DD 7, 8
IIC3_SCL/GPIO4_00 Serial Clock N13 IO DV DD 7, 8
IIC3_SDA/GPIO4_01 Serial Data P13 IO DV DD 7, 8

Pin assignments

pin type
number
IIC4_SCL/GPIO4_02/EVT5_B Serial Clock N12 IO DV DD 7, 8
IIC4_SDA/GPIO4_03/EVT6_B Serial Data P12 IO DV DD 7, 8
eSPI Interface
SPI_CLK SPI Clock B37 O OV DD 1
SPI_CS0_B/GPIO2_00/ SPI Chip Select C35 O OV DD 1, 22
SDHC_DAT4
SPI_CS1_B/GPIO2_01/ SPI Chip Select A36 O OV DD 1, 22
SDHC_DAT5
SPI_CS2_B/GPIO2_02/ SPI Chip Select C36 O OV DD 1, 22
SDHC_DAT6
SPI_CS3_B/GPIO2_03/ SPI Chip Select D36 O OV DD 1, 22
SDHC_DAT7
SPI_MISO Master In Slave Out C37 I OV DD ---
SPI_MOSI Master Out Slave In A37 IO OV DD 20
eSDHC
SDHC_CD_B Card Detection A34 I OV DD 26
SDHC_CLK/GPIO2_09 Host to Card Clock A33 O OV DD 1
SDHC_CMD/GPIO2_04 Command/Response D33 IO OV DD 22
SDHC_DAT0/GPIO2_05 Data B34 IO OV DD 22
SDHC_DAT1/GPIO2_06 Data C34 IO OV DD 22
SDHC_DAT2/GPIO2_07 Data A35 IO OV DD 22
SDHC_DAT3/GPIO2_08 Data B35 IO OV DD 22
SDHC_DAT4/SPI_CS0_B/ Data C35 IO OV DD ---
GPIO2_00
SDHC_DAT5/SPI_CS1_B/ Data A36 IO OV DD ---
GPIO2_01
SDHC_DAT6/SPI_CS2_B/ Data C36 IO OV DD ---
GPIO2_02
SDHC_DAT7/SPI_CS3_B/ Data D36 IO OV DD ---
GPIO2_03
SDHC_WP Card Write Protection C33 I OV DD 26
Programmable Interrupt Controller
IRQ00 External Interrupts V43 I OV DD 1
IRQ01 External Interrupts V44 I OV DD 1
IRQ02 External Interrupts U43 I OV DD 1
IRQ03/GPIO1_23 External Interrupts W42 I OV DD 1
IRQ04/GPIO1_24 External Interrupts U44 I OV DD 1
IRQ05/GPIO1_25 External Interrupts R42 I OV DD 1
IRQ07/GPIO1_27 External Interrupts T42 I OV DD 1

Pin assignments

pin type
number
IRQ08/GPIO1_28 External Interrupts T44 I OV DD 1
IRQ09/GPIO1_29 External Interrupts V42 I OV DD 1
IRQ11/GPIO1_31 External Interrupts U42 I OV DD 1
IRQ_OUT_B/EVT9_B Interrupt Output T41 O OV DD 1, 6, 7
LP Trust
LP_TMP_DETECT_B Low Power Tamper Detect T27 I V DD _LP ---
Trust
TMP_DETECT_B Tamper Detect E35 I OV DD 1
System Control
HRESET_B Hard Reset D35 IO OV DD 6, 7
PORESET_B Power On Reset F35 I OV DD ---
RESET_REQ_B Reset Request (POR or Hard) G33 O OV DD 1, 5
Power Management
ASLEEP/GPIO1_13/ Asleep G34 O OV DD 1, 4
cfg_xvdd_sel
Clocking
RTC/GPIO1_14 Real Time Clock V33 I OV DD 1
SYSCLK System Clock U34 I OV DD ---
DDR Clocking
DDRCLK DDR Controllers Clock AL14 I OV DD ---
Debug
CKSTP_OUT_B Checkstop Out L44 O OV DD 1, 6, 7
CLK_OUT Clock Out N44 O OV DD 2
EVT0_B Event 0 N42 IO OV DD 9
EVT1_B Event 1 M43 IO OV DD ---
EVT2_B Event 2 M42 IO OV DD ---
EVT3_B Event 3 L43 IO OV DD ---
EVT4_B Event 4 L42 IO OV DD ---
EVT5_B/IIC4_SCL/GPIO4_02 Event 5 N12 IO DV DD ---
EVT6_B/IIC4_SDA/GPIO4_03 Event 6 P12 IO DV DD ---
EVT7_B/DMA2_DACK0_B/ Event 7 P44 IO OV DD ---
GPIO4_08
EVT8_B/DMA2_DDONE0_B/ Event 8 P42 IO OV DD ---
GPIO4_09
EVT9_B/IRQ_OUT_B Event 9 T41 IO OV DD ---
DFT
SCAN_MODE_B Reserved for internal use only E33 I OV DD 10
TEST_SEL_B Reserved for internal use only F34 I OV DD 10

Pin assignments

pin type
number
JTAG
TCK Test Clock K44 I OV DD ---
TDI Test Data In J43 I OV DD 9
TDO Test Data Out K42 O OV DD 2
TMS Test Mode Select K41 I OV DD 9
TRST_B Test Reset J42 I OV DD 9
SerDes 1
SD1_IMP_CAL_RX SerDes Receive Impedence M16 I S1V DD 11
Calibration
SD1_IMP_CAL_TX SerDes Transmit Impedance M22 I X1V DD 16
Calibration
SD1_PLL1_TPA Reserved for internal use only M18 O AVDD_SD1_PLL1 12
SD1_PLL1_TPD Reserved for internal use only L16 O X1V DD 12
SD1_REF_CLK1 SerDes PLL 1 Reference Clock P18 I S1V DD ---
SD1_REF_CLK1_B SerDes PLL 1 Reference Clock P19 I S1V DD ---
Complement
SD1_REF_CLK2_B SerDes PLL 2 Reference Clock N21 I S1V DD ---
Complement
SD1_RX0 SerDes Receive Data C15 I S1V DD ---
(positive)
SD1_RX0_B SerDes Receive Data D15 I S1V DD ---
(negative)
SD1_RX1 SerDes Receive Data A16 I S1V DD ---
(positive)
SD1_RX1_B SerDes Receive Data B16 I S1V DD ---
(negative)
(positive)
(negative)
(positive)
(negative)
(positive)
(negative)

Pin assignments

pin type
number
(positive)
(negative)
(positive)
(negative)
(positive)
(negative)
SD1_TX0 SerDes Transmit Data H15 O X1V DD ---
(positive)
SD1_TX0_B SerDes Transmit Data J15 O X1V DD ---
(negative)
SD1_TX1 SerDes Transmit Data F16 O X1V DD ---
(positive)
SD1_TX1_B SerDes Transmit Data G16 O X1V DD ---
(negative)
(positive)
(negative)
(positive)
(negative)
(positive)
(negative)
(positive)
(negative)
(positive)
(negative)
(positive)
(negative)

Pin assignments

pin type
number
SerDes 2
SD2_IMP_CAL_RX SerDes Receive Impedence M23 I S2V DD 11
Calibration
SD2_IMP_CAL_TX SerDes Transmit Impedance M29 I X2V DD 16
Calibration
SD2_REF_CLK1_B SerDes PLL 1 Reference Clock N24 I S2V DD ---
Complement
SD2_REF_CLK2_B SerDes PLL 2 Reference Clock P26 I S2V DD ---
Complement
(positive)
(negative)
(positive)
(negative)
(positive)
(negative)
(positive)
(negative)
(positive)
(negative)
(positive)
(negative)
(positive)
(negative)

Pin assignments

pin type
number
(positive)
(negative)
(positive)
(negative)
(positive)
(negative)
(positive)
(negative)
(positive)
(negative)
(positive)
(negative)
(positive)
(negative)
(positive)
(negative)
(positive)
(negative)
SerDes 3
SD3_IMP_CAL_RX SerDes Receive Impedence AN19 I S3V DD 11
Calibration
SD3_IMP_CAL_TX SerDes Transmit Impedance AN25 I X3V DD 16
Calibration
SD3_PLL1_TPA Reserved for internal use only AN21 O AVDD_SD3_PLL1 12
SD3_PLL1_TPD Reserved for internal use only AP19 O X3V DD 12

Pin assignments

pin type
number
SD3_REF_CLK1 SerDes PLL 1 Reference Clock AL21 I S3V DD ---
SD3_REF_CLK1_B SerDes PLL 1 Reference Clock AL22 I S3V DD ---
Complement
SD3_REF_CLK2_B SerDes PLL 2 Reference Clock AM24 I S3V DD ---
Complement
SD3_RX0 SerDes Receive Data BB18 I S3V DD ---
(positive)
SD3_RX0_B SerDes Receive Data BA18 I S3V DD ---
(negative)
SD3_RX1 SerDes Receive Data BD19 I S3V DD ---
(positive)
SD3_RX1_B SerDes Receive Data BC19 I S3V DD ---
(negative)
(positive)
(negative)
(positive)
(negative)
(positive)
(negative)
(positive)
(negative)
(positive)
(negative)
(positive)
(negative)
SD3_TX0 SerDes Transmit Data AU18 O X3V DD ---
(positive)
SD3_TX0_B SerDes Transmit Data AT18 O X3V DD ---
(negative)

Pin assignments

pin type
number
SD3_TX1 SerDes Transmit Data AW19 O X3V DD ---
(positive)
SD3_TX1_B SerDes Transmit Data AV19 O X3V DD ---
(negative)
(positive)
(negative)
(positive)
(negative)
(positive)
(negative)
(positive)
(negative)
(positive)
(negative)
(positive)
(negative)
SerDes 4
SD4_IMP_CAL_RX SerDes Receive Impedence AN26 I S4V DD 11
Calibration
SD4_IMP_CAL_TX SerDes Transmit Impedance AN32 I X4V DD 16
Calibration
SD4_REF_CLK1_B SerDes PLL 1 Reference Clock AM27 I S4V DD ---
Complement
SD4_REF_CLK2_B SerDes PLL 2 Reference Clock AL29 I S4V DD ---
Complement

Pin assignments

pin type
number
(positive)
(negative)
(positive)
(negative)
(positive)
(negative)
(positive)
(negative)
(positive)
(negative)
(positive)
(negative)
(positive)
(negative)
(positive)
(negative)
(positive)
(negative)
(positive)
(negative)
(positive)
(negative)

Pin assignments

pin type
number
(positive)
(negative)
(positive)
(negative)
(positive)
(negative)
(positive)
(negative)
(positive)
(negative)
USB PHY 1 & 2
USB1_DRVVBUS USB PHY Digital signal - Drive E32 O USB_HV DD ---
VBUS
USB1_PWRFAULT USB PHY Digital signal - F32 I USB_HV DD ---
Power Fault
USB1_UDM USB PHY Data Minus J31 IO USB_HV DD ---
USB1_UDP USB PHY Data Plus K31 IO USB_HV DD ---
USB1_UID USB PHY ID Detect L32 I USB_OV DD ---
USB1_VBUSCLMP USB PHY VBUS G32 I USB_HV DD ---
USB2_DRVVBUS USB PHY Digital signal - Drive A32 O USB_HV DD ---
VBUS
USB2_PWRFAULT USB PHY Digital signal - B32 I USB_HV DD ---
Power Fault
USB2_UDM USB PHY Data Minus M31 IO USB_HV DD ---
USB2_UDP USB PHY Data Plus N31 IO USB_HV DD ---
USB2_UID USB PHY ID Detect H32 I USB_OV DD ---
USB2_VBUSCLMP USB PHY VBUS C32 I USB_HV DD ---
USB_IBIAS_REXT USB PHY Impedance D31 IO - 23
Calibration
USB CLK
USBCLK USB PHY Clock In E34 I OV DD ---
IEEE1588

Pin assignments

pin type
number
TSEC_1588_ALARM_OUT1/ Alarm Out 1 K13 O LV DD 1
GPIO3_03
TSEC_1588_ALARM_OUT2/ Alarm Out 2 J12 O LV DD 1
GPIO3_04
TSEC_1588_CLK_IN/ Clock In A14 I LV DD 1
GPIO3_00
TSEC_1588_CLK_OUT/ Clock Out F14 O LV DD 1
GPIO3_05
TSEC_1588_PULSE_OUT1/ Pulse Out 1 M14 O LV DD 1
GPIO3_06
TSEC_1588_PULSE_OUT2/ Pulse Out 2 L13 O LV DD 1
GPIO3_07
TSEC_1588_TRIG_IN1/ Trigger In 1 N15 I LV DD 1
GPIO3_01
TSEC_1588_TRIG_IN2/ Trigger In 2 N14 I LV DD 1
GPIO3_02
Ethernet Management Interface 1
EMI1_MDC Management Data Clock G13 O LV DD ---
EMI1_MDIO Management Data In/Out H13 IO LV DD 6
Ethernet Management Interface 2
EMI2_MDC Management Data Clock (1.2V D13 O OV DD 7, 13
open drain)
EMI2_MDIO Management Data In/Out (1.2V E13 IO OV DD 7, 13
open drain)
Ethernet Controller 1
EC1_GTX_CLK/GPIO3_13 Transmit Clock Out F12 O LV DD 1
EC1_GTX_CLK125 Reference Clock D12 I LV DD ---
EC1_RXD0/GPIO3_19 Receive Data C12 I LV DD 1
EC1_RXD1/GPIO3_18 Receive Data E12 I LV DD 1
EC1_RXD2/GPIO3_17 Receive Data A12 I LV DD 1
EC1_RXD3/GPIO3_16 Receive Data G12 I LV DD 1
EC1_RX_CLK/GPIO3_15 Receive Clock B12 I LV DD 1
EC1_RX_DV/GPIO3_14 Receive Data Valid A13 I LV DD 1
EC1_TXD0/GPIO3_11 Transmit Data H12 O LV DD 1
EC1_TXD1/GPIO3_10 Transmit Data K12 O LV DD 1
EC1_TXD2/GPIO3_09 Transmit Data L12 O LV DD 1
EC1_TXD3/GPIO3_08 Transmit Data M12 O LV DD 1
EC1_TX_EN/GPIO3_12 Transmit Enable C13 O LV DD 1, 14
Ethernet Controller 2
EC2_GTX_CLK/GPIO3_25 Transmit Clock Out H10 O LV DD 1
EC2_GTX_CLK125 Reference Clock E10 I LV DD ---

Pin assignments

pin type
number
EC2_RXD2/GPIO3_29 Receive Data C11 I LV DD 1
EC2_RXD3/GPIO3_28 Receive Data D10 I LV DD 1
EC2_RX_CLK/GPIO3_27 Receive Clock B10 I LV DD 1
EC2_RX_DV/GPIO3_26 Receive Data Valid C10 I LV DD 1
EC2_TXD0/GPIO3_23 Transmit Data D11 O LV DD 1
EC2_TXD1/GPIO3_22 Transmit Data F10 O LV DD 1
EC2_TXD2/GPIO3_21 Transmit Data F11 O LV DD 1
EC2_TXD3/GPIO3_20 Transmit Data G11 O LV DD 1
EC2_TX_EN/GPIO3_24 Transmit Enable G10 O LV DD 1, 14
DMA
DMA1_DACK0_B/GPIO4_05 DMA1 channel 0 acknowledge R43 O OV DD 1
DMA1_DDONE0_B/GPIO4_06 DMA1 channel 0 done R44 O OV DD 1
DMA1_DREQ0_B/GPIO4_04 DMA1 channel 0 request P43 I OV DD 1
DMA2_DACK0_B/GPIO4_08/ DMA2 channel 0 acknowledge P44 O OV DD 1
EVT7_B
DMA2_DDONE0_B/ DMA2 channel 0 done P42 O OV DD 1
GPIO4_09/EVT8_B
DMA2_DREQ0_B/GPIO4_07 DMA2 channel 0 request N41 I OV DD 1
Analog signals
D1_MVREF SSTL1.35/1.5 Reference V13 I G1V DD/2 ---
Voltage
D1_TPA Reserved for internal use only AL13 - - 12
D2_MVREF SSTL1.35/1.5 Reference AH13 I G2V DD/2 ---
Voltage
D2_TPA Reserved for internal use only AM13 - - 12
D3_MVREF SSTL1.35/1.5 Reference AD32 I G3V DD/2 ---
Voltage
D3_TPA Reserved for internal use only AF32 - - 12
FA_ANALOG_G_V Reserved for internal use only R32 - - 15
FA_ANALOG_PIN Reserved for internal use only T32 - - 15
TD1_ANODE Thermal diode anode pin AA34 - Internal Diode 19, 24
TD1_CATHODE Thermal diode cathode pin Y34 - Internal Diode 19, 24
TD2_ANODE Thermal diode anode pin AL16 - Internal Diode 19, 24
TD2_CATHODE Thermal diode cathode pin AL17 - Internal Diode 19, 24
TH_TPA Thermal Test Point Analog W32 - - 12
Power-On-Reset Configuration
cfg_dram_type/IFC_AD21 Power-On-Reset Configuration J40 I OV DD 1, 4
Signal

Pin assignments

pin type
number
cfg_gpinput0/IFC_AD00 Power-On-Reset Configuration W39 I OV DD 1, 4
Signal
cfg_gpinput1/IFC_AD01 Power-On-Reset Configuration W40 I OV DD 1, 4
Signal
cfg_gpinput2/IFC_AD02 Power-On-Reset Configuration V39 I OV DD 1, 4
Signal
cfg_gpinput3/IFC_AD03 Power-On-Reset Configuration V40 I OV DD 1, 4
Signal
cfg_gpinput4/IFC_AD04 Power-On-Reset Configuration U40 I OV DD 1, 4
Signal
cfg_gpinput5/IFC_AD05 Power-On-Reset Configuration U41 I OV DD 1, 4
Signal
cfg_gpinput6/IFC_AD06 Power-On-Reset Configuration T39 I OV DD 1, 4
Signal
cfg_gpinput7/IFC_AD07 Power-On-Reset Configuration T40 I OV DD 1, 4
Signal
cfg_ifc_te/IFC_TE Power-On-Reset Configuration G42 I OV DD 1, 4
Signal
cfg_rcw_src0/IFC_AD08 Power-On-Reset Configuration R39 I OV DD 1, 4
Signal
cfg_rcw_src1/IFC_AD09 Power-On-Reset Configuration R40 I OV DD 1, 4
Signal
cfg_rcw_src2/IFC_AD10 Power-On-Reset Configuration P40 I OV DD 1, 4
Signal
cfg_rcw_src3/IFC_AD11 Power-On-Reset Configuration P41 I OV DD 1, 4
Signal
cfg_rcw_src4/IFC_AD12 Power-On-Reset Configuration N39 I OV DD 1, 4
Signal
cfg_rcw_src5/IFC_AD13 Power-On-Reset Configuration N40 I OV DD 1, 4
Signal
cfg_rcw_src6/IFC_AD14 Power-On-Reset Configuration M39 I OV DD 1, 4
Signal
cfg_rcw_src7/IFC_AD15 Power-On-Reset Configuration M40 I OV DD 1, 4
Signal
cfg_rcw_src8/IFC_CLE Power-On-Reset Configuration E43 I OV DD 1, 4
Signal
cfg_xvdd_sel/ASLEEP/ Power-On-Reset Configuration G34 I OV DD 1, 4
GPIO1_13 Signal
General Purpose Input/Output
GPIO1_09/IFC_CS4_B General Purpose Input/Output C41 IO OV DD ---
GPIO1_10/IFC_CS5_B General Purpose Input/Output B41 IO OV DD ---
GPIO1_11/IFC_CS6_B General Purpose Input/Output A41 IO OV DD ---

Pin assignments

pin type
number
GPIO1_13/ASLEEP/ General Purpose Input/Output G34 O OV DD 1, 4
cfg_xvdd_sel
GPIO1_14/RTC General Purpose Input/Output V33 IO OV DD ---
GPIO1_15/UART1_SOUT General Purpose Input/Output L10 IO DV DD ---
GPIO1_16/UART2_SOUT General Purpose Input/Output J10 IO DV DD ---
GPIO1_17/UART1_SIN General Purpose Input/Output M11 IO DV DD ---
GPIO1_18/UART2_SIN General Purpose Input/Output J11 IO DV DD ---
GPIO1_19/UART1_RTS_B/ General Purpose Input/Output M10 IO DV DD ---
UART3_SOUT
GPIO1_20/UART2_RTS_B/ General Purpose Input/Output K10 IO DV DD ---
UART4_SOUT
GPIO1_21/UART1_CTS_B/ General Purpose Input/Output N11 IO DV DD ---
UART3_SIN
GPIO1_22/UART2_CTS_B/ General Purpose Input/Output K11 IO DV DD ---
UART4_SIN
GPIO1_23/IRQ03 General Purpose Input/Output W42 IO OV DD ---
GPIO1_24/IRQ04 General Purpose Input/Output U44 IO OV DD ---
GPIO1_25/IRQ05 General Purpose Input/Output R42 IO OV DD ---
GPIO1_27/IRQ07 General Purpose Input/Output T42 IO OV DD ---
GPIO1_28/IRQ08 General Purpose Input/Output T44 IO OV DD ---
GPIO1_29/IRQ09 General Purpose Input/Output V42 IO OV DD ---
GPIO1_31/IRQ11 General Purpose Input/Output U42 IO OV DD ---
GPIO2_00/SPI_CS0_B/ General Purpose Input/Output C35 IO OV DD ---
SDHC_DAT4
GPIO2_01/SPI_CS1_B/ General Purpose Input/Output A36 IO OV DD ---
SDHC_DAT5
GPIO2_02/SPI_CS2_B/ General Purpose Input/Output C36 IO OV DD ---
SDHC_DAT6
GPIO2_03/SPI_CS3_B/ General Purpose Input/Output D36 IO OV DD ---
SDHC_DAT7
GPIO2_04/SDHC_CMD General Purpose Input/Output D33 IO OV DD ---
GPIO2_05/SDHC_DAT0 General Purpose Input/Output B34 IO OV DD ---
GPIO2_06/SDHC_DAT1 General Purpose Input/Output C34 IO OV DD ---
GPIO2_07/SDHC_DAT2 General Purpose Input/Output A35 IO OV DD ---
GPIO2_08/SDHC_DAT3 General Purpose Input/Output B35 IO OV DD ---
GPIO2_09/SDHC_CLK General Purpose Input/Output A33 IO OV DD ---
GPIO2_11/IFC_CS2_B General Purpose Input/Output B43 IO OV DD ---

Pin assignments

pin type
number
GPIO2_12/IFC_CS3_B General Purpose Input/Output A42 IO OV DD ---
GPIO2_13/IFC_PAR0 General Purpose Input/Output E38 IO OV DD ---
GPIO2_14/IFC_PAR1 General Purpose Input/Output D38 IO OV DD ---
GPIO2_15/IFC_PERR_B General Purpose Input/Output E37 IO OV DD ---
GPIO2_16/IFC_PAR2 General Purpose Input/Output F38 IO OV DD ---
GPIO2_17/IFC_PAR3 General Purpose Input/Output F37 IO OV DD ---
GPIO2_18/IFC_A26 General Purpose Input/Output B40 IO OV DD ---
GPIO2_19/IFC_A27 General Purpose Input/Output A40 IO OV DD ---
GPIO2_20/IFC_A28 General Purpose Input/Output D39 IO OV DD ---
GPIO2_21/IFC_A29 General Purpose Input/Output C39 IO OV DD ---
GPIO2_22/IFC_A30 General Purpose Input/Output A39 IO OV DD ---
GPIO2_23/IFC_A31 General Purpose Input/Output C38 IO OV DD ---
GPIO2_25/IFC_AD25/ General Purpose Input/Output G41 IO OV DD ---
IFC_WP1_B
GPIO2_26/IFC_AD26/ General Purpose Input/Output G39 IO OV DD ---
IFC_WP2_B
GPIO2_27/IFC_AD27/ General Purpose Input/Output F40 IO OV DD ---
IFC_WP3_B
GPIO2_28/IFC_AD28 General Purpose Input/Output E41 IO OV DD ---
GPIO2_29/IFC_AD29/ General Purpose Input/Output E40 IO OV DD ---
IFC_RB2_B
GPIO2_30/IFC_AD30/ General Purpose Input/Output E39 IO OV DD ---
IFC_RB3_B
GPIO2_31/IFC_AD31/ General Purpose Input/Output D41 IO OV DD ---
IFC_RB4_B
GPIO3_00/ General Purpose Input/Output A14 IO LV DD ---
TSEC_1588_CLK_IN
GPIO3_01/ General Purpose Input/Output N15 IO LV DD ---
TSEC_1588_TRIG_IN1
GPIO3_02/ General Purpose Input/Output N14 IO LV DD ---
TSEC_1588_TRIG_IN2
GPIO3_03/ General Purpose Input/Output K13 IO LV DD ---
TSEC_1588_ALARM_OUT1
GPIO3_04/ General Purpose Input/Output J12 IO LV DD ---
TSEC_1588_ALARM_OUT2
GPIO3_05/ General Purpose Input/Output F14 IO LV DD ---
TSEC_1588_CLK_OUT
GPIO3_06/ General Purpose Input/Output M14 IO LV DD ---
TSEC_1588_PULSE_OUT1
GPIO3_07/ General Purpose Input/Output L13 IO LV DD ---
TSEC_1588_PULSE_OUT2
GPIO3_08/EC1_TXD3 General Purpose Input/Output M12 IO LV DD ---

Pin assignments

pin type
number
GPIO3_09/EC1_TXD2 General Purpose Input/Output L12 IO LV DD ---
GPIO3_10/EC1_TXD1 General Purpose Input/Output K12 IO LV DD ---
GPIO3_11/EC1_TXD0 General Purpose Input/Output H12 IO LV DD ---
GPIO3_12/EC1_TX_EN General Purpose Input/Output C13 IO LV DD ---
GPIO3_13/EC1_GTX_CLK General Purpose Input/Output F12 IO LV DD ---
GPIO3_14/EC1_RX_DV General Purpose Input/Output A13 IO LV DD ---
GPIO3_15/EC1_RX_CLK General Purpose Input/Output B12 IO LV DD ---
GPIO3_16/EC1_RXD3 General Purpose Input/Output G12 IO LV DD ---
GPIO3_17/EC1_RXD2 General Purpose Input/Output A12 IO LV DD ---
GPIO3_18/EC1_RXD1 General Purpose Input/Output E12 IO LV DD ---
GPIO3_19/EC1_RXD0 General Purpose Input/Output C12 IO LV DD ---
GPIO3_20/EC2_TXD3 General Purpose Input/Output G11 IO LV DD ---
GPIO3_21/EC2_TXD2 General Purpose Input/Output F11 IO LV DD ---
GPIO3_22/EC2_TXD1 General Purpose Input/Output F10 IO LV DD ---
GPIO3_23/EC2_TXD0 General Purpose Input/Output D11 IO LV DD ---
GPIO3_24/EC2_TX_EN General Purpose Input/Output G10 IO LV DD ---
GPIO3_25/EC2_GTX_CLK General Purpose Input/Output H10 IO LV DD ---
GPIO3_26/EC2_RX_DV General Purpose Input/Output C10 IO LV DD ---
GPIO3_27/EC2_RX_CLK General Purpose Input/Output B10 IO LV DD ---
GPIO3_28/EC2_RXD3 General Purpose Input/Output D10 IO LV DD ---
GPIO3_29/EC2_RXD2 General Purpose Input/Output C11 IO LV DD ---
GPIO4_00/IIC3_SCL General Purpose Input/Output N13 IO DV DD ---
GPIO4_01/IIC3_SDA General Purpose Input/Output P13 IO DV DD ---
GPIO4_02/IIC4_SCL/EVT5_B General Purpose Input/Output N12 IO DV DD ---
GPIO4_03/IIC4_SDA/EVT6_B General Purpose Input/Output P12 IO DV DD ---
GPIO4_04/DMA1_DREQ0_B General Purpose Input/Output P43 IO OV DD ---
GPIO4_05/DMA1_DACK0_B General Purpose Input/Output R43 IO OV DD ---
GPIO4_06/DMA1_DDONE0_B General Purpose Input/Output R44 IO OV DD ---
GPIO4_07/DMA2_DREQ0_B General Purpose Input/Output N41 IO OV DD ---
GPIO4_08/DMA2_DACK0_B/ General Purpose Input/Output P44 IO OV DD ---
EVT7_B
GPIO4_09/ General Purpose Input/Output P42 IO OV DD ---
DMA2_DDONE0_B/EVT8_B
Power and Ground Signals
GND001 GND A43 --- --- ---
GND002 GND B11 --- --- ---

Pin assignments

pin type
number
GND003 GND B13 --- --- ---
GND004 GND B33 --- --- ---
GND005 GND B36 --- --- ---
GND006 GND B39 --- --- ---
GND007 GND B42 --- --- ---
GND008 GND B44 --- --- ---
GND009 GND C4 --- --- ---
GND010 GND C5 --- --- ---
GND011 GND C6 --- --- ---
GND012 GND C7 --- --- ---
GND013 GND C8 --- --- ---
GND014 GND C9 --- --- ---
GND015 GND D3 --- --- ---
GND016 GND D9 --- --- ---
GND017 GND D34 --- --- ---
GND018 GND D37 --- --- ---
GND019 GND D40 --- --- ---
GND020 GND D43 --- --- ---
GND021 GND E3 --- --- ---
GND022 GND E6 --- --- ---
GND023 GND E9 --- --- ---
GND024 GND E11 --- --- ---
GND025 GND F3 --- --- ---
GND026 GND F4 --- --- ---
GND027 GND F8 --- --- ---
GND028 GND F9 --- --- ---
GND029 GND F13 --- --- ---
GND030 GND F33 --- --- ---
GND031 GND F36 --- --- ---
GND032 GND F39 --- --- ---
GND033 GND F41 --- --- ---
GND034 GND G3 --- --- ---
GND035 GND G6 --- --- ---
GND036 GND G9 --- --- ---
GND037 GND G43 --- --- ---
GND038 GND H3 --- --- ---
GND039 GND H9 --- --- ---
GND040 GND H11 --- --- ---

Pin assignments

pin type
number
GND041 GND H34 --- --- ---
GND042 GND H37 --- --- ---
GND043 GND H39 --- --- ---
GND044 GND J3 --- --- ---
GND045 GND J5 --- --- ---
GND046 GND J7 --- --- ---
GND047 GND J9 --- --- ---
GND048 GND J13 --- --- ---
GND049 GND J41 --- --- ---
GND050 GND J44 --- --- ---
GND051 GND K3 --- --- ---
GND052 GND K6 --- --- ---
GND053 GND K9 --- --- ---
GND054 GND K33 --- --- ---
GND055 GND K36 --- --- ---
GND056 GND K43 --- --- ---
GND057 GND L3 --- --- ---
GND058 GND L6 --- --- ---
GND059 GND L9 --- --- ---
GND060 GND L11 --- --- ---
GND061 GND L39 --- --- ---
GND062 GND M3 --- --- ---
GND063 GND M6 --- --- ---
GND064 GND M9 --- --- ---
GND065 GND M13 --- --- ---
GND066 GND M34 --- --- ---
GND067 GND M41 --- --- ---
GND068 GND M44 --- --- ---
GND069 GND N3 --- --- ---
GND070 GND N6 --- --- ---
GND071 GND N9 --- --- ---
GND072 GND N37 --- --- ---
GND073 GND N43 --- --- ---
GND074 GND P3 --- --- ---
GND075 GND P6 --- --- ---
GND076 GND P9 --- --- ---
GND077 GND P11 --- --- ---
GND078 GND P14 --- --- ---

Pin assignments

pin type
number
GND079 GND P15 --- --- ---
GND080 GND P16 --- --- ---
GND081 GND P33 --- --- ---
GND082 GND P39 --- --- ---
GND083 GND R3 --- --- ---
GND084 GND R6 --- --- ---
GND085 GND R9 --- --- ---
GND086 GND R31 --- --- ---
GND087 GND R41 --- --- ---
GND088 GND T3 --- --- ---
GND089 GND T6 --- --- ---
GND090 GND T9 --- --- ---
GND091 GND T10 --- --- ---
GND092 GND T11 --- --- ---
GND093 GND T12 --- --- ---
GND094 GND T14 --- --- ---
GND095 GND T17 --- --- ---
GND096 GND T31 --- --- ---
GND097 GND T37 --- --- ---
GND098 GND T43 --- --- ---
GND099 GND U3 --- --- ---
GND100 GND U6 --- --- ---
GND101 GND U13 --- --- ---
GND102 GND U14 --- --- ---
GND103 GND U16 --- --- ---
GND104 GND U18 --- --- ---
GND105 GND U20 --- --- ---
GND106 GND U22 --- --- ---
GND107 GND U24 --- --- ---
GND108 GND U26 --- --- ---
GND109 GND U28 --- --- ---
GND110 GND U31 --- --- ---
GND111 GND U33 --- --- ---
GND112 GND U39 --- --- ---
GND113 GND V3 --- --- ---
GND114 GND V6 --- --- ---
GND115 GND V9 --- --- ---
GND116 GND V12 --- --- ---

Pin assignments

pin type
number
GND117 GND V14 --- --- ---
GND118 GND V17 --- --- ---
GND119 GND V19 --- --- ---
GND120 GND V21 --- --- ---
GND121 GND V23 --- --- ---
GND122 GND V25 --- --- ---
GND123 GND V27 --- --- ---
GND124 GND V29 --- --- ---
GND125 GND V31 --- --- ---
GND126 GND V34 --- --- ---
GND127 GND V41 --- --- ---
GND128 GND W3 --- --- ---
GND129 GND W6 --- --- ---
GND130 GND W9 --- --- ---
GND131 GND W12 --- --- ---
GND132 GND W13 --- --- ---
GND133 GND W14 --- --- ---
GND134 GND W16 --- --- ---
GND135 GND W18 --- --- ---
GND136 GND W20 --- --- ---
GND137 GND W22 --- --- ---
GND138 GND W24 --- --- ---
GND139 GND W26 --- --- ---
GND140 GND W28 --- --- ---
GND141 GND W31 --- --- ---
GND142 GND W33 --- --- ---
GND143 GND W37 --- --- ---
GND144 GND W43 --- --- ---
GND145 GND Y3 --- --- ---
GND146 GND Y6 --- --- ---
GND147 GND Y9 --- --- ---
GND148 GND Y14 --- --- ---
GND149 GND Y17 --- --- ---
GND150 GND Y19 --- --- ---
GND151 GND Y21 --- --- ---
GND152 GND Y23 --- --- ---
GND153 GND Y25 --- --- ---
GND154 GND Y27 --- --- ---

Pin assignments

pin type
number
GND155 GND Y29 --- --- ---
GND156 GND Y31 --- --- ---
GND157 GND Y35 --- --- ---
GND158 GND Y36 --- --- ---
GND159 GND Y37 --- --- ---
GND160 GND Y38 --- --- ---
GND161 GND Y39 --- --- ---
GND162 GND Y40 --- --- ---
GND163 GND Y41 --- --- ---
GND164 GND Y42 --- --- ---
GND165 GND AA3 --- --- ---
GND166 GND AA6 --- --- ---
GND167 GND AA10 --- --- ---
GND168 GND AA11 --- --- ---
GND169 GND AA12 --- --- ---
GND170 GND AA13 --- --- ---
GND171 GND AA14 --- --- ---
GND172 GND AA16 --- --- ---
GND173 GND AA18 --- --- ---
GND174 GND AA20 --- --- ---
GND175 GND AA22 --- --- ---
GND176 GND AA24 --- --- ---
GND177 GND AA26 --- --- ---
GND178 GND AA28 --- --- ---
GND179 GND AA31 --- --- ---
GND180 GND AA35 --- --- ---
GND181 GND AA42 --- --- ---
GND182 GND AB3 --- --- ---
GND183 GND AB4 --- --- ---
GND184 GND AB8 --- --- ---
GND185 GND AB14 --- --- ---
GND186 GND AB17 --- --- ---
GND187 GND AB19 --- --- ---
GND188 GND AB21 --- --- ---
GND189 GND AB23 --- --- ---
GND190 GND AB25 --- --- ---
GND191 GND AB27 --- --- ---
GND192 GND AB29 --- --- ---

Pin assignments

pin type
number
GND193 GND AB31 --- --- ---
GND194 GND AB32 --- --- ---
GND195 GND AB33 --- --- ---
GND196 GND AB34 --- --- ---
GND197 GND AB35 --- --- ---
GND198 GND AB42 --- --- ---
GND199 GND AC3 --- --- ---
GND200 GND AC6 --- --- ---
GND201 GND AC8 --- --- ---
GND202 GND AC14 --- --- ---
GND203 GND AC16 --- --- ---
GND204 GND AC18 --- --- ---
GND205 GND AC20 --- --- ---
GND206 GND AC22 --- --- ---
GND207 GND AC24 --- --- ---
GND208 GND AC26 --- --- ---
GND209 GND AC28 --- --- ---
GND210 GND AC31 --- --- ---
GND211 GND AC33 --- --- ---
GND212 GND AC36 --- --- ---
GND213 GND AC37 --- --- ---
GND214 GND AC38 --- --- ---
GND215 GND AC39 --- --- ---
GND216 GND AC40 --- --- ---
GND217 GND AC41 --- --- ---
GND218 GND AC42 --- --- ---
GND219 GND AD3 --- --- ---
GND220 GND AD5 --- --- ---
GND221 GND AD8 --- --- ---
GND222 GND AD10 --- --- ---
GND223 GND AD11 --- --- ---
GND224 GND AD12 --- --- ---
GND225 GND AD13 --- --- ---
GND226 GND AD14 --- --- ---
GND227 GND AD17 --- --- ---
GND228 GND AD19 --- --- ---
GND229 GND AD21 --- --- ---
GND230 GND AD23 --- --- ---

Pin assignments

pin type
number
GND231 GND AD25 --- --- ---
GND232 GND AD27 --- --- ---
GND233 GND AD29 --- --- ---
GND234 GND AD31 --- --- ---
GND235 GND AD33 --- --- ---
GND236 GND AD36 --- --- ---
GND237 GND AD39 --- --- ---
GND238 GND AD42 --- --- ---
GND239 GND AE3 --- --- ---
GND240 GND AE7 --- --- ---
GND241 GND AE9 --- --- ---
GND242 GND AE14 --- --- ---
GND243 GND AE16 --- --- ---
GND244 GND AE18 --- --- ---
GND245 GND AE20 --- --- ---
GND246 GND AE22 --- --- ---
GND247 GND AE24 --- --- ---
GND248 GND AE26 --- --- ---
GND249 GND AE28 --- --- ---
GND250 GND AE31 --- --- ---
GND251 GND AE33 --- --- ---
GND252 GND AE36 --- --- ---
GND253 GND AE39 --- --- ---
GND254 GND AE42 --- --- ---
GND255 GND AF3 --- --- ---
GND256 GND AF4 --- --- ---
GND257 GND AF5 --- --- ---
GND258 GND AF6 --- --- ---
GND259 GND AF9 --- --- ---
GND260 GND AF14 --- --- ---
GND261 GND AF17 --- --- ---
GND262 GND AF19 --- --- ---
GND263 GND AF21 --- --- ---
GND264 GND AF23 --- --- ---
GND265 GND AF25 --- --- ---
GND266 GND AF27 --- --- ---
GND267 GND AF29 --- --- ---
GND268 GND AF31 --- --- ---

Pin assignments

pin type
number
GND269 GND AF33 --- --- ---
GND270 GND AF36 --- --- ---
GND271 GND AF39 --- --- ---
GND272 GND AF42 --- --- ---
GND273 GND AG3 --- --- ---
GND274 GND AG8 --- --- ---
GND275 GND AG11 --- --- ---
GND276 GND AG12 --- --- ---
GND277 GND AG13 --- --- ---
GND278 GND AG14 --- --- ---
GND279 GND AG16 --- --- ---
GND280 GND AG18 --- --- ---
GND281 GND AG20 --- --- ---
GND282 GND AG22 --- --- ---
GND283 GND AG24 --- --- ---
GND284 GND AG26 --- --- ---
GND285 GND AG28 --- --- ---
GND286 GND AG31 --- --- ---
GND287 GND AG33 --- --- ---
GND288 GND AG36 --- --- ---
GND289 GND AG39 --- --- ---
GND290 GND AG42 --- --- ---
GND291 GND AH3 --- --- ---
GND292 GND AH9 --- --- ---
GND293 GND AH12 --- --- ---
GND294 GND AH14 --- --- ---
GND295 GND AH17 --- --- ---
GND296 GND AH19 --- --- ---
GND297 GND AH21 --- --- ---
GND298 GND AH23 --- --- ---
GND299 GND AH25 --- --- ---
GND300 GND AH27 --- --- ---
GND301 GND AH29 --- --- ---
GND302 GND AH31 --- --- ---
GND303 GND AH33 --- --- ---
GND304 GND AH36 --- --- ---
GND305 GND AH39 --- --- ---
GND306 GND AH42 --- --- ---

Pin assignments

pin type
number
GND307 GND AJ3 --- --- ---
GND308 GND AJ4 --- --- ---
GND309 GND AJ5 --- --- ---
GND310 GND AJ6 --- --- ---
GND311 GND AJ7 --- --- ---
GND312 GND AJ8 --- --- ---
GND313 GND AJ9 --- --- ---
GND314 GND AJ10 --- --- ---
GND315 GND AJ11 --- --- ---
GND316 GND AJ12 --- --- ---
GND317 GND AJ14 --- --- ---
GND318 GND AJ16 --- --- ---
GND319 GND AJ18 --- --- ---
GND320 GND AJ20 --- --- ---
GND321 GND AJ30 --- --- ---
GND322 GND AJ31 --- --- ---
GND323 GND AJ34 --- --- ---
GND324 GND AJ35 --- --- ---
GND325 GND AJ36 --- --- ---
GND326 GND AJ39 --- --- ---
GND327 GND AJ42 --- --- ---
GND328 GND AK3 --- --- ---
GND329 GND AK6 --- --- ---
GND330 GND AK9 --- --- ---
GND331 GND AK12 --- --- ---
GND332 GND AK13 --- --- ---
GND333 GND AK15 --- --- ---
GND334 GND AK17 --- --- ---
GND335 GND AK19 --- --- ---
GND336 GND AK33 --- --- ---
GND337 GND AK36 --- --- ---
GND338 GND AK37 --- --- ---
GND339 GND AK38 --- --- ---
GND340 GND AK39 --- --- ---
GND341 GND AK40 --- --- ---
GND342 GND AK41 --- --- ---
GND343 GND AK42 --- --- ---
GND344 GND AL3 --- --- ---

Pin assignments

pin type
number
GND345 GND AL6 --- --- ---
GND346 GND AL9 --- --- ---
GND347 GND AL12 --- --- ---
GND348 GND AL33 --- --- ---
GND349 GND AL34 --- --- ---
GND350 GND AL39 --- --- ---
GND351 GND AL42 --- --- ---
GND352 GND AM3 --- --- ---
GND353 GND AM6 --- --- ---
GND354 GND AM9 --- --- ---
GND355 GND AM12 --- --- ---
GND356 GND AM33 --- --- ---
GND357 GND AM36 --- --- ---
GND358 GND AM39 --- --- ---
GND359 GND AM42 --- --- ---
GND360 GND AN3 --- --- ---
GND361 GND AN6 --- --- ---
GND362 GND AN9 --- --- ---
GND363 GND AN12 --- --- ---
GND364 GND AN34 --- --- ---
GND365 GND AN35 --- --- ---
GND366 GND AN36 --- --- ---
GND367 GND AN39 --- --- ---
GND368 GND AN42 --- --- ---
GND369 GND AP3 --- --- ---
GND370 GND AP6 --- --- ---
GND371 GND AP9 --- --- ---
GND372 GND AP12 --- --- ---
GND373 GND AP14 --- --- ---
GND374 GND AP15 --- --- ---
GND375 GND AP16 --- --- ---
GND376 GND AP37 --- --- ---
GND377 GND AP39 --- --- ---
GND378 GND AP42 --- --- ---
GND379 GND AR3 --- --- ---
GND380 GND AR6 --- --- ---
GND381 GND AR9 --- --- ---
GND382 GND AR12 --- --- ---

Pin assignments

pin type
number
GND383 GND AR39 --- --- ---
GND384 GND AR42 --- --- ---
GND385 GND AT3 --- --- ---
GND386 GND AT4 --- --- ---
GND387 GND AT5 --- --- ---
GND388 GND AT6 --- --- ---
GND389 GND AT7 --- --- ---
GND390 GND AT8 --- --- ---
GND391 GND AT9 --- --- ---
GND392 GND AT10 --- --- ---
GND393 GND AT11 --- --- ---
GND394 GND AT12 --- --- ---
GND395 GND AT13 --- --- ---
GND396 GND AT14 --- --- ---
GND397 GND AT15 --- --- ---
GND398 GND AT16 --- --- ---
GND399 GND AT34 --- --- ---
GND400 GND AT35 --- --- ---
GND401 GND AT36 --- --- ---
GND402 GND AT39 --- --- ---
GND403 GND AT42 --- --- ---
GND404 GND AU3 --- --- ---
GND405 GND AU10 --- --- ---
GND406 GND AU37 --- --- ---
GND407 GND AU39 --- --- ---
GND408 GND AU41 --- --- ---
GND409 GND AU42 --- --- ---
GND410 GND AV3 --- --- ---
GND411 GND AV10 --- --- ---
GND412 GND AV38 --- --- ---
GND413 GND AV42 --- --- ---
GND414 GND AW3 --- --- ---
GND415 GND AW4 --- --- ---
GND416 GND AW5 --- --- ---
GND417 GND AW6 --- --- ---
GND418 GND AW7 --- --- ---
GND419 GND AW8 --- --- ---
GND420 GND AW9 --- --- ---

Pin assignments

pin type
number
GND421 GND AW10 --- --- ---
GND422 GND AW11 --- --- ---
GND423 GND AW12 --- --- ---
GND424 GND AW13 --- --- ---
GND425 GND AW14 --- --- ---
GND426 GND AW15 --- --- ---
GND427 GND AW16 --- --- ---
GND428 GND AW35 --- --- ---
GND429 GND AW36 --- --- ---
GND430 GND AW38 --- --- ---
GND431 GND AW40 --- --- ---
GND432 GND AW42 --- --- ---
GND433 GND AY3 --- --- ---
GND434 GND AY10 --- --- ---
GND435 GND AY38 --- --- ---
GND436 GND AY42 --- --- ---
GND437 GND BA3 --- --- ---
GND438 GND BA10 --- --- ---
GND439 GND BA34 --- --- ---
GND440 GND BA38 --- --- ---
GND441 GND BA42 --- --- ---
GND442 GND BB4 --- --- ---
GND443 GND BB5 --- --- ---
GND444 GND BB6 --- --- ---
GND445 GND BB7 --- --- ---
GND446 GND BB8 --- --- ---
GND447 GND BB9 --- --- ---
GND448 GND BB10 --- --- ---
GND449 GND BB11 --- --- ---
GND450 GND BB12 --- --- ---
GND451 GND BB13 --- --- ---
GND452 GND BB14 --- --- ---
GND453 GND BB15 --- --- ---
GND454 GND BB16 --- --- ---
GND455 GND BB35 --- --- ---
GND456 GND BB36 --- --- ---
GND457 GND BB37 --- --- ---
GND458 GND BB38 --- --- ---

Pin assignments

pin type
number
GND459 GND BB39 --- --- ---
GND460 GND BB40 --- --- ---
GND461 GND BB41 --- --- ---
GND_DET1 GND C3 --- --- ---
GND_DET2 GND BB3 --- --- ---
GND_DET3 GND BB42 --- --- ---
USB_AGND1 USB PHY 1 Transceiver GND D32 --- --- ---
USB_AGND2 USB PHY 1 Transceiver GND J32 --- --- ---
USB_AGND3 USB PHY 1 Transceiver GND L31 --- --- ---
USB_AGND4 USB PHY 1 Transceiver GND M32 --- --- ---
USB_AGND5 USB PHY 1 Transceiver GND N30 --- --- ---
X1GND01 Serdes 1 Transceiver GND F15 --- --- ---
X1GND05 Serdes 1 Transceiver GND G14 --- --- ---
X1GND10 Serdes 1 Transceiver GND H14 --- --- ---
X1GND15 Serdes 1 Transceiver GND J14 --- --- ---
X1GND20 Serdes 1 Transceiver GND K14 --- --- ---
X1GND21 Serdes 1 Transceiver GND L15 --- --- ---
X1GND23 Serdes 1 Transceiver GND M17 --- --- ---
X2GND01 Serdes 2 Transceiver GND E31 --- --- ---

Pin assignments

pin type
number
X2GND25 Serdes 2 Transceiver GND N29 --- --- ---
X3GND01 Serdes 3 Transceiver GND AN20 --- --- ---
X3GND03 Serdes 3 Transceiver GND AP18 --- --- ---
X3GND05 Serdes 3 Transceiver GND AR17 --- --- ---
X3GND06 Serdes 3 Transceiver GND AT17 --- --- ---
X3GND11 Serdes 3 Transceiver GND AU17 --- --- ---
X3GND16 Serdes 3 Transceiver GND AV17 --- --- ---

Pin assignments

pin type
number
X3GND21 Serdes 3 Transceiver GND AW18 --- --- ---
X4GND01 Serdes 4 Transceiver GND AM32 --- --- ---
X4GND25 Serdes 4 Transceiver GND AY34 --- --- ---
S1GND01 Serdes 1 core logic GND A15 --- --- ---
S1GND05 Serdes 1 core logic GND B14 --- --- ---

Pin assignments

pin type
number
S1GND10 Serdes 1 core logic GND C14 --- --- ---
S1GND15 Serdes 1 core logic GND D14 --- --- ---
S1GND20 Serdes 1 core logic GND E14 --- --- ---
S1GND29 Serdes 1 core logic GND M15 --- --- ---
S1GND31 Serdes 1 core logic GND N16 --- --- ---
S1GND36 Serdes 1 core logic GND P17 --- --- ---
S1GND37 Serdes 1 core logic GND R18 --- --- ---

Pin assignments

pin type
number
S2GND34 Serdes 2 core logic GND P28 --- --- ---
S3GND01 Serdes 3 core logic GND AK21 --- --- ---

Pin assignments

pin type
number
S3GND06 Serdes 3 core logic GND AL20 --- --- ---
S3GND07 Serdes 3 core logic GND AM19 --- --- ---
S3GND12 Serdes 3 core logic GND AN18 --- --- ---
S3GND14 Serdes 3 core logic GND AY17 --- --- ---
S3GND23 Serdes 3 core logic GND BA17 --- --- ---
S3GND28 Serdes 3 core logic GND BB17 --- --- ---
S3GND33 Serdes 3 core logic GND BC17 --- --- ---
S3GND38 Serdes 3 core logic GND BD18 --- --- ---

Pin assignments

pin type
number
S4GND06 Serdes 4 core logic GND AL31 --- --- ---

Pin assignments

pin type
number
AGND_SD1_PLL1 Serdes1 PLL 1 GND L18 --- --- ---
AGND_SD3_PLL1 Serdes3 PLL 1 GND AP21 --- --- ---
SENSEGND_CA GND Sense pin R13 --- --- ---
SENSEGND_CB GND Sense pin AM17 --- --- ---
SENSEGND_CC GND Sense pin AA33 --- --- ---
SENSEGND_PL GND Sense pin AA32 --- --- ---
OVDD1 General I/O supply R30 --- OV DD ---
OVDD2 General I/O supply T30 --- OV DD ---
OVDD3 General I/O supply U30 --- OV DD ---
OVDD4 General I/O supply V30 --- OV DD ---
OVDD5 General I/O supply W30 --- OV DD ---
OVDD6 General I/O supply Y30 --- OV DD ---
OVDD7 General I/O supply AA30 --- OV DD ---
OVDD8 General I/O supply AK14 --- OV DD ---
DVDD1 UART/I2C supply R14 --- DV DD ---
DVDD2 UART/I2C supply R15 --- DV DD ---
G1VDD01 DDR supply for port 1 A2 --- G1V DD ---
G1VDD04 DDR supply for port 1 B1 --- G1V DD ---
G1VDD07 DDR supply for port 1 D2 --- G1V DD ---
G1VDD08 DDR supply for port 1 F1 --- G1V DD ---
G1VDD09 DDR supply for port 1 H2 --- G1V DD ---
G1VDD10 DDR supply for port 1 K1 --- G1V DD ---
G1VDD11 DDR supply for port 1 M2 --- G1V DD ---
G1VDD12 DDR supply for port 1 P1 --- G1V DD ---
G1VDD13 DDR supply for port 1 T2 --- G1V DD ---

Pin assignments

pin type
number
G1VDD14 DDR supply for port 1 T15 --- G1V DD ---
G1VDD15 DDR supply for port 1 U15 --- G1V DD ---
G1VDD16 DDR supply for port 1 V1 --- G1V DD ---
G1VDD17 DDR supply for port 1 V15 --- G1V DD ---
G1VDD18 DDR supply for port 1 W15 --- G1V DD ---
G1VDD19 DDR supply for port 1 Y2 --- G1V DD ---
G1VDD21 DDR supply for port 1 AA15 --- G1V DD ---
G1VDD22 DDR supply for port 1 AB1 --- G1V DD ---
G1VDD24 DDR supply for port 1 AD2 --- G1V DD ---
G1VDD25 DDR supply for port 1 AF1 --- G1V DD ---
G2VDD01 DDR supply for port 2 AC15 --- G2V DD ---
G2VDD03 DDR supply for port 2 AE15 --- G2V DD ---
G2VDD05 DDR supply for port 2 AG1 --- G2V DD ---
G2VDD07 DDR supply for port 2 AH15 --- G2V DD ---
G2VDD08 DDR supply for port 2 AJ2 --- G2V DD ---
G2VDD09 DDR supply for port 2 AJ15 --- G2V DD ---
G2VDD10 DDR supply for port 2 AL1 --- G2V DD ---
G2VDD11 DDR supply for port 2 AN2 --- G2V DD ---
G2VDD12 DDR supply for port 2 AR1 --- G2V DD ---
G2VDD13 DDR supply for port 2 AU2 --- G2V DD ---
G2VDD14 DDR supply for port 2 AW1 --- G2V DD ---
G2VDD15 DDR supply for port 2 BA2 --- G2V DD ---
G2VDD16 DDR supply for port 2 BC1 --- G2V DD ---
G2VDD21 DDR supply for port 2 BD2 --- G2V DD ---

Pin assignments

pin type
number
G3VDD05 DDR supply for port 3 AC30 --- G3V DD ---
G3VDD08 DDR supply for port 3 AE30 --- G3V DD ---
G3VDD14 DDR supply for port 3 AK43 --- G3V DD ---
G3VDD15 DDR supply for port 3 AM44 --- G3V DD ---
G3VDD16 DDR supply for port 3 AP43 --- G3V DD ---
G3VDD17 DDR supply for port 3 AT44 --- G3V DD ---
G3VDD18 DDR supply for port 3 AV43 --- G3V DD ---
G3VDD19 DDR supply for port 3 AY44 --- G3V DD ---
G3VDD20 DDR supply for port 3 BB43 --- G3V DD ---
S1VDD1 SerDes1 core logic supply N17 --- S1V DD ---
S1VDD2 SerDes1 core logic supply P20 --- S1V DD ---
S1VDD4 SerDes1 core logic supply T19 --- S1V DD ---

Pin assignments

pin type
number
S3VDD1 SerDes3 core logic supply AJ22 --- S3V DD ---
S3VDD5 SerDes3 core logic supply AL23 --- S3V DD ---
S3VDD7 SerDes3 core logic supply AM20 --- S3V DD ---
X1VDD1 SerDes1 transceiver supply K15 --- X1V DD ---
X2VDD9 SerDes2 transceiver supply M30 --- X2V DD ---
X3VDD1 SerDes3 transceiver supply AR18 --- X3V DD ---

Pin assignments

pin type
number
X4VDD1 SerDes4 transceiver supply AN33 --- X4V DD ---
LVDD1 Ethernet controller and GPIO L14 --- LV DD ---
supply
LVDD2 Ethernet controller and GPIO R16 --- LV DD ---
supply
LVDD3 Ethernet controller and GPIO R17 --- LV DD ---
supply
FA_VL Reserved for internal use only R33 --- FA_VL 15
PROG_MTR Reserved for internal use only T29 --- PROG_MTR 15
PROG_SFP SFP Fuse Programming R29 --- PROG_SFP ---
Override supply
TH_VDD Thermal Monitor Unit supply V32 --- TH_V DD 27
VDD01 Supply for cores and platform T16 --- V DD ---
VDD02 Supply for cores and platform U17 --- V DD ---
VDD09 Supply for cores and platform V16 --- V DD ---
VDD16 Supply for cores and platform W17 --- V DD ---

Pin assignments

pin type
number
VDD23 Supply for cores and platform Y16 --- V DD ---
VDD30 Supply for cores and platform AA17 --- V DD ---
VDD37 Supply for cores and platform AB16 --- V DD ---
VDD44 Supply for cores and platform AC17 --- V DD ---
VDD51 Supply for cores and platform AD16 --- V DD ---

Pin assignments

pin type
number
VDD58 Supply for cores and platform AE17 --- V DD ---
VDD65 Supply for cores and platform AF16 --- V DD ---
VDD72 Supply for cores and platform AG17 --- V DD ---
VDD79 Supply for cores and platform AH16 --- V DD ---
VDD86 Supply for cores and platform AJ17 --- V DD ---
VDD89 Supply for cores and platform AK16 --- V DD ---
VDD_LP Low Power Security Monitor R28 --- V DD _LP ---
supply
AVDD_CGA1 e6500 Cluster Group A PLL1 AP13 --- AVDD_CGA1 ---
supply

Pin assignments

pin type
number
AVDD_CGA2 e6500 Cluster Group A PLL2 AR13 --- AVDD_CGA2 ---
supply
AVDD_CGA3 e6500 Cluster Group A PLL3 AR14 --- AVDD_CGA3 ---
supply
AVDD_CGB1 e6500 Cluster Group B PLL1 AR16 --- AVDD_CGB1 ---
supply
AVDD_CGB2 e6500 Cluster Group B PLL2 AR15 --- AVDD_CGB2 ---
supply
AVDD_PLAT Platform PLL supply T28 --- AVDD_PLAT ---
AVDD_D1 DDR1 PLL supply T13 --- AVDD_D1 ---
AVDD_D2 DDR2 PLL supply AJ13 --- AVDD_D2 ---
AVDD_D3 DDR3 PLL supply AC32 --- AVDD_D3 ---
AVDD_SD1_PLL1 SerDes1 PLL 1 supply L17 --- AVDD_SD1_PLL1 ---
AVDD_SD3_PLL1 SerDes3 PLL 1 supply AP20 --- AVDD_SD3_PLL1 ---
SENSEVDD_CA Vdd Sense pin for core cluster R12 --- SENSEVDD_CA ---
A
SENSEVDD_CB Vdd Sense pin for core cluster AM16 --- SENSEVDD_CB ---
B
SENSEVDD_CC Vdd Sense pin for core cluster Y33 --- SENSEVDD_CC ---
C
SENSEVDD_PL Vdd Sense pin for platform Y32 --- SENSEVDD_PL ---
USB_HVDD1 USB PHY Transceiver 3.3V K32 --- USB_HV DD ---
Supply
USB_HVDD2 USB PHY Transceiver 3.3V N32 --- USB_HV DD ---
Supply
USB_OVDD1 USB PHY Transceiver 1.8V P31 --- USB_OV DD ---
Supply
USB_OVDD2 USB PHY Transceiver 1.8V P32 --- USB_OV DD ---
Supply
USB_SVDD1 USB PHY Analog 1.0V Supply P29 --- USB_SV DD ---
USB_SVDD2 USB PHY Analog 1.0V Supply P30 --- USB_SV DD ---
No Connection Pins
NC01 No Connection G35 --- --- 12

Pin assignments

pin type
number
NC05 No Connection H33 --- --- 12
NC09 No Connection J33 --- --- 12
NC15 No Connection K34 --- --- 12
NC19 No Connection L33 --- --- 12
NC25 No Connection M33 --- --- 12
NC30 No Connection N33 --- --- 12
NC35 No Connection P34 --- --- 12
NC40 No Connection R34 --- --- 12

Pin assignments

pin type
number
NC45 No Connection T18 --- --- 12
NC51 No Connection U32 --- --- 12
NC56 No Connection V35 --- --- 12
NC60 No Connection W34 --- --- 12
NC64 No Connection AE32 --- --- 12
NC65 No Connection AG32 --- --- 12
NC66 No Connection AH32 --- --- 12
NC67 No Connection AJ32 --- --- 12
NC68 No Connection AJ33 --- --- 12
NC69 No Connection AK31 --- --- 12
NC70 No Connection AK32 --- --- 12
NC71 No Connection AL15 --- --- 12
NC75 No Connection AM14 --- --- 12
NC78 No Connection AN13 --- --- 12

Pin assignments

pin type
number
NC83 No Connection AP17 --- --- 12
NC84 No Connection AW17 --- --- 12
NC_DET No Connection C42 --- --- 12
1. Functionally, this pin is an output or an input, but structurally it is an I/O because it

either samples configuration input during reset, is a muxed pin, or has other
manufacturing test functions. This pin will therefore be described as an I/O for boundary
scan.
2. This output is actively driven during reset rather than being tri-stated during reset.
3. MDIC[0] is grounded through an 237 Ω (for Rev. 1) or 187 Ω (for Rev. 2) precision
1% resistor and MDIC[1] is connected to GV DD through an 237 Ω (for Rev. 1) or 187 Ω
(for Rev. 2) precision 1% resistor. For either full or half driver strength calibration of
DDR I/Os, use the same MDIC resistor value of 237 Ω (for Rev. 1) or 187 Ω (for Rev. 2).
Memory controller register setting can be used to determine automatic calibration is done
to full or half drive strength. These pins are used for automatic calibration of the DDR3/
DDR3L IOs. The MDIC[0:1] pins must be connected to 237 Ω (for Rev. 1) or 187 Ω (for
Rev. 2) precision 1% resistors.
4. This pin is a reset configuration pin. It has a weak (~20 kΩ) internal pull-up P-FET that
is enabled only when the processor is in its reset state. This pull-up is designed such that
it can be overpowered by an external 4.7 kΩ resistor. However, if the signal is intended to
be high after reset, and if there is any device on the net that might pull down the value of
the net at reset, a pull-up or active driver is needed.
5. Pin must NOT be pulled down during power-on reset. This pin may be pulled up,
driven high, or if there are any externally connected devices, left in tristate. If this pin is
connected to a device that pulls down during reset, an external pull-up is required to drive
this pin to a safe state during reset.
6. Recommend that a weak pull-up resistor (2 to 10 kΩ) be placed on this pin to the
respective power supply, or appropriate pull up resistor value for signals like HRESET_B
which might require 1 kΩ.
7. This pin is an open-drain signal.

Pin assignments
8. Recommend a pull-up resistor be placed on this pin to the respective power supply. In
the I2C interface, the value of the resistor should be calculated such that maximum rise
time stays under 300 ns as well as VOL be under 0.4 V at IOL = 3 mA IOL and I2C load
capacitance which should not exceed 400 pF.
9. This pin has a weak (~20 kΩ) internal pull-up P-FET that is always enabled.
10. These are test signals for factory use only and must be pulled up (100 Ω to 1 kΩ) to
the respective power supply for normal operation.
11. This pin requires a 200 Ω pull-up to respective power supply.
12. Do not connect. These pins should be left floating.
13. These pins must be pulled up to 1.2 V through a 180 Ω ± 1% resistor for MDC and a
330 Ω ± 1% resistor for MDIO.
14. This pin requires an external 1 kΩ pull-down resistor to prevent PHY from seeing a
valid Transmit Enable before it is actively driven.
15. These pins must be pulled to ground (GND).
16. This pin requires a 698 Ω pull-up to respective power supply.
18. Recommend that a weak pull-up resistor (4.7 kΩ) be placed on this pin to the
respective power supply.
19. These pins should be tied to ground if the diode is not utilized for temperature
monitoring.
20. This pin requires a pull-up of 10 to 50 kΩ to its corresponding I/O supply if it is not a
GPIO or not used as one.
21. This pin always needs to be either pulled up by 10 to 50 kΩ or down by 4.7 kΩ to
GND, depending on the intended RCW setting to be high or low, respectively.
22. If used as SDHC signal, pull-up 10 to 100 kΩ to the respective I/O supply.
23. New board designs should leave a place holder for a series resistor and capacitor
filter, which is in parallel and very close proximity to a 1%, 10 kΩ resistor pulling
USB_IBIAS_REXT low. This allows the flexibility of populating them if needed to
avoid board coupled noise to this pin. An SMD ceramic 100 nF low ESL in series with
100 Ω SMD resistor will do the filtration needed with slight variations that suit each
board case.
24. The non-ideality factor over temperature range 85C⁰ to 105C⁰, n = 1.006 ± 0.003,
with approximate error +/- 1 C⁰ and approximate error under +/- 3 C⁰ for temperature
range 0 C⁰ to 85C⁰.

Electrical characteristics
25. In GPCM mode, this pin also serves as IFC_WE1_B.

26. T4240/T4160/T4080 Rev. 2 silicon requires SDHC_CD_B and SDHC_WP signals
even when eMMC/eSDHC is used.
27. TH_VDD is a quiet power domain used for the Thermal Unit. Despite being de-
featured, it should be connected to a quiet recommended supply level.
28. When Dn_MDQS_B[9:17] pins are not used; terminate with 50 Ω to VTT or 100 Ω to
GND. Place termination close to T4 pin when discrete x8 or x16 DRAM is used or close
to the DIMM connector when signals are connected to DIMM connector to be used only
by DIMMs with x8 or x16 DRAM.
29. For T4160, this pin may be left floating or pulled up. For T4080, this pin must be
pulled to ground. Pull with a 4.7 k resistor.
Warning
See "Connection Recommendations" for additional details on
properly connecting these pins for specific applications.
3 Electrical characteristics
This section provides the AC and DC electrical specifications for the chip. The chip is
currently targeted to these specifications, some of which are independent of the I/O cell
but are included for a more complete reference. These are not purely I/O buffer design
specifications.
3.1 Overall DC electrical characteristics

This section describes the ratings, conditions, and other characteristics.
3.1.1 Absolute maximum ratings

This table provides the absolute maximum ratings.
Table 2. Absolute maximum ratings1
Absolute Maximum Ratings for Supply Voltage Levels
Characteristic Symbol Min Max Unit Notes
Core and platform VDD -0.3 1.08 V 9, 11
supply voltage

Table 2. Absolute maximum ratings1 (continued)

PLL supply voltage AVDD_CGAn -0.3 1.98 V 11
(core, platform, DDR)
AVDD_CGBn
AVDD_PLAT
AVDD_Dn
PLL supply voltage AVDD_SDn_PLLn -0.3 1.65 V 11
(SerDes, filtered from
-0.3 1.48
XnVDD)
Fuse programming PROG_SFP -0.3 1.98 V 11
override supply
Thermal monitor unit TH_VDD -0.3 1.98 V 10, 11
supply
eSHDC, eSPI, DMA, OVDD -0.3 1.98 V 11
MPIC, GPIO, system
control and power
management, clocking,
debug, IFC, DDRCLK
supply, and JTAG I/O
voltage
DUART, I2C I/O voltage DVDD -0.3 2.75 V 11
-0.3 1.98
DDR3 DRAM I/O GnVDD -0.3 1.58 V 11
voltage
DDR3L DRAM I/O GnVDD -0.3 1.42 V 11
voltage
Main power supply for SnVDD -0.3 1.08 V 11
internal circuitry of
SerDes and pad power
supply for SerDes
receivers
Pad power supply for XnVDD -0.3 1.65 V 8, 11
SerDes transmitter
-0.3 1.45
Ethernet, Ethernet LVDD -0.3 2.75 V 11
management interface
-0.3 1.98
1 (EMI1) 1588, GPIO
I/O voltage
Ethernet management — -0.3 1.32 V 7, 11
interface 2 (EMI2) I/O
voltage
USB PHY Transceiver USB_HVDD -0.3 3.63 V 11
supply voltage USB_OVDD -0.3 1.98 V 11
USB PHY Analog USB_SVDD -0.3 1.08 V 11
supply voltage
Low Power Security VDD_LP -0.3 1.08 V 11
Monitor supply
Absolute Maximum Ratings for Storage Temperature Conditions
Characteristic Symbol Min Max Unit Notes

Table 2. Absolute maximum ratings1 (continued)

Storage temperature TSTG -55 155 °C —
range
Absolute Maximum Ratings for Input Signal Voltage Levels
Interface Input Signal Symbol Min_DCV Max_DCV Min Max Unit Notes
Undersho Overshoot
V_input V_input
ot Voltage Voltage
DDR3 and DDR3L MVIN GND Nominal -0.3 Nominal V 2, 13
DRAM signals GVDD x GVDD x 1.1
1.05
DDR3 and DDR3L Dn_MVREF GND Nominal -0.3 Nominal V 5
DRAM reference GVDD/2 x GVDD/2 x
1.05 1.1
Ethernet (except EMI2), LVIN GND Nominal -0.3 Nominal V 4, 5
1588, GPIO signals LVDD x 1.1 LVDD x
1.15
eSHDC, eSPI, DMA, OVIN GND Nominal -0.3 Nominal V 3, 5
MPIC, GPIO, system OVDD x 1.1 OVDD x
control and power 1.15
management, clocking,
debug, IFC, DDRCLK
supply, and JTAG
signals
DUART, I2C signals DVIN GND Nominal -0.3 Nominal V 5, 6
DVDD x 1.1 DVDD x
1.15
SerDes No internal SVIN 0.8 V SnGND Nominal 0.3 Nominal V 5
signals termination maximum SnVDD x SnVDD x
selected signal 1.05 1.1
swing
starting
from 0.3 V
0.8 V SnGND Nominal -0.4 +0.4
maximum SnVDD x
signal 1.05
swing
starting
from -0.4 V
50 Ω SVIN SnGND +0.3 -0.4 +0.4
internal
termination
selected
USB PHY Transceiver USB_HVIN USB_AGN USB_HVDD -0.3 USB_HVDD V 5, 12
signals D + 0.3 + 0.3
USB_OVIN USB_AGN USB_OVD -0.3 USB_OVD V 5, 12
D D x 1.1 D x 1.15
Ethernet management — GND 1.2 x 1.1 -0.3 1.2 x 1.15 V —

interface 2 signals
LP Trust signal VIN_LP GND 1.05 x -0.3 1.1 x V —
LP_TMP_DETECT_B VDD_LP VDD_LP
Notes:

Table 2. Absolute maximum ratings1

1. Functional operating conditions are given in Table 3. Absolute maximum ratings are stress ratings only, and functional
operation at the maximums is not guaranteed. Stresses beyond those listed may affect device reliability or cause permanent
damage to the device.
2. Caution: MVIN must not exceed GVDD by more than 0.3 V. This limit may be exceeded for a maximum of 20 ms during
power-on reset and power-down sequences.
3. Caution: OVIN must not exceed OVDD by more than 0.3 V. This limit may be exceeded for a maximum of 20 ms during
4. Caution:LVIN must not exceed LVDD by more than 0.3 V. This limit may be exceeded for a maximum of 20 ms during
5. (G,O,L,D,S, USB_H, USB_O)VIN may overshoot/undershoot to a voltage and for a maximum duration as shown in Figure
7. Note that the Dn_MVREF maximum slew rate is restricted to 25 kv/s.
6. Caution: DVIN must not exceed DVDD by more than 0.3 V. This limit may be exceeded for a maximum of 20 ms during
7. Ethernet MII management interface 2 pins function as open drain I/Os. The interface shall conform to 1.2 V nominal
voltage levels.
8. The cfg_xvdd_sel (ASLEEP) reset configuration pin must select the correct XVDD voltage.
9. Supply voltage specified at the voltage sense pin. Voltage input pins should be regulated to provide specified voltage at the
sense pin. For additional information, see the "Ganged sense-line implementation example" section in the T4240 QorIQ
Integrated Processor Design Checklist (AN4559). See also note 6 in Table 3.
10. Thermal monitoring unit is de featured on current silicon, but TH_VDD should be biased always.
11. Exposing device to Absolute Maximum Ratings conditions for long periods of time may affect reliability or cause
permanent damage.
12. USB Overshoot or Undershoot signal time should be under 10% of signal rise time or under 2 nSec.
13. Typical DDR interface uses ODT enabled mode. For test purposes with ODT off mode, simulation should be done first so
as to make sure that the overshoot signal level at the input pin does not exceed GVDD by more than 10%. The Overshoot/
Undershoot period should comply with JEDEC standards.
3.1.2 Recommended operating conditions

This table provides the recommended operating conditions for this chip.
NOTE
The values shown are the recommended operating conditions
and proper device operation outside these conditions is not
guaranteed.
Table 3. Recommended operating conditions
Characteristic Symbol Recommended Unit Notes
Value
Core and platform supply voltage At initial start-up VDD ( VID or 1.025 V) ± V 4, 5, 6,
30 mV 7, 9
During normal operation VID ± 30 mV

Table 3. Recommended operating conditions (continued)

Value
PLL supply voltage (core, platform, DDR) AVDD_CGAn 1.8 V ± 90 mV V 11
AVDD_CGBn
AVDD_PLAT
AVDD_Dn
PLL supply voltage (SerDes, filtered from XnVDD) AVDD_SDn_PLLn 1.5 V ± 75 mV or V -
1.35 V ± 67 mV
Fuse programming override supply PROG_SFP 1.8 V ± 90 mV V 2
Thermal monitor unit supply TH_VDD 1.8 V ± 90 mV V 8
eSHDC, eSPI, DMA, MPIC, GPIO, system control and power OVDD 1.8 V ± 90 mV V -
management, clocking, debug, IFC, DDRCLK supply, and JTAG
I/O voltage
DUART, I2C I/O voltage DVDD 2.5 V ± 125 mV V -
1.8 V ± 90 mV
DDR DRAM I/O voltage DDR3 GnVDD 1.5 V ± 75 mV V -
DDR3L 1.35 V ± 67 mV
Main power supply for internal circuitry of SerDes and pad power SnVDD 1.0 V ± 50 mV V -
supply for SerDes receivers
Pad power supply for SerDes transmitters XnVDD 1.5 V ± 75 mV V -
1.35 V ± 67 mV
Ethernet, Ethernet management interface 1 (EMI1), 1588, GPIO LVDD 2.5 V ± 125 mV V 1
I/O voltage
1.8 V ± 90 mV
Ethernet management interface 2 (EMI2) I/O voltage - 1.2 V ± 60 mV V 10
USB PHY Transceiver supply voltage USB_HVDD 3.3 V ± 165 mV V -
USB_OVDD 1.8 V ± 90 mV V -
USB PHY Analog supply voltage At initial start-up USB_SVDD ( VID or 1.025 V ) ± V 6,7,9
30 mV
During normal operation VID ± 30 mV
Low Power Security Monitor supply VDD_LP 1.0 V ± 50 mV V -
Input voltage DDR3 and DDR3L DRAM MVIN GND to GVDD V -
signals
DDR3 and DDR3L DRAM Dn_MVREF GVDD/2 ± 1% V -
reference
Ethernet (except EMI2), LVIN GND to LVDD V -
1588, GPIO signals
eSHDC, eSPI, DMA, MPIC, OVIN GND to OVDD V -
GPIO, system control and
power management,
clocking, debug, IFC,
DDRCLK supply, and JTAG
signals
DUART, I2C signals DVIN GND to DVDD V -
SerDes signals SVIN GND to SVDD V -

Table 3. Recommended operating conditions (continued)

Value
USB PHY Transceiver USB_HVIN GND to USB_HVDD V -
signals USB_OVIN GND to USB_OVDD V -
Ethernet management - GND to 1.2V V 3
interface 2 (EMI2) signals
LP Trust signal VIN_LP GND to VDD_LP V -
LP_TMP_DETECT_B
Operating temperature range Normal operation TA, TA = 0 (min) to °C -
TJ TJ = 105(max)
Extended Temperature TA, TA = -40 (min) to °C -
TJ TJ = 105(max)
Secure boot fuse TA, TA = 0 (min) to °C 2
programming
TJ TJ = 70 (max)
1. Selecting RGMII limits to LVDD = 2.5 V.
2. PROG_SFP must be supplied 1.8 V and the chip must operate in the specified fuse programming temperature range only
during secure boot fuse programming. For all other operating conditions, PROG_SFP must be tied to GND, subject to the
power sequencing constraints shown in Power sequencing.
3. Ethernet MII management interface 2 pins function as open drain I/Os. The interface conforms to 1.2 V nominal voltage
levels.
4. Refer to Voltage ID (VID) controllable supply and Core and platform supply voltage filtering for additional information.
5. Supply voltage specified at the voltage sense pin. Voltage input pins should be regulated to provide specified voltage at the
sense pin. For additional information, see the "Ganged sense-line implementation example" section in the T4240 QorIQ
Integrated Processor Design Checklist (AN4559).
6. Operation at 1.1V is allowable for up to 25ms at initial power on. Alternatively the initial start-up voltage can power up
straight to the VID voltage if the system has previously programmed that specific part’s VID value.
7. Voltage ID (VID) operating range is between 0.975V to 1.025V. Regulator selection should be based on Vout range wider
than VIDmin to VIDmax with resolution of 12.5mV or better.
8. Keep this pin biased to the specified voltage, despite the thermal monitoring unit being de-featured.
9. If VID is known at initial start-up, set VDD=VID else if VID is not known at initial start-up, set VDD to 1.025V and change it
immediately, to VDD=VID after reading VID at the beginning of booting.
10.This supply does not have a designated pin in this device because it is used only for EMI2 signals external pull-up resistor
source.
11.Keep filter close to pin. Voltage and tolerance for AVDD is defined at the input of the PLL supply filter and not the pin of
AVDD.
This figure shows the undershoot and overshoot voltages at the interfaces of the chip.

Maximum overshoot
D/X/S/G/L/OVDD
VIH
GND
VIL
Minimum undershoot
Overshoot/undershoot period
Notes:
The overshoot/undershoot period should be less than 10% of shortest possible toggling period " bit time", of the
input signal or per input signal specific protocol requirement. For GPIO input signal overshoot/undershoot period,
it should be less than 10% of the SYSCLK period.
Figure 7. Overshoot/Undershoot voltage for USB_OVIN/USB_HVIN/LVIN/OVIN/MVIN/

SVIN/DVIN
See Table 3 for actual recommended core voltage. Voltage to the processor interface I/Os
are provided through separate sets of supply pins and must be provided at the voltages
shown in Table 3. The input voltage threshold scales with respect to the associated I/O
supply voltage. DVDD, OVDD and LVDD based receivers are simple CMOS I/O circuits
and satisfy appropriate LVCMOS type specifications. The DDR SDRAM interface uses
differential receivers referenced by the externally supplied Dn_MVREF signal (nominally
set to GVDD/2) as is appropriate for the SSTL_1.35/SSTL_1.5 electrical signaling
standard. The DDR DQS receivers cannot be operated in single-ended fashion. The
complement signal must be properly driven and cannot be grounded.
3.1.3 Output driver characteristics

This chip provides information on the characteristics of the output driver strengths.
NOTE
These values are preliminary estimates.

Table 4. Output drive capability

Driver type Output impedance (Ω) Supply voltage Notes
DDR3 signal 18(full-strength mode) GVDD = 1.5 V 1
27(half-strength mode)
DDR3L signal 18(full-strength mode) GVDD = 1.35 V 1
27(half-strength mode)
Ethernet signals 45 LVDD = 2.5 V 2
eSPI, JTAG, system control, Integrated flash controller (IFC) 45 OVDD = 1.8 V 2
DUART, I2C 45 DVDD = 2.5 V 2
DVDD = 1.8 V
1. The drive strength of the DDR3 or DDR3L interface in half-strength mode is at Tj = 105 °C and at GVDD (min).
2. Impedance value varies by +/- 20%
3.2 Power sequencing

For power up, the requirements are as follows:
1. Bring up VDD, SnVDD, USB_SVDD, VDD_LP, USB_HVDD, LVDD, DVDD,
USB_OVDD, OVDD, TH_VDD, AVDD (cores, platform, DDR), GnVDD, XnVDD, and
AVDD_SDn_PLLn. Drive PROG_SFP = GND.
• PORESET_B input must be driven asserted and held during this step.
Power supplies in this step have no ordering requirement with respect to one another
except for the USB power supplies per the following note.
NOTE
a. USB_SVDD supply must ramp before or after the
USB_HVDD and USB_OVDD supplies have ramped.
The supply set that ramp first must reach 90% of its
final value before a supply from the other set can be
ramped up.
b. USB_HVDD and USB_OVDD supplies among
themselves are sequence independent.
c. USB_HVDD rise time (10% to 90%) has a minimum of
100 us.
2. Negate PORESET_B input as long as the required assertion/hold time has been met
per Table 21.
3. For secure boot fuse programming, use the following steps:
a. After negation of PORESET_B, drive PROG_SFP = 1.8 V after a required
minimum delay per Table 5.

b. After fuse programming is completed, it is required to return PROG_SFP =

GND before the system is power cycled (PORESET_B assertion) or powered
down (VDD ramp down) per the required timing specified in Table 5. See
Security fuse processor, for additional details.
Warning
No activity other than that required for secure boot fuse
programming is permitted while PROG_SFP is driven
to any voltage above GND, including the reading of the
fuse block. The reading of the fuse block may only
occur while PROG_SFP = GND.
From a system standpoint, if any of the I/O power

supplies ramp prior to the VDD supply, there will be a
brief period as the VDD powers up that the I/Os
associated with that I/O supply may go from being tri-
stated to an indeterminate state (either driven to a logic
one or zero), and extra current may be drawn by the
device.
Only 300,000 POR cycles are permitted per lifetime of

a device. Note that this value is based on design
estimates and is preliminary.
All supplies must be at their stable values within 400 ms.

If using Trust Architecture Security Monitor battery backed features, then ensure that
both, OVDD is ramped to recommended operational voltage, and SYSCLK is running,
prior to VDD ramping up to the 0.5 Volt level. The running system clock should have a
minimum frequency of 800HZ and a maximum frequency no greater than the supported
maximum system clock frequency as in Table 14 table.
This figure provides the PROG_SFP timing diagram.

Fuse programming
10% PROG_SFP 10% PROG_SFP

PROG_SFP
90% VDD
tPROG_SFP_VDD
VDD
90% OVDD tPROG_SFP_PROG 90% OVDD

PORESET_B
tPROG_SFP_DELAY tPROG_SFP_RST
NOTE: PROG_SFP must be stable at 1.8 V prior to initiating fuse programming.
Figure 8. PROG_SFP timing diagram
This table provides information on the power-down and power-up sequence parameters
for PROG_SFP.
Table 5. PROG_SFP timing 5
Driver type Min Max Unit Notes
tPROG_SFP_DELAY 100 - SYSCLKs 1
tPROG_SFP_PROG 0 - μs 2
tPROG_SFP_VDD 0 - μs 3
tPROG_SFP_RST 0 - μs 4
1. Delay required from the deassertion of PORESET_B to driving PROG_SFP ramp up. Delay measured from PORESET_B
deassertion at 90% OVDD to 10% PROG_SFP ramp up.
2. Delay required from fuse programming finished to PROG_SFP ramp down start. Fuse programming must complete while
PROG_SFP is stable at 1.8 V. No activity other than that required for secure boot fuse programming is permitted while
PROG_SFP driven to any voltage above GND, including the reading of the fuse block. The reading of the fuse block may
only occur while PROG_SFP = GND. After fuse programming is completed, it is required to return PROG_SFP = GND.
3. Delay required from PROG_SFP ramp down complete to VDD ramp down start. PROG_SFP must be grounded to
minimum 10% PROG_SFP before VDD is at 90% VDD.
4. Delay required from PROG_SFP ramp down complete to PORESET_B assertion. PROG_SFP must be grounded to
minimum 10% PROG_SFP before PORESET_B assertion reaches 90% OVDD.
5. Only two secure boot fuse programming events are permitted per lifetime of a device.
Warning
PROG_SFP ramp up slew rate must not exceed 25kV/s. Ramp
down does not have a slew rate constraint.
3.3 Power-down requirements

The power-down cycle must complete such that power supply values are below 0.4 V
before a new power-up cycle can be started.

If performing secure boot fuse programming per Power sequencing, it is required that
PROG_SFP = GND before the system is power cycled (PORESET_B assertion) or
powered down (VDD ramp down) per the required timing specified in Table 5.
NOTE
All input signals, including I/Os that are configured as inputs,
driven into the chip need to monotonically increase/decrease
through entire rise/fall durations.
3.4 Power characteristics

This table shows the power dissipations of the VDD and SnVDD supply for various
operating platform clock frequencies versus the core and DDR clock frequencies when
Altivec power is gated off. See the e6500 core reference manual, section 8.6.1, "Altivec
Power Down - Software Controlled Entry" for details on how to place Altivec in low
power state.
Table 6. T4240 Power dissipation for rev 2 silicon with Altivec power-gated off1
Power Core Plat DDR PME/FM VDD8 SnVDD Junction VDD VDD SnVDD Notes
mode freq freq data freq (MHz) (V) temp. (ºC) (Core + (Core +
(V) power
(MHz) (MHz) rate Platform) Platfor
(W)9
(MT/s) + SVDD m)
Power Power
(W)1
Typical 1500 667 1600 500/667 VID 1.0 65 32 29.7 2.3 2, 3
Thermal 105 42 39.7 2.3 4, 5
Maximum 50 47.7 2.3 5, 6, 7
Typical 1667 733 1866 550/733 VID 1.0 65 35 32.7 2.3 2, 3
Thermal 105 52 49.7 2.3 4, 5
Maximum 61 58.7 2.3 5, 6, 7
Typical 1800 733 1866 550/733 VID 1.0 65 38 35.7 2.3 2, 3
Thermal 105 54 51.7 2.3 4, 5
Maximum 64 61.7 2.3 5, 6, 7
Notes:
1. Combined power of VDD and SnVDD with platform at power-on reset default state, all DDR controllers and all SerDes banks
active. Does not include I/O power and Altivec is power-gated off.
2. Typical power assumes Dhrystone running with activity factor of 60% (on all cores) and is executing DMA on the platform
with 100% activity factor.
3. Typical power based on nominal process distribution for this device.
4. Thermal power assumes Dhrystone running with activity factor of 60% (on all cores) and executing DMA on the platform at
100% activity factor.
5. Thermal and maximum power are based on worst-case process distribution for this device.

(V) power
(W)9
(MT/s) + SVDD m)
Power Power
(W)1
6. Maximum power assumes Dhrystone running with activity factor at 100% (on all cores) and is executing DMA on the
platform at 115% activity factor.
7. Maximum power provided for power supply design sizing.
8. Voltage ID (VID) operating range is between 0.975 V to 1.025 V.
9. Total SnVDD Power Conditions (S1,S2,S3,S4). This represents the highest possible power at 105ºC based upon worst-
case voltage tolerances and data patterns. Use the equations in Table 9 for average power at 105ºC.
a- SerDes1: 2 lanes @ 10.3125 G, 6 lanes @ 3.125 G.
b- SerDes2: 2 lanes @ 10.3125 G, 6 lanes @ 3.125 G.
c- SerDes3: 8 lanes @ 10.3125 G.
d- SerDes4: 4 lanes @ 10 G, 4 lanes @ 5 G.
(V) power
(W)9
(MT/s) + SVDD m)
Power Power
(W)1
Typical 1500 667 1600 500/667 VID 1.0 65 29.1 26.8 2.3 2, 3
Thermal 105 37.5 35.2 2.3 4, 5
Maximum 45.2 42.9 2.3 5, 6, 7
Typical 1667 733 1866 550/733 VID 1.0 65 32.2 29.9 2.3 2, 3
Thermal 105 43.7 41.4 2.3 4, 5
Maximum 52.5 50.2 2.3 5, 6, 7
Typical 1800 733 1866 550/733 VID 1.0 65 34.1 31.8 2.3 2, 3
Thermal 105 45.1 42.8 2.3 4, 5
Maximum 54.6 52.3 2.3 5, 6, 7
Notes:
active. Does not include I/O power and Altivec is power-gated off.
2. Typical power assumes Dhrystone running with activity factor of 60% (on all cores) and is executing DMA on the platform
with 100% activity factor.
4. Thermal power assumes Dhrystone running with activity factor of 60% (on all cores) and executing DMA on the platform at
100% activity factor.

(V) power
(W)9
(MT/s) + SVDD m)
Power Power
(W)1
6. Maximum power assumes Dhrystone running with activity factor at 100% (on all cores) and is executing DMA on the
platform at 115% activity factor.
a- SerDes1: 2 lanes @ 10.3125 G, 6 lanes @ 3.125 G.
b- SerDes2: 2 lanes @ 10.3125 G, 6 lanes @ 3.125 G.
c- SerDes3: 8 lanes @ 10.3125 G.
d- SerDes4: 4 lanes @ 10 G, 4 lanes @ 5 G.
This table shows the power dissipations of the VDD and SnVDD supplies for various
operating platform clock frequencies versus the core and DDR clock frequencies when
Altivec power is on.
Table 8. T4240 Power dissipation for rev 2 silicon with Altivec enabled1
Power Core Plat DDR PME VDD8 SnVDD Junction VDD(Cor VDD SnVDD Notes
mode freq freq data (V) temp. (ºC) e+ (Core+
/FM freq (V) power
(MHz) (MHz) rate Platform) Platform
(MHz) (W)9
(MT/s) + SVDD ) power
(W)1
Typical 1500 667 1600 500/667 VID 1.0 65 35 32.7 2.3 2, 3
Thermal 105 45 42.7 2.3 4, 5
Maximum 53 50.7 2.3 5, 6, 7
Typical 1667 733 1866 550/733 VID 1.0 65 38 35.7 2.3 2, 3
Thermal 105 55 52.7 2.3 4, 5
Maximum 64 61.7 2.3 5, 6, 7
Typical 1800 733 1866 550/733 VID 1.0 65 41 38.7 2.3 2, 3
Thermal 105 57 54.7 2.3 4, 5
Maximum 66 63.7 2.3 5, 6, 7
Notes:
active. Does not include I/O power.
2. Typical power assumes Altivec benchmark running (on all cores) and is executing DMA on the platform with 100% activity
factor.

/FM freq (V) power
(MHz) (W)9
(W)1
4. Thermal power assumes Altivec benchmark running with work power activity factor of 100% (on all cores) and executing
DMA on the platform at 100% activity factor.
6. Maximum power assumes Altivec benchmark running with work power activity factor at 100% (on all cores) and is
executing DMA on the platform at 115% activity factor.
a- SerDes1: 2-lanes @ 10.3125 G, 6-lanes SGMII @ 3.125 G.
b- SerDes2: 2-lanes @ 10.3125 G, 6-lanes SGMII @ 3.125 G.
c- SerDes3: 8-lanes @ 10.3125 G.
d- SerDes4: 4-lanes @ 10 G, 4-lanes @ 5 G.
/FM freq (V) power
(MHz) (W)9
(W)1
Typical 1500 667 1600 500/667 VID 1.0 65 31.5 29.2 2.3 2, 3
Thermal 105 40.4 38.1 2.3 4, 5
Maximum 48.1 45.8 2.3 5, 6, 7
Typical 1667 733 1866 550/733 VID 1.0 65 34.9 32.6 2.3 2, 3
Thermal 105 47.1 44.8 2.3 4, 5
Maximum 55.9 53.6 2.3 5, 6, 7
Typical 1800 733 1866 550/733 VID 1.0 65 37.0 34.7 2.3 2, 3
Thermal 105 48.7 46.4 2.3 4, 5
Maximum 58.2 55.9 2.3 5, 6, 7
Notes:
active. Does not include I/O power.
2. Typical power assumes Altivec benchmark running (on all cores) and is executing DMA on the platform with 100% activity
factor.
4. Thermal power assumes Altivec benchmark running with work power activity factor of 100% (on all cores) and executing
DMA on the platform at 100% activity factor.

/FM freq (V) power
(MHz) (W)9
(W)1
6. Maximum power assumes Altivec benchmark running with work power activity factor at 100% (on all cores) and is
executing DMA on the platform at 115% activity factor.
a- SerDes1: 2-lanes @ 10.3125 G, 6-lanes SGMII @ 3.125 G.
b- SerDes2: 2-lanes @ 10.3125 G, 6-lanes SGMII @ 3.125 G.
c- SerDes3: 8-lanes @ 10.3125 G.
d- SerDes4: 4-lanes @ 10 G, 4-lanes @ 5 G.
This table provides low power mode saving estimation.

Table 10. T4240/T4160/T4080 rev 2 single core, single cluster low power mode power
savings, 1.0 V 1,2,3,7
Mode Temp Core Core Core Units Comment Notes
Freque Frequency = Frequency =
ncy = 1.667 GHz 1.5 GHz
1.8 GHz
PH10 65°C 0.95 0.88 0.79 Watts Saving realized 4
moving from PH00
to PH10 state,
single core.
PH15 65°C 0.27 0.25 0.22 Watts Saving realized 4,5
moving from PH10
state to PH15
state, single core.
PH20 65°C 0.33 0.33 0.33 Watts Saving realized 4
moving from PH15
to PH20 state,
single core.
PCL10 65°C 0.9 0.9 0.9 Watts Saving realized 6
moving from PH20
to PCL10 for single
cluster.
LPM20 (T4080) 65°C 1.2 1.2 1.0 Watts Saving realized 6
moving from
PCL10 to LPM20.
moving from
PCL10 to LPM20.

Table 10. T4240/T4160/T4080 rev 2 single core, single cluster low power mode power
savings, 1.0 V 1,2,3,7 (continued)
Mode Temp Core Core Core Units Comment Notes
Freque Frequency = Frequency =
ncy = 1.667 GHz 1.5 GHz
1.8 GHz
moving from
PCL10 to LPM20.
LPM40 65°C 1.33 1.33 0.83 Watts Saving realized 6
moving from
LPM20 to LPM40.
Notes:
1. Power for VDD only.
2. Typical power assumes Dhrystone running (PH00 state) with activity factor of 60%.
4. PH10, PH15, PH20 power savings with one core. Maximum savings would be N times, where N is the number of used
cores.
5. Require both threads of the core to enter the same low-power mode.
6. See the e6500 reference manual and the T4240 reference manual for additional low power mode details.
7. Also applicable for lower power T4241 devices.
This table provides all the estimated I/O power supply values based on preliminary
measurements.
Table 11. T4240/T4241 I/O power dissipation
I/O Power Supply Used in Parameter Typical (mW) Maximum Notes
(mw)
LVCMOS OVDD 1.8 V eSHDC, eSPI, DMA, — 140 — 1, 3, 4, 5
MPIC, GPIO
management,
clocking, debug, IFC,
DDRCLK supply, and
JTAG
LVCMOS LVDD 1.8 V Ethernet, Ethernet — 122 —
management
interface 1 (EMI1),
1588, GPIO
LVCMOS LVDD 2.5 V Ethernet, Ethernet — 198 —
management
interface 1 (EMI1),
1588, GPIO
LVCMOS DVDD 1.8 V DUART, I 2 C — 12 —
LVCMOS DVDD 2.5 V DUART, I 2 C — 17 —
LVCMOS PROG_SFP 1.8V Fuse programming — 200 —

Table 11. T4240/T4241 I/O power dissipation (continued)

(mw)
LVCMOS VDD_LP 1 V Low Power Security — 8 —
Monitor
DDR I/O GVDD 1.5 V All three DDR 1866 MT/s 3500 5000 1, 2, 5
controllers
DDR I/O GVDD 1.5 V All three DDR 1600 MT/s 3100 4900
controllers
DDR I/O Dn_MV_REF DDR3 and DDR3L — — — —
DRAM reference
USB_PHY USB_OVDD 1.8 V USB PHY — 54 — 1, 5
Transceiver supply
voltage
USB_PHY USB_HVDD 3.3 V USB PHY — 59 —
Transceiver supply
voltage
USB_PHY USB_SVDD 1 V USB PHY Analog — 6 —
supply voltage
PLL AVDD _CGAn 1.8 PLL of core and — 15 for each — 1, 5
V system
AVDD _CGBn 1.8
V
AVDD _PLAT 1.8
V
PLL_DDR AVDD_Dn 1.8 V PLL of DDR — 15 —
PLL_SerDes AVDD PLL of SerDes — 60 —
_SDn_PLLn 1.5
V or 1.35 V
SerDes, 1.35 Pad power SVDD Fi = Lane data P_ SVDD = — 6
XVDD, 1.0 V supply for single rate in Gbps 155.047 +
SVDD SerDes module's 16.766 * N +
N = Total
receivers 3.287 * (Sum(ni
number of lanes
* Fi)) ± 15 mW
used
ni = number of
lanes running at
Fi rate
SerDes, 1.35 Pad power XVDD Fi = Lane data P_ XVDD = — 6
XVDD, 1.0 V supply for single rate in Gbps 53.256 + 50.685
SVDD SerDes module's * N + 0.683 *
N = Total
transmitters (Sum(ni * Fi)) ±
number of lanes
15 mW
used
ni = number of
lanes running at
Fi rate
Notes:

Table 11. T4240/T4241 I/O power dissipation

(mw)
1. The maximum values are dependent on actual use case such as what application, external components used,
environmental conditions such as temperature, voltage and frequency. This is not intended to be the maximum guaranteed
power. Expect different results depending on the use case. The maximum values are estimated and they are based on
simulations at 105 °C junction temperature.
2. Typical DDR power numbers are based on one 2-rank DIMM with 20% utilization, while maximum assumes 40% utilization
of bus. These values are good for thermal design but for supply design it should be assumed 100% utilization of bus where
DDR I/O power can be up to 9.6 Watts for the three controllers in T4240. Writes at 60 Ω ODT & full.
3. Assuming 15 pF total capacitance load.
4. GPIOs are supported on 1.8 V and 2.5 V rails as specified in the hardware specification.
5. The typical values are estimates and based on measurements at nominal recommended voltage for the I/O power supply
and assuming at 65° C junction temperature.
6. The total power numbers of XVDD and SVDD depend on the customer's application usecase. Power formulas assume 105°
C junction temperature. If one PLL is used, then subtract 60 mW from the resulting P_ SVDD. The following examples show
how to use the formulas in estimating P_ SVDD and P_ XVDD for different SerDes usecases.
Example 1:
On a SerDes block running SGMII at 3.125 Gbps on one lane, the SerDes typical powers are expected to be:
P_ SVDD = 155.047 + 16.766 * 1 + 3.287 *(1 * 3.125) ± 15 mW - (60 mW "because one PLL is used" ) = 122 mW ± 15 mW
P_ XVDD = 53.256 + 50.685 * 1 + 0.683 * (1 * 3.125) ± 15 mW = 106 mW ± 15 mW
Example 2:
On a SerDes block running PCIe at 5 Gbps on eight lanes, the SerDes typical powers are expected to be:
P_ SVDD = 155.047 + 16.766 * 8 + 3.287 * (8 * 5) ± 15 mW - (60 mW "because one PLL is used" ) = 361 ± 15 mW
P_ XVDD = 53.256 + 50.685 * 8 + 0.683 *(8 * 5) ± 15 mW = 486 mW ± 15 mW
Example 3:
On a single SerDes block running XFI at 10.3125 Gbps on two lanes and SGMII at 3.75 G on four lanes, the single SerDes
module typical powers are expected to be:
P_ SVDD = 155.047 + 16.766 * 6 + 3.287 * (2 * 10.3125 + 4 * 3.75 ) ± 15 mW = 373 mW ± 15 mW
P_ XVDD = 53.256 + 50.685 * 6 + 0.683 * (2 * 10.3125 + 4 * 3.75) ± 15 mW = 382 mW ± 15 mW
3.5 Power-on ramp rate

This section describes the AC electrical specifications for the power-on ramp rate
requirements. Controlling the maximum power-on ramp rate is required to avoid excess
in-rush current.
This table provides the power supply ramp rate specifications.

Table 12. Power supply ramp rate

Parameter Min Max Unit Notes
Required ramp rate for all voltage supplies (including OVDD/DVDD/ GnVDD/ - 25 V/ms 1, 2
SnVDD/XnVDD/LVDD, all core and platform VDD supplies, Dn_MVREF and all AVDD
supplies.)
Required ramp rate for PROG_SFP - 25 V/ms 1, 2
Note:
1. Ramp rate is specified as a linear ramp from 10 to 90%. If non-linear (for example, exponential), the maximum rate of
change from 200 to 500 mV is the most critical as this range might falsely trigger the ESD circuitry.
2. Over full recommended operating temperature range (see Table 3).
3.6 Input clocks
3.6.1 System clock (SYSCLK) and real-time clock (RTC) timing

specifications
This section provides the system clock and real-time clock DC and AC timing
specifications.
3.6.1.1 SYSCLK and RTC DC timing specifications

This table provides the SYSCLK and RTC DC specifications.
Table 13. SYSCLK and RTC DC electrical characteristics3
Parameter Symbol Min Typical Max Unit Notes
Input high voltage VIH 1.25 — — V 1
Input low voltage VIL — — 0.6 V 1
Input capacitance (SYSCLK) CIN — 3.3 — pF —
Input capacitance (RTC) CIN — 2.6 — pF —

Input current (OVIN = 0 V or OVIN = IIN -50 — 50 μA 2
OVDD)
Note:
1. The min VILand max VIH values are based on the respective min and max OVIN values found in Table 3.
2. The symbol OVIN, in this case, represents the OVIN symbol referenced in Recommended operating conditions.
3. At recommended operating conditions with OVDD = 1.8 V, see Table 3.

3.6.1.2 SYSCLK and RTC AC timing specifications

This table provides the SYSCLK AC timing specifications.
Table 14. SYSCLK AC timing specifications5
Parameter/Condition Symbol Min Typ Max Unit Notes
SYSCLK frequency fSYSCLK 66.7 — 133.3 MHz 1, 2
SYSCLK cycle time tSYSCLK 7.5 — 15 ns 1, 2
SYSCLK duty cycle tKHK / tSYSCLK 40 — 60 % 2
SYSCLK slew rate — 1 — 4 V/ns 3
SYSCLK peak period jitter — — — ± 150 ps —
SYSCLK jitter phase noise at -56 dBc — — — 500 KHz 4
AC Input Swing voltage ΔVAC 0.6 x OVDD — 1 x OVDD V 6
Notes:
1. Caution: The relevant clock ratio settings must be chosen such that the resulting SYSCLK frequency do not exceed their
respective maximum or minimum operating frequencies.
2. Measured at the rising edge and/or the falling edge at OVDD/2.
3. Slew rate as measured from 0.35 x OVDD to 0.65 x OVDD.
4. Phase noise is calculated as FFT of TIE jitter.
5. At recommended operating conditions with OVDD = 1.8V, see Table 3.
6. AC swing measured relative to half OVDD or VIH and VIL have equal absolute offset from OVDD /2, So, Swing = (VIH-VIL)/
OVDD and ΔVAC = Swing x OVDD
This table provides the RTC AC timing specifications.

Table 15. RTC AC timing specifications5
RTC frequency fRTC — platform MHz 1, 2
clock/16
RTC cycle time tRTC 16/platform — — ns 1, 2
clock
RTC duty cycle tKHK / tRTC 40 — 60 % 2
RTC slew rate — 1 — 4 V/ns 3
RTC peak period jitter — — — ± 150 ps —
RTC jitter phase noise at -56 dBc — — — 500 KHz 4
AC Input Swing voltage ΔVAC 0.6 x OVDD — 1 x OVDD V 6
Notes:
1. Caution: The relevant clock ratio settings must be chosen such that it fits IEEE1588, or MPIC, or RCPM requirements.

Table 15. RTC AC timing specifications5

OVDD and ΔVAC = Swing x OVDD
3.6.2 Spread-spectrum sources

Spread-spectrum clock sources are an increasingly popular way to control
electromagnetic interference emissions (EMI) by spreading the emitted noise to a wider
spectrum and reducing the peak noise magnitude in order to meet industry and
government requirements. These clock sources intentionally add long-term jitter to
diffuse the EMI spectral content. The jitter specification given in this table considers
short-term (cycle-to-cycle) jitter only. The clock generator's cycle-to-cycle output jitter
should meet the chip's input cycle-to-cycle jitter requirement. Frequency modulation and
spread are separate concerns; the chip is compatible with spread-spectrum sources if the
recommendations listed in this table are observed.
Table 16. Spread-spectrum clock source recommendations3
Frequency modulation - 60 kHz -
Frequency spread - 1.0 % 1, 2
Notes:
1. SYSCLK frequencies that result from frequency spreading and the resulting core frequency must meet the minimum and
maximum specifications given in Table 14.
2. Maximum spread-spectrum frequency may not result in exceeding any maximum operating frequency of the device.
CAUTION
The processor's minimum and maximum SYSCLK and core/
platform/DDR frequencies must not be exceeded regardless of
the type of clock source. Therefore, systems in which the
processor is operated at its maximum rated core/platform/DDR
frequency should avoid violating the stated limits by using
down-spreading only.

3.6.3 Real-time clock (RTC) timing

The RTC timing input is sampled by the platform clock. The output of the sampling latch
is then used as an input to the counters of the MPIC and the time base unit of the core;
there is no need for jitter specification. The minimum period of the RTC signal should be
greater than or equal to 16x the period of the platform clock. There is no minimum RTC
frequency; RTC may be grounded if not needed.
3.6.4 Gigabit Ethernet reference clock timing

This table provides the Ethernet gigabit reference clock DC specifications.
Table 17. ECn_GTX_CLK125 DC electrical characteristics 1
Input high VIH 1.7 - - V 2
voltage
Input low VIL - - 0.7 V 2
voltage
Input CIN - - 6 pF -
capacitance
Input current IIN -50 - 50 μA 3
(LVIN = 0 V or
LVIN = LVDD)
1. At recommended operating conditions with LVDD = 2.5 V
2. The min VIL and max VIH values are based on the respective min and max LVIN values found in Table 3.
3. The symbol LVIN, in this case, represents the LVIN symbol referenced in Recommended operating conditions.
This table provides the Ethernet gigabit reference clocks AC timing specifications.
Table 18. ECn_GTX_CLK125 AC timing specifications 1
Parameter/Condition Symbol Min Typical Max Unit Notes
ECn_GTX_CLK125 frequency tG125 125 - 100 ppm 125 125 + 100 ppm MHz -
ECn_GTX_CLK125 cycle time tG125 - 8 - ns -
ECn_GTX_CLK125 rise and fall time tG125R/tG125F - - 0.75 ns 2
LVDD = 2.5 V
ECn_GTX_CLK125 duty cycle tG125H/tG125 47 - 53 % 3
1000Base-T for RGMII
ECn_GTX_CLK125 jitter - - - ± 150 ps 3
1. At recommended operating conditions with LVDD = 2.5 V ± 125 mV.
2. Rise and fall times for ECn_GTX_CLK125 are measured from 0.5 and 2.0 V for LVDD = 2.5 V.
3. ECn_GTX_CLK125 is used to generate the GTX clock for the Ethernet transmitter with 2% degradation. The
ECn_GTX_CLK125 duty cycle can be loosened from 47%/53% as long as the PHY device can tolerate the duty cycle
generated by the GTX_CLK. See RGMII AC timing specifications for duty cycle for 10Base-T and 100Base-T reference clock.

3.6.5 DDR clock timing

This section provides the DDR clock DC and AC timing specifications.
3.6.5.1 DDR clock DC timing specifications

This table provides the DDR clock (DDRCLK) DC specifications.
Table 19. DDRCLK DC electrical characteristics3
Input high voltage VIH 1.25 - - V 1
Input low voltage VIL - - 0.6 V 1
Input capacitance CIN - 11 pF -
Input current (OVIN= 0 V or OVIN = IIN -50 - 50 μA 2
OVDD)
Note:
2. The symbol OVIN, in this case, represents the OVIN symbol referenced in Recommended operating conditions.
3.6.5.2 DDR clock AC timing specifications

This table provides the DDR clock (DDRCLK) AC timing specifications.
Table 20. DDRCLK AC timing specifications5
DDRCLK frequency fDDRCLK 66.7 - 133.3 MHz 1, 2
DDRCLK cycle time tDDRCLK 7.5 - 15 ns 1, 2
DDRCLK duty cycle tKHK / tDDRCLK 40 - 60 % 2
DDRCLK slew rate - 1 - 4 V/ns 3
DDRCLK peak period jitter - - - ± 150 ps -
DDRCLK jitter phase noise at -56 dBc - - - 500 KHz 4
AC Input Swing voltage ΔVAC 0.6 x OVDD - 1 x OVDD V 6
Notes:
1. Caution: The relevant clock ratio settings must be chosen such that the resulting DDRCLK frequency do not exceed their
respective maximum or minimum operating frequencies.

Table 20. DDRCLK AC timing specifications5

OVDD and ΔVAC = Swing x OVDD .
3.6.6 Other input clocks

A description of the overall clocking of this device is available in the chip reference
manual in the form of a clock subsystem block diagram. For information about the input
clock requirements of functional modules sourced external of the chip, such as SerDes,
Ethernet management, eSDHC, IFC, see the specific interface section.
3.7 RESET initialization

This section describes the AC electrical specifications for the RESET initialization timing
requirements. This table describes the AC electrical specifications for the RESET
initialization timing.
Table 21. RESET Initialization timing specifications
Parameter/Condition Min Max Unit Notes
Required assertion time of PORESET_B 1 - ms 1
Required input assertion time of HRESET_B 32 - SYSCLKs 2, 3
Maximum rise/fall time of PORESET_B signal - 1 SYSCLK 4
Maximum rise/fall time of HRESET_B signal - 4 SYSCLK 4

PLL input setup time with stable SYSCLK before HRESET_B negation 100 - μs -
Input setup time for POR configs with respect to negation of 4 - SYSCLKs 2
PORESET_B
Input hold time for all POR configs with respect to negation of 2 - SYSCLKs 2
PORESET_B
Maximum valid-to-high impedance time for actively driven POR - 5 SYSCLKs 2
configs with respect to negation of PORESET_B
1. PORESET_B must be driven asserted before the core and platform power supplies are powered up.
2. SYSCLK is the primary clock input for the chip.
3. The device asserts HRESET_B as an output when PORESET_B is asserted to initiate the power-on reset process. The
device releases HRESET_B sometime after PORESET_B is deasserted. The exact sequencing of HRESET_B deassertion is
documented in section "Power-On Reset Sequence" in the chip reference manual.

Table 21. RESET Initialization timing specifications

4. System/board must be designed to ensure the input requirement to the device is achieved. Proper device operation is
guaranteed for inputs meeting this requirement by design, simulation, characterization, or functional testing. For example On
table 1, notes 6 and 7, recommends a week pull up resistor for HRESET signal pin in the range of 2K to 10K Ohms, But PCB
designers have to reduce the pull up resistor ( min of 280 Ohms) or in addition use bidirectional level shifter to comply with
maximum rise/fall time requirement for HRESET if this pin is too loaded.
This table provides the PLL lock times.

Table 22. PLL lock times
PLL lock times (Core, platform, DDR only) - 100 μs -
3.8 DDR3 and DDR3L SDRAM controller

This section describes the DC and AC electrical specifications for the DDR3 and DDR3L
SDRAM controller interface. Note that the required GVDD(typ) voltage is 1.5 V when
interfacing to DDR3 SDRAM and the GVDD(typ) voltage is 1.35 V when interfacing to
DDR3L SDRAM.
NOTE
When operating at a DDR data rate of 1866 MT/s, only one
dual-ranked module per memory controller is supported.
3.8.1 DDR3 and DDR3L SDRAM interface DC electrical

characteristics
This table provides the recommended operating conditions for the DDR SDRAM
controller when interfacing to DDR3 SDRAM.
Table 23. DDR3 SDRAM interface DC electrical characteristics (GVDD = 1.5 V)1, 7
Parameter Symbol Min Max Unit Note
I/O reference voltage Dn_MVREF 0.49 x GVDD 0.51 x GVDD V 2, 3, 4
Input high voltage VIH Dn_MVREF + 0.100 GVDD V 5
Input low voltage VIL GND Dn_MVREF - 0.100 V 5
I/O leakage current IOZ -100 100 μA 6
Notes:

Table 23. DDR3 SDRAM interface DC electrical characteristics (GVDD = 1.5 V)1, 7
1. GVDD is expected to be within 50 mV of the DRAM's voltage supply at all times. The DRAM's and memory controller's
voltage supply may or may not be from the same source.
2. Dn_MVREF is expected to be equal to 0.5 x GVDD and to track GVDD DC variations as measured at the receiver. Peak-to-
peak noise on Dn_MVREF may not exceed the Dn_MVREF DC level by more than ±1% of GVDD(i.e. ±15 mV).
3. VTT is not applied directly to the device. It is the supply to which far end signal termination is made, and it is expected to be
equal to Dn_MVREF with a min value of Dn_MVREF - 0.04 and a max value of Dn_MVREF + 0.04. VTT should track variations in
the DC level of Dn_MVREF.
4. The voltage regulator for Dn_MVREF must meet the specifications stated in Table 25.
5. Input capacitance load for DQ, DQS, and DQS_B are available in the IBIS models.
6. Output leakage is measured with all outputs disabled, 0 V ≤ VOUT ≤ GVDD.
7. For recommended operating conditions, see Table 3.
This table provides the recommended operating conditions for the DDR SDRAM
controller when interfacing to DDR3L SDRAM.
Table 24. DDR3L SDRAM interface DC electrical characteristics (GVDD = 1.35 V)1, 7
I/O reference voltage Dn_MVREF 0.49 x GVDD 0.51 x GVDD V 2, 3, 4
Input high voltage VIH Dn_MVREF + 0.090 GVDD V 5
Input low voltage VIL GND Dn_MVREF - 0.090 V 5
I/O leakage current IOZ -100 100 μA 6
Notes:
1. GVDD is expected to be within 50 mV of the DRAM's voltage supply at all times. The DRAM's and memory controller's
voltage supply may or may not be from the same source.
2. Dn_MVREF is expected to be equal to 0.5 x GVDD and to track GVDD DC variations as measured at the receiver. Peak-to-
peak noise on Dn_MVREF may not exceed the Dn_MVREF DC level by more than ±1% of GVDD (i.e. ±13.5mV).
3. VTT is not applied directly to the device. It is the supply to which far end signal termination is made, and it is expected to be
equal to Dn_MVREF with a min value of Dn_MVREF - 0.04 and a max value of Dn_MVREF + 0.04. VTT should track variations in
the DC level of Dn_MVREF.
4. The voltage regulator for Dn_MVREF must meet the specifications stated in Table 25.
5. Input capacitance load for DQ, DQS, and DQS_B are available in the IBIS models.
6. Output leakage is measured with all outputs disabled, 0 V ≤ VOUT ≤ GVDD.
This table provides the current draw characteristics for Dn_MVREF.

Table 25. Current draw characteristics for Dn_MVREF1

Parameter Symbol Min Max Unit Notes
Current draw for DDR3 SDRAM for IDn_MVREF - 500 μA -
Dn_MVREF
Current draw for DDR3L SDRAM for IDn_MVREF - 500 μA -
Dn_MVREF
Note:
3.8.2 DDR3 and DDR3L SDRAM interface AC timing specifications

This section provides the AC timing specifications for the DDR SDRAM controller
interface. The DDR controller supports DDR3 and DDR3L memories. Note that the
required GVDD(typ) voltage is 1.5 V when interfacing to DDR3 SDRAM and the
required GVDD(typ) voltage is 1.35 V when interfacing to DDR3L SDRAM.
3.8.2.1 DDR3 and DDR3L SDRAM interface input AC timing specifications

This table provides the input AC timing specifications for the DDR controller when
interfacing to DDR3 SDRAM.
Table 26. DDR3 and DDR3L SDRAM interface input AC timing specifications3
Controller Skew for MDQS-MDQ/MECC tCISKEW ps 1
1866 MT/s data rate -93 93
1600 MT/s data rate -112 112
1333 MT/s data rate -125 125
1200 MT/s data rate -142 142
1066 MT/s data rate -170 170
Tolerated Skew for MDQS-MDQ/MECC tDISKEW ps 2
1866 MT/s data rate -175 175
1600 MT/s data rate -200 200
1333 MT/s data rate -250 250
1200 MT/s data rate -275 275
1066 MT/s data rate -300 300
1. tCISKEW represents the total amount of skew consumed by the controller between MDQS[n] and any corresponding bit that
is captured with MDQS[n]. This must be subtracted from the total timing budget.
2. The amount of skew that can be tolerated from MDQS to a corresponding MDQ signal is called tDISKEW.This can be
determined by the following equation: tDISKEW = ±(T ÷ 4 - abs(tCISKEW)) where T is the clock period and abs(tCISKEW) is the
absolute value of tCISKEW.

This figure shows the DDR3 and DDR3L SDRAM interface input timing diagram.
MCK[n]_B
MCK[n]
tMCK
MDQS[n]
tDISKEW
MDQ[x] D0 D1
tDISKEW
tDISKEW
Figure 9. DDR3 and DDR3L SDRAM Interface Input Timing Diagram
3.8.2.2 DDR3 and DDR3L SDRAM interface output AC timing

specifications
This table contains the output AC timing targets for the DDR3 SDRAM interface.
Table 27. DDR3 and DDR3L SDRAM interface output AC timing specifications7
Parameter Symbol1 Min Max Unit Notes
MCK[n] cycle time tMCK 0.938 2 ns 2
ADDR/CMD output setup with respect to MCK tDDKHAS ns 3
1866 MT/s data rate 0.410 -
ADDR/CMD output hold with respect to MCK tDDKHAX ns 3
1866MT/s data rate 0.390 -

Table 27. DDR3 and DDR3L SDRAM interface output AC timing specifications7 (continued)
Parameter Symbol1 Min Max Unit Notes
MCK to MDQS Skew tDDKHMH ns 4
> 1600 MT/s data rate -0.150 0.150 4, 6
> 1066 MT/s data rate, ≤ 1600 MT/s data rate -0.245 0.245 4, 6
MDQ/MECC/MDM output Data eye tDDKXDEYE ns 5
MDQS preamble tDDKHMP 0.9 x tMCK - ns -
MDQS postamble tDDKHME 0.4 x tMCK 0.6 x tMCK ns -
1. The symbols used for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state) (reference)(state) for
inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. Output hold time can be read as DDR timing (DD)
from the rising or falling edge of the reference clock (KH or KL) until the output went invalid (AX or DX). For example, tDDKHAS
symbolizes DDR timing (DD) for the time tMCK memory clock reference (K) goes from the high (H) state until outputs (A) are
setup (S) or output valid time.
2. All MCK/MCK_B and MDQS/MDQS_B referenced measurements are made from the crossing of the two signals.
3. ADDR/CMD includes all DDR SDRAM output signals except MCK/MCK_B, MCS_B, and MDQ/MECC/MDM/MDQS.
4. Note that tDDKHMH follows the symbol conventions described in note 1. For example, tDDKHMH describes the DDR timing
(DD) from the rising edge of the MCK[n] clock (KH) until the MDQS signal is valid (MH). tDDKHMH can be modified through
control of the MDQS override bits (called WR_DATA_DELAY) in the TIMING_CFG_2 register. This is typically set to the
same delay as in DDR_SDRAM_CLK_CNTL[CLK_ADJUST]. The timing parameters listed in the table assume that these two
parameters have been set to the same adjustment value. See the chip reference manual for a description and explanation of
the timing modifications enabled by the use of these bits.
5. Available eye for data (MDQ), ECC (MECC), and data mask (MDM) outputs at the pin of the processor. Memory controller
will center the strobe (MDQS) in the available data eye at the DRAM (end point) during the initialization.
6. Note that for data rates of 1200 MT/s or higher, it is required to program the start value of the DQS adjust for write leveling.
NOTE
For the ADDR/CMD setup and hold specifications in Table 27,
it is assumed that the clock control register is set to adjust the
memory clocks by ½ applied cycle.
This figure shows the DDR3 and DDR3L SDRAM interface output timing for the MCK
to MDQS skew measurement (tDDKHMH).

MCK[n]_B
MCK[n]
tMCK
tDDKHMH(max)
MDQS
tDDKHMH(min)
MDQS
Figure 10. tDDKHMH timing diagram
This figure shows the DDR3 and DDR3L SDRAM output timing diagram.

MCK_B
MCK
tMCK
tDDKHAS
tDDKHAX
ADDR/CMD Write A0 NOOP
tDDKHMP
tDDKHMH
MDQS[n]
tDDKHME
MDQ[x] D0 D1
tDDKXDEYE
tDDKXDEYE
Figure 11. DDR3 and DDR3L output timing diagram
3.9 eSPI interface

This section describes the DC and AC electrical specifications for the eSPI interface.
3.9.1 eSPI DC electrical characteristics

This table provides the DC electrical characteristics for the eSPI interface operating at
OVDD = 1.8 V.
Table 28. eSPI DC electrical characteristics (1.8 V)3
Input high voltage VIH 1.25 - V 1
Input low voltage VIL - 0.6 V 1
Input current (VIN = 0 V or VIN = OVDD) IIN -50 50 μA 2
Output high voltage VOH 1.35 - V -

Table 28. eSPI DC electrical characteristics (1.8 V)3 (continued)

(OVDD = min, IOH = -0.5 mA)
Output low voltage VOL - 0.4 V -
(OVDD = min, IOL = 0.5 mA)
Notes:
2. The symbol VIN, in this case, represents the OVIN symbol referenced in Recommended operating conditions.
3.9.2 eSPI AC timing specifications

This table provides the eSPI input and output AC timing specifications.
Table 29. eSPI AC timing specifications3
Parameter/Condition Symbol 2 Min Max Unit Notes
SPI_MOSI output-Master data (internal clock) tNIKHOX n1 + ( tPLATFORM_CLK * - ns 1, 2, 4
hold time SPMODE[HO_ADJ])
SPI_MOSI output-Master data (internal clock) tNIKHOV - n2 + ( tPLATFORM_CLK * ns 1, 2, 4
delay SPMODE[HO_ADJ])
SPI_CS outputs-Master data (internal clock) tNIKHOX2 0 - ns 1
hold time
SPI_CS outputs-Master data (internal clock) tNIKHOV2 - 6.0 ns 1
delay
SPI inputs-Master data (internal clock) input tNIIVKH 3.0 - ns -
setup time
SPI inputs-Master data (internal clock) input tNIIXKH 0 - ns -
hold time
Clock-high time tNIKCKH 4 - ns
Clock-low time tNIKCKL 4 - ns -
Notes:
1. See the chip reference manual for details about the SPMODE register.
2. Output specifications are measured from the 50% level of the rising edge of CLKIN to the 50% level of the signal. Timings
are measured at the pin.
3. The symbols used for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state) (reference)(state) for
inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tNIKHOV symbolizes the NMSI outputs
internal timing (NI) for the time tSPI memory clock reference (K) goes from the high state (H) until outputs (O) are valid (V).
4. n1 and n2 values are -1.0 and 1.0 respectively.
This figure provides the AC test load for the eSPI.

Output Z0= 50 Ω OVDD/2
RL = 50 Ω
Figure 12. eSPI AC test load
This figure provides the eSPI clock output timing diagram.
Figure 13. eSPI clock output timing diagram
This figure represents the AC timing from Table 29 in master mode (internal clock). Note
that although the specifications generally reference the rising edge of the clock, these AC
timing diagrams also apply when the falling edge is the active edge. Also, note that the
clock edge is selectable on eSPI.
SPICLK (output)1
tNIIXKH
tNIIVKH
Input Signals:
tNIKHOX
tNIKHOV
Output Signals:
tNIKHOX2
tNIKHOV2
Output Signals:
SPI_CS[0:3] 1
Figure 14. eSPI AC timing in master mode (internal clock) diagram
1. SPICLK appears on the interface only after CS assertion.

NXP Semiconductors
Freescale Semiconductor Freescale Confidential Proprietary 3 105
Preliminary—Subject to Change Without Notice
3.10 DUART interface

This section describes the DC and AC electrical specifications for the DUART interface.
3.10.1 DUART DC electrical characteristics

This table provides the DC electrical characteristics for the DUART interface at DVDD =
2.5 V.
Table 30. DUART DC electrical characteristics(2.5 V)3
Input current (DVIN = 0 V or DVIN = DVDD) IIN -50 50 μA 2
Output high voltage (DVDD = min, IOH = -1 mA) VOH 2.0 - V -
Output low voltage (DVDD = min, IOL = 1 mA) VOL - 0.4 V -
Notes:
1. The min VILand max VIH values are based on the min and max DVIN respective values found in Table 3.
2. The symbol DVIN represents the input voltage of the supply. It is referenced in Recommended operating conditions.
This table provides the DC electrical characteristics for the DUART interface at DVDD =
1.8 V.
Table 31. DUART DC electrical characteristics(1.8 V)3
Input current (DVIN = 0 V or DVIN = DVDD) IIN -50 50 μA 2
Output high voltage (DVDD = min, IOH = -0.5 mA) VOH 1.35 - V -
Output low voltage (DVDD = min, IOL = 0.5 mA) VOL - 0.4 V -
Notes:
1. The min VILand max VIH values are based on the min and max DVIN respective values found in Table 3.
2. The symbol DVIN represents the input voltage of the supply. It is referenced in Recommended operating conditions.

3.10.2 DUART AC electrical specifications

This table provides the AC timing parameters for the DUART interface.
Table 32. DUART AC timing specifications
Parameter/Condition Value Unit Notes
Minimum baud rate fPLAT/(2 x 1,048,576) baud 1, 3
Maximum baud rate fPLAT/(2 x 16) baud 1, 2
Notes:
1. fPLAT refers to the internal platform clock.
2. The actual attainable baud rate is limited by the latency of interrupt processing.
3. The middle of a start bit is detected as the eighth sampled 0 after the 1-to-0 transition of the start bit. Subsequent bit values
are sampled each 16th sample.
3.11 Ethernet interface, Ethernet management interface 1 and 2,

IEEE Std 1588™
This section provides the AC and DC electrical characteristics for the Ethernet controller
and the Ethernet management interfaces.
3.11.1 SGMII electrical specifications

See SGMII interface.
3.11.2 RGMII electrical specifications

This section discusses the electrical characteristics for the RGMII interface.
3.11.2.1 RGMII DC electrical characteristics

This table shows the DC electrical characteristics for the RGMII interface.
Table 33. RGMII DC electrical characteristics(LVDD = 2.5 V)3
Input current (LVIN= 0 V or LVIN= LVDD) IIN -50 50 μA 2
Output high voltage (LVDD = min, IOH = -1.0 mA) VOH 2.00 LVDD + 0.3 V -

Table 33. RGMII DC electrical characteristics(LVDD = 2.5 V)3 (continued)

Output low voltage (LVDD = min, IOL = 1.0 mA) VOL GND - 0.3 0.40 V -
1. The min VILand max VIH values are based on the respective min and max LVIN values found in Table 3.
3.11.2.2 RGMII AC timing specifications

This table presents the RGMII AC timing specifications.
Table 34. RGMII AC timing specifications (LVDD = 2.5 V)8
Parameter/Condition Symbol1 Min Typ Max Unit Notes
Data to clock output skew (at transmitter) tSKRGT_TX -750 0 1250 ps 7,9
Data to clock input skew (at receiver) tSKRGT_RX 1.0 - 2.6 ns 2,10
RGMII RX_CLK Clock period duration tRGT 7.2 8.0 8.8 ns 3

Duty cycle for 10BASE-T and 100BASE-TX tRGTH/tRGT 40 50 60 % 3, 4
Duty cycle for Gigabit tRGTH/tRGT 45 50 55 % -
Rise time (20%-80%) tRGTR - - 0.75 ns 5, 6
Fall time (20%-80%) tRGTF - - 0.75 ns 5, 6
Notes:
1. In general, the clock reference symbol representation for this section is based on the symbols RGT to represent RGMII
timing. Note that the notation for rise (R) and fall (F) times follows the clock symbol that is being represented. For symbols
representing skews, the subscript is skew (SK) followed by the clock that is being skewed (RGT).
2. This implies that PC board design will require clocks to be routed such that an additional trace delay of greater than 1.5 ns
is added to the associated clock signal. Many PHY vendors already incorporate the necessary delay inside their device. If so,
additional PCB delay is probably not needed.
3. For 10 and 100 Mbps, tRGT scales to 400 ns ± 40 ns and 40 ns ± 4 ns, respectively.
4. Duty cycle may be stretched/shrunk during speed changes or while transitioning to a received packet's clock domains as
long as the minimum duty cycle is not violated and stretching occurs for no more than three tRGT of the lowest speed
transitioned between.
5. Applies to inputs and outputs.
6. System/board must be designed to ensure this input requirement to the chip is achieved. Proper device operation is
guaranteed for inputs meeting this requirement by design, simulation, characterization, or functional testing.
7. The frequency of ECn_RX_CLK (input) should not exceed the frequency of ECn_GTX_CLK (output) by more than 300
ppm.
9. IEEE spec mandates tSKRGT_TX = +- 0.5ns. Per erratum A-005177 we see tSKRGT_TX has a wider output skew range
from -0.75ns to 1.25ns which is larger than the spec asks for. If can not cope with this wide skew then use RGMII at 100
Mbps or 10 Mbps (which allows larger maximum RX skews) or terminate 1000 Mbps RGMII links with PHYs that
accommodate larger RX skews or terminate to a second Rev2 device.
10. This device has better input clock to data skew tSKRGT_RX tolerance (1ns to 3.5ns) than spec (1ns to 2.6ns) requires.

This figure shows the RGMII AC timing and multiplexing diagrams.

tRGT
tRGTH
GTX_CLK
output
tSKRGT_TX tSKRGT_TX
TXD[7:4][3:0]
TXD[3:0] TXD[7:4]
output
TX_CTL
TXEN TXERR
output
RXD[7:4][3:0]
RXD[3:0] RXD[7:4]
input
RX_CTL
RXDV RXERR
input
tSKRGT_RX
tSKRGT_RX
RX_CLK
input
tRGTH
tRGT
Figure 15. RGMII AC timing and multiplexing diagrams
Warning
NXP guarantees timings generated from the MAC. Board
designers must ensure delays needed at the PHY or the MAC.
3.11.3 Ethernet management interface (EMI)

This section discusses the electrical characteristics for the EMI1 and EMI2 interfaces.
Frame Manager 2’s external GE MDIO configures external GE PHYs connected to EMI1
pins. Frame Manager 2’s external 10GE MDIO configures external XAUI, XFI and
HiGig/HiGig2 PHYs connected to EMI2 pins.
The EMI1 interface timing is compatible with IEEE Std 802.3™ clause 22 and EMI2
interface timing is compatible with IEEE Std 802.3™ clause 45. The External MDIO
interfaces on FM1 are not available for use.
3.11.3.1 Ethernet management interface 1 DC electrical characteristics

The DC electrical characteristics for EMI1_MDIO and EMI1_MDC are provided in this
section.

Table 35. Ethernet management interface 1 DC electrical characteristics (LVDD = 2.5 V)3
Input current (LVIN=0V or LVIN=LVDD) IIN -50 50 μA 2
Notes:
2. The symbol VIN, in this case, represents the LVIN symbol referenced in Recommended operating conditions.
Table 36. DC electrical characteristics (1.8 V)

Input current (LVIN= 0V or LVIN=LVDD) IIN -50 50 μA 2
Output high voltage (LVDD = min, IOH = -0.5 mA) VOH 1.35 - V -
Output low voltage (LVDD = min, IOL = 0.5 mA) VOL - 0.40 V -
Notes:
1. The min VILand max VIH values are based on the respective min and max OVIN/QVIN values found in Table 3.
3.11.3.2 Ethernet management interface 2 DC electrical characteristics

Ethernet management interface 2 pins function as open drain I/Os. The interface
conforms to 1.2 V nominal voltage levels. The DC electrical characteristics for
EMI2_MDIO and EMI2_MDC are provided in this section.
Table 37. Ethernet management interface 2 DC electrical characteristics (1.2 V)1
Input high voltage VIH 0.84 - V -
Input low voltage VIL - 0.36 V -
Output low voltage (IOL = 5.5 mA) VOL - 0.2 V -
Input capacitance CIN - 10 pF -
Notes:

3.11.3.3 Ethernet management interface 1 AC electrical specifications

This table provides the Ethernet management interface 1 AC timing specifications.
Table 38. Ethernet management interface 1 AC timing specifications6
MDC frequency (1/TMDC_ClK) fMDC — — 2.5 MHz 2
MDC clock pulse width high tMDCH 160 — — ns —
MDC to MDIO Rev1 tMDKHDX (Y x tenet_clk ) - — (Y x tenet_clk) + ns 3, 4, 5
delay 3, 3,
MDIO_CFG[
EHOLD] = 0 Y=2x Y=2x
MDIO_CFG[M MDIO_CFG[M
MDIO_CFG[
DIO_HOLD] + DIO_HOLD] +
NEG] = 0
1 1
Rev2 tMDKHDX (Y x tenet_clk) - — (Y x tenet_clk) + ns 3, 4, 5
3, 3,
MDIO_CFG[
NEG] = 0 Y=2x Y=2x
MDIO_CFG[
EHOLD] = 0
1 1
3, 3,
MDIO_CFG[
NEG] = 0 Y=8x Y=8x
MDIO_CFG[
DIO_HOLD] DIO_HOLD] +
EHOLD] = 1
+1 1
Rev2 tMDKHDX (Y x TMDC_ClK) — (Y x TMDC_ClK) ns 4
- 3, + 3,
MDIO_CFG[
NEG] = 1 Y=½ Y=½
MDIO to MDC setup time tMDDVKH 9 — — ns —
MDIO to MDC hold time tMDDXKH 0 — — ns —
Notes:
1. The symbols used for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state)(reference)(state) for
inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tMDKHDX symbolizes management
data timing (MD) for the time tMDC from clock reference (K) high (H) until data outputs (D) are invalid (X) or data hold time.
Also, tMDDVKH symbolizes management data timing (MD) with respect to the time data input signals (D) reach the valid state
(V) relative to the tMDC clock reference (K) going to the high (H) state or setup time.
2. This parameter is dependent on the Ethernet clock frequency. (MDIO_CFG [MDIO_CLK_DIV] field determines the clock
frequency of the MgmtClk Clock MDIO_MDC).
3. This parameter is dependent on the Ethernet clock frequency. The delay is equal to Y x Ethernet clock periods ± 3 ns. For
example, in default rev1 silicon, with an Ethernet clock of 400 MHz, the min/max delay is = (Y x tenet_clk) ± 3 ns = ((2 x 2 + 1) x
1/400 M) ± 3 ns = 12.5 ns ± 3 ns.
Default values for Rev 1: silicon:
• MDIO_CFG[MDIO_HOLD]= 3’b010 which selects Y = 2 x 2 + 1 = 5 tenet_clk cycles.
• MDIO_CFG[NEG] = 0, in Rev 1, NEG bit field was not visible.
• MDIO_CFG[EHOLD] = 0, in Rev 1, NEG bit field was not visible.
Default values for Rev 2 silicon:

• MDIO_CFG[MDIO_HOLD]= 3’b010, since MDIO_CFG[NEG] = 1 then Y = ½.


• MDIO_CFG[NEG] = 1
• MDIO_CFG[EHOLD] = 0
• For Rev 1 silicon: Y = 2 x MDIO_CFG[MDIO_HOLD] + 1

• For Rev 2 silicon:
• If MDIO_CFG[EHOLD] = 0 and MDIO_CFG[NEG] = 0 then Y = 2 x MDIO_CFG[MDIO_HOLD] + 1
• If MDIO_CFG[NEG] = 1 then Y = ½ . Thus, Y is not affected by MDIO_CFG[HOLD] and MDIO_CFG[EHOLD]
when MDIO_CFG[NEG] = 1. For example, in this case, if MDC clock = 2.5 MHz, then min/max of tMDKHDX delay
is = Y * TMDC_ClK ± 3 ns = ½ x 1/2.5 M ± 3 ns = 200 ns ± 3 ns.
4. tMDKHDX transition:
• For Rev 1 silcon: tMDKHDX is MDC positive edge to MDIO transition.
• If MDIO_CFG[NEG] = 0 then tMDKHDX is MDC positive edge to MDIO transition.
• If MDIO_CFG[NEG] = 1 then tMDKHDX is MDC negative edge to MDIO transition.
• The default value of MDIO_CFG [MDIO_CLK_DIV] is 0 which means no MDIO clock is available. Recommended
to configure this field in PBL.
5. tenet_clk is the Ethernet clock period derived from Frame Manager clock, FM clock. tenet_clk=1/FM_clock.
3.11.3.4 Ethernet management interface 2 AC electrical characteristics

This table provides the Ethernet management interface 2 AC timing specifications.
MDC frequency (1/TMDC_ClK ) fMDC — — 2.5 MHz 2
MDC clock pulse width high tMDCH 160 — — ns —
MDC to MDIO Rev1 tMDKHDX (Y x tenet_clk ) - — (Y x tenet_clk) + ns 3, 4, 5
delay 3, 3,
MDIO_CFG[
EHOLD] = 0 Y=2x Y=2x
MDIO_CFG[
NEG] = 0
1 1
3, 3,
MDIO_CFG[
NEG] = 0 Y=2x Y=2x
MDIO_CFG[
EHOLD] = 0
1 1
Rev2 tMDKHDX (Y x tenet_clk) - - (Y x tenet_clk) + ns 3, 4, 5
3, 3,
MDIO_CFG[
NEG] = 0

Table 39. Ethernet management interface 2 AC timing specifications6 (continued)

MDIO_CFG[ Y=8x Y=8x
EHOLD] = 1 MDIO_CFG[M MDIO_CFG[M
DIO_HOLD] + DIO_HOLD]
1 +1
Rev2 tMDKHDX (Y x TMDC_ClK) — (Y x TMDC_ClK ) ns 4
- 3, + 3,
MDIO_CFG[
NEG] = 1 Y=½ Y=½
MDIO to MDC setup time tMDDVKH 8 — — ns 7
MDIO to MDC hold time tMDDXKH 0 — — ns —
Notes:
1. The symbols used for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state)(reference)(state) for
inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tMDKHDX symbolizes management
data timing (MD) for the time tMDC from clock reference (K) high (H) until data outputs (D) are invalid (X) or data hold time.
Also, tMDDVKH symbolizes management data timing (MD) with respect to the time data input signals (D) reach the valid state
(V) relative to the tMDC clock reference (K) going to the high (H) state or setup time.
2. This parameter is dependent on the Ethernet clock frequency (MDIO_CFG [MDIO_CLK_DIV] field determines the clock
frequency of the MgmtClk Clock MDIO_MDC).
3. This parameter is dependent on the Ethernet clock frequency. The delay is equal to Y x Ethernet clock periods ± 3 ns. For
example, in default rev1 silicon, with an Ethernet clock of 400 MHz, the min/max delay is = (Y x tenet_clk) = ((2 x 2 + 1) x
1/400M) ± 3 ns = 12.5 ns ± 3 ns.
Default values for Rev 1: silicon:
• MDIO_CFG[MDIO_HOLD] = 3’b010, which selects Y = 2 x 2 + 1 = 5 tenet_clk cycles.
• MDIO_CFG[NEG] = 0, in Rev 1, NEG bit field was not visible.
• MDIO_CFG[EHOLD] = 0, in Rev 1, NEG bit field was not visible.
Default values for Rev 2 silicon:

• MDIO_CFG[MDIO_HOLD] = 3’b010, since MDIO_CFG[NEG] = 1 then Y = ½.
• MDIO_CFG[NEG] = 1
• MDIO_CFG[EHOLD] = 0
• For Rev 1 silicon: Y = 2 x MDIO_CFG[MDIO_HOLD] + 1

• If MDIO_CFG[NEG] = 1 then Y = ½ . Thus Y is not affected by MDIO_CFG[HOLD] and MDIO_CFG[EHOLD]
when MDIO_CFG[NEG]=1. For example in this case If MDC clock = 2.5 MHz, then min/max of tMDKHDX delay is =
Y * TMDC_ClK ± 3 ns = ½ x 1/2.5 M ± 3ns = 200 ns ±3 ns.
4. tMDKHDX transition:
• For Rev 1 silcon: tMDKHDX is MDC positive edge to MDIO transition.
• If MDIO_CFG[NEG] = 0 then tMDKHDX is MDC positive edge to MDIO transition.
• If MDIO_CFG[NEG]= 1 then tMDKHDX is MDC negative edge to MDIO transition.
• The default value of MDIO_CFG [MDIO_CLK_DIV] is 0, which means no MDIO clock is available. Recommended
to configure this field in PBL.
5. tenet_clk is the Ethernet clock period derived from Frame Manager clock (FM clock). tenet_clk = 1/FM_clock.


7. The actual setup time varies with the MDC slew rate. For a 180 Ω MDC pull-up and 470 pF load, the setup time is
expected to be 68 ns measured at 50% points. To ensure setup time is met, the EMI2 clock frequency may need to be
reduced from the default setting by selecting a larger clock divide via configuration of MDIO_CFG[MDIO_CLK_DIV]
associated with EMI2.
This figure shows the Ethernet management interface timing diagram.
tMDC
MDC
tMDCH
MDIO
(Input)
tMDDVKH
tMDDXKH
MDIO
(Output)
Rev 1
tMDKHDX
MDIO
(Output)
Rev 2
tMDKHDX
Figure 16. Ethernet management interface timing diagram
3.11.4 IEEE 1588 electrical specifications
3.11.4.1 IEEE 1588 DC electrical characteristics

This table shows IEEE 1588 DC electrical characteristics when operating at LVDD = 2.5
V supply.
Table 40. IEEE 1588 DC electrical characteristics(LVDD = 2.5 V)3

Table 40. IEEE 1588 DC electrical characteristics(LVDD = 2.5 V)3 (continued)

This table shows IEEE 1588 DC electrical characteristics when operating at LVDD = 1.8
V supply.
Table 41. IEEE 1588 DC electrical characteristics(LVDD = 1.8 V)3
3.11.4.2 IEEE 1588 AC specifications

This table provides the IEEE 1588 AC timing specifications.
Table 42. IEEE 1588 AC timing specifications3
TSEC_1588_CLK_IN clock period tT1588CLK 6 - ns
TSEC_1588_CLK_IN duty cycle tT1588CLKH/ 40 50 60 %
tT1588CLK
TSEC_1588_CLK_IN peak-to-peak jitter tT1588CLKINJ - - 250 ps -
Rise time TSEC_1588_CLK_IN (20% tT1588CLKINR 1.0 - 2.0 ns -
-80%)
Fall time TSEC_1588_CLK_IN (80% tT1588CLKINF 1.0 - 2.0 ns -
-20%)
TSEC_1588_CLK_OUT clock period tT1588CLKOUT 2 x tT1588CLK - - ns 2

Table 42. IEEE 1588 AC timing specifications3 (continued)

TSEC_1588_CLK_OUT duty cycle tT1588CLKOTH/ 30 50 70 % -
tT1588CLKOUT
TSEC_1588_PULSE_OUT1/2, tT1588OV 0.5 - 4.0 ns -
TSEC_1588_ALARM_OUT1/2 hold time
TSEC_1588_TRIG_IN1/2 pulse width tT1588TRIGH 2 x tT1588CLK - - ns 1
Notes:
1. It needs to be at least two times the clock period of the clock selected by TMR_CTRL[CKSEL]. See the chip reference
manual for a description of TMR_CTRL registers.
2. There are 3 input clock sources for 1588 i.e. TSEC_1588_CLK_IN, RTC, and MAC clock / 2 in rev1 silicon and MAC clock
in rev2 silicon.
This figure shows the data and command output AC timing diagram.
tT1588CLKOUT
tT1588CLKOUTH
TSEC_1588_CLK_OUT
tT1588OV
TSEC_1588_PULSE_OUT1/2
TSEC_1588_ALARM_OUT1/2
Note: The output delay is counted starting at the rising edge if tT1588CLKOUT is non-inverting.
Otherwise, it is counted starting at the falling edge.
Figure 17. IEEE 1588 output AC timing
This figure shows the data and command input AC timing diagram.
tT1588CLK
TSEC_1588_CLK_IN tT1588CLKH
TSEC_1588_TRIG_IN1/2
tT1588TRIGH
Figure 18. IEEE 1588 input AC timing
3.12 USB interface

This section provides the AC and DC electrical specifications for the USB interface.

3.12.1 USB DC electrical characteristics

This table provides the DC electrical characteristics for the USB interface at USB_HVDD
= 3.3 V.
Table 43. USB DC electrical characteristics (USB_HVDD = 3.3 V) 3
Input high voltage VIH 2.0 - V 1, 4
Input low voltage VIL - 0.8 V 1, 4
Input current (USB_HVIN = 0 V or USB_HVIN= IIN -100 +100 μA 2, 4
USB_HVDD)
Output high voltage (USB_HVDD = min, IOH = -2 mA) VOH 2.8 - V 5
Output low voltage (USB_HVDD = min, IOL = 2 mA) VOL - 0.3 V 5
Notes:
1. The min VILand max VIH values are based on the respective min and max USB_HVIN values found in Table 3.
2. The symbol USB_HVIN, in this case, represents the USB_HVIN symbol referenced in Recommended operating conditions.
4. These specifications only apply to the following pins: USB1_PWRFAULT, USB2_PWRFAULT, USB1_UDM (full-speed
mode), USB2_UDM (full-speed mode), USB1_UDP (full-speed mode), and USB2_UDP (full-speed mode).
5. This specification only applies to USB1_DRVVBUS and USB2_DRVVBUS pins.
This table provides the DC electrical characteristics for the USBCLK at OVDD = 1.8 V.
Table 44. USBCLK DC electrical characteristics (1.8 V)3
Input current (VIN = IIN -50 50 μA 2
0 V or VIN = OVDD)
Notes:
1. The min VIL and max VIH values are based on the respective min and max OVIN values found in Table 3.
3.12.2 USB AC timing specifications

This section describes the AC timing specifications for the on-chip USB PHY. See
Chapter 7 in the Universal Serial Bus Revision 2.0 Specification for more information.

This table provides the USB clock input (USBCLK) AC timing specifications.
Table 45. USBCLK AC timing specifications1
Parameter/Condition Symbol Condition Min Typ Max Unit Notes
USBCLK Frequency fUSB_CLK_IN - - 24 - MHz -
USBCLK Rise/Fall time tUSRF Measured between 10% and 90% - - 6 ns 2
USBCLK frequency tCLK_TOL - -0.005 0 0.005 % -
tolerance
USBCLK duty cycle tCLK_DUTY Measured at rising edge and/or failing edge 40 50 60 % -
at OVDD/2
USBCLK total input tCLK_PJ RMS value measured with a second-order, - - 5 ps -
jitter/time interval error band-pass filter of 500 kHz to 4 MHz
bandwidth at 10-12 BER
Notes:
1. For recommended operating conditions, see Table 3
2. System/board must be designed to ensure the input requirement to the device is achieved. Proper device operation is
guaranteed for inputs meeting this requirement by design, simulation, characterization, or functional testing.
3.13 Integrated flash controller

This section describes the DC and AC electrical specifications for the integrated flash
controller.
3.13.1 Integrated flash controller DC electrical characteristics

This table provides the DC electrical characteristics for the integrated flash controller
when operating at OVDD= 1.8 V.
Table 46. Integrated flash controller DC electrical characteristics (1.8 V)3
Input current IIN -50 50 μA 2
(VIN = 0 V or VIN = OVDD)
(OVDD = min, IOH = -0.5 mA)
(OVDD = min, IOL = 0.5 mA)

Table 46. Integrated flash controller DC electrical characteristics (1.8 V)3

3.13.2 Integrated flash controller AC timing specification

This section describes the AC timing specifications for the integrated flash controller.
3.13.2.1 Test condition

This figure provides the AC test load for the integrated flash controller.
RL = 50 Ω
Figure 19. Integrated flash controller AC test load
3.13.2.2 Integrated flash controller AC timing specifications

All output signal timings are relative to the falling edge of any IFC_CLK. The external
circuit must use the rising edge of the IFC_CLKs to latch the data.
All input timings are relative to the rising edge of IFC_CLKs.
This table describes the timing specifications of the integrated flash controller interface.
Table 47. Integrated flash controller timing specifications (OVDD = 1.8 V)5
Parameter/Condition Symbol1 Min Max Unit Notes
IFC_CLK cycle time tIBK 10 - ns -
IFC_CLK duty cycle tIBKH/ tIBK 45 55 % -
IFC_CLK[n] skew to IFC_CLK[m] tIBKSKEW 0 ±75 ps 2
Input setup tIBIVKH 4 - ns -
Input hold tIBIXKH 1 - ns -
Output delay tIBKLOV - 1.5 ns -
Output hold tIBKLOX -2 - ns 4

Table 47. Integrated flash controller timing specifications (OVDD = 1.8 V)5 (continued)
IFC_CLK to output high impedance for AD tIBKLOZ - 2 ns 3
1. All signals are measured from OVDD/2 of rising/falling edge of IFC_CLK to OVDD/2 of the signal in question.
2. Skew measured between different IFC_CLK signals at OVDD/2.
3. For purposes of active/float timing measurements, the high impedance or off state is defined to be when the total current
delivered through the component pin is less than or equal to the leakage current specification.
4. Here the negative sign means output transit happens earlier than the falling edge of IFC_CLK.
This figure shows the AC timing diagram.
IFC_CLK[m]
tIBIXKH
tIBIVKH
Input signals
tIBIVKL
tIBKLOV tIBKLOX
Output signals
tIBKLOZ
tIBKLOX
AD (data phase)
Figure 20. Integrated flash controller signals
The figure above applies to all the controllers that IFC supports.
• For input signals, the AC timing data is used directly for all controllers.
• For output signals, each type of controller provides its own unique method to control
the signal timing. The final signal delay value for output signals is the programmed
delay plus the AC timing delay.
This figure shows how the AC timing diagram applies to GPCM. The same principle also
applies to other controllers of IFC.

IFC_CLK
AD Address Read data Address Write data
teahc + tIBKLOV
teadc + tIBKLOV
AVD
tacse+ tIBKLOV
CE_B
taco + tIBKLOV
OE_B trad + tIBKLOV

tch + tIBKLOV
tcs + tIBKLOV
WE_B
twp+ tIBKLOV
BCTL
Read Write
Figure 21. GPCM output timing diagram1, 2
Notes for figure:

1. taco, trad,teahc,teadc, tacse, tcs, tch,twp are programmable. See the chip reference manual.
2. For output signals, each type of controller provides its own unique method to control
the signal timing. The final signal delay value for output signals is the programmed delay
plus the AC timing delay.
3.14 Enhanced secure digital host controller (eSDHC)

This section describes the DC and AC electrical specifications for the eSDHC interface.
3.14.1 eSDHC DC electrical characteristics

This table provides the DC electrical characteristics for the eSDHC interface.
Table 48. eSDHC interface DC electrical characteristics (dual-voltage cards)3
Input high voltage VIH 0.7 x OVDD - V 1
Input low voltage VIL - 0.3 x OVDD V 1
I/O leakage current IIN/IOZ -50 50 μA -
Output high voltage (IOH = -100 μA at VOH OVDD - 0.2 V - V -
OVDD min)
Output low voltage (IOL= 100 μA at VOL - 0.2 V -
OVDD min)

Table 48. eSDHC interface DC electrical characteristics (dual-voltage cards)3 (continued)

Output high voltage (IOH = -100 μA) VOH OVDD - 0.2 V - V 2
Output low voltage (IOL = 2 mA) VOL - 0.3 V 2
1. The min VIL and VIH values are based on the respective min and max OVIN values found in Table 3.
2. Open-drain mode is for MMC cards only.
3.14.2 eSDHC AC timing specifications

This table provides the eSDHC AC timing specifications as defined in Figure 22.
Table 49. eSDHC AC timing specifications6
SD_CLK clock frequency: fSHSCK 0 MHz 2, 4
25/50
SD/SDIO Full-speed/high-speed mode
20/52
MMC Full-speed/high-speed mode
SD_CLK clock low time-Full-speed/High-speed mode tSHSCKL 10/7 - ns 4
SD_CLK clock high time-Full-speed/High-speed mode tSHSCKH 10/7 - ns 4
SD_CLK clock rise and fall times tSHSCKR/ - 3 ns 4
tSHSCKF
Input setup times: SD_CMD, SD_DATx, SD_CD to SD_CLK tSHSIVKH 2.5 - ns 3, 4, 5
Input hold times: SD_CMD, SD_DATx, SD_CD to SD_CLK tSHSIXKH 2.5 - ns 4, 5
Output hold time: SD_CLK to SD_CMD, SD_DATx valid tSHSKHOX -3 - ns 4, 5
Output delay time: SD_CLK to SD_CMD, SD_DATx valid tSHSKHOV - 3 ns 4, 5
Notes:
1. The symbols used for timing specifications herein follow the pattern of t(first three letters of functional block)(signal)(state) (reference)(state)
for inputs and t(first three letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tFHSKHOV symbolizes eSDHC
high-speed mode device timing (SHS) clock reference (K) going to the high (H) state, with respect to the output (O) reaching
the invalid state (X) or output hold time. Note that in general, the clock reference symbol is based on five letters representing
the clock of a particular functional. For rise and fall times, the latter convention is used with the appropriate letter: R (rise) or F
(fall).
2. In full-speed mode, the clock frequency value can be 0-25 MHz for an SD/SDIO card and 0-20 MHz for an MMC card. In
high-speed mode, the clock frequency value can be 0-50 MHz for an SD/SDIO card and 0-52 MHz for an MMC card.
3. To satisfy setup timing, one-way board-routing delay between Host and Card, on SD_CLK, SD_CMD, and SD_DATx
should not exceed 1 ns for any high speed MMC card. For any high speed or default speed mode SD card, the one way
board routing delay between Host and Card, on SD_CLK, SD_CMD, and SD_DATx should not exceed 1.5ns.
4. CCARD ≤ 10 pF, (1 card), and CL = CBUS + CHOST + CCARD ≤ 40 pF.
5. The parameter values apply to both full-speed and high-speed modes.

This figure provides the eSDHC clock input timing diagram.
eSDHC
external clock
operational mode VM VM VM
tSHSCKL tSHSCKH
tSHSCK
tSHSCKR tSHSCKF
VM = Midpoint voltage (OVDD/2)
Figure 22. eSDHC clock input timing diagram
This figure provides the data and command input/output timing diagram.
SDHC_CLK VM VM VM VM
external clock
tSHSIVKH tSHSIXKH
SDHC_DAT/CMD inputs
SDHC_DAT/CMD outputs
tSHSKHOV tSHSKHOX

Figure 23. eSDHC data and command input/output timing diagram referenced to clock
3.15 Multicore programmable interrupt controller (MPIC)

This section describes the DC and AC electrical specifications for the multicore
programmable interrupt controller.
3.15.1 MPIC DC specifications

This figure provides the DC electrical characteristics for the MPIC interface.

Table 50. MPIC DC electrical characteristics (OVDD = 1.8 V)3

Input current (OVIN = 0 V or OVIN = OVDD) IIN -50 50 μA 2
Output high voltage (OVDD = min, IOH = -0.5 mA) VOH 1.35 - V -
Output low voltage (OVDD = min, IOL = 0.5 mA) VOL - 0.4 V -
Note:
1. The min VILand max VIH values are based on the min and max OVIN respective values found in Table 3.
2. The symbol OVIN, in this case, represents the OVIN symbol referenced in Table 3.
3.15.2 MPIC AC timing specifications

This table provides the MPIC input and output AC timing specifications.
Table 51. MPIC Input AC timing specifications2
Parameter/Condition Symbol Min Max Unit Notes
MPIC inputs-minimum pulse width tPIWID 3 - SYSCLKs 1
1. MPIC inputs and outputs are asynchronous to any visible clock. MPIC outputs must be synchronized before use by any
external synchronous logic. MPIC inputs are required to be valid for at least tPIWID ns to ensure proper operation when
working in edge triggered mode.
3.16 JTAG controller

This section describes the DC and AC electrical specifications for the IEEE 1149.1
(JTAG) interface.
3.16.1 JTAG DC electrical characteristics

This table provides the JTAG DC electrical characteristics.
Table 52. JTAG DC electrical characteristics (OVDD = 1.8V)3

Table 52. JTAG DC electrical characteristics (OVDD = 1.8V)3 (continued)

Input current (OVIN = 0 V or OVIN = OVDD) IIN -100 50 μA 2, 4
Output high voltage (OVDD = min, IOH = -0.5 mA) VOH 1.35 - V -
Output low voltage (OVDD = min, IOL = 0.5 mA) VOL - 0.4 V -
Notes:
2. The symbol VIN, in this case, represents the OVIN symbol found in Table 3.
4. TMI, TMS, and TRST_B have internal pull-ups per the IEEE Std. 1149.1 specification.
3.16.2 JTAG AC timing specifications

This table provides the JTAG AC timing specifications as defined in Figure 24 through
Figure 27.
Table 53. JTAG AC timing specifications4
JTAG external clock frequency of operation fJTG 0 33.3 MHz 5
JTAG external clock cycle time tJTG 30 - ns 6
JTAG external clock pulse width measured at 1.4 V tJTKHKL 15 - ns 7
JTAG external clock rise and fall times tJTGR/tJTGF 0 2 ns 8
TRST_B assert time tTRST 25 - ns 2
Input setup times tJTDVKH 4.5 - ns 9
Input hold times tJTDXKH 11 - ns 10
Output valid times Boundary-scan data tJTKLDV - 15 ns 3, 11, 12
TDO - 10
Output hold times tJTKLDX 0 - ns 3
Notes:
1. The symbols used for timing specifications follow the pattern t(first two letters of functional block)(signal)(state)(reference)(state) for inputs
and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tJTDVKH symbolizes JTAG device timing (JT)
with respect to the time data input signals (D) reaching the valid state (V) relative to the tJTG clock reference (K) going to the
high (H) state or setup time. Also, tJTDXKH symbolizes JTAG timing (JT) with respect to the time data input signals (D)
reaching the invalid state (X) relative to the tJTG clock reference (K) going to the high (H) state. Note that in general, the clock
reference symbol representation is based on three letters representing the clock of a particular functional. For rise and fall
times, the latter convention is used with the appropriate letter: R (rise) or F (fall).
2.TRST_B is an asynchronous level sensitive signal. The setup time is for test purposes only.
3. All outputs are measured from the midpoint voltage of the falling edge of tTCLK to the midpoint of the signal in question. The
output timings are measured at the pins. All output timings assume a purely resistive 50-Ω load. Time-of-flight delays must be
added for trace lengths, vias, and connectors in the system.

Table 53. JTAG AC timing specifications4

5. TCK frequency can be as high as 100MHz for internal debug modes.
6. If TCK = 100 MHz then tJTG = 10 nsec
7. If TCK = 100 MHz then tJTKHKL = 5 nsec
8. If TCK = 100 MHz then tJTGR/tJTGF=<1 nsec
9. If TCK = 100 MHz then tJTDVKH = 1.33 nsec
10. If TCK = 100 MHz then tJTDXKH = 3.3 nsec
11. Due to value of tJTKLDV, after Update-IR or Update-DR transitions for EXTEST* or CLAMP instructions, a transition
through the optional Run-Test-Idle state is recommended to allow for board level propagation and setup times of observation
points.
12. DDR output pins when transitioning from a tristate to driving a logic 1 or 0 can require up to 24ns. Use of Run-Test Idle
state is recommended after Update-IR or Update-DR TAP states.
This figure provides the AC test load for TDO and the boundary-scan outputs of the
device.
RL = 50 Ω
Figure 24. AC test load for the JTAG interface
This figure provides the JTAG clock input timing diagram.
VM VM VM
JTAG external clock
tJTGR
tJTKHKL
tJTGF
tJTG
Figure 25. JTAG clock input timing diagram
This figure provides the TRST_B timing diagram.

TRST_B
VM VM
tTRST
Figure 26. TRST_B timing diagram
This figure provides the boundary-scan timing diagram.
JTAG External Clock
VM VM
tJTDVKH
tJTDXKH
Boundary Data Inputs Input Data Valid
tJTKLDV
tJTKLDX
Boundary Data Outputs Output Data Valid
VM = Midpoint Voltage (OVDD/2)
Figure 27. Boundary-scan timing diagram
3.17 I2C interface

This section describes the DC and AC electrical characteristics for the I2C interface.
3.17.1 I2C DC electrical characteristics

This table provides the DC electrical characteristics for the I2C interfaces operating at
2.5V.
Table 54. I2C DC electrical characteristics (DVDD = 2.5V)5

Table 54. I2C DC electrical characteristics (DVDD = 2.5V)5 (continued)

Output low voltage (DVDD = min, IOL = 3 mA) VOL 0 0.4 V 2
Pulse width of spikes which must be suppressed by the input filter tI2KHKL 0 50 ns 3
Leakage Input current at each I/O pin (input voltage is between 0.1 x IOZ -50 50 μA 4
DVDD and 0.9 x DVDD(max)
Capacitance for each I/O pin CI - 10 pF -
Notes:
1. The min VILand max VIH values are based on the respective min and max DVIN values found in Table 3.
2. See the chip reference manual for information about the digital filter used.
3. I/O pins obstruct the SDA and SCL lines if DVDD is switched off.
This table provides the DC electrical characteristics for the I2C interfaces operating at
1.8V.
Table 55. I2C DC electrical characteristics (DVDD = 1.8V)5
Output low voltage (DVDD = min, IOL = 3 mA) VOL 0 0.36 V 2
Pulse width of spikes which must be suppressed by the input filter tI2KHKL 0 50 ns 3
Leakage Input current each I/O pin (input voltage is between 0.1 x IOZ -50 50 μA 4
DVDD and 0.9 x DVDD(max)
Capacitance for each I/O pin CI - 10 pF -
Notes:
1. The min VILand max VIH values are based on the respective min and max DVIN values found in Table 3.
2. See the chip reference manual for information about the digital filter used.
3. I/O pins obstruct the SDA and SCL lines if DVDD is switched off.
3.17.2 I2C AC timing specifications

This table provides the AC timing parameters for the I2C interfaces.

Table 56. I2C AC timing specifications5

SCL clock frequency fI2C 0 400 kHz 2
Low period of the SCL clock tI2CL 1.3 — μs —
High period of the SCL clock tI2CH 0.6 — μs —
Setup time for a repeated START condition tI2SVKH 0.6 — μs —
Hold time (repeated) START condition (after this period, the first tI2SXKL 0.6 — μs —
clock pulse is generated)
Data setup time tI2DVKH 100 — ns —
Data input hold time: tI2DXKL — — μs 3
Data output delay time tI2OVKL — 0.9 μs 4
Setup time for STOP condition tI2PVKH 0.6 — μs —
Bus free time between a STOP and START condition tI2KHDX 1.3 — μs —
Noise margin at the LOW level for each connected device VNL 0.1 x OVDD — V —
(including hysteresis)
Noise margin at the HIGH level for each connected device VNH 0.2 x OVDD — V —
(including hysteresis)
Capacitive load for each bus line Cb — 400 pF —
Notes:
1. The symbols used for timing specifications herein follow the pattern t(first two letters of functional block)(signal)(state)(reference)(state) for
inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tI2DVKH symbolizes I2C timing (I2) with
respect to the time data input signals (D) reaching the valid state (V) relative to the tI2C clock reference (K) going to the high
(H) state or setup time. Also, tI2SXKL symbolizes I2C timing (I2) for the time that the data with respect to the START condition
(S) went invalid (X) relative to the tI2C clock reference (K) going to the low (L) state or hold time. Also, tI2PVKH symbolizes I2C
timing (I2) for the time that the data with respect to the STOP condition (P) reaches the valid state (V) relative to the tI2C clock
reference (K) going to the high (H) state or setup time.
2. The requirements for I2C frequency calculation must be followed. See Determining the I2C Frequency Divider Ratio for
SCL (AN2919).
3. As a transmitter, the chip provides a delay time of at least 300 ns for the SDA signal (referred to the VIHmin of the SCL
signal) to bridge the undefined region of the falling edge of SCL to avoid unintended generation of a START or STOP
condition. When the chip acts as the I2C bus master while transmitting, it drives both SCL and SDA. As long as the load on
SCL and SDA are balanced, the chip does not generate an unintended START or STOP condition. Therefore, the 300 ns
SDA output delay time is not a concern. If, under some rare condition, the 300 ns SDA output delay time is required for the
chip as transmitter, see Determining the I2C Frequency Divider Ratio for SCL (AN2919).
4. The maximum tI2OVKL has to be met only if the device does not stretch the LOW period (tI2CL) of the SCL signal.
This figure provides the AC test load for the I2C.

Output Z0= 50 Ω DVDD/2
RL = 50 Ω
Figure 28. I2C AC test load
This figure shows the AC timing diagram for the I2C bus.
SDA
tI2DVKH tI2KHKL tI2KHDX

tI2CL tI2SXKL
SCL
tI2CH tI2SVKH tI2PVKH

tI2SXKL
tI2DXKL, tI2OVKL
S Sr P S
Figure 29. I2C Bus AC timing diagram
3.18 GPIO interface

This section describes the DC and AC electrical characteristics for the GPIO interface.
3.18.1 GPIO DC electrical characteristics

This table provides the DC electrical characteristics for GPIO pins operating at LVDD =
2.5 V.
Table 57. GPIO DC electrical characteristics (2.5 V)3
Input current (VIN = 0 V or VIN = LVDD) IIN -50 50 μA 2
(LVDD = min, IOH = -1 mA)

Table 57. GPIO DC electrical characteristics (2.5 V)3 (continued)

(LVDD = min, IOL = 1 mA)
1. The min VILand max VIH values are based on the respective min and max LVIN values found in Table 3 .
2. The symbol VIN, in this case, represents the LVIN symbol referenced in Recommended operating conditions.
This table provides the DC electrical characteristics for GPIO pins operating at LVDD or
OVDD= 1.8 V.
Table 58. GPIO DC electrical characteristics (1.8 V)3
Input current (VIN = 0 V or VIN = L/OVDD) IIN -50 50 μA 2
(L/OVDD = min, IOH = -0.5 mA)
(L/OVDD = min, IOL = 0.5 mA)
1. The min VILand max VIH values are based on the respective min and max L/OVIN values found in Table 3.
2. The symbol VIN, in this case, represents the L/OVIN symbol referenced in Recommended operating conditions.
This table provides the DC electrical characteristics for the LP Trust pin,
LP_TMP_DETECT_B, operating at VDDLP = 1 V.
Table 59. LP_TMP_DETECT_B Pin DC electrical characteristics (1 V)3
Input high voltage VIH 0.8 x VDD_LP - V 1
Input low voltage VIL - 0.4 x VDD_LP V 1
Input current (VIN_LP = 0 V or VIN_LP = IIN -50 50 μA 2
VDD_LP)
1. The min VILand max VIH values are based on the respective min and max VDD_LP values found in Table 3.
2. The symbol VIN_LP, in this case, represents the VIN_LP symbol referenced in Recommended operating conditions.

3.18.2 GPIO AC timing specifications

This table provides the GPIO input and output AC timing specifications.
Table 60. GPIO input AC timing specifications2
Parameter/Condition Symbol Min Unit Notes
GPIO inputs—minimum pulse width tPIWID 20 ns 1
Notes:
1. GPIO inputs and outputs are asynchronous to any visible clock. GPIO outputs should be synchronized before use by any
external synchronous logic. GPIO inputs are required to be valid for at least tPIWID to ensure proper operation.
This figure provides the AC test load for the GPIO.
Output Z0= 50 Ω (L/O) VDD/2
RL = 50 Ω
Figure 30. GPIO AC test load
3.19 High-speed serial interfaces (HSSI)

The chip features a serializer/deserializer (SerDes) interface to be used for high-speed
serial interconnect applications. The SerDes interface can be used for PCI Express,
SATA, Serial RapidIO, XAUI, XFI, 10GBase-KR, Aurora, Interlaken LA, HiGig/
HiGig2, SGMII, 2.5x SGMII and QSGMII data transfers.
This section describes the common portion of SerDes DC electrical specifications: the
DC requirement for SerDes reference clocks. The SerDes data lane's transmitter (Tx) and
receiver (Rx) reference circuits are also shown.
3.19.1 Signal terms definition

The SerDes utilizes differential signaling to transfer data across the serial link. This
section defines the terms that are used in the description and specification of differential
signals.

This figure shows how the signals are defined. For illustration purposes only, one SerDes
lane is used in the description. This figure shows the waveform for either a transmitter
output (SD_TXn and SD_TXn_B) or a receiver input (SD_RXn and SD_RXn_B). Each
signal swings between A volts and B volts where A > B.
SD_TXn or
SD_RXn
A Volts
Vcm= (A + B)/2
SD_TXn_B or
SD_RXn_B
B Volts
Differential swing, VID orVOD = A - B

Differential peak voltage, VDIFFp = |A - B|
Differential peak-to-peak voltage, VDIFFpp =2 x VDIFFp (not shown)
Figure 31. Differential voltage definitions for transmitter or receiver
Using this waveform, the definitions are as shown in the following list. To simplify the
illustration, the definitions assume that the SerDes transmitter and receiver operate in a
fully symmetrical differential signaling environment:
Single-Ended Swing
The transmitter output signals and the receiver input signals SD_TXn, SD_TXn_B,
SD_RXn and SD_RXn_B each have a peak-to-peak swing of A - B volts. This is also
referred as each signal wire's single-ended swing.
Differential Output Voltage, VOD (or Differential Output Swing)
The differential output voltage (or swing) of the transmitter, VOD, is defined as the
difference of the two complementary output voltages: VSD_TXn- VSD_TXn_B. The VOD
value can be either positive or negative.
Differential Input Voltage, VID (or Differential Input Swing)
The differential input voltage (or swing) of the receiver, VID, is defined as the
difference of the two complementary input voltages: VSD_RXn- VSD_RXn_B. The VID
value can be either positive or negative.
Differential Peak Voltage, VDIFFp
The peak value of the differential transmitter output signal or the differential receiver
input signal is defined as the differential peak voltage, VDIFFp = |A - B| volts.
Differential Peak-to-Peak, VDIFFp-p
Since the differential output signal of the transmitter and the differential input signal of
the receiver each range from A - B to -(A - B) volts, the peak-to-peak value of the
differential transmitter output signal or the differential receiver input signal is defined
as differential peak-to-peak voltage, VDIFFp-p = 2 x VDIFFp = 2 x |(A - B)| volts, which
is twice the differential swing in amplitude, or twice of the differential peak. For

example, the output differential peak-to-peak voltage can also be calculated as VTX-
DIFFp-p = 2 x |VOD|.
Differential Waveform
The differential waveform is constructed by subtracting the inverting signal
(SD_TXn_B, for example) from the non-inverting signal (SD_TXn, for example)
within a differential pair. There is only one signal trace curve in a differential
waveform. The voltage represented in the differential waveform is not referenced to
ground. See Figure 36 as an example for differential waveform.
Common Mode Voltage, Vcm
The common mode voltage is equal to half of the sum of the voltages between each
conductor of a balanced interchange circuit and ground. In this example, for SerDes
output, Vcm_out = (VSD_TXn+ VSD_TXn_B) ÷ 2 = (A + B) ÷ 2, which is the arithmetic
mean of the two complementary output voltages within a differential pair. In a system,
the common mode voltage may often differ from one component's output to the other's
input. It may be different between the receiver input and driver output circuits within
the same component. It is also referred to as the DC offset on some occasions.
To illustrate these definitions using real values, consider the example of a current mode
logic (CML) transmitter that has a common mode voltage of 2.25 V and outputs, TD and
TD_B. If these outputs have a swing from 2.0 V to 2.5 V, the peak-to-peak voltage swing
of each signal (TD or TD_B) is 500 mV p-p, which is referred to as the single-ended
swing for each signal. Because the differential signaling environment is fully symmetrical
in this example, the transmitter output's differential swing (VOD) has the same amplitude
as each signal's single-ended swing. The differential output signal ranges between 500
mV and -500 mV. In other words, VOD is 500 mV in one phase and -500 mV in the other
phase. The peak differential voltage (VDIFFp) is 500 mV. The peak-to-peak differential
voltage (VDIFFp-p) is 1000 mV p-p.
3.19.2 SerDes reference clocks

The SerDes reference clock inputs are applied to an internal PLL whose output creates
the clock used by the corresponding SerDes lanes. The SerDes reference clocks inputs are
SD1_REF_CLK[1:2] and SD1_REF_CLK[1:2]_B for SerDes 1, SD2_REF_CLK[1:2]
and SD2_REF_CLK[1:2]_B for SerDes 2, SD3_REF_CLK[1:2] and
SD3_REF_CLK[1:2]_B for SerDes 3 and SD4_REF_CLK[1:2] and
SD4_REF_CLK[1:2]_B for SerDes 4.
SerDes 1-4 may be used for various combinations of the following IP blocks based on the
RCW Configuration field SRDS_PRTCLn:
• SerDes 1: SGMII (1.25 and 3.125 Gbaud), QSGMII (5 Gbps only), HiGig/HiGig2
(3.125 Gbps), HiGig/HiGig2 (3.75 Gbps) or XAUI (3.125 Gb/s)

• SerDes 2: SGMII (1.25 and 3.125 Gbaud), QSGMII (5 Gbps only), XAUI (3.125
Gb/s), HiGig/HiGig2 (3.125 Gbps), HiGig/HiGig2 (3.75 Gbps), XFI (10.3125 Gb/s
only) or 10GBase-KR (10.3125 Gbaud only)
• SerDes 3: PEX1/2 (2.5, 5, and 8 GT/s), SRIO1(2.5, 3.125, and 5 Gbaud) or
Interlaken-LA(6.25)
• SerDes 4: PEX3/4 (2.5, 5, and 8 GT/s), SRIO2(2.5, 3.125, and 5 Gbaud), Aurora
(2.5, 3.125, and 5 Gbps) or SATA1/2 (1.5 and 3.0 Gbps)
The following sections describe the SerDes reference clock requirements and provide
application information.
3.19.2.1 SerDes spread-spectrum clock source recommendations

SDn_REF_CLKn/SDn_REF_CLKn_B are designed to work with spread-spectrum clock
for PCI Express protocol only with the spreading specification defined in Table 61. When
using spread-spectrum clocking for PCI Express, both ends of the link partners should
use the same reference clock. For best results, a source without significant unintended
modulation must be used.
For SATA protocol, the SerDes transmitter does not support spread-spectrum clocking.
The SerDes receiver does support spread-spectrum clocking on receive, which means the
SerDes receiver can receive data correctly from a SATA serial link partner using spread-
spectrum clocking
The spread-spectrum clocking cannot be used if the same SerDes reference clock is
shared with other non-spread-spectrum supported protocols. For example, if the spread-
spectrum clocking is desired on a SerDes reference clock for PCI Express and the same
reference clock is used for any other protocol such as SATA/SGMII/QSGMII/SRIO/
XAUI due to the SerDes lane usage mapping option, spread-spectrum clocking cannot be
used at all.
Table 61. SerDes spread-spectrum clock source recommendations 1
Frequency modulation 30 33 kHz -
Frequency spread +0 -0.5 % 2
1. At recommended operating conditions. See Table 3.
2. Only down-spreading is allowed.
3.19.2.2 SerDes reference clock receiver characteristics

This figure shows a receiver reference diagram of the SerDes reference clocks.

50 Ω
SDn_REF_CLKn
Input
amp
SDn_REF_CLKn_B
50 Ω
Figure 32. Receiver of SerDes reference clocks
The characteristics of the clock signals are as follows:

• The SerDes transceivers core power supply voltage requirements (SVDDn) are as
specified in Recommended operating conditions.
• The SerDes reference clock receiver reference circuit structure is as follows:
• The SDn_REF_CLKn and SDn_REF_CLKn_B are internally AC-coupled
differential inputs as shown in Figure 32. Each differential clock input
(SDn_REF_CLKn or SDn_REF_CLKn_B) has on-chip 50 Ω termination to
SGNDn followed by on-chip AC-coupling.
• The external reference clock driver must be able to drive this termination.
• The SerDes reference clock input can be either differential or single-ended. See
the differential mode and single-ended mode descriptions below for detailed
requirements.
• The maximum average current requirement also determines the common mode
voltage range.
• When the SerDes reference clock differential inputs are DC coupled externally
with the clock driver chip, the maximum average current allowed for each input
pin is 8 mA. In this case, the exact common mode input voltage is not critical as
long as it is within the range allowed by the maximum average current of 8 mA
because the input is AC-coupled on-chip.
• This current limitation sets the maximum common mode input voltage to be less
than 0.4 V (0.4 V ÷ 50 Ω = 8 mA) while the minimum common mode input level
is 0.1 V above SGNDn. For example, a clock with a 50/50 duty cycle can be
produced by a clock driver with output driven by its current source from 0 mA to
16 mA (0-0.8 V), such that each phase of the differential input has a single-
ended swing from 0 V to 800 mV with the common mode voltage at 400 mV.
• If the device driving the SDn_REF_CLKn and SDn_REF_CLKn_B inputs
cannot drive 50 Ω to SGNDn DC or the drive strength of the clock driver chip
exceeds the maximum input current limitations, it must be AC-coupled off-chip.
• The input amplitude requirement is described in detail in the following sections.
3.19.2.3 DC-level requirement for SerDes reference clocks

The DC level requirement for the SerDes reference clock inputs is different depending on
the signaling mode used to connect the clock driver chip and SerDes reference clock
inputs, as described below:
• Differential Mode
• The input amplitude of the differential clock must be between 400 mV and 1600
mV differential peak-to-peak (or between 200 mV and 800 mV differential
peak). In other words, each signal wire of the differential pair must have a
single-ended swing of less than 800 mV and greater than 200 mV. This
requirement is the same for both external DC-coupled or AC-coupled
connection.
• For an external DC-coupled connection, as described in SerDes reference clock
receiver characteristics, the maximum average current requirements sets the
requirement for average voltage (common mode voltage) as between 100 mV
and 400 mV. Figure 33 shows the SerDes reference clock input requirement for
DC-coupled connection scheme.
200 mV < Input amplitude or differential peak < 800 mV
SDn_REF_CLKn Vmax < 800mV
100 mV < Vcm < 400 mV
SDn_REF_CLKn_B Vmin > 0 V
Figure 33. Differential reference clock input DC requirements (external DC-coupled)

• For an external AC-coupled connection, there is no common mode voltage
requirement for the clock driver. Because the external AC-coupling capacitor
blocks the DC level, the clock driver and the SerDes reference clock receiver
operate in different common mode voltages. The SerDes reference clock receiver
in this connection scheme has its common mode voltage set to SGNDn. Each
signal wire of the differential inputs is allowed to swing below and above the
common mode voltage (SGNDn). Figure 34 shows the SerDes reference clock
input requirement for AC-coupled connection scheme.

200 mV < Input amplitude or differential peak < 800 mV
SDn_REF_CLKn Vmax < Vcm + 400 mV
Vcm
SDn_REF_CLK_B Vmin > Vcm - 400 mV
Figure 34. Differential reference clock input DC requirements (external AC-coupled)

• Single-Ended Mode
• The reference clock can also be single-ended. The SDn_REF_CLKn input
amplitude (single-ended swing) must be between 400 mV and 800 mV peak-to-
peak (from VMIN to VMAX) with SDn_REF_CLKn_B either left unconnected or
tied to ground.
• The SDn_REF_CLKn input average voltage must be between 200 and 400 mV.
Figure 35 shows the SerDes reference clock input requirement for single-ended
signaling mode.
• To meet the input amplitude requirement, the reference clock inputs may need to
be DC- or AC-coupled externally. For the best noise performance, the reference
of the clock could be DC- or AC-coupled into the unused phase
(SDn_REF_CLKn_B) through the same source impedance as the clock input
(SDn_REF_CLKn) in use.
400 mV < SD_REF_CLKn input amplitude < 800 mV
SDn_REF_CLKn
0V
SDn_REF_CLKn_B
Figure 35. Single-ended reference clock input DC requirements
3.19.2.4 AC requirements for SerDes reference clocks

This table lists the AC requirements for SerDes reference clocks for protocols running at
data rates up to 8 Gb/s.

This includes PCI Express (2.5, 5, 8 GT/s), SGMII (1.25 Gbaud), 2.5x SGMII
(3.125 Gbaud), QSGMII (5 Gbps), Serial RapidIO (2.5, 3.125, 5 Gbaud), Aurora (2.5,
3.125, 5 Gbps), HiGig/HiGig2 (3.125 Gbps), HiGig/HiGig2 (3.75 Gbps), XAUI
(3.125 Gb/s) and Interlaken-LA (6.25 Gbps) SerDes reference clocks to be guaranteed by
the customer's application design.
Table 62. SDn_REF_CLKn and SDn_REF_CLKn_B input clock requirements (SnVDD = 1.0 V)
1
Parameter Symbol Min Typ Max Unit Notes

SDn_REF_CLKn/ SDn_REF_CLKn_B frequency tCLK_REF - 100/125/156.25 - MHz 2
range
SDn_REF_CLKn/ SDn_REF_CLKn_B clock tCLK_TOL -300 - 300 ppm 3, 12
frequency tolerance
SDn_REF_CLKn/ SDn_REF_CLKn_B clock tCLK_TOL -100 - 100 ppm 4, 12
frequency tolerance
SDn_REF_CLKn/ SDn_REF_CLKn_B reference tCLK_DUTY 40 50 60 % 5
clock duty cycle
SDn_REF_CLKn/ SDn_REF_CLKn_B max tCLK_DJ - - 42 ps -
deterministic peak-to-peak jitter at 10-6 BER
SDn_REF_CLKn/ SDn_REF_CLKn_B total reference tCLK_TJ - - 86 ps 6
clock jitter at 10-6 BER (peak-to-peak jitter at refClk
input)
SDn_REF_CLKn/ SDn_REF_CLKn_B 10 kHz to 1.5 tREFCLK-LF-RMS - - 3 ps 7
MHz RMS jitter RMS
SDn_REF_CLKn/ SDn_REF_CLKn_B > 1.5 MHz to tREFCLK-HF-RMS - - 3.1 ps 7
Nyquist RMS jitter RMS
SDn_REF_CLKn/ SDn_REF_CLKn_B RMS tREFCLK-RMS-DC - - 1 ps 8
reference clock jitter RMS
SDn_REF_CLKn/ SDn_REF_CLKn_B rising/falling tCLKRR/tCLKFR 1 - 4 V/ns 9
edge rate
Differential input high voltage - VCM - - mV 5
+200 m
V
Differential input low voltage - - - VCM-20 mV 5
0 mV
Rising edge rate (SDn_REF_CLKn) to falling edge Rise-Fall - - 20 % 10, 11
rate (SDn_REF_CLKn) matching Matching
2. Caution: Only 100, 125 and 156.25 have been tested.In-between values do not work correctly with the rest of the system.
3. For PCI Express (2.5, 5, 8 GT/s)
4. For SGMII, 2.5x SGMII, QSGMII, sRIO, HiGig/HiGig2, XAUI, Interlaken-LA, Aurora
5. Measurement taken from differential waveform. VCM is the common mode voltage.
6. Limits from PCI Express CEM Rev 2.0
7. For PCI Express-5 GT/s, per PCI Express base specification rev 3.0
8. For PCI-Express-8 GT/s, per PCI-Express base specification rev 3.0

Table 62. SDn_REF_CLKn and SDn_REF_CLKn_B input clock requirements (SnVDD = 1.0 V)
1

9. Measured from -200 mV to +200 mV on the differential waveform (derived from SDn_REF_CLKn minus
SDn_REF_CLKn_B). The signal must be monotonic through the measurement region for rise and fall time. The 400 mV
measurement window is centered on the differential zero crossing. See Figure 36.
10. Measurement taken from single-ended waveform
11. Matching applies to rising edge for SDn_REF_CLKn and falling edge rate for SDn_REF_CLKn_B. It is measured using a
200 mV window centered on the median cross point where SDn_REF_CLKn rising meets SDn_REF_CLKn_B falling. The
median cross point is used to calculate the voltage thresholds that the oscilloscope uses for the edge rate calculations. The
rise edge rate of SDn_REF_CLKn must be compared to the fall edge rate of SDn_REF_CLKn_B, the maximum allowed
difference should not exceed 20% of the slowest edge rate. See Figure 37.
12. When 2 or more protocols share the same PLL on a SerDes module, the tightest SDn_REF_CLKn/ SDn_REF_CLKn_B
clock frequency tolerance must be followed.
This table lists the AC requirements for SerDes reference clocks for protocols running at
data rates greater than 8 Gb/s.
This includes XFI (10.3125 Gb/s) and 10GBase-KR (10.3125 GBd) SerDes reference
clocks to be guaranteed by the customer's application design.
Table 63. SDn_REF_CLKn and SDn_REF_CLKn_B input clock requirements (SVDDn = 1.0 V)
1

SDn_REF_CLKn/ SDn_REF_CLKn_B frequency range tCLK_REF - 156.25/ - MHz 2
161.1328135
SDn_REF_CLKn/ SDn_REF_CLKn_B clock frequency tCLK_TOL -100 - 100 ppm 5
tolerance
SDn_REF_CLKn/ SDn_REF_CLKn_B reference clock duty tCLK_DUTY 40 50 60 % 3
cycle
SDn_REF_CLKn/ SDn_REF_CLKn_B single side band @1 kHz - - -85 dBC/Hz 4
noise
SDn_REF_CLKn/ SDn_REF_CLKn_B single side band @10 kHz - - -108 dBC/Hz 4
noise
SDn_REF_CLKn/ SDn_REF_CLKn_B single side band @100 kH - - -128 dBC/Hz 4
noise z
SDn_REF_CLKn/ SDn_REF_CLKn_B single side band @1 MHz - - -138 dBC/Hz 4
noise
SDn_REF_CLKn/ SDn_REF_CLKn_B single side band @10 MHz - - -138 dBC/Hz 4
noise
SDn_REF_CLKn/ SDn_REF_CLKn_B random jitter tCLK_RJ - - 0.8 ps -
(1.2 MHz to 15 MHz)
SDn_REF_CLKn/ SDn_REF_CLKn_B total reference clock tCLK_TJ - - 11 ps -
jitter at 10-12 BER (1.2 MHz to 15 MHz)
SDn_REF_CLKn/ SDn_REF_CLKn_B spurious noise - - - -75 dBC -
(1.2 MHz to 15 MHz)

Table 63. SDn_REF_CLKn and SDn_REF_CLKn_B input clock requirements (SVDDn = 1.0 V)
1 (continued)

Differential input high voltage - VCM - - mV 6
+200 m
V
Differential input low voltage - - - VCM-20 mV 6
0 mV
Rising edge rate (SDn_REF_CLKn) to falling edge rate Rise-Fall - - 20 % 7, 8
(SDn_REF_CLKn) matching Matching
2. Caution: Only 156.25 and 161.1328135 have been tested. In-between values do not work correctly with the rest of the
system.
3. Measurement taken from differential waveform.
4. Per XFP Spec. Rev 4.5, the Module Jitter Generation spec at XFI Optical Output is 10mUI (RMS) and 100 mUI (p-p). In the
CDR mode the host is contributing 7 mUI (RMS) and 50 mUI (p-p) jitter.
5. When 2 or more protocols share the same PLL on a SerDes module, the tightest SDn_REF_CLKn/ SDn_REF_CLKn_B
clock frequency tolerance must be followed.
6. Measurement taken from differential waveform. VCM is the common mode voltage.
7. Measurement taken from single-ended waveform .
8. Matching applies to rising edge for SDn_REF_CLKn and falling edge rate for SDn_REF_CLKn_B. It is measured using a
200 mV window centered on the median cross point where SDn_REF_CLKn rising meets SDn_REF_CLKn_B falling. The
median cross point is used to calculate the voltage thresholds that the oscilloscope uses for the edge rate calculations. The
rise edge rate of SDn_REF_CLKn must be compared to the fall edge rate of SDn_REF_CLKn_B, the maximum allowed
difference should not exceed 20% of the slowest edge rate. See Figure 37.
Rise-edge rate Fall-edge rate
VIH = + 200 mV
0.0 V
VIL = - 200 mV
SDn_REF_CLKn
SDn_REF_CLKn_B
Figure 36. Differential measurement points for rise and fall time

SDn_REF_CLKn_B SDn_REF_CLKn_B
TFALL TRISE
VCROSS MEDIAN + 100 mV
VCROSS MEDIAN VCROSS MEDIAN
VCROSS MEDIAN - 100 mV
SDn_REF_CLKn SDn_REF_CLKn
Figure 37. Single-ended measurement points for rise and fall time matching
3.19.3 SerDes transmitter and receiver reference circuits

This figure shows the reference circuits for SerDes data lane's transmitter and receiver.
SDn_TXn SDn_RXn
50 Ω
Transmitter 100 Ω Receiver
SDn_TXn_B SDn_RXn_B 50 Ω
Figure 38. SerDes transmitter and receiver reference circuits
The DC and AC specification of SerDes data lanes are defined in each interface protocol
section below based on the application usage:
• PCI Express
• Serial RapidIO (sRIO)
• XAUI interface
• Aurora interface
• Serial ATA (SATA) interface
• SGMII interface
• QSGMII interface
• HiGig/HiGig2 interface
• XFI interface
• Interlaken interface
Note that external AC-coupling capacitor is required for the above serial transmission
protocols with the capacitor value defined in the specification of each protocol section.

3.19.4 PCI Express

This section describes the clocking dependencies, DC and AC electrical specifications for
the PCI Express bus.
3.19.4.1 Clocking dependencies

The ports on the two ends of a link must transmit data at a rate that is within 600 parts per
million (ppm) of each other at all times. This is specified to allow bit rate clock sources
with a ±300 ppm tolerance.
3.19.4.2 PCI Express clocking requirements for SDn_REF_CLKn and

SDn_REF_CLKn_B
SerDes 3-4 (SD[3:4]_REF_CLK[1:2] and SD[3:4]_REF_CLK[1:2]_B) may be used for
various SerDes PCI Express configurations based on the RCW Configuration field
SRDS_PRTCL. PCI Express is not supported on SerDes 1 and 2.
NOTE
PCI Express operating in x8 mode is only supported at 2.5 and
5.0 GT/s.
For more information on these specifications, see SerDes reference clocks.
3.19.4.3 PCI Express DC physical layer specifications

This section contains the DC specifications for the physical layer of PCI Express on this
chip.
3.19.4.3.1 PCI Express DC physical layer transmitter specifications

This section discusses the PCI Express DC physical layer transmitter specifications for
2.5 GT/s, 5 GT/s and 8 GT/s.
This table defines the PCI Express 2.0 (2.5 GT/s) DC specifications for the differential
output at all transmitters. The parameters are specified at the component pins.
Table 64. PCI Express 2.0 (2.5 GT/s) differential transmitter output DC specifications (XVDD
= 1.35 V or 1.5 V)1
Parameter Symbol Min Typical Max Units Notes
Differential peak-to-peak VTX-DIFFp-p 800 1000 1200 mV VTX-DIFFp-p = 2 x │ VTX-D+ - VTX-D- │
output voltage

Table 64. PCI Express 2.0 (2.5 GT/s) differential transmitter output DC specifications (XVDD
= 1.35 V or 1.5 V)1 (continued)
De-emphasized differential VTX-DE-RATIO 3.0 3.5 4.0 dB Ratio of the VTX-DIFFp-p of the second and
output voltage (ratio) following bits after a transition divided by the VTX-
DIFFp-p of the first bit after a transition.
DC differential transmitter ZTX-DIFF-DC 80 100 120 Ω Transmitter DC differential mode low Impedance
impedance
Transmitter DC impedance ZTX-DC 40 50 60 Ω Required transmitter D+ as well as D- DC
Impedance during all states
Notes:
This table defines the PCI Express 2.0 (5 GT/s) DC specifications for the differential
Table 65. PCI Express 2.0 (5 GT/s) differential transmitter output DC specifications (XVDD =
1.35 V or 1.5 V)1
Differential peak-to-peak VTX-DIFFp-p 800 1000 1200 mV VTX-DIFFp-p = 2 x │ VTX-D+ - VTX-D- │
output voltage
Low power differential VTX-DIFFp-p_low 400 500 1200 mV VTX-DIFFp-p = 2 x │ VTX-D+ - VTX-D- │
peak-to-peak output
voltage
De-emphasized differential VTX-DE-RATIO-3.5dB 3.0 3.5 4.0 dB Ratio of the VTX-DIFFp-p of the second and
output voltage (ratio) following bits after a transition divided by the
VTX-DIFFp-p of the first bit after a transition.
De-emphasized differential VTX-DE-RATIO-6.0dB 5.5 6.0 6.5 dB Ratio of the VTX-DIFFp-p of the second and
output voltage (ratio) following bits after a transition divided by the
VTX-DIFFp-p of the first bit after a transition.
DC differential transmitter ZTX-DIFF-DC 80 100 120 Ω Transmitter DC differential mode low
impedance impedance
Transmitter DC ZTX-DC 40 50 60 Ω Required transmitter D+ as well as D- DC
Impedance impedance during all states
Notes:
This table defines the PCI Express 3.0 (8 GT/s) DC specifications for the differential

Table 66. PCI Express 3.0 (8 GT/s) differential transmitter output DC specifications (XVDD =
1.35 V or 1.5 V)3
Full swing transmitter VTX-FS-NO-EQ 800 - 1300 mVp-p See Note 1.
voltage with no TX Eq
Reduced swing VTX-RS-NO-EQ 400 - 1300 mV See Note 1.
transmitter voltage with
no TX Eq
De-emphasized VTX-DE-RATIO-3.5dB 3.0 3.5 4.0 dB -
differential output voltage
(ratio)
De-emphasized VTX-DE-RATIO-6.0dB 5.5 6.0 6.5 dB -
differential output voltage
(ratio)
Minimum swing during VTX-EIEOS-FS 250 - - mVp-p See Note 2
EIEOS for full swing
Minimum swing during VTX-EIEOS-RS 232 - - mVp-p See Note 2
EIEOS for reduced swing
DC differential transmitter ZTX-DIFF-DC 80 100 120 Ω Transmitter DC differential mode low
impedance impedance
Transmitter DC ZTX-DC 40 50 60 Ω Required transmitter D+ as well as D- DC
Impedance impedance during all states
Notes:
1. Voltage measurements for VTX-FS-NO-EQ and VTX-RS-NO-EQ are made using the 64-zeroes/64-ones pattern in the compliance
pattern.
2. Voltage limits comprehend both full swing and reduced swing modes. The transmitter must reject any changes that would
violate this specification. The maximum level is covered in the VTX-FS-NO-EQ measurement which represents the maximum
peak voltage the transmitter can drive. The VTX-EIEOS-FS and VTX-EIEOS-RS voltage limits are imposed to guarantee the EIEOS
threshold of 175 mVP-P at the receiver pin. This parameter is measured using the actual EIEOS pattern that is part of the
compliance pattern and then removing the ISI contribution of the breakout channel.
3.19.4.4 PCI Express DC physical layer receiver specifications

This section discusses the PCI Express DC physical layer receiver specifications for 2.5
GT/s, 5 GT/s and 8 GT/s.
This table defines the DC specifications for the PCI Express 2.0 (2.5 GT/s) differential
input at all receivers. The parameters are specified at the component pins.
Table 67. PCI Express 2.0 (2.5 GT/s) differential receiver input DC specifications (SVDD = 1.0
V)4
Parameter Symbol Min Typ Max Units Notes
Differential input peak-to-peak VRX-DIFFp-p 120 1000 1200 mV VRX-DIFFp-p = 2 x |VRX-D+ - VRX-D-| See
voltage Note 1.

Table 67. PCI Express 2.0 (2.5 GT/s) differential receiver input DC specifications (SVDD = 1.0
V)4 (continued)
DC differential input impedance ZRX-DIFF-DC 80 100 120 Ω Receiver DC differential mode
impedance. See Note 2
DC input impedance ZRX-DC 40 50 60 Ω Required receiver D+ as well as D- DC
Impedance (50 ± 20% tolerance). See
Notes 1 and 2.
Powered down DC input impedance ZRX-HIGH-IMP-DC 50 - - kΩ Required receiver D+ as well as D- DC
Impedance when the receiver
terminations do not have power. See
Note 3.
Electrical idle detect threshold VRX-IDLE-DET- 65 - 175 mV VRX-IDLE-DET-DIFFp-p = 2 x |VRX-D+ -VRX-
DIFFp-p D-|
Measured at the package pins of the

receiver
Notes:
1. Measured at the package pins with a test load of 50Ω to GND on each pin.
2. Impedance during all LTSSM states. When transitioning from a fundamental reset to detect (the initial state of the LTSSM)
there is a 5 ms transition time before receiver termination values must be met on all unconfigured lanes of a port.
3. The receiver DC common mode impedance that exists when no power is present or fundamental reset is asserted. This
helps ensure that the receiver detect circuit does not falsely assume a receiver is powered on when it is not. This term must
be measured at 300 mV above the receiver ground.
This table defines the DC specifications for the PCI Express 2.0 (5 GT/s) differential
Table 68. PCI Express 2.0 (5 GT/s) differential receiver input DC specifications (SVDD = 1.0
V)4
Differential input peak-to-peak voltage VRX-DIFFp-p 120 1000 1200 mV VRX-DIFFp-p = 2 x |VRX-D+ - VRX-D-|
See Note 1.
DC input impedance ZRX-DC 40 50 60 Ω Required receiver D+ as well as D-
DC Impedance (50 ± 20%
tolerance). See Notes 1 and 2.
Powered down DC input impedance ZRX-HIGH-IMP-DC 50 - - kΩ Required receiver D+ as well as D-
DC Impedance when the receiver
terminations do not have power.
See Note 3.
Electrical idle detect threshold VRX-IDLE-DET- 65 - 175 mV VRX-IDLE-DET-DIFFp-p = 2 x |VRX-D+ -
DIFFp-p VRX-D-|
Measured at the package pins of
the receiver

V)4 (continued)
Notes:
1. Measured at the package pins with a test load of 50 Ω to GND on each pin.
This table defines the DC specifications for the PCI Express 3.0 (8 GT/s) differential
V)6
DC input impedance ZRX-DC 40 50 60 Ω Required receiver D+ as well as D-
DC Impedance (50 ± 20%
tolerance). See Notes 1 and 2.
Powered down DC input impedance ZRX-HIGH-IMP-DC 50 - - kΩ Required receiver D+ as well as D-
DC Impedance when the receiver
terminations do not have power.
See Note 3.
Generator launch voltage VRX-LAUNCH-8G - 800 - mV Measured at TP1 per PCI Express
base spec. rev 3.0
Eye height (-20dB Channel) VRX-SV-8G 25 - - mV Measured at TP2P per PCI Express
base spec. rev 3.0. See Notes 4, 5
Electrical idle detect threshold VRX-IDLE-DET- 65 - 175 mV VRX-IDLE-DET-DIFFp-p = 2 x |VRX-D+ -
DIFFp-p VRX-D-|
Measured at the package pins of
the receiver
Notes:
1. Measured at the package pins with a test load of 50Ω to GND on each pin.

V)6
4. VRX-SV-8G is tested at three different voltages to ensure the receiver device under test is capable of equalizing over a range
of channel loss profiles. The "SV" in the parameter names refers to stressed voltage.
5. VRX-SV-8G is referenced to TP2P and is obtained after post processing data captured at TP2.
3.19.4.5 PCI Express AC physical layer specifications

This section contains the AC specifications for the physical layer of PCI Express on this
device.
3.19.4.5.1 PCI Express AC physical layer transmitter specifications

This section discusses the PCI Express AC physical layer transmitter specifications for
2.5 GT/s, 5 GT/s and 8 GT/s.
This table defines the PCI Express 2.0 (2.5 GT/s) AC specifications for the differential
output at all transmitters. The parameters are specified at the component pins. The AC
timing specifications do not include RefClk jitter.
Table 70. PCI Express 2.0 (2.5 GT/s) differential transmitter output AC specifications4
Unit interval UI 399.88 400 400.12 ps Each UI is 400 ps ± 300 ppm. UI does not
account for spread-spectrum clock dictated
variations.
Minimum transmitter eye TTX-EYE 0.75 - - UI The maximum transmitter jitter can be
width derived as TTX-MAX-JITTER = 1 - TTX-EYE =
0.25 UI. Does not include spread-spectrum
or RefCLK jitter. Includes device random
jitter at 10-12.
See Notes 1 and 2.
Maximum time between the TTX-EYE-MEDIAN- - - 0.125 UI Jitter is defined as the measurement
jitter median and maximum to- MAX-JITTER variation of the crossing points (VTX-DIFFp-p =
deviation from the median 0 V) in relation to a recovered transmitter
UI. A recovered transmitter UI is calculated
over 3500 consecutive unit intervals of
sample data. Jitter is measured using all
edges of the 250 consecutive UI in the
center of the 3500 UI used for calculating
the transmitter UI. See Notes 1 and 2.
AC coupling capacitor CTX 75 - 200 nF All transmitters must be AC coupled. The
AC coupling is required either within the
media or within the transmitting component
itself. See Note 3.

Table 70. PCI Express 2.0 (2.5 GT/s) differential transmitter output AC specifications4
(continued)
Notes:
1. Specified at the measurement point into a timing and voltage test load as shown in Figure 40 and measured over any 250
consecutive transmitter UIs.
2. A TTX-EYE = 0.75 UI provides for a total sum of deterministic and random jitter budget of TTX-JITTER-MAX = 0.25 UI for the
transmitter collected over any 250 consecutive transmitter UIs. The TTX-EYE-MEDIAN-to-MAX-JITTER median is less than half of the
total transmitter jitter budget collected over any 250 consecutive transmitter UIs. It must be noted that the median is not the
same as the mean. The jitter median describes the point in time where the number of jitter points on either side is
approximately equal as opposed to the averaged time value.
3. The chip's SerDes transmitter does not have CTX built-in. An external AC coupling capacitor is required.
This table defines the PCI Express 2.0 (5 GT/s) AC specifications for the differential
Table 71. PCI Express 2.0 (5 GT/s) differential transmitter output AC specifications3
Unit Interval UI 199.94 200.00 200.06 ps Each UI is 200 ps ± 300 ppm. UI does not
account for spread-spectrum clock dictated
variations.
Minimum transmitter eye width TTX-EYE 0.75 - - UI The maximum transmitter jitter can be
derived as: TTX-MAX-JITTER = 1 - TTX-EYE =
0.25 UI.
See Note 1.
Transmitter RMS deterministic TTX-HF-DJ-DD - - 0.15 ps -
jitter > 1.5 MHz
AC coupling capacitor CTX 75 - 200 nF All transmitters must be AC coupled. The
AC coupling is required either within the
media or within the transmitting component
itself. See Note 2.
Notes:
1. Specified at the measurement point into a timing and voltage test load as shown in Figure 40 and measured over any 250
consecutive transmitter UIs.
This table defines the PCI Express 3.0 (8 GT/s) AC specifications for the differential

Table 72. PCI Express 3.0 (8 GT/s) differential transmitter output AC specifications4
Unit Interval UI 124.9625 125.00 125.0375 ps Each UI is 125 ps ± 300 ppm. UI does
not account for spread-spectrum clock
dictated variations.
Transmitter uncorrelated total TTX-UTJ - - 31.25 ps p-p -
jitter
Transmitter uncorrelated TTX-UDJ-DD - - 12 ps p-p -
deterministic jitter
Total uncorrelated pulse width TTX-UPW-TJ - - 24 ps p-p See Note 1, 2
jitter (PWJ)
Deterministic data dependent TTX-UPW-DJDD - - 10 ps p-p See Note 1, 2
jitter (DjDD) uncorrelated
pulse width jitter (PWJ)
Data dependent jitter TTX-DDJ - - 18 ps p-p See Note 2
AC coupling capacitor CTX 176 - 265 nF All transmitters must be AC coupled.
The AC coupling is required either
within the media or within the
transmitting component itself. See
Note 3.
Notes:
1. PWJ parameters shall be measured after data dependent jitter (DDJ) separation.
2. Measured with optimized preset value after de-embedding to transmitter pin.
3.19.4.5.2 PCI Express AC physical layer receiver specifications

This section discusses the PCI Express AC physical layer receiver specifications for 2.5
GT/s, 5 GT/s and 8 GT/s.
This table defines the AC specifications for the PCI Express 2.0 (2.5 GT/s) differential
input at all receivers. The parameters are specified at the component pins. The AC timing
specifications do not include RefClk jitter.
Table 73. PCI Express 2.0 (2.5 GT/s) differential receiver input AC specifications4
Unit Interval UI 399.88 400.00 400.12 ps Each UI is 400 ps ± 300 ppm. UI does not
account for spread-spectrum clock
dictated variations.
Minimum receiver eye width TRX-EYE 0.4 - - UI The maximum interconnect media and
transmitter jitter that can be tolerated by
the receiver can be derived as TRX-MAX-
JITTER = 1 - TRX-EYE= 0.6 UI.
See Notes 1 and 2.

Table 73. PCI Express 2.0 (2.5 GT/s) differential receiver input AC specifications4
(continued)
Maximum time between the TRX-EYE-MEDIAN- - - 0.3 UI Jitter is defined as the measurement
jitter median and maximum to-MAX-JITTER variation of the crossing points (VRX-DIFFp-p
deviation from the median. = 0 V) in relation to a recovered
transmitter UI. A recovered transmitter UI
is calculated over 3500 consecutive unit
intervals of sample data. Jitter is
measured using all edges of the 250
consecutive UI in the center of the 3500
UI used for calculating the transmitter UI.
See this table notes.
Notes:
1. Specified at the measurement point and measured over any 250 consecutive UIs. The test load in Figure 40 must be used
as the receiver device when taking measurements. If the clocks to the receiver and transmitter are not derived from the same
reference clock, the transmitter UI recovered from 3500 consecutive UI must be used as a reference for the eye diagram.
2. A TRX-EYE = 0.40 UI provides for a total sum of 0.60 UI deterministic and random jitter budget for the transmitter and
interconnect collected any 250 consecutive UIs. The TRX-EYE-MEDIAN-to-MAX-JITTER specification ensures a jitter
distribution in which the median and the maximum deviation from the median is less than half of the total. UI jitter budget
collected over any 250 consecutive transmitter UIs. It must be noted that the median is not the same as the mean. The jitter
median describes the point in time where the number of jitter points on either side is approximately equal as opposed to the
averaged time value. If the clocks to the receiver and transmitter are not derived from the same reference clock, the
transmitter UI recovered from 3500 consecutive UI must be used as the reference for the eye diagram.
3. It is recommended that the recovered transmitter UI is calculated using all edges in the 3500 consecutive UI interval with a
fit algorithm using a minimization merit function. Least squares and median deviation fits have worked well with experimental
and simulated data.
5. The TRX-EYE-MEDIAN-to-MAX-JITTER for common and separated reference clock architecture.

6. If spread spectrum clocking is desired, common clock receiver architecture must be used.
7. The AC specifications do not include Refclk jitter.
This table defines the AC specifications for the PCI Express 2.0 (5 GT/s) differential
Table 74. PCI Express 2.0 (5 GT/s) differential receiver input AC specifications1
Unit Interval UI 199.40 200.00 200.06 ps 1, 2
Max receiver inherent timing error TRX-TJ-CC - - 0.4 UI 3, 5, 6
Max receiver inherent deterministic timing TRX-DJ-DD-CC - - 0.30 UI 4, 5, 6
error
Note:
1. Each UI is 200 ps ± 300 ppm. UI does not account for spread-spectrum clock dictated variations.
3. The maximum inherent total timing error for common and separated RefClk receiver architecture.

4. The maximum inherent deterministic timing error for common and separated RefClk receiver architecture.
5. If spread spectrum clocking is desired, common clock must be used.
This table defines the AC specifications for the PCI Express 3.0 (8 GT/s) differential
Unit Interval UI 124.9625 125.00 125.0375 ps Each UI is 125 ps ± 300 ppm. UI
does not account for spread-
spectrum clock dictated variations.
See Note 1.
Eye Width at TP2P TRX-SV-8G 0.3 - 0.35 UI See Note 1
Differential mode interference VRX-SV-DIFF-8G 14 - - mV Frequency = 2.1GHz. See Note 2.

Sinusoidal Jitter at 100 MHz TRX-SV-SJ-8G - - 0.1 UI p-p Fixed at 100 MHz. See Note 3.
Random Jitter TRX-SV-RJ-8G - - 2.0 ps Random jitter spectrally flat before
RMS filtering. See Note 4.
Note:
1. TRX-SV-8G is referenced to TP2P and obtained after post processing data captured at TP2. TRX-SV-8G includes the effects of
applying the behavioral receiver model and receiver behavioral equalization.
2. VRX-SV-DIFF-8G voltage may need to be adjusted over a wide range for the different loss calibration channels.
3. The sinusoidal jitter in the total jitter tolerance may have any amplitude and frequency as shown in Figure 39.
4. Random jitter (Rj) is applied over the following range: The low frequency limit may be between 1.5 and 10 MHz, and the
upper limit is 1.0 GHz. See Figure 39 for details. Rj may be adjusted to meet the 0.3 UI value for TRX-SV-8G.

0.03 MHz 100 MHz
Sj sweep range
1.0 UI
20 dB
Rj (ps RMS)
Sj (UI PP)
decade
Sj
0.1 UI
Rj
~ 3.0 ps RMS
0.01 MHz 0.1 MHz 1.0 MHz 10 MHz 100 MHz 1000 MHz
Figure 39. Swept sinusoidal jitter mask
3.19.4.6 Test and measurement load

The AC timing and voltage parameters must be verified at the measurement point. The
package pins of the device must be connected to the test/measurement load within 0.2
inches of that load, as shown in the following figure.
NOTE
The allowance of the measurement point to be within 0.2 inches
of the package pins is meant to acknowledge that package/
board routing may benefit from D+ and D- not being exactly
matched in length at the package pin boundary. If the vendor
does not explicitly state where the measurement point is
located, the measurement point is assumed to be the D+ and D-
package pins.

D + package pin
C = CTX
Transmitter
silicon
+ package
C = CTX
D - package pin
R = 50 Ω R = 50 Ω
Figure 40. Test/measurement load
3.19.5 Serial RapidIO (sRIO)

This section describes the DC and AC electrical specifications for the serial RapidIO
interface of the LP-Serial physical layer. The electrical specifications cover both single
and multiple-lane links. Two transmitters (short run and long run) and a single receiver
are specified for each of three baud rates: 2.50, 3.125 and 5 GBaud.
Two transmitter specifications allow for solutions ranging from simple board-to-board
interconnect to driving two connectors across a backplane. A single receiver specification
is given that accepts signals from both the short run and long run transmitter
specifications.
The short run transmitter must be used mainly for chip-to-chip connections on either the
same printed circuit board or across a single connector. This covers the case where
connections are made to a mezzanine (daughter) card. The minimum swings of the short
run specification reduce the overall power used by the transceivers.
The long run transmitter specifications use larger voltage swings that are capable of
driving signals across backplanes. This allows a user to drive signals across two
connectors and a backplane.
All unit intervals are specified with a tolerance of ± 100 ppm. The worst case frequency
difference between any transmit and receive clock is 200 ppm.
To ensure interoperability between drivers and receivers of different vendors and
technologies, AC coupling at the receiver input must be used.

3.19.5.1 Signal definitions

This section defines the terms used in the description and specification of the differential
signals used by the LP-Serial links. The following figure shows how the signals are
defined. The figures show waveforms for either a transmitter output (TD and TD_B) or a
receiver input (RD and RD_B). Each signal swings between A volts and B volts where A
> B. Using these waveforms, the definitions are as follows:
• The transmitter output signals and the receiver input signals-TD, TD_B, RD, and
RD_B-each have a peak-to-peak swing of A - B volts.
• The differential output signal of the transmitter, VOD, is defined as VTD - VTD_B
• The differential input signal of the receiver, VID, is defined as VRD - VRD_B
• The differential output signal of the transmitter and the differential input signal of the
receiver each range from A - B to -(A - B) volts
• The peak value of the differential transmitter output signal and the differential
receiver input signal is A - B volts.
• The peak-to-peak value of the differential transmitter output signal and the
differential receiver input signal is 2 x (A - B) volts.
TD or RD
A volts
TD or RD
B volts
Differential peak-to-peak = 2 x (A - B)
Figure 41. Differential peak-to-peak voltage of transmitter or receiver
To illustrate these definitions using real values, consider the case of a CML (current
mode logic) transmitter that has a common mode voltage of 2.25 V, and each of its
outputs TD and TD_B, has a swing that goes between 2.5 V and 2.0 V. Using these
values, the peak-to-peak voltage swing of the signals TD and TD_B is 500 mV p-p. The
differential output signal ranges between 500 mV and -500 mV. The peak differential
voltage is 500 mV. The peak-to-peak differential voltage is 1000 mV p-p.
3.19.5.2 Equalization
With the use of high-speed serial links, the interconnect media causes degradation of the
signal at the receiver and produces effects such as inter-symbol interference (ISI) or data-
dependent jitter. This loss can be large enough to degrade the eye opening at the receiver
beyond what is allowed in the specification. To negate a portion of these effects,

equalization can be used. The most common equalization techniques that can be used are
as follows:
• Pre-emphasis on the transmitter
• A passive high-pass filter network placed at the receiver, often referred to as passive
equalization.
• The use of active circuits in the receiver, often referred to as adaptive equalization.
3.19.5.3 Serial RapidIO clocking requirements for SDn_REF_CLKn and

SDn_REF_CLKn_B
SerDes 3 and SerDes 4 (SD[3:4]_REF_CLK[1:2] and SD[3:4]_REF_CLK[1:2]_B) may
be used for various SerDes serial RapidIO configurations based on the RCW
Configuration field SRDS_PRTCL. Serial RapidIO is not supported on SerDes 1 and 2.
The ref clock frequency tolerance spec is ±100ppm.
3.19.5.4 DC requirements for serial RapidIO

This section explains the DC requirements for the serial RapidIO interface.
3.19.5.4.1 DC serial RapidIO transmitter specifications

This table defines the transmitter DC specifications for serial RapidIO operating at 2.5
and 3.125 GBaud.
Table 76. Serial RapidIO transmitter DC specifications-2.5 GBaud, 3.125 GBaud2
Long-run differential output voltage VDIFFPP 800 - 1600 mV p-p -
Short-run differential output voltage VDIFFPP 500 - 1000 mV p-p -
DC Differential transmitter impedance ZTX-DIFF-DC 80 100 120 Ω Transmitter DC differential
impedance
Notes:
1. Voltage relative to COMMON of either signal comprising a differential pair
This table defines the transmitter DC specifications for serial RapidIO operating at 5
GBaud.

Table 77. Serial RapidIO transmitter DC specifications-5 GBaud1

Long-run differential output voltage VDIFF 800 - 1200 mV -
Short-run differential output voltage VDIFF 400 - 750 mV -
Long-run de-emphasized differential output voltage (ratio) VTX-DE-RATIO-3.5dB 3 3.5 4 dB -
Long-run de-emphasized differential output voltage (ratio) VTX-DE-RATIO-6.0dB 5.5 6.0 6.5 dB -
Differential resistance TRD 80 100 120 Ω -
Notes:
3.19.5.4.2 DC serial RapidIO receiver specifications

LP-Serial receiver electrical and timing specifications are stated in the text and tables of
this section.
Receiver input impedance results in a differential return loss better than 10 dB and a
common mode return loss better than 6 dB from 100 MHz to (0.8) x (Baud Frequency).
This includes contributions from on-chip circuitry, the chip package, and any off-chip
components related to the receiver. AC coupling components are included in this
requirement. The reference impedance for return loss measurements is 100-Ω resistive for
differential return loss and 25-Ω resistive for common mode.
This table defines the receiver DC specifications for serial RapidIO operating at 2.5 and
3.125 GBaud.
Table 78. Serial RapidIO receiver DC specifications-2.5 GBaud, 3.125 GBaud2
Differential input voltage VIN 200 - 1600 mV p-p 1
DC differential receiver input impedance ZRX-DIFF-DC 80 100 120 Ω Receiver DC differential
impedance
Notes:
1. Measured at the receiver
This table defines the receiver DC specifications for serial RapidIO operating at 5
GBaud.

Table 79. Serial RapidIO receiver DC specifications-5 GBaud2

Long-run differential input voltage VDIFF - - 1200 mV 1
Short-run differential input voltage VDIFF 125 - 1200 mV 1

Differential resistance RRD 80 - 120 Ω -
Notes:
1. Measured at the receiver.
3.19.5.5 AC requirements for serial RapidIO

This section explains the AC requirements for the serial RapidIO interface.
3.19.5.5.1 AC requirements for serial RapidIO transmitter

This table defines the transmitter AC specifications for the serial RapidIO operating at
2.5 and 3.125 GBaud. The AC timing specifications do not include RefClk jitter.
Table 80. Serial RapidIO transmitter, 2.5 GBaud and 3.125 GBaud, AC timing specifications1
Parameter Symbol Min Typical Max Unit
Deterministic jitter JD - - 0.17 UI p-p
Total jitter JT - - 0.35 UI p-p
Unit Interval: 2.5 GBaud UI 400 - 100ppm 400 400 + 100ppm ps
Unit Interval: 3.125 GBaud UI 320 - 100ppm 320 320 + 100ppm ps
Notes:
This table defines the transmitter AC specifications for the serial RapidIO operating at 5
GBaud, short range. The AC timing specifications do not include RefClk jitter.
Table 81. Serial RapidIO transmitter, 5 GBaud, AC timing specifications1
Baud rate TBAUD 5.000 - 100ppm 5.000 5.000 + GBaud
100ppm
Uncorrelated high probability jitter TUHPJ - - 0.155 UI p-p
Total jitter TJ - - 0.30 UI p-p
Notes:

This table defines the receiver AC specifications for serial RapidIO operating at 2.5 and
3.125 GBaud. The AC timing specifications do not include RefClk jitter.
Table 82. Serial RapidIO receiver, 2.5 GBaud and 3.125 GBaud, AC timing specifications3
Deterministic jitter tolerance JD - - 0.37 UI p-p 1
Combined deterministic and random JDR - - 0.55 UI p-p 1

jitter tolerance
Total jitter tolerance2 JT - - 0.65 UI p-p 1
Bit error rate BER - - 10-12 - -
Unit Interval: 2.5 GBaud UI 400 - 100ppm 400 400 + 100ppm ps -
Unit Interval: 3.125 GBaud UI 320 - 100ppm 320 320 + 100ppm ps -
Notes:
1. Measured at receiver
2. Total jitter is composed of three components: deterministic jitter, random jitter and single frequency sinusoidal jitter. The
sinusoidal jitter may have any amplitude and frequency in the unshaded region of Figure 42. The sinusoidal jitter component
is included to ensure margin for low-frequency jitter, wander, noise, crosstalk, and other variable system effects.
This figure shows the single-frequency sinusoidal jitter limits for 2.5 GBaud and 3.125
GBaud rates.

8.5 UI p-p
Sinuosidal
Jitter 20 dB/dec
Amplitude
0.10 UI p-p
baud/142000 Frequency baud/1667 20 MHz
Figure 42. Single-frequency sinusoidal jitter limits, substitute the baud parameter in this
figure by either 2.5G or 3.125G.
This table defines the receiver AC specifications for serial RapidIO operating at 5
GBaud. The AC timing specifications do not include RefClk jitter.
Table 83. Serial RapidIO receiver, 5G Baud, AC timing specifications1
Receiver baud rate RBAUD 5.000 - 100ppm 5.000 5.000 + 100ppm Gbaud -
Long-run Gaussian jitter RGJ - - 0.2 UI p-p 2
Long-Run Uncorrelated bounded high RUHPJ - - 0.12 UI p-p 2, 3
probability jitter
Long-run correlated bounded high probability RCBHPJ - - 0.63 UI p-p 2, 4
jitter
Short-run correlated bounded high probability RCBHPJ - - 0.30 UI p-p 2, 4
jitter
Long-run bounded high probability jitter RBHPJ - - 0.75 UI p-p 3, 4
Short-run bounded high probability jitter RBHPJ - - 0.45 UI p-p 3, 4
Sinusoidal jitter, maximum RSJ-max - - 5.00 UI p-p -
Sinusoidal jitter, high frequency RSJ-hf - - 0.05 UI p-p -
Long-run total jitter (does not include RTj - - 0.95 UI p-p 3, 4
sinusoidal jitter)
Short-run total jitter (does not include RTj - - 0.60 UI p-p 3, 4
sinusoidal jitter)

Table 83. Serial RapidIO receiver, 5G Baud, AC timing specifications1 (continued)

Notes:
3. The jitter (RUHPJ ) is Bounded High Probability Jitter and is commonly caused by crosstalk coupling and can have periodic
and bounded PRBS jitter subcomponents.
4. The jitter (RCBHPJ ) and amplitude have to be correlated, for example by a PCB trace.
This figure shows the single-frequency sinusoidal jitter limits for 5 GBaud rate.
5 UI p-p
Sinuosidal
Jitter 20 dB/dec
Amplitude
0.05 UI p-p
35.2 kHz Frequency 3 MHz 20 MHz
Figure 43. Single-frequency sinusoidal jitter limits
3.19.6 XAUI interface

This section describes the DC and AC electrical specifications for the XAUI bus.
3.19.6.1 XAUI DC electrical characteristics

This section discusses the XAUI DC electrical characteristics for the clocking signals,
transmitter, and receiver.
3.19.6.1.1 DC requirements for XAUI SDn_REF_CLKn and SDn_REF_CLKn_B

Only SerDes 1-2 (SD[1:2]_REF_CLK[1:2] and SD[1:2]_REF_CLK[1:2]_B) may be used
for various SerDes XAUI configurations based on the RCW Configuration field
SRDS_PRTCL. The ref clock frequency tolerance spec is ±100ppm.
3.19.6.1.2 XAUI transmitter DC electrical characteristics

This table defines the XAUI transmitter DC electrical characteristics.
Table 84. XAUI transmitter DC electrical characteristics (XVDD = 1.35V or 1.5V)1
Differential output voltage VDIFFPP 800 1000 1600 mV p-p -
DC Differential transmitter impedance ZTX-DIFF-DC 80 100 120 Ω 3

2. Absolute output voltage limit
3. Transmitter DC differential impedance
3.19.6.1.3 XAUI receiver DC electrical characteristics

This table defines the XAUI receiver DC electrical characteristics.
Table 85. XAUI receiver DC timing specifications (SVDD = 1.0 V)1
DC Differential receiver input ZRX-DIFF-DC 80 100 120 Ω 3

impedance

2. Measured at the receiver.
3. Receiver DC differential impedance
3.19.6.2 XAUI AC timing specifications

This section explains the AC requirements for the XAUI interface.

3.19.6.2.1 XAUI transmitter AC timing specifications

This table defines the XAUI transmitter AC timing specifications. RefClk jitter is not
included.
Table 86. XAUI transmitter AC timing specifications 1
Unit Interval: 3.125 Gb/s UI 320 - 100 ppm 320 320 + 100 ppm ps
3.19.6.2.2 XAUI receiver AC timing specifications

This table defines the receiver AC specifications for XAUI. RefClk jitter is not included.
Table 87. XAUI receiver AC timing specifications3

jitter tolerance
Total jitter tolerance JT - - 0.65 UI p-p 1, 2

Unit Interval: 3.125 Gb/s UI 320 - 100 ppm 320 320 + 100 ppm ps -
Notes:
1. Measured at receiver.
2. Total jitter is composed of three components: deterministic jitter, random jitter, and single frequency sinusoidal jitter. The
is included to ensure margin for low frequency jitter, wander, noise, crosstalk, and other variable system effects.
3.19.7 Aurora interface

This section describes the Aurora clocking requirements and its DC and AC electrical
characteristics.

3.19.7.1 Aurora clocking requirements for SDn_REF_CLKn and

SDn_REF_CLKn_B
Only SerDes 4 (SD4_REF_CLK[1:2] and SD4_REF_CLK[1:2]_B) may be used for
SerDes Aurora configurations based on the RCW Configuration field SRDS_PRTCL.
The ref clock frequency tolerance spec is ±100ppm. Aurora is not supported on SerDes
1-3.
3.19.7.2 Aurora DC electrical characteristics

This section describes the DC electrical characteristics for the Aurora interface.
3.19.7.2.1 Aurora transmitter DC electrical characteristics

This table defines the Aurora transmitter DC electrical characteristics.
Table 88. Aurora transmitter DC electrical characteristics (XVDD = 1.35 V or 1.5 V) 1
Differential output voltage VDIFFPP 800 1000 1600 mV p-p
DC Differential transmitter impedance ZTX-DIFF-DC 80 100 120 Ω
3.19.7.2.2 Aurora receiver DC electrical characteristics

This table defines the Aurora receiver DC electrical characteristics for the Aurora
interface.
Table 89. Aurora receiver DC electrical characteristics (SVDD = 1.0V)1
DC Differential receiver impedance ZRX-DIFF-DC 80 100 120 Ω 3
Notes:
3. DC Differential receiver impedance

3.19.7.3 Aurora AC timing specifications

This section describes the AC timing specifications for Aurora.
3.19.7.3.1 Aurora transmitter AC timing specifications

This table defines the Aurora transmitter AC timing specifications. RefClk jitter is not
included.
Table 90. Aurora transmitter AC timing specifications1
Unit interval: 2.5 Gbps UI 400 - 100 ppm 400 400 + 100 ppm ps
Notes:
3.19.7.3.2 Aurora receiver AC timing specifications

This table defines the Aurora receiver AC timing specifications. RefClk jitter is not
included.
Table 91. Aurora receiver AC timing specifications3

jitter tolerance

Unit Interval: 2.5 Gbps UI 400 - 100 ppm 400 400 + 100 ppm ps -
Notes:
is included to ensure margin for low frequency jitter, wander, noise, crosstalk and other variable system effects.

3.19.8 Serial ATA (SATA) interface

This section describes the DC and AC electrical specifications for the serial ATA
(SATA) interface.
3.19.8.1 SATA DC electrical characteristics

This section describes the DC electrical characteristics for SATA.
3.19.8.1.1 SATA DC transmitter output characteristics

This table provides the differential transmitter output DC characteristics for the SATA
interface at Gen1i/1m or 1.5 Gbps transmission.
Table 92. Gen1i/1m 1.5G transmitter DC specifications (XVDD = 1.35 V or 1.5 V)3
Tx differential output voltage VSATA_TXDIFF 400 500 600 mV p-p 1
Tx differential pair impedance ZSATA_TXDIFFIM 85 100 115 Ω 2

Notes:
1. Terminated by 50 Ω load
2. DC impedance
This table provides the differential transmitter output DC characteristics for the SATA
interface at Gen2i/2m or 3.0 Gbps transmission.
Table 93. Gen 2i/2m 3G transmitter DC specifications (XVDD = 1.35 V or 1.5 V)2
Transmitter differential output voltage VSATA_TXDIFF 400 - 700 mV p-p 1
Transmitter differential pair impedance ZSATA_TXDIFFIM 85 100 115 Ω -

Notes:
1. Terminated by 50 Ω load.
3.19.8.1.2 SATA DC receiver input characteristics

This table provides the Gen1i/1m or 1.5 Gbps differential receiver input DC
characteristics for the SATA interface.

Table 94. Gen1i/1m 1.5 G receiver input DC specifications (SVDD = 1.0 V)3
Differential input voltage VSATA_RXDIFF 240 500 600 mV p-p 1
Differential receiver input impedance ZSATA_RXSEIM 85 100 115 Ω 2
OOB signal detection threshold VSATA_OOB 50 120 240 mV p-p -
Notes:
1. Voltage relative to common of either signal comprising a differential pair
2. DC impedance
This table provides the Gen2i/2m or 3 Gbps differential receiver input DC characteristics
for the SATA interface.
Table 95. Gen2i/2m 3 G receiver input DC specifications (SVDD = 1.0 V)3
Differential input voltage VSATA_RXDIFF 240 - 750 mV p-p 1
Differential receiver input impedance ZSATA_RXSEIM 85 100 115 Ω 2
OOB signal detection threshold VSATA_OOB 75 120 240 mV p-p 2
Notes:
1. Voltage relative to common of either signal comprising a differential pair
2. DC impedance
3.19.8.2 SATA AC timing specifications

This section discusses the SATA AC timing specifications.
3.19.8.2.1 AC requirements for SATA REF_CLK

The AC requirements for the SATA reference clock listed in this table are to be
guaranteed by the customer's application design. SATA does not support TX Spread
Spectrum Clock as it is an optional requirement in protocol. However T4 SATA supports
RX spread spectrum data as it is required in the SATA standard that all SATA Receivers
handle spread spectrum. SerDes can receive spread spectrum without affecting other
protocols since this doesn’t affect SerDes PLL.

Table 96. SATA reference clock input requirements6

SDn_REF_CLKn/SDn_REF_CLKn_B tCLK_REF - 100/125 - MHz 1
frequency range
SDn_REF_CLKn/SDn_REF_CLKn_B clock tCLK_TOL -350 - +350 ppm -
frequency tolerance
SDn_REF_CLKn/SDn_REF_CLKn_B reference tCLK_DUTY 40 50 60 % 5
clock duty cycle
SDn_REF_CLKn/SDn_REF_CLKn_B cycle-to- tCLK_CJ - - 100 ps 2
cycle clock jitter (period jitter)
SDn_REF_CLKn/SDn_REF_CLKn_B total tCLK_PJ -50 - +50 ps 2, 3, 4
reference clock jitter, phase jitter (peak-to-peak)
Notes:
1. Caution: Only 100 and 125MHz have been tested. In-between values do not work correctly with the rest of the system.
2. At RefClk input
3. In a frequency band from 150 kHz to 15 MHz at BER of 10-12
4. Total peak-to-peak deterministic jitter must be less than or equal to 50 ps.
5. Measurement taken from differential waveform
3.19.8.3 AC transmitter output characteristics

This table provides the differential transmitter output AC characteristics for the SATA
interface at Gen1i/1m or 1.5 Gbps transmission. The AC timing specifications do not
include RefClk jitter.
Table 97. Gen1i/1m 1.5 G transmitter AC specifications2
Channel speed tCH_SPEED - 1.5 - Gbps -
Unit Interval TUI 666.4333 666.6667 670.2333 ps -
Total jitter data-data 5 UI USATA_TXTJ5UI - - 0.355 UI p-p 1
Total jitter, data-data 250 UI USATA_TXTJ250UI - - 0.47 UI p-p 1
Deterministic jitter, data-data 5 UI USATA_TXDJ5UI - - 0.175 UI p-p 1
Deterministic jitter, data-data 250 UI USATA_TXDJ250UI - - 0.22 UI p-p 1
Notes:
1. Measured at transmitter output pins peak to peak phase variation, random data pattern
This table provides the differential transmitter output AC characteristics for the SATA

Table 98. Gen 2i/2m 3 G transmitter AC specifications2

Channel speed tCH_SPEED - 3.0 - Gbps -
Total jitter fC3dB = fBAUD ÷ 500 USATA_TXTJfB/500 - - 0.37 UI p-p 1
Total jitter fC3dB = fBAUD ÷ 1667 USATA_TXTJfB/1667 - - 0.55 UI p-p 1
Deterministic jitter, fC3dB = fBAUD ÷ 500 USATA_TXDJfB/500 - - 0.19 UI p-p 1
Deterministic jitter, fC3dB = fBAUD ÷ USATA_TXDJfB/1667 - - 0.35 UI p-p 1
1667
Notes:
1. Measured at transmitter output pins peak-to-peak phase variation, random data pattern
3.19.8.4 AC differential receiver input characteristics

This table provides the Gen1i/1m or 1.5 Gbps differential receiver input AC
characteristics for the SATA interface. The AC timing specifications do not include
RefClk jitter.
Table 99. Gen 1i/1m 1.5G receiver AC specifications2
Total jitter data-data 5 UI USATA_RXTJ5UI - - 0.43 UI p-p 1
Total jitter, data-data 250 UI USATA_RXTJ250UI - - 0.60 UI p-p 1
Deterministic jitter, data-data 5 UI USATA_RXDJ5UI - - 0.25 UI p-p 1
Deterministic jitter, data-data 250 UI USATA_RXDJ250UI - - 0.35 UI p-p 1
Notes:
1. Measured at receiver.
This table provides the differential receiver input AC characteristics for the SATA
Table 100. Gen 2i/2m 3G receiver AC specifications2
Total jitter fC3dB = fBAUD ÷ 500 USATA_RXTJfB/500 - - 0.60 UI p-p 1
Total jitter fC3dB = fBAUD ÷ 1667 USATA_RXTJfB/1667 - - 0.65 UI p-p 1
Deterministic jitter, fC3dB = fBAUD ÷ 500 USATA_RXDJfB/500 - - 0.42 UI p-p 1

Table 100. Gen 2i/2m 3G receiver AC specifications2 (continued)

Deterministic jitter, fC3dB = fBAUD ÷ 1667 USATA_RXDJfB/1667 - - 0.35 UI p-p 1
Notes:
3.19.9 SGMII interface

Each SGMII port features a 4-wire AC-coupled serial link from the SerDes interface of
the chip, as shown in Figure 44, where CTX is the external (on board) AC-coupled
capacitor. Each SerDes transmitter differential pair features 100-Ω output impedance.
Each input of the SerDes receiver differential pair features 50-Ω on-die termination to
XGNDn. The reference circuit of the SerDes transmitter and receiver is shown in Figure
38.
3.19.9.1 SGMII clocking requirements for SDn_REF_CLKn and

SDn_REF_CLKn_B
When operating in SGMII mode, the ECn_GTX_CLK125 clock is not required for this
port. Instead, a SerDes reference clock is required on SD[1:2]_REF_CLK[1:2] and
SD[1:2]_REF_CLK[1:2]_Bpins. SerDes 1-2 may be used for SerDes SGMII
configurations based on the RCW Configuration field SRDS_PRTCL.
3.19.9.2 SGMII DC electrical characteristics

This section discusses the electrical characteristics for the SGMII interface.
3.19.9.2.1 SGMII and SGMII 2.5x transmit DC specifications

This table describes the SGMII SerDes transmitter AC-coupled DC electrical
characteristics. Transmitter DC characteristics are measured at the transmitter outputs
(SDn_TXn and SDn_TXn_B)as shown in Figure 45.
Table 101. SGMII DC transmitter electrical characteristics (XVDD = 1.35 V or 1.5 V)4
Parameter Symb Min Typ Max Unit Notes
ol
Output high voltage VOH - - 1.5 x │VOD│-max mV 1

Table 101. SGMII DC transmitter electrical characteristics (XVDD = 1.35 V or 1.5 V)4
(continued)
Parameter Symb Min Typ Max Unit Notes
ol
Output low voltage VOL │VOD│-min/2 - - mV 1
Output differential │VOD│ 320 500 725 mV SRDSxLNmTECR0 [AMP_RED] =
voltage2, 3 6b000000
(XVDD-Typ at 1.35 V and 293.8 459.0 665.6 SRDSxLNmTECR0 [AMP_RED] =
1.5 V) 6b000001
266.9 417.0 604.7 SRDSxLNmTECR0 [AMP_RED] =

6b000011

6b000010

6b000110 (Default)

6b000111

6b010000
Output impedance RO 40 50 60 Ω -
(single ended)
Notes:
1. This does not align to DC-coupled SGMII.
2. │VOD│ = │VSD_TXn - VSD_TXn_B│. │VOD│ is also referred to as output differential peak voltage. VTX-DIFFp-p = 2 x │VOD│.
3. The │VOD│ value shown in the Typ column is based on the condition of XVDD_SRDSn-Typ = 1.35 V or 1.5 V, no common
mode offset variation. SerDes transmitter is terminated with 100-Ω differential load between SDn _TXn and SDn_TXn_B.
This figure shows an example of a 4-wire AC-coupled SGMII serial link connection.

SDn_TXn SDn_RXn
CTX
50 Ω
Transmitter 100 Ω Receiver
CTX
SDn_TXn_B SDn_RXn_B
50 Ω
SGMII
SerDes Interface
SDn_RXn SDn_TXn
CTX
50 Ω
Receiver Transmitter
100 Ω
CTX
SDn_RXn_B SDn_TXn_B
50 Ω
Figure 44. 4-wire AC-coupled SGMII serial link connection example
This figure shows the SGMII transmitter DC measurement circuit.

SGMII
SerDes Interface
SDn_TXn
50 Ω
Transmitter 100 Ω VOD
50 Ω
SDn_TXn_B
Figure 45. SGMII transmitter DC measurement circuit
This table defines the SGMII 2.5x transmitter DC electrical characteristics for 3.125
GBaud.
Table 102. SGMII 2.5x transmitter DC electrical characteristics (XVDD = 1.35 V or 1.5 V)1
Parameter Symbo Min Typical Max Unit Notes
l
Output differential voltage │VOD│ 400 - 600 mV SRDSxLNmTECR0 [AMP_RED] = 6b000000
Output impedance RO 80 100 120 Ω -

(differential)
Notes:
3.19.9.2.2 SGMII and SGMII 2.5x DC receiver electrical characteristics

This table lists the SGMII DC receiver electrical characteristics. Source synchronous
clocking is not supported. Clock is recovered from the data.
Table 103. SGMII DC receiver electrical characteristics (SVDD = 1.0V)4
DC input voltage range - N/A - 1
Input differential voltage SRDSxLNmGCR1 VRX_DIFFp-p 100 - 1200 mV 2
[REIDL_TH] = 001

Table 103. SGMII DC receiver electrical characteristics (SVDD = 1.0V)4 (continued)

SRDSxLNmGCR1 175 -
[REIDL_TH] = 100
Loss of signal threshold SRDSxLNmGCR1 VLOS 30 - 100 mV 3
[REIDL_TH] = 001
SRDSxLNmGCR1 65 - 175
[REIDL_TH] = 100
Receiver differential input impedance ZRX_DIFF 80 - 120 Ω -
Notes:
1. Input must be externally AC coupled.
2. VRX_DIFFp-p is also referred to as peak-to-peak input differential voltage.
3. The concept of this parameter is equivalent to the electrical idle detect threshold parameter in PCI Express. See PCI
Express DC physical layer receiver specifications, and PCI Express AC physical layer receiver specifications, for further
explanation.
This table defines the SGMII 2.5x receiver DC electrical characteristics for 3.125 GBaud.
Table 104. SGMII 2.5x receiver DC timing specifications (SVDD = 1.0V)1
Input differential voltage VRX_DIFFp-p 200 - 1200 mV -
Loss of signal threshold VLOS 75 - 200 mV -
Receiver differential input impedance ZRX_DIFF 80 - 120 Ω -
Notes:
3.19.9.3 SGMII AC timing specifications

This section discusses the AC timing specifications for the SGMII interface.
3.19.9.3.1 SGMII and SGMII 2.5x transmit AC timing specifications

This table provides the SGMII and SGMII 2.5x transmit AC timing specifications. A
source synchronous clock is not supported. The AC timing specifications do not include
RefClk jitter.
Table 105. SGMII transmit AC timing specifications4
Unit Interval: 1.25 GBaud (SGMII) UI 800 - 100 ppm 800 800 + 100 ppm ps 1
Unit Interval: 3.125 GBaud (2.5x SGMII]) UI 320 - 100 ppm 320 320 + 100 ppm ps 1

Table 105. SGMII transmit AC timing specifications4 (continued)

Deterministic jitter JD - - 0.17 UI p-p -
Total jitter JT - - 0.35 UI p-p 2
AC coupling capacitor CTX 10 - 200 nF 3
Notes:
1. Each UI is 800 ps ± 100 ppm or 320 ps ± 100 ppm.
2. See Figure 42 for single frequency sinusoidal jitter measurements.
3. The external AC coupling capacitor is required. It is recommended that it be placed near the device transmitter outputs.
3.19.9.3.2 SGMII AC measurement details

Transmitter and receiver AC characteristics are measured at the transmitter outputs
(SDn_TXn and SDn_TXn_B) or at the receiver inputs (SDn_RXn and SDn_RXn_B)
respectively, as depicted in this figure.
D + package pin
C = CTX
Transmitter
silicon
+ package
C = CTX
D - package pin
R = 50 Ω R = 50 Ω
Figure 46. SGMII AC test/measurement load
3.19.9.3.3 SGMII and SGMII 2.5x receiver AC timing Specification

This table provides the SGMII and SGMII 2.5x receiver AC timing specifications. The
AC timing specifications do not include RefClk jitter. Source synchronous clocking is not
supported. Clock is recovered from the data.

Table 106. SGMII Receive AC timing specifications3

Combined deterministic and random jitter tolerance JDR - - 0.55 UI p-p 1
Bit error ratio BER - - 10-12 - -

Unit Interval: 1.25 GBaud (SGMII) UI 800 - 100 ppm 800 800 + 100 ppm ps 1
Unit Interval: 3.125 GBaud (2.5x SGMII]) UI 320 - 100 ppm 320 320 + 100 ppm ps 1
Notes:
The sinusoidal jitter in the total jitter tolerance may have any amplitude and frequency in
the unshaded region of Figure 43.
3.19.10 QSGMII interface

This section describes the QSGMII clocking and its DC and AC electrical characteristics.
3.19.10.1 QSGMII clocking requirements for SDn_REF_CLKn and

SDn_REF_CLKn_B
The ref clock frequency tolerance spec is ±100ppm. For more information on these
specifications, see SerDes reference clocks.
3.19.10.2 QSGMII DC electrical characteristics

This section discusses the electrical characteristics for the SGMII interface.
3.19.10.2.1 QSGMII transmitter DC specifications

This table describes the QSGMII SerDes transmitter AC-coupled DC electrical
characteristics. Transmitter DC characteristics are measured at the transmitter outputs
(SDn_TXn and SDn_TXn_B).

Table 107. QSGMII DC transmitter electrical characteristics (XVDD = 1.35V or 1.5V)1

Output differential voltage VDIFF 400 - 900 mV -

Notes:
3.19.10.2.2 QSGMII DC receiver electrical characteristics

This table defines the QSGMII receiver DC electrical characteristics.
Table 108. QSGMII receiver DC timing specifications (SVDD = 1.0V)1
Input differential voltage VDIFF 100 - 900 mV -
Differential resistance RRDIN 80 100 120 Ω -
Notes:
3.19.10.3 QSGMII AC timing specifications

This section discusses the AC timing specifications for the QSGMII interface.
3.19.10.3.1 QSGMII transmit AC timing specifications

This table provides the QSGMII transmitter AC timing specifications.
Table 109. QSGMII transmit AC timing specifications1
Transmitter baud rate TBAUD 5.000 - 100 ppm 5.000 5.000 + 100 ppm Gbps -
Uncorrelated high probability jitter TUHPJ - - 0.15 UI p-p -
Total jitter tolerance JT - - 0.30 UI p-p -
Notes:
3.19.10.3.2 QSGMII receiver AC timing Specification

This table provides the QSGMII receiver AC timing specifications.

Table 110. QSGMII receive AC timing specifications2

Receiver baud rate RBAUD 5.000 - 100 ppm 5.000 5.000 + 100 ppm Gbps -
Uncorrelated bounded high probability jitter RDJ - - 0.15 UI p-p -
Correlated bounded high probability jitter RCBHPJ - - 0.30 UI p-p 1
Bounded high probability jitter RBHPJ - - 0.45 UI p-p -
Total jitter (does not include sinusoidal jitter) RTj - - 0.60 UI p-p -
Notes:
1. The jitter (RCBHPJ) and amplitude have to be correlated, for example, by a PCB trace.
The sinusoidal jitter may have any amplitude and frequency in the unshaded region of
this figure.
5 UI p-p
Sinuosidal
Jitter
20 dB/dec
Amplitude
0.05 UI p-p
35.2 kHz Frequency 3 MHz 20 MHz
Figure 47. QSGMII single-frequency sinusoidal jitter limits
3.19.11 HiGig/HiGig2 interface

This section describes the HiGig/HiGig2 clocking requirements and its DC and AC
electrical characteristics.
3.19.11.1 HiGig/HiGig2 clocking requirements for SDn_REF_CLKn and

SDn_REF_CLKn_B
Only SerDes 1 and 2 (SD[1:2]_REF_CLK[1:2] and SD[1:2]_REF_CLK[1:2]_B) may be
used for SerDes HiGig/HiGig2 configurations based on the RCW Configuration field
3.19.11.2 HiGig/HiGig2 DC electrical characteristics

This section describes the DC electrical characteristics for HiGig/HiGig2.
3.19.11.2.1 HiGig/HiGig2 transmitter DC electrical characteristics

This table defines the HiGig/HiGig2 transmitter DC electrical characteristics.
Table 111. HiGig/HiGig2 transmitter DC electrical characteristics (XVDD = 1.35V or 1.5V)2
Differential output voltage VDIFFPP 800 1000 1600 mV p-p -
DC Differential transmitter impedance ZTX-DIFF-DC 80 100 120 Ω Transmitter DC

differential impedance
Notes:
1. Absolute output voltage limit
3.19.11.2.2 HiGig/HiGig2 receiver DC electrical characteristics

This table defines the HiGig/HiGig2 receiver DC electrical characteristics.
Table 112. HiGig/HiGig2 receiver DC electrical characteristics (SVDD = 1.0V)2
DC Differential receiver impedance ZRX-DIFF-DC 80 100 120 Ω DC Differential receiver
impedance
3.19.11.3 HiGig/HiGig2 AC timing specifications

This section describes the AC timing specifications for HiGig/HiGig2.
3.19.11.3.1 HiGig/HiGig2 transmitter AC timing specifications

This table defines the HiGig/HiGig2 transmitter AC timing specifications. RefClk jitter is
not included.
Table 113. HiGig/HiGig2 transmitter AC timing specifications1
Unit Interval: 3.125 Gbps (HiGig/HiGig2) UI 320 - 100 ppm 320 320 + 100 ppm ps
Unit Interval: 3.75 Gbps (HiGig/HiGig2) UI 266.66 - 100 ppm 266.66 266.66 + 100 ps
ppm
Notes:
3.19.11.3.2 HiGig/HiGig2 receiver AC timing specifications

This table defines the HiGig/HiGig2 receiver AC timing specifications. RefClk jitter is
not included.
Table 114. HiGig/HiGig2 receiver AC timing specifications3

jitter tolerance
Unit Interval: 3.125 Gbps (HiGig/ UI 320 - 100ppm 320 320 + 100ppm ps -
HiGig2)
Unit Interval: 3.75 Gbps (HiGig/HiGig2) UI 266.66 - 266.66 266.66 + ps -
100ppm 100ppm
3.19.12 XFI interface

This section describes the XFI clocking requirements and its DC and AC electrical
characteristics.

3.19.12.1 XFI clocking requirements for SDn_REF_CLKn and

SDn_REF_CLKn_B
SerDes XFI configurations based on the RCW Configuration field SRDS_PRTCL.
The ref clock frequency tolerance spec is ±100ppm. For more information on these
specifications, see SerDes reference clocks.
3.19.12.2 XFI DC electrical characteristics

This section describes the DC electrical characteristics for XFI.
3.19.12.2.1 XFI transmitter DC electrical characteristics

This table defines the XFI transmitter DC electrical characteristics.
Table 115. XFI transmitter DC electrical characteristics (XVDD = 1.35V or 1.5V)1
Output differential voltage VTX-DIFF 360 - 770 mV -
De-emphasized differential output VTX-DE- 0.6 1.1 1.6 dB -

RATIO-1.14dB
voltage (ratio)
De-emphasized differential output VTX-DE- 3 3.5 4 dB -
RATIO-3.5dB
voltage (ratio)
RATIO-4.66dB
voltage (ratio)
RATIO-6.0dB
voltage (ratio)
RATIO-9.5dB
voltage (ratio)
Notes:
3.19.12.2.2 XFI receiver DC electrical characteristics

This table defines the XFI receiver DC electrical characteristics.

Table 116. XFI receiver DC electrical characteristics (SVDD = 1.0V)2

Input differential voltage VRX-DIFF 110 - 1050 mV 1
Differential resistance RRD 80 100 120 Ω -
3.19.12.3 XFI AC timing specifications

This section describes the AC timing specifications for XFI.
3.19.12.3.1 XFI transmitter AC timing specifications

This table defines the XFI transmitter AC timing specifications. RefClk jitter is not
included.
Table 117. XFI transmitter AC timing specifications1
Transmitter baud rate TBAUD 10.3125 - 100ppm 10.3125 10.3125 + Gb/s
100ppm
Unit Interval UI - 96.96 - ps
Deterministic jitter DJ - - 0.155 UI p-p
Notes:
3.19.12.3.2 XFI receiver AC timing specifications

This table defines the XFI receiver AC timing specifications. RefClk jitter is not
included.
Table 118. XFI receiver AC timing specifications3
Receiver baud rate RBAUD 10.3125 - 10.3125 10.3125 + Gb/s -
100ppm 100ppm
Unit Interval UI - 96.96 - ps -
Total non-EQJ jitter TNON-EQJ - - 0.45 UI p-p 1
Total jitter tolerance TJ - - 0.65 UI p-p 1, 2

Table 118. XFI receiver AC timing specifications3 (continued)

1. The total jitter (TJ) consists of Random Jitter (RJ), Duty Cycle Distortion (DCD), Periodic Jitter (PJ), and Inter symbol
Interference (ISI). Non-EQJ jitter can include duty cycle distortion (DCD), random jitter (RJ), and periodic jitter (PJ). Non-EQJ
jitter is uncorrelated to the primary data stream with exception of the DCD and so cannot be equalized by the receiver under
test. It can exhibit a wide spectrum. Non - EQJ = TJ - ISI = RJ + DCD + PJ
2. The XFI channel has a loss budget of 9.6 dB @5.5GHz. The channel loss including connector @ 5.5GHz is 6dB. The
channel crosstalk and reflection margin is 3.6dB. Manual tuning of TX Equalization and amplitude will be required for
performance optimization.
This figure shows the sinusoidal jitter tolerance of XFI receiver.
1.13x 0.2 + 0.1 , f in MHz

f
Sinuosidal Jitter Tolerance (UIp-p)
-20 dB/Dec
0.17
0.05
0.04 4 8 27.2 40
Frequency (MHz)
Figure 48. XFI host receiver input sinusoidal jitter tolerance

3.19.13 10GBase-KR interface

This section describes the 10GBase-KR clocking requirements and its DC and AC
electrical characteristics.
3.19.13.1 10GBase-KR clocking requirements for SDn_REF_CLKn and

SDn_REF_CLKn_B
SerDes 10GBase-KR configurations based on the RCW Configuration field
SRDS_PRTCL. . The ref clock frequency tolerance spec is ±100ppm.
For more information on these specifications, see SerDes reference clocks .
3.19.13.2 10GBase-KR DC electrical characteristics

This section describes the DC electrical characteristics for 10GBase-KR.
3.19.13.2.1 10GBase-KR transmitter DC electrical characteristics

This table defines the 10GBase-KR transmitter DC electrical characteristics.
Table 119. 10GBaseKR transmitter DC electrical characteristics (XVDD = 1.35V or 1.5V)1
Output differential voltage VTX-DIFF 800 - 1200 mV -

RATIO-1.14dB
voltage (ratio)
RATIO-3.5dB
voltage (ratio)
RATIO-4.66dB
voltage (ratio)
RATIO-6.0dB
voltage (ratio)
RATIO-9.5dB
voltage (ratio)
Differential resistance TRD 80 100 120 Ω -
3.19.13.2.2 10GBase-KR receiver DC electrical characteristics

This table defines the 10GBase-KR receiver DC electrical characteristics.

Table 120. 10GBase-KR receiver DC electrical characteristics (XVDD = 1.35V or 1.5V)1

Input differential voltage VRX-DIFF - - 1200 mV -
Differential resistance RRD 80 - 120 Ω -
3.19.13.3 10GBase-KR AC timing specifications

This section describes the AC timing specifications for 10GBase-KR.
3.19.13.3.1 10GBase-KR transmitter AC timing specifications

This table defines the 10GBase-KR transmitter AC timing specifications. RefClk jitter is
not included.
Table 121. 10GBase-KR transmitter AC timing specifications1
Transmitter baud rate TBAUD 10.3125 - 100 10.3125 10.3125 + 100 GBd
ppm ppm
Deterministic jitter DJ - - 0.155 UI p-p
3.19.13.3.2 10GBase-KR receiver AC timing specifications

This table defines the 10GBase-KR receiver AC timing specifications. RefClk jitter is not
included.
Table 122. 10GBase-KR receiver AC timing specifications4,3
Receiver baud rate RBAUD 10.3125 - 100 10.3125 10.3125 + 100 GBd -
ppm ppm
Random jitter RJ - - 0.130 UI p-p 1
Sinusodial jitter, maximum SJ-max - - 0.115 UI p-p 1
Duty cycle distortion DCD - - 0.035 UI p-p 1
Total jitter TJ - - 1.0 UI p-p 1,2
2. The Total applied Jitter Tj = ISI + Rj + DCD + Sj-max where ISI is jitter due to frequency dependent loss.
3. TX Equalization and amplitude tuning is through software for performance optimization, as in Freescale provided SDKs.

3.19.14 Interlaken interface

This section describes the Interlaken clocking requirements and its DC and AC electrical
characteristics.
3.19.14.1 Interlaken clocking requirements for SDn_REF_CLKn and

SDn_REF_CLKn_B
SerDes Interlaken-LA configurations based on the RCW Configuration field
3.19.14.2 Interlaken-short reach DC electrical characteristics

This section describes the DC electrical characteristics for Interlaken-short reach.
3.19.14.2.1 Interlaken-short reach transmitter DC electrical characteristics

This table defines the Interlaken-short reach transmitter DC electrical characteristics.
Table 123. Interlaken-short reach transmitter DC electrical characteristics (XVDD = 1.35V or
1.5V)1
Output differential voltage VDIFF 400 - 750 mV -

Notes:
3.19.14.2.2 Interlaken-short reach receiver DC electrical characteristics

This table defines the Interlaken-short reach receiver DC electrical characteristics.
Table 124. Interlaken-short reach receiver DC electrical characteristics (SVDD = 1.0V)1
Input differential voltage VDIFF 125 - 1200 mV -
Differential resistance RRDIN 80 100 120 Ω -
Notes:

3.19.14.3 Interlaken-short reach AC timing specifications

This section describes the AC timing specifications for Interlaken-short reach.
3.19.14.3.1 Interlaken-short reach transmitter AC timing specifications

This table defines the Interlaken-short reach transmitter AC timing specifications. RefClk
jitter is not included.
Table 125. Interlaken-short reach transmitter AC timing specifications1
Transmitter baud rate TBAUD 3.125 - 100ppm 3.125 3.125 + 100ppm Gbps
Transmitter baud rate TBAUD 6.25 - 100 ppm 6.25 6.25 + 100 ppm Gbps
Uncorrelated high probability jitter TUHPJ - - 0.155 UI p-p
Total jitter tolerance TJ - - 0.30 UI p-p
Notes:
3.19.14.3.2 Interlaken-short reach receiver AC timing specifications

This table defines the Interlaken-short reach receiver AC timing specifications. RefClk
jitter is not included.
Table 126. Interlaken-short reach receiver AC timing specifications2
Receiver baud rate RBAUD 3.125 - 100 3.125 3.125 + 100 Gbps -
ppm ppm
Receiver baud rate RBAUD 6.25 - 100 ppm 6.25 6.25 + 100 ppm Gbps -
Uncorrelated bounded high probability jitter RUBHPJ - - 0.15 UI p-p -
Correlated bounded high probability jitter RCBHPJ - - 0.30 UI p-p 1
Bounded high probability jitter RBHPJ - - 0.45 UI p-p -
Total jitter (does not include sinusoidal jitter) RTj - - 0.60 UI p-p -
1. The jitter (RCBHPJ) and amplitude have to be correlated, for example, by a PCB trace.
The sinusoidal jitter in the total jitter tolerance may have any amplitude and frequency in
the unshaded region of this figure.

Hardware design considerations
5 UI p-p
Sinuosidal
Jitter 20 dB/dec
Amplitude
0.05 UI p-p
baud/142000 Frequency baud/1667 20 MHz
Figure 49. Single-frequency sinusoidal jitter limits
4 Hardware design considerations
4.1 System clocking

This section describes the PLL configuration of the chip.
4.1.1 PLL characteristics

Characteristics of the chip's PLLs include the following:
• There are five selectable core cluster PLLs which generate a clock for each core
cluster from the externally supplied SYSCLK input.
• Core cluster 1 (cores 0-3) can select from cluster group A PLL 1, 2 or 3 (CGA1,
2, 3 PLL)
• Core cluster 2 (cores 4-7) can select from cluster group A PLL 1, 2 or 3 (CGA1,
2, 3 PLL), not applicable to T4080 parts

• Core cluster 3 (cores 8-11) can select from cluster group B PLL 1 or 2 (CGB1, 2
PLL)
• The frequency ratio between each of the core cluster PLLs and SYSCLK is
selected using the configuration bits as described in Core cluster to SYSCLK
PLL ratio. The frequency for each core cluster 1-3 is selected using the
configuration bits as described in Table 131 and Table 132.
• The platform PLL generates the platform clock from the externally supplied
SYSCLK input. The frequency ratio between the platform and SYSCLK is selected
using the platform PLL ratio configuration bits as described in Platform to SYSCLK
PLL ratio.
• Cluster group A generates an asynchronous clock for PME from cluster group A
PLL 1 or cluster group A PLL 2. Described in Frame Manager (FMn) clock select.
• Cluster group B generates an asynchronous clock for FMan 1 and FMan 2 from the
platform PLL, cluster group B PLL 1, or cluster group B PLL 2. Described in Frame
Manager (FMn) clock select.
• The DDR block PLL generates an asynchronous DDR clock from the externally
supplied DDRCLK input. The frequency ratio is selected using the Memory
Controller Complex PLL multiplier/ratio configuration bits as described in DDR
controller PLL ratios.
• Each of the four SerDes blocks has 2 PLLs which generate a core clock from their
respective externally supplied SDn_REF_CLKn/SDn_REF_CLKn_B inputs. The
frequency ratio is selected using the SerDes PLL RCW configuration bits as
described in SerDes PLL ratio.
4.1.2 Clock ranges

This table provides the clocking specifications for the processor core, platform, memory,
and integrated flash controller.
Table 127. Processor, platform, and memory clocking specifications
Characteristic Maximum processor core frequency Unit Notes
1500 MHz 1667 MHz 1800 MHz
Min Max Min Max Min Max
Core cluster group PLL frequency 1000 1500 1000 1667 1000 1800 MHz 1, 2
Core cluster frequency See note 1500 See note 1667 See note 1800 MHz 2
2 2 2
Platform clock frequency 400 667 400 733 400 733 MHz 1, 7
Memory bus clock frequency 533 800 533 933.333 533 933.333 MHz 1, 3, 4
IFC clock frequency — 100 — 100 — 100 MHz 5

Table 127. Processor, platform, and memory clocking specifications (continued)

Characteristic Maximum processor core frequency Unit Notes
1500 MHz 1667 MHz 1800 MHz
Min Max Min Max Min Max
PME See note 500 See note 550 See note 550 MHz 6
6 6 6
FMn 450/667 667 450/667 733 450/667 733 MHz 8
1. Caution:The platform clock to SYSCLK ratio and core to SYSCLK ratio settings must be chosen such that the resulting
SYSCLK frequency, core frequency, and platform clock frequency do not exceed their respective maximum or minimum
operating frequencies.
2. The core cluster can run at cluster group PLL/1, PLL/2, or PLL/4. For the PLL/1 case, the minimum frequency is 1000
MHz. With a minimum cluster group PLL frequency of 1000 MHz, this results in a minimum allowable core cluster frequency
of 500 MHz for PLL/2. For the PLL/4 case, the minimum allowable core cluster frequency is platform clock frequency / 2. For
the case of the minimum platform frequency = 400 MHz, the minimum core cluster frequency is 200 MHz.
3. The memory bus clock speed is half the DDR3/DDR3L data rate. DDR3/3L memory bus clock frequency is limited to min =
533 MHz.
4. The memory bus clock speed is dictated by its own PLL.
5. The integrated flash controller (IFC) clock speed on IFC_CLK[0:2] is determined by the IFC module input clock (platform
clock / 2) divided by the IFC ratio programmed in CCR[CLKDIV]. See the chip reference manual for more information.
6. The PME minimum frequency is Platform Frequency / 2. For the case of the minimum platform frequency = 400 MHz, the
minimum PME frequency is 200 MHz.
7. The minimum platform frequency should meet the requirements in Minimum platform frequency requirements for high-
speed interfaces. For SRIO proper operations the FMAN minimum frequency has to be equal to 528 MHz.
8. If all MACs operate using RGMII or SGMII at 1.25 G, then the minimum required FMAN frequency is 450 MHz. Also, If any
MAC operates at a higher rate then the minimum FMAN is 667 MHZ.
4.1.2.1 DDR clock ranges

The DDR memory controller can run only in asynchronous mode, where the memory bus
is clocked with the clock provided on the DDRCLK input pin, which has its own
dedicated PLL.
This table provides the clocking specifications for the memory bus.
Table 128. Memory bus clocking specifications
Characteristic Min Max Unit Notes
Memory bus clock frequency 533 933.3333 MHz 1, 2, 3
Notes:
1. Caution: The platform clock to SYSCLK ratio and core to platform clock ratio settings must be chosen such that the
resulting SYSCLK frequency, core frequency, and platform frequency do not exceed their respective maximum or minimum
operating frequencies. See Platform to SYSCLK PLL ratio, and Core cluster to SYSCLK PLL ratio, and DDR controller PLL
ratios, for ratio settings.
2. The memory bus clock refers to the chip's memory controllers' Dn_MCK[0:3] and Dn_MCK[0:3]_B output clocks, running at
half of the DDR data rate.
3. The memory bus clock speed is dictated by its own PLL. See DDR controller PLL ratios.

4.1.3 Platform to SYSCLK PLL ratio

This table lists the allowed platform clock to SYSCLK ratios.
Because the DDR operates asynchronously, the memory-bus clock-frequency is
decoupled from the platform bus frequency.
For all valid platform frequencies supported on this chip, set the RCW Configuration
field SYS_PLL_CFG = 0b00.
Table 129. Platform to SYSCLK PLL ratios
Binary Value of SYS_PLL_RAT Platform:SYSCLK Ratio
0_0011 3:1
0_0100 4:1
0_0101 5:1
0_0110 6:1
0_0111 7:1
0_1000 8:1
0_1001 9:1
0_1010 10:1
0_1011 11:1
0_1100 12:1
0_1101 13:1
0_1110 14:1
0_1111 15:1
1_0000 16:1
All Others Reserved
4.1.4 Core cluster to SYSCLK PLL ratio

The clock ratio between SYSCLK and each of the core cluster PLLs is determined by the
binary value of the RCW Configuration field CGm_PLLn_RAT. This table describes the
supported ratios. For all valid core cluster frequencies supported on this chip, set the
RCW Configuration field CGn_PLL_CFG = 0b00.
This table lists the supported asynchronous core cluster to SYSCLK ratios.

Table 130. Core cluster PLL to SYSCLK ratios

Binary value of CGm_PLLn_RAT Core cluster:SYSCLK Ratio
00_1000 8:1
00_1001 9:1
00_1010 10:1
00_1011 11:1
00_1100 12:1
00_1101 13:1
00_1110 14:1
00_1111 15:1
01_0000 16:1
01_0010 18:1
01_0100 20:1
01_0110 22:1
01_1001 25:1
01_1010 26:1
01_1011 27:1
All others Reserved
4.1.5 Core complex PLL select

The clock frequency of each core cluster is determined by the binary value of the RCW
Configuration field Cn_PLL_SEL. These tables describe the selections available to each
core cluster, where each individual core cluster can select a frequency from their
respective tables.
NOTE
There is a restriction that requires that the frequency provided
to the e6500 core cluster after any dividers must always be
greater than half of the platform frequency. Special care must
be used when selecting the /2 or /4 outputs of a cluster PLL in
which this restriction is observed.
Table 131. Core cluster [1-2] PLL select
Binary Value of Cn_PLL_SEL for n = 1-2 Core cluster ratio
0000 CGA PLL1/1
0001 CGA PLL1/2
0010 CGA PLL1/4
0100 CGA PLL2/1

Table 131. Core cluster [1-2] PLL select (continued)

Binary Value of Cn_PLL_SEL for n = 1-2 Core cluster ratio
0101 CGA PLL2/2
0110 CGA PLL2/4
1000 CGA PLL3/1
1001 CGA PLL3/2
1010 CGA PLL3/4
All Others Reserved
Table 132. Core cluster [3] PLL select

Binary Value of Cn_PLL_SEL for n = 3 Core cluster ratio
0000 CGB PLL1/1
0001 CGB PLL1/2
0010 CGB PLL1/4
0100 CGB PLL2/1
0101 CGB PLL2 2
0110 CGB PLL2/4
All Others Reserved
4.1.6 DDR controller PLL ratios

The three DDR memory controller complexes operate asynchronous to the platform. All
DDR controllers operate at the same frequency configuration.
In asynchronous DDR mode, the DDR data rate to DDRCLK ratios supported are listed
in the following table. This ratio is determined by the binary value of the RCW
Configuration field MEM_PLL_RAT (bits 10-15).
The RCW Configuration field MEM_PLL_CFG (bits 8-9) must be set to
MEM_PLL_CFG = 0b00 for all valid DDR PLL reference clock frequencies supported
on this chip.
Table 133. DDR data Rate to DDRCLK ratios1
Binary value of Decimal values of DDR data rate Resulting DDR data-rate (MT/s)
MEM_PLL_RAT MEM_PLL_RAT to DDRCLK
Ratio value
Rev 1 Rev 2 Rev 1 Rev 2 Examples of DDRCLK frequency values that give
silicon silicon silicon silicon typical DDR data rata values at Ratio value
66.6667 100 MHz 125 MHz 133.333 MHz
MHz
00_1010 00_0101 10 5 10 1333.333

Table 133. DDR data Rate to DDRCLK ratios1 (continued)

Binary value of Decimal values of DDR data rate Resulting DDR data-rate (MT/s)
MEM_PLL_RAT MEM_PLL_RAT to DDRCLK
Ratio value
Rev 1 Rev 2 Rev 1 Rev 2 Examples of DDRCLK frequency values that give
silicon silicon silicon silicon typical DDR data rata values at Ratio value
66.6667 100 MHz 125 MHz 133.333 MHz
MHz
00_1100 00_0110 12 6 12 1500 1600
00_1110 00_0111 14 7 14 1750 1866.667
01_0000 00_1000 16 8 16 1066.667 1600
01_0010 00_1001 18 9 18 1800
01_0100 00_1010 20 10 20 1333.333
All Others All Others Reserved Reserved Reserved
Notes:
1. This table shows examples of standard DDR data rate resulted from multiplying the MEM_PLL_RAT by some common
DDRCLK frequencies like 66.66MHZ, 100MHz, or 133MHZ. Customers can supply of course different DDRCLK frequency
from the common ones presented in this table and thus they have to pick up the correct MEM_PLL_RAT value that will give
them a common DDR data rate and always use a value for Rev2 silicon that is half of what is supposed to be given in Rev1
or simply in rev2 MEM_PLL_RAT = 0.5 * DDR data rate/ DDRCLK.
4.1.7 SerDes PLL ratio

The clock ratio between each of the three SerDes PLLs and their respective externally
supplied SDn_REF_CLKn/SDn_REF_CLKn_B inputs is determined by a set of RCW
Configuration fields-SRDS_PRTCL_Sn, SRDS_PLL_REF_CLK_SEL_Sn, and
SRDS_DIV_*_Sn-as shown in this table.
Table 134. Valid SerDes RCW encodings and reference clocks
SerDes protocol (given Valid reference Legal setting for Legal setting Legal setting for Notes
lane) clock SRDS_PRTCL_Sn for SRDS_DIV_*_Sn
frequency SRDS_PLL_RE
F_CLK_SEL_Sn
High-speed serial and debug interfaces
PCI Express 2.5 GT/s 100 MHz Any PCIe 0b0: 100 MHz 2b10: 2.5 G 1
(doesn't negotiate upwards) 125 MHz 0b1: 125 MHz 1
PCI Express 5 GT/s 100 MHz Any PCIe 0b0: 100 MHz 2b01: 5.0 G 1
(can negotiate up to 5 GT/s) 125 MHz 0b1: 125 MHz 1
PCI Express 8 GT/s 100 MHz Any PCIe 0b0: 100 MHz 2b00: 8.0 G 1
(can negotiate up to 8 GT/s) 125 MHz 0b1: 125 MHz 1
Serial RapidIO 2.5 Gbaud 100 MHz SRIO @ 2.5/5 Gbaud 0b0: 100 MHz 0b1: 2.5 G -
125 MHz 0b1: 125 MHz -
Serial RapidIO 3.125 Gbaud 125 MHz SRIO @ 3.125 Gbaud 0b0: 125 MHz Don't care -

Table 134. Valid SerDes RCW encodings and reference clocks (continued)
SerDes protocol (given Valid reference Legal setting for Legal setting Legal setting for Notes
lane) clock SRDS_PRTCL_Sn for SRDS_DIV_*_Sn
frequency SRDS_PLL_RE
F_CLK_SEL_Sn
156.25 MHz 0b1: 156.25 MHz -
Serial RapidIO 5 Gbaud 100 MHz SRIO @ 2.5/5 Gbaud 0b0: 100 MHz 0b0: 5.0 G -
125 MHz 0b1: 125 MHz -
Interlaken Lookaside (6.25 125 MHz Interlaken LA @ 6.25 0b0: 125 MHz Don't care -
Gbps) Gbps
156.25 MHz 0b1: 156.25 MHz -
Interlaken Lookaside (10.3125 156.25 MHz Interlaken LA @ 10.3125 0b0: 156.25 MHz Don't care -
Gbps) Gbps
161.1328125 0b1: -
MHz 161.1328125
MHz
SATA (1.5 or 3 Gbps) 100 MHz Any SATA 0b0: 100 MHz Don't care 2
125 MHz 0b1: 125 MHz
Debug (2.5 Gbps) 100 MHz Aurora @ 2.5/5 Gbps 0b0: 100 MHz 0b1: 2.5 G -
125 MHz 0b1: 125 MHz -
Debug (3.125 Gbps) 125 MHz Aurora @ 3.125 Gbps 0b0: 125 MHz Don't Care -
156.25 MHz 0b1: 156.25 MHz -
Debug (5 Gbps) 100 MHz Aurora @ 2.5/5 Gbps 0b0: 100 MHz 0b0: 5.0 G -
125 MHz 0b1: 125 MHz -
Networking interfaces
SGMII (1.25 Gbaud) 100 MHz SGMII @ 1.25 Gbaud 0b0: 100 MHz Don't care -
125 MHz 0b1: 125 MHz -
2.5x SGMII (3.125 Gbaud) 125 MHz SGMII @ 3.125 Gbaud 0b0: 125 MHz Don't care -
156.25 MHz 0b1: 156.25 MHz -
QSGMII (5.0 Gbps) 100 MHz Any QSGMII 0b0: 100 MHz 0b0: 5.0 G -
125 MHz 0b1: 125 MHz -
XAUI (3.125 Gb/s) 125 MHz XAUI @ 3.125 Gb/s 0b0: 125 MHz Don't care -
156.25 MHz 0b1: 156.25 MHz -
HiGig or HiGig2 (3.125 Gbps) 125 MHz HiGig @ 3.125 Gbps 0b0: 125 MHz Don't care -
156.25 MHz 0b1: 156.25 MHz -
HiGig or HiGig2 (3.75 Gbps) 125 MHz HiGig @ 3.75 Gbps 0b0: 125 MHz Don't care -
156.25 MHz 0b1: 156.25 MHz -
XFI (10.3125 Gbps) 156.25 MHz XFI @ 10.3125 Gbps 0b0: 156.25 MHz Don't care -
10GBase-KR (10.3125 GBd) 156.25 MHz 10GBase-KR @ 10.3125 0b0: 156.25 MHz Don't care -
GBd
1. A spread-spectrum reference clock is permitted for PCI Express. However, if any other high-speed interfaces such as
sRIO, Interlaken, SATA, SGMII, SGMII 2.5x, QSGMII, XAUI, XFI, 10GBase-KR, HiGig/HiGig2 or Aurora are used
concurrently on the same SerDes bank, spread-spectrum clocking is not permitted.
2. SerDes lanes configured as SATA initially operate at 3.0 Gbps. 1.5 Gbps operation may later be enabled through the
SATA IP itself. It is possible for software to set each SATA at different rates.

4.1.8 Frame Manager (FMn) clock select

The following tables describe the clocking options that may be applied to each FM. The
clock selection is determined by the binary value of the RCW Clocking Configuration
fields HWA_CGB_M1_CLK_SEL and HWA_CGB_M2_CLK_SEL.
Table 135. Frame Manager (FMn) clock select
Binary value of Frame Manager (FM1) clock select1 Frame Manager (FM2) clock select1
HWA_CGB_Mn_CLK_SEL
000b, 001b Reserved Reserved
010b Cluster group B PLL 1/2 Cluster group B PLL 2/2
101b Platform clock frequency/1 Platform clock frequency/1
111b Reserved Cluster group B PLL 1/3
1. For max frequency, see Table 127 .
4.1.9 Pattern Matching Engine (PME) clock select

The PME can be synchronous with or asynchronous to the platform, depending on
configuration.
This table describes the clocking options that may be applied to the PME. The clock
selection is determined by the binary value of the RCW Clocking Configuration field
HWA_CGA_M1_CLK_SEL.
Table 136. Pattern Matching Engine clock select
Binary Value of HWA_CGA_M1_CLK_SEL PME Frequency 1
000b Platform clock frequency/2 (synchronous mode)
001b Reserved
010b Cluster group A PLL 1/2 (Asynchronous mode)
101b Reserved
Note:
1. For asynchronous mode, max frequency, see Table 127.

4.1.10 Frequency options

This section discusses interface frequency options.
4.1.10.1 SYSCLK and core cluster frequency options

This table shows the expected frequency options for SYSCLK and core cluster
frequencies.
Table 137. SYSCLK and core cluster frequency options
Core cluster: SYSCLK Ratio2 SYSCLK (MHz) 2
66.67 100.00 133.33
Core cluster Frequency (MHz)1
8:1 1067
9:1 1200
10:1 1000 1333
11:1 1100 1467
12:1 1200 1600
13:1
14:1 1400
15:1 1000 1500
16:1 1067 1600
18:1 1200 1800
20:1 1333
22:1 1467
25:1 1667
26:1
27:1 1800
Notes:
1. Core cluster frequency values are shown rounded up to the nearest whole number (decimal place accuracy removed)
2. Example values.
4.1.10.2 SYSCLK and platform frequency options

This table shows the expected frequency options for SYSCLK and platform frequencies.

Table 138. SYSCLK and platform frequency options

Platform: SYSCLK Ratio3 SYSCLK (MHz)3
66.67 100.00 133.33
Platform Frequency (MHz)1
4:1 400 533
5:1 667
6:1 4002 600
7:1 700
8:1 533
9:1 600
10:1 667
11:1 733
12:1
Notes:
1. Platform frequency values are shown rounded up to the nearest whole number (decimal place accuracy removed)
2. A minimum platform clock frequency requirement is 528MHz if x4 SRIO is used.
3.Example values.
4.1.10.3 DDRCLK and DDR data rate frequency options

This table shows the expected frequency options for DDRCLK and DDR data rate
frequencies.
Table 139. DDRCLK and DDR data rate frequency options
DDR data rate: DDRCLK DDRCLK (MHz)2
Ratio2
66.67 100.00 125.00 133.33
DDR Data Rate (MT/s)1
10:1 1333
12:1 1500 1600
14:1 1750 1866
16:1 1067 1600
18:1 1800
20:1 1333
Notes:
1. DDR data rate values are shown rounded up to the nearest whole number (decimal place accuracy removed).
2. Example values.
4.1.10.4 SYSCLK and FMan frequency options

These table shows the expected frequency options for SYSCLK and FMan frequencies.
Table 140. SYSCLK and FMan frequency options (clocked by CGB PLLn / 2)
Core cluster: SYSCLK Ratio3 SYSCLK (MHz)3
66.67 100.00 133.33
FMan Frequency (MHz)1, 2
8:1 533
9:1 600
10:1 500 667
11:1 550 733
12:1 600
13:1
14:1 700
15:1 500 750
16:1 533
18:1 600
20:1 667
22:1 733
25:1
26:1
27:1
Notes:
1. FMan frequency values are shown rounded up to the nearest whole number (decimal place accuracy removed).
2. For min frequency, see Table 127.
3. Example values.
66.67 100.00 133.33
8:1
9:1
10:1
11:1 489
12:1 533
13:1 578
14:1 467
15:1 500
16:1 533
18:1 600
20:1
22:1 489

(continued)
66.67 100.00 133.33
25:1 556
26:1 578
27:1 600
Notes:
1. FMan frequency values are shown rounded up to the nearest whole number (decimal place accuracy removed)
2. For min frequency, see Table 127
3. Example values.
Table 142. SYSCLK and FMan frequency options (clocked by CGB PLL1 / 4)
66.67 100.00 133.33
8:1
9:1
10:1
11:1
12:1
13:1
14:1
15:1
16:1
18:1 450
20:1
22:1
25:1
26:1
27:1 450
Notes:
3. Example values.

Table 143. SYSCLK and FMan frequency options (clocked by platform frequency/1)
66.67 100.00 133.33
4:1 533
5:1 667
6:1 600
7:1 700
8:1 533
9:1 600
10:1 667
11:1 733
12:1
Notes:
3. Example values.
4.1.10.5 SYSCLK and PME frequency options

These table shows the expected frequency options for SYSCLK and PME frequencies.
Table 144. SYSCLK and PME frequency options (clocked by CGA PLLn / 2)
66.67 100.00 133.33
PME Frequency (MHz)1
8:1 533
9:1 600
10:1 500
11:1 550
12:1 600
13:1
14:1
15:1 500
16:1 533
18:1 600
20:1
22:1
25:1
26:1

(continued)
66.67 100.00 133.33
27:1
Notes:
1. PME frequency values are shown rounded up to the nearest whole number (decimal place accuracy removed).
2. Example values.
66.67 100.00 133.33
8:1
9:1 400
10:1 444
11:1 489
12:1 400 533
13:1 578
14:1 467
15:1 500
16:1 533
18:1 400 600
20:1 444
22:1 489
25:1 556
26:1 578
27:1 600
Notes:
2. Example values.
Table 146. SYSCLK and PME frequency options (clocked by platform frequency/2)
66.67 100.00 133.33
4:1 200 267
5:1 334

Table 146. SYSCLK and PME frequency options (clocked by platform frequency/2)
(continued)
66.67 100.00 133.33
6:1 200 300 400
7:1 350
8:1 267 400
9:1 300
10:1 334
11:1 367
12:1 400
Notes:
2. Example values.
4.1.10.6 Minimum platform frequency requirements for high-speed

interfaces
The platform clock frequency must be considered for proper operation of high-speed
interfaces as described below.
For proper PCI Express operation, the platform clock frequency must be greater than or
equal to:
527 MHz x (PCI Express link width)
16
Figure 50. Gen 1 PEX minimum platform frequency
See section "Link Width," in the chip reference manual for PCI Express interface width
details. Note that "PCI Express link width" in the above equation refers to the negotiated
link width as the result of PCI Express link training, which may or may not be the same

as the link width POR selection. It refers to the widest port in use, not the combined
width of the number ports in use. For instance, if two x4 PCIe Gen3 ports are in use,
527MHz platform frequency is needed to support by using Gen 3 equation (527 x 4 / 4,
not 527 x 4 x 2 / 4).
4.2 Power supply design
4.2.1 Voltage ID (VID) controllable supply

To guarantee performance and power specifications, a specific method of selecting the
optimum voltage-level must be implemented when the chip is used. As part of the chip's
boot process, software must read the VID efuse values stored in the Fuse Status register
(FUSESR) and then configure the external voltage regulator based on this information.
This method requires a point of load voltage regulator for each chip.
NOTE
During the power-on reset process, the fuse values are read and
stored in the FUSESR. It is expected that the chip's boot code
reads the FUSESR value very early in the boot sequence and
updates the regulator accordingly.
The default voltage regulator setting that is safe for the system to boot is the
recommended operating VDD at initial start-up of 1.025 V. It is highly recommended to
select a regulator with a Vout range of at least 0.9 V to 1.1 V, with a resolution of
12.5 mV or better, when implementing a VID solution. If the VID for a specific part is
already known at initial start-up, it is acceptable to program the voltage regulator to the
VID value. The device does not require an initial voltage of 1.025V at start-up.
The table below lists the valid VID efuse values that will be programmed at the factory
for this chip.
Table 147. Fuse Status Register
(DCFG_CCSR_FUSESR)
Binary value of DA_V / DA_ALT_V VDD voltage
00001 0.9875 V
00010 0.9750 V
10000 1.0000 V
10001 1.0125 V
10010 1.0250 V
All other values See the complete list in the Fuse Status Register
(DCFG_CCSR_FUSESR) section of the chip reference
manual.

If DA_ALT_V is not all zeros, then software should read DA_ALT_V for the VID value
and not the DA_V. For additional information on VID, please see the chip reference
manual.
4.2.1.1 Options for system design

There are several widely-accepted options available to the system designer for obtaining
the benefits of a VID solution. The most common option is to use the VID solution to
drive a system's controllable voltage-regulators through a sideband interface such as a
simple parallel bus or PMBus interface. PMbus is similar to I2C but with extensions to
improve robustness and address shortcomings of I2C; the PMBus specification can be
found at www.pmbus.org. The simple parallel bus is supported by the chip through GPIO
pins and the PMBus interface is supported by an I2C interface. Other VID solutions may
be to access an FPGA/ASIC or separate power management chip through the IFC, SPI, or
other chip-specific interface, where the other device then manages the voltage regulator.
The method chosen for implementing the chip-specific voltage in the system is decided
by the user.
4.2.1.1.1 Example 1: Regulators supporting parallel bus configuration

In this example, a user builds a VID solution using controllable regulators with a parallel
bus. In this implementation, the user chooses to utilize any subset of the available GPIO
pins on the chip except those noted below.
NOTE
GPIO pins that are muxed on an interface used by the
application for loading RCW information are not available for
VID use.
It is recommended that all GPIO pins used for VID are located
in the same 32-bit GPIO IP block so that all bits can be
accessed with a single read or write.
The general procedure for setting the core voltage regulator to the desired operating
voltage is as follows:
1. The GPIO pins are released to high-impedance at POR. Because GPIO pins default
to being inputs, they do not begin automatically driving after POR, and only work as
outputs under software control.
2. The board is responsible for a default voltage regulator setting that is "safe" for the
system to boot. To achieve this, the user puts pull-up and/or pull-down resistors on
the GPIO pins as needed for that specific system. For the case where the regulator's

interface operates at a different voltage than OVDD, the chip's GPIO module can be
operated in an open drain configuration.
3. There is no direct connection between the Fuse Status Register (FUSESR) and the
chip's pins. As part of the chip's boot process, software must read the efuse values
stored in the FUSESR and then configure the voltage regulator based on this
information. The software determines the proper value for the parallel interface and
writes it to the GPIO block data (GPDAT) register. It then changes the GPIO
direction (GPDIR) register from input to output to drive the new value on the device
pins, thus overriding the board configuration default value. Note that some regulators
may require a series of writes so that the voltage is slowly stepped from its old to its
new value.
4. When the voltage has stabilized, software adjusts the operating frequencies as
desired.
Upon completion of configuration, some regulators may have a write-protect pin to
prevent undesired data changes after configuration is complete. A single GPIO pin on the
chip could be allocated for this task if desired.
4.2.1.1.2 Example 2: Regulators supporting PMBus configuration

In this example, a user builds a VID solution using controllable regulators with a PMBus
interface. For the case where the regulator's interface operates at a different voltage than
DVDD, the chip's I2C module can be operated in an open-drain configuration.
In this implementation, the user chooses to utilize any I2C interface available on the chip.
These regulators have a means for setting a safe, default, operating value either through
strapping pins or through a default, non-volatile store.
NOTE
If I2C1controller is selected, it is important that its calling
address is different than the 7-bit value of 0x50h used by the
pre-boot loader (PBL) for RCW and pre-boot initialization.
1. The board is responsible for configuring a safe default value for the controllable
regulator either through dedicated pins or its non-volatile store.
2. As part of the chip's boot process, software must read the efuse values stored in the
FUSESR register and then configure the voltage regulator based on this information.
The software decides on a new configuration and sends this value across the I2C
interface connected to the regulator's PMBus interface. Note that some regulators
may require a series of writes so that the voltage is slowly stepped from its old to its
new value.

desired.
chip could be allocated for this task, if desired.
4.2.1.1.3 Example 3: Regulators supporting FPGA/ASIC or separate power

management device configuration
In this example, a user builds a VID solution using controllable regulators that are
managed by a FPGA/ASIC or a separate power-management device. In this
implementation, the user chooses to utilize the IFC, eSPI or any other available chip
interface to connect to the power-management device.
1. The board is responsible for configuring a safe default value for the controllable
regulator either through dedicated pins or its non-volatile store.
2. As part of the chip's boot process, software must read the efuse values stored in the
FUSESR and then configure the voltage regulator based on this information. The
software decides on a new configuration and sends this value across the IFC, eSPI, or
any other interface that is used to connect to the FPGA/ASIC or separate power-
management device that manages the regulator. Note that some regulators may
require a series of writes so that the voltage is slowly stepped from its old to its new
value.
desired.
chip could be allocated for this task, if desired.
4.2.2 Core and platform supply voltage filtering

The VDD supply is normally derived from a high current capacity linear or switching
power supply which can regulate its output voltage very accurately despite changes in
current demand from the chip within the regulator's relatively low bandwidth. Several
bulk decoupling capacitors must be distributed around the PCB to supply transient
current demand above the bandwidth of the voltage regulator.

These bulk capacitors should have a low ESR (equivalent series resistance) rating to
ensure the quick response time necessary. They should also be connected to the power
and ground planes through two vias to minimize inductance. However, customers should
work directly with their power regulator vendor for best values and types of bulk
capacitors.
As a guideline for customers and their power regulator vendors, NXP recommends that
these bulk capacitors be chosen to maintain the positive transient power surges to less
than VID+50 mV (except that a positive transient of up to +100 mV can be tolerated for
less than 1 us, negative transient undershoot should comply with specification of
VID-30mV) for current steps of up to 20A for 12 cores, 15A for 8 cores and 10A for 4
cores with a slew rate of 12 A/us.
These bulk decoupling capacitors will ideally supply a stable voltage for current
transients into the megahertz range. Above that, see Decoupling recommendations for
further decoupling recommendations.
4.2.3 PLL power supply filtering

Each of the PLLs described in System clocking is provided with power through
independent power supply pins (AVDD_PLAT, AVDD_CGAn, AVDD_CGBn and
AVDD_Dn and AVDD_SDn_PLLn). AVDD_PLAT, AVDD_CGAn, AVDD_CGBn and
AVDD_Dn voltages must be derived directly from a 1.8 V voltage source through a low
frequency filter scheme. AVDD_SDn_PLLn voltages must be derived directly from the
XnVDD source through a low frequency filter scheme. The recommended solution for
PLL filtering is to provide independent filter circuits per PLL power supply, as illustrated
in Figure 53, one for each of the AVDD pins. By providing independent filters to each
PLL, the opportunity to cause noise injection from one PLL to the other is reduced. This
circuit is intended to filter noise in the PLL's resonant frequency range from a 500 kHz to
10 MHz range.
Each circuit should be placed as close as possible to the specific AVDD pin being
supplied to minimize noise coupled from nearby circuits. It should be possible to route
directly from the capacitors to the AVDD pin, which is on the periphery of the footprint,
without the inductance of vias.
This figure shows the PLL power supply filter circuit.
Where:
• R = 5 Ω ± 5%
• C1 = 10 μF ± 10%, 0603, X5R, with ESL ≤ 0.5 nH
• C2 = 1.0 μF ± 10%, 0402, X5R, with ESL ≤ 0.5 nH

NOTE
A higher capacitance value for C2 may be used to improve
the filter as long as the other C2 parameters do not change
(0402 body, X5R, ESL ≤ 0.5 nH).
NOTE
Keep filter close to pin. Voltage and tolerance for AVDD is
defined at the input of the PLL supply filter and not the pin
of AVDD.
R
1.8 V source AVDD_PLAT, AVDD_CGAn, AVDD_CGBn, AVDD_Dn
C1 C2
Low-ESL surface-mount capacitors

GND
Figure 53. PLL power supply filter circuit
The AVDD_SDn_PLLn signals provide power for the analog portions of the SerDes PLL.
To ensure stability of the internal clock, the power supplied to the PLL is filtered using a
circuit similar to the one shown in following Figure 54. For maximum effectiveness, the
filter circuit is placed as closely as possible to the AVDD_SDn_PLLn balls to ensure it
filters out as much noise as possible. The ground connection should be near the
AVDD_SDn_PLLn balls. The 0.003-µF capacitors closest to the balls, followed by a 4.7-
µF and 47-µF capacitor, and finally the 0.33 Ω resistor to the board supply plane. The
capacitors are connected from AVDD_SDn_PLLn to the ground plane. Use ceramic chip
capacitors with the highest possible self-resonant frequency. All traces should be kept
short, wide, and direct.
0.33 Ω
XnVDD AVDD_SDn_PLLn
47μF 4.7 μF 0.003 μF
0Ω
XnVDD AGND_SDn_PLLn
board GND zero Ω 0603 sized default resistance
with provision to be changed to inductance
Figure 54. SerDes PLL power supply filter circuit
Note the following:

• AVDD_SDn_PLLn should be a filtered version of XnVDD.
• Signals on the SerDes interface are fed from the XnVDD power plane.
• Voltage for AVDD_SDn_PLLn is defined at the PLL supply filter and not the pin of
AVDD_SDn_PLLn.

• A 47-µF 0805 XR5 or XR7, 4.7-µF 0603, and 0.003-µF 0402 capacitor are
recommended. The size and material type are important. A 0.33-Ω ± 1% resistor is
recommended.
• There needs to be dedicated analog ground, AGND_SDn_PLLn for each
AVDD_SDn_PLLn pin up to the physical local of the filters themselves.
4.2.4 SnVDD power supply filtering

SnVDD must be supplied by a decicated linear regulator.
An example solution for SnVDD filtering, where SnVDD is sourced from a linear
regulator, is illustrated in Figure 55. The component values in this example filter are
system dependent and are still under characterization, component values may need
adjustment based on the system or environment noise.
Where:
• C1 = 0.003 μF ± 10%, X5R, with ESL ≤ 0.5 nH
• C2 and C3 = 2.2 μF ± 10%, X5R, with ESL ≤ 0.5 nH
• F1 and F2 are 0603 sized Ferrite SMD, like the Murata part BLM18PG121SH1. Its
maximum DC resistance is 0.05Ω, or 0.025Ω for the parallel resultant, and each has
about a 120 Ω +/- 25% of AC impedance at 100 MHz, which is half valued for the
parallel resultant, with individual maximum DC current carrying capacity of 2Amps.
• Bulk and decoupling capacitors are added, as needed, per power supply design.
Bulk and F1
SnVDD Linear regulator output
decoupling
capacitors C1 C2 C3
F2
GND
Figure 55. SVDD power supply filter circuit
Note the following:

• Please refer to Power-on ramp rate, for maximum SnVDD power-up ramp rate.
• There needs to be enough output capacitance or a soft start feature to assure ramp
rate requirement is met.
• The ferrite beads should be placed in parallel to reduce voltage droop.
• Besides a linear regulator, a low noise dedicated switching regulator can also be
used. 10 mVp-p, 50kHz - 500MHz is the noise goal.

4.2.5 XnVDD power supply filtering

XnVDD may be supplied by a linear regulator or sourced by a filtered GnVDD. Systems
may design in both options to allow flexibility to address system noise dependencies.
However, for initial system bring-up, the linear regulator option is highly recommended.
An example solution for XnVDD filtering, where XnVDD is sourced from a linear
regulator, is illustrated in Figure 56. The component values in this example filter are
system dependent and are still under characterization, component values may need
Where:
• C1 = 0.003 μF ± 10%, X5R, with ESL ≤ 0.5 nH
• F1 and F2 are 0603 sized Ferrite SMD, like the Murata part BLM18PG121SH1. Its
maximum DC resistance is 0.05Ω, or 0.025Ω for the parallel resultant, and each has
about a 120+-25% Ω of AC impedance at 100 MHz, which is half valued for the
parallel resultant, with individual maximum DC current carrying capacity of 2Amps.
Bulk and F1
XnVDD Linear regulator output
decoupling
capacitors C1 C2 C3
F2
GND
Figure 56. XnVDD power supply filter circuit
Note the following:

• See Power-on ramp rate for maximum XnVDD power-up ramp rate.
• There needs to be enough output capacitance or a soft-start feature to assure ramp
rate requirement is met.
• The ferrite beads should be placed in parallel to reduce voltage droop.
• Besides a linear regulator, a low-noise, dedicated switching regulator can be used. 10
mVp-p, 50 kHz - 500 MHz is the noise goal.
4.2.6 USB_HVDD and USB_OVDD power supply filtering

USB_HVDD and USB_OVDD must be sourced by a filtered 3.3 V and 1.8 V voltage
source using a star connection. An example solution for USB_HVDD and USB_OVDD
filtering, where USB_HVDD and USB_OVDD are sourced from a 3.3 V and 1.8 V voltage

source, is illustrated in the following figure. The component values in this example filter
is system dependent and are still under characterization, component values may need
Where:
• C1 = 0.003 μF ± 10%, X5R, with ESL ≤ 0.5 nH
• F1 is an 0603 sized Ferrite SMD, like the Murata part BLM18PG121SH1. Its
maximum DC resistance is 0.05Ω and it has about a 120+-25% Ω of AC impedance
at 100 MHz with maximum DC current carrying capacity of 2Amps.
USB_HVDD Bulk and F1

decoupling 3.3 V or 1.8 V source
or USB_OVDD
capacitors C1 C2 C3
GND
Figure 57. USB_HVDD and USB_OVDD power supply filter circuit
4.2.7 USB_SVDD power supply filtering

USB_SVDD must be sourced by a filtered VDD using a star connection. An example
solution for USB_SVDD filtering, where USB_SVDD is sourced from VDD, is illustrated
in the following figure. The component values in this example filter is system dependent
and are still under characterization, component values may need adjustment based on the
system or environment noise.
Where:
• C1 = 2.2 μF ± 20%, X5R, with Low ESL (for example, Panasonic ECJ0EB0J225M)
• F1 is an 0603 sized Ferrite SMD, like the Murata part BLM18PG121SH1. Its
maximum DC resistance is 0.05Ω and it has about a 120+-25% Ω of AC impedance
at 100 MHz with maximum DC current carrying capacity of 2Amps.

Bulk and F1
USB_SVDD decoupling VDD
capacitors C1 C1
GND
Figure 58. USB_SVDD power supply filter circuit
4.3 Decoupling recommendations

Due to large address and data buses, and high operating frequencies, the device can
generate transient power surges and high frequency noise in its power supply, especially
while driving large capacitive loads. This noise must be prevented from reaching other
components in the chip system, and the chip itself requires a clean, tightly regulated
source of power. Therefore, it is recommended that the system designer place at least one
decoupling capacitor at each VDD, OVDD, DVDD, GnVDD, and LVDD pin of the device.
These decoupling capacitors should receive their power from separate VDD, OVDD,
DVDD, GnVDD, LVDD, and GND power planes in the PCB, utilizing short traces to
minimize inductance. Capacitors may be placed directly under the device using a
standard escape pattern. Others may surround the part.
These capacitors should have a value of 0.1 µF. Only ceramic SMT (surface mount
technology) capacitors should be used to minimize lead inductance, preferably 0402 or
0603 sizes.
As presented in Core and platform supply voltage filtering, it is recommended that there
be several bulk storage capacitors distributed around the PCB, feeding the VDD and other
planes (for example, OVDD, DVDD, GnVDD, and LVDD), to enable quick recharging of
the smaller chip capacitors.
4.4 SerDes block power supply decoupling recommendations

The SerDes block requires a clean, tightly regulated source of power (SnVDD and
XnVDD) to ensure low jitter on transmit and reliable recovery of data in the receiver. An
appropriate decoupling scheme is outlined below.
NOTE
Only SMT capacitors should be used to minimize inductance.
Connections from all capacitors to power and ground should be
done with multiple vias to further reduce inductance.
1. The board should have at least 1 x 0.1-uF SMT ceramic chip capacitor placed as
close as possible to each supply ball of the device. Where the board has blind vias,
these capacitors should be placed directly below the chip supply and ground
connections. Where the board does not have blind vias, these capacitors should be
placed in a ring around the device as close to the supply and ground connections as
possible.
2. Between the device and any SerDes voltage regulator there should be a lower bulk
capacitor for example a 10-uF, low ESR SMT tantalum or ceramic and a higher bulk
capacitor for example a 100uF - 300-uF low ESR SMT tantalum or ceramic
capacitor.
4.5 Connection recommendations

The following is a list of connection recommendations:
• To ensure reliable operation, it is highly recommended to connect unused inputs to
an appropriate signal level. Unless otherwise noted in this document, all unused
active low and open drain I/O inputs should be pulled up to VDD, OVDD, DVDD,
GnVDD, and LVDD as required. All unused active high inputs should be connected to
GND. All NC (no-connect) signals must remain unconnected. Power and ground
connections must be made to all external VDD, OVDD, DVDD, GnVDD, LVDD and
GND pins of the device.
• The TEST_SEL_B pin must be pulled to OVDD through a 100-ohm to 1k-ohm
resistor.
• The chip has temperature diodes that can be used to monitor its temperature by using
some external temperature monitoring devices (such as Analog Devices,
ADT7481A™). For more information, see AN4787. The following are the
specifications of the chip temperature diodes:
• Operating range: 10-230 μA
• Non-ideality factor over temperature range 85C⁰ to 105C⁰, n = 1.006 ± 0.003,
with approximate error +/- 1 C⁰ and error under +/- 3 C⁰ for temperature range 0
C⁰ to 85C⁰.
4.5.1 Legacy JTAG configuration signals

Correct operation of the JTAG interface requires configuration of a group of system
control pins as demonstrated in Figure 60. Care must be taken to ensure that these pins
are maintained at a valid deasserted state under normal operating conditions as most have
asynchronous behavior and spurious assertion will give unpredictable results.

Boundary-scan testing is enabled through the JTAG interface signals. The TRST_B
signal is optional in the IEEE Std 1149.1 specification, but it is provided on all processors
built on Power Architecture technology. The device requires TRST_B to be asserted
during power-on reset flow to ensure that the JTAG boundary logic does not interfere
with normal chip operation. While the TAP controller can be forced to the reset state
using only the TCK and TMS signals, generally systems assert TRST_B during the
power-on reset flow. Simply tying TRST_B to PORESET_B is not practical because the
JTAG interface is also used for accessing the common on-chip processor (COP), which
implements the debug interface to the chip.
The COP function of these processors allow a remote computer system (typically, a PC
with dedicated hardware and debugging software) to access and control the internal
operations of the processor. The COP interface connects primarily through the JTAG port
of the processor, with some additional status monitoring signals. The COP port requires
the ability to independently assert PORESET_B or TRST_B in order to fully control the
processor. If the target system has independent reset sources, such as voltage monitors,
watchdog timers, power supply failures, or push-button switches, then the COP reset
signals must be merged into these signals with logic.
The arrangement shown in Figure 60 allows the COP port to independently assert
PORESET_B or TRST_B, while ensuring that the target can drive PORESET_B as well.
The COP interface has a standard header, shown in Figure 59, for connection to the target
system, and is based on the 0.025" square-post, 0.100" centered header assembly (often
called a Berg header). The connector typically has pin 14 removed as a connector key.
The COP header adds many benefits such as breakpoints, watchpoints, register and
memory examination/modification, and other standard debugger features. An inexpensive
option can be to leave the COP header unpopulated until needed.
There is no standardized way to number the COP header; so emulator vendors have
issued many different pin numbering schemes. Some COP headers are numbered top-to-
bottom then left-to-right, while others use left-to-right then top-to-bottom. Still others
number the pins counter-clockwise from pin 1 (as with an IC). Regardless of the
numbering scheme, the signal placement recommended in Figure 59 is common to all
known emulators.
4.5.1.1 Termination of unused signals

If the JTAG interface and COP header will not be used, NXP recommends the following
connections:
• TRST_B should be tied to PORESET_B through a 0 kΩ isolation resistor so that it is
asserted when the system reset signal (PORESET_B) is asserted, ensuring that the

JTAG scan chain is initialized during the power-on reset flow. NXP recommends
that the COP header be designed into the system as shown in Figure 60. If this is not
possible, the isolation resistor will allow future access to TRST_B in case a JTAG
interface may need to be wired onto the system in future debug situations.
• No pull-up/pull-down is required for TDI, TMS or TDO.
COP_TDO 1 2 NC
COP_TDI 3 4 COP_TRST_B
NC 5 6 COP_VDD_SENSE
COP_TCK 7 8 COP_CHKSTP_IN_B
COP_TMS 9 10 NC
COP_SRESET_B 11 12 NC
COP_HRESET_B KEY
13
No pin
COP_CHKSTP_OUT_B 15 16 GND
Figure 59. Legacy COP Connector Physical Pinout

1 kΩ OVDD
10 kΩ
From target HRESET_B 7
board sources HRESET_B6
(if any)
PORESET_B 10 kΩ
PORESET_B1
COP_HRESET_B
13
COP_SRESET_B 10 kΩ
11
B 10 kΩ
A
5 10 kΩ
1 2
3 4 10 kΩ
5 6
COP_TRST_B TRST_B1
4
7 8 COP_VDD_SENSE2 10 Ω
6
COP header
9 10 5 NC
COP_CHKSTP_OUT_B
11 12 15 CKSTP_OUT_B
KEY
13
No pin 143 10 kΩ
15 16
COP_CHKSTP_IN_B
8 System logic
COP connector COP_TMS
physical pinout 9 TMS
COP_TDO TDO
1
COP_TDI TDI
3
COP_TCK TCK
7
2 NC
10 NC 10 kΩ
4
12
16
Notes:
1. The COP port and target board should be able to independently assert PORESET_B and TRST_B to the processor in
order to fully control the processor as shown here.
2. Populate this with a 10 Ω resistor for short-circuit/current-limiting protection.
3. The KEY location (pin 14) is not physically present on the COP header.
4. Although pin 12 is defined as a no-connect, some debug tools may use pin 12 as an additional GND pin for improved signal integrity.
5. This switch is included as a precaution for BSDL testing. The switch should be closed to position A during BSDL testing to avoid accidentally
asserting the TRST_B line. If BSDL testing is not being performed, this switch should be closed to position B.
6. Asserting HRESET_B causes a hard reset on the device
7. This is an open-drain output gate.
Figure 60. Legacy JTAG Interface Connection

4.5.2 Aurora configuration signals

Correct operation of the Aurora interface requires configuration of a group of system
control pins as demonstrated in the figures below. Care must be taken to ensure that these
pins are maintained at a valid deasserted state under normal operating conditions as most
have asynchronous behavior and spurious assertion will give unpredictable results.
NXP recommends that the Aurora 34 pin duplex connector be designed into the system as
shown in Figure 63 or the 70 pin duplex connector be designed into the system as shown
in Figure 64.
If the Aurora interface will not be used, NXP recommends the legacy COP header be
designed into the system as described in Termination of unused signals .

TX0_P 1 2 VIO (VSense)
TX0_N 3 4 TCK
GND 5 6 TMS
TX1_P 7 8 TDI
TX1_N 9 10 TDO
GND 11 12 TRST
RX0_P 13 14 Vendor I/O 0
RX0_N 15 16 Vendor I/O 1
GND 17 18 Vendor I/O 2
RX1_N 21 22 RESET
GND 23 24 GND
TX2_P 25 26 CLK_P
TX2_N 27 28 CLK_N
GND 29 30 GND
TX3_P 31 32 Vendor I/O 4
TX3_N 33 34 Vendor I/O 5
Figure 61. Aurora 34 pin connector duplex pinout

TX0_P 1 2 VIO (VSense)
TX0_N 3 4 TCK
GND 5 6 TMS
TX1_P 7 8 TDI
TX1_N 9 10 TDO
GND 11 12 TRST
RX0_N 15 16 Vendor I/O 1
GND 17 18 Vendor I/O 2
RX1_N 21 22 RESET
GND 23 24 GND
TX2_P 25 26 CLK_P
TX2_N 27 28 CLK_N
GND 29 30 GND
TX3_P 31 32 Vendor I/O 4
TX3_N 33 34 Vendor I/O 5
GND 35 36 GND
RX2_P 37 38 N/C
RX2_N 39 40 N/C
GND 41 42 GND
RX3_P 43 44 N/C
RX3_N 45 46 N/C
GND 47 48 GND
TX4_P 49 50 N/C
TX4_N 51 52 N/C
GND 53 54 GND
TX5_P 55 56 N/C
TX5_N 57 58 N/C
GND 59 60 GND
TX6_P 61 62 N/C
TX6_N 63 64 N/C
GND 65 66 GND
TX7_P 67 68 N/C
TX7_N 69 70 N/C
Figure 62. Aurora 70 pin connector duplex pinout

1 kΩ OVDD
10 kΩ
(if any)
PORESET_B 10 kΩ
PORESET_B1
RESET
22
10 kΩ
20, 25 NC
27, 31 B
A
1 2
32, 33
3 4
3 10 kΩ
5 6
7 8
9 10
11 12
10 kΩ
13 14
AURORA_TRST_B TRST_B1
15 16
12
17 18 VIO VSense2 1 kΩ
2
19 20
AURORA_TMS
21 22
6 TMS
AURORA_TDO
23 24
10 TDO
AURORA_TDI
25 26
8 TDI
4 AURORA_TCK
27 28 TCK
Vendor I/O 5 (Aurora_HRESET_B)
29 30 34
Vendor I/O 2 (Aurora_Event_Out_B) 10 kΩ
31 32 18 EVT4_B
Vendor I/O 1 (Aurora_Event_In_B)
33 34
16 EVT1_B
Vendor I/O 0 (Aurora_HALT_B)
14 EVT0_B
Duplex 34 Connector CLK 100 nF
Physical Pinout 26 SD4_REF_CLKn
28 CLK_B 100 nF
SD4_REF_CLKn_B
1 TX0
SD4_TX5
3 TX0_B SD4_TX5_B
TX1
7 SD4_TX4
TX1_B SD4_TX4_B
9
RX0 0.01 uF
13 SD4_RX5
RX0_B 0.01 uF
15 SD4_RX5_B
RX1 0.01 uF
19 SD4_RX4
RX1_B 0.01 uF
21 SD4_RX4_B
5, 11, 17 6 6
23, 24
REF_CLK1
29, 30 REF_CLK REF_CLK1_B
REF_CLK_B
Notes:
1. The Aurora port and target board should be able to independently assert PORESET_B and TRST_B to the processor in
2. Populate this with a 1 kΩ resistor for short-circuit/current-limiting protection.
6. REF_CLK/REF_CLK_B and REF_CLK1/REFCLK1_B are buffered clocks from the same common source.
Figure 63. Aurora 34 pin connector duplex interface connection

1 kΩ
OVDD
10 kΩ
(if any)
PORESET_B 10 kΩ
PORESET_B1
1 2
3 4 Reset
5 6
22
7 8
20, 25, 27, 31, 10 kΩ
32, 33, 37, 38,
9 10
39, 40, 43, 44, B
11 12
45, 46, 49, 50, NC A
13 14
51, 52, 55, 56,
15 16
57, 58, 61, 62, 3 10 kΩ
17 18 63, 64, 67, 68,
19 20 69, 70
21 22
10 kΩ
23 24
25 26
AURORA_TRST_B TRST_B1
27 28
12
29 30 VIO VSense2
2
31 32
6 AURORA_TMS 1 kΩ
33 34
TMS
AURORA_TDO
35 36
10 TDO
8 AURORA_TDI
37 38 TDI
4 AURORA_TCK
39 40 TCK
Aurora Header
Vendor I/O 5 (Aurora_HRESET_B)

41 42
34
CLK 100 nF 10 kΩ SD4_REF_CLKn
43 44
26
45 46 CLK_B 100 nF SD4_REF_CLKn_B
28
47 48
Vendor I/O 2 (Aurora_Event_Out_B)
18 EVT4_B
49 50
16 Vendor I/O 1 (Aurora_Event_In_B)

51 52 EVT1_B
14 Vendor I/O 0 (Aurora_HALT_B)
53 54 EVT0_B
1 TX0
55 56 SD4_TX5
57 58 3 TX0_B SD4_TX5_B
TX1
59 60
7 SD4_TX4
61 62 TX1_B SD4_TX4_B
9
63 64
RX0 0.01 uF
65 66
13 SD4_RX5
RX0_B 0.01 uF
67 68 15 SD4_RX5_B
RX1 0.01 uF
69 70 19 SD4_RX4
RX1_B 0.01 uF
21 SD4_RX4_B
Duplex 70 Connector 6 6
5, 11, 17, 23, 24,
Physical Pinout 29, 30, 35, 36, 41,
42, 47, 48, 53, 54, REF_CLK1
REF_CLK REF_CLK1_B
59, 60, 65, 66 REF_CLK_B
Notes:
1. The Aurora port and target board should be able to independently assert PORESET_B and TRST_B to the processor in
2. Populate this with a 1 kΩ resistor for short-circuit/current-limiting protection.
6. REF_CLK/REF_CLK_B and REF_CLK1/REFCLK1_B are buffered clocks from the same common source.
Figure 64. Aurora 70 pin connector duplex interface connection

4.5.3 Guidelines for high-speed interface termination
4.5.3.1 SerDes interface entirely unused

If the high-speed SerDes interface is not used at all, the unused pin should be terminated
as described in this section.
Note that SnVDD, XnVDD and AVDD_SDn_PLLn must remain powered.
For AVDD_SDn_PLLn, it must be connected to XnVDD through a zero ohm resistor
(instead of filter circuit shown in Figure 54).
The following pins must be left unconnected:

• SDn_TX[7:0]
• SDn_TX[7:0]_B
• SDn_IMP_CAL_RX
• SDn_IMP_CAL_TX
The following pins must be connected to SnGND:
• SDn_REF_CLK1, SDn_REF_CLK2
• SDn_REF_CLK1_B, SDn_REF_CLK2_B
It is recommended for the following pins to be connected to SnGND:
• SDn_RX[7:0]
• SDn_RX[7:0]_B
It is possible to independently disable each SerDes module by disabling all PLLs
associated with it.
SerDes n = 1:4 is disabled as follows:
• SRDS_PLL_PD_Sn = 2’b11 (both PLLs configured as powered down, all data lanes
selected by the protocols defined in SRDS_PRTCL_Sn associated to the PLLs are
powered down as well)
• SRDS_PLL_REF_CLK_SEL_Sn = 2’b00
• SRDS_PRTCL_Sn = 2 (no other values permitted when both PLLs are powered
down

4.5.3.2 SerDes interface partly unused

If only part of the high speed SerDes interface pins are used, the remaining high-speed
serial I/O pins should be terminated as described in this section.
Note that both SnVDD and XnVDD must remain powered.
If any of the PLLs are un-used, the corresponding AVDD_SDn_PLLn must be connected
to XnVDD through a zero ohm resistor (instead of filter circuit shown in Figure 54).
The following unused pins must be left unconnected:
• SDn_TX[n]
• SDn_TX[n]_B
The following unused pins must be connected to SnGND:
• SD1_REF_CLK[1:2], SD1_REF_CLK[1:2]_B (If entire SerDes 1 unused)
It is recommended for the following unused pins to be connected to SnGND:
• SDn_RX[n]
• SDn_RX[n]_B
In the RCW configuration field SRDS_PLL_PD_Sn, the respective bits for each unused
PLL must be set to power it down. A module is disabled when both its PLLs are turned
off.
Unused lanes must be powered down through the SRDSx Lane m General Control
Register 0 (SRDSxLNmGCR0) as follows:
• SRDSxLNmGCR0[RRST] = 0
• SRDSxLNmGCR0[TRST] = 0
• SRDSxLNmGCR0[RX_PD] = 1
• SRDSxLNmGCR0[TX_PD] = 1
Note that in the case where the SerDes pins are connected to slots , it is acceptable to
have these pins unterminated when unused.
4.5.4 USB controller connections

This section details the hardware connections required for the USB controllers.

4.5.4.1 USB divider network

This figure shows the required divider network for the VBUS interface for the chip.
Additional requirements for the external components are:
• Both resistors require 1% accuracy and a current capability of up to 1 mA. They must
both have the same temperature coefficient and accuracy.
• The zener diode must have a value of 5 V−5.25 V.
• The 0.6 V diode requires an IF = 10 mA, IR < 500 nA and VF(Max) = 0.8 V. If the
USB PHY does not support OTG mode, this diode can be removed from the
schematic or made a DNP component.
USBn_DRVVBUS
VBUS VBUS charge
(USB connector) pump USBn_PWRFAULT
51.2 k Ω 0.6 VF
5 VZ
USBn_VBUSCLMP
18.1 k Ω
Chip
Figure 65. Divider network at VBUS
4.6 Thermal
This table shows the thermal characteristics for the chip. Note that these numbers are
based on design estimates and are preliminary.
Table 148. Package thermal characteristics6
Rating Board Symbol Value Unit Notes
Junction to ambient, natural convection Single-layer board (1s) RΘJA 11 °C/W 1, 2
Junction to ambient, natural convection Four-layer board (2s2p) RΘJA 9 °C/W 1, 3
Junction to ambient (at 200 ft./min.) Single-layer board (1s) RΘJMA 8 °C/W 1, 2
Junction to ambient (at 200 ft./min.) Four-layer board (2s2p) RΘJMA 6 °C/W 1, 2
Junction to board - RΘJB 3 °C/W 3
Junction to case top - RΘJCtop 0.3 °C/W 4
Junction to lid top - RΘJClid 0.11 °C/W 5

Table 148. Package thermal characteristics6 (continued)

Rating Board Symbol Value Unit Notes
1. Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site
(board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal
resistance.
2. Per JEDEC JESD51-3 and JESD51-6 with the board (JESD51-9) horizontal.
3. Thermal resistance between the die and the printed-circuit board per JEDEC JESD51-8. Board temperature is measured
on the top surface of the board near the package.
4. Junction-to-case-top at the top of the package determined using MIL-STD 883 Method 1012.1. The cold plate temperature
is used for the case temperature. Reported value includes the thermal resistance of the interface layer.
5. Junction-to-lid-top thermal resistance determined using the using MIL-STD 883 Method 1012.1. However, instead of the
cold plate, the lid top temperature is used here for the reference case temperature. Reported value does not include the
thermal resistance of the interface layer between the package and cold plate.
6. See Thermal management information, for additional details.
4.7 Recommended thermal model

Information about Flotherm models of the package or thermal data not available in this
document can be obtained from your local NXP sales office.
4.8 Thermal management information

This section provides thermal management information for the flip-chip, plastic-ball, grid
array (FC-PBGA) package for air-cooled applications. Proper thermal control design is
primarily dependent on the system-level design-the heat sink, airflow, and thermal
interface material.
The recommended attachment method to the heat sink is illustrated in Figure 66. The heat
sink should be attached to the printed-circuit board with the spring force centered over
the die. This spring force should not exceed 60 pounds force (270 Newtons).

FC-PBGA package (with lid)

Heat sink
Heat sink clip
Adhesive or
Die lid
thermal interface material
Die
Lid adhesive
Printed circuit-board
Figure 66. Package exploded, cross-sectional view-FC-PBGA (with lid)
The system board designer can choose between several types of heat sinks to place on the
device. There are several commercially-available thermal interfaces to choose from in the
industry. Ultimately, the final selection of an appropriate heat sink depends on many
factors, such as thermal performance at a given air velocity, spatial volume, mass,
attachment method, assembly, and cost.
4.8.1 Internal package conduction resistance

For the package, the intrinsic internal conduction thermal resistance paths are as follows:
• The die junction-to-case thermal resistance
• The die junction-to-lid-top thermal resistance
• The die junction-to-board thermal resistance
This figure depicts the primary heat transfer path for a package with an attached heat sink
mounted to a printed-circuit board.

External resistance Radiation Convection
Heat sink Junction to case top
Thermal interface material

Junction to lid top
Die/Package
Internal resistance Die junction
Package/Solder balls
Printed-circuit board
External resistance Radiation Convection
(Note the internal versus external package resistance)
Figure 67. Package with heat sink mounted to a printed-circuit board
The heat sink removes most of the heat from the device. Heat generated on the active side
of the chip is conducted through the silicon and through the heat sink attach material (or
thermal interface material), and finally to the heat sink. The junction-to-case thermal
resistance is low enough that the heat sink attach material and heat sink thermal
resistance are the dominant terms.
4.8.2 Thermal interface materials

A thermal interface material is required at the package-to-heat sink interface to minimize
the thermal contact resistance. The performance of thermal interface materials improves
with increasing contact pressure; this performance characteristic chart is generally
provided by the thermal interface vendor. The recommended method of mounting heat
sinks on the package is by means of a spring clip attachment to the printed-circuit board
(see Figure 66).

Package information
The system board designer can choose among several types of commercially-available
thermal interface materials.
5 Package information
5.1 Package parameters for the FC-PBGA

The package parameters are as provided in the following list. The package type is 45 mm
x 45 mm, 1932 flip-chip, plastic-ball, grid array (FC-PBGA).
• Package outline - 45 mm x 45 mm
• Interconnects - 1932
• Ball Pitch - 1.0 mm
• Ball Diameter (typical) - 0.60 mm
• Solder Balls - 96.5% Sn, 3% Ag, 0.5% Cu
• Module height (typical) - 3.03 mm to 3.33 mm (maximum)
5.2 Mechanical dimensions of the FC-PBGA

This figure shows the mechanical dimensions and bottom surface nomenclature of the
chip.

Package information
Figure 68. Mechanical dimensions of the FC-PBGA with full lid

Security fuse processor
NOTES:
1. All dimensions are in millimeters.
2. Dimensions and tolerances per ASME Y14.5M-1994.
3. Maximum solder ball diameter measured parallel to datum A.
4. Datum A, the seating plane, is determined by the spherical crowns of the solder balls.
5. Parallelism measurement shall exclude any effect of mark on top surface of package.
6 Security fuse processor

This chip implements the QorIQ platform's Trust Architecture, supporting capabilities
such as secure boot. Use of the Trust Architecture features is dependent on programming
fuses in the Security Fuse Processor (SFP). The details of the Trust Architecture and SFP
can be found in the chip reference manual.
To program SFP fuses, the user is required to supply 1.8 V to the PROG_SFP pin per
Power sequencing. PROG_SFP should only be powered for the duration of the fuse
programming cycle, with a per device limit of two fuse programming cycles. All other
times PROG_SFP should be connected to GND. The sequencing requirements for raising
and lowering PROG_SFP are shown in Figure 8. To ensure device reliability, fuse
programming must be performed within the recommended fuse programming
temperature range per Table 3.
NOTE
Users not implementing the QorIQ platform's Trust
Architecture features should connect PROG_SFP to GND.
7 Ordering information
Contact your local NXP sales office or regional marketing team for order information.
7.1 Part numbering nomenclature

This table provides the NXP QorIQ platform part numbering nomenclature.

Ordering information
Table 149. Part numbering nomenclature

pt or t n nn n x t e n c d r
Number of virtual cores
Temperature range
DDR data rate

Package type
Die revision
Encryption
CPU speed
Qual status
Generation
Derivative
Platform
PT = 28 nm 4 24 = 24 0= P= S= E = SEC 7 = FC- P = Q= A=
(Prototype) virtual Standard Prototype Standard present PBGA 1500 MHz 1600 MT/s Rev
cores power temp C4/C5 1.0
T = 28 nm N= N = SEC Q= T= 1866
Pb-free
(Production) 16 = 16 1 = Low Qualified X= not 1667 MHz MT/s B=
virtual power to Extended present Rev 2.0
T= Z= TBD
cores industrial temp
1800 MHz
tier
08 = 8
virtual
cores
7.2 Orderable part numbers addressed by this document

This table provides the NXP orderable part numbers addressed by this document for the
chip.
Table 150. Orderable part numbers addressed by this document
Part number pt or t n nn n x t e n c d r
(Freq-Core/Freq-
Platform/Freq-DDR
(MT/s))
T4240NSE7PQB T=28 4 24=24 0 N=Qualifie S=Std E=SEC 7 P=1500 M Q=1600 M B =
nm virtual d temp present Hz CPU T/s DDR Rev
cores 2.0
T4240NSE7QTB T=28 4 24=24 0 N=Qualifie S=Std E=SEC 7 Q=1667 M T=1866 M B =
nm virtual d temp present Hz CPU T/s DDR Rev
cores 2.0
T4240NSN7PQB T=28 4 24=24 0 N=Qualifie S=Std N=No 7 P=1500 M Q=1600 M B =
nm virtual d temp SEC Hz CPU T/s DDR Rev
cores present 2.0
T4240NSN7QTB T=28 4 24=24 0 N=Qualifie S=Std N=No 7 Q=1667 M T=1866 M B =
nm virtual d temp SEC Hz CPU T/s DDR Rev
cores present 2.0

Ordering information
Table 150. Orderable part numbers addressed by this document (continued)

(Freq-Core/Freq-
Platform/Freq-DDR
(MT/s))
T4240NSE7TTB T = 28 4 24=24 0 N=Qualifie S=Std E= SEC 7 T=1800 T=1866 B=
nm virtual d temp present MHz CPU MT/S Rev
cores DDR 2.0
T4240NSN7TTB T = 28 4 24=24 0 N=Qualifie S=Std N = No 7 T=1800 T=1866 B=
nm virtual d temp SEC MHz CPU MT/S Rev
cores present DDR 2.0
T4240NXE7PQB T=28 4 24=24 0 N=Qualifie X=extende E=SEC 7 P=1500 M Q=1600 M B =
nm virtual d d temp present Hz CPU T/s DDR Rev
cores 2.0
T4240NXN7PQB T=28 4 24=24 0 N=Qualifie X=extende N=No 7 P=1500 M Q=1600 M B =
nm virtual d d temp SEC Hz CPU T/s DDR Rev
cores present 2.0
T4241NSE7PQB T=28 4 24=24 1 N=Qualifie S= Std E=SEC 7 P=1500 Q=1600 M B =
nm virtual d temp present MHz CPU T/s DDR Rev
cores 2.0
T4241NSE7QTB T=28 4 24=24 1 N=Qualifie S= Std E=SEC 7 Q=1667 M T=1866 B=
nm virtual d temp present Hz CPU MT/s DDR Rev
cores 2.0
T4241NSE7TTB T=28 4 24=24 1 N=Qualifie S= Std E=SEC 7 T=1800 T=1866 B=
nm virtual d temp present MHz CPU MT/s DDR Rev
cores 2.0
T4241NSN7PQB T=28 4 24=24 1 N=Qualifie S= Std N = SEC 7 P=1500 Q=1600 M B =
nm virtual d temp not MHz CPU T/s DDR Rev
cores present 2.0
T4241NSN7QTB T=28 4 24=24 1 N=Qualifie S= Std N = SEC 7 Q=1667 M T=1866 B=
nm virtual d temp not Hz CPU MT/s DDR Rev
cores present 2.0
T4241NSN7TTB T=28 4 24=24 1 N=Qualifie S= Std N = SEC 7 T=1800 T=1866 B=
nm virtual d temp not MHz CPU MT/s DDR Rev
cores present 2.0
T4241NXE7PQB T=28 4 24=24 1 N=Qualifie X=extende E=SEC 7 P=1500 Q=1600 M B =
nm virtual d d temp present MHz CPU T/s DDR Rev
cores 2.0
T4241NXE7QTB T=28 4 24=24 1 N=Qualifie X=extende E=SEC 7 Q=1667 M T=1866 B=
nm virtual d d temp present Hz CPU MT/s DDR Rev
cores 2.0
T4241NXE7TTB T=28 4 24=24 1 N=Qualifie X=extende E=SEC 7 T=1800 T=1866 B=
nm virtual d d temp present MHz CPU MT/s DDR Rev
cores 2.0
T4241NXN7PQB T=28 4 24=24 1 N=Qualifie X=extende N = SEC 7 P= Q=1600 M B =
nm virtual d d temp not 1500MHz T/s DDR Rev
cores present CPU 2.0
T4241NXN7QTB T=28 4 24=24 1 N=Qualifie X=extende N = SEC 7 Q=1667 M T=1866 B=
nm virtual d d temp not Hz CPU MT/s DDR Rev
cores present 2.0

Revision history
Table 150. Orderable part numbers addressed by this document (continued)

(Freq-Core/Freq-
Platform/Freq-DDR
(MT/s))
T4241NXN7TTB T=28 4 24=24 1 N=Qualifie X=extende N = SEC 7 T=1800 T=1866 B=
nm virtual d d temp not MHz CPU MT/s DDR Rev
cores present 2.0
Notes:
1. The 1866 MT/s DDR rate is associated with 733 MHz platform frequency in high speed parts while the 1600 MT/s DDR
rate is associated with 667 MHz platform clock frequency in lower speed parts in the part number encoding.
2. The T4241/T4161/T4081 are identical to T4240/T4160/T4080 except they consume less power. See the power
requirements in Power characteristics.
7.2.1 Part marking

Parts are marked as in the example shown in this figure.
T424nxtencdr
ATWLYYWW
MMMMMM CCCCC
YWWLAZ
FC-PBGA
Legend:
T424nxtencdr is the orderable part number.
ATWLYYWW is the test traceability code.
MMMMMM is the mask number.
CCCCC is the country code.
YWWLAZ is the assembly traceability code.
Figure 69. Part marking for T424n FC-PBGA chip
8 Revision history
This table summarizes revisions to this document.

Revision history
Table 151. Revision history

Revision Date Description
1 05/2016 • Updated the document title to conform with new naming requirements.
• Rebranded to NXP company name.
• Removed all references to and sections for 10.3215G Interlaken.
• Updated the speed units throughout the document.
• In the pinout list table:
• Modified notes 6, 8, 23, and 24.
• Added note 29.
• Added note 28 to the D3_MDMn pins.
• Changed the note reference on IFC_AD16 to 29.
• Updated note 29 so the pull down resistance is 4.7 K instead of 10 to 50 kΩ.
• In Table 2 :
• Changed format to group "Supply Voltage Levels," "Storage Temperature Conditions,"
and "Signal Voltage Levels."
• Reduced Maximum VDD, SnVDD supply voltage level from 1.1 V to 1.08 V.
• Reduced the max GnVDD I/O voltage levels from 1.65 to 1.58 (DDR3) and from 1.45 to
1.42 (DDR3L).
• Increased the storage temperature range max value from 150 to 155.
• Added "Min_DCV V_input," "Max_DCV V_input," and "Max Overshoot Voltage"
columns for Signal Voltage level signals.
• In the SerDes signals, added additional rows for "No internal termination selected" and
"50 ohm internal termination selected".
• Added the LP Trust signal LP_TMP_DETECT_B.
• Renamed "USBn_VIN_3P3" and "USBn_VIN_1P8" in note 5 and stressed the max slew
rate of Dn_MVREF to 25 kv/s.
• Updated note 9 to include "See also note 6 in Table 3".
• Updated note 10 to include required biasing.
• Added notes 11, 12, and 13.
• In Table 3, added table note 11 and added the LP Trust signal.
• Updated Figure 7.
• In Power sequencing, added a paragraph for VDD_LP special power sequencing. Also relaxed
power lines stability time from 75 ms to 400 ms.
• In Table 6 :
• Added 1.8 GHz power numbers.
• Updated note 9.
• In Table 8 :
• Added 1.8 GHz power numbers.
• Changed the 1667 MHz freq DDR data rate from 1867 to 1866.
• Updated note 9.
• Added Table 7 and Table 9 for the T4241 low-power device.
• In Table 10 :
• Added the 1.8 GHz frequency.
• Added the T4240/T4160 and T4080 LPM20 data.
• Updated power numbers so they are relevant to 65°C.
• Added a note saying that these numbers are good for the T4241 device.
• In Table 11 :
• Reduced the 1600 MT/s GVDD typical and max values from 3150 to 3100 and 4920 to
4900, respectively.
• Improved the PLL_SerDes typical value from 40 to 60.
• Added a formula for XVDD and SVDD typical power estimation rather than have multiple
rows showing different SerDes configuration power.
• Removed the note: "Maximum DDR power numbers are based on one 2-rank DIMM
with 100% utilization," (previously note 5) and renumbered the notes.
• Updated note 6 and added example.
• Added low power devices to the table title.

Revision history
Table 151. Revision history (continued)

Revision Date Description
• In Table 13, included RTC clock DC specifications and updated the input capacitance data for
both SYSCLK and RTC clock pins.
• In Table 14, changed the maximum SYSCLK AC swing value from "TBD" to "1 x OVDD" and
updated note 6.
• In "SYSCLK and RTC AC timing specifications," added Table 15, "RTC AC timing
specification."
• In Real-time clock (RTC) timing, removed the 50% duty cycle requirement from the RTC
period minimum.
• In Table 19, changed the DDRCLK input pin capacitance typical value from 7 to 11 and
removed the max value.
• In Table 20 :
• Changed the minimum DDRCLK cycle time from 5 ns to 7.5 ns.
• Changed the maximum DDRCLK AC swing value from "TBD" to "1 x OVDD".
• Updated note 6.
• In Table 21, relaxed HRESET_B signal rise/fall time to 4 SYSCLK cycles.
• In Table 29, updated the SPI_MOSI hold time min and SPI_MOSI delay max formulas.
• Updated the tMDKHDX delay equation presentation in Table 38 and Table 39. (When
MDIO_CFG[NEG] = 0 then Y = 0.5 and tMDKHDX is Y x TMDC_ClK ± 3 ns.)
• In Table 42 :
• Updated the TSEC_1588_CLK_IN clock period min value and removed the max value.
• Updated the TSEC_1588_CLK_OUT clock period min value.
• Added "hold time" to TSEC_1588_ALARM_OUT1/2.
• Changed the TSEC_1588_TRIG_IN1/2 pulse width min value.
• Removed notes 4 and 5 and updated notes 1 and 2.
• Updated all note references.
• In Table 46, changed VOH/VOL min and max from (0.8 x OVDD, 0.4) to (1.6 V, 0.32 V).
• In Table 55, changed IOL at 1.8 V from 1 mA to 3 mA.
• In "GPIO DC electrical characteristics," added Table 59, "LP_TMP_DETECT_B pin DC
electrical characteristics."
• In Table 76, Table 84, and Table 111, removed the absolute output voltage limits (min -0.4 V,
max 2.30 V).
• In Table 105, changed the figure reference in note 2 from Figure 43 to Figure 42.
• In Table 122, added note 2 and 3 and updated all note references.
• In Table 127, added the 1800 MHz data columns and added note 8 to describe why FMAN
might have two different minimum frequencies.
• In Table 133, changed the 133.333 MHz DDRCLK frequency example value to 1866.667.
• In Table 137, added the 1800 MHz Core cluster: SYSCLK Ratio options.
• In Minimum platform frequency requirements for high-speed interfaces, removed the SRIO
equation that shows minimum platform frequency.
• In Table 147, changed the VDD voltage note for "All other values". After the table, added
paragraph for if DA_ALT_V is not all zeroes.
• In PLL power supply filtering, updated the second NOTE.
• Updated Figure 53 and Figure 54.
• In Connection recommendations, added the expected temperature error to the non-ideality
factor temperature range.
• Updated Mechanical dimensions of the FC-PBGA to include package parameters.
• In Table 149 :
• Added 16 and 08 cores to column nn.
• Changed column n to "0 = Standard power; 1 = Low power".
• Added symbol "T = 1800 MHz" to column C.
• In Orderable part numbers addressed by this document, added two new orderable 1.8 G parts
and added T4241 part numbers.
• Updated Part marking to include low power numbers.
0 07/2014 Initial release

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Document Number T4240

Revision 1, 05/2016
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NXP Semiconductors Document Number T4240

Data Sheet: Technical Data Rev. 1, 05/2016

2 Pin assignments.................................................................................... 3 3.17 I2C interface.............................................................................. 127

2.1 1932 ball layout diagrams......................................................... 4 3.18 GPIO interface...........................................................................130

2.2 Pinout list...................................................................................10 3.19 High-speed serial interfaces (HSSI).......................................... 132

3 Electrical characteristics.......................................................................73 4 Hardware design considerations...........................................................188

3.1 Overall DC electrical characteristics......................................... 73 4.1 System clocking........................................................................ 188

3.2 Power sequencing......................................................................80 4.2 Power supply design..................................................................204

3.3 Power-down requirements.........................................................82 4.3 Decoupling recommendations................................................... 213

3.5 Power-on ramp rate................................................................... 90 4.5 Connection recommendations................................................... 214

3.6 Input clocks............................................................................... 91 4.6 Thermal......................................................................................225

3.9 eSPI interface.............................................................................103 5 Package information.............................................................................229

IEEE Std 1588........................................................................... 107 6 Security fuse processor.........................................................................231

3.12 USB interface............................................................................ 116 7 Ordering information............................................................................231

3.13 Integrated flash controller..........................................................118 7.1 Part numbering nomenclature....................................................231

3.15 Multicore programmable interrupt controller (MPIC).............. 123 8 Revision history....................................................................................234

QorIQ T4240 Data Sheet, Rev. 1, 05/2016

Power Architecture Power Architecture Power Architecture Power Architecture

512 KB 64-bit DDR3/3L

Power mgmt FMan FMan

SD/MMC Parse, classify, Parse, classify, 3x DMA Watch point

Figure 1. Block diagram

QorIQ T4240 Data Sheet, Rev. 1, 05/2016

2.1 1932 ball layout diagrams

QorIQ T4240 Data Sheet, Rev. 1, 05/2016

J SEE DETAIL A SEE DETAIL B J

AL SEE DETAIL C SEE DETAIL D AL

DDR Interface 1 DDR Interface 2 DDR Interface 3 IFC DUART

I2C eSPI eSDHC MPIC LP Trust

Trust System Control ASLEEP Clocking DDR Clocking

Debug DFT JTAG SerDes 1 SerDes 2

SerDes 3 SerDes 4 USB PHY 1 and 2 USB CLK IEEE1588

Ethernet MI 1 Ethernet MI 2 Ethernet Cont. 1 Ethernet Cont. 2 DMA

Analog signals Power Ground No Connects

Figure 2. Complete BGA Map for the T4240

QorIQ T4240 Data Sheet, Rev. 1, 05/2016

D1_ D1_ D1_ D1_ D1_ D1_ EC2_ EC1_

D1_ D1_ D1_ D1_ D1_ EC1_ TSEC_A

D1_ D1_ D1_ D1_ D1_ D1_ TSEC_T TSEC_T SD1_

D1_ D1_ D1_ D1_ D1_ SD1_ SD1_ SD1_

D1_ D1_ D1_ D1_ D1_ D1_ SENSE SENSE

D1_ D1_ D1_ D1_ D1_

D1_ D1_ D1_ D1_ D1_ D1_

D1_ D1_ D1_ D1_ D1_ D1_ D1_

D1_ D1_ D1_ D1_ D1_ D1_ D1_ D1_ D1_

D1_ D1_ D1_ D1_ D1_ D1_

D1_ D1_ D1_ D1_ D1_ D1_ D1_ D1_ D1_

I2C eSPI eSDHC MPIC LP Trust

Trust System Control ASLEEP Clocking DDR Clocking

Debug DFT JTAG SerDes 1 SerDes 2

SerDes 3 SerDes 4 USB PHY 1 and 2 USB CLK IEEE1588

Ethernet MI 1 Ethernet MI 2 Ethernet Cont. 1 Ethernet Cont. 2 DMA

Analog signals Power Ground No Connects

QorIQ T4240 Data Sheet, Rev. 1, 05/2016

USB1_ IFC_ IFC_ IFC_ IFC_ IFC_

SD2_ SD2_ SD2_ SD2_ USB1_ IFC_ IFC_ IFC_

SD2_ SD2_ SD2_ SD2_ IFC_ IFC_ IFC_

SD2_ SD2_ SD2_ SD2_ USB_ IFC_ IFC_

USB_ IFC_ IFC_