Ece 3-1 Lab Manual

(An Autonomous Institution approved by UGC and affiliated to JNTUH))
(Accredited by NAAC with ‘A” Grade, Accredited by NBA of AICTE and

Recipient of World Bank under TEQIP-I and II )
Yamnampet, Ghatkesar Mandal, Hyderabad - 501 301
LAB MANUALS
For
MICROPROCESSOR &
MICRO CONTROLLERS
(From Page No. 1 to 96)
&
IC APPLICATIONS
(From Page No. 97 to 158 )
DIGITAL COMMUNICATIONS
(From Page No. 159 to End)
FOR
B. Tech. III year - I Semester
ECE Branch
DEPARTMENT OF ELECTRONICS & COMMUNICATION

ENGINEERING
JUNE-2020
SREENIDHI INSTITUTE OF SCIENCE ANDTECHNOLOGY
(AN AUTONOMOUS INSTITUTION UNDER JNTUH)
(Approved by AICTE & Aided by World Bank under TEQIP )
Yamnampet, Ghatkesar Mandal, Hyderabad - 501 301.
LAB MANUAL
For
MICROPROCESSORS & MICROCONTROLLERS
For
B. Tech. III year - I Semester
ECE Branch
DEPARTMENT OF
ELECTRONICS & COMMUNICATION ENGINEERING
JUNE 2019
1
PREFACE
The significance of the Microprocessors and Microcontrollers Lab is renowned in the

various fields of engineering applications. For an Electrical Engineer, it is obligatory to have the
practical ideas about the applications of Microprocessors and Microcontrollers. By this
perspective we have introduced a Laboratory manual cum Observation for Microprocessors and
Microcontrollers Lab.
The manual uses the plan, cogent and simple language to explain the fundamental aspects of
Microprocessors and Microcontrollers in practical. The manual prepared very carefully with our
level best. It gives all the steps in executing an experiment.
GUIDELINES TO WRITE YOUR OBSERVATION BOOK
1. Assembly Language Programs (ALP‟s), Algorithm, Theoretical Result and Practical Result
should be on right side.
2. Flow Chart should be left side.
3. Result should always be in the ending.
4. You all are advised to leave sufficient no of pages between ALP‟s for theoretical or
Model calculations purpose.
2
DO’S AND DON’TS IN THE LAB
DO’S:-
1. Proper dress has to be maintained while entering in the Lab. (Boys Tuck in and shoes and girls
should be neatly dressed)
2. Students should carry observation notes and record completed in all aspects.
3. ALP and its theoretical result should be there in the observation before coming to the next lab.
4. Student should be aware of next ALPs.
5. Students should be at their concerned desktop, unnecessary moment is restricted.
6. Student should follow the procedure to start executing the ALP they have to get signed by the
Lab instructor for theoretical result then with the permission of Lab instructor they need to
switch on the desktop and after completing the same they need to switch off and keep the chairs
properly.
7. After completing the ALP Students should verify the ALP by the Lab Instructor.
8. The Practical Result should be noted down into their observations and result must be shown to
the Lecturer In-Charge for verification.
9. Students must ensure that all switches are in the OFF position, desktop is shut down properly.
DON’Ts:-
1. Don‟t come late to the Lab.
2. Don‟t leave the Lab without making proper shut down of desktop and keeping the chairs
properly.
3. Don‟t leave the Lab without verification by Lab instructor.
4. Don‟t leave the lab without the permission of the Lecturer In-Charge.
3
Vision of the Department
To emerge as a leading centre for students and faculty in their pursuits of professional excellence
in the fields of Electronics and Communication Engineering by making use of current Scientific
and Technological advancements, with focus on human values, professional ethics and social
responsibility.
Mission of the Department

Training students in the basic core and application oriented subjects of Electronics and
Communication engineering with due focus on multi-disciplinary areas.
Establishing liaison with relevant industries, R&D organizations and renowned academia for
exposure to practical R&D aspects of technology.
Inculcating team work, leadership, professional ethics and other skills such as effective
communication, logical reasoning, career goal setting, liberal use of modern tools, familiarity
with IPR to make students globally competent in employment as well as entrepreneurship.
Promoting scientific temper and research culture in the graduates towards lifelong learning to
produce useful research outcomes
PEO – I. To apply the knowledge of mathematics, science and engineering fundamentals to find the
solution of complex engineering problems concerning societal, health, safety, cultural and environmental
issues.
PEO – II. Empowering graduates to exhibit proficiency in core areas through evolving
technologies in electronics and communication engineering and to identify, analyze, design, and
conduct experiments for innovative solutions.
PEO – III. Facilitating graduates to achieve academic excellence and pursue R&D in multi-
disciplinary domains leading to design of novel products using modern tools and to promote skills
in project management, entrepreneurship and IPR.
PEO- IV. Developing human values, and professional ethics, improving the effective
communication skills, team work, leadership qualities, and life-long learning.
Attainment B. Tech (ECE) Programme Outcomes

Engineering Graduates will be able to:
1. Engineering knowledge: Apply the knowledge of mathematics, science,

engineering fundamentals, and an engineering specialization to the solution of
complex engineering problems.
2. Problem analysis: Identify, formulate, review research literature, and
analyze complex engineering problems reaching substantiated conclusions
4
using first principles of mathematics, natural sciences, and engineering
sciences.
3. Design/development of solutions: Design solutions for complex
engineering problems and design system components or processes that meet
the specified needs with appropriate consideration for the public health and
safety, and the cultural, societal, and environmental considerations.
4. Conduct investigations of complex problems: Use research-based
knowledge and research methods including design of experiments, analysis and
interpretation of data, and synthesis of the information to provide valid
conclusions.
5. Modern tool usage: Create, select, and apply appropriate techniques,
resources, and modern engineering and IT tools including prediction and
modeling to complex engineering activities with an understanding of the
limitations.
6. The engineer and society: Apply reasoning informed by the contextual
knowledge to assess societal, health, safety, legal and cultural issues and the
consequent responsibilities relevant to the professional engineering practice.
7. Environment and sustainability: Understand the impact of the
professional engineering solutions in societal and environmental contexts, and
demonstrate the knowledge of, and need for sustainable development.
8. Ethics: Apply ethical principles and commit to professional ethics and
responsibilities and norms of the engineering practice.
9. Individual and team work: Function effectively as an individual, and as a
member or leader in diverse teams, and in multidisciplinary settings.
10. Communication: Communicate effectively on complex engineering
activities with the engineering community and with society at large
11. Project management and finance: Demonstrate knowledge and
understanding of the engineering and management principles and apply these
to one’s own work
12. Life-long learning: Recognize the need for, and have the preparation and
ability to engage in independent and life-long learning in the broadest
context of technological change.
Expected level of Attainment of B. Tech (ECE) Program Specific Outcomes (PSOs)
PSO1: Should be able to gain the in-depth knowledge in core subjects to

identify, formulate, analyze, and suggest viable solutions to the real-life
problems in the field of electronics and communication engineering.
PSO2: Should have the capability to apply modern design tools to analyze and
design subsystems/processes for a variety of applications in the allied fields of
electronics and communications.
PSO3: Should possess good interpersonal skills, and also an ability to work as a
team member as well as team leader with good professional ethics, and also to
become a life-long learner in the context of technological developments.
5
Syllabus for B. Tech (E.C.E.) III Year I semester
Year/Sem Sub. Code Subject Name L T P/D C
III - I 7DC71 Microprocessors and Micro Controllers Lab - - 4 2
Course Objectives:
The objective of this course is to develop the Assembly language programming skills and real-
time applications of Microprocessor as well as microcontroller.
Course Outcomes: After studying this course, the students will be able to
CO1 Explore to write the Assembly Language Programs using Arithmetic instructions of
8086
CO2 Explore to write the Assembly Language Programs using String instructions of 8086
CO3 Explore to write the Assembly Language Programs for I/O interface with 8086
CO4 Explore to write the Assembly Language Programs using Arithmetic instructions of
8051
CO5 Explore to write the Assembly Language Programs using Timers and interrupts of
8051
Mapping of Course Outcomes with Program Outcomes

a b c d e f g h I j k l m
(PO (PO (PO (PO (PO (PO (PO (PO (PO (PO1 (PO1 (PO1 (PO1
1) 2) 3) 4) 5) 6) 7) 8) 9) 0) 0) 2) 3)
CO1 3 2 3
CO2 2 2 3 2 2
CO3 2 3 2
CO4 2 3
CO5 2 3
Over x X x
X x x x
all
Prerequisites: STLD,LDICA
Syllabus Content
Introduction to MASM/TASM, KIEL Assemblers
Familiarization with 8086, 8051 Kits
Cycle - I
8086 ALP using kit and MASM
1. Basic arithmetic and logical operations
2. Code conversion decimal arithmetic programs
3. String manipulation programs
4. Display a message on the screen of a computer using DOS / BIOS interrupts.
Cycle – II
7
Following peripherals and interfacing experiments to be implemented on 8086 and 8051
kits
1. A/D and D/A interfacing
2. Serial interfacing with PC
3. Keyboard and display interfacing
4. Stepper motor controller
Following simple programs may be given as lab assignment for students to executive at
home by using 8086 emulator like EMU86 or MASM.
Write ALP and execute the program to

1. Find square of a number
2. Exchange two numbers
3. Find average of a given series of numbers
4. Add a constant to a series of values in memory & store the result back in memory
5. Find sum of cubes of a given series of numbers
6. Display squares of a given series of numbers in memory
7. Find factorial of a given number
8. Find largest number from a given series of numbers
9. Sort a series of given numbers in ascending order
10. Find whether the given number is even or odd number
11. Find sum of all even no.s from a given series of even and odd numbers
12. Find GCD of two given numbers
13. Find LCM of two given numbers
14. Display Fibonacci series
15. Reverse a String
16. Programs based on DOS/BIOS interrupts
Programs on 8051
1. Arithmatic Operations
2. Timers
3. Interrupts
4. Serial communication
8
Course Objectives
 Familiarize the architecture of 8086 processor, assembling language

programming and interfacing with various modules.
 The student can also understand of 8051 Microcontroller concepts,
architecture, programming and application of Microcontrollers.
 Student able to do any type of VLSI, embedded systems, industrial and real
time applications by knowing the concepts of Microprocessor and
Microcontrollers.
Course Outcomes
 Analyze and apply working of 8086.

 Analyze and apply working of 8051
 Compare the various interface techniques. Analyze and apply the working of 8255, 8279,
8259, 8251, 8257 ICs and design and develop the programs.
 Learning the Communication Standards.
9
INDEX
1. INTRODUCTION TO MASM/TASM 11
2. INTRODUCTION TO ASSEMBLY LANGUAGE PROGRAMMING 13
Levels of programming
Program Development Tools
Assembler Directives
3. MICROPROCESSOR TRAINER KIT 18
4. PROGRAMMING MODEL OF 8086 27
5. PROGRAMMING IN 8086 MPU 31
1. BASIC ARITHMATIC OPERATIONS& ON KITS
2. ARRAY PROGRAMMING
3. BCD, DECIMAL,ASCII OPERATIONS
4. STRING MANIPULATION PROGRAMS
5. DOS AND BIOS INTERUPTS 63
6. INTERFACING 66
6.1 STEPPER MOTOR PROGRAMMING
6.2 INTERFACING DAC
6.2.1 TRIANGULAR WAVE GENERATION
6.2.2 SQUARE WAVE GENERATION
6.2.3 RAMP SIGNAL GENERATION
6.3 INTERFACE A KEYBOARD
6.4 INTERFACE SEVEN SEGMENT DISPLAY
6.8051 MICROCONTROLLER PROGRAMMING 74
6.5 INTERFCING OF 4X4 KEYPAD AND 7 SEGMENT DISPLAY
6.6 DECIMAL COUNTER DISPLAY ON 7 SEGMENT LED
6.7 8 BIT ADC INTERFACE
6.8 STEPPER MOTOR INTERFACING
6.9 DC MOTOR INTERFACING
10
Introduction to MASM
(Microsoft assembler) To Create Source File: An editor is a program which allows you to create
a file containing the assembly language statements for your program. This file is called a source
file.
Command to create a source file
C:\MASM\BIN> Edit filename. Asm Enter
The next step is to process the source file with an assembler. When you run the assembler, it
reads the source file of your program. On the first pass through the source program, the
assembler determines the displacement of named data items, the offset labels, etc. and puts this
information in a symbol table. On the second pass through the source program the assembler
produces the binary code for each instruction and inserts the offsets, etc. that it calculated during
first pass.
C:\MASM\BIN > Masm filename. asm X, Y, Z Enter
With this command assembler generates three files.

1. The first file (X) called the object file, is given the extension .OBJ
The object file contains the binary codes for the instructions and
information about the addresses of the instructions.
2. The second file (Y) generated by the assembler is called the assembler list file and is given the
extension .LST. The list file contains your assembly language statements, the binary codes for
each instruction and the offset for each instruction.
3. The third file (Z) generated by this assembler is called the cross-reference file and is given the
extension .CRF. The cross-reference file lists all labels and pertinent information required for
cross – referencing
NOTE : The Assembler only finds syntax errors : It will not tell you whether program does
what it is supposed to do.
To determine whether your program works, you have to run the program and test it.
Next step is to process the object file with linker.
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C:\MASM\BIN>LINK filename . obj Enter
Run File [ Filename1.exe] : “filename1.exe”

List file [ nul.map] : NUL
Libraries [.lib] : library_name
Definitions File [ nul.def] :
Creation of Library: Refer Modular Programming Section

A Linker is a program used to join several object files into one layer object file
NOTE : On IBM PC – type Computers, You must run the LINK program on your .OBJ file even
if it contains only one assembly module.
The linker produces a link file with the .EXE extension (an execution file)
Next Run C:\MASM\BIN> filename
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2.Assembly Language Programming
The assembler uses two basic formats for developing S/W
a) One method uses MODELS and

b) Other uses Full-Segment Definitions
* The models are easier to use for simple tasks.
* The full – segment definitions offer better control over the assembly language
task and are recommended for complex programs.
a) Format using Models:
; ABSTRACT ; 8086 program

; Aim of Program
; REGISTERS ; Registers used in your program
; PORTS ; PORTS used in your program
. MODEL (type of model i.e. size of memory system)
FOR EXAMPLE
. MODEL SMALL
.STACK size of stack; define stack
. DATA; define data segment
------
------Define variables
. CODE ; define code segment
HERE : MOV AX, @DATA ; load ES,DS
MOV ES, AX
MOV DS, AX
---------
---------
---------
. EXIT 0 ; exit to DOS
END HERE
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(or)
We can write Code segment as follows.
. CODE; Define Code Segment
. STARTUP
----------
----------
. EXIT 0
END
MEMORY MODELS FOR THE ASSEMBLER
LEVELS OF PROGRAMMING:
14
There are three levels of programming
1. Machine language
2. Assembler language
3. High level language
Machine language programs are programs that the computer can understand and execute directly.
Assembly language instructions match machine language instructions, but are written using
character strings so that they are more easily understood. and High-level language instructions
are much closer to the English language and are structured.
Ultimately, an assembly language or high level language program must be converted into
machine language by programs called translators.
If the program being translated is in assembly language, the translator is referred to as an
assembler, and if it is in a high level language the translator is referred to as a compiler or
interpreter.
ASSEMBLY LANGUAGE PROGRAM DEVELOPMENT TOOLS:
EDITOR: An editor is a program, which allows you to create a file containing the assembly
language statements for your program.
ASSEMBLER: An assembler program is used to translate the assembly language Mnemonic
instructions to the corresponding binary codes. The second file generated by assembler is called
the assembler List file.
LINKER: A Linker is a program used to join several object files in to one large object file. The
linkers produce link files with the .EXE extension.
DEBUGGER: If your program requires no external hardware, then you can use a debugger to
run and debug your program. A debugger is a program, which allows you to load your object
code program into system memory, execute the program, and troubleshoot or “debug” it.
ASSEMBLER DIRECTIVES:
An assembler is a program used to convert an assembly language program into the equivalent
machine code modules. The assembler decides the address of each label and substitutes the
15
values for each of the constants and variables. It then forms the machine code for mnemonics
and data in assembly language program.
Assembler directives help the assembler to correctly understand assembly language programs to
prepare the codes. Commonly used assembler directives are DB, DD, DW, DUP, ASSUME,
BYTE, SEGMENT, MACRO, PROC, OFFSET, NEAR, FAR, EQU, STRUC, PTR, END,
ENDM, ENDP etc. Some directives generate and store information in the memory, while others
do not.
DB :- Define byte directive stores bytes of data in memory.
BYTE PTR :- This directive indicates the size of data referenced by pointer.
SEGMENT :- This directive is to indicate the start of the segment.
DUP (Duplicate) :- The DUP directive reserves memory locations given by the number
preceding it, but stores no specific values in any of these locations.
ASSUME : - The ASSUME statement is only used with full segment definitions. This statement
tells the assembler what names have been chosen for the code, data, extra and stack segments.
EQU : - The equate directive equates a numeric ASCII or label to another label.
ORG : - The ORG (origin) statement changes the starting offset address in a segment.
PROC and ENDP : - The PROC and ENDP directives indicate start and end of a procedure
(Sub routine). Both the PROC and ENDP directives require a label to indicate the name of the
procedure. The PROC directive, must also be followed with the NEAR or FAR. A NEAR
procedure is one that resides in the same code segment as the program. A FAR procedure may
reside at any location in the memory system.
MACROS
A macro is a group of instructions that performs one task, just as a procedure. The difference is
that a procedure is accessed via a CALL instruction, while a macro is inserted in the program at
the point of usage as a new sequence of instructions.
MACRO : - The first statement of a macro is the MACRO directive preceded with name of the
macro.
ENDM : - The last statement of a macro is the ENDM instruction. Never place a label in front of
the ENDM statement.
16
PUBLIC &EXTRN : - The public and extern directives are very important to modular
programming. We use PUBLIC to declare that labels of code, data or entire segments are
available to other program modules. We use EXTRN to declare that labels are external to a
module. Without this statement, we could not link modules together to create a program using
modular programming techniques.
OFFSET : - Offset of a label. When the assembler comes across the OFFSEToperator along
with a label, it first computes the 16 – bit displacement of the particular label, and replaces the
string „OFFSET LABEL‟ by the computed displacement.
LENGTH : - Byte length of the label. This directive is used to refer to the length of data array or
a string.
17
3. MICROPROCESSOR TRAINER KIT
The microprocessor trainer kit (microprocessor development kit) is an aid to understand the
architecture, interfacing and programming of a microprocessor. Here we describe the ESA 86/88
– 2-trainer kit.
ESA 86/88-2 is a powerful, general-purpose microcomputer system, which can be operated
either with 8086 CPU or with 8088 CPU. The basic system can be easily expanded through the
system BUS connector. The built in Assembler/ Disassembler feature simplifies the
programmers task of entering Assembly language programs .The on-board provision for 8087
numeric data processor makes it useful for number crunching applications. On board battery
back up provision is an added feature to take care of frequent power failures while conducting
experiments of the trainer using manually assembled code.
It is also provided with peripherals and controllers such as
8251A: Programmable communication Interface for serial communication.

8253-5 : Programmable Interval Timer
8255A: Two Programmable Peripheral Interface Devices provide 48 programmable I/O lines
8259A: Programmable Interrupt Controller provides interrupt vectors for 8 sources.
8288: Bus Controller for generating control signals
ESA 86/88-2 is operated from the CRT terminals or a host computer system via the serial
monitor and also can be operated from the on board key board.
Working on 8086/88 Microprocessor kit:

Procedure to type a program:
1. Press RST button
2. Type „EB‟
3. Type 2000 after starting address and press next key
4. Enter opcode and press next key to go next address
5. Press RST after entering all the opcodes
Procedure to execute a program:

1. Press RST
2. GO and enter 2000 (starting address)
3. Press Exec ( displays as „-„ or „E‟)
Procedure to check the result:

1. Press RST
18
2. EB 2500 (address location given in program to see the result)
3. Press next key
4. Press next to Check the next address
in KIT:
ER : used for viewing the registers
EB : Show Byte
GO(Starting Address): used for executing the program
CONFIGURATION AND INSTALLATION
Configuration ESA 86/88-2
ESA 86/88-2-microcomputer trainer is versatile and can be configured in a number of ways, as

determined by the setting of a DIP switch and other jumpers. (Refer to the component layout
diagram in appendix C to locate the DIP switch and the jumpers). This chapter describes all the
configuration options and the installation procedures.
Operational mode selection
ESA 86/88-2 can be operated either in the serial mode or in Hexadecimal keypad mode. In the
serial mode, the trainer is connected to a CRT terminal or to a host computer system (like PC
compatible) through an RS 232 C interface. In the keypad mode, the trainer is operated through
Hexadecimal keypad.
SW4 of the DIP switch Operational mode
1. OFF Serial mode

2. ON Hexadecimal keypad mode*
(*Factory installed Option)
Printer Enable/Disable
ESA 86/88-2 firmware includes the driver program for centronics compatible parallel printer
interface. This driver can be enabled/disabled as shown below:
SW5 of the DIP Switch Printer Driver
1. OFF Disabled*
19
2. ON Enabled
(*Factory installed Option)
Baud rate selection
In the serial mode of operation, ESA 86/88-2 configures an 8251A USART as follows:
1. Asynchronous mode
2. 8-bit character length
3. 2 stop bits
4. No parity
5. Baud rate factor of 16X
Timers 0 of an 8253 provide the Transmit and receive baud clocks for the USART. (Refer to
chapter 5 for a detailed discussion of the Hardware).This timer is initialized by the system
firmware to provide proper baud clock based on the settings of the DIP Switch as shown below.
DIP SWITCH
1. SW3 SW2 SW1 Baud rate

OFF OFF ON 9,600*
2. Memory selection:
ESA 86/88-2 has four sockets, labeled U9, U8, U7, U6 for RAM. These sockets are configured
for 62256(32X 4) devices. Two of these sockets are populated (providing 64K Bytes of RAM)
and two are for user expansion.
DEVICE DIP SWITCH JUMPER
SW7 SW6
27256 ON OFF JP10 – 1-2
20
21
22
23
8255 INTERFACE FOR ESA 86-2 KIT :
On the Esa86-2 kit there are two 8255 Ics which can provide a full sixteen bit parallel interface
to the external peripherals they are divided into
1.even address ( jp4 ) RANGE FROM 0FFE0H to OFFE6H
Addresses for ports
PORT A - 00FFE0H
PORT B - 0FFE2H
PORT C - 0FFE4H
Control word register – 0FFE6H
2. Odd Address (Jp5) odd addresses in the range from 0FFE1H to OFFE7H
Addresses for ports
PORT A - 00FFE1H
PORT B - 0FFE3H
PORT C - 0FFE5H
Control word register – 0FFE7H
For accessing data from any port, we should provide 16 bit port address in DX. Data to be
output in register AL. so general format for port access is
Output to port:
Mov dx,0ffe6h ; port address
Mov al,50h ;data
Out dx,al
Input from port:
Mov dx,0ffe6h ; port address
In al, dx
8255 operational modes
8255 ports can be initialized in three different modes.

MODE 0: In this mode, all ports function as simple I/O ports without hand shaking.
MODE 1: This mode is handshake mode where by port A and port B use the bits Port C as
handshake signals.
24
MODE 2: Only port A can be initialized in mode 2.
In this mode port A can be used for Bidirectional handshake data transfer. Port B can be
initialized in mode 0 or mode1.
25
COMMUNICATION WITH A HOST COMPUTER SYSTEM
ESA 86/88-2 operating in the serial mode can be connected to either CRT terminal or host
computer system. When computer system is the controlling element it must be executing the
driver software to communicate with ESA 86/88-2.
WIN 862 is a package which allows the user to establish a communication link between ESA
86/88-2 system and a computer system. The link is established between asynchronous serial
ports of the computer and ESA 86/88-2.A suitable RS232-C cables have to be used for
connecting the kit to the computer system.
User can develop assembly language programs on the computer system, cross- assemble them
using a suitable cross assembler to generate object code files and then use WIN862 to download
these object code files into the trainer kit for execution.
Procedure for dumping the code via serial port for ESA-86-2 Kit
1. Assemble the .asm file using masm
2. Link .obj file to generate .exe file
3. Use exe2hex program to convert .exe file to .hex standard intel hex file.
3.1 when you run exe2hex, it will ask for file name- specify .exe file
3.2 next it prompts for segment address- mention as 0400 (equivalent to 0000:4000)
3.3 offset address give as 0000
3.4 it creates the corresponding hex file.
Before using the EXE2HEX program make sure that there is no filename.hex in the
directory corresponding to the .exe file which you want to convert.
4. On the kit make sure that switch 1-4 are ( on- off-off-off)
5. Now open Win862 software
5.1 port setting should be port1, baud rate -9600, data- 8bit, stop bit- 1, parity-none
5.2 it will open the window with various options
5.3 from file menu select download file: browse for corresponding hex file
5.4 after the hex file is succefully downloaded, open disassembly view
5.5 here mention the starting segment and offset address
5.6 You can execute the program through the disassembly.
Win 86-2 also provides you the facility of memory view, modify, single stepping etc
26
4.Programming model of 8086
ARCHITECTURE OF INTEL 8086
27
8086 Register Set
"General" Registers
AX AH (4) AL (0) 0 Accumulator
CX CH (5) CL (1) 1 Counter
DX DH (6) DL (2) 2 Data
BX BH (7) BL (3) 3 Base
SP 4 Stack Pointer
BP 5 Base Pointer
SI 6 Source Index
DI 7 Destination Index Memory Space
220-1
Segment Registers
ES 0 Extra Segment
CS 1 Code Segment
SS 2 Stack Segment
DS 3 Data Segment
Program Registers
IP Instruction Pointer
I/O Space
F Flags 16
2 -1
0
Addressing Modes of 8086
1. Immediate Addressing Mode
Immediate data is a part of instruction and appears in the form of successive byte
or bytes
Ex: MOV AX, 0005H
2. Direct Addressing Mode
it memory address (Offset) is directly specified in the instruction as a part of it
Ex: MOV AX,[5000H]
3. Register Addressing Mode
Data is stored in a register and it is referred using the particular register
28
Ex: MOV BX,AX
4. Register Indirect Addressing Mode
The offset address of data is in either BX or SI or DI register
Default segment is either DS or ES
EX: MOV AX,[BX]
5. Indexed Addressing Mode
Offset of the operand is stored in one of Index register
DS is default segment for index registers SI and DI
For Strings DS and ES are default segments for SI and DI
EX: MOV AX, [SI]
6. Register Relative Addressing Mode
Data is available at an effective address formed by adding an 8 bit or 16 bit
displacement with the content of any one of the registers BX,BP,SI and DI in
default segment
EX: AX,50H[BX]
7. Based Indexed Addressing Register
Effective address of data is formed by adding content of base register to content
of Index register
Default segment register may be ES or DS
EX: MOV AX,[BX][SI]
8. Relative Based Indexed
Effective address is formed by adding an 8 or 16 bit displacement with the sum of
contents of any one of base registers (BX or BP) and any one of Index registers in
a default segment
EX: MOV AX,50H [BX] [SI]
9. Intrasegment Direct Mode
Effective address to which the control is to be transferred is given by the sum of 8
or 16 bit displacement and current content of IP
EX: For JMP if signed displacement is 8 bits it is termed as short jump and if it
is 16 bits, it is termed as Long jump
10. Intrasegment Indirect Mode
29
The displacement to which the control is to be transferred, is in the same segment
in which the control transfer instruction lies, but it is passed to the instruction
indirectly used in Unconditional branch instructions
EX: JMP [BX];
11. Intersegment Direct Addressing Mode
Address to which the control is to be transferred is in a different segment
CS and IP of the destination address are specified directly in the instruction
EX: JPM 5000H : 2000H
12. Intersegment Indirect Addressing Mode
Address to which the control is to be transferred lies in a different segment and it
is passed to the instruction indirectly. Contents of memory block contains 4bytes
(IP(LSB), IP(MSB), CS(LSB), CS(MSB)) Starting address of the memory block
may be referred using any of the addressing modes except immediate mode
EX: JMP [2000H]
30
5.Intel 8086 MPU PROGRAMMING
USING DEBUG TO EXECUTE 80X86 PROGRAMS:
DEBUG is a utility program that allows a user to load an 80x 86 programs in to memory and
execute it step by step. DEBUG displays the contents of all processor registers after each
instruction executes, allowing user to determine if the code is performing the desired task.
DEBUG only displays the 16-bit portion of the general purpose registers. Code view is capable
of displaying the entire 32 bits. DEBUG is a very useful debugging tool. We will use DEBUG to
step through number of simple programs, gaining familiarity with DEBUG commands as we do.
DEBUG contains commands that can display and modify memory, assemble instructions,
disassemble code already placed into memory, trace through single or multiple instructions, load
registers with data, and do much more.
DEBUG loads into memory like any other program, in the fist available slot. The memory space
used by DEBUG for the user program begins after the end of DEBUG code. If an .EXE or. COM
file were specified, DEBUG would load the program according to the accepted conventions.
To execute the program file PROG.EXE use this command:
DEBUG PROG.EXE
DEBUG uses a minus as its command prompt, so you should see a “-”appear on display.
To get a list of some commands available with DEBUG is:
T trace (step by step execution)
U un assemble
D Dump
G go (complete execution)
H Hex
DEBUG- Testing and edition tool help ; MS-DOS based program.
MS-DOS prompt/debug [filename .exe/.com/others]
assemble A [address]
compare C range address
dump D [range]
enter E address [list]
fill F range list
31
go G [=address] [addresses]
hex H value1 value2
input I port
load L [address] [drive] [firstsector] [number]
move M range address
name N [pathname] [arglist]
output O port byte
proceed P [=address] [number]
quit Q
register R [register]
search S range list
trace T [=address] [value]
unassemble U [range]
write W [address] [drive] [firstsector] [number]
allocate expanded memory XA [#pages]
deallocate expanded memory XD [handle]
map expanded memory pages XM [Lpage] [Ppage] [handle]
display expanded memory status X
32
1. ARTHIMETIC OPERATIONS
1.1 8-BIT ADDITION

ASSUME DS: DATA, CS: CODE
DATA SEGMENT
NUM1 DB 03
NUM2 DB 08
RESULT DB 00
DATA ENDS
CODE SEGMENT
START:
MOV AX, DATA
MOV DS, AX
MOV AX, 00
MOV AL, NUM1
MOV BL, NUM2
ADD AL, BL
MOV RESULT, AL
INT 3
CODE ENDS
END START
RESULT: 03H
08H
0BH
33
1.2 16-BIT ADDITION
ASSUME CS: CODE, DS: DATA

DATA SEGMENT
NUM1 DW 0FFFFH
NUM2 DW 0FFFFH
RESULT DW 00
DATA ENDS
CODE SEGMENT
START:
MOV AX, DATA
MOV DS, AX
MOV AX, 00
MOV AX, NUM1
MOV BX, NUM2
ADD AX, BX
MOV RESULT, AX
INT 3
CODE ENDS
END START
RESULT: 0FFFFH 1111 1111 1111 1111 1111

0FFFFH 1111 1111 1111 1111 1111
1FFFEH 1,1111 1111 1111 1111 1110
CARRY
34
1.3 32 BIT ADDITION
ASSUME DS:DATA, CS:CODE

DATA SEGMENT
NUM1 DD 11223344H
NUM2 DD 44332211H
RES DD ?
DATA ENDS
CODE SEGEMENT
START:MOV AX,DATA
MOV DS, AX
MOV AX,WORDPTR (NUM1)
ADD AX,WORDPTR (NUM2)
MOV WORDPTR(RES), AX
MOV AX, WORDPTR(NUM1+2)
ADC AX, WORDPTR(NUM2+2)
MOV WORDPTR(RES+2), AX
INT 3H
CODE ENDS
END START
35
1.4 8-BIT SUBTRACTION
ASSUEM CS: CODE, DS:DATA
DATA SEGMENT
NUM1 DB 0FFH
NUM2 DB 0AAH
RESULT DB 00
DATA ENDS
CODE SEGMENT
START:
MOV AX, DATA
MOV DS, AX
MOV AX, 00
MOV AL, NUM1
MOV BL, NUM2
SUB AL, BL
MOV RESULT, AL
INT 3
CODE ENDS
END START
RESULT: 0FFH
0AAH
055H
1.5 16-BIT SUBTRACTION

ASSUME CS:CODE, DS: DATA
DATA SEGMENT
NUM1 DW 0FFFFH
NUM2 DW 0EABCH
RESULT DW 00
DATA ENDS
CODE SEGMENT
START:
MOV AX,DATA
MOV DS,AX
MOV AX,00
MOV AX,NUM1
MOV BX,NUM2
SUB AX,BX
MOV RESULT,AX
INT 3
CODE ENDS
END START
36
RESULT: 0FFFFH
0EABCH
01543H
1.6 32 BIT SUBTRACTIONS

ASSUME CS:CODE DS:DATA
DATA SEGMENT
NUM1 DD 44332211H
NUM2 DD 11223344H
RES DD ?
DATA ENDS
CODE SEGMENT
START:MOV AX,DATA
MOV DS,AX
MOV AX,WORDPTR (NUM1)
SUB AX,WORDPTR (NUM2)
MOV WORDPTR(RES),AX
MOV AX,WORDPTR (NUM1+2)
SBB AX,WORDPTR (NUM2+2)
MOV WORDPTR(RES+2),AX
INT 3H
CODE ENDS
END START
37
1.7 8-BIT MULTIPLICATION
DATA
NUM1 DB 0FFH
NUM2 DB 0AAH
RESULT DB 00
RESULT1 DB 00
DATA ENDS
CODE SEGMENT
START:
MOV AX,DATA
MOV DS, AX
MOV AX,00
MOV AL, NUM1
MOV BL, NUM2
MUL BL
MOV RESULT, AL
MOV RESULT1, AH
INT 3
CODE ENDS
END START
RESULT: 0FFH
0AAH
A956H
1.8 16-BIT MULTIPLICATION
ASSUME CS:CODE, DS:DATA
DATA
NUM1 DW 0FFFFH
NUM2 DW 0FFFFH
RESULT DW 00
RESULT1 DW 00
DATA ENDS
CODE SEGMENT
START:
MOV AX, DATA
MOV DS, AX
MOV AX, 00
MOV AX, NUM1
MOV BX, NUM2
MUL BX
MOV RESULT,AX
MOV RESULT1,DX
INT 3
CODE ENDS
38
END START
RESULT: 0FFFFH
0FFFFH
FFFE0001H
1.9 8-BIT DIVISION (16 Bit by 8 Bit)

.DATA
NUM1 DW 0FFH
NUM2 DB 0AAH
QUOTIENT DB 00
REMAINDER DB 00
DATA ENDS
CODE SEGMENT
START: MOV AX,DATA
MOV DS,AX
MOV AX,00
MOV DX,00
MOV AX,NUM1
MOV BL,NUM2
DIV BL
MOV QUOTIENT,AL
MOV REMAINDER,AH
INT 3
CODE ENDS
END START
RESULT: 0FFH
0AAH
5501H QUOTIENT: 01H
REMAINDER R: 55H
1.10 16-BIT DIVISION (32 Bit by 16 Bit)

DATA SEGMENT
NUM1 DW 0FFFFH
NUM2 DW 0AAAAH
QUOTIENT DW 00
REMAINDER DW 00
DATA ENDS
CODE SEGEMENT
START: MOV AX,DATA
MOV DS,AX
MOV AX,00
MOV DX,00
39
MOV AX,NUM1
MOV BX,NUM2
DIV BX
MOV QUOTIENT,AX
MOV REMAINDER,DX
INT 3
CODE ENDS
END START
RESULT: 0FFFFH
0AAAAH
55550001H QUOTIENT: 0001H
REMAINDER: 5555
1.11 Find Square of a number

DATA SEGMENT
NUM1 DB 0FFH
RESULT DW 00
DATA ENDS
CODE SEGMENT
START:MOV AX,DATA
MOV DS,AX
MOV AX,00
MOV AL,NUM1
MUL NUM1
MOV RESULT,AX
INT 3
CODE ENDS
END START
40
1.12 Exchange two numbers

DATA SEGMENT
NUM1 DB 0FH
NUM2 DB 05H
DATA ENDS
CODE SEGMENT
START: MOV AX,DATA
MOV DS,AX
MOV AL,NUM1
MOV BL,NUM2
MOV NUM1,BL
MOV NUM2,AL
INT 3
CODE ENDS
ENDS START
41
1.13 SIGNED MULTIPLICATION
DATA SEGMENT
DP1 DB 0A5H
DP2 DB 20H
RES DW 00H
DATA ENDS
CODE SEGMENT
ASSUME CS:CODE,DS:DATA
START: MOV AX,DATA
MOV DS,AX
SUB AX,AX
MOV AL,DP1
MOV BL,DP2
IMUL BL
MOV RES,AX
NOP
INT 3H
CODE ENDS
END START
42
1.14. SIGNED DIVISION
DATA SEGMENT
DP1 DB 0D5H
DP2 DB 20H
QUO DB 0H
REM DB 0H
DATA ENDS
CODE SEGMENT
START: MOV AX,DATA
MOV DS,AX
XOR AX,AX
MOV AL,DP1
CBW
MOV BL,DP2
IDIV BL
MOV QUO,AL
MOV REM,AH
NOP
INT 3H
CODE ENDS
END START
43
2. ARRAY PROGRAMMING
2.1 FACTORIAL OF A GIVEN NUMBER
DATA SEGMENT
ARR1 DW 1
ARR2 DW 5
DATA ENDS
CODE SEGMENT
START:
MOV AX,DATA
MOV DS,AX
MOV AX,ARR1
MOV BX,ARR2
FACT: MUL BX
DEC BX
JNZ FACT
INT 3H
CODE ENDS
END START
2.2 DISPLAY OF SQUARES OF N. NUMBERS
DATA SEGMENT
DATA DB 01H,02H,03H,04H,05H
COUNT DW 0005H
SQDATA DW 05H DUP(?)
DATA ENDS
CODE SEGMENT
START: MOV AX,DATA
MOV DS,AX
MOV ES,AX
MOV SI,OFFSET DATA
MOV DI,OFFSET SQDATA
MOV AX,0H
MOV CX,COUNT
L1: MOV AL,[SI]
MUL [SI]
MOV [DI],AX
INC SI
44
INC DI
LOOP L1
INT 3H
CODE ENDS
END START
2.3 SORTING IN ASCENDING ORDER

;REGISTERS:AX,BX,CX,DX,SI,DI,ES,DS
;PROCEDURE:NONE
;PORT:NONE
DATA SEGMENT
ARR DB 99H,88H,77H,66H,55H,44H
COUNT DW 0006H
DATA ENDS
CODE SEGMENT
ASSUME CS:CODE,DS:DATA,ES:DATA
START:MOV AX,DATA ;STARTING ADDRESS OF DATA SEGMENT

MOV DS,AX
MOV ES,AX ;STARTING ADDRESS OF EXTRA SEGMENT
MOV DX,COUNT ;NO OF ELEMENT IN AN ARRAYS=6
DEC DX
NXTITER:MOV CX,DX ;NO OF COMPARISION=5
MOV SI,0
NXTCMP: MOV AL,ARR[SI]

CMP AL,ARR[SI+1] ;COMPARE TWO ELEMENTS
JC NOSWAP ;CARRY=SET INDICATES 1ST ELEMENT IS SMALLEST
XCHG AL,ARR[SI+1] ;SWAPPING OF 2 ELEMENTS
MOV ARR[SI],AL
NOSWAP: INC SI ;GO COMPARE FOR 2 AND 3 ELEMENT
LOOP NXTCMP
DEC DX ;GO FOR NEXT SMALLEST ELEMENT
JNZ NXTITER
INT 3H ;BREAK AND DISPLAY
CODE ENDS
END START
45
2.4 SORTING IN DESCENDING ORDER
;PROCEDURE:NONE
;PORT:NONE
DATA SEGMENT
ARR DW 1111H,2222H,3333H,4444H,5555H,6666H
COUNT DW 0006H
DATA ENDS
CODE SEGMENT
START:MOV AX,DATA ;STARTING ADDRESS OF DATA SEGMENT

MOV DS,AX
MOV DX,COUNT ;NO OF ELEMENT IN AN ARRAYS=6
DEC DX
NXTITER:MOV CX,DX ;NO OF COMPARISION=5
MOV SI,0
NXTCMP:MOV AX,ARR[SI]
CMP AX,ARR[SI+2] ;COMPARE TWO ELEMENTS
JNC NOSWAP ;CARRY=CLEAR INDICATES 1ST ELEMENT IS LARGE
XCHG AX,ARR[SI+2] ;SWAPPING OF 2 ELEMENTS
XCHG AX,ARR[SI+2]
MOV ARR[SI],AX
NOSWAP:INC SI
INC SI ;GO COMPARE FOR 2 AND 3 ELEMENT
LOOP NXTCMP
DEC DX ;GO FOR NEXT SMALLEST ELEMENT
JNZ NXTITER
INT 3H ;BREAK AND DISPLAY
CODE ENDS
END START
2.5 SQUARE ROOT OF A GIVEN NUMBER
DATA SEGMENT
NUM DB 25
RESULT DB (?)
DATA ENDS
46
CODE SEGMENT
START:
MOV AX,DATA
MOV DS,AX
MOV CL,NUM
MOV BL,01
MOV AL,00
UP: CMP CL,00
JZ ZRESULT
SUB CL,BL
INC AL
ADD BL,02
JMP UP
ZRESULT: MOV RESULT,AL
INT 03H
CODE ENDS
END START
47
2.6 AVERAGE OF GIVEN NUMBERS
DATA SEGMENT
VALUES DW 03H,08H,05H,08H
N DW 04H
RES DW (?)
DATA ENDS
CODE SEGMENT
START: MOV AX,DATA
MOV DS,AX
MOV CX,N
MOV AX,0
MOV BX,N
AVG:ADD AX, VALUES[SI]
INC SI
INC SI
LOOP AVG
DIV BX
MOV RES,AX
INT 3H
CODE ENDS
48
2.7 FIND LCM AND GCD OF TWO NUMBERS.
2.8 FIBONACCI SERIES
ASSUME DS:DATA,CS:CODE
DATA SEGMENT
FBS DB 10 DUP(?)
DATA ENDS
CODE SEGMENT
MOV AX,DATA
MOV DS,AX
MOV SI,OFFSET FBS
MOV CL,08H
MOV AL,00H
MOV BL,01H
MOV [SI],AL
INC SI
MOV [SI],BL
L1:INC SI
ADD AL,BL
MOV [SI],AL
MOV BL,[SI-1]
LOOP L1
INT 3H
CODE ENDS
END START
3. BCD, DECIMAL,ASCII OPERATIONS

3.1 BCD ADDITION
ASSUME CS:CODE, DS: DATA
DATA SEGMENT
NUM1 DB 03
49
NUM2 DB 08
RESULT DB 00
DATA ENDS
CODE SEGMENT
START:MOV AX,DATA
MOV DS,AX
MOV AX,00
MOV AL,NUM1
MOV BL,NUM2
ADD AL,BL
DAA
MOV RESULT,AL
INT 3
CODE ENDS
END START
3.2 BCD Subtraction

ASSUME CS: CODE, DS:DATA
DATA SEGMENT
NUM1 DB 08
NUM2 DB 03
RESULT DB 00
DATA ENDS
CODE SEGMENT
START:
MOV AX,DATA
MOV DS,AX
MOV AX,00
MOV AL,NUM1
MOV BL,NUM2
SUB AL,BL
50
DAS
MOV RESULT,AL
INT 3
CODE ENDS
END START
3.3 BCD TO ASCII CONVERSION

.MODEL TINY
.STACK 32H
.CODE
MOV AX,@DATA
MOV DS,AX
MOV AX,00
MOV AL,BCD
AND AL,0FH
MOV BL,AL
MOV AL,BCD
AND AL,0F0H
MOV CL,04H
SHL AX,CL
ADD AL,BL
ADD AX, 3030H
MOV ASCII,AX
INT 3
.DATA
BCD DB 44H
ASCII DW ?
END
51
3.4 TWO DIGIT ASCII TO BCD CONVERSION
.MODEL TINY
.STACK 32H
.CODE
MOV AX,CS
MOV DS,AX
MOV AX,ASCII
SUB AX,3030H
MOV BL,AL
MOV CL,04H
SHR AX,CL
ADD AL,BL
MOV BCD,AL
INT 3
.DATA
BCD DB ?
Ascii DW 3436H
END
3.5 FOUR DIGIT DECIMAL TO BINARY CONVERSION

.MODEL TINY
.STACK 32H
.CODE
MOV AX,@DATA
MOV DS,AX
MOV SI,OFFSET BINARY
MOV AX,DECIMAL
AND AX, 0F000H
MOV CL, 04H
ROL AX, CL
MOV BX, 1000
52
MUL AX, BX
MOV [SI], DX
ADD [SI], AX
MOV AX, DECIMAL
AND 0F00H
MOV AL, AH
MOV BL, 100
MUL BL
ADD [SI], AX
MOV AX, DECIMAL
AND AX, 00F0H
ROR AL, CL
MOV BL, 10
MUL BL
ADD [SI], AX
MOV AX,DECIMAL
AND AX,000FH
ADD[SI], AX
INT 3
.DATA
DECIMAL DW 1234H
BINARY DW ?
END
53
3.6 FOUR DIGIT DECIMAL TO BINARY CONVERSION
.MODEL TINY
.STACK 32H
.CODE
MOV AX,@DATA
MOV DS,AX
MOV SI,OFFSET DECIMAL
MOV AX,HEX
MOV DX,0000
MOV BX,1000
DIV BX
MOV CL, 04H
ROR AX, CL
MOV [SI],AX
MOV AX,DX
MOV DX,0000
MOV BL,100
DIV BL
MOV BH,AH
MOV AH,AL
MOV AL,00
ADD [SI].AX
MOV AL,BH
MOV AH,00
MOV BL,10
DIV BL
MOV BH,AH
SHL AL,CL
MOV AH,00
ADD [SI].AX
MOV AL,BH
54
ADD[SI],AX
INT 3
.DATA
HEX DW 04D2H
DECIMAL DW ?
END
4. STRING AND ARRAY OPERATIONS

4.1 MOVE A BLOCK OF STRING(NON OVERLAPPING )
;BY USING STRING OPERATION AND INSTRUCTION PREFIX

;PROCEDURE:NONE
;PORT:NONE
DATA SEGMENT
STRINGA DB 'MICROPROCESSOR'
STRINGB DB 25 DUP(0)
DATA ENDS
CODE SEGMENT
ASSUME CS:CODE, DS:DATA,ES:DATA
START:MOV AX,DATA
MOV DS,AX
MOV ES,AX
MOV BX,0000H
MOV CX,14
LEA SI,STRINGA ;STARTING ADDRESS OF STRING-A
LEA DI,STRINGB ;STARTING ADDRESS OF STRING-B
CLD
55
REP MOVSB
INT 3H
CODE ENDS
END START
4.2 MOVE A BLOCK OF STRING (OVERLAPPING )
;BY USING STRING OPERATION AND INSTRUCTION PREFIX

;PROCEDURE:NONE
;PORT:NONE
DATA SEGMENT
DATA ENDS
CODE SEGMENT
ASSUME CS:CODE, DS:DATA,ES:DATA
START:MOV AX,DATA
MOV DS,AX
MOV ES,AX
MOV BX,0000H
MOV CX,14
LEA SI,STRINGA ;STARTING ADDRESS OF STRING-A
MOV AX,SI
ADD AX,CX
MOV SI,AX
ADD AX,05H
MOV DI,AX ;STARTING ADDRESS OF STRING-B
STD
REP MOVSB
56
INT 3H
CODE ENDS
END START
4.3 Check whether string is palindrome
data segment
str db 'madan'
stre db 5 dup(0)
res db 4 dup(0)
data ends
code segment
assume cs:code,ds:data,es:data
start: mov ax,data
mov ds,ax
mov es,ax
mov ax,0
mov bx,0
lea si,str
lea di,stre
mov cx,0005h
add di,cx
dec di
l1: mov al,[si]
mov [di],al
inc si
dec di
loop l1
cld
mov cx,0005h
mov si,offset str
mov di,offset stre
57
repe cmpsb
jz l2
mov si, offset res
mov byte ptr [si],'n'
inc si
mov byte ptr[si],'o'
int 3h
l2: mov si,offset res
mov byte ptr[si],'y'
inc si
mov byte ptr[si],'e'
inc si
mov byte ptr[si],'s'
int 3h
code ends
end start
4.4 REVERSE OF A STRING
;PROCEDURE:NONE
;PORT:NONE
DATA SEGMENT
DATA ENDS
CODE SEGMENT
START: MOV AX,DATA
MOV DS,AX
MOV ES,AX
58
MOV BX,0000H
MOV CX,14
LEA SI,STRINGA
LEA DI,STRINGB+13
GOBACK: MOV AL,[SI]
MOV [DI],AL
INC SI
DEC DI
LOOP GOBACK
INT 03H
CODE ENDS
END START
4.5. FINDING THE LENGTH OF STRING
;REGISTERS:AX,SI,CX,DS,ES
;PROCEDURE:NONE
DATA SEGMENT
STRING DB 'MICROPROCESSOR',0
LEN DW ?
DATA ENDS
CODE SEGMENT
START: MOV AX,DATA ;STARTING ADDRESS OF DATA SEGMENT
MOV DS,AX
MOV AX,0000H ; SEARCH SPACE
MOV CX,256
LEA DI,STRING
CLD ; INCREMENT SI/DI
REPNE SCASB ; CMP AL,[DI]
59
JZ FOUND
MOV BX,5555H ; BX=5555H INDICATES NOT FOUND
MOV AX,4C00H
INT 21H
FOUND: DEC DI
MOV LEN,DI ; BX=9999H INDICATES FOUND
MOV BX,9999H ; LEN=DI =STRING LENGTH
MOV AX,4C00H ; EXIT TO DOS INTERRUPT
INT 03H
CODE ENDS
END START ; IGNORE NEXT INSTRUCTION
4.6. COMPARE TWO STRINGS
;PROCEDURE:NONE
;PORT:NONE
DATA SEGMENT
STRINGB DB 'MICROPROCESSOR',0
STRINGA DB 'MICROPROCESSOR',0
ACTLEN DW 000EH
DATA ENDS
CODE SEGMENT
START: MOV AX,DATA
MOV DS,AX
MOV ES,AX
MOV CX,256
LEA SI,STRINGA
60
LEA DI,STRINGB
MOV AL,00H
REPNE SCASB
DEC DI
MOV BX,DI
CMP ACTLEN,BX
JZ CMP2STR
MOV DX,2222H
INT 3H
CMP2STR: LEA SI,STRINGA
LEA DI,STRINGB
MOV CX,ACTLEN
CLD
REPE CMPSB
JNZ NOTMATCH
MOV DX,9999H
INT 3H
NOTMATCH: MOV AX,0000H

INT 3H
CODE ENDS
END START
61
4.7. FINDING THE LENGTH OF STRING
;REGISTERS:AX,SI,CX,DS,ES
;PROCEDURE:NONE
DATA SEGMENT
STRING DB 'MICROPROCESSOR',0
LEN DW ?
DATA ENDS
CODE SEGMENT
START: MOV AX,DATA ;STARTING ADDRESS OF DATA SEGMENT

MOV DS,AX
MOV AX,0000H ; SEARCH SPACE
MOV CX,256
LEA DI,STRING
CLD ; INCREMENT SI/DI
REPNE SCASB ; CMP AL,[DI]
JZ FOUND
MOV BX,5555H ; BX=5555H INDICATES NOT FOUND
MOV AX,4C00H
INT 21H
FOUND: DEC DI
MOV LEN,DI ; BX=9999H INDICATES FOUND
MOV BX,9999H ; LEN=DI =STRING LENGTH
MOV AX,4C00H ; EXIT TO DOS INTERRUPT
INT 03H
CODE ENDS
END START ; IGNORE NEXT INSTRUCTION
62
5 DOS AND BIOS PROGRAMMING
5.1 ALP TO DISPLAY THE GIVEN TWO STRINGS
;PROCEDURE:NONE
;PORT:NONE
DATA SEGMENT
MESSAGE1 DB 0AH,0DH,'THIS IS ECM DEPARTMENT',0AH,0DH, "$"
MESSAGE2 DB 0AH,0DH, 'SNIST', 0AH,0DH,"$"
DATA ENDS
CODE SEGMENT
ASSUME DS:DATA,CS:CODE
START:
MOV AX,DATA
MOV DS,AX
MOV DX,OFFSET MESSAGE1
MOV AH,09H
INT 21H
MOV DX,OFFSET MESSAGE2
MOV AH,09H
INT 21H
INT 3H
CODE ENDS
END START
63
5.2. ALP TO DISPLAY THE STRINGS MATCHING OR NOT
DATA SEGMENT
STRINGA DB 'MICROPROCESSOR',0,0,0
STRINGB DB 'MICROPROCESSOR'
ACTLEN DW 000EH
MESSAGE1 DB 0AH,0DH,"STRINGS ARE MATCHING",0AH,0DH,"$"
MESSAGE2 DB 0AH,0DH,"STRINGS ARE NOT MATCHING",0AH,0DH,"$"
DATA ENDS
CODE SEGMENT
START: MOV AX,DATA
MOV DS,AX
MOV ES,AX
LEA SI,STRINGA
LEA DI,STRINGB
MOV CX,ACTLEN
CLD
REPE CMPSB
JNZ NOTMATCH
MATCH: MOV DX,OFFSET MESSAGE1
MOV AH,09h
INT 21H
INT 3H
NOTMATCH: MOV DX,OFFSET MESSAGE2
MOV AH,09H
INT 21H
INT 3H
CODE ENDS
END START
64
5.3 ALP TO DISPLAY THE REVERSE OF A STRING
;PORT:NONE
DATA SEGMENT
STRINGA DB 'MICROPROCESSOR',0,0
STRINGB DB 0AH,0DH,"$",'50 DUP(0)',0AH,0DH,"$"
DATA ENDS
CODE SEGMENT
ASSUME CS:CODE, DS:DATA, ES:DATA
START: MOV AX,DATA
MOV DS,AX
MOV ES,AX
MOV BX,0000H
MOV CX,14
LEA SI,STRINGA
LEA DI,STRINGB+13
GOBACK: MOV AL,[SI]
MOV [DI],AL
INC SI
DEC DI
LOOP GOBACK
JZ AHEAD
MOV DX,SI
MOV AH,09
INT 21H
AHEAD: MOV DX,DI
MOV AH,09
INT 21H
INT 3H
CODE ENDS
END START
65
6 INTERFACING WITH 8255
6.1 STEPPER MOTOR INTERFACING
Aim : To interface the stepper motor and rotate it using microprocessor

Circuit description:
The stepper motor interface uses four transistor pairs (SL 100 and 2N3055) darlington
pair configuration. Each configuration pair is used to excite the particular winding of the motor
connected to 4 pin connector on the interface. The inputs to these transistors are from the 8255
PPI I/O lines of trainer kit. The free wheeling diode across each winding protects transistor from
switching transients. Port pins pa0-pa3 are connected to stepper motor windings through driver
circuit.
.MODEL SMALL
.STACK 20H
.CODE
ORG 2000H
MOV AL,80H ;INITIALIZE 8255
MOV DX,0FFE7H ;ALL PORTS ARE OUTPUT
OUT DX,AL ; 0FFE7H INDICATES ADDRESS OF CWR
MOV AL,88H ; PA3-PA0 ARE CONNECTED TO 4 FIELD
GO:MOV DX,0FFE1H ; 0FFE1H INDICATE PORT A ADDRESS
OUT DX,AL ; 1=ON AND 0=OFF
CALL DELAY ; DELAY BETWEEN FIELDS
ROR AL,1
JNZ GO ; ROTATE CONTINOUSLY
INT 3H
DELAY:MOV CX,0FFFH
L1:NOP
LOOP L1
RET
END
6.2DAC INTERFACING
Aim : To interface the 8 bit DAC to microprocessor using 8255
Circuit description:
66
The dual dac interface kit accepts 8 bit inputs from port A and port B of 8255 to two DAC ICs which will give use
differential analog output across analog o/p two DACS. For using this kit we need to connect 26 pin FRC connector
from JP4 of 8086 kit to the Dual DAC kit and connect separate supply for the interface kit. Output can be observed
on CRO
EX1: SQUARE WAVE GENRATION USING DAC

;8086 MICROPROCESSOR
;INTERFACING TO 8086 WITH DAC INTERFACE
;PORT: PORTA USED ASOUTPUT
CODE SEGMENT
ORG 2000H
ASSUME CS:CODE
MOV AL,80H ;INTIALIZE 8255PPI
MOV DX,0FFE6H ;PORTA,PORTB,PORTC ARE OUTPUT
OUT DX,AL ;0FFE6H CONTAINS CWR OF 8255
REPEAT: MOV AL,00H
GOB: MOV DX,0FFE0H ;0FFE0H INDICATES PORT A
OUT DX,AL
CALL DELAY
MOV AL,00H
OUT DX,AL
CALL DELAY
JMP REPEAT
INT 3H
DELAY PROC NEAR
MOV CX,0FFFFH
L1: NOP
LOOP L1
RET
DELAY ENDP
CODE ENDS
END
EX2: RAMP WAVE GENRATION USING DAC
67
CODE SEGMENT
ORG 2000H
ASSUME CS:CODE
MOV DX,0FFE0H ;0FFE0H INDICATES PORT
MOV AL,00H
REPEAT: OUT DX,AL
CALL DELAY
INC AL
JMP REPEAT
INT 3H
DELAY PROC NEAR
MOV CX,01FFH
L1: NOP
LOOP L1
RET
DELAY ENDP
CODE ENDS
END
EX3: TRIANGULAR WAVE GENRATION USING DAC
68
CODE SEGMENT
ORG 4000H
ASSUME CS:CODE
MOV DX,0FFE0H ;0FFE0H INDICATES PORT
MOV AL,00H
REPEAT: OUT DX,AL
CALL DELAY
INC AL
CJNE AL,0FFH, REPEAT
REPEAT1: DEC AL
OUT DX,AL
CALL DELAY
CJNE AL,00H, REPEAT1
JMP REPEAT
INT 3H
DELAY PROC NEAR
MOV CX,01FFH
L1: NOP
LOOP L1
RET
DELAY ENDP
CODE ENDS
END
69
6.3 Interfacing matrix keyboard with 8086
; KEYBOARD INTERFACE
; Assumes the interface is connected over J4 of trainer
; This program displays the value of the pressed key LCD
; This program starts at 0:2000H location
.MODEL SMALL
.STACK 32
.DATA
FNPTR DD 0FF000B0AH
.CODE
MOV AX,@DATA
MOV ES,AX
MOV DS,AX
MOV DX,0FFE6H ; CONFIGURE 8255 IN MODE0
MOV AL,92H ; PORTA AS I/P , PORTC AS O/P
OUT DX,AL
KBDM: CALL KSCAN
MOV AH,00H
MOV SI, OFFSET FNPTR
CALL DWORD PTR[SI]
CALL DELAY
JMP SHORT KBDM
INT 3H
KSCAN PROC NEAR
KS: MOV CL,01H
NEXT: MOV AL,CL
MOV DX,0FFE4H
OUT DX,AL
MOV DX,0FFE0H
IN AL,DX
MOV AH,AL
OR AL,AL
JNZ KEYCODE
CONT: ROL CL,1
CMP CL,08H
JE KS
JMP NEXT
KEYCODE:MOV BL,0H
MOV AL,AH
SHIFT: SHR AL,1
CMP AL,00H
JZ ROW
INC BL
JMP SHIFT
70
ROW: MOV AL,CL
MOV CL,02H
ROL AL,CL
AND AL,0FBH
OR AL,BL
RET
KSCAN ENDP
DELAY PROC NEAR
PUSH CX
MOV CX,0000H ; DELAY ROUTINE
DLY: NOP
LOOP DLY
POP CX
RET
DELAY ENDP
END
6.4 SEVEN SEGMENT LED INTERFACING
; Demonstration program for Seven segment Display interface for

; ESA 86/88-2 Trainer.The program assumes that the interface is
; connected over FRC connector J4 of the trainer. This program
; module displays „0 TO F‟ in group of four each on the interface LEDs with
; specific delay.
; The program can be executed in Stand Alone MODE or Serial mode.
; Execute the program from memory location 0:4000H
.MODEL SMALL
.STACK 32
.CODE
MOV AX,CS ;INITIALISE SEGMENT REG.
MOV DS,AX
MOV DX,0FFE6H ;CONFIGURE ALL 8255 PORTS
MOV AL,80H ;AS OUTPUT.
OUT DX,AL
71
LOOP4: MOV SI,0080H ;INITIALISE POINTER
MOV CL,05H ;SET COUNTER FOR 5 GROUPS.
LOOP3: MOV CH,04H ;4 CHARECTERS/GROUP
LOOP2: MOV BL,08H ;8 SEGMENTS/CHARECTER
MOV AL,[SI] ;GET THE DISPLAY CODE
INC SI ;INCREMENT POINTER
LOOP1: ROL AL,1
MOV DX,0FFE2H
OUT DX,AL
MOV AH,AL
MOV AL,01H
MOV DX,0FFE4H
OUT DX,AL
DEC AL
OUT DX,AL
MOV AL,AH
DEC BL
JNZ LOOP1
DEC CH
JNZ LOOP2
CALL DELAY
DEC CL
JNZ LOOP3
JMP SHORT LOOP4
DELAY: PUSH CX
MOV CX,0
L1: LOOP L1
L2: LOOP L2
L3:LOOP L3
POP CX
RET
72
ORG 0080H
STRING: DB 0FFH,0FFH,0FFH,0FFH
DB 0C0H,0F9H,0A4H,0B0H
DB 099H,092H,082H,0F8H
DB 080H,090H,088H,083H
DB 0C6H,0A1H,086H,08EH
END
73
7 Microcontrollers Programming
The ALS-EMB-EVAL-03 is a comprehensive aid to understand the capabilities of

advanced 8051 compatible Atmel 89C51ED2
Its features are
On-chip 64KB flash program memory

On-chip 1792 bytes XRAM
On-chip 2048 bytes EPROM
On-chip spi interface
Capabilities of the kit are
1. Operation at 11.0592MHz
2. All port are terminated at individual four 10pin FRC headers to interface various
onboard circuits
3. RS232 compatible serial interface for communication and ISP
4. Alphanumeric 16X2 LCD display
5. Six digit 7 segment LED display interface
6. 4x4 matrix keypad
7. 8 bit SAR ADC and temperature sensor interface
8. 8 bit DAC interface using I2C and without I2C interface
9. SPI interface to 12 bit ADC
10. Three level elevator simulator interface
11. On board stepper motor and DC motor interface
12. Solid state relay and buzzer interface
13. RF transmitter and receiver interface
14. IR receiver with remote control
15. 8 pin DIP switch interface
16. Variable PWM and frequency generator using dual timers
17. RS484/422 interface
74
Block diagram of 8051
Special function registers

NAME ADDRESS FUNCTION BIT
(HEX) ADDRESSABLE
A E0 Accumulator Y
B F0 Math register Y
DPH,DPL 83,82 Address pointer N
IE,IP A8,B8 Interrupt control Y
P0-P3 80,90,A0,B0 General purpose Y
ports
PC - Program counter N
PCON 87 Power control and N
Misc
PSW D0 Program status Y
SCON,SBUF 98,99 Serial port control Y,N
SP 81 Stack pointer N
TCON,TMOD 88,89 Timer control Y,N
THO,TLO 8C,8A Timer 0 N
TH1-TL1 8D,8B Timer 1 N
75
Timer operation:
8051 has two 8 bit timers T0 and T1. Their mode is selected by SFR TMOD its format
is given below
TMOD REGISTER FORMAT
D7 D0
-- -
Gate C/T M1 M0 Gate C/T M1 M0
<-------------------- Timer 1------------> <-------------------- Timer 0 ------------>
 MODES OF OPERATION
M1 M0 MODE
0 0 13 BIT Timer
0 1 16 BIT Timer
1 0 8 BIT Auto Reload
1 1 2 separate 8 BIT
Timers
 INPUT TO TIMER: Fosc/12

 INPUT TO COUNTER
o Pin T0 for counter 0
o Pin T1 for counter 1
 OVERFLOW FLAGS
o TF0
o TF1
 TCON REGISTER FORMAT
D7 D0
TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0
o TF1 & TR1 (Timer 1 flag and Run control)

o TF0 & TR0 (Timer 0 flag and Run control)
o IE1,IT1,IE0 & IT0 (Interrupt Control)
SERIAL PORT OF 8051
76
 SCON REGISTER FORMAT
D7 D0
SM0 SM1 SM2 REN TB8 RB8 TI RI
o SMO & SM1 (Modes of Operation)

o SM2 controls microprocessor to microprocessor communication
o REN (receive enable)
o TB8 (Transmit bit 8)
o RB8 (Received bit 8)
o TI (transmit flag)
o RI (Received Flag)
MODES OF OPERATION
SM1 SM0 MODE OPERATION

0 0 0 Shift register, baud rate = f/12
0 1 1 8 BIT UART, baud rate programmable
1 0 2 9 BIT UART, baud rate = f/32, f/64
1 0 3 9 BIT UART, baud rate programmable
 BAUD frequency = 2SMOD * Oscillator frequency/(256-TH1)(12*32)

o SMOD is bit 7 of PCON register
INTERRUPT STRUCTURE OF 8051

There are 5 INTERRUPTS in 8051
i. Timer Interrupts (TF0 & TF1)
ii. External Interrupts (INT 0 & INT1)
iii. Serial port Interrupt
RESET considered as 6th interrupt
RESPONSE TO INTERRUPT
o Complete current instruction
o Save PC on stack
o Save interrupt status
o Jump to fixed ISR address
o Execute ISR
o Return on RETI instruction, restore status
77
INTERRUPT VECTOR ADDRESS
INTERRUPT VECTOR ADDRESS (HEX)

RESET 0000
INT 0 0003
TF0 000B
INT 1 0013
TF1 001B
SERIAL PORT 0023
INTERRUPT ENABLE REGISTER FORMAT

D7
D0
EA - ET2 ES ET1 EX1 ET0 EX0
o EA (Enable All)
o ET2 (Timer 2 enable, in 8052 only)
o ES (Serial port interrupt enable)
o ET1 (Timer 1 interrupt enable)
o EX1 (External Interrupt 1 enable)
o ET0 (Timer 1 interrupt enable)
o EX0 (External interrupt 0 enable)
o 1 for enable and 0 for disable
INTERRUPT PRIORITY REGISTER FORMAT

D7 D0
- - PT2 PS PT1 PX1 PT0 PX0
o 0 for low priority and 1 for higher priority

 DEAFULT INTERRUPT PRIORITY
o Higher to Lower
 INT0
 TF0
 INT1
 TF1
78
 Serial Port

I/0 INTERFACING
p1 is used as a general purpose port, P0 and P2 are used as data and address bus in
case of external memory acess, otherwise can be used as input/output ports. P3 port
contains multifunction pins. If we are using serial port, timer input pins ar external
interrupt this port can not be used as port. Out of 8 bits of port p1 some can be
programmed as inputs and some as outputs for example, higher nibble as output can
be connected to leds & lower nibble as input can be connected to 4 switches.
Writing code for 8051

The code can be developed in either assembly language using 8051 instructions or by
using a simple „c‟ program by using cross compilers provided by microcontroller IDEs
like KEIL µVision 3. The code will be compiles/assembled linked and then executable
file will be converted to HEX file to dump it in Microcontroller. For that we use flash
programming software provided my manufacturer i.e. Atmel. Atmel‟s FLIP software is
used for dumping the code into microcontroller.
Steps for writing the code
1. Open KEIL µVision IDE
2. Go to project menu select „new project‟, navigate to desired project folder and give
project name in the file name window and save
3. Select device for target window will open, click on Atmel to drop down the menu,
select AT89C51ED2 and press ok. Another window opens asking to add startup files,
click no, to not to add startup.a51 file
4. Right click on Target1 in project Window and select ‘options for target Target1’
In Target select Xtal(MHz): 11.0592
Check box use on-chip ROM
In output window check the box ‘Create HEX file’
5. Go to File menu open new file to open an editor. Create your souce file(s) and use the
header file “at89c51xd2.h‟ in the source file and save files.
6. Right click on Source group1 and select the option add files to group.
7. After adding source files go to projects-> “build Target” to build source files and create
final outputs. It creates <hex file to be downloaded to target device. After successful
build.
Program downloading
1. Set the slide swich SW2 to PROG position and press reset with SW1 on the kit.
2. Open atmel FLIP 2.4.2 tool
3. Go to device option select, select the specific device AT89C51ED2 and press OK
4. Go to file-> Load hex file, Navigate to desired hex file of the project
5. Go to settings option-> rs232, a window will open make sure that no other
application is using com port. Click on COM select com1, set the baud rate to
115200 and click on connect
6. In operations flow region, check the options ERASE, BLANK CHECK,
PROGRAM, VERIFY.
79
7. In the right most side of the window check the box BLJB abd set the address of
BSB,EB,SBV as 00,FF and FC respectively and select option „level0‟ in device SSB
region.
8. After performing above steps click run button wait until the status bar displays
finished.
9. After programming slide SW2 to RUN position and reset SW1 to execute the
program.
6.1 4x4 keypad and 7 segment LED interfacing
// Takes a key from key board and displays it on LCD screen

/* connections: CN1 port0 to CN5 keypad
CN2 port1 CN8 7 segment display
CN4 port3 CN7 7 segment display as digit select */
// target Atmel89c51ed2
#include "at89c51xd2.h"
// This project includes the following files:
// 1. kbdisp.c the source program to keypad
void scan(void);
void get_key(void);
void display(void);
void delay_ms(int i);
void uart_init(void);
void delay(int);
unsigned char temp1=0x00;
unsigned char temp2;
idata unsigned char row,col,key;
unsigned char scan_code[16]={0xEE, 0xDE, 0xBE, 0x7E, 0xED, 0xDD, 0xBD, 0x7D,
0xEB, 0xDB, 0xBB, 0x7B, 0xE7, 0xD7, 0xB7, 0x77 };
unsigned char LED_CODE[16]=
{0x3f,0x66,0x7f,0x39,0x06,0x6d,0x6f,0x5e, 0x5b,0x7d,0x77,0x79,
0x4f,0x07,0x7c,0x71};
idata unsigned char temp,temp4,temp3,res1,flag,result=0x3F;
void main ()
{
80
// configure P2 lower as input to read from rows
//P2=0x0f;
while(1)
{
get_key();
display();
P3 = 0xFF;
}
} //end of main()
// get_key() function will make columns high one by one
// and calls scan() function
// on sensing a key from scan() function it
// will compare the received scan code with
// scan code lookup table and returns ASCII code
// rows are read from Port P0 is scan() function
// this function is in an eternal loop
// wiil return to main() only after getting a key
void get_key(void)
{
int i;
display();
flag = 0x00;
while(flag == 0x00)
{
for(row=0;row<4;row++)
{
if( row == 0)
temp3=0xFE;
else if(row == 1)
temp3=0xFD;
else if(row == 2)
temp3=0xFB;
else if(row == 3)
temp3=0xF7;
// make coulmn high one by one output to Port P1 and
81
// invoke scan() function
P0 = temp3;
scan();
delay_ms(10);
// on sensing a key scan() function will make flag = 0xff
if(flag == 0xff)
break;
} // end of for
if(flag == 0xff)
break;
} // end of while
// in this for for loop scan code received which is in res1 variable is compared with
// the lookup table for array scan code[] and when a match is
// found will return the correspoding led code for the key pressed
P3 = 0x00; // Enable U21
for(i=0;i<16;i++)
{
if(scan_code[i] == res1)
{
result = LED_CODE[i];
break;
}
}
}// end of get_key();
// columns are made high one by one in the get_key() function

// will read the rows one by one and if key is sensed
// will return the scan code for the key pressed
// row lines are connected to P2.0 - P2.3 lines
void scan(void)
{
82
unsigned char t;
temp4 = P0;
temp4 = temp4 & 0xF0; //read port2 ,mask with 0x0Fh
if(temp4 != 0xF0)// Means a key is sensed

{
delay_ms(30);
delay_ms(30); // give some delay for debouncing
temp4 = P0; // read the port again

temp4 = temp4 & 0xF0;
if(temp4 != 0xF0) // debounce

{
flag = 0xff; // set the flag denoting a key is received
res1 = temp4;
t = temp3 & 0x0F; // take the row input from P2
res1 = res1 | t; // and OR it with column value
} // to get the scan
code of the key pressed
else
{
flag = 0x00;
}
}
} // end of scan()
void display(void)
{
// P2 = 0x0f is done beacuse P2 upper 4 bits are used
// as address of 7 segment display
// data is output on to P0 port
// result contians
83
// P3=0x00;
P1 = result;
}
void delay_ms(int i)
{
int j;
for(j=0;j<i;j++);
}
6.2 Decimal Counter display on seven segment LED display
/* When this routine is executed the counting starts from 000000 to 999999 */
/* on six 7-segment display units(U21 to U26).
Connections: CN1 port0 to CN7 and CN2 port1 to CN8 */
#include <at89c51xd2.h>
#include <intrins.h>
void delay(int);
unsigned char temp1=0x00;
unsigned char dig1=0x00, dig2=0x00, dig3=0x00,dig4=0x00, dig5=0x00, dig6=0x00,
temp3=0x00;
unsigned char twenty_count = 0x00,dig_count=0x00;
/*Lookup Table for displaying 0 to 9 digits

array_dec[10]:->
value= h g f e d c b a On 7-SEG U15
0x3F = 0 0 1 1 1 1 1 1 -> Displaying '0'
0x06 = 0 0 0 0 0 1 1 0 -> Displaying '1'
0x5B = 0 1 0 1 1 0 1 1 -> Displaying '2'
0x4F = 0 1 0 0 1 1 1 1 -> Displaying '3'
0x66 = 0 1 1 0 0 1 1 0 -> Displaying '4'
84
0x6D = 0 1 1 0 1 1 0 1 -> Displaying '5'
0x7D = 0 1 1 1 1 1 0 1 -> Displaying '6'
0x07 = 0 0 0 0 0 1 1 1 -> Displaying '7'
0x7F = 0 1 1 1 1 1 1 1 -> Displaying '8'
0x6F = 0 1 1 0 1 1 1 1 -> Displaying '9' */
unsigned char array_dec[10] = {0x3F,0x06,0x5B,0x4F,0x66,0x6D,0x7D,0x07,0x7F,0x6F};

unsigned char temp2 = 0x00;
unsigned int i=0;
bit tmr0_flg = 0,one_sec_flg = 0;
void timer0_init(void);
void Display(void);
void main(void)
{
timer0_init(); // Initialize the Timer-0
EA = 1; // Enabling Global Interrupt
while(1)
{
while(tmr0_flg == 0);
tmr0_flg = 0;
dig_count += 1;
if(dig_count == 0x06)
dig_count = 0x00;
if(one_sec_flg == 1)
{
one_sec_flg = 0;
dig1 +=1;
if(dig1 == 0x0A)
{
dig1 = 0;
dig2 +=1;
if(dig2 == 0x0A)
85
{
dig2 = 0;
dig3+=1;
if(dig3 == 0x0A)
{
dig3 = 0;
dig4 += 1;
if(dig4 == 0x0A)
{
dig4 = 0;
dig5 += 1;
if(dig5 == 0x0A)
{
dig5 = 0;
dig6 +=1;
if(dig6 == 0x0A)
{
dig6 = 0;
}
}
}
}
}
}
} //end of one_sec if
Display();
} //end of while(1)
} //end of main
void timer0_init(void)
{
86
TMOD = 0x01; // Timer0 is configured in Mode-1,
TL0 = 0x00;
TH0 = 0xF8; // For 2.2ms Delay
TCON = 0x00; // Clearing All Flags

ET0 = 1; // Enabling Timer0 Interrupt
TR0 = 1; // Turn ON the Timer0
}
void timer0_isr(void) interrupt 1

{
TL0 = 0x00; // Reloading Value into registers for
every overflow
TH0 = 0xF8;
TF0 = 0; // Clearing Interrupt Flag
tmr0_flg = 1;
if(twenty_count == 5)//multiplied by 50 for Sec
{
one_sec_flg = 1;
twenty_count = 0x00;
}
else twenty_count += 1;
}
void Display(void) // To display on 7-segments

{
P0 = 0xF0;
for(i=0;i<6;i++);
if(dig_count == 0x00) // For Segment U26

{
temp3 = dig1;
P0 = 0x50;
}
87
else if(dig_count == 0x01) // For Segment U25
{
temp3 = dig2;
P0 = 0x40;
}
{
temp3 = dig3;
P0 = 0x30;
}
{
temp3 = dig4;
P0 = 0x20;
}
{
temp3 = dig5;
P0 = 0x10;
}
{
temp3 = dig6;
P0 = 0x00;
}
temp3 &= 0x0F;
temp2 = array_dec[temp3]; // Decoding to 7-segment
P1 = temp2; // Taking Data Lines for 7-Seg
}
88
6.3 ADC interfacing
/* This program displays the ADC output of the ADC0809 IC.

Connections: CN2 port1 to CN15 connector and CN1 port0 connector to CN16 of adc
block.Also Connect CN3 port2 to CN6 of LCD block. Vary pot R42 to gewt different input
voltage values
*/
#include<at89c51xd2.h>
#include<stdio.h>
// LCD FUNCTION PROTOTYPE

void lcd_init(void);
void lcd_comm(void);
void lcd_data(void);
void delay(int);

unsigned char temp2,buf[8];
float adc_temp;
sbit EOC = P0^4;
sbit START_ALE = P0^7;
unsigned char xdata arr1[12]={"ADC O/P = "};
unsigned char xdata arr2[12]={"ADC I/P = "};
unsigned char i,a,temp_hi,temp_low;
unsigned int vtemp1,adc_val;
unsigned char temp_msg[]={" "};
void main ()
{
START_ALE = 0;
lcd_init();
temp1 = 0x80; // Display the data from first

position of first line
lcd_comm(); // Command Writing
for(i=0;i<10;i++)
{
temp2 = arr1[i];
lcd_data(); // Data Writing
}
89
P1 = 0xff; // Configure P1 as input to read the ADC o/p
delay(200);
while(1)
{
P0 &= 0xF0; // Select the as input channel
START_ALE=1; // Generate H->L transition on ALE line

to start ADC
delay(5);
START_ALE = 0;
do // Wait until
End of conversion takes place
{
vtemp1=P0;
vtemp1=vtemp1 & 0x10;
} while(vtemp1 == 0x10); // POLL EOC LINE HI TO LOW
do
{
vtemp1=P0;
vtemp1=vtemp1 & 0x10;
} while(vtemp1 == 0x00); // LOW TO HIGH
adc_val = P1; // display adc result on

the data field
adc_temp = (((float)adc_val * 5)/255);
temp_hi=adc_val>>4;
temp_hi=temp_hi & 0x0f;
temp_low=adc_val & 0x0f;
if(temp_hi>9) // Convert the

received ADC o/p into ASCII code
temp_hi = temp_hi + 0x37;
else
temp_hi = temp_hi + '0';
if(temp_low>9)
temp_low = temp_low + 0x37;
90
else
temp_low = temp_low + '0';
delay(100);
temp_msg[1] = temp_hi ;
temp_msg[2] = temp_low ;
temp1 = 0x8A;
lcd_comm(); // Command Writing
temp2 = temp_hi;
lcd_data();
temp2 = temp_low;
lcd_data();
adc_temp = (int)(adc_temp*100);
i=100;
for(a=0;a<4;a++)
{
buf[a] = adc_temp / i;
adc_temp -= buf[a] * i;
buf[a] += '0';
i /= 10;
}
buf[3] = buf[2];
buf[2] = buf[1];
buf[1] = '.';
buf[4] = '\0';
temp1 = 0xC0;
lcd_comm(); // Displaying at 1st line of LCD
for(i=0;i<10;i++)
{
temp2 = arr2[i];
lcd_data(); // Data Writing
}
for(i=0;(buf[i]!='\0');i++)
{
temp2 = buf[i];
91
lcd_data();
}
} // end of while(1)
}
\\ LCD routines LCD.C

#include <intrins.h>
//For _nop_();
// LCD FUNCTION PROTOTYPE

extern void lcd_comm(void);
extern void wr_cn(void);
extern void wr_dn(void);
void delay(int);
extern unsigned char temp1;

extern unsigned char temp2;
unsigned char var;
sbit RS = P2^7;
sbit EN = P2^6;
sbit RW = P2^5;
sbit lcd_backlight = P2^4;
void lcd_init(void)
{
temp1 = 0x30; // D5(P2.5)=1,D4(P2.4)=1
wr_cn();
delay(500);
temp1 = 0x30; // D5(P2.5)=1,D4(P2.4)=1

wr_cn();
delay(500);
temp1 = 0x30; // D5(P2.5)=1,D4(P2.4)=1

wr_cn();
delay(500);
temp1 = 0x20; // Sets the interface data lenght to 4-bits, 1-line, 5X7
dots
wr_cn();
delay(500);
temp1 = 0x28; // Display shift
92
lcd_comm();
delay(500);
temp1 = 0x0f; // display on,cursor on, cursor blinking

lcd_comm();
delay(500);
temp1 = 0x06; // Shift cursor right with auto increment

lcd_comm();
delay(500);
temp1 = 0x80; // Clear display with cursor on first position

lcd_comm();
delay(500);
temp1 = 0x01;
lcd_comm();
delay(500);
// Function to pass commands to LCD

void lcd_comm(void)
{
var = temp1;
temp1 = temp1 & 0xf0; // Convert the byte into two nibbles
temp1 = temp1 >> 4; // Shift the most significant nibble to
least position
wr_cn();
temp1 = var & 0x0f; // Get the least significant nibble

wr_cn();
// lcd_backlight = 1;
delay(60);
}
// Function to pass data to LCD

void lcd_data(void)
{
var = temp2;
temp2 = temp2 & 0xf0; // Convert the byte into two nibbles
temp2 = temp2 >> 4; // Shift the most significant nibble to least position
wr_dn();
93
temp2 = var & 0x0f; // Get the least significant nibble
wr_dn();
// lcd_backlight = 1;
delay(60);
}
// Function to write to command reg of LCD

void wr_cn(void)
{
temp1 = temp1 & 0x7f; // RS=0
temp1 = temp1 & 0xDF;
temp1 = temp1 | 0x40; // EN=1
P2 = temp1;
_nop_();
_nop_();
_nop_();
_nop_();
_nop_();
temp1 = temp1 & 0xbf; // EN=0,

P2 = temp1;
}
// Function to write to data reg of LCD

void wr_dn(void)
{
temp2 = temp2 | 0xc0; // RS=1,EN=1
temp2 = temp2 & 0xDF;
P2 = temp2;
_nop_();
_nop_();
_nop_();
_nop_();
_nop_();
temp2 = temp2 & 0xbf; // EN = 0;

P2 = temp2;
}
void delay(int count)

{
94
int i;
for(i=0;i<count;i++);
}
6.4 Stepper motor interface
/**************************** Stepper Motor

******************************
Object : To demonstrate the Stepper motor interface.
Connection : PORT0 Connected to CN12 of SSR block. Connect stepper motor to PM1
on board. Also connect port3 CN4 connector to CN18 and short pins 1 &2 of jp4 for
INT0
Output: whenever you run the program the motor rotates in clockwise.
If you want to change the direction press the interrupt button
( P3.2/INTO*). when you press the button, INT0 interrupts the main
program
and changes the direction of the motor .
***********************************************************************
***/
static bit Dir=0;

sbit buzzer = P0^5;
void ChangeDir(void) interrupt 0 /* Int Vector at 000BH, Reg Bank 1 */

{
Dir = ~Dir; /* Complement the Direction flag */
}
void delay(unsigned int x) /* Delay Routine */
{
for(;x>0;x--);
}
main()
{
unsigned char Val,i;
EA=0x1; /* Enable Interrupt flag and Interrupt
0 & Serial Interrupt */
EX0=0x1;
ES=1; /*since the monitor is using the serial interrupt it has to be enabled*/
while(1)
{
95
if(Dir) //* If Dir Clockwise
{
Val = 0x08;
for(i=0;i<4;i++)
{
P0 = Val; //* Write data for clock wise
direction
Val = Val>>1;
delay(575);
}
}
else // AntiClockwise Direction
{
Val = 0x01;
for(i=0;i<4;i++)
{
P0 = Val; // Write data for anticlock wise
direction
Val = Val<<1;
delay(575);
}
}
}
}
96
LAB MANUAL
For
IC APPLICATIONS LAB
(Common to III Year I Semester ECE, ECM & EEE)
(Department of Electronics and Communication Engineering)
Sreenidhi Institute of Science and Technology
(Autonomous)
(2020-2021)
97
Contents
S.No Contents Page No.
1 Syllabus copy 99
2 Vision of the Department 100
3 Mission of the Department 100
4 PEOs and POs 100
5 Course objectives and outcomes 102
6 Brief notes on the importance of the course and how it fits into 102
the curriculum
7 Prerequisites 103
8 Course mapping with PEOs and POs 103
9 Do‟s and Don‟ts 105
10 OP AMP Modes(-ve feed back) – Inverting ,Non inverting, 106
Differential amp, Unity gain.
11 OP AMP Applications – Adders, Subtractor. 113
12 OP AMP Applications – Comparator Circuits. 117
13 OP AMP Applications – clipper Circuits. 120
14 Square wave generator using OP AMP 124
15 Triangular wave generator using OP AMP 127
16 Active Filter Applications – LPF, HPF (first order) 133
17 Oscillators-RC phase shift , wein bridge. 135
18 IC 555 Timer – Monostable 141
19 IC 555 Timer -Astable 143
20 4 bit DAC using OP AMP. 147
21 IC 723 voltage regulator 150
22 IC 741 Data sheet 155
23 IC NE 555 Data Sheet 156
24 IC LM 723 Data Sheet 158
Year/Sem Sub. Code Subject Name L T P/D C
7CC76 IC APPLICATIONS LAB
III-I - - 4 2
Prerequisites: EDC, ECA, STLD, NT.
Course Objectives:
The objectives of this course are

 To Design and analyze the various circuits and systems using IC 741 op-amp.
 To Design and analyze the various circuits and systems using Digital ICs.
 An ability to explore the applications of IC 741 OP-AMP.
 An ability to design Active filters and its applications
 An ability to understand and implement generate square and Triangular waveforms using 555
Timers
 An ability to design D to A converters and its applications

a b c d e f g h i j k L m
CO1 3 3 2 3 3 2 3 3 2
CO2 3 2 2 3 3 3 3 2
CO3 3 3 2 3 3
CO4 3 2 3 3 2 3 2
CO5 3 2 3 3
CO6 2 3 3 3 2 3 3 2
Syllabus Content
(IC Application Lab)
Design and testing of
1. OP AMP Modes(-ve feed back) – Inverting ,Non inverting, Differential amp, Unity gain.
2. OP AMP Applications – Adders, Subtractor.
3. OP AMP Applications – Comparator Circuits.
4. OP AMP Applications – clipper Circuits.
5. Square wave generator using OP AMP
6. Triangular wave generator using OP AMP
7. Active Filter Applications – LPF, HPF (first order)
8. Oscillators-RC phase shift , wein bridge.
9. IC 555 Timer – Monostable
10. IC 555 Timer -Astable .
11. 4 bit DAC using OP AMP.
12. IC 723 voltage regulator
99
To create an educational environment for students to excel in their professional carrier, and to
solve the challenges of industry in the field of Electronics and Communication Engineering with
focus on human values, professional ethics and social responsibility.

1. Training the students in the core subjects of Electronics and Communication engineering
with due focus on multi-disciplinary areas.
2. Establishing liaison with relevant industries, R&D organizations and renowned academia for
exposure to modern tools and practical aspects of technology.
3. Inculcating team work, leadership, professional ethics, effective communication and
interpersonal skills to make students globally competent in employment as well as
entrepreneurship.
4. Promoting scientific temper and research culture in the graduates towards lifelong learning,
and to work towards the engineering solution in the contexts of society and environment.
PEOs and POs

Program Educational Objectives of B. Tech (ECE) Program :
PEO- I. To apply the knowledge of mathematics, science and engineering fundamentals to find
the solution of complex engineering problems concerning societal, health, safety, cultural and
environmental issues.
disciplinary domains leading to design of novel products using modern tools and to promote
skills in project management, entrepreneurship and IPR.
100
Program Outcomes of B.Tech ECE Program:
a. Engineering knowledge: Apply the knowledge of mathematics, science, engineering
fundamentals, and an engineering specialization to the solution of complex engineering
problems.
b. Problem analysis: Identify, formulate, review research literature, and analyze complex
engineering problems reaching substantiated conclusions using first principles of
mathematics, natural sciences, and engineering sciences.
c. Design/development of solutions: Design solutions for complex engineering problems

and design system components or processes that meet the specified needs with
appropriate consideration for the public health and safety, and the cultural, societal, and
environmental considerations.
d. Conduct investigations of complex problems: Use research-based knowledge and

research methods including design of experiments, analysis and interpretation of data,
and synthesis of the information to provide valid conclusions.
e. Modern tool usage: Create, select, and apply appropriate techniques, resources, and
modern engineering and IT tools including prediction and modeling to complex
engineering activities with an understanding of the limitations.
f. The engineer and society: Apply reasoning informed by the contextual knowledge to
assess societal, health, safety, legal and cultural issues and the consequent responsibilities
relevant to the professional engineering practice.
g. Environment and sustainability: Understand the impact of the professional engineering

solutions in societal and environmental contexts, and demonstrate the knowledge of, and
need for sustainable development.
h. Ethics: Apply ethical principles and commit to professional ethics and responsibilities
and norms of the engineering practice.
i. Individual and team work: Function effectively as an individual, and as a member or

leader in diverse teams, and in multidisciplinary settings.
j. Communication: Communicate effectively on complex engineering activities with the

engineering community and with society at large, such as, being able to comprehend and
101
write effective reports and design documentation, make effective presentations, and give
and receive clear instructions
k. Project management and finance: Demonstrate knowledge and understanding of the

engineering and management principles and apply these to one‟s own work, as a member
and leader in a team, to manage projects and in multidisciplinary environments.
l. Life-long learning: Recognize the need for, and have the preparation and ability to
engage in independent and life-long learning in the broadest context of technological
change.
Course objectives and outcomes

Course Objectives:
 To Design and analyze the various circuits and systems using IC 741 op-amp.
 To Design and analyze the various circuits and systems using Digital ICs.
 An ability to explore the applications of IC 741 OP-AMP.
 An ability to design Active filters and its applications
 An ability to understand and implement generate square and Triangular waveforms
using 555 Timers
 An ability to design D to A converters and its applications
Brief notes on the importance of the laboratory course and how it

fits into the curriculum
In this laboratory course, the students will be able to study and explore the fundamentals of ICs
and OP -Amps. They will also explore the applications like adder, subtractor, Amplifier etc..
The experimental design analysis includes the various circuits like Filters, Timers, Oscillators
and D/A Converters. After the completion of the course students can proceed to build an analog
circuits using ICs.
102
Prerequisites: EDC, ECA, STLD, NT.
Course mapping with PEOs and POs
Mapping of PEOs with POs

PEOs PEOs Description Program Outcomes(POs)
To apply the
knowledge of a) Apply the knowledge of mathematics, science,
mathematics, science engineering fundamentals, and an engineering
and engineering specialization to the solution of complex
fundamentals to find engineering problems.
I the solution of
complex engineering b) Identify, formulate, review research literature,
problems concerning and analyze complex engineering problems
societal, health, reaching substantiated conclusions using first
safety, cultural and principles of mathematics, natural sciences, and
environmental engineering sciences.
issues.
c) Design solutions for complex engineering

Empowering problems and design system components or
graduates to exhibit processes that meet the specified needs with
proficiency in core appropriate consideration for the public health
areas through and safety, and the cultural, societal, and
evolving technologies environmental considerations.
II in electronics and
communication d) Use research-based knowledge and research
engineering and to methods including design of experiments,
identify, analyze, analysis and interpretation of data, and
design, and conduct synthesis of the information to provide valid
experiments for conclusions.
innovative solutions.
Facilitating
graduates to achieve e) Create, select, and apply appropriate
academic excellence techniques, resources, and modern engineering
and pursue R&D in and IT tools including prediction and modeling
III multi-disciplinary to complex engineering activities with an
domains leading to understanding of the limitations.
design of novel
products using f) Apply reasoning informed by the contextual
modern tools and to knowledge to assess societal, health, safety,
promote skills in legal and cultural issues and the consequent
103
project management, responsibilities relevant to the professional
entrepreneurship and engineering practice.
IPR.
g) Understand the impact of the professional
engineering solutions in societal and
environmental contexts, and demonstrate the
knowledge of, and need for sustainable
development.
h) Apply ethical principles and commit to

professional ethics and responsibilities and
norms of the engineering practice.
i) Function effectively as an individual, and as a

member or leader in diverse teams, and in
multidisciplinary settings.
j) Communicate effectively on complex

Developing human engineering activities with the engineering
values, and community and with society at large, such as,
professional ethics, being able to comprehend and write effective
improving the reports and design documentation, make
IV effective effective presentations, and give and receive
communication skills, clear instructions
team work, leadership
k) Demonstrate knowledge and understanding of
qualities, and life-long
the engineering and management principles and
learning.
apply these to one‟s own work, as a member
and leader in a team, to manage projects and in
multidisciplinary environments.
l) Recognize the need for, and have the

preparation and ability to engage in
independent and life-long learning in the
broadest context of technological change.
104
DO’S AND DON’TS
Do’s
 Be punctual.
 Maintain discipline & silence.
 Keep the Laboratory clean and tidy.
 Enter Laboratory with shoes.
 Handle instruments with utmost care.
 Come prepared with circuit diagrams, writing materials and calculator.
 Follow the procedure that has been instructed.
 Return all the issued equipment‟s properly.
 Get the signature on experiment result sheet daily.
 For any clarification contact faculty/staff in charge only.
 Shut down the power supply after the experiment.
Don’ts
 Avoid unnecessary chat or walk.
 Playing mischief in the laboratory is forbidden.
 Disfiguring of furniture is prohibited.
 Do not start the experiment without instructions.
 Avoid using cell phones unless absolutely necessary.
 Avoid late submission of laboratory reports.
105
Expt-1
Op-Amp Modes ( - feed back) – Inverting, Non-Inverting, Differential
Amplifier, Unity Gain
AIM: To design and study the Op-Amp modes ( negative feedback) – Inverting, Non-Inverting,
Differential Amplifier, Unity Gain using IC 741 Op-Amp.
EQUIPMENTS AND COMPONENTS:

IC 741 Op-Amp
Function Generator
IC Trainer Kit
Dual Trace Oscilloscope
Connecting probes and wires
THEORY:
An “Operational amplifier” is a direct coupled high-gain amplifier usually consisting of one or
more differential amplifiers and usually followed by a level translator and output stage. The
operational amplifier is a versatile device that can be used to amplify dc as well as ac input
signals and was originally designed for computing such mathematical functions as addition,
subtraction, multiplication and integration. The Op-Amp can be used in two modes Open Loop:
(The output assumes one of the two possible output states, that is +Vsat or – Vsat and the amplifier
acts as a switch only). Closed Loop: (The utility of an op-amp can be greatly increased by
providing negative feedback. The output in this case is not driven into saturation and the circuit
behaves in a linear manner).
The op-amp can be used in three modes in closed loop configuration they are
1. Differential amplifier
2. Inverting amplifier
3. Non inverting amplifier
106
The pin configuration of an Op-Amp is given below.
Fig-1: Pin Diagram of IC 741 Op-Amp
Inverting Amplifier:
An inverting-amplifier circuit is built by grounding the positive input of the operational amplifier
and connecting resistors R1 and R2, called the feedback networks, between the inverting input
and the signal source and amplifier output node, respectively. With assumption that reverse-
transfer parameter is negligibly small, open-circuit voltage gain Av, input resistance Zin and
output resistance Zo can be calculated.
Non-Inverting Amplifier:
The operational amplifier can also be used to construct a non-inverting amplifier with the circuit
indicated below. The input signal is applied to the positive or non-inverting input terminal of the
operational amplifier, and a portion of the output signal is fed back to the negative input
terminal. Analysis of the circuit is performed by relating the voltage at V2 to both the input
voltage Vin and the output voltage Vo. The output is applied back to the inverting (-) input
through the feedback circuit (closed loop) formed by the input resistor R1 and the feedback
resistor R2. This creates ve feedback as follows. Resistors R1 and R2 form a voltage-divider
circuit, which reduces Vo and connects the reduced voltage V2 to the inverting input.
107
Differential Amplifier:
The amplifier which amplifies the difference between the two input voltages is called differential
amplifier. It has two input signals V1 and V2 and two input resistances R1 and R2 and a
feedback resistor Rf . The input signals scaled to the desired values by selecting appropriate
values for the external resistors. From the figure, the output voltage of the differential amplifier
with a gain of „1‟ is V0= -Rf/R1 (V2-V1) V0= V1-V2 Also R1=R2= Rf =1KΩ
Thus, the output voltage V0 is equal to the voltage V1 applied to the non-inverting terminal
minus voltage V2 applied to inverting terminal.
Unity Gain Amplifier (Buffer Amplifier):
Buffer amplifier:
A buffer amplifier (sometimes simply called a buffer) is one that provides electrical impedance
transformation from one circuit to another. Two main types of buffer exist: the voltage buffer
and the current buffer.
Voltage buffer: A voltage buffer amplifier is used to transfer a voltage from a first circuit,
having a high output impedance level, to a second circuit with a low input impedance level. The
interposed buffer amplifier prevents the second circuit from loading the first circuit unacceptably
and interfering with its desired operation.
Current buffer: A current buffer amplifier is used to transfer a current from a first circuit,
having a low output impedance level, to a second circuit with a high input impedance level. The
interposed buffer amplifier prevents the second circuit from loading the first circuit unacceptably
and interfering with its desired operation
Op-Amp as a Voltage follower
A unity gain buffer amplifier may be constructed by applying a full series negative feedback
(Fig. 1) to an op-amp simply by connecting its output to its inverting input, and connecting the
signal source to the non-inverting input (Fig. 2). In this configuration, the entire output voltage
(β = 1 in Fig. 1) is placed contrary and in series with the input voltage. Thus the two voltages are
subtracted according to KVL and their difference is applied to the op-amp differential input. This
108
connection forces the op-amp to adjust its output voltage simply equal to the input voltage
(Vout follows Vin )so the circuit is named op-amp voltage follower.
Used as a buffer amplifier to eliminate loading effects (e.g., connecting a device with a high
source impedance to a device with a low input impedance).
The importance of the circuit is due to the input and output impedances of the op-amp. The input
impedance of the op-amp is very high, meaning that the input of the op-amp does not load down
the source or draw any current from it. Because the output impedance of the op-amp is very low,
it drives the load as if it were a perfect voltage source. Both the connections to and from the
buffer are therefore bridging connections, which reduce power consumption in the source,
distortion from overloading, crosstalk and other electromagnetic interference. The voltage
follower is often used for the construction of buffers for logic circuits.
CIRCUIT DIAGRAM:
Fig-2: Inverting Amplifier using IC 741 Op-Amp
109
Fig-3: Non-Inverting Amplifier using IC 741 Op-Amp
Fig-4: Differential Amplifier using IC 741 Op-Amp
Fig-5: Unity gain amplifier using IC 741 Op-Amp

PROCEDURE:
110
1. Connect the circuit as shown in the circuit diagram in Fig-2.
2. Measure the input and output voltage from the input and output waveform in the CRO.
3. Note down the outputs from the CRO
4. Draw the necessary waveforms on the graph sheet.
5. Repeat the above steps from 1 to 4 for figures 3, 4 and 5.
OBSERVATIONS:
1. Observe the output waveform from CRO. An inverted/non-inverted and amplified waveform
will be observed based on the type of connection done.
2. Measure the input and output voltage from the input and output waveform in the CRO.
3. Calculate
4. Compare the theoretical voltage gain from the above equations with the experimental values
obtained by dividing output voltage by input voltages observed.
5. Observe outputs of the all the circuits using different input waveforms.
RESULT:
1. The output and voltage gain of the inverting amplifier is found to be _______.
2. The output and voltage gain of the non-inverting amplifier is found to be _______.
3. The output and voltage gain of the differential amplifier is found to be _______.
4. The output and voltage gain of the unity gain amplifier is found to be _______.
111
Hence the op-amp can be configured as inverting amplifier, non-inverting amplifier, differential
amplifier and unity gain amplifier circuit.
REVIEW QUESTIONS:
1. Inverting amplifier with feedback is a

(a) Voltage – shunt feedback amplifier (b) Voltage – series feedback amplifier
(c) Current shunt feedback amplifier (d) Current series feedback amplifier
2. Non-inverting amplifier with feedback.
(a) Voltage – shunt feedback amplifier (b) Voltage – series feedback amplifier
(c) Current shunt feedback amplifier (d) Current series feedback amplifier
3. What do you mean by a differential amplifier?
4. What are the ideal characteristics of an op-amp?
112
Expt-2
OP-AMP APPLICATIONS-ADDERS, SUBTRACTORS
AIM: To study and verify the Op-Amp applications adders and subtractors using IC 741
operational amplifier.
S.NO NAME OF TYPE RANGE QUANTITY

EQUIPMENT/COMPONENT
1 OP-AMP IC 741 - 1
2 RESISTOR - 1KOhm 4
3 IC TRAINER KIT - - 1
THEORY:
ADDER:
The Operational Amplifier is probably the most versatile Integrated Circuit available. It is very
cheap especially keeping in mind the fact that it contains several hundred components. The most
common Op-Amp is the 741 and it is used in many circuits. The OP-AMP is a „Linear
Amplifier‟ with an amazing variety of uses. Its main purpose is to amplify (increase) a weak
signal - a little like a Darlington Pair. The OP-AMP has two inputs, INVERTING ( - ) and NON-
INVERTING (+), and one output at pin 6.Op-Amp may be used to design a circuit whose output
is the sum of several input signals such a circuit is called a summing amplifier or summer. We
can obtain either inverting or non-inverting summer. The circuit diagrams shows a two input
inverting summing amplifier. It has two input voltages V1and V2, two input resistors R1, R2 and
a feedback resistor Rf .Assuming that Op-Amp is in ideal conditions and input bias current is
assumed to be zero, there is no voltage drop across the resistor Rcomp and hence non inverting
input terminal of op-amp is at ground potential and by taking nodal equations we have,
V1/R1+V2/R2+V0/Rf =0
V0= - [ ( R f /R1) V1+(Rf /R2) V2] And here
R1= R2= Rf =1KΩ V0= -(V1+V2) Thus output is inverted and sum of inputs.
113
SUBTRACTOR:
A basic differential amplifier can be used as a subtractor. It has two input signals V1 and V2 and
two input resistances R1 and R2 and a feedback resistor Rf . The input signals scaled to the
desired values by selecting appropriate values for the external resistors. From the figure, the
output voltage of the differential amplifier with a gain of „1‟ is
V0= -Rf/R1 (V2-V1)
V0= V1-V2
Also R1=R2= Rf =1KΩ
Thus, the output voltage V0 is equal to the voltage V1applied to the non-inverting terminal
minus voltage V2 applied to inverting terminal. Hence the circuit is a subtractor.
CIRCUIT DIAGRAMS:
ADDER:
Fig-1: Adder using IC 741 Op-Amp

SUBTRACTOR:
Fig-2: Subtractor using IC 741 Op-Amp
114
PROCEDURE:
ADDER AND SUBTRACTOR
1. Connections are made as per the circuit diagram.
2. Apply input voltage 1) V1= 5V, V2=2V 2) V1= 5V,V2=5V
3. Using multimeter measure the dc output voltage at the output terminal.
4. For different values of V1 and V2 measure the output voltage.
OBSERVATIONS:
ADDER:
Theoretical Practical
V1 (Volts) V2 (Volts)
Vo = - (V1+V2) Vo= - (V1+V2)
Ex: Vo= - (V1+V2) = -(2+3) = -5V

SUBTRACTOR:
Theoretical Practical
V1 (Volts) V2 (Volts)
Vo=(V1-V2) Vo=(V1-V2)
Ex: Vo = (V1-V2) = (4-2) = 2V
115
RESULT:
ADDER: The obtained value of addition of two voltages is equal to __________.
SUBTRACTOR: The obtained value of subtraction of two voltages is equal to _________.
The operation of IC 741 Op-Amp as an adder and a subtractor is studied and the practical values
are found to be equal to the theoretical values.
REVIEW QUESTIONS:
1. What is the function of an adder?
2. What is the function of a subtrator?
116
Expt-3
OP-AMP APPLICATIONS-COMPARATORS
AIM: To study and verify the Op-Amp application as a comparator using IC 741 operational
amplifier.

NAME OF
S.NO TYPE RANGE QUANTITY
EQUIPMENT/COMPONENT
1 OP-AMP IC 741 - 1
THEORY:
COMPARATOR:
A comparator is a circuit which compares a signal voltage applied at one input of an op-amp
with a known reference voltage at the other input. It is basically an open loop Op-Amp with
output ±Vsat as in the ideal transfer characteristics. It is clear that the change in the output state
takes place with an increment in input Vi of only 2mV. This is the uncertainty region where
output cannot be directly defined. There are basically 2 types of comparators.
a) Non-inverting Comparator ii) Inverting Comparator
The applications of comparator are zero crossing detector, window detector, time marker
generator and phase meter.
CIRCUIT DIAGRAM:
117
Fig-1: Comparator using IC 741 Op-Amp
PROCEDURE:
COMPARATOR:
2. Select the sine wave of 5V peak to peak, 1K Hz frequency.
3. Apply the reference voltage 1V and trace the input and output wave forms.
4. Superimpose input and output waveforms and measure sine wave amplitude with reference to
Vref.
5. Repeat steps 3 and 4 with reference voltages as 2V, 4V, -2V, -4V and observe the waveforms.
6. Replace sine wave input with 5V dc voltage and Vref = 0V.
7. Observe dc voltage at output using CRO.
8. Slowly increase Vref voltage and observe the change in saturation voltage.
9. To make a zero crossing detector, set Vref = 0V and observe the output waveforms.
OBSERVATIONS:
Input Voltage Vref Observed square wave

amplitude
MODEL GRAPH:
Fig2: Comparator output model graphs
118
RESULT:
The operation of IC 741 Op-Amp as a comparator is studied and the practical values are found to
be equal to the theoretical values.
REVIEW QUESTIONS:
1.What is meant by a comparator?
2. What is a window detector?
3.What is a zero crossing detector?
119
Expt-4
OP-AMP APPLICATIONS-CLIPPERS CIRCUITS
AIM: To study and verify the Op-Amp application as a clipper using IC 741 operational
amplifier.
NAME OF
S.NO TYPE RANGE QUANTITY
EQUIPMENT/COMPONENT
1 OP-AMP IC 741 - 1
3 DIODE - - 1
THEORY:
Positive Clipper:
A circuit that removes positive parts of the input signal can be formed by using an op-amp with a
rectifier diode. T he clipping level is determined by the reference voltage Vref, which should less
than the i/p range of the op-amp (Vref < Vin). The Output voltage has the portions of the positive
half cycles above Vref clipped off.
The circuit works as follows:
During the positive half cycle of the input, the diode D1 conducts only until Vin = Vref. This
happens because when Vin <Vref, the output volts V0 of the op-amp becomes negative to device
D1 into conduction when D1 conducts it closes feedback loop and op-amp operates as a voltage
follower. (i.e.) Output V0 follows input until Vin = Vref.
When Vin > Vref => the V0 becomes +ve to derive D1 into off. It opens the feedback loop and op-
amp operates open loop. When Vin drops below Vref (Vin<Vref) the o/p of the op-amp V0 again
becomes –ve to device D1 into conduction. It closes the feedback path. (o/p follows the i/p).
Thus diode D1 is on for vin<Vref (o/p follows the i/p) and D1 is off for Vin>Vref.
120
The op-amp alternates between open loop (off) and closed loop operation as the D1 is turned off
and on respectively. For this reason the op-amp used must be high speed and preferably
compensated for unity gain.
Negative Clipper:
The positive clipper is converted into a –ve clipper by simply reversing diode D1 and changing
the polarity of Vref voltage. The negative clipper clips off the –ve parts of the input signal below
the reference voltage. Diode D1 conducts -> when Vin > -Vref and therefore during this period o/p
volt V0 follows the i/p volt Vin. The –Ve portion of the output volt below –Vref is clipped off
because (D1 is off) Vin<-Vref. If –Vref is changed to –Vref by connecting the potentiometer Rp to
the +Vcc, the V0 below +Vref will be clipped off. The diode D1 must be on for Vin > Vref and off
for Vin.
CIRCUIT DIAGRAM:
Fig-1: Positive Clipper using IC 741 Op-Amp
121
Fig-2: Negative Clipper using IC 741 Op-Amp
PROCEDURE:
1. Set up the circuit shown in Fig.1
2. Connect the output terminals to CRO and observe triangular wave output and plot the
graph.
3. Measure the frequency and amplitude.
OBSERVATIONS:
Observe the input and output waveforms for positive and negative clipper circuits with and
without reference voltages.
Plot the waveforms on graph paper.
MODEL GRAPH:
Fig-3: Expected waveformS for Positive clipper
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Fig-4: Expected waveforms for Negative Clipper
RESULT:
Op-Amp as a positive clipper circuit and negative clipper circuit is verified with and without
reference voltage.
REVIEW QUESTIONS:
1. Why is it important to keep the load resistance for the simple clipping and clamping
circuits as high as possible?
2. Why do diodes have reverse leakage current?
3. How are the leakage current and forward voltage drop affected by temperature?
.
123
Expt-5
SQUARE WAVE GENERATOR USING 741 OP-AMP
AIM:
To verify square wave generator circuit using IC 741 Op-Amp and find its frequency of
oscillation.

IC 741 Op-Amp
Resistors and Capacitor
IC Trainer Kit
Cathode Ray Oscilloscope
Probes and Connecting Wires
THEORY:
Function generator is a signal generator that produces various specific waveforms for test
purposes over a wide range of frequencies. In laboratory type function generator generally one of
the functions (sine, triangle, etc.) is generated using dedicated chips or standard circuits and
converts it into required signal.
There are two main classes of oscillator: relaxation and sinusoidal. Relaxation oscillators
generate the triangular, sawtooth and other non-sinusoidal waveforms. Sinusoidal oscillators
consist of amplifiers with external components used to generate oscillation, or crystals that
internally generate the oscillation. Sine wave oscillators are used as references or test waveforms
by many circuits.
Square wave generator (Astable Multivibrator)

A simple Op-Amp square wave generator is shown in fig.1. also called a free running oscillator.
The principle of generation of square wave output is to force an Op-Amp to operate in the
saturation region. In fig.1 a fraction of β=R2/R1+R2 of the output is fed back to the(+) input
terminal. Thus the reference voltage Vref is βV0 and may take values as +βVsat or – βVsat. The
output is fed back to (-) input terminal after integrating by means of a low-pass RC combination.
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Whenever input at the (-) input terminal just exceeds Vsat switching takes place resulting in a
square wave output. In astable multivibrator both the states are quasi stable.
CIRCUIT DIAGRAM:
Fig-1: Square wave generator using IC 741 Op-Amp
PROCEDURE:
2 .Connect the output terminals to CRO and observe square wave output and plot the graph.
OBSERVATIONS:
Observe the output square waveform.

The Amplitude of the wave form is ________.
The frequency of the wave form is ________.
125
MODEL GRAPH:
Fig-2: Output square waveform

RESULT:
Op-Amp as a square wave generator circuit is verified and its frequency of oscillation is found to
be _____.
REVIEW QUESTIONS:
1. Write some applications of square wave generator?
2. How to calculate the frequency of oscillation of a square wave generator?
3. How to calculate the duty cycle of the square wave generated?
126
Expt-6
TRIANGULAR WAVE GENERATOR USING 741 OP-AMP
AIM:
To verify triangular wave generator circuit using IC 741 Op-Amp and find its frequency of
oscillation.

IC 741 Op-Amps
Resistors and Capacitors
IC Trainer Kit
THEORY:
generate the triangular, saw tooth and other non-sinusoidal waveforms. Sinusoidal oscillators
by many circuits.
Triangular Wave generator

A triangular wave can be simply obtained by integrating a square wave as shown in fig.1.It is
obvious that the frequency of the square wave and triangular wave is the same .Although the
amplitude of the square wave is constant at ±Vsat, the amplitude of triangular wave will decrease
as the frequency increases. This is because the reactance of the capacitor C2 in the feedback
127
circuit decreases at high frequencies. A resistance R5 is connected across C2 to avoid the
saturation problem at low frequencies as in the case of practical integrator.
Fig-1: Triangular Waveform generator using IC 741 Op-Amp
PROCEDURE:
2. Connect the output terminals to CRO and observe triangular wave output and plot the graph.
OBSERVATIONS:
The amplitude of the square wave form is found to be_____.
The amplitude of the triangular wave form is found to be _______.
The time period of the square wave form is found to be ________.
The time period of the triangular wave form is found to be________.
The frequency of the square wave form is found to be ________.
The frequency of the triangular wave form is found to be ________.
MODEL GRAPH:
128
Fig-2: Output wave form of triangular waveform generator
RESULT:
Op-Amp as a triangular wave generator circuit is verified and its frequency of oscillation is
found to be _____.
REVIEW QUESTIONS:
1. What is the equation for calculating frequency of triangular wave output?

2. What is the technique used to generate the triangular wave in the given circuit?.
129
Expt-7
ACTIVE FILTER APLLICATIONS-LPF, HPF [FIRST ORDER]
AIM:
To study, design and obtain frequency response of first order LPF and HPF using Op-Amp IC
741.
EQUIPMENTS AND COMPONENTS:-
S.N QUANTIT
NAME OF TYPE RANGE
O Y
EQUIPMENT/COMPONENT
1 OP-AMP IC 741 - 1
3 RESISTOR - 10Kohm 3
4 CAPACITOR - 0.01uf 1
6 FUNCTION GENERATOR - (0-3)MHz 1
7 CATHODE RAY OSCILLOSCOPE - (0-20)MHz 1
8 PROBES AND CONNECTING - -

WIRES
THEORY:
LOW PASS FILTER:
A frequency selective electric circuit that passes electric signals of specified band of frequencies
and attenuates the signals of frequencies outside the band is called an electric filter. The first
order low pass filter consists of a single RC network connected to the non-inverting input
terminal of the operational amplifier. Resisters R1 and Rf determine the gain of the filter in the
pass band. The low pass filter as maximum gain at f= 0Hz. The frequency range from 0 to fh is
130
called the pass band the frequency range f>fh is called the stop band. The first order low pass
butter worth filter uses an RC network for filtering. The Op-Amp is used in the non-inverting
configuration; hence it does not load down the RC network. Resistor R1 and R2 determine the
gain of the filter. V0/Vin = Af /(1+ jf/f h) Af = 1+ Rf /R1=passband gain of filter
F=frequency of the input signal
Fh=1/2ΠRC =High cut off frequency of filter
V0/Vin=Gain of the filter as a function of frequency
The gain magnitude and phase angle equations of the LPF the can be obtained by converting
V0/Vin into its equivalent polar form as follows|V0/Vin| = Af /(√1 +(f/f h) Φ___ = - t a n - 1 ( f /
f h) where Φ is the phase angle in degrees. The operation of the LPF can be verified from the
gain magnitude equation.
HIGH PASS FILTER:
High pass filters are often formed simply by interchanging frequency determining resistors and
capacitors in LPFs that is, a first order HPF is formed from a first order LPF by interchanging
components „R‟ and „C‟ in the figure. Shows a first order Butterworth HPF with a lower cut off
frequency of „ Fl‟. This is the frequency at which magnitude of the gain is 0.707 times its pass
band value. Obviously all frequencies, with the highest frequency determinate by the closed loop
band width of Op-Amp. For the first order HPF the output voltage is
V0= [1+Rf /R1]j2ΠRCVin/(1-j2ΠfRC)
V0/Vin=Af [j(f/f l)/(1+j(f/f l)]
Where Af =Rf /R1 pass band gain of the filter.
f =frequency of input signal. fl=1/2ΠRC = lower cut off frequency
Since, HPFs are formed from LPFs simply by interchanging R‟s and C‟s the design and
frequency scaling procedures of the LPFs are also applicable to HPFs.
CIRCUIT DIAGRAM:
LPF:
131
Fig-1: Low pass filter using IC 741 Op-Amp
HPF:
Fig-2: High pass filter using IC 741 Op-Amp
PROCEDURE:
2. Apply sine wave of amplitude 2Vp-p to the non-inverting input terminal.
3. Vary the input signal frequency.
4. Note down the corresponding output voltage.
5 .Calculate gain in dB.
6 . Tabulate the values.
7. Plot a graph between frequency and gain.
8. Identify stop band and pass band from the graph.
.
132
OBSERVATIONS: (LPF)
Gain in dB (20 log

S.NO Input frequency Output voltage
Vo/Vi)
OBSERVATIONS: (HPF)
Gain in dB (20 log

S.NO Input frequency Output voltage
Vo/Vi)
CALCULATIONS
LPF:
fh=1/2πRC
fh=1/2πx15kx0.01µf
= 1kHz
Choose C=0.01µf
Av=1+Rf/R1
With this
R1=10kΩ
Rf=10kΩ
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HPF:
Choose a standard value of Capacitor C say 0.01 uF
Then fl=1/2πRC
1/2πx15kx0.01µf
= 1k
fL=1kHz
Av=1+Rf/R1
With this
R1=10kΩ
Rf=10kΩ
MODEL GRAPH:
LPF:
Fig-3: Model frequency response of LPF

HPF:
134
Fig-4: Model frequency response of HPF
RESULT:-
HPF : The obtained gain Av =__________

The band width =__________
LPF: The obtained gain Av =__________

The band width =__________
The HPF and LPF filters are designed and obtained gain is found to be equal to the theoretical
value of gain .The frequency response of LPF and HPF using IC741 Op-Amp is plotted.
REVIEW QUESTIONS
1. Classify filters.
2. Discuss the disadvantages of passive filters.
3. Why are active filters preferred?
4. List the commonly used filters.
135
Expt-8
OSCILLATORS-RC PHASE SHIFT, WEIN BRIDGE
AIM:
To verify oscillator circuits- RC Phase Shift and Wein Bridge oscillators using Op-Amp and
calculate its frequency of oscillation.
IC 741 Op-Amp
Resistors and Capacitors
IC Trainer Kit
THEORY:
generate the triangular, sawtooth and other non-sinusoidal waveforms. Sinusoidal oscillators
by many circuits.
Sine wave Generator

Fig.1 shows an RC Phase Shift oscillator. The op-amp provides a phase shift of 180 degrees as it
is used in the inverting mode. An additional phase shift of 180 degrees is provided by the
feedback RC network.
136
RC Phase Shift Oscillator:
RC phase-shift oscillator is a linear electronic oscillator circuit that produces a sine wave output.
It consists of an inverting amplifier element such as a transistor or op-amp with its output fed
back to its input through a phase-shift network consisting of resistors and capacitors in a ladder
network. Each of the three RC networks in the feedback loop can provide a maximum phase shift
approaching 90 degrees. Oscillation occurs at the frequency where the total phase shift through
the three RC network is 180 degrees. Inversion output at the output of op-amp itself produces the
additional 180 degree to meet the requirement for oscillation of 360 degrees (or zero degree)
phase shift around the feedback loop.
DESIGN:
The attenuation B of the three section RC feedback network is 1 29 B  To meet the greater than
unity loop gain requirement, the closed loop voltage gain of op-amp must be greater than 29.
Given frequency, f = 1 kHz. We have
Wein Bridge Oscillator:

Wien bridge oscillator is an audio frequency sine wave oscillator of high stability and simplicity.
The feedback signal in this circuit is connected to the non-inverting input terminal so that the op-
amp is working as a non-inverting amplifier. Therefore, the feedback network need not provide
any phase shift. The circuit can be viewed as a Wien bridge with a series combination of R1 and
C1 in one arm and parallel combination of R2 and C2 in the adjoining arm. Resistors R3 and R4
are connected in the remaining two arms. The condition of zero phase shift around the circuit is
achieved by balancing the bridge. The series and parallel combination of RC network form a
lead-lag circuit. At high frequencies, the reactance of capacitor C1 and C2 approaches zero. This
causes C1 and C2 appears short. Here, capacitor C2 shorts the resistor R2. Hence, the output
voltage Vo will be zero since output is taken across R2 and C2 combination. So, at high
frequencies, circuit acts as a 'lag circuit'. At low frequencies, both capacitors act as open because
capacitor offers very high reactance. Again, output voltage will be zero because the input signal
is dropped across the R1 and C1 combination. Here, the circuit acts like a 'lead circuit'. But at
one particular frequency between the two extremes, the output voltage reaches to the maximum
137
value. At this frequency only, resistance value becomes equal to capacitive reactance and gives
maximum output. Hence, this frequency is known as oscillating frequency (f).
CIRCUIT DIAGRAM:
Fig.1 RC Phase Shift Oscillator using IC 741 Op-Amp
Fig-2: Wein Bridge Oscillator using IC 741 Op-Amp
138
PROCEDURE:
2. Connect the output terminals to CRO and observe sine wave output and plot the graph.
4. Repeat the above 3 steps for figure 2.
OBSERVATIONS:
S.No Amplitude Theoretical Practical Frequency

Frequency
S.No Amplitude Theoretical Practical Frequency

Frequency
CALCULATIONS:
139
MODEL GRAPH:
RESULT:
The amplitude of the sine wave form generated by RC Phase shift oscillator is found to be
_____.
The amplitude of the sine wave form generated by Wein Bridge oscillator is found to be ______.
The time period of the sine wave form generated by RC Phase shift oscillator is found to be ___.
The time period of the sine wave form generated by Wein Bridge oscillator is found to be _____.
REVIEW QUESTIONS:
1. Write about sinusoidal wave generator.
2. Equation for frequency of sine wave in RC Phase Shift oscillator is ____.
3. Write some applications of function generator.
4. Equation for frequency of sine wave in Wein Bridge oscillator is ____.
140
Expt-9
IC 555 TIMER – MONOSTABLE MULTIVIBRATOR
AIM:- To design a Monostable Multivibrator using IC 555 Timer and to measure its pulse width.

1. NE 555 IC.
2. Resistors and Capacitors
3. IC Trainer Kit
4. CRO 25 MHz Dual channels.
5. Connecting wires and probes
THEORY:
Monostable multivibrator often called a one shot multivibrator is a pulse generating circuit in
which the duration of this pulse is determined by the RC network connected externally to the 555
timer. Monostable - has only ONE stable state and if triggered externally, it returns back to its
first stable state. In a stable or standby state, the output of the circuit is approximately zero or a
logic-low level. When external trigger pulse is applied output is forced to go high ( VCC). The
time for which output remains high is determined by the external RC network connected to the
timer. At the end of the timing interval, the output automatically reverts back to its logic-low
stable state. The output stays low until trigger pulse is again applied. Then the cycle repeats. The
monostable circuit has only one stable state (output low) hence the name monostable.
IC 555 Timer is connected as a monostable multivibrator as shown in figure-1.
Initially when the circuit is in the stable state i.e, when the output is low, transistor Q in IC 555 is
ON and the capacitor C is shorted out to ground. Upon the application of a negative trigger pulse
to pin 2, transistor Q is turned OFF, which releases the short circuit across the external capacitor
C and drives the output high. The capacitor C now starts charging up towards VCC through R.
When the voltage across the capacitor equals 2/3 VCC, the upper comparator‟s (see schematics
of IC 555) output switches from low to high, which in turn drives the output to its low state via
the output of the flip-flop. At the same time the output of the flip-flop turns transistor Q ON and
hence the capacitor C rapidly discharges through the transistor. The output of the monostable
remains low until a trigger pulse is again applied. Then the cycle repeats. The pulse width of the
141
trigger input must be smaller than the expected pulse width of the output waveform. Also the
trigger pulse must be a negative going input signal with amplitude larger than 1/3 VCC.
DESIGN PROCEDURE:
Voltage across C is given by
Vc=Vcc(1-e –T/RC) Vc=(2/3)Vcc at t=tp Therefore (2/3)Vcc = Vcc(1-e –tp/RC)
tp=RC log(1/3)=1.1 RC tp=1.1 RAC Seconds
CIRCUIT DIAGRAM:
Fig-1: IC 555 Timer in Monostable Configuration

PROCEDURE:
1. Configure the circuit as per the circuit diagram.
2. Apply the trigger input to the monostable multivibrator from the output of Astable
multivibrator.
3. Observe the output on CRO. Determine the value of pulse duration from your observations
and compare with the theoretical values.
OBSERVATIONS:
(THEOROTICAL) (PRACTICAL)
RC COMPONENTS Designed O/P waveform results Designed O/P waveform
results
RA C tp f tp f
142
MODEL GRAPH:
Fig-2: Model Waveforms of IC 555 in Monostable configuration
RESULT:
The pulse width of the monostable multivibrator using IC 555 is found to be____.
Hence verified the operation of monostable multivibrator using IC 555 timer.
REVIEW QUESTIONS:
1. Design a 555 monostable multivibrator to generate 10sec pulse width having Vcc =12V.
2. Why the above timer IC is called 555 Timer?
143
Expt-10
IC 555 TIMER – ASTABLE MULTIVIBRATOR
AIM:- To design an Astable Multivibrator using IC 555 Timer, find its frequency of operation
and duty cycle.
EXPERIMENT EQUIPMENT:
1. NE 555 IC.
2. Resistors and Capacitors
3. IC Trainer Kit
4. CRO 25 MHz Dual channels.
THEORY:
Astable multivibrator often called a free running multivibrator is a pulse generating circuit in
which the duration of this pulse is determined by the RC network connected externally to the 555
timer. These circuits are not stable in any state and switch outputs after predetermined time
periods. The result of this is that the output is a continuous square/rectangular wave.
Referring to the figure-2 of a rectangular waveform, the time period of the pulse is defined as T
and duration of the pulse (ON time) is τ. Duty cycle can be defined as the On time/Period that is,
τ/T in the above figure. Obviously, a duty cycle of 50% will yield a square wave.
The key external component of the Astable timer is the capacitor. An astable multivibrator can
be designed as shown in the circuit diagram (with typical component values) using IC 555, for a
duty cycle of more than 50%. The corresponding voltage across the capacitor and voltage at
output is also shown. The astable function is achieved by charging/discharging a capacitor
through resistors connected, respectively, either to VCC or GND. Switching between the
charging and discharging modes is handled by resistor divider R1-R3, two Comparators, and an
RS Flip-Flop in IC 555. The upper or lower comparator simply generates a positive pulse if Vc
goes above 2/3 VCC or below 1/3 VCC. And these positive pulses either SET or RESET the Q
output.
144
Thus, while designing these circuits following parameters need to be determined:
1.Frequency (or the time period) of the wave.
2. The duty cycle of the wave.
DESIGN PROCEDURE:
The time for charging C from 1/3 to 2/3 VCC, i.e, ON Time = 0.693 (RA+ RB). C
The time for discharging C from 2/3 to 1/3 Vcc, i.e. OFF Time = 0.693 RB. C
To get the total oscillation period, just add the two:
Tosc= 0.693·(RA+RB)·C + 0.693·(RB)·C = 0.693 · (RA+ 2·RB) · C
Thus, fosc= 1/ Tosc = 1.44/( RA+ 2·RB).C
Duty cycle = RA+RB/ RA+ 2·RB
CIRCUIT DIAGRAM:
Fig-1: IC 555 Timer as an Astable multivibrator
PROCEDURE:
1. Configure the circuit as per the circuit diagram.
2. Observe the output on CRO.
3. Compute the expected values of Tosc, fosc and duty cycle (%).
145
OBSERVATIONS:
(THEOROTICAL) (PRACTICAL)
R,C COMPONENTS Designed O/P waveform Designed O/P waveform
results results
RA RB C Tosc fosc Duty cycle Tos fosc Duty cycle
c
MODEL GRAPH:
Fig-2: Model output waveforms of IC 555 in Astable Configuration

RESULT:
The frequency of wave generated using IC 555 in Astable configuration is found to be ______.
The % dutycycle of wave generated using IC 555 in Astable configuration is found to be ______.
Verified the operation of astable multivibrator using IC 555 timer.
REVIEW QUESTIONS:
1. Design a 555 astable multivibrator to generate 10 kHZ frequency having VCC=12V.
2. How to obtain the duty cycle of less than 50%?
3. Why the above timer IC is called 555 Timer?
146
Expt-11
4 BIT DAC USING OP-AMP
AIM:
To construct a 4-bit R–2R ladder type D/A converter using IC 741 Op-
Amp. Plot the transfer characteristics, that is, binary input Vs output voltage. Calculate its
resolution.

IC 741 Op-Amp
Resistors (1Kohms, 2.2Kohms)
Trainer Kit
Probes and Connecting wires
THEORY:
Most of the real world physical quantities such as voltage current temperature pressure are
available in analog form. It is very difficult to process the signal in analog form hence ADC and
DAC are used. The DAC is to convert digital signal into analog and hence the functioning of
DAC is exactly opposite to that of ADC. The DAC is usually operated at the same frequency as
the ADC. The output of the DAC is commonly staircase. This staircase like digital output is
passed through a smoothing filter to reduce the effect of quantization noise. There are three types
of DAC techniques (i) Weighted resistor DAC (ii) R-2R ladder. (iii) Inverted R-2R ladder. Wide
range of resistors is required in binary weighted resistor type DAC. This can be avoided by using
R-2R ladder type DAC where only two values of resistors are required it is well suited for
integrated circuit realization.
147
CIRCUIT DIAGRAM:
Fig-1: 4-bit R-2R Ladder DAC using IC 741 Op-Amp
PROCEDURE:
1. Set up the circuit shown in Fig.
2. Measure the output voltage for all binary input states (0000 to 1111) and plot a graph of
binary inputs Vs output voltage.
3. Measure the size of each step and hence calculate resolution
OBSERVATIONS:
R-2R LADDER DAC

D3 D2 D1 D0
THEORITICAL(V) PRACTICAL(V)
148
CALCULATIONS:
VO = Vref [D3/R3+D2/R2+D1/R1+D0/R0]
Resolution (in volts) = VFS / (2n –1) = 1 LSB increment

MODEL GRAPH:
Fig-2: Model output graph for 3-Bit DAC

RESULT:
The obtained output voltage of DAC =__________V
The 4 bit DAC is constructed and Vo is calculated for different data bits and practical Vo is
verified with theoretical values and found to be nearly equal.
REVIEW QUESTIONS:
1. Classify DAC on the basis of their output?
2. Name the essential parts of a DAC?
3. What is meant by accuracy of DAC?
4. How many resistors are required in 12 bit weighted resistor DAC?
5. Why is an inverted R-2R ladder network DAC is better than R-2R ladder DAC?
6. Define resolution.
7. Define linearity.
8. Define step size.
149
Expt-12
VOLTAGE REGULATOR USING IC 723
AIM: To construct and study low and high voltage regulators using IC 723 and also to find the
% regulation of low and high voltage regulators.
S.N
NAME OF TYPE RANGE QUANTITY
O
EQUIPMENT/COMPONENT
1 Regulator IC IC 723 - 1
2 Potentiometer - 10KOhm 1
3 RESISTOR - 2.2 Kohm 2
4 RESISTOR - 1 Kohm 1
5 CAPACITOR - 0.1uf 1
CAPACITOR - 100pf 1
7 CATHODE RAY OSCILLOSCOPE - (0-20)MHz 1
8 PROBES AND CONNECTING - -

WIRES
9. Digital Multimeter 1
THEORY:
The IC 723 is a monolithic integrated circuit voltage regulator featuring high ripple rejection,
excellent input and load regulation & excellent temperature stability etc. It consists of a
temperature compensating reference voltage amplifier, an error amplifier, 150mA output
transistor and an adjustable output current limiter. The basic low voltage regulator type 723
circuit is shown in figure.1.The unregulated input voltage is 24V and the regulated output
voltage is varied from 0.2V to 7.5V by varying the value of R2. A stabilizing capacitor (C1) of
150
100pF is connected between frequency compensation terminal and inverting (INV) terminal.
External NPN pass transistor is added to the basic 723-regulator circuit to increase its load
current capability. For intermediate output voltages the following formula can be used
The basic high voltage regulator type 723 circuit is shown in figure.2.The output voltage can be
regulated from 7 to 37Volts for an input voltage range from 9.5 to 40Volts. For intermediate
output voltages the following formula can be used
CIRCUIT DIAGRAM:
Low voltage Regulator:
Fig-1: Low Voltage Regulator using IC 723

High Voltage Regulator:
151
Fig-2: High Voltage Regulator using IC 723
PROCEDURE:
LOW VOLTAGE REGULATOR
1. Connect the circuit diagram as shown in figure.1.
2. Apply the unregulated voltage to the 723 IC and note down the regulator output voltage.
3.Calculate the line regulation of the regulator using the formula Line Regulation = ΔVO / ΔVi --
_________ (3)
4. By varying 10K potentiometer at the load section and note down the regulator output voltage.
5. Calculate the Load regulation of the regulator using the formula Load Regulation ==ΔVO /
ΔIL _______ (4)
6. Also calculate the Percentage of load regulation using the formula 1 2 1 *100 E E E −
_______ (5) Where E1 = Output voltage without load & E2 = Out put voltage with load.
HIGH VOLTAGE REGULATOR
1. Connect the circuit diagram as shown in figure.2.
2. Apply the unregulated voltage to the 723 IC and note down the regulator output voltage.
3. Calculate the line regulation of the regulator using the formula Line Regulation = ΔVO / ΔVi -
________ (6)
4. By varying 10K potentiometer at the load section and note down the regulator output voltage.
5. Calculate the Load regulation of the regulator using the formula Load Regulation = ΔVO /
ΔIL ------------ (7)
6. Also calculate the Percentage of load regulation using the formula 1 2 1 *100 E E E −
______(8) Where E1 = Output voltage without load & E2 = Output voltage with load.
152
OBSERVATION TABLE:
FOR LOW VOLTAGE REGULATOR
LINE REGULATION: (RL is constant)
S.No Unregulated DC input, Vi in Volts Regulated DC output, VO in Volts
LOAD REGULATION: (Vi is Constant)

S.No Load Resistance, RL in Ohms Regulated DC output, VO in Volts
FOR HIGH VOLTAGE REGULATOR

LINE REGULATION: (RL is constant)
S.No Unregulated DC input, Vi in Volts Regulated DC output, VO in Volts
LOAD REGULATION: (Vi is Constant)

S.No Load Resistance, RL in Ohms Regulated DC output, VO in Volts
153
MODEL GRAPH:
Fig-3: Model graph for Line Regulation
Fig-4: Model Graph for Load Regulation

RESULT:
1. The line regulation of low voltage regulator using IC 723 is found to be ________.
2. The load regulation of low voltage regulator using IC723 is found to be _________.
3. The line regulation of high voltage regulator using IC 723 is found to be ________.
4. The load regulation of high voltage regulator using IC723 is found to be _________.
Low and high voltage regulators using IC 723 were constructed and studied. Also the line and
load regulations of the low & high voltage regulators are verified.
154
REVIEW QUESTIONS:
1. Design a high voltage and low voltage regulator using IC 723.
2. Design a series regulated power supply to provide a nominal output voltage of 20 V, at IL =
1.2 A. Given Vi = 40 ± 5 V, r0 = 15 Ω, Rz = 10 Ω, Iz = 15 mA, IC2 = 12 mA, hie2 = 600 Ω.
hfe2 = 300. IL = 10 mA.
3. Design a regulated power supply using 3-terminal I.C. to give V0 = + 5 V. I0 = 0.6 A, Vin =
12 VDC, TA = 60°C.
4. Design a power supply using 3-terminal I.C. regulator to give + 5 V output at 400 μA at
30°C.
5. 5. Using I.Cs, design a regulated power supply to give output voltage, which is adjustable
from 1.2 V to 12 V. IL is to be 0.5 A, TA = 35°C.
IC 741 DATA SHEET
155
156
NE 555 IC DATA SHEET
157
LM 723 IC DATA SHEET
Lab Manual Prepared by Anupama Rani N, Assistant Professor, Dept. of ECE, SNIST,
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DIGITAL COMMUNICATIONS
LAB MANUAL
III Year – II Semester ECE
PREPARED BY
Dr.S.P.V.Subba Rao
Professor, Dept. of ECE
&
Mr.R Madhusudhan Goud
Assistant Professor.
Dept. of ECE
Department of Electronics and Communication Engineering

SREENIDHI INSTITUTE OF SCIENCE AND TECHNOLOGY
(An Autonomous Institution)
Yamnampet, Ghatkesar, Hyderabad-501 301
July 2020--21
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To emerge as a leading centre for students and faculty in their pursuits of professional excellence
in the fields of Electronics and Communication Engineering by making use of current Scientific
and Technological advancements, with focus on human values, professional ethics and social
responsibility.

Training students in the basic core and application oriented subjects of Electronics and
Communication engineering with due focus on multi-disciplinary areas.
Establishing liaison with relevant industries, R&D organizations and renowned academia for
exposure to practical R&D aspects of technology.
Inculcating team work, leadership, professional ethics and other skills such as effective
communication, logical reasoning, career goal setting, liberal use of modern tools, familiarity
with IPR to make students globally competent in employment as well as entrepreneurship.
Promoting scientific temper and research culture in the graduates towards lifelong learning to
produce useful research outcomes
PEO – I. To apply the knowledge of mathematics, science and engineering fundamentals to find the
solution of complex engineering problems concerning societal, health, safety, cultural and environmental
issues.
disciplinary domains leading to design of novel products using modern tools and to promote skills
in project management, entrepreneurship and IPR.
Attainment B. Tech (ECE) Programme Outcomes

Engineering Graduates will be able to:
1. Engineering knowledge: Apply the knowledge of mathematics, science,

engineering fundamentals, and an engineering specialization to the solution of
complex engineering problems.
2. Problem analysis: Identify, formulate, review research literature, and
analyze complex engineering problems reaching substantiated conclusions
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using first principles of mathematics, natural sciences, and engineering
sciences.
3. Design/development of solutions: Design solutions for complex
engineering problems and design system components or processes that meet
the specified needs with appropriate consideration for the public health and
safety, and the cultural, societal, and environmental considerations.
4. Conduct investigations of complex problems: Use research-based
knowledge and research methods including design of experiments, analysis and
interpretation of data, and synthesis of the information to provide valid
conclusions.
5. Modern tool usage: Create, select, and apply appropriate techniques,
resources, and modern engineering and IT tools including prediction and
modeling to complex engineering activities with an understanding of the
limitations.
6. The engineer and society: Apply reasoning informed by the contextual
knowledge to assess societal, health, safety, legal and cultural issues and the
consequent responsibilities relevant to the professional engineering practice.
7. Environment and sustainability: Understand the impact of the
professional engineering solutions in societal and environmental contexts, and
demonstrate the knowledge of, and need for sustainable development.
8. Ethics: Apply ethical principles and commit to professional ethics and
responsibilities and norms of the engineering practice.
9. Individual and team work: Function effectively as an individual, and as a
member or leader in diverse teams, and in multidisciplinary settings.
10. Communication: Communicate effectively on complex engineering
activities with the engineering community and with society at large
11. Project management and finance: Demonstrate knowledge and
understanding of the engineering and management principles and apply these
to one’s own work
12. Life-long learning: Recognize the need for, and have the preparation and
ability to engage in independent and life-long learning in the broadest
context of technological change.
Expected level of Attainment of B. Tech (ECE) Program Specific Outcomes (PSOs)
PSO1: Should be able to gain the in-depth knowledge in core subjects to

identify, formulate, analyze, and suggest viable solutions to the real-life
problems in the field of electronics and communication engineering.
PSO2: Should have the capability to apply modern design tools to analyze and
design subsystems/processes for a variety of applications in the allied fields of
electronics and communications.
PSO3: Should possess good interpersonal skills, and also an ability to work as a
team member as well as team leader with good professional ethics, and also to
become a life-long learner in the context of technological developments.
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Year/Sem Sub. Subject Name L T P/D C
Code
III-I 7C577 DIGITAL COMMUNICATIONS LAB - - 4 2
Prerequisites: SS, PTSP, AC, BS Lab
Course Objectives:
 To perform laboratory experiments on various digital modulation techniques and
measure the performance parameters using both Hardware and MatLab.
CO1 Understand the Practical concepts of converting analog signal to digital signal by
using PCM, DM, ADM circuits of Modulator and demodulator.
CO2 Design and analyze ASK, FSK, PSK, DPSK, QPSK modulators and demodulators. .
CO3 Design and Evaluate the performances of Linear Block code.
CO4 Understand the Practical concepts of Digital modulation techniques DPSK and
QPSK.
CO5 Design of modulator and demodulator using MAT Lab Simulation Tool.
CO6 Design and implementation of Compander and Data Scrambler/Descrambler using
Matlab.

A b c d e f g h i j k l m
CO1 3 2
CO2 3 2
CO3 3 2
CO4 3 2
CO5 3 2
CO6 3 2
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Part A: LIST OF HARDWARE EXPERIMENTS (Any EIGHT)
1. Sampling Theorem, Time Division Multiplexing – Verification

2. PCM/DPCM
3. Delta Modulation/ Adaptive Delta Modulation.
4. Line Coding Techniques
5. Amplitude Shift Keying
6. Frequency Shift Keying
7. Phase Shift Keying
8. Differential Phase Shift Keying
9. Quadrature Phase Shift Keying
Part B: List of experiments to be simulated using MATLAB (Any

FOUR)
1. µ-LAW Companding
2. DPCM Encoding and Decoding
3. Scrambling/Descramblng
4. Design of ASK, PSK, FSK. and QPSK MATLAB
5. Error Control Coding using Linear Block Codes
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III B.Tech II Sem ECE
DIGITAL COMMUNICATIONS LAB
List of Experiments:
Cycle-I
1. Sampling theorem - Verification
2. Time Division Multiplexing and Demultiplexing
3. Pulse Code modulation and demodulation
4. Differential Pulse Code modulation and demodulation
5. Delta modulation and demodulation
6. Adaptive Delta Modulation and Demodulation
Cycle-II
7. Line coding Techniques
8. Amplitude Shift Keying
9. Frequency Shift Keying
10. Phase Shift Keying
11. Differential Phase Shift Keying
12. Quadrature Phase Shift Keying
MATLAB Experiments
1. µ-LAW Companding
2. DPCM Encoding and Decoding
3. Delta modulation
4. Eye diagram measurements on simulated signals.
5. Design of ASK, PSK,FSK. and QPSK MATLAB
6. Error Control Coding Using MATLAB
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SAMPLING THEOREM - VERIFICATION
AIM: 1.To sample the given input signal at different sampling rates and reconstruct the
original signal by passing through a low pass filter.
2.To calculate the Nyquist rate .
3.To calculate the bandwidth of the sampled signal.
APPARATUS:
1. Sampling and reconstructing trainer kit.
2. C.R.O
3. Connecting wires & Probes
THEORY:
Pulse Modulation is used to Transmit analog information. In this system continuous
waveforms are sampled at regular intervals. Information regarding the signal is
transmitted only at the sampling times together with synchronizing signals.At the
receiving end, the original waveforms may be reconstituted from the information
regarding the samples.
Sampling Theorem Statement:
A band limited signal of finite energy which has no frequency components higher than
fm Hz, is completely described by specifying the values of the signal at instants of time
separated by ½ fm seconds. The sampling theorem states that, if the sampling rate in
any pulse modulation system exceeds twice the maximum signal frequency, the original
signal can be reconstructed in the receiver with minimum distortion. Fs > 2fm is called
Nyquist rate.
Where fs – sampling frequency
Fm – Modulation signal frequency.
If we reduce the sampling frequency fs less than fm, the side bands and the information
signal will overlap and we cannot recover the information signal simply by low pass
filter. This phenomenon is called fold over distortion or aliasing.
There are two methods of sampling. (1) Natural sampling (2) Flat top sampling.
Sample & Hold circuit holds the sample value until the next sample is taken.
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Sample & Hold technique is used to maintain reasonable pulse energy. The duty cycle
of a signal is defined as the ratio of Pulse duration to the Pulse repetition period. The
duty cycle of 50% is desirous taking the efficiency into account.
CIRCUIT DIAGRAM:
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PROCEDURE:
2. An input of continuous-time signal will be given to the input terminal of
the trainer.
3. The discrete-time signals are observed at the sampled output, and
holding outputs are observed at Hold output terminal.
4. By selecting of different sampling frequencies sampling outputs are
observed.
5. By giving this sampled output to BUTTER WORTH LOW PASS
FILTER we can observe the reconstructed output i.e. nothing but a
continuous-time signal.
OUTPUT WAVE FORMS:
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DEMODULATED OUTPUT
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PRECAUTIONS:
1. Connections must be tight.
2. Waveforms must be note carefully
RESULTS: 1. sampling theorem is verified.

2. Nyquist rate is calculated.
3. Bandwidth of the sampled signal is calculated.
VIVA QUESTIONS:
1. Give the statement of sampling theorem?
2. What do you mean by Nyquist interval?
3. What is meant by Guard band?
4. What is meant by Aperture effect?
5. Draw the sampled output of an analog signal in frequency -domain?
6. What is meant by Aliasing effect?
7. Which filters are used to attenuate the aliasing effect?
8. What are the different types of sampling techniques?
9. What is meant by Nyquist rate?
10. Define sampling theorem in time- domain?
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2. TIME DIVISION MULTIPLEXING AND DEMULTIPLEXING
AIM: 1.To transmit a multiplexed output of different frequency message signals through
a single channel using TDM system and recover back the original message signals
through a demultiplexer at receiver end.
2. To calculate the bandwidth of the Multiplexed signal.
APPARATUS:
1. TDM trainer kit
2. CRO
3. Patch cards
4. Connecting wires
THEORY:
Time division multiplexing is a technique used for transmitting several analog
message signals over a single communication channel, by dividing the time frame in to
number of slots, i.e. one slot for each signal. Here there are four input signals; all are
band limited to fx by the input Low pass filters, and all these are sequentially sampled at
the transmitter by using a rotary switch i.e. commutator. This commutator makes fs
revolutions per second and extracts one sample from each input during each revolution.
The out put of the switch is a PAM wave form containing samples of the input signals
periodically interfaced with time.
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TDMA slots and frame
CIRCUIT DIAGRAM:
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Example1:Four 1-Kbps connections are multiplexed together. A unit is 1 bit. Find
(a) the duration of 1 bit before multiplexing, (b) the transmission rate of the link,
(c) the duration of a time slot, and (d) the duration of a frame?
a) The duration of 1 bit is 1/1 Kbps, or 0.001 s (1 ms).
b) The rate of the link is 4 Kbps.
c) The duration of each time slot 1/4 ms or 250 μs.
d) The duration of a frame 1 ms.
Example2:We have four sources, each creating 250 characters per second. If
the interleaved unit is a character and 1 synchronizing bit is added to each frame,
find (a) the data rate of each source, (b) the duration of each character in each
source, (c) the frame rate, (d) the duration of each frame, (e) the number of bits
in each frame, and (f) the data rate of the link.
1. The data rate of each source is 2000 bps = 2 Kbps.
2. The duration of a character is 1/250 s, or 4 ms.
3. The link needs to send 250 frames per second.
4. The duration of each frame is 1/250 s, or 4 ms.
5. Each frame is 4 x 8 + 1 = 33 bits.
6. The data rate of the link is 250 x 33, or 8250 bps
Applications:
T-1 Line for Multiplexing Telephone Lines.
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T-1 Frame
Structure
PROCEDURE:
(AT TRANSMITTING BLOCK)

1. Place the duty cycle controlled switch in position-5
2. Turn the potentiometer in function generator block fully in clock wise
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3. The following connections are made
 250Hz to channel-o
 500Hz to channel-1
 1kHz to channel-2
 2kHz to channel -3
4. The external triggering will be given to the channel-0 terminal.
5. Then multiplexed output is observed across Tx output terminal.
6. Vary the amplitude of input sine wave by varying the potentiometers in
function generator block to indicate which sample belongs to which output
channel and then the outputs are plotted on the graph.
(AT RECEIVER BLOCK)

1. The following connections are made
 Tx output to Rx output
 Tx clock to Rx clock
 Tx t0 to Rx t0
2. Above connections are made sure that the Tx clock signal is used by the Rx
to Synchronize its activity
3. Then de-multiplexed original message signals are available across the low
pass filters at receiver block.
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OUTPUT WAVEFORMS: (Transmitting Signals)
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DEMULTIPLEXED OUTPUT:
176
RESULTS:
1.Hence four message signals are transmitted at a time through a single communication
channel, using TDM system and again de-multiplex these four message signals at
receiver is observed.
2. Bandwidth of the Multiplexed signal is calculated.
VIVA QUESTIONS:
1. What is meant by multiplexing technique and what are the different types of
Multiplexers?
2. Briefly explain about TDM&FDM?
3. What is the transmission band width of a PAM/TDM signal?
4. Define crosstalk effect in PAM/TDM system?
5. What are the advantages of TDM system?
6. What are major differences between TDM&FDM?
7. Give the value of Ts in TDM system?
8. What are the applications of TDM system and give some example?
9. What is meant by signal overlapping?
10. Which type of modulation technique will be used in TDM?
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3. PULSE CODE MODULATION & DEMODULATION
AIM: 1.To convert an analog signal into a pulse digital signal using PCM system and to
convert the digital signal into analog signal using PCM demodulation system.
2.To find the bandwidth of PCM signal
3. To calculate Signal to Noise ratio of PCM signal
APPARATUS:
1. PCM transmitter trainer.
2. PCM receiver trainer.
3. CRO and connecting wires.
THEORY:
In the PCM communication system, the input analog signal is sampled and these
samples are subjected to the operation of quantization. The quantized samples are
applied to an encoder. The encoder responds to each such a sample by generation
unique and identifiable binary pulse. The combination of quantize and encoder is called
analog to digital converter. It accepts analog signal and replaces it with a successive
code symbol, each symbol consists of a train of pulses in which the each pulse
represents a digit in arithmetic system.
When this digitally encoded signal arrives at the receiver, the first operation to
be performed is separation of noise which has been added during transmission along
the channel. It is possible because of quantization of the signal for each pulse interval; it
has to determine which of many possible values has been received.
Pulse Code Modulation (PCM) is different from Amplitude Modulation (AM) and
Frequency Modulation (FM) because those two are continuous forms of modulation.
PCM is used to convert analog signals into binary form. In the absence of noise and
distortion it is possible to completely recover a continuous analog modulated signals.
But in real time they suffer from transmission distortion and noise to an appreciable
extent. In the PCM system, groups of pulses or codes are transmitted which represent
binary numbers corresponding to modulating signal voltage levels. Recovery of the
transmitter information does not depend on the height, width, or energy content of the
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individual pulses, but only on their presence or absence. Since it is relatively easy to
recover pulses under these conditions, even in the presence of large amounts of noise
and distortion, PCM systems tend to be very immune to interference and noise.
Regeneration of the pulse reroute is also relatively easy, resulting in system that
produces excellent result for long distance communication.
PCM ENCODING:
The encoding process generates a binary code number corresponding to modulating
signal voltage level to be transmitted for each sampling interval. Any one of the codes
like binary, ASCII etc, may be used as it provides a sufficient number of different
symbols to represent all of the levels to be transmitted. Ordinary binary number will
contain a train of‟1‟ and „0‟ pulses with a total of log2N pulses in each number. (N is no
of levels in the full range). This system is very economical to realize because it
corresponds exactly to the process of analog – to – digital (A/D) conversion.
QUANTIZATION:
The 1st step in the PCM system is to quantize the modulating signal. The modulating
signal can assume an infinite no. of different level between the two limit values, which
define the range of the signal. In PCM a coded no is transmitted for each level sampled
in the modulating signal. If the exact no corresponding to the exact voltage were to be
transmitted for every sample, an infinitely large no of different code symbols would be
needed. Quantization has the effect of reducing this infinite no of levels to a relatively
small number, which can be coded without difficulty.
In the quantization process, the total range of the modulating signal is divided into a no
of small sub ranges. The number will depend on the nature of the modulating signal and
will form as few as 8 to as many as 128 levels. A number that is an integer power of two
is usually chosen because of the ease of generating binary codes. The result is stepped
waveform, which follows the counter of the original modulating signal with each step
synchronized to the sampling period.
The quantized staircase waveform is an approximation to the original waveform. The
difference between the two-wave form amounts to “noise” added to the signal by the
quantizing circuit. The mean square quantization noise voltage has a value of
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E2np = S2/12 Where S is the voltage of each step. As a result the number of
quantization levels must be kept high in order to keep the quantization noise below
some acceptable limit given by the power signal-to-noise ratio, which is the ratio of
average noise power.
DECODING:
The decoding process reshapes the incoming pulses and eliminates most of the
transmission noise. A serial to parallel circuit passes the bits in parallel groups to a
digital to analog converter (D/A) for decoding. Thus decoded signal passes through a
sample and hold amplifier, which maintains the pulse level for the duration of the
sampling period, recreating the staircase waveform approximation of the modulation
signal. A low-pass filter may be used to reduce the quantization noise.
BLOCK DIAGRAM:
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OUTPUT WAVEFORMS:
DC SIGNAL
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AC SIGNAL
PROCEDURE:
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1. The two inputs of function generator are connected to channel -0 and
channel-1 simultaneously that is DC1 output to channel -0 and DC2 to
channel-1.
2. With the help of oscillator DC1 output is adjusted to 0 volts.
3. Transmitter and receiver are connected by the synchronization of clock
pulses and by connecting ground transmitter to ground receiver.
4. The transmitter is connected to the input of receiver to go the original signal at
the receiver output.
5. After connection is made the inputs channel 1 and channel 0 are noted. The
sampled output of bit channels are taken by connecting DC1 output to
channel 0 and DC2 output to channel-1.
6. The phase shift of a channel can be obtained by comparing the input and
output of channels at the transmitter block.
7. Thus the output of transmitter can be noted down and input of receiver is
similar to that.
8. The receiver output signals are noted down at channel 0 and channel 1 of the
receiver block.
RESULTS:1. Analog signal is converted into a pulse digital signal using PCM system
and digital signal into analog signal using PCM demodulation system
2.Bandwidth of PCM signal is calculated.
3. Signal to Noise ratio of PCM signal is calculated.
VIVA QUESTIONS:
1. What is bit synchronization & frame synchronization?
2. Explain block diagram of PCM?
3. What is the different error control coding technique?
4. What is resolution in ADC?
5. For arbitrary fixed reference voltage write the table of 4-bit ADC?
6. The accuracy of any digital reproduction of an analog signal depends on what?
7. If sample requires at least 12 levels of precision (+0 to +5 and –0 to –5). How many bits
should be sent for each sample? use one bit form sign.
8. What is the formula for bit rate in PCM?
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9. If we want to digitize human voice (4KHz B.W), what is the bit rate assuming 8 bits/sample?
10. What is the sampling rate for PCM if the frequency ranges from 1000Hz to 4000Hz?
11. If the interval between two samples in a digital signal is 125 micro seconds. What is the
sampling rate?
12. What is the expression for transmission bandwidth in a PCM system?
13. What is the expression for quantization noise /error in PCM system?
14. What are the applications of PCM?
15. What are the advantages of the PCM?
16. What are the disadvantages of PCM?
4.DIFFERENTIAL PULSE CODE MODULATION

AIM: 1.To generate DPCM wave and to demodulate it.
2.To find the bandwidth of DPCM signal
3. To calculate Signal to Noise ratio of PCM signal
APPARATUS: DPCM Trainer kit,

Power chords,
20 MHz Dual trace CRO,
Power supply.
THEORY:
Differential PCM is quite similar to ordinary PCM. However, each word in this system
indicates the difference in amplitude, positive or negative, between this sample and the
previous sample. Thus the relative value of each sample is indicated rather than the
absolute value as in normal PCM. In this each amplitude is related to the previous
amplitude, so that large variations from one sample to the next are unlikely. This being
the case, it would take fewer bits to indicate to indicate the size of the amplitude change
than the absolute amplitude, and so a smaller bandwidth would be required for the
transmission. The differential PCM system has not found wide acceptance because
complications in the encoding and decoding process appear to out weigh advantages
gained.
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According to the Nyquist sampling criterion, a signal must be sampled at a sampling
rate that is at least twice the highest frequency in the signal to be able to reconstruct it
without aliasing. The samples of a signal that is sampled at that rate or close to
generally have little correlation between each other (knowing a sample does not give
much information about the next sample). However, when a signal is highly
oversampled (sampled at several times the Nyquist rate, the signal does not change a
lot between from one sample to another. Consider, for example, a sine function that is
sampled at the Nyquist rate. Consecutive samples of this signal may alternate over the
whole range of amplitudes from –1 and 1. However, when this signal is sampled at a
rate that is 100 times the Nyquist rate (sampling period is 1/100 of the sampling period
in the previous case), consecutive samples will change a little from each other. This fact
can be used to improve the performance of quantizers significantly by quantizing a
signal that is the difference between consecutive samples instead of quantizing the
original signal. This will result in
either requiring a quantizer with much less number of bits (less information to transmit)
or a quantizer with the same number of bits but much smaller quantization intervals
(less quantization noise and much higher SNR).
Consider a signal x(t) that is sampled to obtain the samples x(kTs), where Ts is the
sampling period and k is an integer representing the sample number. For simplicity, the
samples can be written in the form x[k], where the sample period Ts is implied. Assume
that the signal x(t) is sampled at a very high sampling rate. We can define d[k] to be the
difference between the present sample of a signal and the previous sample, or
Now this signal d[k] can be quantized instead of x[k] to give the quantized signal dq[k].
As mentioned above, for signals x(t) that are sampled at a rate much higher than the
Nyquist rate, the range of values of d[k] will be less than the range of values of x[k].
After the transmission of the quatized signal dq[k], theoretically we can reconstruct the
original signal by doing an operation that is the inverse of the above operation. So, we
can obtain an approximation of x[k] using
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So, if dq[k] is close to d[k], it appears from the above equation that obtained xˆ[k ] will be
close to d[k]. The transmitter of the above system can be represented by the following
block diagram.
The receiver that will attempt to reconstruct the original signal after transmitting it
through the channel can be represented by the following block diagram.
Because we are quantizing a difference signal and transmitting that difference over the
channel, the reconstructed signal may suffer from one or two possible problems.
BLOCK DIAGRAM:
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DPCM ENCODING: DPCM Encoding is similar to the PCM encoding, except that initial
stage employs Delta modulation after that PCM encoding is following.. This system is
very economical to realize because it corresponds exactly to the process of analog – to
– digital (A/D) conversion. The 1st step in the PCM system is to quantize the modulating
signal. The modulating signal can assume an infinite no.of different level between the
two limit values, which define the range of the signal. In PCM a coded no is transmitted
for each level sampled in the modulating signal. If the exact no corresponding to the
exact voltage were to be transmitted for every sample, an infinitely large no of different
code symbols would be needed. Quantization has the effect of reducing this infinite no
of levels to a relatively small number, which can be coded without difficulty.
187
In the quantization process, the total range of the modulating signal is divided into a no
of small sub ranges. The number will depend on the nature of the modulating signal and
will form as few as 8 to as many as 128 levels. A number that is an integer power of two
is usually chosen because of the ease of generating binary codes. The result is stepped
waveform which follows the counter of the original modulating signal with each step
synchronized to the sampling period.
The quantized staircase waveform is an approximation to the original waveform. The
difference between the two-wave form amounts to “noise” added to the signal by the
quantizing circuit. The mean square quantization noise voltage has a value of
E2np = S2/12 Where S is the voltage of each step. As a result the number of
quantization levels must be kept high in order to keep the quantization noise below
some acceptable limit given by the power signal-to-noise ratio, which is the ratio of
average noise power.
DECODING: The decoding process reshapes the incoming pulses and eliminates most
of the transmission noise. A serial to parallel circuit passes the bits in parallel groups to
a digital to analog converter (D/A) for decoding. Thus decoded signal passes through a
sample and hold amplifier, which maintains the pulse level for the duration of the
sampling period, recreating the staircase waveform approximation of the modulation
signal. A low-pass filter may be used to reduce the quantization noise.
PROCEDURE:
1) Connect the AC power supply to the trainer kit and switch it ON.
2) Connect the DC output signal to the input of DPCM Modulator.
3) Observe the sampling signal output on the CH-1 of CRO.
4) Observe the DPCM output put on the CH-2 of CRO.
5) By adjusting the DC voltage we can get the DPCM output from 0000 0000 to 1111 1111.
6) Now disconnect the DC voltage and apply AF output to the input of DPCM modulator.
7) Observe the conditioning amplifier output & DPCM output with respect to sampling
signal.
8) Connect the DPCM output to the input of demodulator and observe the output with
respect to AF output signal.
9) Calculate the Phase shift of the demodulated signal.
10) Plot the observed waveforms on the graph sheet.
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OUTPUT WAVEFORMS:
RESULTS:1.DPCM signal is generated and demodulated.

2.Bandwidth of DPCM signal is calculated.
VIVA QUESTIONS:
1. What is bit synchronization & frame synchronization?
2. Explain block diagram of PCM?
3. What is the different error control coding technique?
4. What is resolution in ADC?
5. For arbitrary fixed reference voltage write the table of 4-bit ADC?
6. The accuracy of any digital reproduction of an analog signal depends on what?
7. If sample requires at least 12 levels of precision (+0 to +5 and –0 to –5). How many bits
should be sent for each sample? use one bit form sign.
8. What is the formula for bit rate in DPCM?
9. If we want to digitize human voice (4KHz B.W), what is the bit rate assuming 8 bits/sample?
10. What is the sampling rate for DPCM if the frequency ranges from 1000Hz to 4000Hz?
11. If the interval between two samples in a digital signal is 125 micro seconds. What is the
sampling rate?
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5. DELTA MODULATION AND DEMODULATION
AIM: 1.To transmit an analog message signal in its digital form and again reconstruct
back the original analog message signal at receiver by using Delta modulator.
2.To calculate slope overload error.
3. To calculate bandwidth of DM signal.
APPARATUS:
1. Delta modulator trainer kit
2. CRO
3. Probes & patch cards
THEORY:
Delta modulator is an advanced version of PCM system. DM uses a single bit PCM
code to achieve to achieve digital transmission of analog signal. so it is also known as
„Single bit PCM system‟. It generates the output signal by comparing the input signal
with its quantized approximated output i.e. if the step size increases to+▲ it gives binary
value „1‟ and if step downs to -▲it gives binary value „o‟. In this way it reduces the
transmission channel band width. With conventional PCM each code is binary
representation of both sign and magnitude of a particular sample. With DM, rather than
transmitting a coded representation of a sample a single bit is transmitted, which
indicates whether the sample is smaller or larger than the previous sample.
The algorithm for a delta modulation system is a simple one. If the current sample is
smaller than the previous sample then logic 0 is transmitted or logic 1 is transmitted if
the current sample is larger than the previous sample. The input analog is sampled and
converted to a PAM signal followed by comparing it with the output of the DAC. The
output of the DAC is equal to the regenerated magnitude of the previous sample which
was stored in the up/down counter as a binary number. The up/down counter is
incremented or decremented whether the previous sample is larger or smaller than the
current sample.
The block diagram of the delta modulation is also known as linear delta modulator.The
signal m(t) is the analog input signal. While r(t) is a reconstructed signal which is same
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as the quantized input signal with 1 bit delay. The signal r (t) tries to follow the input
signal m(t) with one bit period delay.
The process of encoding is as follows. The comparator compares the input signal m(t)
and r(t). if m(t) > r(t) a logic 1 is generated at the output of the comparator, otherwise a
logic 0 is generated. The value of logic 1 or logic 0 turned as (t) is held for the bit
duration by the sampled and hold current to generate So(t), the delta modulated output.
This output So(t) is fed to the 8 bit binary up/down counter to control it‟s count direction.
Logic 1 at the mode control input increases the count value by one and logic „0‟
decrements the count value by one. All the 8 outputs of the counter are given to DAC to
reconstruct the original signal. In essence the counter & decoder forms the delta
modulator in the feedback loop of the comparator. Thus if the input signal is higher than
the reconstructed signal the counter increments at each step so as to enable the DAC
output to reach to the input signal values. Similarly if the input signal m(t) is lower than
the reconstructed signal r(t), the counter decrements at each step, and the DAC output
gets reduced to reach a value to that of m(t).
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The block diagram of Delta modulator is shown below. It works in the same way as it
was in the feedback loop of the Delta modulator. The received Delta modulated signal
So(t) is given to the mode control input (U/D) of the up/down counter. The counter is a 8
bit wide and counts in binary fashion. All the 8 outputs are connected to an 8-bit DAC,
which gives a quantized analog signal (stepped wave form). A low pass filter is used to
smooth out the steps. A buffer amplifier provides the necessary drive capability to the
output signal. Thus the digital modulated data is demodulated and reconstructed into an
analog signal.
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Although this process of Delta Modulation and demodulation is a simple and cost
effective method of coding, there will be poor approximation at starting build up and
hunting at flat top signals. Another limitation is delta modulation is „slope overloading‟ If
the input signal frequency is greater than the limiting value slope overloading occurs. In
such a case true reproduction of the analog signal is not possible. A sinusoidal
waveform of amplitude A & frequency f has a maximum slope of 2fA which occurs at
zero crossing of the sine wave. If the overloading is to be avoided then the following
condition should be satisfied.
S  2fA/fs
where S quantization step size
fs sampling frequency
f signal frequency
A signal amplitude
BLOCK DIAGRAM:
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BLOCK DIAGRAM FOR DEMODULATOR:
PROCEDURE:
MODULATOR
1. 1.Give the 1kHz analog input to the comparator input pin(9) and the output of the
comparator is given to the bi-stable circuit input the TX clock signal is given to
the other input of the bi-stable circuit.
2. The bi-stable circuit output is internally given to the Unipolar/bipolar converter
and the output of this converter will be given to the input of integrator.
3. The integrator output is given to the second input of the comparator.
4. Then plot the comparator input waveforms and the bi-stable circuit output, and
the corresponding clock signal.
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DEMODULATOR
1. Connect the bi-stable circuit output to the demodulator side bi-stable circuit
input, and also give the receiver clock signal to this circuit.
2. The output of this bi-stable circuit is internally given to the Unipolar/bipolar
converter and the output of this converter will be given to the input of integrator at
demodulator side.
3. Then the integrator output is given to the low pass filter, so finally we observe the
original analog signal output across low pass filter output terminal.
OUTPUT WAVEFORMS:
PRECAUTIONS:
2. Note down the comparator inputs carefully.
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VIVA QUESTIONS:
1. What are the advantages of Delta modulator?
2. What are the disadvantages of delta modulator?
3. How to overcome slope overload distortion?
4. How to overcome Granular or ideal noise?
5. What are the differences between PCM & DM?
6. Define about slope over load distortion?
7. What is the other name of Granular noise?
8. What is meant by staircase approximation?
9. What are the disadvantages of Delta modulator?
10. Write the equation for error at present sample?
RESULTs: 1.The given analog message signal is converted to digital data output by
using delta modulator and converted to analog using demodulator .
2. Slope overload error is calculated.
3. Bandwidth of DM signal is calculated
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6. ADAPTIVE DELTA MODULATION
AIM:1. To convert analog signal to digital using Adaptive delta modulation and to
demodulate adaptive delta modulated signal.
2.To calculate the bandwidth of ADM signal.
APPARATUS:
1. Adaptive delta modulator trainer kit
2. C.R.O
3. Connecting wires& probes
THEORY:
In this ADM the step size of the Quantizer is made adaptive to the input signal
variation. To overcome the disadvantages of Delta modulator we will go for this
Adaptive delta modulation technique in this there is on slope over load distortion and
granular noise. Compared to delta modulator the ADM is having very high signaling
rate.
BLOCK DIAGRAM:
ADAPTIVE DELTA MODULATOR
197
ADAPTIVE DELTA DEMODULATOR
198
PROCEDURE:
MODULATOR
1. Give the 1kHz analog input to the comparator input pin(9) and the output
of the comparator is given to the bi-stable circuit input the TX clock
signal is given to the other input of the bi-stable circuit.
2. The bi-stable circuit output is internally given to the Unipolar/bipolar
converter and the output of this converter will be given to the input of
integrator.
3. The integrator output is given to the second input of the comparator.
4. Connect A&B gain controls from adaptive control circuit to integrator and
also put the gain control switches at L.H.S position
5. Connect the transmitter clock to adaptive control circuit, and also
connect the data output of bi-stable network to adaptive control circuit
6. Then plot the comparator input waveforms and the bi-stable circuit
output, and the corresponding clock signal.
7. Finally obtain the adaptive delta modulated output across the output
terminal of a bi-stable network.
DEMODULATOR
8. Connect the bi-stable circuit output to the demodulator side bi-stable
circuit input, and also give the receiver clock signal to this circuit.
9. The output of this bi-stable circuit is internally given to the
Unipolar/bipolar converter and the output of this converter will be given
to the input of integrator at demodulator side.
10. Here also connect the A&B terminals of adaptive control circuit to
integrator and also keep gain control switch at R.H.S position.
11. Then the integrator output is given to the low pass filter, so finally we
observe the original analog signal output across low pass filter output
terminal.
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OUTPUT WAVEFORMS:
PRECAUTIONS:
2. Note down the comparator inputs carefully
RESULTS: 1.Hence we obtained the digital data output of a given analog message
signal by using adaptive delta modulator and converted digital signal to analog using
adaptive delta demodulator .
2. Bandwidth of adaptive delta modulated wave is calculated.
VIVA QUESTIONS:
1. What are the disadvantages of delta modulation?
2. What are the necessary steps to overcome the disadvantages?
3. What is adaptive delta modulation?
4. What happens if the step size is decreased?
5. What is Granular noise?
6. What is the importance of integrator in ADM?
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7.LINE CODING AND DECODING TECHNIQUES
AIM :
1.To study different line coding techniques.
2.To calculate bandwidth of different line coding techniques
APPARATUS REQUIRED:
1. Communication trainer kit
2. Multi Output Power Supply.
3. Patch cords.
4. DSO/CRO
THEORY:
Line coding: the process of converting digital data to digital signals We need to
represent PCM binary digits by electrical pulses in order to transmit them through a
base band channel. The most commonly used PCM popular data formats are being
realized here.Line coding refers to the process of representing the bit stream (1‟s and
0‟s) in the form of voltage or current variations optimally tuned for the specific
properties of the physical channel being used.
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Signal Element and Data Element
Data Rate Versus Signal Rate

Data rate defines the number of data elements (bits) sent in 1s: bps
• Signal rate is the number of signal elements sent in 1s: baud
• Data rate = bit rate, signal rate = pulse rate, modulation rate, baud rate
• S = c x N x 1/r, where N is the date rate; c is the case factor, S is the number of
signal elements; r is the number of data elements carried by each signal element
• Although the actual bandwidth of a digital signal is infinite, the effective
bandwidth is finite
• The bandwidth is proportional to the signal rate (baud rate)
• The minimum bandwidth: Bmin = c x N x 1/r
• The maximum data rate: Nmax = 1/c x B x r
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Line Coding Schemes
The selection of a proper line code can help in so many ways: One possibility is to aid
in clock recovery at the receiver. A clock signal is recovered by observing transitions in
the received bit sequence, and if enough transitions exist, a good recovery of the clock
is guaranteed, and the signal is said to be self-clocking.
• Another advantage is to get rid of DC shifts. The DC component in a line code is
called the bias or the DC coefficient. Unfortunately, most long-distance
communication channels cannot transport a DC component. This is why most
line codes try to eliminate the DC component before being transmitted on the
channel.Such codes are called DC balanced, zero-DC, zero-bias, or DC
equalized.Some common types of line encoding in common-use nowadays are
unipolar, polar, bipolar, Manchester, MLT-3 and Duobinary encoding. These
codes are explained here:
1. Unipolar (Unipolar NRZ and Unipolar RZ):
Unipolar is the simplest line coding scheme possible. It has the advantage of being
compatible with TTL logic. Unipolar coding uses a positive rectangular pulse p(t) to
represent binary 1, and the absence of a pulse (i.e., zero voltage) to represent a binary
0. Two possibilities for the pulse p(t) exist3: Non-Return-to-Zero (NRZ) rectangular
pulse and Return-to-Zero (RZ) rectangular pulse. The difference between Unipolar NRZ
and Unipolar RZ codes is that the rectangular pulse in NRZ stays at a positive value
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(e.g., +5V) for the full duration of the logic 1 bit, while the pule in RZ drops from +5V to
0V in the middle of the bit time.
A drawback of unipolar (RZ and NRZ) is that its average value is not zero, which
means it creates a significant DC-component at the receiver (see the impulse at zero
frequency in the corresponding power spectral density (PSD) of this line code
UNIPOLAR NRZ CODE
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The disadvantage of unipolar RZ compared to unipolar NRZ is that each
rectangular pulse in RZ is only half the length of NRZ pulse. This means that unipolar
RZ requires twice the bandwidth of the NRZ code.
Polar (Polar NRZ and Polar RZ):

In Polar NRZ line coding binary 1‟s are represented by a pulse p(t) and binary
0‟s are represented by the negative of this pulse -p(t) (e.g., -5V). Polar (NRZ and RZ)
signals .Using the assumption that in a regular bit stream a logic 0 is just as likely as a
logic 1,polar signals (whether RZ or NRZ) have the advantage that the resulting
Dccomponent is very close to zero.
The rms value of polar signals is bigger than unipolar signals, which means that
polar signals have more power than unipolar signals, and hence have better SNR at the
receiver. Actually, polar NRZ signals have more power compared to polar RZ signals.
The drawback of polar NRZ, however, is that it lacks clock information especially when
a long sequence of 0‟s or 1‟s is transmitted. Non-Return-to-Zero, Inverted (NRZI):
NRZI is a variant of Polar NRZ. In NRZI there are two possible pulses, p(t) and –p(t). A
transition from one pulse to the other happens if the bit being transmitted is a logic 1,
and no transition happens if the bit being transmitted is a logic 0.
This is the code used on compact discs (CD), USB ports, and on fiber-based
Fast Ethernet at 100-Mbit/s .
MANCHESTER ENCODING:
In Manchester code each bit of data is signified by at least one transition.
Manchester encoding is therefore considered to be self-clocking, which means that
accurate clock recovery from a data stream is possible. In addition, the DC component
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of the encoded signal is zero. Although transitions allow the signal to be self-clocking, it
carries significant overhead as there is a need for essentially twice the bandwidth of a
simple NRZ or NRZI encoding
POWER SPECTRA OF LINE CODES:
 Unipolar most of signal power is centered around origin and there is waste of
power due to DC component that is present.
 Polar format most of signal power is centered around origin and they are simple
to implement.
 Bipolar format does not have DC component and does not demand more
bandwidth, but power requirement is double than other formats.
 Manchester format does not have DC component but provides proper clocking.
PROCEDURE
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1. Connect the PRBS (test point P5) to various line coding formats.
2. Obtain the coded output as per the requirement.
3. Connect coded signal test point to corresponding decoding test point as inputs.
4. Switch ON the power supply.
signal on one channel of CRO and decoded signal on second channel of CRO.
CIRCUIT DIAGRAM
EXPECTED GRAPH
207
• NRZ-L (Non Return to Zero-Level)
– Level of the voltage determines the value of the bit
• NRZ-I (Non Return to Zero-Invert)
– Inversion or the lack of inversion determines the value of the bit

RZ
• Provides synchronization for consecutive 0s/1s

• Signal changes during each bit
• Three values (+, -, 0) are used
– Bit 1: positive-to-zero transition, bit 0: negative-to-zero transition
Biphase
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– Combination of RZ and NRZ-L ideas
– Signal transition at the middle of the bit is used for synchronization
– Manchester
– Used for Ethernet LAN
– Bit 1: negative-to-positive transition
– Bit 0: positive-to-negative transition
– Differential Manchester
– Used for Token-ring LAN
– Bit 1: no transition at the beginning of a bit
– Bit 0: transition at the beginning of a bit
• Minimum bandwidth is 2 times that of NRZ
Bipolar Scheme
• Three levels of voltage, called “multilevel binary”

• Bit 0: zero voltage, bit 1: alternating +1/-1
– (Note) In RZ, zero voltage has no meaning
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• AMI (Alternate Mark Inversion) and pseudoternary
– Alternative to NRZ with the same signal rate and no DC component problem
Multilevel Scheme
• To increase the number of bits per baud by encoding a pattern of m data elements into a
pattern of n signal elements
• In mBnL schemes, a pattern of m data elements is encoded as a pattern of n signal
elements in which 2m ≤ Ln
• 2B1Q (two binary, one quaternary)
• 8B6T (eight binary, six ternary)
• 4D-PAM5 (four-dimensional five-level pulse amplitude modulation)
•
2B1Q (two binary, one quaternary)
•
8B6T
Summary of Line Coding Schemes
210
Observations
Name of the Time period in

S.No Amplitude in V Frequency in Hz
signal Sec
1 Clock Signal
2 Modulated Signal
RESULTS:
1. Thus the different line coding techniques was studied.
2. Bandwidth of different line coding techniques are calculated.
VIVA QUESTIONS:
1. What are the applications of Line encoding schemes?
2. Compare different Line encoding schemes.
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8. AMPLITUDE SHIFT KEYING
AIM: 1.To generate the ASK signal for given binary data and also modulate the
transmitted binary data.

2.To calculate probability of error for ASK signal.
3. To calculate bandwidth of ASK signal.
APPARATUS:
1. SL100 transistor
2. Op-amp
3. 1KΩ resistors
4. 100 KΩ resistors
5. +5v power supply
6. Function generator
7. CRO
8. Bread board
9. Connecting wires, probes
THEORY:
ASK is one in which the amplitude of a carrier is switched between two values
i.e, on and off. The resultant waveform consists of on pulses representing binary 1 and
off pulses representing binary 0.The binary ASKS signaling scheme was one of the
earliest forms of digital modulation used in wireless telegraphy at the beginning of this
century. It is the simplest form of digital modulation & serves as a useful model for
introducing certain concepts.
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• Data element versus signal element
• Data rate (bit rate) versus signal rate (baud rate)
– S = N x 1/r baud S (signal rate), N (data rate),
r (number of data element in one signal element)
– Bit rate: bits per second (in bps)
– Baud rate: signal elements per second (in baud)
– Bit rate  baud rate
– BASK or OOK (on-off keying)
– Bandwidth for ASK: B = (1 + d) x S
Example:An analog signal has a bit rate of 8000 bps and a baud rate of 1000 baud.
How many data elements are carried by each signal element? How many signal
elements do we need?
Solution
S = 1000, N = 8000, and r and L are unknown. We find first the value of r and
then the value of L.
213
CIRCUITDIAGRAM:
214
PROCEDURE:
2. Set function generator (square wave) of 1v, 1 kHz for input modulating signal
then switch ON the power supply.
3. Now observe ASK output waveform on the CRO.
4. Plot the observed waveform on the graph.
OUTPUT WAVEFORMS:
RESULTS: 1. ASK signal is generated form a given binary input &also the demodulated
signal of an ASK is obtained.
2. Probability of error for ASK signal is calculated..
3. Bandwidth of ASK signal is calculated.
215
VIVA QUESTIONS:
1. What is the other name of ASK signal?

2. Draw the o/p waveform of ASK?
3. What are the demodulation techniques of BASK?
4. Draw the power spectral density of ASK signal?
5. Write the standard equation of ASK signal?
6. What is the transmission BW of an ASK signal?
7. What are the differences between BASK&FSK?
8. What the advantages are of ASK over an AM?
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9. FREQUENCY SHIFT KEYING
AIM:1. To generate the frequency shift keying signal for a given binary data and also
demodulate the original data input.
2.To calculate probability of error for FSK signal.
3. To calculate bandwidth of FSK signal.
APPARATUS:
1. PCM transmitter trainer kit.
2. Data formatting & carrier modulation transmitter trainer kit
3. Data reformatting & carrier demodulation receiver trainer kit
4. C.R.O
THEORY:
In FSK, the waveform is generated by switching the frequency of the carrier between
two values corresponding to the binary information which is to be transmitted. Here the
carrier frequency varies from lowest to highest point i.e. carrier swing is known as
Frequency shift keying. FSK signaling schemes find a wide range of applications in low
speed digital data transmission systems.
• Bandwidth for FSK: B = (1 + d) x S + 2Δf
217
•
• Example:We have an available bandwidth of 100 kHz which spans from 200 to
300 kHz. What should be the carrier frequency and the bit rate if we modulated
our data by using FSK with d = 1?
The midpoint of the band is at 250 kHz. We choose 2Δf to be 50 kHz; this means
Multilevel FSK
• The frequencies need to be 2Δf apart. Min. value 2Δf needs to be S.
• B = (1 + d) x S + (L – 1) 2Δf  B = L x S with d = 0
• Example: We need to send data 3 bits at a time at a bit rate of 3 Mbps. The
carrier frequency is 10 MHz. Calculate the number of levels (different
frequencies), the baud rate, and the bandwidth
L = 23 = 8. The baud rate is S = 3 MHz/3 = 1000 Mbaud. This means that the
carrier frequencies must be 1 MHz apart (2Δf = 1 MHz). The bandwidth is B = 8 × 1000
= 8000.
218
BLOCK DIAGRAM:
219
Circuit Diagram
PROCEDURE: (PCM TX)

1. The following connections are made at PCM TX
 D.C 1 to CH.0
 CH.0 to CH.1
2. The following conditions should be there
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 Mode switch - fast mode
 Sync switch - ON
 Switched faults – OFF
 Error check code – OFF
 TX .T0 - CRO external triggering.
 Adjust D.C1 until the 7 bit code is displayed on A/D converter LED.
 Then observe the PCM TX data output.

(DATA FORMATTING AND CARRIER MOD.&DEMOD. TRAINER)

1. From PCM Tx clock to Tx clock input terminal.
2. PCM output to Tx data input.
3. Then connect NRZ (L) output, carrier of 1.44MHz is applied at modulating
input& carrier inputs of Modulator I.
4. Now invert the NRZ (L) output, then the inverted output and 960MHz
carrier signal both are given to Modulator II.
5. Both the outputs of Modulator I& Modulator II are given to a summing
amplifier then we observe the FSK output across the summing amplifier
output terminal.
6. For demodulation of this FSK signal, connect this FSK output to FSK
demodulator input terminal and the output of this FSK demodulator block
is given to the input of LPF.
7. The LPF output is given to the input of voltage comparator, then we
observe the demodulated output across the output terminal of the voltage
comparator of DF&CDM trainer kit.
OUTPUT WAVEFORMS:
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.RESULT: 1. Hence obtained the FSK signal for a given input data and also obtained
demodulated data the given FSK signal.
2. Probability of error for FSK signal is calculated..
3. Bandwidth of FSK signal is calculated.
VIVA QUESTIONS:
1. Define Binary FSK signal?
2. What is meant by carrier swing?
3. Define Frequency deviation of FSK signal?
4. What are the advantages of this FSK signal?
5. Give the differences between FSK & FM?
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10. PHASE SHIFT KEYING
AIM: 1.To generate the phase shift keying signal for the given binary data & to
demodulated to Receive the transmitted binary data.

2.To calculate probability of error for PSK signal.
3. To calculate bandwidth of PSK signal.
APPARATUS:
1. PCM trainer kit
2. PSK trainer kit
3. CRO
THEORY:
Phase shift keying or discrete phase modulation is another technique available
for communicating digital information over band pass channels. In PSK signaling
schemes the waveforms s1(t) = -Acoswct & S2(T) = Acoswct are used to convey binary
digits 0& 1 respectively. The binary PSK waveform Z (t) can be described by, Z (t) = D
(t) Acoswct . Where D (T) is a random binary waveform with period T b& levels -1&1. The
only difference b/w the ASK&PSK waveform is that in the ASK scheme the carrier is
switched on &off whereas in the PSK scheme the carrier is switched b/w levels +A & -A.
If the carrier phase is shifted between two values then the method is called Phase
Shift keying (PSK). In PSK the amplitude of the carrier remains constant.
To generate a binary PSK signal, we have to represent the input binary sequence in
polar form with symbols 1 and 0 represented by constant amplitude levels of +√E b and
-√E b, respectively. This signal transmission encoding is performed by a polar non
return – to – zero (NRZ) level encoder. The resulting binary wave and a sinusoidal
carrier φ (t), whose frequency fc = (nc / Tb) for some fixed integer nc, are applied to a
product modulator as shown fig.1. The carrier and the pulses used to generate the
binary wave are usually extracted from a common master clock. The desired PSK wave
is obtained at the modulator output. To detect the original binary sequence of 1s and 0s,
we apply the noisy PSK signal x (t) (at the channel output) to a correlator, which is also
supplied with a locally generated coherent reference signal φ1 (t) as shown fig.. The
223
correlator output, X1 is compared with a threshold of zero volts. If X1 <0, it decides in
favour of symbol 0. If X1 is exactly zero, the receiver makes a random guess in favour
of 0 or 1.
224
• Bandwidth of BPSK, B = (1 + d) x S
• Less than that for BFSK
Constellation diagram
• Define the amplitude and phase of a signal element
Constellation Diagram: Examples
225
226
CIRCUIT DIAGRAM:
Circuit Description : In this carrier Generator is designed around a wein bridge'

oscillator using 741. The sinusoidal output has a frequency of around 10KHz. Square
227
wave clock at the same frequency is generated by using TL084 Op Amp in comparator
Mode. A transistor inverter using BC 107 Improves the clock shape with sharp, rising
and falling edges. This square wave is used as a clock input to a decade counter
(IC7490), which generates the modulating data outputs. IC CD4051 is an Analog
multiplexer to which carrier is applied with and without 1800 phase shift to the two
multiplex inputs of the IC. Modulating data input is applied to its control input.
Depending upon the level of the control signal, carrier signal applied with or without
Phase shift is steered to the output. The 180 0 phase shift to the carrier signal created by
an operational amplifier using 741 IC. During the demodulation, the PSK signal is
converted into a +5 volts square wave signal using a transistor and is applied to one
input of an EX-ORgate. To the second input of the gate, carrier signal is applied after
conversion into a +5 volts signal. So the EX-OR gate output is equivalent to the
modulating data signal.
PROCEDURE:
1. Assume that the following connections are made on PCM T X.
2. DC1 o/p is connected to channel -0 i/p.
3. Channel-0 i/p is connected to chennal-1 i/p
4. Mode switch is kept in fast mode.
5. Synch button is kept in on position.
6. Switched faults should be in OFF position.
7. Error check OFF (00).
8. TX to be connected to CRO external triggering.
9. Adjust the DC1 until the 7bit code displayed on A/D converter.
10. LED is observing the PCM o/p at PCM Tx o/p.
228
OUTPUT WAVEFORMS:
RESULT: 1.PSK output of a given binary data is generated and also the demodulated
output of a PSK signal is obtained.

2. Probability of error for PSK signal is calculated..
3. Bandwidth of PSK signal is calculated.
229
VIVA QUESTIONS:
1. What is the bandwidth requirement of BPSK?
2. What is the expression for error probability of BPSK reception using coherent
matched filter detection?
3. What are the draw backs of BPSK?
4. Draw the Power spectral density of BPSK?
5. What are the major differences between DPSK&BPSK?
6. What are the advantages of BPSK over a PSK signal?
11. DIFFERENTIAL PHASE SHIFT KEYING
AIM: 1.To generate differentially phase shift keying signal and also demodulate the
original binary data.
2.To calculate probability of error for DPSK signal.
3. To calculate bandwidth of DPSK signal.
APPARATUS:
1. DPSK modulation and demodulation trainer kit
2. CRO
3. Patch cards
THEORY:
We may view DPSK as the non-coherent vision of PSK. It eliminates the need for
adjustment coherent reference signal at the receiver by connecting two basic operations
at the transmitter.
1. Differential encoding at the transmitter.
230
2. Phase shift keying
Hence differential encoding means the given input data will be done EX-OR operation
with the previous encoded bit. Now the process of Phase shift keying will be done for
both differentially encoded data and the carrier signal.
In effect to send symbol 0, we phase advance the current signal wave-form by 1800,
and to send symbol 1, we leave the phase of the current signal waveform unchanged.
The receiver is equipped with a storage capability, so that it can measure the relative
phase difference between the waveforms received during two successive bit intervals.
Provided that the unknown phase θ contained in the received wave varies slowly, the
phase difference between wave forms received in two successive bit intervals will be
independent of θ.
The block diagram of a DPSK transmitter is shown in fig. below. It consists, in part of a
logic network and a one-bit delay element interconnected so as to convert the binary
sequence {b k} into a differentially encoded sequence {d k}. This sequence is amplitude
level encoded and then used to modulate a carrier wave of frequency fc, thereby
producing the desired DPSK signal
231
The optimum receiver for differentially coherent detection of binary DPSK is as shown in
fig. below. This implementation merely requires that sample values be stored, thereby
avoiding the need for delay lines that may be needed otherwise. The equivalent receiver
implementation that tests squared elements is more complicated, but its use makes the
analysis easier to handle in that the two signals to be considered are orthogonal.
232
BLOCK DIAGRAM:
DPSK MODULATOR
233
DPSK DEMODULATOR
Phase shift keying (PSK) is a relatively new system, in which the carrier may be
phase shifted by + 90 degrees for a mark, and by -90 degrees for a space. PSK has a
number of similarities to FSK in many aspects, as in FSK frequency of the carrier is
shifted according to the modulating square wave. shows the circuit diagram of
Differential phase Shift Key Modulation & Demodulation. In this IC 8038 is a basic
waveform generator, which generates Sine, Square, and Triangle waveforms. The sine
wave generated by this 8038 IC is used as carrier signal to the system. The Square
Wave generated by 80381C is at +/- 12V level. So this is converted. Into a +5V signal
with the help of a transistor and diode as shown in fig-1. This Square wave is used as a
clock input to a decade counter (IC 7490), which generates the modulating data
outputs.
MODULATION: The Differential signal to the modulating signal is generated using an

Exclusive -OR gate and a 1-bit delay circuit (It is shown in fig-1). CD 4051 is an analog
multiplexer to which carrier is applied with and without 180 0 degrees Phase shift
(created by using an operational amplifier connected in inverting amplifier mode) to the
two inputs of the IC741. Differential signal generated by Ex-OR gate (IC7486) is given
to the multiplexer's control signal input. Depending upon the level of the control signal,
carrier signal applied with or without phase shift is steered to the output. Using a D-flip-
flop (IC747) creates 11bit delay generation of differential signal to the input.
DEMODULATION: During the demodulation, the DPSK signal is converted into a +5V
Square Wave signal using a transistor and is applied to one input of an EX-OR gate. To
the second input of the gate, carrier signal is applied after conversion into a +5V signal.
So the EX-OR gate output is equivalent to the differential signal of the modulating data.
This differential data is applied to one input of an Exclusive -OR gate and to the second
input. after 1-bit delay the same signal is given. So the output of this Ex-OR gate is
modulating signal
234
PROCEDURE:
(MODULATOR)
1. In this DPSK trainer kit there three signal generators one is for carrier signal
and the second is for clock signal and another is for electrical representation
of data bits, so give the carrier signal to CARRIER IN terminal OF
MODULATOR.
2. Give the clock signal to CLOCK IN terminal and there are four different data
bit combinations are available in the form of (D1, D2, D3 and D4) so
connect one of this input data signal to DATA IN terminal of the modulator.
3. Take the differential data output across the DIFF.OUT terminal of the
modulator.
4. And then observe the differentially phase shifted carrier signal across the
output of the modulator i.e. DPSK output.
(DEMODULATOR)
5. Connect DPSK output to DPSK input terminal of the demodulator block.

6. Give the clock signal to CLOCK IN terminal and also connect the carrier
signal to CARRIER IN terminal.
7. Ground both the modulator and demodulator circuits.
8. Observe the DPSK demodulated output across the DEMOD.OUT terminal
of the demodulator circuit.
235
OUTPUT WAVE FORMS:
PRECAUTIONS:
1. Connections should be tight.
2. Note the output wave forms carefully.
RESULTS:
1. Hence the differential phase shift keying output of a given binary data and
the corresponding demodulated outputs are observed.
2. Probability of error for DPSK signal is calculated..
3. Bandwidth of DPSK signal is calculated.
VIVA QUESTIONS:
1. What is the difference between PSK&DPSK?
2. What is the band width requirement of a DPSK?
3. Explain the operation of DPSK detection?
4. What are the advantages of DPSK?
5. What is meant by differential encoding?
6. In Differential encoding technique which type of logic gates are used
236
12. QPSK MODULATION AND DEMODULATION
AIM
1.To generate a Quadrature Phase Shift Keying signal using QPSK modulator and
detect the message signal from QPSK signal using QPSK detector.
2.To calculate the Probability of error for QPSK signal.
3. To calculate the bandwidth of QPSK signal.
APPARATUS REQUIRED
QPSK kit, CRO and connecting probes
THEORY
QPSK is another form of angle-modulated, constant-amplitude digital modulation.
It is an M-ary encoding technique where M=4. with QPSK four output phases are
possible for a single carrier frequency. Two bits (a dibit) are clocked into the bit splitter.
After both bits have been serially inputted, they are simultaneously parallel outputted.
One bit is directed to the I channel and the other to the Q channel. The I bit modulates a
carrier that is in phase with the reference oscillator and the Q bit modulates a carrier
that is 900 out of phase with the reference carrier.
QPSK modulator is two BPSK modulators combined in parallel. The input QPSK
signal is given to the I and Q product detectors and the carrier recovery circuit. The
carrier recovery circuit produces the original transmit carrier oscillator signal. The
recovered carrier must be frequency and phase coherent with the transmit reference
carrier. The QPSK signal is demodulated in the I and Q product detectors, which
generate the original I and Q data bits. The output of the product detectors are fed to
the bit combining circuit, where they are converted from parallel I and Q data channels
to a single binary output data stream.
237
PROCEDURE:
1. Connect the binary input data to I-channel.
2. Connect the binary input data to Q-channel.
3. Connect the sine wave input to balanced modulator (I channel) as a carrier
signal and to sine wave input to balanced modulator (Q channel) as a carroer
signal.
4. Switch on the power supply.
5. Display binary input data on CRO. Adjust pot1 and pot3 to get bipolar data.
6. Adjust gain control pot to set equal amplitude in I and Q channel.
7. Obtain QPSK signal.
8. Connect the QPSK to input of QPSK demodulator.
9. Obtain the demodulated QPSK signal.
238
Circuit Diagram
QPSK MODULATOR
QPSK DEMODULATOR
239
240
EXPECTED WAVE FORMS:
241
observations
Name of the Time period in
S.No Amplitude in V Frequency in Hz
signal Sec
1 Modulating Signal
2 Carrier Signal
3 Modulated Signal
4 Demodulated
Signal
RESULTS;
1.Quadrature Phase Shift Keying signal was generated using QPSK modulator and the
message signal was detected from QPSK signal using QPSK detector.
2. Probability of error for FSK signal is calculated..
3. Bandwidth of FSK signal is calculated.
VIVA QUESTIONS:
1. What is the difference between PSK&QPSK?
2. What is the band width requirement of a QPSK?
3. Explain the operation of QPSK detection?
4. What are the advantages of QPSK?
5. What is meant by differential encoding?
242
DIGITAL COMMUNICATION USING
MATLAB
243
1. µ-LAW COMPANDING.
Aim: To perform µ-Law Companding using MAT LAB
Theory:
The code below quantizes an exponential signal in two ways and compares the
resulting mean square distortions. First, it uses the quantizer function with a partition
consisting of length-one intervals. In the second trial, compand implements a µ-law
compressor, quantizer quantizes the compressed data, and compand expands the
quantized data. The output shows that the distortion is smaller for the second scheme.
This is because equal-length intervals are well suited to the logarithm of sig, but not well
suited to sig. The figure shows how the compander changes sig.
Mu = 255; % Parameter for mu-law compander
sig = -4:.1:4;
sig = exp(sig); % Exponential signal to quantize
V = max(sig);
% 1. Quantize using equal-length intervals and no compander.
[index,quants,distor] = quantiz(sig,0:floor(V),0:ceil(V));
% 2. Use same partition and codebook, but compress

% before quantizing and expand afterwards.
compsig = compand(sig,Mu,V,'mu/compressor');
[index,quants] = quantiz(compsig,0:floor(V),0:ceil(V));
newsig = compand(quants,Mu,max(quants),'mu/expander');
distor2 = sum((newsig-sig).^2)/length(sig);
[distor, distor2] % Display both mean square distortions.
plot(sig); % Plot original signal.

hold on;
plot(compsig,'r--'); % Plot companded signal.
legend('Original','Companded','Location','NorthWest')
244
2.DPCM Encoding and Decoding
Aim: To perform DPCM encoding and decoding using MAT LAB
Theory:
The quantization in the section Quantize a Signal requires no a priori knowledge about
the transmitted signal. In practice, you can often make educated guesses about the
present signal based on past signal transmissions. Using such educated guesses to
help quantize a signal is known as predictive quantization. The most common predictive
quantization method is differential pulse code modulation (DPCM).
The functions dpcmenco, dpcmdeco, and dpcmopt can help you implement a DPCM
predictive quantizer with a linear predictor.
DPCM Terminology
To determine an encoder for such a quantizer, you must supply not only a partition and
codebook as described in Represent Partitions and Represent Codebooks, but also a
predictor. The predictor is a function that the DPCM encoder uses to produce the
educated guess at each step. A linear predictor has the form
y(k) = p(1)x(k-1) + p(2)x(k-2) + ... + p(m-1)x(k-m+1) + p(m)x(k-m)
where x is the original signal, y(k) attempts to predict the value of x(k), and p is an m-
tuple of real numbers. Instead of quantizing x itself, the DPCM encoder quantizes the
predictive error, x-y. The integer m above is called the predictive order. The special
case when m = 1 is called delta modulation.
Represent Predictors
If the guess for the kth value of the signal x, based on earlier values of x, is
y(k) = p(1)x(k-1) + p(2)x(k-2) +...+ p(m-1)x(k-m+1) + p(m)x(k-m)
then the corresponding predictor vector for toolbox functions is
predictor = [0, p(1), p(2), p(3),..., p(m-1), p(m)]
Note: The initial zero in the predictor vector makes sense if you view the vector as the
polynomial transfer function of a finite impulse response (FIR) filter.
Example: DPCM Encoding and Decoding
245
A simple special case of DPCM quantizes the difference between the signal's current
value and its value at the previous step. Thus the predictor is just y(k) = x (k - 1). The
code below implements this scheme. It encodes a sawtooth signal, decodes it, and plots
both the original and decoded signals. The solid line is the original signal, while the
dashed line is the recovered signals. The example also computes the mean square
error between the original and decoded signals.
predictor = [0 1]; % y(k)=x(k-1)
partition = [-1:.1:.9];
codebook = [-1:.1:1];
t = [0:pi/50:2*pi];
x = sawtooth(3*t); % Original signal
% Quantize x using DPCM.
encodedx = dpcmenco(x,codebook,partition,predictor);
% Try to recover x from the modulated signal.
decodedx = dpcmdeco(encodedx,codebook,predictor);
plot(t,x,t,decodedx,'--')
legend('Original signal','Decoded signal','Location','NorthOutside');
distor = sum((x-decodedx).^2)/length(x) % Mean square error.
246
3.DELTA MODULATION
Aim: To perform Delta modulation using MAT LAB.
Theory:
dpcmenco
Encode using differential pulse code modulation
Syntax
indx = dpcmenco(sig,codebook,partition,predictor)
[indx,quants] = dpcmenco(sig,codebook,partition,predictor)
Description
indx = dpcmenco(sig,codebook,partition,predictor) implements differential pulse code
modulation to encode the vector sig. partition is a vector whose entries give the
endpoints of the partition intervals. codebook, a vector whose length exceeds the length
of partition by one, prescribes a value for each partition in the quantization. predictor
specifies the predictive transfer function. If the transfer function has predictive order M,
predictor has length M+1 and an initial entry of 0. The output vector indx is the
quantization index.
See Differential Pulse Code Modulation for more about the format of predictor. See
Represent Partitions, Represent Partitions, or the reference page for quantiz in this
chapter, for a description of the formats of partition and codebook.
[indx,quants] = dpcmenco(sig,codebook,partition,predictor) is the same as the syntax
above, except that quants contains the quantization of sig based on the quantization
parameters. quants is a vector of the same size as sig.
Note If predictor is an order-one transfer function, the modulation is called a delta
modulation
247
4. EYE DIAGRAM MEASUREMENTS ON SIMULATED SIGNALS
Aim: To perform eye diagram measurements on simulated signals using MAT
LAB.
% Set up the pattern generator
hSrc = commsrc.pattern(...
'RiseTime', Trise, ...
'FallTime', Tfall) %#ok
% Generate NRZ signal
msgSymbols = generate(hSrc, frameLen);
% Create an comm.AWGNChannel System object.
% Set the NoiseMethod property of the channel to 'Signal to noise ratio
% (SNR)'. The commsrc.pattern object generates unit power signals; set the
% SignalPower property to 1 Watt.
hChan = comm.AWGNChannel('NoiseMethod', 'Signal to noise ratio (SNR)',...
'SNR', SNR, 'SignalPower', 1);
% Add AWGN
msgRx = step(hChan, msgSymbols);
% Create an eye diagram and display properties
eyeObj = commscope.eyediagram(...
'MinimumAmplitude', -1.5, ...
'MaximumAmplitude', 1.5, ...
'MeasurementDelay', 0.006, ...
'ColorScale', 'log') %#ok
% Update the eye diagram object with the noisy NRZ signal
update(eyeObj, msgRx);
% Plot the time domain signal
t = 0:1/Fs:15/Rs-1/Fs; idx = round(t*Fs+1);
hFig = figure('Position', [0 0 460 360]); plot(t, msgRx(idx));
title('Noisy NRZ signal');xlabel('Time (sec)');ylabel('Amplitude');grid on;
managescattereyefig(hFig, eyeObj, 'left')
hSrc =
248
Type: 'Pattern Generator'
SamplingFrequency: 10000
SamplesPerSymbol: 100
SymbolRate: 100
PulseType: 'NRZ'
OutputLevels: [-1 1]
RiseTime: 0.0020
FallTime: 0.0020
DataPattern: 'PRBS7'
Jitter: [1x1 commsrc.combinedjitter]
eyeObj =
Type: 'Eye Diagram'
SamplingFrequency: 10000
SamplesPerSymbol: 100
SymbolRate: 100
SymbolsPerTrace: 2
MinimumAmplitude: -1.5000
MaximumAmplitude: 1.5000
AmplitudeResolution: 0.0100
MeasurementDelay: 0.0060
OperationMode: 'Real Signal'
PlotType: '2D Color'
PlotTimeOffset: 0
RefreshPlot: 'on'
PlotPDFRange: [0 1]
ColorScale: 'log'
SamplesProcessed: 0
Measurements: [1x1 commscope.eyemeasurements]
MeasurementSetup: [1x1 commscope.eyemeasurementsetup]
249
5.DESIGN OF ASK, PSK, FSK, QPSK USING MATLAB
AIM:
To write a program in MATLAB for design of ASK,PSK,FSK.and QPSK
Baseband Versus Passband Simulation
For a given modulation technique, two ways to simulate modulation techniques are
called baseband and passband. Baseband simulation requires less computation. The
MATLAB_ Communication toolbox supports baseband simulation for digital
modulation and passband simulation for analog modulation. In this tutorial, baseband
simulation will be used.
PROGRAM:
ASK:
clc
clear all;
close all;
N=10;
x=randint(1,N);
k=1;
for t=0.01:0.01:10
c(k)=sin(2*pi*t);
k=k+1;
end
for j=1:1:N
if x(j)==0
for i=(j-1)*100+1:1:j*100
y(i)=0;
tr(i)=0;
end
end
250
if x(j)==1
for i=(j-1)*100+1:1:j*100
y(i)=1;
tr(i)=c(i);
end
end
end
for i=1:1:1000
re(i)=tr(i)*c(i);
end
for j=1:1:N
d=0;
for i=(j-1)*100+1:1:j*100
d=d+re(i)
end
if d>0.5
det(j)=1;
else
det(j)=0;
end
end
for j=1:1:N
if det(j)==0
for i=(j-1)*100+1:1:j*100
det(i)=0;
end
end
if x(j)==1
for i=(j-1)*100+1:1:j*100
det(i)=1;
end
251
end
end
subplot(5,1,1);
plot(y);
title('message Signal');
subplot(5,1,2);
plot(c);
title('Carrier Signal');
subplot(5,1,3);
plot(tr);
title('Transmitted Signal');
subplot(5,1,4);
plot(re);
title('Received Signal');
subplot(5,1,5);
plot(det);
title('Detected Signal');
252
FSK
clc
clear all
close all
N=10;
x=randint(1,N);
k=1;
for t=0.01:0.01:10
c1(k)=sin(2*pi*t);
c2(k)=sin(4*pi*t);
k=k+1;
end
253
for j=1:1:N;
if x(j)==0
for i=(j-1)*100+1:1:j*100
y(i)=0;
tr(i)=c2(i);
end
end
if x(j)==1
for i=(j-1)*100+1:1:j*100
y(i)=1;
tr(i)=c1(i);
end
end
end
for i=1:1:1000
re(i)=tr(i)*c1(i)*c2(i);
end
for j=1:1:N
d=0;
for i=(j-1)*100+1:1:j*100
d=d+re(i);
end
if d>0.5
det(j)=1;
else
det(j)=0;
end
end
for j=1:1:N
254
if det(j)==0
for i=(j-1)*100+1:1:j*100
det(i)=0;
end
end
if x(j)==1
for i=(j-1)*100+1:1:j*100
det(i)=1;
end
end
end
subplot(6,1,1);
plot(y);
title('message signal');
subplot(6,1,2);
plot(c1);
title('Carrier Signal-1');
subplot(6,1,3);
plot(c2);
title('Carrier Signal-2');
subplot(6,1,4);
plot(tr);
subplot(6,1,5);
plot(re);
subplot(6,1,6);
plot(det);
255
PSK
clc
clear all;
close all;
N=10;%No.of Data
x=randint(1,N);
k=1;
for t=0.01:0.01:10
c(k)=2*sin(2*pi*t);
k=k+1;
end
for j=1:1:N
if x(j)==0
for i=(((j-1)*100)+1):1:(j*100)
y(i)=0;
tr(i)=-c(i);
end
else
256
for i=(((j-1)*100)+1):1:(j*100)
y(i)=1;
tr(i)=c(i);
end
end
end
for i=1:1:1000
re(i)=tr(i)*c(i);
end
for j=1:1:N
d=0;
for i=(((j-1)*100)+1):1:(j*100)
d=d+re(i)
end
if d>=0
det(j)=1;
else
det(j)=0;
end
end
for j=1:1:N
if det(j)==0
for i=(((j-1)*100)+1):1:(j*100)
det(i)=0;
end
end
if x(j)==1
for i=(((j-1)*100)+1):1:(j*100)
det(i)=1;
end
257
end
end
subplot(5,1,1);
plot(y);
title('Message Signal');
subplot(5,1,2);
plot(c);
title('Carrier Signal');
subplot(5,1,3);
plot(tr);
subplot(5,1,4);
plot(re);
subplot(5,1,5);
plot(det);
258
QPSK
clc
clear all;
close all;
N=20;
X=randint(1,N);
L=100;
l=(N/2*L*0.01)-0.01
i=1;
for t=0:0.01:1
I(i)=cos(2*pi*t);
i=i+1;
end
i=1;
for t=0:0.01:1
Q(i)=sin(2*pi*t);
i=i+1;
end
for i=1:N/2
if X((i-1)*2+1)==1
for j=((i-1)*L+1):(i*L)
259
y(j)=1;
QMI(j)=y(j)*I(j);
end
else
for j=((i-1)*L+1):(i*L)
y(j)=-1;
QMI(j)=y(j)*I(j);
end
end
k=((i-1)*2)+2;
if X(k)==1
for j=((i-1)*L+1):(i*L)
y(j)=1;
QMQ(j)=y(j)*Q(j);
end
else
for j=((i-1)*L+1):(i*L)
y(j)=-1;
QMQ(j)=y(j)*Q(j);
end
end
end
for i=1:(N/2*L)
QP(i)=QMI(i)+QMQ(i);
end
for i=1:(N/2*L)
re1(i)=QP(i)*I(i);
reQ(i)=QP(i)*Q(i);
end
k=1;
for i=1:N/2
260
rI=0;
rQ=0;
for j=((i-1)*L+1):(i*L)
rI=rI+re(j);
rQ=rQ+reQ(j);
end
if rI>=0
real(i)=1;
else
real(i)=0;
end
if rQ>=0
imag(i)=1;
else
imag(i)=0;
end
det(k)=real(i);
det(k+1)=imag(i);
k=k+2;
end
RESULT:
Thus the ASK,PSK,QPSK and FSK was designed using MATLAB.
261
6.ERROR CONTROL CODING USING MATLAB
AIM:
To write a program in MATLAB for error control coding techniques.
Error Control
• Detection Versus Correction
– Detection: error ? yes or no
– Correction: Need to know the exact number of bits that are corrupted, and
their location in the message
• Forward Error Correction Versus Retransmission
– Retransmission (resending) : Backward error correction
• Coding for redundancy
– Block coding: discussed in our textbook
– Convolution coding
Block Coding
• Divide the message into blocks, each of k bits, called datawords.
• Add r redundant bits to each block to make the length n = k + r. The resulting n-
bit blocks are called codewords
• Example: 4B/5B block coding
– k = 4 and n = 5.
2k = 16 datawords and 2n = 32 codewords
ALGORITHM:
1.Get the input binary sequcence.
2.Calculate the reundancy bits for the corrosponding code.
3.Transmit the signal that contains message bits+redundancy bits added at the end.
4.Calculate the redundancy bits once again for the received bits.
262
5.If the redundancy bits=‟0‟ then no error in the transmission otherwise some error in
the transmission.
PROGRAM:
clc;
clear all;
close all;
k=input('Number of message bits');
n=input('Number of coded bits');
P=[1 1 1;0 1 1;1 0 1;1 1 0]
G=[eye(k) P]
for i=1:2^k
str=dec2base(i-1,2,4);
for j=1:k
m(i,j)=str(j);
end
end
for i=1:(2^k)
for r=1:n
o=0;
for j=1:k
o=o+(m(i,j)*G(j,r));
end
c(i,r)=mod(o,2);
end
end
e=zeros(n,n)
for i=1:n
e(i,i)=1;
end
% Syndrome Table
H=[P' eye(n-k)];
263
H1=H';
for i=1:n
for r=1:n-k
o=0;
for j=1:n
o=o+(e(i,j)*H1(j,r));
end
er(i,r)=mod(o,2);
end
end
for i=1:n
rec1=c(2^k,i)+e(1,i);
rec(1,i)=mod(rec1,2);
end
for i=1:1
for r=1:n-k
o=0;
for j=1:n
o=o+(rec(i,j)*H1(j,r));
end
sy(i,r)=mod(o,2);
end
end
i=1;
j=1;
while sy(1,j)==er(i,j)&&sy(1,j+1)==er(i,j+1)&&sy(1,j+2)==er(i,j+2)
rec_er=e(i,:);
i=i+1;
end
rec_er
%Error Corrected Message
264
for i=1:n
Det=rec(1,i)+rec_er(1,i);
det_rec(1,i)=mod(Det,2);
end
det_rec
RESULT:Thus the error control coding techniques are executed using MATLAB
programs.
Introduction To Matlab Simulink
Simulink is a program that runs as a companion to MATLAB, these programs are

developed and marketed by the MathWorks, Inc. Simulink and MATLAB form a package
that serves as a vehicle for modeling dynamic systems. Simulink provides a graphical
user interface (GUI) that is used in building block diagrams, performing simulations, as
well as analyzing results. In Simulink, models are hierarchical so you can view a system
at a high level, then double-click on blocks by using the mouse to go down through the
design levels. This document is a tutorial that was written for the introductory controls
theory class at Worcester Polytechnic Institute.
An Example
To get you started in using Simulink, this tutorial guides you through a simple
example. The point of the example is to introduce you to many of the important concepts
associated with Simulink. As you become more familiar with Simulink you will probably
want to dig into more advanced documentation, this is not a problem as advanced
documentation is available online. The figure below shows the model that you will enter.
The model has a Sine Wave block which provides a signal which is integrated. The
multiplexer (Mux) block forms a vector signal so that the scope block will display the
sine-wave signal IN as well as the integrated output OUT.
265
Figure 6.1: Block diagram of first model
6.1.2 Getting Stared with Simulink
Introduction
In this first step, you start MATLAB and then start Simulink. A short discussion of the
significance of blocks is presented. The notion of having a block selected is presented.
You will move, copy, and delete model blocks, lastly you will learn how to save and
name your design by using the save-as command.
Starting Up Simulink
Before starting Simulink, you must start MATLAB. For the following, it is assumed that
you are running Windows 95. This document was written on a machine that has
MATLAB 5.1 installed, if your machine has a newer version make the substitution when
you select the following with your mouse.
Start => Programs => MATLAB 7.1 => MATLAB
With MATLAB running there are three ways to start Simulink.
 You may click on the Simulink icon in the MATLAB toolbar.

 You may enter the command simulink at the MATLAB prompt.
 You may specify an existing Simulink file. We will do this later, for now pick one of
the other options.
266
After MATLAB finishes processing the command, your desktop will include the
MATLAB command window, a new empty model window, and the Simulink block library
window, shown below.
Figure 6.2: Simulink block library
In Simulink, blocks are used to build up a model. Unlike the blocks in a diagram
that we draw by hand, the blocks in Simulink are active and allow the program to
simulate the behavior of the entire system. In the Simulink library window the icons each
refer to a different block library, each of which contains a class of blocks. For now we will
only consider the libraries used to build the first model, the libraries are listed below.
Source type blocks produce input signals.

The Sine Wave block is a source type block.
Sink type blocks provide a place for output.

The scope block is a sink type block.
Linear type blocks perform a linear transformation.

The Integrator is a linear type block.
Connection type blocks are involved with forming

vector signals, the Mux block is an example.
267
The descriptive titles Sources and Sinks deserve a special comment as they do
not refer to power supplies. Remember that while power supplies are important in real
circuits, in drawing a block diagram we are concerned only with signals that convey
information in some way. Block diagrams are necessarily abstract in form, this
abstraction greatly simplifies the analysis.
In developing a block diagram, we use source type blocks to produce the input
signals. Conversely, sink type blocks provide a place for a model to have output appear.
Linear type blocks perform a linear transformation on signals. Lastly, the connections
type blocks are used for switching and forming vector signals.
Adding a block from a library
To open a block library, double click on the associated library icon in the Simulink block
library window. After opening the Sources library, the Sources library window opens, as
shown below. Go ahead and double click on the icon if you have not already done so.
Figure 6.3: Sources library window
268
To add the first block to the diagram, point the mouse at the Sine Wave block in
the Sources library window and press the left mouse button. Without releasing the left
mouse button, drag the mouse to the new model window and release the mouse button.
Figure 6.4 Diagram window with Sine Wave block
Deleting a Block
Another useful command is delete. To delete a block, select it and then press the
backspace or the delete key. If a group of blocks is selected, the delete command will
delete all the selected blocks. Make sure to get some practice selecting blocks, copying,
and deleting. When you are ready to move on, leave one copy of the Sine Wave block in
the diagram window and delete the rest.
Undoing and Redoing
Now that you know how to delete objects, to get yourself out of trouble, you will
want to know about the Undo command. The Simulink documentation indicates that you
can cancel the effects of up to 101 consecutive operations by choosing Undo from the
Edit menu. The following is a list of some of the operations that may be undone.
 Adding or deleting a block

 Adding of deleting a line
 Adding or deleting annotation
 Changing the name of a block
269

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(An Autonomous Institution approved by UGC and affiliated to JNTUH))

(Accredited by NAAC with ‘A” Grade, Accredited by NBA of AICTE and

DEPARTMENT OF ELECTRONICS & COMMUNICATION

MICROPROCESSORS & MICROCONTROLLERS

The significance of the Microprocessors and Microcontrollers Lab is renowned in the

GUIDELINES TO WRITE YOUR OBSERVATION BOOK

Mission of the Department

Attainment B. Tech (ECE) Programme Outcomes

1. Engineering knowledge: Apply the knowledge of mathematics, science,

Expected level of Attainment of B. Tech (ECE) Program Specific Outcomes (PSOs)

PSO1: Should be able to gain the in-depth knowledge in core subjects to

Mapping of Course Outcomes with Program Outcomes

Write ALP and execute the program to

 Familiarize the architecture of 8086 processor, assembling language

 Analyze and apply working of 8086.

C:\MASM\BIN> Edit filename. Asm Enter

With this command assembler generates three files.

Run File [ Filename1.exe] : “filename1.exe”

Creation of Library: Refer Modular Programming Section

Next Run C:\MASM\BIN> filename

a) One method uses MODELS and

a) Format using Models:

; ABSTRACT ; 8086 program

ASSEMBLY LANGUAGE PROGRAM DEVELOPMENT TOOLS:

It is also provided with peripherals and controllers such as

8251A: Programmable communication Interface for serial communication.

Working on 8086/88 Microprocessor kit:

Procedure to execute a program:

Procedure to check the result:

Configuration ESA 86/88-2

ESA 86/88-2-microcomputer trainer is versatile and can be configured in a number of ways, as

Operational mode selection

SW4 of the DIP switch Operational mode

1. OFF Serial mode

SW5 of the DIP Switch Printer Driver

Baud rate selection

1. SW3 SW2 SW1 Baud rate

8255 operational modes

8255 ports can be initialized in three different modes.

USING DEBUG TO EXECUTE 80X86 PROGRAMS:

1.1 8-BIT ADDITION

ASSUME CS: CODE, DS: DATA

RESULT: 0FFFFH 1111 1111 1111 1111 1111

ASSUME DS:DATA, CS:CODE

1.5 16-BIT SUBTRACTION

1.6 32 BIT SUBTRACTIONS

1.9 8-BIT DIVISION (16 Bit by 8 Bit)

1.10 16-BIT DIVISION (32 Bit by 16 Bit)

1.11 Find Square of a number

ASSUME CS:CODE, DS:DATA

2.2 DISPLAY OF SQUARES OF N. NUMBERS

2.3 SORTING IN ASCENDING ORDER

START:MOV AX,DATA ;STARTING ADDRESS OF DATA SEGMENT

NXTCMP: MOV AL,ARR[SI]

START:MOV AX,DATA ;STARTING ADDRESS OF DATA SEGMENT

2.5 SQUARE ROOT OF A GIVEN NUMBER

3. BCD, DECIMAL,ASCII OPERATIONS

3.2 BCD Subtraction

3.3 BCD TO ASCII CONVERSION