Unit-2

Arithmetic Logic Unit (ALU)

Inside a computer, there is an Arithmetic Logic Unit (ALU), which is capable of performing logical
operations (e.g. AND, OR, Ex-OR, Invert etc.) in addition to the arithmetic operations (e.g.
Addition, Subtraction etc.). The control unit supplies the data required by the ALU from memory,
or from input devices, and directs the ALU to perform a specific operation based on the
instruction fetched from the memory. ALU is the “calculator” portion of the computer.

An arithmetic logic unit(ALU) is a major component of the central processing unit of the a
computer system. It does all processes related to arithmetic and logic operations that need to be
done on instruction words. In some microprocessor architectures, the ALU is divided into the
arithmetic unit (AU) and the logic unit (LU).

ALU is also known as an Integer Unit (IU). The arithmetic logic unit is that part of the CPU that
handles all the calculations the CPU may need. Most of these operations are logical in nature.
Depending on how the ALU is designed, it can make the CPU more powerful, but it also
consumes more energy and creates more heat. Therefore, there must be a balance between
how powerful and complex the ALU is and how expensive the whole unit becomes. This is why
faster CPUs are more expensive, consume more power and dissipate more heat.

Different operation as carried out by ALU can be categorized as follows –

 logical operations − These include operations like AND, OR, NOT, XOR, NOR, NAND, etc.

 Bit-Shifting Operations − This pertains to shifting the positions of the bits by a certain
number of places either towards the right or left, which is considered a multiplication or
division operations.

 Arithmetic operations − This refers to bit addition and subtraction. Although

multiplication and division are sometimes used, these operations are more expensive to
make. Multiplication and subtraction can also be done by repetitive additions and
subtractions respectively
Carry Look-Ahead Adder

Carry Look-ahead Adder :

A carry look-ahead adder reduces the propagation delay by introducing more complex hardware.
In this design, the ripple carry design is suitably transformed such that the carry logic over fixed
groups of bits of the adder is reduced to two-level logic. Let us discuss the design in detail.

Consider the full adder circuit shown above with corresponding truth table. We define two
variables as ‘carry generate’ and ‘carry propagate’ then,

The sum output and carry output can be expressed in terms of carry generate and carry
propagate as

From the above Boolean equations we can observe that does not have to wait for and to
propagate but actually is propagated at the same time as and Since the Boolean expression for
each carry output is the sum of products so these can be implemented with one level of AND
gates followed by an OR gate.

The implementation of three Boolean functions for each carry output ( and for a carry look-ahead
carry generator shown in below figure.

Time Complexity Analysis :

We could think of a carry look-ahead adder as made up of two “parts”

1. The part that computes the carry for each bit.

2. The part that adds the input bits and the carry for each bit position.

The complexity arises from the part that generates the carry, not the circuit that adds the bits.
Now, for the generation of the carry bit, we need to perform a AND between (n+1) inputs. The
complexity of the adder comes down to how we perform this AND operation. If we have AND
gates, each with a fan-in (number of inputs accepted) of k, then we can find the AND of all the bits
in time. This is represented in asymptotic notation as .

Advantages and Disadvantages of Carry Look-Ahead Adder :

Advantages –

 The propagation delay is reduced.

 It provides the fastest addition logic.

Disadvantages –

 The Carry Look-ahead adder circuit gets complicated as the number of variables increase.

 The circuit is costlier as it involves more number of hardware

Multiplication Algorithm in Signed Magnitude Representation

Multiplication of two fixed point binary number in signed magnitude representation is done with
process of successive shift and add operation.

In the multiplication process we are considering successive bits of the multiplier, least significant
bit first.
If the multiplier bit is 1, the multiplicand is copied down else 0’s are copied down.

The sign of the product is determined from the sign of the multiplicand and multiplier. If they are
alike, sign of the product is positive else negative.

Hardware Implementation :
Following components are required for the Hardware Implementation of multiplication algorithm :

1. Registers:
Two Registers B and Q are used to store multiplicand and multiplier respectively.
Register A is used to store partial product during multiplication.
Sequence Counter register (SC) is used to store number of bits in the multiplier.

2. Flip Flop:
To store sign bit of registers we require three flip flops (A sign, B sign and Q sign).
Flip flop E is used to store carry bit generated during partial product addition.

3. Complement and Parallel adder:

This hardware unit is used in calculating partial product i.e, perform addition required.
Flowchart of Multiplication:

1. Initially multiplicand is stored in B register and multiplier is stored in Q register.

2. Sign of registers B (Bs) and Q (Qs) are compared using XOR functionality (i.e., if both the
signs are alike, output of XOR operation is 0 unless 1) and output stored in As (sign of A
register).

Note: Initially 0 is assigned to register A and E flip flop. Sequence counter is initialized with
value n, n is the number of bits in the Multiplier.

3. Now least significant bit of multiplier is checked. If it is 1 add the content of register A with
Multiplicand (register B) and result is assigned in A register with carry bit in flip flop E.
Content of E A Q is shifted to right by one position, i.e., content of E is shifted to most
significant bit (MSB) of A and least significant bit of A is shifted to most significant bit of Q.

4. If Qn = 0, only shift right operation on content of E A Q is performed in a similar fashion.

5. Content of Sequence counter is decremented by 1.

6. Check the content of Sequence counter (SC), if it is 0, end the process and the final product
is present in register A and Q, else repeat the process.
Booth’s Algorithm

Booth algorithm gives a procedure for multiplying binary integers in signed 2’s complement
representation in efficient way, i.e., less number of additions/subtractions required. It operates
on the fact that strings of 0’s in the multiplier require no addition but just shifting and a string of
1’s in the multiplier from bit weight 2^k to weight 2^m can be treated as 2^(k+1 ) to 2^m.

As in all multiplication schemes, booth algorithm requires examination of the multiplier bits and
shifting of the partial product. Prior to the shifting, the multiplicand may be added to the partial
product, subtracted from the partial product, or left unchanged according to following rules:

1. The multiplicand is subtracted from the partial product upon encountering the first least
significant 1 in a string of 1’s in the multiplier

2. The multiplicand is added to the partial product upon encountering the first 0 (provided
that there was a previous ‘1’) in a string of 0’s in the multiplier.

3. The partial product does not change when the multiplier bit is identical to the previous
multiplier bit.

Hardware Implementation of Booths Algorithm – The hardware implementation of the booth

algorithm requires the register configuration shown in the figure below.
Booth’s Algorithm Flowchart –

We name the register as A, B and Q, AC, BR and QR respectively. Qn designates the least
significant bit of multiplier in the register QR. An extra flip-flop Qn+1is appended to QR to facilitate
a double inspection of the multiplier.The flowchart for the booth algorithm is shown below.

AC and the appended bit Qn+1 are initially cleared to 0 and the sequence SC is set to a number n
equal to the number of bits in the multiplier. The two bits of the multiplier in Qn and Qn+1are
inspected. If the two bits are equal to 10, it means that the first 1 in a string has been
encountered. This requires subtraction of the multiplicand from the partial product in AC. If the 2
bits are equal to 01, it means that the first 0 in a string of 0’s has been encountered. This requires
the addition of the multiplicand to the partial product in AC.

When the two bits are equal, the partial product does not change. An overflow cannot occur
because the addition and subtraction of the multiplicand follow each other. As a consequence, the
2 numbers that are added always have a opposite signs, a condition that excludes an overflow.
The next step is to shift right the partial product and the multiplier (including Qn+1). This is an
arithmetic shift right (ashr) operation which AC and QR ti the right and leaves the sign bit in AC
unchanged. The sequence counter is decremented and the computational loop is repeated n
times.
Example – A numerical example of booth’s algorithm is shown below for n = 4. It shows the step
by step multiplication of -5 and -7.

MD = -5 = 1011, MD = 1011, MD'+1 = 0101

MR = -7 = 1001

The explanation of first step is as follows: Qn+1

AC = 0000, MR = 1001, Qn+1 = 0, SC = 4

Qn Qn+1 = 10

So, we do AC + (MD)'+1, which gives AC = 0101

On right shifting AC and MR, we get

AC = 0010, MR = 1100 and Qn+1 = 1

OPERATION AC MR QN+1 SC

0000 1001 0 4

AC + MD’ + 1 0101 1001 0

ASHR 0010 1100 1 3

AC + MR 1101 1100 1

ASHR 1110 1110 0 2

ASHR 1111 0111 0 1

AC + MD’ + 1 0010 0011 1 0

Product is calculated as follows:

Product = AC MR Product = 0010 0011 = 35

Division Algorithm For Unsigned Integer

A division algorithm provides a quotient and a remainder when we divide two number. They are
generally of two type slow algorithm and fast algorithm. Slow division algorithm are restoring,
non-restoring, non-performing restoring, SRT algorithm and under fast comes Newton–Raphson
and Goldschmidt.

In this article, will be performing restoring algorithm for unsigned integer. Restoring term is due to
fact that value of register A is restored after each iteration.

Here, register Q contain quotient and register A contain remainder. Here, n-bit dividend is loaded
in Q and divisor is loaded in M. Value of Register is initially kept 0 and this is the register whose
value is restored during iteration due to which it is named Restoring.
Let’s pick the step involved:

 Step-1: First the registers are initialized with corresponding values (Q = Dividend, M =
Divisor, A = 0, n = number of bits in dividend)

 Step-2: Then the content of register A and Q is shifted left as if they are a single unit

 Step-3: Then content of register M is subtracted from A and result is stored in A

 Step-4: Then the most significant bit of the A is checked if it is 0 the least significant bit of Q
is set to 1 otherwise if it is 1 the least significant bit of Q is set to 0 and value of register A is
restored i.e the value of A before the subtraction with M

 Step-5: The value of counter n is decremented

 Step-6: If the value of n becomes zero we get of the loop otherwise we repeat from step 2

 Step-7: Finally, the register Q contain the quotient and A contain remainder

Examples:

Perform Division Restoring Algorithm

Dividend = 11

Divisor = 3

N M A Q OPERATION

4 00011 00000 1011 initialize

00011 00001 011_ shift left AQ

00011 11110 011_ A=A-M

00011 00001 0110 Q[0]=0 And restore A

3 00011 00010 110_ shift left AQ

N M A Q OPERATION

00011 11111 110_ A=A-M

00011 00010 1100 Q[0]=0

2 00011 00101 100_ shift left AQ

00011 00010 100_ A=A-M

00011 00010 1001 Q[0]=1

1 00011 00101 001_ shift left AQ

00011 00010 001_ A=A-M

00011 00010 0011 Q[0]=1

Floating-point arithmetic

In computing, floating-point arithmetic (FP) is arithmetic using formulaic representation of real

numbers as an approximation to support a trade-off between range and precision. For this
reason, floating-point computation is often found in systems which include very small and very
large real numbers, which require fast processing times. A number is, in general, represented
approximately to a fixed number of significant digits (the significand) and scaled using
an exponent in some fixed base; the base for the scaling is normally two, ten, or sixteen.
FLOATING POINT ADDITION AND SUBTRACTION

 FLOATING POINT ADDITION

To understand floating point addition, first we see addition of real numbers in decimal as same
logic is applied in both cases.

For example, we have to add 1.1 * 103 and 50.

We cannot add these numbers directly. First, we need to align the exponent and then, we can add
significand.

After aligning exponent, we get 50 = 0.05 * 103

Now adding significand, 0.05 + 1.1 = 1.15

So, finally we get (1.1 * 103 + 50) = 1.15 * 103

Here, notice that we shifted 50 and made it 0.05 to add these numbers.

Now let us take example of floating point number addition

We follow these steps to add two numbers:

1. Align the significand

2. Add the significands

3. Normalize the result

FLOATING POINT SUBTRACTION

Subtraction is similar to addition with some differences like we subtract mantissa unlike addition
and in sign bit we put the sign of greater number.

Let the two numbers be

x = 9.75
y = – 0.5625

Converting them into 32-bit floating point representation

9.75’s representation in 32-bit format = 0 10000010 00111000000000000000000

– 0.5625’s representation in 32-bit format = 1 01111110 00100000000000000000000

(10000010 – 01111110)2 = (4)10

IEEE Standard 754 Floating Point Numbers

The IEEE Standard for Floating-Point Arithmetic (IEEE 754) is a technical standard for floating-point
computation which was established in 1985 by the Institute of Electrical and Electronics
Engineers (IEEE). The standard addressed many problems found in the diverse floating point
implementations that made them difficult to use reliably and reduced their portability. IEEE
Standard 754 floating point is the most common representation today for real numbers on
computers, including Intel-based PC’s, Macs, and most Unix platforms.

There are several ways to represent floating point number but IEEE 754 is the most efficient in
most cases. IEEE 754 has 3 basic components:

1. The Sign of Mantissa –

This is as simple as the name. 0 represents a positive number while 1 represents a negative
number.

2. The Biased exponent –

The exponent field needs to represent both positive and negative exponents. A bias is
added to the actual exponent in order to get the stored exponent.

3. The Normalised Mantissa –

The mantissa is part of a number in scientific notation or a floating-point number, consisting
of its significant digits. Here we have only 2 digits, i.e. O and 1. So a normalised mantissa is
one with only one 1 to the left of the decimal.

IEEE 754 numbers are divided into two based on the above three components: single precision
and double precision.
Special Values: IEEE has reserved some values that can ambiguity.

 Zero –
Zero is a special value denoted with an exponent and mantissa of 0. -0 and +0 are distinct
values, though they both are equal.

 Denormalised –
If the exponent is all zeros, but the mantissa is not then the value is a denormalized
number. This means this number does not have an assumed leading one before the binary
point.

 Infinity –
The values +infinity and -infinity are denoted with an exponent of all ones and a mantissa of
all zeros. The sign bit distinguishes between negative infinity and positive infinity.
Operations with infinite values are well defined in IEEE.

 Not A Number (NAN) –

The value NAN is used to represent a value that is an error. This is represented when
exponent field is all ones with a zero sign bit or a mantissa that it not 1 followed by zeros.
This is a special value that might be used to denote a variable that doesn’t yet hold a value.