CMPT 300: Operating Systems I Assignment 3: Policies

CMPT 300: Operating Systems I
Assignment 3
Due July 26, 2018
POLICIES:
1. Coverage
Chapters 7-9
2. Grade
10 points, 100% counted into the final grade
3. Individual or Group
Individual based, but group discussion is allowed and encouraged
4. Academic Honesty
Violation of academic honesty may result in a penalty more severe than zero
credit for an assignment, a test, and/or an exam.
5. Submission
Electronic copy via CourSys
6. Late Submission
2-point deduction for late submission within one week;
5-point deduction for late submission over one week;
Deduction ceases upon zero;
Late submissions after the sample solution is available will NOT be graded.
QUESTIONS:
1. 2 points
Consider the following snapshot of a system:
Allocation Max
ABCD ABCD
P0 3014 5117
P1 2210 3211
P2 3121 3321
P3 0510 4512
P4 4212 6325
Using the banker's algorithm, determine whether or not each of the following
states is unsafe. If the state is safe, illustrate the order in which the processes may
complete.
a. Available = (0, 3, 0, 1)
b. Available = (1, 0, 0, 2)
[Grading Rubric: 1 point per state. If a safe sequence exists, BOTH the
correct safe sequence AND the derivation steps are required.]
2. 2 points
Consider a system with a number r of resources of the same type. These resources
are shared by a number p of processes. A process can request or release only one
resource at a time. Prove that the system is deadlock free given the following two
conditions:
a. The number of the maximum need of each process is in [1, r];
b. The sum of all maximum needs is less than r + p.
[Grading Rubric: 2 points if a correct proof is provided. 0 point otherwise.]
3. 1 point
Why are page sizes always powers of 2?
Consider a logical address space of 64 pages of 1,024 words each, mapped onto a
physical memory of 32 frames.
a. How many bits are there in the logical address?
b. How many bits are there in the physical address?
[Grading Rubric: 1 point if ALL three subquestions are correctly answered
with necessary derivations. 0 point otherwise.]
4. 1 point
Given six memory partitions of 300 KB, 600 KB, 350 KB, 200 KB, 750 KB, and
125 KB (in order), how would the first-fit, best-fit, and worst-fit algorithms place
processes of size 115 KB, 500 KB, 358 KB, 200 KB, and 375 KB (in order)?
[Grading Rubric: 1 point if ALL three placement decisions are correctly
determined. 0 point otherwise.]
5. 1 point
Consider the two-dimensional array A:
int A[][] = new int[100][100];
where A[0][0] is at location 200 in a paged memory system with pages of size
200. A small process that manipulates the matrix resides in page 0 (locations 0 to
199). Thus, every instruction fetch will be from page 0.
For three page frames, how many page faults are generated by the following
array-initialization loops? Use LRU replacement, and assume that page frame 1
contains the process and the other two are initially empty.
[Grading Rubric: 1 point if ALL A two su
ubquestionss are correectly answeered
with necesssary derivvations. 0 pooint otherw
wise.]
6. 1 point
Consider thhe followinng page reference string g:
7, 2, 3, 1, 2,
2 5, 3, 4, 6,, 7, 7, 1, 0, 5,
5 4, 6, 2, 3,, 0, 1.
Assuming demand paaging with three t frames, how manny page faults would occur
o
for the folllowing replaacement alggorithms?
a. LRU repplacement
b. FIFO replacement
c. Optimall replacemennt
[Grading Rubric: 1 point if AL LL three su ubquestion
ns are correectly answeered
with illusttrations simmilar as thee following figure. 0 pooint otherw wise.]
7. 2 points
In a multillevel cache system, thee CPU firstt sends the memory reqquest to lev vel 1
cache. If itt is a cache hit, the datta is transfeerred to the CPU. If it iis a cache miss,
m
the CPU will
w send thee same mem mory requesst to level 2 cache. If itt is still a caache
miss there, the CPU willw furtherr send the memorym reqquest to low
wer level caaches
until a cachhe hit happeens or mem mory access takes
t place..
A limitatioon of the preeceding muultilevel caching is thatt, even thouugh a data block
b
is cached in
i some low wer level caache, the system still needs to enddure all the time
cost by thhe memory request gooing through h all higher level caches with caache
misses. Simmilarly, eveen if a data block is nott cached, thhe CPU stilll sends mem
mory
request to one level of cache after a another, taking likely a lonng time beefore
accessing the
t memoryy.
Design a possible soolution agaiinst the preceding lim

mitation andd show how it
speeds up the
t averagee memory acccess time.
[Grading Rubric: Op pen questioon! Time too convince the
t TA.]

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