Effects of Gaussian Doping Profile on the

Performance of Triple Metal Double Gate TFET

Sudipta Ghosh1, Priyanka Saha2, Supratim Kundu1, Prithviraj Pachal1, P.Venkateswaran2, Subir Kumar Sarkar2
1Department of Electronics and Communication Engineering, Meghnad Saha Institute of Technology, Kolkata, India
2Department of Electronics and Telecommunication Engineering, Jadavpur University, Kolkata, India

[email protected], [email protected], [email protected], [email protected], [email protected],

[email protected]

Abstract—Tunneling field effect transistor (TFETs) has current, several improvisation have been proposed, one of
recently intrigued interest because of their implicit use in low which is gate-drain overlap structure [6-8], but it has a
power logic applications. This paper proposes Triple Metal major drawback of low current driving capacity. Another
Double Gate TFET (TMDGFET) structure where the drain technique developed to suppress the ambipolar current is
has been subjected to two different Gaussian doping profiles
developing a gaussian doped drain TFET [1-2][9] but it has
and the effect for the same has been studied. The Gaussian
doping at the drain region reduces the ambipolar current as a major drawback of very low ON current.
well as the OFF current significantly without compromising
the ON- state current. It has also been revealed that the In this paper, we propose a TMDGFET structure with
introduction of a small density layer at the region of the gaussian doping profile in the drain region along with a small
channel-source junction has improved the ON current by a few high density layer in the source-channel junction to reduce
orders of magnitude. the ambipolar current and subsequent improvement in the
ON current. In order to reduce OFF current due to lower
Keywords—TFET, Gaussian Doping, Ambipolar Current, Band- leakage, a gate tunable barrier in the channel region is also
to-Band Tunneling. adopted here.
I. INTRODUCTION
Today’s nanoscale industry is revolutionized by the use
II. DEVICE STRUCTURE AND PARAMETERS
of Tunneling (T) Field Effect Transistors (FETs) on a large
scale, shadowing out the usage of the conventional Metal
Oxide Semiconductor (MOS) FETs because of their
performance limitation. The attributes of MOS devices have
atrophied due to adversarial scaling, as a result of which the
MOS devices are contrived by various short-channel effects
(SCEs) alike surface scattering, drain-induced barrier
lowering (DIBL) and so on. The gate leakage current of
MOS devices has also escalated due to this fierce spanning
and the carrier injection in MOS devices is chiefly
commanded by thermionic emission over the potential
Fig.1. Device schematic of TMDGFET.
barrier and hence the converse subthreshold slope is
bounded at room temperature to 60mV/decade.

TFET provides the benefit of current conduction through

modulation of quantum-mechanical band to band tunneling
phenomenon (BTBT). Thus, the current is primarily bridled
by the tunneling mechanism at the source-channel junction
because of the in-built tunnel barrier. The TFET is resistive
to short channel effects (SCEs), furthermore it can have
subthreshold swing lower than 60mV/decade. In addition to
this, it also exhibits very small leakage current in its OFF
Fig.2. Device schematic of TMDGFET with a layer of high density in the
state. Nevertheless, TFETs also have varied downsides alike channel region at source-channel junction and diagonally doped drain.
low ON current and high ambipolar current.

Various different techniques have been reported to

increase the ON current such as using heterojunction and
narrow band gap material [1-3] at the source-channel
interface to reduce the barrier, which in turn aids the
tunneling current considering the bandgap in other regions is
voluminous to burke the high OFF current [4]. Actuality of
gate tunable barrier in the channel region to confine the
conduction of the TFET device in directions of two is also
rehearsed in [5] as an effective performance boosting Fig.3. Device schematic of TMDGFET with a layer of high density in the
technique. To compensate the limitation of ambipolar channel region at source-channel junction and laterally doped drain.
 Figure 1 demonstrates the schematic view of TMDGFET function of Metal-1 and Metal-3 are intentionally made less
under study in this work. The double gate device consists of in comparison to the work function of Metal-2 so that the
three metals (Metal-1, Metal-2, Metal-3) possessing distinct ION/IOFF ratio can be enhanced by creating a barrier.
work functions over the channel. The front gate (gate-1) and
back gate (gate-2) consists of the three metals of distinct The electric field at the source-channel junction boosts
lengths L1, L2 and L3 respectively. Gate length (Lg) under owed to the inferior value of work function of Metal-1
study is 60nm with the length of source and drain being owing to supplements in band bending in that region. An
20nm each. The lengths for the metal contacts are 10nm (L1) improved value of work function for Metal-2 brings on a
for Metal-1, 30nm (L2) for Metal-2 and 20nm (L3) for Metal- barrier in the channel and an inferior value of work function
3.The channel region is lightly doped p-type silicon for Metal-3 begets a band-pass filter structure. The gate
possessing a doping concentration of 1× 1016 cm-3, the source voltage tunes the height of this barrier as exhibited in figure
is formed of highly doped p-type silicon having doping 6 and figure 7. Figure 8 and figure 9 show the profile of
concentration of 1 x 1020 cm-3, the drain is formed using surface potential for different values of Vds. As Vds
heavily doped n-type silicon possessing doping concentration increases, the potential increases only under Metal-3. The
of 5 x 1018 cm-3. A p-type small high density layer possessing proposed TMDGFET has four depletion regions in the body,
doping concentration of 1 x 1018 cm-3 is placed at the source- one is the source-channel depletion region, and three
channel junction in the channel region with length of layer depletion regions at the interface of the three metal contacts.
region being 5nm. Also, there are three channel regions under the three metal
contacts. The comparison in terms of the three doping
The drain layer is gaussian doped with doping profiles for surface potential is shown in figure 10.
concentration of 5 x 1018 cm-3 (p-type) diagonally with
lateral characteristic of 0.006 as shown in Fig.2 and laterally The variation of total electric field in respect of channel
with characteristic length of 0.001 and lateral characteristic length is shown in figure 11 and figure 12 for different
of 0.006 as shown in Fig.3. Body thickness considered here values of Vds. The region under Metal-1 creates more band-
(tsi) is 5nm. Both front gate and back gate oxide thickness are bending, wherefore the electric field is sufficiently high
equal (tox) being 2nm. The metal work functions are 4.4eV hither the source-channel junction, downgrading the
for Metal-1, 5.08eV for Metal-2 and 4.08eV for Metal-3. The tunneling path. The region under Metal-2 begets a tunneling
dielectric material used is SiO2 which has a dielectric barrier in the channel. On the other hand, Metal-3 has the
constant of 3.9. minutest work function of all the three metals, to reduce the
drain-channel tunneling. The comparison in terms of the
The simulations are accomplished using 2-D Silvaco three doping profiles for total electric field is shown in
Atlas version 5.19.20.R by including best suitable models figure 13. The Id-Vgs characteristics have been thought-out
alike non-local BTBT, Fermi-Dirac statistics, and Auger in the negative bias region for disparate doping profiles,
recombination model. which are explained in figure 14.

III. SIMULATION RESULT AND DISCUSSION

In the OFF state, the tunneling process does not take
place because there is no overlapping present between the
valence band of source and the conduction band of channel,
and also the reverse tunneling of carriers blocks the barrier
in the channel, thus commanding to a very small amount of
OFF state current, as explained in figure 4. In the ON state,
the height of the tunneling barrier is reduced because the
energy band of the channel region is pulled down by the
gate voltage. As a result of this reduction in the energy
barrier, the tunneling current is formed as the carriers can
tunnel from the valence band of source to the conduction Fig.4. Energy Band diagram comparison in OFF State of TFET devices
band of channel, as illustrated in figure 5. On placing a with disparate doping profiles.
gaussian doping profile instead of uniform doping profile in
drain region, the width of depletion region at channel-drain
junction escalates bringing on improved OFF state current
and the ambipolar conduction current is quite suppressed.

Also, if we place a small high density layer in the

channel region at the source-channel junction, the electric
field in the space charge region increases and the width of
the barrier between the source and channel becomes small,
resulting in the probability of carrier tunneling through the
forbidden gap escalates and hence the subthreshold slope
enhances and the ON state current escalates by a few orders.
In our proposed work, the gate comprises of three metals Fig.5. Energy Band diagram comparison in ON State of TFET devices with
corresponding to three distinct work functions. The work disparate doping profiles.
Fig.6. Surface Potential profile considering channel length Lg=60nm and Fig.10. Surface Potential profile considering channel length Lg=60nm,
Vds=0.5V concerning disparate gate voltages for Lateral gaussian doping. Vds=0.5V concerning Vgs=0.5V for disparate doping profiles.

Fig.7. Surface Potential profile considering channel length Lg=60nm and Fig.11. Total Electric Field profile considering channel length Lg=60nm
Vds=0.5V concerning disparate gate voltages for Diagonal gaussian doping. and Vgs=0.5V concerning disparate drain voltages for Lateral gaussian
doping.

Fig.8. Surface Potential profile considering channel length Lg=60nm and

Vgs=0.5V concerning disparate drain voltages for Lateral gaussian doping. Fig.12. Total Electric Field profile considering channel length Lg=60nm
and Vgs=0.5V concerning disparate drain voltages for Diagonal gaussian
doping.

Fig.9. Surface Potential profile considering channel length Lg=60nm and

Vgs=0.5V concerning disparate drain voltages for Diagonal gaussian
doping. Fig.13. Total Electric Field profile considering channel length Lg=60nm,
Vds=0.5V and Vgs=0.5V concerning disparate doping profiles.
Fig.14. Id-Vgs characteristics outlined on a log scale with Vds=0.5V Fig.17. Id-Vgs characteristics outlined on a linear scale with disparate work
concerning disparate doping profiles. function of metals concerning lateral gaussian doping.

Fig.15. Id-Vgs characteristics outlined on a log scale with Vds=0.5V, tsi=5nm Fig.18. Id-Vgs characteristics outlined on a linear scale with disparate work
considering Lateral gaussian doping and varying the oxide thickness. function of metals concerning diagonal gaussian doping.

Fig.16. Id-Vgs characteristics outlined on a log scale with Vds=0.5V, tox=2nm

considering Diagonal gaussian doping and varying the silicon thickness.
Fig.19. Ion and Ioff for disparate lateral characteristic lengths of lateral
It is ostensible from figure 14, that the negative gate bias gaussian doped TFET.
results in significantly reduced ambipolar conduction for the
diagonal gaussian doping in comparison to the lateral
gaussian doping, which suppresses the ambipolar current to
an extent but lesser than the diagonal gaussian doping. The
effect of drain gaussian doping along with the small high
density layer near the source-channel junction on the Ion, Ioff
and ambipolar conduction current is presented in Figure 14.

The variation of Id-Vgs characteristics in logarithmic

scale for disparate values of front and back gate oxide
thickness is unveiled in Figure 15. To attain a high Ion/Ioff
ratio in TFET, typically abatement in gate oxide thickness is
assiduous. Figure 16 exhibits the alteration of Id-Vgs
characteristics in logarithmic scale considering disparate
values of silicon thickness. To improve the current, by
downsizing the body thickness the bulk capacitive effect is Fig.20. Ion and Ioff for disparate lateral characteristic lengths of diagonal
gaussian doped TFET.
diminished.
 Figure 17 and figure 18 show the linear scale variation of
Id-Vgs characteristics by varying the work function of metals
for lateral and diagonal gaussian doping profiles. The ON
current improves by decreasing the work function of metals.
Figure 19 and figure 20 show the variation of I on and Ioff for
different lateral characteristic lengths of triple metal double
gate lateral and diagonal gaussian doped TFET.

Figure 21 and figure 22 show the variation of I on/Ioff and

subthreshold Slope for different lateral characteristic lengths
of triple metal double gate with lateral and diagonal
gaussian doped TFET.

Fig.24. Ion/Ioff and subthreshold slope for disparate characteristic lengths of

diagonal gaussian doped TFET.

The variation of Ion, Ioff for different characteristic

lengths of diagonal gaussian doped triple metal double gate
TFET is depicted in figure 23. Figure 24 depicts the
variation of Ion/Ioff and subthreshold slope for different
characteristic lengths of diagonal gaussian doped triple
metal double gate TFET.
IV. CONCLUSION
The proffered device unveils better performance over
conventional TMDGFET in terms of higher ON current and
Fig.21. Ion/Ioff and subthreshold slope for disparate lateral characteristic lower ambipolar current. It is evident that the TMDGFET
lengths of lateral gaussian doped TFET. with a small high density layer at the source-channel
junction and laterally doped gaussian drain has a better
Ion/Ioff ratio as compared to conventional TMDGFET. On the
other hand, if a diagonally doped drain with a small high
density layer at the source-channel junction is cultivated in a
TMDGFET, then the ambipolar current is suppressed to an
extent greater than the conventional TMDGFET and
TMDGFET with laterally doped gaussian drain.

Furthermore, the SS (subthreshold slope) also meliorates

on utilizing a gaussian doping in the drain region instead of
uniform doping, resulting in SS=26.9mV/dec for lateral
gaussian doping and SS=47.8mV/dec for diagonal gaussian
doping which are far better than the subthreshold slope
(54mV/dec) achieved with uniform doping. Ion also
meliorates on placing a small high density layer at the
Fig.22. Ion/Ioff and subthreshold slope for disparate lateral characteristic
source-channel junction in the channel region.
lengths of diagonal gaussian doped TFET.
ACKNOWLEDGEMENT
We would like to impart our unfeigned gratification to
Spintronix Lab, Jadavpur University for furnishing all the
arrangements and edifices. One of the scriveners, Priyanka
Saha thankfully acknowledges this publication as a corollary
of the R&D work undertaken project under the
Visvesvaraya PhD Scheme of Ministry of Electronics and
Information Technology, Govt. Of India, enforced by
Digital India Corporation.
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