Scribd Logo
Upload

Welcome to Scribd!

  • 35 views

    VHDL Tutorial: Nand Gates

    Uploaded by

    sikopiko
    This document provides an overview of various VHDL concepts including: - Declaring signals and entities with ports - Modeling logic gates like NAND and XOR - Using processes, if/else statements, case statements, for loops, and the numeric standard library for operations - Assigning signals conditionally or in a case statement - Using wait statements to control signal updates The document covers basic syntax and examples for many common VHDL constructs to build up understanding of modeling digital circuits and systems with VHDL.

    Copyright:

    © All Rights Reserved
    Download as DOCX, PDF, TXT or read online from Scribd

    VHDL Tutorial: Nand Gates

    Uploaded by

    sikopiko
    35 views11 pages
    This document provides an overview of various VHDL concepts including: - Declaring signals and entities with ports - Modeling logic gates like NAND and XOR - Using processes, if/else statements, case statements, for loops, and the numeric standard library for operations - Assigning signals conditionally or in a case statement - Using wait statements to control signal updates The document covers basic syntax and examples for many common VHDL constructs to build up understanding of modeling digital circuits and systems with VHDL.

    Original Title

    VHDL easy

    Copyright

    © © All Rights Reserved

    Available Formats

    DOCX, PDF, TXT or read online from Scribd

    Did you find this document useful?

    Is this content inappropriate?

    This document provides an overview of various VHDL concepts including: - Declaring signals and entities with ports - Modeling logic gates like NAND and XOR - Using processes, if/else statements, case statements, for loops, and the numeric standard library for operations - Assigning signals conditionally or in a case statement - Using wait statements to control signal updates The document covers basic syntax and examples for many common VHDL constructs to build up understanding of modeling digital circuits and systems with VHDL.

    Copyright:

    © All Rights Reserved
    Download as DOCX, PDF, TXT or read online from Scribd
    Download as docx, pdf, or txt
    35 views11 pages

    VHDL Tutorial: Nand Gates

    Uploaded by

    sikopiko
    This document provides an overview of various VHDL concepts including: - Declaring signals and entities with ports - Modeling logic gates like NAND and XOR - Using processes, if/else statements, case statements, for loops, and the numeric standard library for operations - Assigning signals conditionally or in a case statement - Using wait statements to control signal updates The document covers basic syntax and examples for many common VHDL constructs to build up understanding of modeling digital circuits and systems with VHDL.

    Copyright:

    © All Rights Reserved
    Download as DOCX, PDF, TXT or read online from Scribd
    Download as docx, pdf, or txt
    of 11

    VHDL TUTORIAL

    NAND GATES:

    library ieee;
    use ieee.std_logic_1164.all;
    use ieee.numeric_std.all; signed and unsigned

    entity xorCircuit is
    port (x1, x2: in std_logic;
    f : out std_logic); To declare the input and output
    end xorCircuit;

    architecture behavioral of xorCircuit is name + entity


    signal S : std_logic := ‘1’; declare a signal S and give it a bit
    signal M : std_logic_vector(7 downto 0) := “10110011”; declare a signal of 8 bits

    begin
    S <= ‘1’; assign 1 to signal S
    M <= "10110011"; assign 10110011 to signal M --- MSB = M(7) = ‘1’; LSB = M(0) = ‘1’
    f <= (x1 nand (x1 nand x2)) nand (x2 nand (x1 nand x2));

    In a proper way:
    g <= x1 nand x2;
    a <= x1 nand g;
    b <= x2 nand g;
    f <= a nand b;

    end behavioral;
    Assume the signals in the XOR circuit VHDL model have the following initial
    values: x1=1, x2=1, g=0, a=1, b=1, and f=0.

    Starting with x1 and x2 the initial value is 1 and


    after a delta delay x1 will go to 0 which will affect
    g and a.
    For g <= x1 nand x2. 1 nand 1 is 0 so g will start
    with 0 and after x1 changes we will have g is
    0 nand 1 = 1 so g will go to 1 after 1 delta delay of
    g delay so after 2 delta delays . This will affect a
    and b
    For a <= x1 and g . x1 and g will never be 1 at the
    same time so a will we always be 1.
    For b <= x2 nand g. x2 is always 1 and g goes from
    0 to 1 after 2 delta so 1 nand 1 is 0 this means
    that b will go to 0 after g so after 3 delta delays.
    And finally, f is affected by b and a is always 1. So,
    f = 1 nand 1 = 0 and when b goes to 0, we will
    have 1 nand 0 so 1 and f will go to 1 after 4 delta.
    SELECTED SIGNAL ASSIGNMENT:

    FORM:

    with <select_expression > select

    <signal_name > <= <value1 > when <choice1 > | <choice3> , 1 OR 3

    <value2> when <choice2 > TO <choice9>, Range from 2 TO 9

    ….
    <valueN> when <choiceN >,

    <valueX> when others;

    2 To 4 Decoder:

    library ieee;
    use ieee.std_logic_1164.all;
    entity dec2to4 is
    port (w : in std_logic_vector(1 downto 0);
    En : in std_logic;
    y : out std_logic_vector(3 downto 0));
    end dec2to4;
    architecture behavioral of dec2to4 is
    signal En_w : std_logic_vector (2 downto 0);

    begin

    En_w <= En & w; En is 1 bit and w is 2 bits so En_w is 3 bits


    with En_w select
    y <= "0001" when "100",
    "0010" when "101",
    "0100" when "110",
    "1000" when "111",
    "0000" when others; because we have 0xx so 0 and 2 don’t cares so we use when others.
    end behavioral;
    CONDITIONAL SIGNAL ASSIGNMENT:

    FORM:

    <signal_name > <= [<value_expr_1 > when <condition_1 > else]

    [<value_expr_2 > when <condition_2 > else]

    …..

    [<value_expr_n > when <condition_n >] ;

    4 To 2 encoder:

    library ieee;
    use ieee.std_logic_1164.all;
    entity priority is
    port (w : in std_logic_vector (3 downto 0);
    y : out std_logic_vector (1 downto 0);
    z : out std_logic);
    end priority;
    architecture behavioral of priority is
    begin
    y <= "11" when w(3) = '1' else
    "10" when w(2) = '1' else
    "01" when w(1) = '1' else
    "00";
    z <= '0' when w = "0000" else '1';
    end behavioral;
    PROCESS:

    Like c++ ; statements will be evaluated sequentially in the order in which they are written, and
    it is concurrent (vhdl statement outside the process run in the same time with the process):

    entity dummy is
    end dummy;
    architecture var of dummy is
    signal trigger, sum : integer := 0; -- @t0
    begin begin arch
    p1: process (trigger) name
    variable var1 : integer := 1; -- @t0 declaring
    variable var2 : integer := 2; -- @t0 variables
    variable var3 : integer := 3; -- @t0 of the process

    begin begin the process

    var1 := var2 + var3; -- =2+3=5 @t0


    var2 := var1; -- =5 @t0 process body
    var3 := var2; -- =5 @t0
    sum <= var1+var2+var3; -- =5+5+5=15 @t0+dt
    end process;
    end var;

    entity dummy is
    end dummy;
    architecture sig of dummy is
    signal trigger, sum : integer := 0; -- @t0
    signal sig1: integer := 1; -- @t0
    signal sig2: integer := 2; -- @t0
    signal sig3: integer := 3; -- @t0
    begin
    p1: process (trigger)
    begin
    sig1 <= sig2 + sig3; -- =2+3=5 @t0+dt
    sig2 <= sig1; -- =1 @t0+dt
    sig3 <= sig2; -- =2 @t0+dt
    sum <= sig1+sig2+sig3; -- =1+2+3=6 @t0+dt
    end process;
    end sig;
    IF STATEMENT:

    if <expression> then

    sequential statements

    elsif <expression> then

    sequential statements

    else
    sequential statements

    end if;

    library ieee;
    use ieee.std_logic_1164.all;

    entity priority is
    port (w : in std_logic_vector (3 downto 0);
    y : out std_logic_vector (1 downto 0);
    z : out std_logic);
    end priority;

    architecture behavioral of priority is

    begin

    p1: process (w)


    begin
    if w(3) = '1' then
    y <= "11";
    elsif w(2) = '1' then
    y <= "10";
    elsif w(1) = '1' then
    y <= "01";
    else
    y <= "00";

    end if;
    end process;

    z <= '0' when w = "0000" else '1';


    end behavioral;
    CASE STATEMENT:

    library ieee;
    use ieee.std_logic_1164.all;

    entity seg7 is
    port (bcd: in std_logic_vector (3 downto 0);

    leds: out std_logic_vector (1 to 7)); end seg7;

    architecture beh of seg7 is begin

    p1: process (bcd) begin

    case bcd is
    when "0000" => leds <= "1111110"; when bcd is 0000 so that led is 1111110 y3ne 0

    when "0001" => leds <= "0110000";

    when "0010" => leds <= "1101101";

    when "0011" => leds <= "1111001";

    when "0100" => leds <= "0110011";

    when "0101" => leds <= "1011011";

    when "0110" => leds <= "1011111";

    when "0111" => leds <= "1110000";

    when "1000" => leds <= "1111111";

    when "1001" => leds <= "1110011";

    when others => leds <= "0000000";

    end case;

    end process;

    end beh;
    FOR LOOP:

    [loop_label:] for index in loop_range loop

    sequential statements;

    end loop [loop_label];

    library ieee;
    use ieee.std_logic_1164.all;
    entity xor8 is
    port (a, b: in std_logic_vector (7 downto 0);
    y: out std_logic_vector (7 downto 0));
    end xor8;

    architecture beh of xor8 is

    begin

    p1: process (a, b)

    begin

    for1: for i in 7 downto 0 loop


    y(i) <= a(i) xor b(i);

    end loop for1;


    end process;

    end beh;
    WHILE LOOP:

    [loop_label:] while condition loop

    sequential statements;

    end loop [loop_label] ;

    process (A)

    variable I : integer range 0 to 3;

    begin

    Z <= "0000";
    I := 0;
    while (I <= 3) loop

    if (A = I) then
    Z(I) <= '1';

    end if;

    I := I + 1;

    end loop;

    end process;
    NUMERIC LIBRARY:

    1. <integer> = to integer(<signed>|<unsigned>); signed/unsigned to integer


    2. <unsigned> = to unsigned(<integer>, size); integer to unsigned
    3. <signed> = to signed(<integer>, size); integer to signed

    1. <std logic vector> = std logicvector(<signed>|<unsigned>); un/signed and to logic vector


    2. <signed> = signed(<unsigned>|<std logic vector>); un or vector to signed
    3. <unsigned> = unsigned(<signed>|<std logic vector>); signed or vector to un

    1. <integer> = to integer(unsigned(<std logic vector>)); vector to integer


    2. <std logic vector> = std logic vector(to signed(<integer>,size)); integer to vector sign
    3. <std logic vector> = std logic vector(to unsigned(<integer>,size)); integer to vector uns
    4.

    WAIT STATMENT:
    process (A, B, C, D)
    wait on sensitivity_list; begin
    wait until boolean_expression; Z <= not ((A and B) or (C and D));
    wait for time_expression; end process;
    wait;

    wait on A,B,C; These 2 processes are the same


    wait until A=B;
    wait for 15 ms; process
    wait; begin
    Z <= not ((A and B) or (C and D));
    wait on A, B, C, D;
    end process;

    process
    begin
    wait on DATA;
    wait until data to take its value
    SIG_A <= DATA;
    wait for 0 ns;
    wait 0 ns so SIG_A will be updated
    SIG_B <= SIG_A;
    SIG_B will be updated after the process is finished
    end process;

    You might also like