DRV 8701

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DRV8701
SLVSCX5B – MARCH 2015 – REVISED JULY 2015
DRV8701 Brushed DC Motor Full-Bridge Gate Driver

1 Features 2 Applications
1• Single H-Bridge Gate Driver • Industrial Brushed-DC Motors
– Drives Four External N-Channel MOSFETs • Robotics
– Supports 100% PWM Duty Cycle • Home Automation
• 5.9-V to 45-V Operating Supply Voltage Range • Industrial Pumps and Valves
• Two Control Interface Options • Power Tools
– PH/EN (DRV8701E) • Handheld Vacuum Cleaners
– PWM (DRV8701P)
• Adjustable Gate Drive (5 Levels)
3 Description
The DRV8701 is a single H-bridge gate driver that
– 6-mA to 150-mA Source Current uses four external N-channel MOSFETs targeted to
– 12.5-mA to 300-mA Sink Current drive a 12-V to 24-V bidirectional brushed DC motor.
• Supports 1.8-V, 3.3-V, and 5-V Logic Inputs A PH/EN (DRV8701E) or PWM (DRV8701P)
• Current Shunt Amplifier (20 V/V) interface allows simple interfacing to controller
• Integrated PWM Current Regulation circuits. An internal sense amplifier allows for
adjustable current control. The gate driver includes
– Limits Motor Inrush Current circuitry to regulate the winding current using fixed
• Low-Power Sleep Mode (9 μA) off-time PWM current chopping.
• Two LDO Voltage Regulators to Power External DRV8701 drives both high- and low-side FETs with
Components 9.5-V VGS gate drive. The gate drive current for all
– AVDD: 4.8 V, up to 30-mA Output Load external FETs is configurable with a single external
– DVDD: 3.3 V, up to 30-mA Output Load resistor on the IDRIVE pin.
• Small Package and Footprint A low-power sleep mode is provided which shuts
– 24-Pin VQFN (PowerPAD™) down internal circuitry to achieve very-low quiescent
current draw. This sleep mode can be set by taking
– 4.0 × 4.0 × 0.9 mm the nSLEEP pin low.
• Protection Features:
Internal protection functions are provided:
– VM Undervoltage Lockout (UVLO) undervoltage lockout, charge pump faults,
– Charge Pump Undervoltage (CPUV) overcurrent shutdown, short-circuit protection,
– Overcurrent Protection (OCP) predriver faults, and overtemperature. Fault
conditions are indicated on the nFAULT pin.
– Pre-Driver Fault (PDF)
– Thermal Shutdown (TSD) Device Information(1)
– Fault Condition Output (nFAULT) PART NUMBER PACKAGE BODY SIZE (NOM)
DRV8701 VQFN (24) 4.00 × 4.00 x 0.90 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
SPACE Gate-Drive Current

tDRIVE
Simplified System Block Diagram
IDRIVE,SNK
High-side IHOLD
ISTRONG
IDRIVE,SRC
5.9V to 45 V
gate drive
current IHOLD IHOLD
DRV8701
PH/EN or PWM High-side
Gate
VGS
nSLEEP H-Bridge Gate drive FETs M
VREF Driver tDRIVE
Controller
IDRIVE,SNK
sense Low-side IHOLD IHOLD

ISTRONG
sense output
IDRIVE,SRC
Shunt Amp gate drive

nFAULT current IHOLD
Protection
3.3 & 4.8 V Low-side
LDO VGS
30 mA
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
DRV8701
SLVSCX5B – MARCH 2015 – REVISED JULY 2015 www.ti.com
Table of Contents
1 Features .................................................................. 1 7.4 Device Functional Modes........................................ 26
2 Applications ........................................................... 1 8 Application and Implementation ........................ 28
3 Description ............................................................. 1 8.1 Application Information............................................ 28
4 Revision History..................................................... 2 8.2 Typical Applications ............................................... 28
5 Pin Configuration and Functions ......................... 3 9 Power Supply Recommendations...................... 32
9.1 Bulk Capacitance Sizing ......................................... 32
6 Specifications......................................................... 5
6.1 Absolute Maximum Ratings ...................................... 5 10 Layout................................................................... 33
6.2 ESD Ratings.............................................................. 5 10.1 Layout Guidelines ................................................. 33
6.3 Recommended Operating Conditions....................... 5 10.2 Layout Example .................................................... 33
6.4 Thermal Information .................................................. 6 11 Device and Documentation Support ................. 34
6.5 Electrical Characteristics........................................... 7 11.1 Documentation Support ........................................ 34
6.6 Typical Characteristics .............................................. 9 11.2 Community Resources.......................................... 34
7 Detailed Description ............................................ 12 11.3 Trademarks ........................................................... 34
7.1 Overview ................................................................. 12 11.4 Electrostatic Discharge Caution ............................ 34
7.2 Functional Block Diagram ....................................... 13 11.5 Glossary ................................................................ 34
7.3 Feature Description................................................. 14 12 Mechanical, Packaging, and Orderable
Information ........................................................... 34
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision A (May 2015) to Revision B Page
• Updated test conditions for IDRIVE,SNK and corrected TYP values ........................................................................................... 8
Changes from Original (March 2015) to Revision A Page
• Updated device status to production data ............................................................................................................................. 1
2 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated
Product Folder Links: DRV8701

DRV8701
www.ti.com SLVSCX5B – MARCH 2015 – REVISED JULY 2015
5 Pin Configuration and Functions
RGE Package RGE Package

24-Pin VQFN 24-Pin VQFN
DRV8701E Top View DRV8701P Top View
GH2
GH2
SH2
SH2
GL2
GL1
GL2
GL1
SN
SN
SP
SP
24
23
22
21
20
19
24
23
22
21
20
19
VM 1 18 SH1 VM 1 18 SH1
VCP 2 17 GH1 VCP 2 17 GH1
CPH 3 GND 16 GND CPH 3 GND 16 GND
CPL 4 (PPAD) 15 PH CPL 4 (PPAD) 15 IN1
GND 5 14 EN GND 5 14 IN2
VREF 6 13 nSLEEP VREF 6 13 nSLEEP
10
11
12
10
11
12
7
9
AVDD
SNSOUT
SO
AVDD
SO
DVDD
nFAULT
IDRIVE
DVDD
nFAULT
SNSOUT
IDRIVE
DRV8701E (PH/EN)
PIN
TYPE DESCRIPTION
NAME NO.
EN 14 Input Bridge enable input Logic low places the bridge in brake mode; see Table 1
PH 15 Input Bridge phase input Controls the direction of the H-bridge; see Table 1
DRV8701P (PWM)
PIN
TYPE DESCRIPTION
NAME NO.
IN1 15 Input
Bridge PWM input Logic controls the state of H-bridge; see Table 2
IN2 14 Input
Common Pins
PIN
TYPE DESCRIPTION
NAME NO.
Connect to motor supply voltage; bypass to GND with a 0.1-µF
VM 1 Power Power supply ceramic plus a 10-µF minimum capacitor rated for VM; additional
capacitance may be required based on drive current
5
GND 16 Power Device ground Must be connected to ground
PPAD
VCP 2 Power Charge pump output Connect a 16-V, 1-µF ceramic capacitor to VM
CPH 3 Connect a 0.1-µF X7R capacitor rated for VM between CPH and
Power Charge pump switching nodes
CPL 4 CPL
3.3-V logic supply regulator; bypass to GND with a 6.3-V, 1-µF
DVDD 8 Power Logic regulator
ceramic capacitor
4.8-V analog supply regulator; bypass to GND with a 6.3-V, 1-µF
AVDD 7 Power Analog regulator
ceramic capacitor
Pull logic low to put device into a low-power sleep mode with FETs
nSLEEP 13 Input Device sleep mode
High-Z; internal pulldown
Resistor value or voltage forced on this pin sets the gate drive
IDRIVE 12 Input Gate drive current setting pin
current; see applications section for more details
Copyright © 2015, Texas Instruments Incorporated Submit Documentation Feedback 3

DRV8701
Common Pins (continued)

PIN
TYPE DESCRIPTION
NAME NO.
Controls the current regulation; apply a voltage between 0.3 V and
VREF 6 Input Analog reference input
AVDD
Open Pulled logic low with fault condition; open-drain output requires an
nFAULT 9 Fault indication pin
Drain external pullup
Open Pulled logic low when the drive current hits the current chopping
SNSOUT 10 Sense comparator output
Drain threshold; open-drain output requires an external pullup
Voltage on this pin is equal to the SP voltage times AV plus an
SO 11 Output Shunt amplifier output
offset; place no more than 1 nF of capacitance on this pin
SN 20 Input Shunt amplifier negative input Connect to SP through current sense resistor and to GND
Connect to low-side FET source and to SN through current sense
SP 21 Input Shunt amplifier positive input
resistor
GH1 17
Output High-side gate Connect to high-side FET gate
GH2 24
GL1 19
Output Low-side gate Connect to low-side FET gate
GL2 22
SH1 18
Input Phase node Connect to high-side FET source and low-side FET drain
SH2 23
External Passive Components

COMPONENT PIN 1 PIN 2 RECOMMENDED
CVM1 VM GND 0.1-µF ceramic capacitor rated for VM
CVM2 VM GND ≥10-µF capacitor rated for VM
CVCP VCP VM 16-V, 1-µF ceramic capacitor
CSW CPH CPL 0.1-µF X7R capacitor rated for VM
CDVDD DVDD GND 6.3-V, 1-µF ceramic capacitor
CAVDD AVDD GND 6.3-V, 1-µF ceramic capacitor
RIDRIVE IDRIVE GND See Typical Applications for resistor sizing
RnFAULT VCC (1) nFAULT ≥10-kΩ pullup
(1)
RSNSOUT VCC SNSOUT ≥10-kΩ pullup
RSENSE SP SN/GND Optional low-side sense resistor
(1) VCC is not a pin on the DRV8701, but a VCC supply voltage pullup is required for open-drain outputs nFAULT and SNSOUT. The
system controller supply can be used for this pullup voltage, or these pins can be pulled up to either AVDD or DVDD.
External FETs
Component Gate Drain Source Recommended
QHS1 GH1 VM SH1
QLS1 GL1 SH1 SP or GND Supports up to 200-nC FETs at 40-kHz PWM; see
QHS2 GH2 VM SH2 Detailed Design Procedure for more details
QLS2 GL2 SH2 SP or GND

DRV8701
6 Specifications
6.1 Absolute Maximum Ratings
(1)
over operating free-air temperature range referenced with respect to GND (unless otherwise noted)
MIN MAX UNIT
Power supply voltage (VM) –0.3 47 V
Power supply voltage ramp rate (VM) 0 2 V/µs
Charge pump voltage (VCP, CPH) –0.3 VM + 12 V
Charge pump negative switching pin (CPL) –0.3 VM V
Internal logic regulator voltage (DVDD) –0.3 3.8 V
Internal analog regulator voltage (AVDD) –0.3 5.75 V
Control pin voltage (PH, EN, IN1, IN2, nSLEEP, nFAULT, VREF, IDRIVE, SNSOUT) –0.3 5.75 V
High-side gate pin voltage (GH1, GH2) –0.3 VM + 12 V
Continuous phase node pin voltage (SH1, SH2) –1.2 VM + 1.2 V
Pulsed 10 µs phase node pin voltage (SH1, SH2) –2.0 VM + 2 V
Low-side gate pin voltage (GL1, GL2) –0.3 12 V
Continuous shunt amplifier input pin voltage (SP, SN) –0.5 1 V
Pulsed 10-µs shunt amplifier input pin voltage (SP, SN) –1 1 V
Shunt amplifier output pin voltage (SO) –0.3 5.75 V
Open-drain output current (nFAULT, SNSOUT) 0 10 mA
Gate pin source current (GH1, GL1, GH2, GL2) 0 250 mA
Gate pin sink current (GH1, GL1, GH2, GL2) 0 500 mA
Shunt amplifier output pin current (SO) 0 5 mA
Operating junction temperature, TJ –40 150 °C
Storage temperature, Tstg –65 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6.2 ESD Ratings

VALUE UNIT
Human body model (HBM) ESD stress voltage (1) ±2000
V(ESD) Electrostatic discharge V
Charged device model (CDM) ESD stress voltage (2) ±500
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN MAX UNIT
VM Power supply voltage range 5.9 45 V
VCC Logic level input voltage 0 5.5 V
VREF Reference RMS voltage range (VREF) 0.3 (1) AVDD V
ƒPWM Applied PWM signal (PH/EN or IN1/IN2) 100 kHz
IAVDD AVDD external load current 30 (2) mA
IDVDD DVDD external load current 30 (2) mA
ISO Shunt amplifier output current loading (SO) 5 mA
TA Operating ambient temperature –40 125 °C
(1) Operational at VREF = 0 to 0.3 V, but accuracy is degraded

(2) Power dissipation and thermal limits must be observed

DRV8701
6.4 Thermal Information

DRV8701
THERMAL METRIC (1) RGE (VQFN) UNIT
24 PINS
RθJA Junction-to-ambient thermal resistance 34.8 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 37.1 °C/W
RθJB Junction-to-board thermal resistance 12.2 °C/W
ψJT Junction-to-top characterization parameter 0.6 °C/W
ψJB Junction-to-board characterization parameter 12.2 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance 3.7 °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.

DRV8701
6.5 Electrical Characteristics

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
POWER SUPPLIES (VM, AVDD, DVDD)
VM VM operating voltage 5.9 45 V
IVM VM operating supply current VM = 24 V; nSLEEP high 6 9.5 mA
nSLEEP = 0 TA = 25°C 9 15
IVMQ VM sleep mode supply current μA
VM = 24 V TA = 125°C (1)
14 25
tSLEEP Sleep time nSLEEP low to sleep mode 100 μs
tWAKE Wake-up time nSLEEP high to output change 1 ms
tON Turn-on time VM > UVLO to output transition 1 ms
DVDD Internal logic regulator voltage External load 0 to 30 mA 3.0 3.3 3.5 V
AVDD Internal logic regulator voltage External load 0 to 30 mA 4.4 4.8 5.2 V
CHARGE PUMP (VCP, CPH, CPL)
VM = 12 V; IVCP = 0 to 12 mA 20.5 21.5 22.5
VCP VCP operating voltage VM = 8 V; IVCP = 0 to 10 mA 13.5 14.4 15 V
VM = 5.9 V; IVCP = 0 to 8 mA 9.4 9.9 10.4
VM > 12 V 12
IVCP Charge pump current capacity 8 V < VM < 12 V 10 mA
5.9 V < VM < 8 V 8
(1)
fVCP Charge pump switching frequency VM > UVLO 200 400 700 kHz
CONTROL INPUTS (PH, EN, IN1, IN2, nSLEEP)
VIL Input logic low voltage 0.8 V
VIH Input logic high voltage 1.5 V
VHYS Input logic hysteresis 100 mV
IIL Input logic low current VIN = 0 V –5 5 μA
IIH Input logic high current VIN = 5 V 78 μA
RPD Pulldown resistance 64 115 173 kΩ
tPD Propagation delay PH/EN, IN1/IN2 to GHx/GLx 500 ns
CONTROL OUTPUTS (nFAULT, SNSOUT)
VOL Output logic low voltage IO = 2 mA 0.1 V
IOZ Output high impedance leakage VIN = 5 V –2 2 μA
FET GATE DRIVERS (GH1, GH2, SH1, SH2, GL1, GL2)
VM > 12 V; VGHS with respect to SHx 8.5 9.5 10.5
High-side VGS gate drive (gate-to-
VGHS VM = 8 V; VGHS with respect to SHx 5.5 6.4 7 V
source)
VM = 5.9 V; VGHS with respect to SHx 3.5 4.0 4.5
Low-side VGS gate drive (gate-to- VM > 12 V 8.5 9.3 10.5
VGLS V
source) VM = 5.9 V 3.9 4.3 4.9
Observed tDEAD depends on IDRIVE
tDEAD Output dead time 380 ns
setting
tDRIVE Gate drive time 2.5 μs
RIDRIVE < 1 kΩ to GND 6
RIDRIVE = 33 kΩ ±5% to GND 12.5
RIDRIVE = 200 kΩ ±5% to GND, or
IDRIVE,SRC Peak source current 25 mA
RIDRIVE < 1 kΩ to AVDD
RIDRIVE > 500 kΩ ±5% to GND 100
RIDRIVE = 68 kΩ ±5% to AVDD 150
(1) Specified by design and characterization data

DRV8701
Electrical Characteristics (continued)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
RIDRIVE < 1 kΩ to GND 12.5
RIDRIVE = 33 kΩ ±5% to GND 25
RIDRIVE = 200 kΩ ±5% to GND, or
IDRIVE,SNK Peak sink current 50 mA
RIDRIVE < 1 kΩ to AVDD
RIDRIVE > 500 ±5% kΩ to GND 200
RIDRIVE = 68 kΩ ±5% to AVDD 300
Source current after tDRIVE 6
IHOLD FET holding current mA
Sink current after tDRIVE 25
GHx 490
ISTRONG FET hold-off strong pulldown mA
GLx 690
Pulldown GHx to SHx 200
ROFF FET gate hold-off resistor kΩ
Pulldown GLx to GND 150
CURRENT SHUNT AMPLIFIER AND PWM CURRENT CONTROL (SP, SN, SO, VREF)
VVREF VREF input voltage For current internal chopping 0.3 (2) AVDD V
50 < VSP < 200 mV; VSN = GND 18 20 22
AV Amplifier gain V/V
10 < VSP < 50 mV; VSN = GND 16 20 24
VOFF SO offset VSP = VSN = GND 50 250 mV
ISP SP input current VSP = 100 mV; VSN = GND -40 μA
(3) VSP = VSN = GND to
tSET Settling time to ±1% 1.5 µs
VSP = 100 mV, VSN = GND
(3)
CSO Allowable SO pin capacitance 1 nF
tOFF PWM current regulation off-time 25 µs
tBLANK PWM blanking time 2 µs
PROTECTION CIRCUITS
VM falling; UVLO report 5.4 5.8
VUVLO VM undervoltage lockout V
VM rising; UVLO recovery 5.6 5.9
VUVLO,HYS VM undervoltage hysteresis Rising to falling threshold 100 mV
tUVLO VM UVLO falling deglitch time VM falling; UVLO report 10 μs
VCPUV Charge pump undervoltage CPUV report VM + 2.8 V
Overcurrent protection trip level, High-side FETs: VM – SHx
VDS OCP 0.8 1 V
VDS of each external FET Low-side FETs: SHx – SP
Overcurrent protection trip level,
VSP OCP VSP voltage with respect to GND 0.8 1 V
measured by sense amplifier
tOCP Overcurrent deglitch time 4.5 µs
tRETRY Overcurrent retry time 3 ms
(3)
TTSD Thermal shutdown temperature Die temperature, TJ 150 °C
(3)
THYS Thermal shutdown hysteresis Die temperature, TJ 20 °C
Positive clamping voltage 10.5 13
VGS CLAMP Gate drive clamping voltage V
Negative clamping voltage –1 –0.7 –0.5
(2) Operational at VREF = 0 to 0.3 V, but accuracy is degraded

(3) Specified by design and characterization data

DRV8701
6.6 Typical Characteristics
6.5 6.15
T A = 125°C
6.1 VM = 24 V
6.4 T A = 85°C VM = 12 V
T A = 25°C 6.05
6.3
T A ±& 6
Supply Current (mA)

S u p p ly C u rre n t (m A )
6.2 5.95
6.1 5.9
5.85
6
5.8
5.9 5.75
5.8 5.7
5.65
5.7
5.6
5.6
5.55
5.5 5.5
5 10 15 20 25 30 35 40 45 -50 -25 0 25 50 75 100 125
Supply Voltage VM (V)
D001
Ambient Temperature (°C) D002
Figure 1. Supply Current over VM Figure 2. Supply Current over Temperature

20 16
T A = 125°C VM = 24 V
18 15
T A = 85°C VM = 12 V
T A = 25°C 14
16 T A ±& 13
S le e p C u rre n t (µ A )
Sleep Current (µA)
14 12
12
11
10
10
9
8 8
6
7
6
4
5
2 4
5 10 15 20 25 30 35 40 45 -50 -25 0 25 50 75 100 125
Supply Voltage VM (V)
D003
Ambient Temperature (°C) D004
Figure 3. Sleep Current over VM Figure 4. Sleep Current over Temperature

12 4.6
VM = 12 V VM = 8 V T A = 125°C
4.5
11 VM = 10 V VM = 5.9 V T A = 85°C
4.4 T A = 25°C
10 T A ±&
4.3
9 4.2
V C P -V M (V )
V C P -V M (V )
4.1
8
4
7
3.9
6 3.8
3.7
5
3.6
4
3.5
3 3.4
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Load Current (mA) Load Current (mA)
D005 D006
Figure 5. VCP over Load (TA = 25°C) Figure 6. VCP over Load (VM = 5.9 V)

DRV8701
Typical Characteristics (continued)

3.295 4.875
3.29
4.85
3.285
3.28 4.825
3.275 4.8
3.27
4.775
AVDD (V)
D V D D (V )
3.265
3.26 4.75
3.255
4.725
3.25
3.245 T A = 125°C T A = 25°C
4.7
3.24 T A = 85°C T A ±& TA = -40°C
4.675 TA = +25°C
3.235
4.65 TA = +85°C
3.23 TA = +125°C
3.225 4.625
0 3 6 9 12 15 18 21 24 27 30 0 3 6 9 12 15 18 21 24 27 30
Load Current (mA) Load Current (mA) D008
D007
Figure 7. DVDD Regulator over Load (VM = 12 V) Figure 8. AVDD Regulator over Load (VM = 12 V)
55 20.1
52.5
50 19.9
47.5
19.7
45
42.5 19.5
S O O ffs e t (m V )
40
A v (V /V )
37.5 19.3
35
32.5 19.1
30
27.5 18.9
25 SP = 225 mV
18.7
22.5 SP = 100 mV
20 VM = 24 V 18.5 SP = 50 mV
17.5 VM = 12 V SP = 10 mV
15 18.3
-50 -25 0 25 50 75 100 125 -50 -25 0 25 50 75 100 125
Ambient Temperature (°C) Ambient Temperature (°C)
D009 D010
Figure 9. SO Offset over Temperature Figure 10. Amplifier Gain over Temperature
20 20
19.96 T A = 125°C T A = 25°C
19.8
19.92 T A = 85°C T A ±&
19.88 19.6
19.84
19.8 19.4
19.76
19.2
A v (V /V )
A v (V /V )
19.72
19.68 19
19.64
18.8
19.6
19.56 18.6
19.52
19.48 18.4
19.44 MAX
18.2
19.4 MIN
19.36 18
5 10 15 20 25 30 35 40 45 10 30 50 70 90 110 130 150 170 190 210 225
Supply Voltage VM (V) SP (mV)
D011 D012
Figure 11. Amplifier Gain over VM (SP = 50 mV) Figure 12. Amplifier Gain over VM and Temperature Range

DRV8701
Typical Characteristics (continued)

180 6.2
160
6
140
H ig h -S id e ID R IV E P (m A )
5.8
120
100 5.6
80 150/300 mA 12.5/25 mA 5.4

100/200 mA 6/12.5 mA
60
25/50 mA
5.2
40
5
20 T A ±& T A = 85°C
T A = 25°C T A = 125°C
0 4.8
-50 -25 0 25 50 75 100 125 5 10 15 20 25 30 35 40 45
Ambient Temperature (°C) Supply Voltage VM (V)
D013 D014
Figure 13. High-Side IDRIVEP over Temperature (VM = 12 V) Figure 14. 6-/12.5-mA High-Side IDRIVEP over VM
16 33
15.5 32
H ig h -S id e ID R IV E P (m A ) 31
15
30
14.5
29
14
28
13.5
27
13
26
12.5 T A ±& T A = 85°C 25 T A ±& T A = 85°C

T A = 25°C T A = 125°C T A = 25°C T A = 125°C
12 24
5 10 15 20 25 30 35 40 45 5 10 15 20 25 30 35 40 45
Supply Voltage VM (V) Supply Voltage VM (V)
D015 D016
Figure 15. 12.5-/25-mA High-Side IDRIVEP over VM Figure 16. 25-/50-mA High-Side IDRIVEP over VM
130 185
180
125
175
120
170
115 165
160
110
155
105 150
145
100 T A ±& T A ±&
T A = 25°C 140 T A = 25°C
95 T A = 85°C T A = 85°C
135
T A = 125°C T A = 125°C
90 130
5 10 15 20 25 30 35 40 45 5 10 15 20 25 30 35 40 45
Supply Voltage VM (V) Supply Voltage VM (V)
D017 D018
Figure 17. 100-/200-mA High-Side IDRIVEP over VM Figure 18. 150-/300-mA High-Side IDRIVEP over VM

DRV8701
7 Detailed Description
7.1 Overview
The DRV8701 is an H-bridge gate driver (also called a pre-driver or controller). The device integrates FET gate
drivers in order to control four external NMOS FETs. The device can be powered with a supply voltage between
5.9 and 45 V.
A simple PH/EN (DRV8701E) or PWM (DRV8701P) interface allows interfacing to the controller circuit.
A low-power sleep mode is included, which can be enabled using the nSLEEP pin.
The gate drive strength can be adjusted to optimize a system for a given FET without adding external resistors in
series with the FET gates. The IDRIVE pin allows for selection of the peak current driven into the external FET
gate. Both the high-side and low-side FETs are driven with a VGS of 9.5 V nominally when VM > 12 V. At lower
VM voltages, the VGS is reduced. The high-side gate drive voltage is generated using a doubler-architecture
charge pump that regulates to VM + 9.5 V.
This device greatly reduces the component count of discrete motor driver systems by integrating the necessary
FET drive circuitry into a single device. In addition, the DRV8701 adds protection features above traditional
discrete implementations: UVLO, OCP, pre-driver faults, and thermal shutdown.
A start-up (inrush) or running current limitation is built in using a fixed time-off current chopping scheme. The
chopping current level is set by choosing the sense resistor value and by setting a voltage on the VREF pin.
A shunt amplifier output is provided for accurate current measurements by the system controller. The SO pin
outputs a voltage that is 20 times the voltage seen across the sense resistor.

DRV8701
7.2 Functional Block Diagram
VM
VM 0.1 µF 10 µF minimum
VM
VM
VCP
Power GH1
1 µF HS
VCP
SH1
Gate Driver
CPH Charge VGLS
GL1
Pump LS
0.1 µF
CPL
Logic VM BDC
30 mA DVDD
3.3-V LDO
1 µF VCP
30 mA AVDD GH2
HS
4.8-V LDO
1 µF
SH2
VGLS LDO
Gate Driver
VGLS
GL2
LS
PH/IN1
EN/IN2
Control
nSLEEP Current Regulation
Inputs SP
IDRIVE
+ AV RSENSE
RIDRIVE SN
-
SNSOUT Outputs SO
nFAULT VREF
PPAD GND GND

DRV8701
7.3 Feature Description

7.3.1 Bridge Control
The DRV8701E is controlled using a PH/EN interface. The following logic table (Table 1) gives the full H-bridge
state when driving a single brushed DC motor. Note that Table 1 does not take into account the current control
built into the DRV8701E. Positive current is defined in the direction of xOUT1 → xOUT2.
Table 1. DRV8701E (PH/EN) Control Interface

nSLEEP EN PH SH1 SH2 AVDD/DVDD Description
0 X X High-Z High-Z Disabled Sleep mode; H-bridge disabled High-Z
1 0 X L L Enabled Brake, low-side slow decay
1 1 0 L H Enabled Reverse drive (current SH2 → SH1)
1 1 1 H L Enabled Forward drive (current SH1 → SH2)
The DRV8701P is controlled using a PWM interface (IN1/IN2). The following logic table (Table 2) gives the full H-
bridge state when driving a single brushed DC motor. Note that Table 2 does not take into account the current
control built into the DRV8701P. Positive current is defined in the direction of xOUT1 → xOUT2.
Table 2. DRV8701P (PWM) Control Interface

nSLEEP IN1 IN2 SH1 SH2 AVDD/DVDD Description
0 X X High-Z High-Z Disabled Sleep mode; H-bridge disabled High-Z
1 0 0 High-Z High-Z Enabled Coast; H-bridge disabled High-Z
1 0 1 L H Enabled Reverse (current SH2 → SH1)
1 1 0 H L Enabled Forward (current SH1 → SH2)
1 1 1 L L Enabled Brake; low-side slow decay
VM VM
1 1 Forward drive 1 1 Reverse drive
2 Slow decay (brake) 2 Slow decay (brake)

SH1 SH2 SH1 SH2
2 3 High-Z (coast) 2 3 High-Z (coast)
3 3
Figure 19. H-Bridge Operational States

DRV8701
7.3.2 Half-Bridge Operation

The DRV8701 can be used to drive only a single half-bridge instead of a full H-bridge. To operate in this mode,
leave GH1 and GL1 disconnected. Also, connect a 1/10 W, 330-Ω 5% resistor from SH1 to GND.
GH1
PH/IN1
Gate SH1
EN/IN2 Drive
Control
Inputs GL1 330
nSLEEP
VM
GH2
Gate SH2
Logic Drive
GL2
BDC
nFAULT SP
+ AV RSENSE
SNSOUT Outputs SN
-
SO
VREF
Figure 20. Half-H Bridge Operation Mode
For the DRV8701E, this mode is controlled by tying the PH pin low. Table 3 gives the control scheme. EN = 1
enables the high-side FET, and EN = 0 enables the low-side FET. EN = 1 and PH = 1 is an invalid state.
Table 3. DRV8701E (PH/EN) Control Interface for Half-H Bridge Mode

nSLEEP EN PH SH2 AVDD/DVDD Description
0 X X High-Z Disabled Sleep mode; disabled High-Z
1 0 X L Enabled Brake, low-side slow decay
1 1 0 H Enabled Drive (Current SH2 → GND)
1 1 1 Invalid state
For the DRV8701P, Table 4 gives the control scheme. IN1 = 1 and IN2 = 0 is an invalid state.
Table 4. DRV8701P (PWM) Control Interface for Half-H Bridge Mode

nSLEEP IN1 IN2 SH2 AVDD/DVDD Description
0 X X High-Z Disabled Sleep mode; disabled High-Z
1 0 0 High-Z Enabled Coast; disabled High-Z
1 0 1 H Enabled Drive (current SH2 → GND)
1 1 0 Invalid state
1 1 1 L Enabled Brake; low-side slow decay

DRV8701
7.3.3 Current Regulation

The maximum current through the motor winding is regulated by a fixed off-time PWM current regulation, or
current chopping. When an H-bridge is enabled in forward or reverse drive, current rises through the winding at a
rate dependent on the DC voltage and inductance of the winding. After the current hits the current chopping
threshold, the bridge enters a brake (low-side slow decay) mode until tOFF has expired.
Note that immediately after the current is enabled, the voltage on the SP pin is ignored for a period of time
(tBLANK) before enabling the current sense circuitry.
The PWM chopping current is set by a comparator which compares the voltage across a current sense resistor
connected to the SP pin, multiplied by a factor of AV, with a reference voltage from the VREF pin. The factor AV
is the shunt amplifier gain, which is 20 V/V in the DRV8701.
The chopping current is calculated as follows:
9REF ± 9OFF
ICHOP
A V u RSENSE (1)
Example: If a 50 mΩ sense resistor is used and VREF = 3.3 V, the full-scale chopping current will be 3.25 A. AV
is 20 V/V and VOFF is assumed to be 50 mV in this example.
For DC motors, current regulation is generally used to limit the start-up and stall current of the motor. If the
current regulation feature is not needed, it can be disabled by tying VREF directly to AVDD and tying SP and SN
to GND.
ICHOP
Drive Current (A)
Drive Brake / Slow Decay Drive Brake / Slow Decay

WWBLANK tOFF WWBLANK tOFF
VREF
SO (V)
SNSOUT
Figure 21. Sense Amplifier and Current Chopping Operation
During brake mode (slow decay), current is recirculated through the low-side FETs. Because current is not
flowing through the sense resistor, SO does not represent the motor current.

DRV8701
7.3.4 Amplifier Output SO

The SO pin on the DRV8701 outputs an analog voltage equal to the voltage seen across the SP and SN pins
multiplied by AV. The factor AV is the shunt amplifier gain, which is 20 V/V in the DRV8701. SO is only valid
during forward or reverse drive. The H-bridge current is approximately equal to:
62 ± 9OFF
I
A V u RSENSE (2)
When SP and SN are 0 V, SO outputs the amplifier offset voltage VOFF. No capacitor is required on the SO pin.
I
R SP
Logic +
VCC +
- SN
- RSENSE
AV/(AV-1) x R
SNSOUT
AV x R
SO
VREF
Figure 22. Sense Amplifier Diagram
If the voltage across SP and SN exceeds 1 V, then the DRV8701 flags an overcurrent condition.
The SO pin can source up to 5 mA of current. If the pin is shorted to GND, or if a higher-current load is driven by
this pin, the output acts as a constant-current source. The output voltage is not representative of the H-bridge
current in this state.
This shunt amplifier feature can be disabled by tying the SP and SN pins to GND. When the amplifier is disabled,
current regulation is also disabled.
AVDD
SO (V)
Slope = Av
VOFF
SP - SN (V)
Figure 23. Sense Amplifier Output
7.3.4.1 SNSOUT
The SNSOUT pin of the DRV8701 indicates when the device is in current chopping mode. When the driver is in
a slow decay mode caused by internal PWM current chopping (ICHOP threshold hit), the open-drain SNSOUT
output is pulled low. If the current regulation is disabled, then the SNSOUT pin will be high-Z.
Note that if the H-bridge is put into a slow decay mode using the inputs (PH/EN or IN1/IN2), then SNSOUT is not
pulled low.
During forward or reverse drive mode, SNSOUT is high until the DRV8701 is internally forced into current
chopping. If the drive current rises above ICHOP, the driver enters a brake mode (low-side slow decay). The
SNSOUT pin will be pulled low during this current chopping brake mode. After the driver is re-enabled, the
SNSOUT pin is released high-Z and the drive mode is restarted.
DRV8701
7.3.5 PWM Motor Gate Drivers

The DRV8701 contains gate drivers for a single H-bridge with external NMOS FETs. Figure 24 shows a block
diagram of the gate driver circuitry.
VGHS VM
PH or IN1
GH1
EN or IN2
ROFF
SH1
nSLEEP Pre-Drive
VGLS
GL1
ROFF
Logic
VGHS VM BDC
GH2
ROFF
SH2
Pre-Drive
VGLS
GL2
ROFF
SP
RSENSE
SN
Figure 24. PWM Motor Gate Drivers
Gate drivers inside the DRV8701 directly drive N-channel MOSFETs, which drive the motor current. The high-
side gate drive is supplied by the charge pump, while the low-side gate drive voltage is generated by an internal
regulator.
The peak drive current of the gate drivers is adjustable through the IDRIVE pin. Peak source currents may be set
to 6, 12.5, 25, 100, or 150 mA. The peak sink current is approximately 2× the peak source current. Adjusting the
peak current changes the output slew rate, which also depends on the FET input capacitance and gate charge.
The peak drive current is selected by setting the value of the RIDRIVE resistor on the IDRIVE pin or by forcing a
voltage onto the IDRIVE pin (see Table 6 for details).
Fast switching times can cause extra voltage noise on VM and GND. This can be especially due to a relatively
slow reverse-recovery time of the low-side body diode, where it conducts reverse-bias momentarily, being similar
to shoot-through. Slow switching times can cause excessive power dissipation since the external FETs take a
longer time to turn on and turn off.

DRV8701
When changing the state of the output, the peak current (IDRIVE) is applied for a short drive period (tDRIVE) to
charge the gate capacitance. After this time, a weaker current source (IHOLD) is used to keep the gate at the
desired state. When selecting the gate drive strength for a given external FET, the selected current must be high
enough to fully charge and discharge the gate during tDRIVE, or excessive power will be dissipated in the FET.
During high-side turn-on, the low-side gate is pulled low with a strong pull-down (ISTRONG). This prevents the low-
side FET QGS from charging and keeps the FET off, even when there is fast switching at the outputs.
The pre-driver circuits include enforcement of a dead time in analog circuitry, which prevents the high-side and
low-side FETs from conducting at the same time. When switching FETs on, this handshaking prevents the high-
or low-side FET from turning on until the opposite FET has been turned off.
tDRIVE
IDRIVE,SNK
High-side IHOLD
ISTRONG
IDRIVE,SRC
gate drive
current IHOLD IHOLD
High-side
VGS
tDRIVE
IDRIVE,SNK
Low-side IHOLD IHOLD

ISTRONG
IDRIVE,SRC
gate drive
current IHOLD
Low-side
VGS
Figure 25. Gate Driver Output to Control External FETs
QGD Miller charge

When a FET gate is turned on, three different capacitances must be charged.
• QGS – Gate-to-source charge
• QGD – Gate-to-drain charge (miller charge)
• Remaining QG
The FET output is slewing primarily during the QGD charge.
10 25
VM
D 20
VDS (drain-to-source) (V)

8
VGS (gate-to-source) (V)
VGHS
CGD
GHx G 6 15
Pre-Drive
CGS
SHx 4 10
S 2 5
10 20 30 40 50
QGS QGD Remaining QG
QG gate charge (nC)
Figure 26. Example FET Gate Charging Profile

DRV8701
7.3.6 IDRIVE Pin

The rise and fall times of the H-bridge output (SHx pins) can be adjusted by setting the IDRIVE resistor value or
forcing a voltage onto the IDRIVE pin. The FET gate voltage ramps faster if a higher IDRIVE setting is chosen.
The FET gate ramp directly affects the H-bridge output rise and fall time.
Tying IDRIVE to GND selects the lowest drive setting of 6-mA source and 12.5-mA sink. If this pin is left
unconnected, then the 100-mA source and 200-mA sink setting are selected.
If IDRIVE is shorted to AVDD, then the VDS OCP monitor on the high-side FETs is disabled. In this setting, the
gate driver is configured as 25-mA source and 50-mA sink.
+
4.3V -
AVDD +
3.7V -
190k
IDRIVE
+ Digital
310k
2.5V - Core
+
1.3V -
+
0.1V -
Figure 27. IDRIVE Pin Internal Circuitry
Table 5. IDRIVE Pin Configuration Settings

Source Current
IDRIVE Resistance IDRIVE Voltage Sink Current (IDRIVE,SNK) HS OCP Monitor
(IDRIVE,SRC)
<1 kΩ to GND GND 6 mA 12.5 mA ON
33 kΩ ±5% to GND 0.7 V ±5% 12.5 mA 25 mA ON
200 kΩ ±5% to GND 2 V ±5% 25 mA 50 mA ON
>500 kΩ to GND, High-Z 3 V ±5% 100 mA 200 mA ON
68 kΩ ±5% to AVDD 4 V ±5% 150 mA 300 mA ON
<1 kΩ to AVDD AVDD 25 mA 50 mA OFF
Table 6. IDRIVE Pin Resistor Settings

33 kΩ ±5% to GND
<1 kΩ to GND >500 kΩ to GND, High-Z 68 kΩ ±5% to AVDD <1 kΩ to AVDD
200 kΩ ±5% to GND
AVDD AVDD
RIDRIVE
IDRIVE IDRIVE IDRIVE IDRIVE IDRIVE
««« RIDRIVE ««« «««
IDRIVE IDRIVE IDRIVE IDRIVE IDRIVE

12.5 / 25 mA (33 kΩ) 25 / 50 mA
6 / 12.5 mA 100 / 200 mA 150 / 300 mA
25 / 50 mA (200 kΩ) HS OCP monitor off

DRV8701
7.3.7 Dead Time

Dead time (tDEAD) is measured as the time when SHx is High-Z between turning off one of the H-bridge FETs
and turning on the other. For example, the output is High-Z between turning off the high-side FET and turning on
the low-side FET.
The DRV8701 inserts a digital dead time of approximately 150 ns. The total dead time also includes the FET
gate turn-on time.
The total dead time is dependent on the IDRIVE resistor setting because a portion of the FET gate ramp (GHx
and GLx pins) includes the observable dead time.
7.3.8 Propagation Delay

The propagation delay time (tDELAY) is measured as the time between an input edge to an output change. This
time is composed of two parts: an input deglitch time and output slewing delay. The input deglitcher prevents
noise on the input pins from affecting the output state.
The gate drive slew rate also contributes to the delay time. For the output to change state during normal
operation, first, one FET must be turned off. The FET gate is ramped down according to the IDRIVE setting, and
the observed propagation delay ends when the FET gate has fallen below the threshold voltage.
7.3.9 Overcurrent VDS Monitor

The gate driver circuit monitors the VDS voltage of each external FET when it is driving current. When the voltage
monitored is greater than the OCP threshold voltage (VDS OCP), after the OCP deglitch time (tOCP) has expired, an
OCP condition will be detected.
VM VM
High-side
VDS OCP GH1
Monitor
SH1
-
+ VM GL1
Low-side
VDS OCP
Monitor +
BDC
-
High-side
VDS OCP GH2
Monitor
SH2
-
+ GL2
Low-side
VDS OCP
Monitor
SP
-
RSENSE
SN
Figure 28. Overcurrent VDS Monitors
When IDRIVE is shorted to AVDD, the VDS OCP monitor on the high-side FETs is disabled. In cases where the
VM supplied to the DRV8701 can be different from the external H-bridge supply, this setting must be used in
order to prevent false overcurrent detection. In this mode, the IDRIVE current is set to 25-mA source and 50-mA
sink.

DRV8701
7.3.10 Charge Pump

A charge pump is integrated to supply a high-side NMOS gate drive voltage of VHGS. The charge pump requires
a capacitor between the VM and VCP pins. Additionally a low-ESR ceramic capacitor is required between pins
CPH and CPL. When VM is below 12 V, this charge pump behaves as a doubler and generates VCP = 2 × VM –
1.5 V if unloaded. Above VM = 12 V, the charge pump regulates VCP such that VCP = VM + 9.5 V.
VM
1 µF
VCP
CPH
VM
Charge
0.1 µF Pump
CPL
Figure 29. Charge Pump Diagram
7.3.11 LDO Voltage Regulators

Two LDO regulators are integrated into the DRV8701. They can be used to provide the supply voltage for a low-
power microcontroller or other low-current devices. For proper operation, bypass the AVDD and DVDD pins to
GND using ceramic capacitors.
The AVDD output voltage is nominally 4.8 V, and the DVDD output is nominally 3.3 V. When the AVDD or DVDD
current load exceeds 30 mA, the LDO behaves like a constant current source. The output voltage drops
significantly with currents greater than this limit.
Note that AVDD and DVDD are disabled when the device is in sleep mode (nSLEEP = 0). In addition, when an
overtemperature (TSD) or undervoltage (UVLO) fault is encountered, the AVDD regulator is shut off.
VM
+
4.8 V
- AVDD
30 mA
1 µF max
VM
+
3.3 V
- DVDD
30 mA
1 µF max
Figure 30. AVDD and DVDD LDOs
The power dissipated in the DRV8701 due to these LDOs may be approximated by:
Power = (VM – AVDD) × IAVDD + (VM – DVDD) × IDVDD (3)
For example at VM = 24 V, drawing 10 mA out of both AVDD and DVDD results in a power dissipation of:
Power = (24 V – 4.8 V) × 10 mA + (24 V – 3.3 V) × 10 mA = 192 mW + 207 mW = 399 mW (4)

DRV8701
7.3.12 Gate Drive Clamp

A clamping structure limits the gate drive output voltage to VGS CLAMP to protect the power FETs from damage.
The positive voltage clamp is realized using a series of diodes. The negative voltage clamp uses the body diodes
of the internal gate driver FET.
VGHS
VM
IREVERSE
GHx
VGS > VCLAMP

ICLAMP
SHx
Pre-Drive
VGLS VGS negative
GLx
RSENSE
GND
Figure 31. Gate Drive Clamp Diagram

DRV8701
7.3.13 Protection Circuits

The DRV8701 is fully protected against VM undervoltage, charge pump undervoltage, overcurrent, gate driver
shorts, and overtemperature events.
7.3.13.1 VM Undervoltage Lockout (UVLO)

If at any time the voltage on the VM pin falls below the UVLO threshold voltage, all FETs in the H-bridge are
disabled, the charge pump is disabled, AVDD is disabled, and the nFAULT pin is driven low. Operation resumes
when VM rises above the UVLO threshold. The nFAULT pin is released after operation has resumed.
7.3.13.2 VCP Undervoltage Lockout (CPUV)

If at any time the voltage on the VCP pin falls below the charge pump undervoltage threshold voltage (VCPUV), all
FETs in the H-bridge are disabled and the nFAULT pin is driven low. Operation resumes when VCP rises above
the CPUV threshold. The nFAULT pin is released after operation has resumed.
7.3.13.3 Overcurrent Protection (OCP)

Overcurrent is sensed by monitoring the VDS voltage drop across the external FETs (see Figure 28). If the
voltage across a driven FET exceeds the overcurrent trip threshold (VDS OCP) for longer than the OCP deglitch
time (tOCP), an OCP event is recognized. As a result, all FETs in the H-bridge are disabled and the nFAULT pin is
driven low; the driver is re-enabled after the OCP retry period (tRETRY) has passed. nFAULT releases high-Z
again at after the retry time. If the fault condition is still present, the cycle repeats. If the fault is no longer present,
normal operation resumes and nFAULT remains released high-Z.
This VDS overcurrent monitor on the high-side FETs can be disabled by using a specific IDRIVE setting. This
allows the system to have a higher DRV8701 VM supply than the H-bridge supply.
In addition to this FET VDS monitor, an overcurrent condition is also detected if the voltage at SP exceeds
VSP OCP.
7.3.13.4 Pre-Driver Fault (PDF)

The GHx and GLx pins are monitored such that if the voltage on the external FET gate does not increase above
1 V (when sourcing current) or decrease below 1 V (when sinking current) after tDRIVE, a pre-driver fault is
detected. The device encounters this fault if GHx or GLx are shorted to GND, SHx, or VM. Additionally, the
device encounters the pre-driver fault if the IDRIVE setting selected is not sufficient to turn on the external FET.
As a result, all FETs in the H-bridge are disabled and the nFAULT pin is driven low. The driver is re-enabled after
the retry period (tRETRY) has passed. The nFAULT pin is released after operation has resumed.
7.3.13.5 Thermal Shutdown (TSD)

If the die temperature exceeds TTSD, all FETs in the H-bridge are disabled, the charge pump is shut down, AVDD
is disabled, and the nFAULT pin is driven low. After the die temperature has fallen below TTSD – THYS, operation
automatically resumes. The nFAULT pin is released after operation has resumed.
Table 7. Fault Response

Fault Condition H-Bridge Charge Pump AVDD DVDD Recovery
VM undervoltage
VM ≤ VUVLO Disabled Disabled Disabled Operating VM ≥ VUVLO
(UVLO)
VCP undervoltage
VCP < VCPUV Disabled Operating Operating Operating VCP > VCPUV
(CPUV)
External FET overload VDS ≥ 1.0 V or
Disabled Operating Operating Operating tRETRY
(OCP) VSP – VSN > 1.0 V
Gate voltage
Pre-driver fault (PDF) Disabled Operating Operating Operating tRETRY
unchanged after tDRIVE
Thermal shutdown
TJ ≥ 150°C Disabled Disabled Disabled Operating TJ ≤ 130°C
(TSD)

DRV8701
7.3.14 Reverse Supply Protection

The following circuit may be implemented to protect the system from reverse supply conditions. This circuit
requires the following additional components:
• NMOS FET
• npn BJT
• Diode
• 10-kΩ resistor
• 43-kΩ resistor
VM
43 k
10 k
0.1 µF 1 µF
+
Bulk
0.1 µF
CP1 CP2 VCP VM 10 µF min
GH1
SH1
GL1
BDC
GH2
SH2
GL2
SP
RSENSE
SN
Figure 32. Reverse Supply Protection External Circuitry

DRV8701
7.4 Device Functional Modes

The DRV8701 is active unless the nSLEEP pin is brought low. In sleep mode, the charge pump is disabled, the
H-bridge FETs are High-Z, and the AVDD and DVDD regulators are disabled. Note that tSLEEP must elapse after
a falling edge on the nSLEEP pin before the device is in sleep mode. The DRV8701 is brought out of sleep mode
if nSLEEP is brought high. Note that tWAKE must elapse before the outputs change state after wake-up.
While nSLEEP is brought low, all external H-bridge FETs are disabled. The high-side gate pins GHx are pulled to
the output node SHx by an internal resistor, and the low-side gate pins GLx are pulled to GND.
When VM is not applied, and during the power-on time (tON), the outputs are disabled using weak pulldown
resistors between the GHx and SHx pins and between GLx and GND.
Table 8. Functional Modes

Condition Charge Pump GHx GLx AVDD and DVDD
Unpowered VM < VUVLO Disabled Weak pulldown to SHx Weak pulldown to GND Disabled
VUVLO < VM
Sleep mode Disabled Strong pulldown to GND Strong pulldown to GND Disabled
nSLEEP low
VUVLO < VM
Operating Enabled Depends on inputs Depends on inputs Operating
nSLEEP high

DRV8701
7.4.1 Operating DRV8701 and H-Bridge on Separate Supplies

The DRV8701 can operate with a different supply voltage (VM) than the system H-bridge supply (VBAT). Case 1
describes normal operation when VM and VBAT are roughly the same. Special considerations must be taken into
account for Cases 2, 3, and 4.
• Case 1: VM ≈ VBAT. Recommended operation
• Case 2: VM > VBAT. IDRIVE must be shorted to AVDD to disable the high-side OCP. The IDRIVE current is
fixed at 25-mA source and 50-mA sink. This case can allow the driver to better enhance the external FETs for
VBAT < 11.5 V, or operate down to a lower supply voltage below 5.9 V.
• Case 3: VM > VBAT (higher than Case 2). IDRIVE must be shorted to AVDD to disable the high-side OCP.
This case can also allow the driver to better enhance the external FETs, or operate down to a lower supply
voltage below 5.9 V. The IDRIVE current is fixed at 25-mA source and 50-mA sink. Excess gate drive current
may be driven through the DRV8701 gate clamps causing additional power dissipation in the DRV8701.
• Case 4: VM < VBAT. The high-side FETs may not be in saturation. There may be a significant voltage drop
across the high-side FET when driving current. This causes high power dissipation in the external FET. When
operating in Case 4, the external FET threshold voltage must be greater than 2 V. Otherwise the DRV8701
will report a pre-driver fault whenever the FET is out of saturation.
Table 9. VM Operational Range based on VBAT

VBAT Range Case 3 Case 2 Case 1 Case 4
VM ≥ 5.9 V
1 V ≤ VBAT < 5.9 V N/A N/A
VM < 0.5 × VBAT + 5.75 V
VM ≥ 0.5 × VBAT + 5.75 V
VM ≥ 5.9 V
5.9 V ≤ VBAT < 6.4 V VM ≤ 45 V VM > VBAT VM = VBAT
VM < VBAT
VM < 0.5 × VBAT + 5.75 V
6.4 V ≤ VBAT < 11.5 V VM > 0.6 × VBAT + 2.5 V VM ≥ 5.9 V
11.5 V ≤ VBAT < 14 V VM ≤ VBAT VM ≤ 0.6 × VBAT + 2.5 V
VM > VBAT
N/A VM > VBAT – 4 V VM ≥ 5.9 V
14 V ≤ VBAT ≤ 45 V VM ≤ 45 V
VM ≤ VBAT VM ≤ VBAT – 4 V
Figure 33. VM Operating Range Based on Motor Supply Voltage
When nSLEEP is low, VM may be reduced down to 0 V with up to 45 V present at VBAT. However, nSLEEP
should not be brought high until VM is supplied with a voltage aligning with one of the cases outlined above.

DRV8701
8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information

The DRV8701 is used in brushed-DC, solenoid, or relay control.
8.2 Typical Applications

8.2.1 Brushed-DC Motor Control
The following design procedure can be used to configure the DRV8701.
0.1 µF 1 µF VM
R1 R2
VM
+
0.1 µF Bulk
6
5
4
3
2
1
VREF
GND
CPL
CPH
VCP
VM
7 24
AVDD GH2
8 23
1 µF DVDD SH2
10 k 9 22
1 µF 10 k nFAULT GND GL2
10 21
SNSOUT (PPAD) SP 50 m
11 20 BDC
SO SN
12 19
IDRIVE GL1
nSLEEP
33 k
GND
GH1
SH1
PH
EN
13
14
15
16
17
18
VM
Figure 34. Typical Application Schematic
8.2.1.1 Design Requirements

Table 10 gives design input parameters for system design.
Table 10. Design Parameters

Design Parameter Reference Example Value
Nominal supply voltage VM 18 V
Supply voltage range VMMIN, VMMAX 12 to 24 V
FET total gate charge (1) QG 14 nC (typically)
(1)
FET gate-to-drain charge QGD 2.3 nC (typically)
Target FET gate rise time RT 100 to 300 ns
Motor current chopping level ICHOP 3A
(1) FET part number is CSD88537ND.

DRV8701
8.2.1.2 Detailed Design Procedure
8.2.1.2.1 External FET Selection

The DRV8701 FET support is based on the charge pump capacity and output PWM frequency. For a quick
calculation of FET driving capacity, use the following equations when drive and brake (slow decay) are the
primary modes of operation:
I
QG VCP
¦PWM
where
• fPWM is the maximum desired PWM frequency to be applied to the DRV8701 inputs or the current chopping
frequency, whichever is larger.
• IVCP is the charge pump capacity, which depends on VM. (5)
The internal current chopping frequency is at most:
1
¦PWM | N+]
tOFF tBLANK (6)
Example: If a system at VM = 7 V (IVCP = 8 mA) uses a maximum PWM frequency of 40 kHz, then the DRV8701
will support QG < 200 nC FETs.
If the application will require a forced fast decay (or alternating between drive and reverse drive), the maximum
FET driving capacity is given by:
IVCP
QG
u ¦PWM (7)
8.2.1.2.2 IDRIVE Configuration

Select IDRIVE based on the gate charge of the FETs. Configure this pin so that the FET gates are charged
completely during tDRIVE. If the designer chooses an IDRIVE that is too low for a given FET, then the FET may
not turn on completely. TI suggests to adjust these values in-system with the required external FETs and motor
to determine the best possible setting for any application.
For FETs with a known gate-to-drain charge (QGD) and desired rise time (RT), select IDRIVE based on:
Q
IDRIVE ! GD
RT (8)
Example: If the gate-to-drain charge is 2.3 nC, and the desired rise time is around 100 to 300 ns,
IDRIVE1 = 2.3 nC / 100 ns = 23 mA
IDRIVE2 = 2.3 nC / 300 ns = 7.7 mA
Select IDRIVE between 7.7 and 23 mA
Select IDRIVE as 12.5-mA source (25-mA sink)
Requires a 33-kΩ resistor from the IDRIVE pin to GND
8.2.1.2.3 Current Chopping Configuration

The chopping current is set based on the sense resistor value and the analog voltage at VREF. Calculate the
current using Equation 9. The amplifier gain AV is 20 V/V and VOFF is typically 50 mV.
Example: If the desired chopping current is 3 A,
Set RSENSE = 50 mΩ
9 5 ( ) ± 9O F F
IC H O P
A V u R SENSE (9)
VREF would have to be 3.05 V.
Create a resistor divider from AVDD (4.8 V) to set VREF ≈ 3 V
Set R2 = 3.3 kΩ; set R1 = 2 kΩ.

DRV8701
8.2.1.3 Application Curves
Figure 35. SH1 Rise Time (12.5-mA Source, 25-mA Sink) Figure 36. SH1 Fall Time (12.5-mA Source, 25-mA Sink)
Figure 37. Current Regulating at 3 A on Motor Startup Figure 38. Current Profile on Motor Startup With
Regulation
Figure 39. Current Profile on Motor Startup Without Regulation

DRV8701
8.2.2 Alternate Application

In this example, the DRV8701 is powered from a supply that is boosted above VBAT. This allows the system to
work at lower VBAT voltages, but requires the user to disable OCP monitoring.
VBAT
Boost
+
10 µF 0.1 µF
0.1 µF 1 µF
R1 R2
0.01 µF
+
6
5
4
3
2
1
C1
VREF
GND
CPL
CPH
VCP
VM
7 24
AVDD GH2
8 23
1 µF DVDD SH2
10 k 9 22
1 µF 10 k nFAULT GND GL2
10 21
SNSOUT (PPAD) SP 50 m
11 20 BDC
AVDD SO SN
12 19
68 k IDRIVE GL1
nSLEEP
GND
GH1
SH1
PH
EN
13
14
15
16
17
18
VBAT
Figure 40. DRV8701 on Boosted Supply
8.2.2.1 Design Requirements

Table 11 gives design input parameters for system design.
Table 11. Design Parameters

Design Parameter Reference Example Value
12 V nominal
Battery voltage VBAT
Minimum operation: 4.0 V
VM = 7 V when VBAT < 7 V
DRV8701 supply voltage VM
VM = VBAT when VBAT ≥ 7 V
FET total gate charge QG 42 nC
FET gate-to-drain charge QGD 11 nC
Motor current chopping level ICHOP 3A
8.2.3 Detailed Design Procedure
8.2.3.1 IDRIVE Configuration

Because the VM supply to the DRV8701 is different from the external H-bridge supply VBAT, the designer must
disable the overcurrent monitor to prevent false overcurrent detection. The designer must place a 68-kΩ resistor
between the IDRIVE pin and AVDD.
IDRIVE is fixed at 25-mA source and 50-mA sink in this mode.
So, the rise time is 11 nC / 25 mA = 440 ns.

DRV8701
8.2.3.2 VM Boost Voltage

To determine an effective voltage to boost VM, first determine the minimum VBAT at which the system must
operate. Select VM such that the gate driver clamps do not turn on during normal operation.
V B A T + 1 1 .5 V
VM <
2 (10)
Example: If VBAT minimum is 4.0 V,
VM < 7.75 V
So VM = 7 V is selected to allow for adequate margin.
9 Power Supply Recommendations

The DRV8701 is designed to operate from an input voltage supply (VM) range between 5.9 and 45 V. A 0.1-µF
ceramic capacitor rated for VM must be placed as close to the DRV8701 as possible. In addition, the designer
must include a bulk capacitor with a valued of at least 10 µF on VM.
Bypassing the external H-bridge FETs requires additional bulk capacitance.
9.1 Bulk Capacitance Sizing

Having appropriate local bulk capacitance is an important factor in motor drive system design. It is generally
beneficial to have more bulk capacitance, while the disadvantages are increased cost and physical size.
The amount of local capacitance needed depends on a variety of factors, including:
• The highest current required by the motor system
• The power supply’s capacitance and ability to source current
• The amount of parasitic inductance between the power supply and motor system
• The acceptable voltage ripple
• The type of motor used (brushed DC, brushless DC, stepper)
• The motor braking method
The inductance between the power supply and motor drive system will limit the rate current can change from the
power supply. If the local bulk capacitance is too small, the system will respond to excessive current demands or
dumps from the motor with a change in voltage. When adequate bulk capacitance is used, the motor voltage
remains stable and high current can be quickly supplied.
The datasheet generally provides a recommended value, but system-level testing is required to determine the
appropriate sized bulk capacitor.
Parasitic Wire
Inductance
Power Supply Motor Drive System
VM
+ + Motor
± Driver
GND
Local IC Bypass
Bulk Capacitor Capacitor
Figure 41. Example Setup of Motor Drive System With External Power Supply
The voltage rating for bulk capacitors should be higher than the operating voltage, to provide margin for cases
when the motor transfers energy to the supply.

DRV8701
10 Layout
10.1 Layout Guidelines

Bypass the VM pin to GND using a low-ESR ceramic bypass capacitor with a recommended value of 0.1 µF
rated for VM. Place this capacitor as close to the VM pin as possible with a thick trace or ground plane
connection to the device GND pin.
Bypass the VM pin to ground using a bulk capacitor rated for VM. This component may be an electrolytic. This
capacitance must be at least 10 µF. The bulk capacitor should be placed to minimize the distance of the high-
current path through the external FETs. The connecting metal trace widths should be as wide as possible, and
numerous vias should be used when connecting PCB layers. These practices minimize inductance and allow the
bulk capacitor to deliver high current.
Place a low-ESR ceramic capacitor in between the CPL and CPH pins. The value for this component is 0.1 µF
rated for VM. Place this component as close to the pins as possible.
Place a low-ESR ceramic capacitor in between the VM and VCP pins. The value for this component is 1 µF rated
for 16 V. Place this component as close to the pins as possible.
Bypass AVDD and DVDD to ground with ceramic capacitors rated at 6.3 V. Place these bypassing capacitors as
close to the pins as possible.
If desired, align the external NMOS FETs as shown in Figure 42 to facilitate layout. Route the SH2 and SH1 nets
to the motor.
Use separate traces to connect the SP and SN pins to the RSENSE terminals.
10.2 Layout Example
+
10 µF GND
minimum
GND
D G
0.1 µF 1 µF D S
VM
0.1 µF
D S
GND
D S
VREF
CPH
CPL
VM
VCP
1 µF
SH2
1 µF
6
S D
AVDD 7 24 GH2
S D
DVDD 8 23 SH2
S D
nFAULT 9 GND 22 GL2
(PPAD) G D
GND
SNSOUT 10 21 SP
SO 11 20 SN
RSENSE
IDRIVE 12 19 GL1 S D
RIDRIVE
13
14
15
16
17
18
S D
nSLEEP
EN
PH
GND
GH1
SH1
S D
G D
SH1
D G
D S
VM
GND
D S
D S
Figure 42. Layout Recommendation

DRV8701
11 Device and Documentation Support
11.1 Documentation Support

11.1.1 Related Documentation
• PowerPAD™ Thermally Enhanced Package, SLMA002
• PowerPAD™ Made Easy, SLMA004
• Current Recirculation and Decay Modes, SLVA321
11.2 Community Resources

The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.3 Trademarks
PowerPAD, E2E are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
11.4 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

PACKAGE OPTION ADDENDUM
www.ti.com 6-Feb-2020
PACKAGING INFORMATION
Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) (6) (3) (4/5)
DRV8701ERGER ACTIVE VQFN RGE 24 3000 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 125 8701E
& no Sb/Br)
DRV8701ERGET ACTIVE VQFN RGE 24 250 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 125 8701E
& no Sb/Br)
DRV8701PRGER ACTIVE VQFN RGE 24 3000 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 125 8701P
& no Sb/Br)
DRV8701PRGET ACTIVE VQFN RGE 24 250 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 125 8701P
& no Sb/Br)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com 6-Feb-2020
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com 30-Jun-2015
TAPE AND REEL INFORMATION
*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
DRV8701ERGER VQFN RGE 24 3000 330.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2
DRV8701ERGET VQFN RGE 24 250 180.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2
DRV8701PRGER VQFN RGE 24 3000 330.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2
DRV8701PRGET VQFN RGE 24 250 180.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com 30-Jun-2015
*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
DRV8701ERGER VQFN RGE 24 3000 367.0 367.0 35.0
DRV8701ERGET VQFN RGE 24 250 210.0 185.0 35.0
DRV8701PRGER VQFN RGE 24 3000 367.0 367.0 35.0
DRV8701PRGET VQFN RGE 24 250 210.0 185.0 35.0
Pack Materials-Page 2
GENERIC PACKAGE VIEW
RGE 24 VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
Images above are just a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4204104/H
PACKAGE OUTLINE
RGE0024F SCALE 3.300
VQFN - 1 mm max height
4.1 B
A
3.9
PIN 1 INDEX AREA

0.5
4.1 0.3
3.9
0.30
0.18
DETAIL
OPTIONAL TERMINAL
TYPICAL
C
1 MAX
SEATING PLANE
0.05
0.00 0.08
2.8 0.1
2X 2.5
(0.2) TYP
7 12 EXPOSED
THERMAL PAD
20X 0.5
6
13
2X
25
2.5
1
SEE TERMINAL 18
DETAIL 0.30
24X
0.18
PIN 1 ID 24 19 0.1 C A B
(OPTIONAL)
0.5 0.05
24X
0.3
4222437/A 12/2015
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
4. Reference JEDEC registration MO-220.
www.ti.com
EXAMPLE BOARD LAYOUT
RGE0024F VQFN - 1 mm max height
( 2.8)
SYMM
24 19
24X (0.6)
1
18
24X (0.24)
(1.15)
TYP
25 SYMM
20X (0.5)
(3.8)
6 13
( 0.2) TYP
VIA
7 12
(R0.05)
ALL PAD CORNERS (3.8)
LAND PATTERN EXAMPLE

SCALE:18X
0.05 MAX 0.05 MIN

ALL AROUND ALL AROUND
SOLDER MASK
METAL
OPENING
SOLDER MASK METAL UNDER

OPENING SOLDER MASK
NON SOLDER MASK

SOLDER MASK
DEFINED
DEFINED
(PREFERRED)
SOLDER MASK DETAILS

4222437/A 12/2015
NOTES: (continued)
5. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
6. Vias are optional depending on application, refer to device data sheet. If some or all are implemented, recommended via locations
are shown.
www.ti.com
EXAMPLE STENCIL DESIGN
RGE0024F VQFN - 1 mm max height
4X ( 1.23) (0.715) TYP

(R0.05) TYP
24 19
24X (0.6)
1 25
18
24X (0.24)
(0.715) TYP
SYMM
20X (0.5)
(3.8)
6 13
METAL
TYP
7 12
SYMM
(3.8)
SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD 25:

77% PRINTED SOLDER COVERAGE BY AREA
SCALE:25X
4222437/A 12/2015
NOTES: (continued)
7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
IMPORTANT NOTICE AND DISCLAIMER
TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE
DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants you
permission to use these resources only for development of an application that uses the TI products described in the resource. Other
reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third
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TI’s products are provided subject to TI’s Terms of Sale (www.ti.com/legal/termsofsale.html) or other applicable terms available either on
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warranties or warranty disclaimers for TI products.
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2020, Texas Instruments Incorporated

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DRV8701 Brushed DC Motor Full-Bridge Gate Driver

SPACE Gate-Drive Current

sense Low-side IHOLD IHOLD

Shunt Amp gate drive

Changes from Revision A (May 2015) to Revision B Page

Changes from Original (March 2015) to Revision A Page

• Updated device status to production data ............................................................................................................................. 1

2 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated

Product Folder Links: DRV8701

5 Pin Configuration and Functions

RGE Package RGE Package

Copyright © 2015, Texas Instruments Incorporated Submit Documentation Feedback 3

Common Pins (continued)

External Passive Components

4 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated

Product Folder Links: DRV8701

6.2 ESD Ratings

6.3 Recommended Operating Conditions

(1) Operational at VREF = 0 to 0.3 V, but accuracy is degraded

Copyright © 2015, Texas Instruments Incorporated Submit Documentation Feedback 5

6.4 Thermal Information

6 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated

Product Folder Links: DRV8701

6.5 Electrical Characteristics

(1) Specified by design and characterization data

Copyright © 2015, Texas Instruments Incorporated Submit Documentation Feedback 7

Electrical Characteristics (continued)

(2) Operational at VREF = 0 to 0.3 V, but accuracy is degraded

8 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated

Product Folder Links: DRV8701

6.6 Typical Characteristics

Supply Current (mA)

Figure 1. Supply Current over VM Figure 2. Supply Current over Temperature

Sleep Current (µA)

Figure 3. Sleep Current over VM Figure 4. Sleep Current over Temperature

Copyright © 2015, Texas Instruments Incorporated Submit Documentation Feedback 9

Typical Characteristics (continued)

10 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated

Product Folder Links: DRV8701

Typical Characteristics (continued)

80 150/300 mA 12.5/25 mA 5.4

12.5 T A ±& T A = 85°C 25 T A ±& T A = 85°C

Copyright © 2015, Texas Instruments Incorporated Submit Documentation Feedback 11

12 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated

Product Folder Links: DRV8701

7.2 Functional Block Diagram

PPAD GND GND

Copyright © 2015, Texas Instruments Incorporated Submit Documentation Feedback 13

7.3 Feature Description

Table 1. DRV8701E (PH/EN) Control Interface

Table 2. DRV8701P (PWM) Control Interface

1 1 Forward drive 1 1 Reverse drive

2 Slow decay (brake) 2 Slow decay (brake)

Figure 19. H-Bridge Operational States

14 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated

Product Folder Links: DRV8701

7.3.2 Half-Bridge Operation

12.5 T A ±& T A = 85°C 25 T A ±& T A = 85°C