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Three stage low noise operational amplifier design for a 0.18 um CMOS process

Conference Paper · September 2012

DOI: 10.1109/ICEEE.2012.6421117

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 Three Stage Low Noise Operational Amplifier Design for a 0.18 um
CMOS Process
A. Soltani, M. Yaghmaie, B. Razeghi, R. Pourandoost, S. Izadpanah Tous1, and A. Golmakani
Department of Electrical Engineering, Sadjad Institute of Higher Education, Mashhad, Iran
E-mail: [email protected]

the input stage allowing for designs with low input current
Abstract –– A new three stage low-noise, high-gain noise [2].
operational amplifier (Op-Amp) is proposed in this paper. The first stage of proposed amplifier is shown in Fig. 2.
Design strategies are discussed for minimizing noise and As you know the noise contributions of the Second and third
increasing gain. Multipath nested Miller compensation used for stages of the Op-Amp are negligible, because they are
three stage operational amplifier. The circuit is designed in the
divided by the gain of the previous stages when referred to
0.18µm CMOS technology. The HSPICE software was used for
simulation. The simulation results show that the amplifier has
the main input. Also noise contribution of current source
a 128.5 dB open-loop DC gain and a unity gain-bandwidth of is negligible.
794 MHz. Also input-referred noise of this circuit is 1.233
⁄√ at 1 MHz frequency.

Keywords –– Noise, three stage operational Amplifier,

Thermal noise, Flicker noise, Nested Miller compensation.

I. INTRODUCTION

The low noise operational amplifier is one of the most

important circuits used in analog design. In MOSFET
devices, there are two important noise sources, which are
flicker noise (below 1MHz) and thermal noise. Fig. 1 shows
device noise as a function of frequency. First, the noise
follows a 1⁄ dependence and is referred to as flicker
noise (v 0.8 1.2) or 1⁄ noise. Above the corner Fig. 2. First stage of the operational amplifier
frequency, , the noise normally is frequency independent
With the assumption that ⁄ ⁄ and
(thermal and shot noise). Above the second characteristic
⁄ ⁄ the total input-referred flicker noise
frequency, , the noise increases sharply due to parasitic
Power Spectral Density (PSD) and thermal noise PSD of the
capacitances coupling noise between different regions of the
circuit are described by:
device [1].
2 1 2 1
· · · (1)

and
8 8
· (2)

Where is capacitance per unit area of the gate oxide, W

and L are the channel width and length respectively, is
NMOS flicker noise coefficient, is PMOS flicker noise
coefficient and T is the absolute temperature. The derived
Fig. 1. Power spectral density of flicker noise and thermal noise [1] coefficient is equal 2/3 for long-channel transistors and
may need to be replaced by a larger value for submicron
Operational amplifiers designed using bipolar MOSFETs. It also varies to some extent with the drain-
technology has achieved a wide bandwidth and superior source voltage [3]. The transconductance can be found
voltage noise performance. However, a bipolar Op-Amp
as presented in (3).
needs several milliamps of input current to bias the input
stage. Though CMOS amplifiers tend to be noisier than
2 (3)
bipolar amplifiers, only minimal bias current is needed for
Where is the carrier mobility for NMOS.

II. PARAMETER DETERMINATION TO ACHIEVE LOW NOISE

According to (1), (2) and (3), we find there are three
techniques that can be used to reduce the noise:
1. Determination of the input pair type for ,
2. Optimization of the bias current of the input
pair
3. Optimization of the sizes and aspect ratios of the
MOSFETs
A. Determination of the input pair type for ,
The first approach to minimizing the 1⁄ noise uses
circuit topology and transistor selection. The transistor
selection is easy [4]. In this structure, NMOS should be Fig. 3. Noise Mosel
chosen for the input pair , for the following three reasons:
1. Selecting a NMOS transistor for the input pair III. THREE STAGE OP-AMP
reduces thermal noise according to Equations (2)
and (3), since NMOS transistors have lager carrier Fig. 4(a) shows the schematic of a three stage low noise,
mobility than PMOS transistors. high-gain operational amplifier based on the single stage
2. The NMOS flicker noise coefficient is smaller described above. When three or more voltage-gain stages
than that of PMOS flicker noise coefficient for must be cascaded to achieve the desired gain, the op amp
the process we use (In the 0.18 TSMC CMOS will have three or more poles, and frequency compensation
process flicker noise coefficient for PMOS is becomes complicated. Multipath Nested Miller
2.932E-23 and for NMOS is 3.564E-24), which is compensation can be used with more than two gain stages.
helpful for achieving lower flicker noise according This compensation scheme involves repeated, nested
to (1). application of Miller compensation [5]. Fig. 4(b) shows the
3. NMOS transistors have a higher transition block diagram of nested Miller compensation applied to
frequency than PMOS transistors, which help to three stages operational amplifier.
achieve a higher bandwidth. In this new structure, the parameters determining the DC
B. Bias Current gain and noise floor are independent. Large bias currents are
The bias current of the input pair , must be used for the input pair to reduce thermal noise. The DC gain
maximized to decrease both types of noise. This is achieved of this amplifier is:
by selecting a large size and high aspect ratio for the input
pair. …
1 1 … (4)
C. Size and Aspect Ratio of MOSFET
To decrease the flicker noise, a large size for ⁄ is
chosen and the channel lengths , are designed larger than The gains of individual stages are:
that of the input pair , based on (1). The aspect ratio
| | (5)
⁄ is maximized and made larger than ⁄ to
reduce the thermal noise according to (2) and (3). After | | 1 1 (6)
those choices, the input pair dominates the noise
contribution of both types. From (1), the change of the input | | (7)
pair’s gate length can increase or decrease the flicker noise.
Fig. 3 shows the noise model for the structure in Fig. 2. The The common source configuration is chosen for the output
noise contribution by each gate is referred back to their own stage of the operational amplifier. Such a stage can achieve
gate input, like the noise contribution of , which is about 20-30 dB of gain
represented by connected in series to its gate.
 Vdd

M3 Vb1 M4 M7 M8
C2
M9

M5 Vb2 M6
R1 C1
Iref Vout
Vin+ M1 M2 Vin- M1a M2a

Mb1 Mb2 R3 C3 Mb3 Mb4

(a)

(b)
Fig. 4. (a) New structure for a three stage low noise operational amplifier, (b) Block diagram for a three stage low noise operational amplifier with multipath
nested Miller compensation

IV. SIMULATION RESULTS x 10

-7

The proposed Op-amp is simulated in HSPICE with 3.5

Input-referred noise (V/√ Hz)

BSIM3v3 model based on a standard 0.18 µm CMOS 3

process. The noise performance of the circuit shown in
Fig. 5 and the simulation of the ac performance of this 2.5
circuit is shown in Fig. 6. The simulation results shows a 2
considerable increase in unity-gain bandwidth to the value
1.5
of 794 MHz, the improved DC gain of 128.5 dB, and a
phase margin of 59.5o. The noise level 1.233 ⁄√ 1
is achieved at 1 MHz frequency. 0.5 X: 1e+006
Parasitic Capacitances
Coupling Noise
The simulated performances for the different Y: 1.233e-009
0 0
compensation methods are expressed in Table I. Also, 2 4 6 8 10
10 10 10 10 10 10
detailed data obtained after simulating the proposed Frequency (Hz)
Op-Amp is summarized in Table I. To evaluate this work
Fig. 5. Noise performance
a figure of merit (FOM) can be defined as:

(8)
1000
 150 V. CONCLUSION

X: 1 A three Stage low-noise, high-gain operational

100 Y: 128.5
amplifier in 0.18μm CMOS process is discussed. The
unity-gain bandwidth is maximized to 794MHz, and gain
Gain (dB)

50 is 128.5 dB. The amplifier can achieve low noise

performance and high gain simultaneously, something
UGBW that is often a tradeoff in normal operational amplifier
0
X: 7.943e+008
design.
Y: -0.01178
-50
10
0 2
10 10
4
10
6
10
8
10
10
REFERENCES
Frequency (Hz)
[1] Samuel Martin, Vance D. Archer III, David M. Boulin, Michel R.
Frei, Kwok K. Ng, and Ran-Hong Yan , “Device Noise in Silicon
200 RF Technologies,” Bell Labs Technical Journal, Summer 1997.
[2] Zhineng Zhu, Raghu Tumati, Scott Collins, Rosemary Smith and
David E. Kotecki, “A Low-noise Low-offset Op Amp in 0.35μm
100 CMOS Process,” IEEE 2006.
[3] B. Razavi, Design of Analog CMOS Integrated Circuits. New
Phase (Degree)

York, NY: McGraw-Hill, 2001.

[4] P. E. Allen and D. R. Holberg, CMOS Analog Circuit Design, New
0 York: Oxford University Press, 2002.
[5] P. R. Gray, P. J. Hurst, S. H. Lewis, and R. G. Meyer, Analysis and
Design of Analog Integrated Circuits. Hoboken, NJ: John Wiley
-100 and Sons, 2001.
[6] Jirayuth Mahattanakul and Jamorn Chutichatuporn, “Design
X: 7.943e+008 Procedure for Two-Stage CMOS Op amp With Flexible Noise-
Y: -120.5 Power Balancing Scheme,” IEEE Transactions on Circuits and
-200
0 2 4 6 8 10 Systems, vol. 52, NO. 8, August 2005.
10 10 10 10 10 10
[7] Jui-Lin Lai, Ting-You Lin, Cheng-Fang Tai, Yi-Te Lai, and Rong-
Frequency (Hz) Jian Chen, “Design a Low-Noise Operational Amplifier with
Constant-gm,” SICE Annual Conference 2010, August 2010.
Fig. 6. Simulated open loop gain and phase margin

TABLE I
PERFORMANCE SUMMARY
Performance [2] [6] [7] This work
Supply Voltage (V) 3.3 2.5 3.3 3.3
Technology ( ) 0.35 N.A 0.35 0.18
UGBW (MHz) 380 6.15 60 794
DC gain (dB) 110 85 110 128.5
Phase Margin (deg) 10.6 65 60 59.5
1.297 44 24.92 1.233
Input-referred noise
√ (10MH) (1MHz) (1kH) (1MHz)
CMRR (dB) N.A N.A 137.8 142
Output swing -peak-to-peak (V) N.A N.A N.A 2.77
FOM 12.66 0.425 2 30.917

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