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    OR Explain Inclusion, Coherence and Locality Properties (8 Marks)

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    1HK16CS104 Muntazir Hussain Bhat
    This document outlines topics related to processor architecture and memory hierarchy. It discusses scalar and superscalar processor design, including instruction pipelines, data paths, control units, and instruction set architectures. Specific processors like VAX 8600, MC68040, SPARC, and Intel i860 are examined. Memory hierarchy concepts like cache hit ratio, memory access time, and page replacement algorithms are defined. Virtual memory systems using paging and segmentation are also covered.

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    OR Explain Inclusion, Coherence and Locality Properties (8 Marks)

    Uploaded by

    1HK16CS104 Muntazir Hussain Bhat
    114 views2 pages
    This document outlines topics related to processor architecture and memory hierarchy. It discusses scalar and superscalar processor design, including instruction pipelines, data paths, control units, and instruction set architectures. Specific processors like VAX 8600, MC68040, SPARC, and Intel i860 are examined. Memory hierarchy concepts like cache hit ratio, memory access time, and page replacement algorithms are defined. Virtual memory systems using paging and segmentation are also covered.

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    Original Title

    Module 2 QB (1)

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    This document outlines topics related to processor architecture and memory hierarchy. It discusses scalar and superscalar processor design, including instruction pipelines, data paths, control units, and instruction set architectures. Specific processors like VAX 8600, MC68040, SPARC, and Intel i860 are examined. Memory hierarchy concepts like cache hit ratio, memory access time, and page replacement algorithms are defined. Virtual memory systems using paging and segmentation are also covered.

    Copyright:

    © All Rights Reserved
    Download as DOCX, PDF, TXT or read online from Scribd
    Download as docx, pdf, or txt
    114 views2 pages

    OR Explain Inclusion, Coherence and Locality Properties (8 Marks)

    Uploaded by

    1HK16CS104 Muntazir Hussain Bhat
    This document outlines topics related to processor architecture and memory hierarchy. It discusses scalar and superscalar processor design, including instruction pipelines, data paths, control units, and instruction set architectures. Specific processors like VAX 8600, MC68040, SPARC, and Intel i860 are examined. Memory hierarchy concepts like cache hit ratio, memory access time, and page replacement algorithms are defined. Virtual memory systems using paging and segmentation are also covered.

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    © All Rights Reserved
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    of 2

    Module 2

    Chapter 4

    1. Explain the design space of processors with neat diagram.


    2. Explain instruction pipeline phases in base scalar processor and the concept of
    underpipeline with neat diagrams.
    3. Explain the data path architecture and control unit of a scalar processor with neat
    diagram.
    4. Explain instruction set architectures with neat diagrams. ( RISC and CISC architectures)
    5. Distinguish between typical CISC and RISC architectures. (8 marks)
    6. What are the characteristics of typical CISC and RISC architectures? ((4 marks)
    7. Explain any one CISC scalar processor. (8 marks)
    a. Explain VAX 8600 CPU a typical CISC processor architecture with neat diagram.
    b. Explain architecture of the MC 68040 processor with neat diagram.
    8. Explain any one RISC scalar processor. (8 marks)
    a. Explain the concept of overlapping register windows in the SPARC processor
    along with the processor architecture block diagram.
    b. Explain functional units and data paths of the intel i860 RISC microprocessor.
    9. Explain pipelining concept in superscalar processors.
    10. With a diagram, explain typical superscalar RISC processor architecture consisting of an
    integer unit and floating point unit. (10 marks)
    11. Explain the POWER architecture of IBM RICS system.
    12. Explain architecture of a VLIW processor and its pipeline operation with neat diagram.
    13. Write the format of register based and memory based vector instructions and explain the
    concept of vector processor.
    14. Explain architecture of Symbolics 3600 Lisp processor.
    15. Discuss the characteristics of symbolic processor.
    16. With a diagram, explain the hierarchical memory technology. ( 6 marks)
    17. Explain three properties of information stored in memory hierarchy with neat diagram.
    OR Explain inclusion, coherence and locality properties ( 8 marks)
    18. a. Give the expressions for effective access time and hierarchy optimization.
    b. Consider the design of a three-level memory hierarchy with the following
    specifications for memory characteristics:

    The design goal is to achieve an effective memory-access time t = 850 ns with a cache hit
    ratio h1 = 0.93 and a hit ratio h2 = 0.99 in main memory. Also, the total cost of the
    memory hierarchy is upper-bounded by $1,500. Calculate capacity of disk storage and
    access time of main memory.
    19. Consider a paged virtual memory system with a two-level hierarchy: main memory M1
    and disk memory M2. The number of page frames in M1 is 3, labeled a, b and c; and the
    number of pages in M2 is 10, identified by 0, 1, 2, . ,., 9. The sequence of‘ page numbers
    so formed is the page trace:

    Compute the hit ratio in the main memory using LRU, OPT, FIFO replacement
    algorithms. Assume the PFs are initially empty.
    20. What are the virtual memory models for multiprocessor systems? (private virtual and
    shared virtual memory) (4 marks)
    21. Explain address translation mechanism using TLB and PT for address translation with
    neat diagram. (8 marks)
    22. Explain paged memory, segmented memory, paged segments and inverted paging.
    23. Explain page replacement policies.
    24. Problems related to page replacement policies solved in class.

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