LGLite ATE Protocol

LGLite + 9346(SPI)

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 LGLiteAte with SPI Protocol

LGLite is a new generation three-in-one computer controlled test instrument, an

Interactive Pattern Generator, Logic Analyzer and a Frequency Counter. The
combination of 32 channels of Pattern Generator and Logic Analyzer is a
powerful tool for designing; debugging and automated testing of C/CPLD/FPGA
based designs. LGLite, which is designed, as a PC hosted instrument is an ideal
tool for learning fundamentals of Digital ATE and test program
development.

It’s common when designing a new device for a manufacturer to design multiple
versions of the device, each with a common set of core capabilities, but each
also with a unique serial communication variation (SPI, I2C, JTAG) intended to
broaden the market potential of the product. Subsequently, to perform tests on
the new design, a test system needs to be capable of interfacing with, and
controlling each of the similar, yet separate communication interfaces.

To get started learning and testing communication protocol we need to

understand the simplest SPI interface:
1. How the SPI components – (DUT – Device under Test) on the board work
before you can figure out how to test them.
2. How the LGLite tester’s Drive logic (Pattern Generator) and the
Response Sensor (Logic Analyzer) will be used for the test.

The AT93C46 provides 1024 bits of serial electrically erasable programmable

read only memory (EEPROM). When the ORG pin of 93C46 is connected to
VCC, the “X16” organization is selected. When ORG pin is connected to ground,
the “X8” organization is selected.

The AT93C46 is enabled through the Chip Select pin (CS) and accessed via a
three-wire serial interface consisting of Data Input (DI), Data Output (DO), and
Shift Clock (SK).
Upon receiving a Read instruction at DI, the address is decoded and the data is
clocked out serially on the DO pin. The Write cycle is completely self-timed, and
no separate Erase cycle is required before Write. The Write cycle is only enabled
when the part is in the Erase/Write Enable state. When CS is brought high
following the initiation of a Write cycle, the DO pin outputs the Ready/Busy status
of the part.

The 93C46 is accessed via a simple and versatile three-wire serial

communication interface. Device operation is controlled by seven instructions. A
valid instruction starts with a rising edge of CS and consists of a start bit (logic
“1”) followed by the appropriate op code and the desired memory address
location.

ERASE/WRITE ENABLE (EWEN):

To assure data integrity, 93C46 automatically goes into the Erase/Write Disable
(EWDS) state when power is first applied. An Erase/Write Enable (EWEN)
instruction must be executed first before any programming instructions can be
carried out. Please note that once in the EWEN state, programming remains
enabled until an EWDS instruction is executed or VCC power is removed.

READ (READ):
The Read (READ) instruction contains the address code for the memory location
to be read. After the instruction and address are decoded, data from the selected
memory location is available at the serial output pin DO. Output data changes
are synchronized with the rising edges of serial clock SK. It should be noted that
a dummy bit (logic “0”) precedes the 8- or 16-bit data output string.

WRITE (WRITE):
The Write (WRITE) instruction contains the 8 or 16 bits of data to be written into
the specified memory location. The self-timed programming cycle starts after the
last bit of data is received at serial data input pin DI. The DO pin outputs the
Read/Busy status of the part if CS is brought high after being kept low for a
minimum of 250 ns. Logic “0” at DO indicates that programming is still in
progress.
LGLite Setup:

Power the LGLite and place 93C46 on the load board as shown below. Ensure to
ground the ORG pin. The device ground is not pin #4 but pin #5. Load LGLite
software with 93C46_Write.VCT and we can then use the LGLite to trigger and
check the ATE protocol working.

The 93C46 communication is enabled via the Chip Select pin (CS) and accessed
via a three-wire serial interface consisting of Data Input (DI), Data Output (DO),
and Shift Clock (SK). The 93C46 Read/Write protocol is shown below:

We use LGLite Channel Name Dialog box to name Drive and Response
Signal. Grouping of Drive channels and Response channel is done using the
LGLite Grouping Dialog box. We format the display radix to be used in the
LGLite trigger word dialog box. The last process would be load the 93C46
protocol test program. The program also contains pin mapping. It’s defined with
the first parameter defining LGLite channel number and next DUT pin info.
Note: LGLite has 32 channels and we are using only 3 Pattern (Drive)
channels and 1 Logic Analyser (Response) channel to test 93C46. Hence we
need to configure LGLite to use only 4 channels for ATE operations. Hence
we first select 2 groups as shown below in the LGLite Group Menu. Pattern
Driver Group with 3 channels and LA Response Group with only 1 channel.

LGLite Drive and Response Configuration

We need to configure the LGLite first 8 channels as Drive channels while the
next 8 channels are configured to capture the DUT Response. Open the
Configuration menu and configure LGLite as shown below.

The config->Clear memory operation clears LGLite Drive Signal RAM. Now
we are ready to load the 93C46 Read/Write Protocol test program.
LgLite Test Plan:

To generate a test plan, details of the 93C46 specification be reviewed

1. Test specifications and tests to be executed need to be prepared.

2. Test hardware (Load board and probe card) need to be designed.
3. Test program need to be generated based on the test plan

Test Specification is a document, which contains the detailed step-by-step

procedure to test the circuit fully. Test specification will be created by combined
effort of design, test and product engineering departments. It defines the exact
conditions to be used for Test Program development. Test Specification should
be reviewed and timing diagram should be developed to confirm the tester
capability respective to test requirements.

A test program manipulates LGLite to

1. Simulate the operating environment of a DUT
2. Control the DUT to execute its operational functions
3. Measures its response and Interprets the results to determine if DUT is
good or bad

To verify that the DUT will correctly perform its intended logical functions, test
vectors or truth tables must be created which can detect faults within the DUT.
The ability of truth table to detect faults can be measured and is referred to as
fault coverage.

Test Vectors:
Test vectors represents the input and output states which represents the logical
functions that the DUT has to perform.
1. Input Drive data are represented by character 0 / 1.
2. Test vectors are called as test patterns or truth tables.
3. Output Response data are represented by L / H / Z and X.
4. Test vectors are stored in LGLite Pattern Generator memory

Using LGLite test vector dialog box, engineer should try to automate the test
vector generation rather than manual.
Loading Test Program

Let us now load a 93C46_Write.VCT test program. These sequences of Drive

signal vectors are used to initiate a 93C46 write cycle.

Program explanation (93C46 Write & Read Cycle)

Let us now try to understand the above test waveform. The 93C46 Write
start cycle is expanded in the waveform window and only when CS is driven
high and DI = 1 when SK clocks high defines the start state for the DUT.

93C46 Read or Write operation is controlled by seven instructions issued by

LGLite. A valid instruction starts with a rising edge of CS and consists of a
start bit (logic “1”) followed by the appropriate op code and the desired
memory address location with its associated data.
Text based Waveform Generation Program

We now go ahead to understand the Waveform Generation Program created

using notepad in reference to the above waveform. We need to clock SK and
the DI state has to be embedded into the Drive vector.

The Waveform Generation Language has simple commands, the first being
#VEC which defines a group of waveform bit patterns and each bit pattern is
recorded in the memory using the #REC command. Hence #VEC is group of
bit patterns in a RAM. This named #VEC <name> with multiple #REC can be
placed anywhere in the RAM.

The first #VEC has a name 9346_START. This is group of three signals and
consumes 5 locations in the Waveform RAM. The first recorded location
#REC defines the 32 bit pattern at State 0x0000. The LSB on the 32-bit
pattern is the Chip Select CS while the next bits are SK, DI and DO bits.

Note when we have #REC = xx000 and #REC = xx001 indicating LSB bit CS
going high (generation of Start ) then the next record we bring the DI = 1 by
xx101 keeping CS high. We then go ahead to program the clock SK to be
strobbed high and then low xx111 and xxx101.

We are now in a position to generate a simple waveform for 93C46 protocol

for start bit (1), command bits (2), address (7) and the Data (8). The
waveform window is the easy way to read the text protocol as shown below

The notepad based Waveform Generation Language (WGL) makes

protocol description and testing very easy.
The complete 93C46_Write test program for a write cycle is now ready and
we need to drive this test sequence to DUT chip (93C46) and capture the
response.

The next step is to ensure that this test waveform have a speed with which
we can output. The specification sheet indicates the speed of SPI protocol
and we run it at speed of 1Mhz. The data sheet allows a maximum speed of
2Mhz. This would mean that if we cycle the test program at 10Mhz, the DUT
would not give any response on the DO pin. We now set the test cycle speed
at 200Khz and study the operation of 93C46

The format in the trigger word is dependent on the way we group channels in
the Group dialog box. The grouping can be in Binary, Hex or any other
format. As of now we use XX as don’t care and allow LGLite ATE to collect
when the collection RAM is full. We just drive one set of pattern pulses
and capture the response of 93C46 device.

The Go button starts the LGLite DUT Drive and Response collection. The
collected waveform is shown below for a XX condition on the Trigger word.
We now go ahead to load a complete 93C46_Write.vct program and drive
the DUT using this vector. Before we start we need to understand the 93C46
protocol for the write cycle. Note the protocol expects the drive signals to
output the start bit followed by write enable command and then repeat the
new cycle with erase command followed by the write command, device
address followed by 8 bits of data.

The loaded 93C46 vector is shown above. Do not forget to change clock
speed to 200Khz. Run the LGLite vector once more and capture the
response. The captured 93C46 read protocol response (DO = 0x55) and
expanded view at 200khz is shown below.

Compute the Erase cycle time for 93C46. The shaded block is the time when
DO stays low and goes high when the erase cycle is over.

A real time complex protocol like 93C46 was successfully tested for both
Read and Write cycle using LGLite Waveform Generation Language and
LGLite at different vector speeds.