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Design and Analysis of Hybrid 1-Bit Full Adder Circuit and Its Impact on 2-Bit
Comparator

Article · May 2016

DOI: 10.17148/IJIREEICE.2016.4551

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 ISSN (Online) 2321 – 2004
IJIREEICE ISSN (Print) 2321 – 5526

INTERNATIONAL JOURNAL OF INNOVATIVE RESEARCH IN ELECTRICAL, ELECTRONICS, INSTRUMENTATION AND CONTROL ENGINEERING
Vol. 4, Issue 5, May 2016

Design and Analysis of Hybrid 1-Bit Full Adder

Circuit and Its Impact on 2-Bit Comparator
Rachana S1, Roshan Shetty2, Praveen J3, Raghavendra Rao A4
M.Tech Student, Dept. of ECE, Alva’s Institute of Engg & Technology, Mijar, Moodbidri, Karnataka, India1
Assistant Professor, Dept. of ECE, Alva’s Institute of Engg & Technology, Mijar, Moodbidri, Karnataka, India 2, 3,4

Abstract: Full adder structures are used as a basic and essential blocks to build any VLSI and embedded applications.
So it demands the researchers to design low power and low speed full adder circuits to improve efficiency of the
design. This project deals with a design of 1-bit hybrid adder circuit by incorporating CMOS and transmission gate
logic. Simulations are done using Tanner EDA Tools v.13.0. Parameters of designs like delay and power are measured
and power delay product are tabulated and are compared with the prior literatures that includes CMOS logic, CPL,
TGA and TFA. Power consumption is found to be decreased and delay also reduced greatly. Also all the adders which
are designed from previous literatures and proposed full adder circuits are placed in a 2-bit comparator individually and
performance of 2-bit comparator will be analyzed. The comparator designed with proposed full adder circuit shows less
power and reduced delay, hence better power delay product compared to others.

Keywords: Comparator, hybrid design, low power, CMOS (Complementary Metal Oxide Semiconductor), high speed,
power delay product, Tanner tool.

I. INTRODUCTION

Portable devices such as mobile phones, notebooks, PDP = power * delay

laptops etc. use batteries for their operations. Usages of
these devices are increasing these days. This demands for A. BASICS OF FULL ADDER
less power and reduced delay VLSI designs. All the above Fig.1 gives the basic block level representation of full
mentioned applications require full adder circuits for their adder. This circuit will have three inputs taken as A, B,
implementations. Full adder circuits are the key domain and Cin. Outputs of the circuit will be taken as SUM and
for the researchers to focus on, over the years. Also basic Cout.
operation in arithmetic is addition and it acts as a core for
other operations like subtraction, multiplication, division
etc. Many VLSI systems requires adders for their
implementation. So in a modern electronics, designing of
accurate and fast full adder circuits that leads to long
lasting battery operated designs is the major element. Thus
the full adder design concentrates on two main factors, i.e.,
speed escalation and power consumption devaluation [5].
In very large integrated circuits (VLSI), challenge is to
design a circuit that can operate with lesser supply
voltages. By reducing the supply voltage, circuit may not
work according to the desire and it may affect the overall Fig.1 Basic block diagram of full adder circuit
design implementation. Here the adders are designed with
less supply voltages. Performance analysis is measured by The Sum and Cout are taken as
taking various considerations like power dissipation, total Sum = A exor B exor Cin
propagation delay and transistor count. Hence the power Cout = AB + BCin + ACin
delay product (PDP) for the circuit [1] also calculated. If, A=B, then Cout=B; else Cout=Cin.
Over the years, adders are designed by using different
logic techniques. Each design is having both advantages II. DESIGN IMPLEMENTATION
and disadvantages. Under different loads, the circuit
design should process good drivability balanced output in In this section, conventional approaches of a full adder
order to avoid glitches. Major factors associated with circuits like CCMOS, CPL, TGA, TFA and proposed
power dissipation are transistors size, number, capacitance architecture of a full adder circuits are discussed.
in a node, complexity of a wire, switching activity. The
average power will be equal to sum short circuit, dynamic A. Classical Complementary Metal-Oxide- Semiconductor
and static powers. During switching activity, each gate (CCMOS) Full Adder
will consume some amount of energy and it is represented Classical designs which are used to design the full adder
as PDP. It’s a measure of efficiency in an adder. circuits make use of single logic technique to implement

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IJIREEICE ISSN (Print) 2321 – 5526

INTERNATIONAL JOURNAL OF INNOVATIVE RESEARCH IN ELECTRICAL, ELECTRONICS, INSTRUMENTATION AND CONTROL ENGINEERING
Vol. 4, Issue 5, May 2016

the entire design. CMOS adder structure is an example for impedance and output voltage will be less. It is capable of
this kind of design. The CMOS adder contains 28T. This swing restoration. Since it has better output driving
structure resembles normal CMOS where, PMOS capability and faster differential stages, it makes very
transistors (14T) are placed in pull-up network and NMOS efficient implementation of complex gates. Most prime
transistors (14T) are placed in pull-down network. The feature of CPL is its small stack height that results in less
schematic diagram for CCMOS adder is available in Fig.2. consumption of power.

Fig.2 CCMOS (28T)

1. Advantages: Fig.3 CPL (32T)

The main advantage of CCMOS full adder is, it has a high
noise margins. Hence it will operate under lower voltages Swing Restored Pas- transistor Logic (SRPL) is designed
reliably. It contains a complementary transistor pairs, so using CPL. In this SRPL style, latch structure is formed by
the layout of this design also simplified (layout regularity).cross coupled output inverters. This results in swing
This adder has robustness against transistor sizing and restoration along with output buffering. In order to reduce
voltage scaling [9]. the power in CPL circuits, SRPL and LCPL circuits are
used. DC power is reduced to attain full swing operation
2. Disadvantages: by using complementary transistors in Double Pass-
In this design, each input is connected to either PMOS or Transistor Logic. Hence the restoration circuitry is
NMOS gates, so it results in large input capacitance and eliminated.
also results in degradation of speed. In the output stage, it
has transistors in series that forms a weak driver. Because 2. Disadvantages:
of this reason, additional buffers are placed at the final Pass transistor logic suffer from voltage drop problem. i.e.,
stage. It provides necessary power to drive the cells that when “1” is given as a input to the NMOS, output will be
are cascaded and hence results in large silicon area. This weaker logic “1” because NMOS is a strong passer of “0”.
full adder structure contains more number of PMOS In a same way, when “0” is given as a input to PMOS,
devices. It is a main disadvantage because in order to get a output will be weaker logic “0” as PMOS is a strong
desired performance, sizing has to be carried out for passer of “1”. There are more number of intermediate
PMOS devices. Also, PMOS devices exhibit lower nodes, more number of transistors and overloading of
mobility than that of NMOS. It makes use of CMOS inputs which results in higher switching activity that in
devices in order to generate sum which results in turn consumes more power. CPL does not suit for
additional unwanted delay. Sub threshold leakage will be applications with lesser power since it has a high degree of
more, since there are many leakage paths. wiring complexity, more delay. It gives complementary
outputs as it takes complementary inputs.
B. Complementary Pass-Transistor Logic (CPL) CPL cell layout is not straightforward compare to CMOS
Adder design using this technique contains 32 transistors because of irregularity in transistor arrangements. CPL
in a dual rail structure. Main difference between CPL and suffers because of static power loss at the output inverter
CCMOS full adders is that, in a pass transistor logic gates due to low swing. In this adder architecture, inputs
circuit, input signals connects to the source side instead and outputs both will be in true and complement form. It
connecting them to power lines. Also, speed of operation results in larger short circuit currents and wiring overhead
is better in CPL than CCMOS. Schematic diagram of CPL is more.
adder is given in Fig.3.
C. TRANSMISSION GATE ADDER (TGA)
1. Advantages: Special case of pass transistor logic is transmission gate
The main advantage here is, single pass transistor is logic. This adder structure contains 20 transistors which
required in order to design any logic. It results in less consist of complementary NMOS (10T) and PMOS (10T)
transistor count and less input loading. It has lower input transistor properties. It is designed by connecting NMOS

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IJIREEICE ISSN (Print) 2321 – 5526

INTERNATIONAL JOURNAL OF INNOVATIVE RESEARCH IN ELECTRICAL, ELECTRONICS, INSTRUMENTATION AND CONTROL ENGINEERING
Vol. 4, Issue 5, May 2016

transistor in parallel with PMOS transistor that is power and less silicon area. In terms of power and
controlled by control signals in a complementary form. leakage, this adder gives better performance.
When NMOS and PMOS transistors turn on
simultaneously, then transmission gate will provides a
path for input logic “1” or “0”. Hence there will be no
voltage drop in the circuit. Schematic diagram of TGA is
provided in Fig.4.

Fig.5 TFA (16T)

2. Disadvantages:
Full swing outputs are not obtained by XOR and XNOR
modules, so the transistors that are connected to this
. module turns on or off slowly. Adder designed with
Fig.4 TGA (20T) transmission function logic suffers from lack of driving
capability. There is a significant degradation of
1. Advantages: performance when it is cascaded.
The circuit is very simple when compared to other
conventional adders, hence results in faster operations. E. PROPOSED HYBRID 1-BIT FULL ADDER
Power consumption will be similar to that of CMOS, but it CIRCUIT
performs faster. Here transistor counts are less resulting inProposed adder architecture uses both transmission gate
lesser delay compared to CPL and CCMOS full adders. logic and CMOS logic for its implementation. Here, full
This logic style is well suited for designing XOR or adder is represented by a 3 blocks or modules. For the
XNOR gates. Performance of the circuit degrades when it generation of output sum signal (SUM), we make use of
is connected in cascade. XNOR modules and they are represented by module 1 and
module 2. Generation of carry signal (Cout) is through
2. Disadvantages: module 3. Block representation of proposed full adder is
Twice the number of transistors is required to design the given in Fig.6.
circuit that can be implemented by pass transistor logic. It
has a low driving capability. Followed by two
transmission gates, circuit contains two inverters, together
they acts as 8-T XOR.
Number of internal nodes will be more in this architecture.
Hence parasitic capacitance will be more. It gives a poor
performance in a arithmetic circuits due to additional
buffers at output stage, increasing the power dissipation.

D. TRANSMISSION FUNCTION ADDER (TFA)

This adder structure is designed using transmission Fig.6 Block diagram of proposed full adder
function theory. This adder uses 16T for its operation
which includes transmission gates, pass transistors and Each module is independently designed so that the entire
low power XNOR and XOR gates. Schematic diagram of circuit will be optimized with respect to delay, power and
TFA is presented in Fig.5. area. The modules are discussed below. The internal
architecture of module 1 and 2 are represented in Fig.7
1. Advantages: which is used for generation of sum. Module 3 is
Full adder designed with this logic consumes less power represented in Fig.8.
and offers higher speed reducing the delay compare to
other conventional adders. This logic proves to be a good 1. MODIFIED XNOR MODULE
choice to design XOR and XNOR gates. It gives same XNOR module consumes more power in the proposed
delay for both sum and Cout. As the transistor count adder design. Power can be minimized to best possible
required to implement full adder is less, it results in less extent by optimizing the XNOR module. It also avoids the

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INTERNATIONAL JOURNAL OF INNOVATIVE RESEARCH IN ELECTRICAL, ELECTRONICS, INSTRUMENTATION AND CONTROL ENGINEERING
Vol. 4, Issue 5, May 2016

possibility of voltage degradation. Fig.7 represents The generation of input signal B is from a inverter with
Modified XNOR circuit. transistors Mp1 and Mn1. This in turn used in the design
of controlled inverter comprising of Mp2 and Mn2. The
controlled inverter output will be XNOR of A and B. this
operation has a problem with degradation of voltage. This
can be eliminated by use of 2 pass transistors namely MP3
and Mn3.

Fig.7 Schematic diagram of XNOR module

Here there is a significant reduction in power as it makes

use of a weak inverter (transistors having small channel
width). In a Fig, Mp1 and Mn1 form a weak inverter. Mp3
and Mn3 are referred as level restoring transistors which
results in fall swing of output signals. The XOR/XNOR
circuits that are designed in prior literatures uses 6
transistors to give better output swing. Here also XNOR
Fig.9 Detail circuit diagram of proposed full adder
module consists of 6 transistors but, the arrangement of
transistors are different. It is arranged in such a manner
In a same way, NMOS transistors Mn4, Mn5, Mn6 and
that, it gives lower power and higher speed compared to
also PMOS transistors Mp4, Mp5, Mp6 are used as a
other literatures.
second module of XNOR gates which results in the output
sum signal. The output carry is obtained through
2. CARRY GENERATION MODULE
transistors Mn7, Mp7, Mn8 and Mp8. For the full adder
The schematic of this module is given in Fig.8. The
circuit, carry out is analyzed as follows. If A is equal to B,
transistors Mp7, Mn7, Mp8 and Mn8 are implemented in
then Cout will be equal to B. otherwise, Cout will be equal
order to achieve the output carry signal. Here input carry
to Cin.
signal (Cin) passes or propagates through only one
transmission gate, i.e., Mn7 and Mp7. Hence it reduces
F. DESIGN OVERVIEW: 2-BIT COMPARATOR
path required for carry propagation. Large channel width
2-bit comparator circuit is taken here as a application
transistors are used for transmission gates. Here Mn7,
circuit. Full adder based comparator circuit is designed
Mp7, Mn8 and Mp8 form the transmission gates. Hence it
which is used in a block of ALU.
results in reducing the delay for some extent.

Fig.8 Schematic diagram of carry generation module

3. OPERATION OF PROPOSED FULL ADDER

Detailed circuit for proposed adder is given in Fig.9.
Implementation of sum output is through XNOR modules. Fig.10 Comparator using full adder

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INTERNATIONAL JOURNAL OF INNOVATIVE RESEARCH IN ELECTRICAL, ELECTRONICS, INSTRUMENTATION AND CONTROL ENGINEERING
Vol. 4, Issue 5, May 2016

In order to compare two numbers in digital systems, 3. Power and delay Analysis
magnitude comparators are used. Main objective here is to
optimize delay, power and silicon area. Comparators are
designed by using conventional full adder circuits and also
by using proposed hybrid full adder circuit. Its
performance is measured based on delay, power and
power delay product. 2-bit comparator circuit that uses full
adders for its operation is as shown in Fig.10.

III. SIMULATION RESULTS

Different types of full adders are designed using Tanner

EDA Tools 13.0 Licensed Version in this project. It
includes schematic designs and analysis of conventional
full adders and proposed full adder. Different analysis on
both conventional and proposed adder designs is carried
out. They include power analysis, delay analysis and
calculating PDP. VLSI design involves low voltage
implementation and low power implementation in its Fig.13 Power and Delay results of Full Adder 1
design in order to get optimized performance. Here the
circuits are designed using 1V supply as VDD that results 4. Comparator design by incorporating CCMOS Full
in minimum propagation delay and lower power Adder (Full Adder 1) – Comparator 1
consumption.

A. The CCMOS Full Adder – Full Adder 1

1. Schematic Diagram

Fig.14 Schematic Representation of Comparator 1

Fig.11 Schematic Representation of Full Adder 1 5. Output Waveforms

2. Output Waveforms

Fig.12 Waveforms of Full Adder 1 Fig.15 Waveforms of Comparator 1

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INTERNATIONAL JOURNAL OF INNOVATIVE RESEARCH IN ELECTRICAL, ELECTRONICS, INSTRUMENTATION AND CONTROL ENGINEERING
Vol. 4, Issue 5, May 2016

6. Power and delay analysis D . Transmission Function Full adder – Full adder 4
1. Schematic Diagram

Fig.19 Schematic Representation of Full Adder 4

Fig.16 Power and Delay results of Comparator1 E. Hybrid 1-bit Full Adder - Full Adder 5
1. Schematic Diagram
B. The Complementary Pass Transistor Logic Full Adder
– Full Adder 2
1. Schematic Diagram

Fig.17 Schematic Representation of Full Adder 2

C. Transmission Gate Adder - Full adder 3 Fig.20 Schematic Representation of Full Adder 5
1. Schematic Diagram
F. COMPARISON RESULTS
A. Comparison between Power, Delay and PDP of all Full
Adders

Table 1: Comparison between Power, Delay, PDP and

Transistor Count of all full adders

Sl. Full Power Delay PDP Transis

No Adders (mW) (mS) (uJ) tor
Count
1. CCMOS 6.79 1.36 9.23 28
2. CPL 7.95 1.38 10.97 32
3. TGA 6.61 1.34 8.85 20
4. TFA 7.055 0.68 4.79 16
5. PROPO 6.34 0.33 2.09 16
Fig.18 Schematic Representation of Full Adder 3 SED

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INTERNATIONAL JOURNAL OF INNOVATIVE RESEARCH IN ELECTRICAL, ELECTRONICS, INSTRUMENTATION AND CONTROL ENGINEERING
Vol. 4, Issue 5, May 2016

B. Comparison between Power, Delay and PDP of all [6] P. Prashanth and P. Swamy, “Architecture of adders based on
speed, area and power dissipation,” in Proc. World Congr. Inf.
Comparators
Commun. Technol. (WICT), Dec. 2011, pp. 240–244.
[7] D. Radhakrishnan, “Low-voltage low-power CMOS full adder,”
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[8] C.-K. Tung, Y.-C. Hung, S.-H. Shieh, and G.-S. Huang, “A low-
power high-speed hybrid CMOS full adder for embedded system,”
Sl. Comparators Power Delay PDP in Proc.IEEE Conf. Design Diagnostics Electron. Circuits Syst.,
No (mW) (mS) (uJ) vol. 13.Apr. 2007, pp. 1–4.
1 CCMOS 16.669 1.353 22.553 [9] S. Goel, A. Kumar, and M. A. Bayoumi, “Design of robust, energy
efficient full adders for deep-submicrometer design using hybrid-
2 CPL 13.571 1.342 18.212 CMOS logic style,” IEEE Trans. Very Large Scale Integr. (VLSI)
3 TGA 10.559 1.343 14.180 Syst., vol. 14, no. 12, pp. 1309–1321, Dec. 2006.
4 TFA 10.698 0.724 7.745 [10] C. H. Chang, J. M. Gu, and M. Zhang, “A review of 0.18-μm full
adder performances for tree structured arithmetic circuits,” IEEE
5 PROPOSED 7.458 1.152 1.336 Trans. Very Large Scale Integr. (VLSI) Syst., vol. 13, no. 6, pp.
686–695, Jun. 2005.
IV. CONCLUSION AND FUTURE WORK [11] M. Zhang, J. Gu, and C.-H. Chang, “A novel hybrid pass logic with
static CMOS output drive full-adder cell,” in Proc. Int. Symp.
Circuits Syst., May 2003, pp. 317–320.
The main intension in this project is to minimize the [12] S. Goel, M. Elgamel, and M. A. Bayoumi, “Novel design
power consumption and to reduce the propagation delay, methodology for high-performance XOR-XNOR circuit design,” in
so that the performance and speed of the circuit will be Proc. 16th Symp. Integr. Circuits Syst. Design (SBCCI), Sep. 2003,
improved. Here both conventional and proposed full pp. 71–76.
[13] Hassoune, D. Flandre, I. O’Connor, and J. Legat, “ULPFA: A new
adders are designed using Tanner EDA licensed version efficient design of a power-aware full adder,” IEEE Trans. Circuits
13.0., in 90nm technology at 1V. The designed schematic Syst. I, Reg. Papers, vol. 57, no. 8, pp. 2066–2074, Aug. 2010.
and the results of simulation shows that the proposed [14] M. Alioto, G. Di Cataldo, and G. Palumbo, “Mixed full adder
adder i.e., Hybrid 1-bit full adder circuit gives very less topologies for high-performance low-power arithmetic circuits,”
Microelectron. J., vol. 38, no. 1, pp. 130–139, Jan. 2007.
power consumption and also greatly reduces the [15] Partha Bhattacharyya, Bijoy Kundu, Sovan Ghosh, Vinay Kumar
propagation delay, hence PDP will be less. This is due to and Anup Dandapat, “Performance Analysis of a Low-Power High-
coupling of weaker CMOS inverters to the strong Speed Hybrid 1-bit Full Adder Circuit,” IEEE Trans. on Very Large
transmission gates. The results are compared with Scale Integration (VLSI) Systems, vol. 23, no. 10, Oct 2015.
conventional full adders like CCMOS, CPL, TGA, and
TFA.

2-bit comparator is designed by incorporating all

conventional full adders and proposed adder. The impact
of proposed hybrid 1-bit full adder on comparator 5 results
in improved PDP, reduced delay and minimum power
consumption. Hence the overall circuit performance is
improved.

The future work of this project includes the following

 Designing area efficient full adder.

 Optimizing the design of comparator.
 Different analysis to be carried out on a full adder and
comparator circuits.

REFERENCES

[1] M. Vesterbacka, “A 14-transistor CMOS full adder with full

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[3] Vandana Choudhary Rajesh Mehra, “ 2- Bit Comparator Using
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