TPS4H160-Q1 40-V, 160-mΩ Quad-Channel Smart High-Side Switch

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TPS4H160-Q1
SLVSCV8D – DECEMBER 2015 – REVISED DECEMBER 2019
TPS4H160-Q1 40-V, 160-mΩ Quad-Channel Smart High-Side Switch

1 Features – Loss-of-GND and Loss-of-Battery Protection
•
1 Qualified for Automotive Applications • Diagnostics
• AEC-Q100 Qualified With the Following Results: – Overcurrent and Short-to-Ground Detection
– Device Temperature Grade 1: –40°C to asd – Open-Load and Short-to-Battery Detection
125°C Ambient Operating Temperature Range – Global Fault Report for Fast Interrupt
– Device HBM ESD Classification Level H3A • 28-Pin Thermally-Enhanced PWP Package
– Device CDM ESD Classification Level C4B
• Functional safety capable 2 Applications
– Documentation available to aid functional • Multichannel LED Drivers, Bulb Drivers
safety system design • Multichannel High-Side Switches for Sub-Modules
• Quad-Channel 160-mΩ Smart High-Side Switch • Multichannel High-Side Relay, Solenoid Drivers
With Full Diagnostics • PLC Digital Output Drivers
– Version A: Open-Drain Digital Output
– Version B: Current-Sense Analog Output 3 Description
• Wide Operating Voltage 3.4 V to 40 V The TPS4H160-Q1 device is fully protected quad-
channel smart high-side switch with four integrated
• Ultralow Standby Current, < 500 nA 160-mΩ NMOS power FETs.
• High-Accuracy Current Sense: ±15% Under >25-
Full diagnostics and high-accuracy current sense
mA Load
enable intelligent control of the load.
• Adjustable Current Limit With External Resistor,
±15% Under >500 mA Load An external adjustable current limit improves the
reliability of whole system by limiting the inrush or
• Protection overload current.
– Short-to-GND Protection by Current Limit
(Internal or External) Device Information(1)
– Thermal Shutdown With Latch Off Option and PART NUMBER PACKAGE CHANNELS
Thermal Swing TPS4H160-Q1 Version A
HTSSOP (28) 4
– Inductive Load Negative Voltage Clamp With TPS4H160-Q1 Version B
Optimized Slew Rate (1) For all available packages, see the orderable addendum at
the end of the data sheet.
Typical Application Schematic
Driving a Capacitive Load With Adjustable
3.4 V to 40 V
SupplyVoltage Current Limit
VS
IN1, 2, 3, 4
LED Strings,
OUT1 Small Power Bulbs
DIAG_EN
Overcurrent Is Clamped
THER at the Set Value of 1 A.
OUT2 Solenoids, Valves, Relays
SEH ST1
ST2 Sub-Module:
SEL OUT3 Cameras, Sensors, Displays
FAULT ST3
General Resistive, Capacitive,
OUT4 Inductive Loads
CS ST4
CL
GND
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPS4H160-Q1
SLVSCV8D – DECEMBER 2015 – REVISED DECEMBER 2019 www.ti.com
Table of Contents
1 Features .................................................................. 1 8.3 Feature Description................................................. 15
2 Applications ........................................................... 1 8.4 Device Functional Modes........................................ 27
3 Description ............................................................. 1 9 Application and Implementation ........................ 28
4 Revision History..................................................... 2 9.1 Application Information............................................ 28
9.2 Typical Application ................................................. 28
5 Device Comparison Table..................................... 3
6 Pin Configuration and Functions ......................... 3 10 Power Supply Recommendations ..................... 30
7 Specifications......................................................... 6 11 Layout................................................................... 31
11.1 Layout Guidelines ................................................. 31
7.1 Absolute Maximum Ratings ...................................... 6
11.2 Layout Examples................................................... 31
7.2 ESD Ratings.............................................................. 6
7.3 Recommended Operating Conditions....................... 7 12 Device and Documentation Support ................. 33
7.4 Thermal Information ................................................. 7 12.1 Receiving Notification of Documentation Updates 33
7.5 Electrical Characteristics........................................... 7 12.2 Community Resources.......................................... 33
7.6 Switching Characteristics .......................................... 9 12.3 Trademarks ........................................................... 33
7.7 Typical Characteristics ............................................ 11 12.4 Electrostatic Discharge Caution ............................ 33
12.5 Glossary ................................................................ 33
8 Detailed Description ............................................ 14
8.1 Overview ................................................................. 14 13 Mechanical, Packaging, and Orderable
8.2 Functional Block Diagram ....................................... 15
Information ........................................................... 33
4 Revision History
Changes from Revision C (March 2018) to Revision D Page
• Added Functional safety capable link to the Features section ............................................................................................... 1
Changes from Revision B (January 2017) to Revision C Page
• Added footnote 2 to the Electrical Characteristics table ........................................................................................................ 8

• Added reverse current protection information to the Reverse-Current Protection section .................................................. 26
Changes from Revision A (April 2016) to Revision B Page
• Added an illustration to the first page ..................................................................................................................................... 1

• Changed the functional block diagram ................................................................................................................................. 15
• Changed Figure 38............................................................................................................................................................... 29
• Added Receiving Notification of Documentation Updates section ....................................................................................... 33
Changes from Original (December 2015) to Revision A Page
• Changed data sheet from PRODUCT PREVIEW to PRODUCTION DATA .......................................................................... 1
2 Submit Documentation Feedback Copyright © 2015–2019, Texas Instruments Incorporated
Product Folder Links: TPS4H160-Q1

TPS4H160-Q1
www.ti.com SLVSCV8D – DECEMBER 2015 – REVISED DECEMBER 2019
5 Device Comparison Table
PART NO. FAULT REPORTING MODE

TPS4H160-Q1 Version A Open-drain digital output
TPS4H160-Q1 Version B Current-sense analog output
6 Pin Configuration and Functions
PWP Package
28-Pin HTSSOP With Exposed Thermal Pad
TPS4H160-Q1 Version A Top View
GND 1 28 OUT1
NC 2 27 OUT1
IN1 3 26 OUT2
IN2 4 25 OUT2
IN3 5 24 NC
IN4 6 23 VS
ST1 7 22 VS
Thermal
Pad
ST2 8 21 VS
ST3 9 20 VS
ST4 10 19 NC
CL 11 18 OUT3
GND 12 17 OUT3
THER 13 16 OUT4
DIAG_EN 14 15 OUT4
NC – No internal connection
Copyright © 2015–2019, Texas Instruments Incorporated Submit Documentation Feedback 3

TPS4H160-Q1
PWP Package
28-Pin HTSSOP With Exposed Thermal Pad
TPS4H160-Q1 Version B Top View
GND 1 28 OUT1
NC 2 27 OUT1
IN1 3 26 OUT2
IN2 4 25 OUT2
IN3 5 24 NC
IN4 6 23 VS
SEH 7 22 VS
Thermal
Pad
SEL 8 21 VS
FAULT 9 20 VS
CS 10 19 NC
CL 11 18 OUT3
GND 12 17 OUT3
THER 13 16 OUT4
DIAG_EN 14 15 OUT4
NC – No internal connection
Pin Functions
PIN
NO. I/O DESCRIPTION
NAME
VERSION A VERSION B
Adjustable current limit. Connect to device GND if external current limit is not
CL 11 11 O
used.
CS — 10 O Current-sense output
DIAG_EN 14 14 I Enable-disable pin for diagnostics; internal pulldown
Global fault report with open-drain structure, ORed logic for quad-channel fault
FAULT — 9 O
conditions
GND 1, 12 1, 12 — Ground pin
IN1 3 3 I Input control for channel 1 activation; internal pulldown
NC 2, 19, 24 2, 19, 24 — No internal connection
ST1 7 — O Open-drain diagnostic status output for channel 1

TPS4H160-Q1
Pin Functions (continued)

PIN
NO. I/O DESCRIPTION
NAME
VERSION A VERSION B
SEH — 7 I CS channel-selection high bit; internal pulldown
SEL — 8 I CS channel-selection low bit; internal pulldown
THER 13 13 I Thermal shutdown behavior control, latch off or auto-retry; internal pulldown
OUT1 27, 28 27, 28 O Output of the channel 1 high side-switch, connected to the load
20, 21, 22, 20, 21, 22,
VS I Power supply
23 23
Thermal
— — — Connect to device GND or leave floating
pad

TPS4H160-Q1
7 Specifications
7.1 Absolute Maximum Ratings
(1) (2)
over operating ambient temperature range (unless otherwise noted)
MIN MAX UNIT
Supply voltage t < 400 ms 48 V
(3)
Reverse polarity voltage –36 V
Current on GND pin t < 2 minutes –100 250 mA
Voltage on INx, DIAG_EN, SEL, SEH, and THER pins –0.3 7 V
Current on INx, DIAG_EN, SEL, SEH, and THER pins –10 — mA
Voltage on STx or FAULT pins –0.3 7 V
Current on STx or FAULT pins –30 10 mA
Voltage on CS pin –2.7 7 V
Current on CS pin — 30 mA
Voltage on CL pin –0.3 7 V
Current on CL pin — 6 mA
Inductive load switch-off energy dissipation, single pulse, single channel (4) — 40 mJ
Operating junction temperature –40 150 °C
Storage temperature, Tstg –65 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to the ground plane.
(3) Reverse polarity condition: t < 60 s, reverse current < IR(2), VINx = 0 V, all channels reverse, GND pin 1-kΩ resistor in parallel with diode.
(4) Test condition: VVS = 13.5 V, L = 8 mH, R = 0 Ω, TJ = 150°C. FR4 2s2p board, 2 × 70-μm Cu, 2 x 35-µm Cu. 600 mm2 thermal pad
copper area.
7.2 ESD Ratings

VALUE UNIT
All pins except VS, OUTx,
Human-body model (HBM), per AEC ±4000
GND
Q100-002 (1)
Pins VS, OUTx, GND ±5000
V(ESD) Electrostatic discharge V
All pins ±750
Charged-device model (CDM), per AEC
Q100-011 Corner pins (1, 14, 15,
±750
and 28)
(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.

TPS4H160-Q1
7.3 Recommended Operating Conditions

over operating ambient temperature range (unless otherwise noted)
MIN MAX UNIT
VVS Supply operating voltage 4 40 V
Voltage on INx, DIAG EN, SEL, SEH, and THER pins 0 5 V
Voltage on STx and FAULT pins 0 5 V
Nominal dc load current 0 2.5 A
TA Operating ambient temperature range –40 125 °C
7.4 Thermal Information

TPS4H160-Q1
THERMAL METRIC (1) PWP (HTSSOP) UNIT
28 PINS
RθJA Junction-to-ambient thermal resistance 32.7 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 17.1 °C/W
RθJB Junction-to-board thermal resistance 14.4 °C/W
ψJT Junction-to-top characterization parameter 0.5 °C/W
ψJB Junction-to-board characterization parameter 14.3 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance 2.1 °C/W
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
7.5 Electrical Characteristics

5 V < VVS < 40 V; −40°C < TJ < 150°C, unless otherwise specified)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
OPERATING VOLTAGE
VVS(nom) Nominal operating voltage 4 40 V
VVS(uvr) Undervoltage turnon VVS rises up 3.5 3.7 4 V
VVS(uvf) Undervoltage shutdown VVS falls down 3 3.2 3.4 V
V(uv,hys) Undervoltage shutdown, hysteresis 0.5 V
OPERATING CURRENT
VVS = 13.5 V, VINx = 5 V, VDIAG_EN = 0 V, IOUTx = 0.5 A,
I(op) Nominal operating current (1) 8 mA
current limit = 2 A, all channels on
VVS = 13.5 V, VINx = VDIAG_EN = VCS = VCL = VOUTx =
THER = 0 V, 0.5
TJ = 25°C
I(off) Standby current µA
VVS = 13.5 V, VINx = VDIAG_EN = VCS = VCL = VOUTx =
THER = 0 V, 5
TJ = 125°C
Standby current with diagnostic VVS = 13.5 V, VINx = 0 V, VDIAG_EN = 5 V, VVS – VOUTx >
I(off,diag) 5 mA
enabled V(ol,off), not in open-load mode
IN from high to low, if deglitch time > t(off,deg), the device
t(off,diag) Standby mode deglitch time (1) 10 12.5 15 ms
enters into standby mode.
Ilkg(out) Output leakage current in off-state VVS = 13.5 V, VINx = VDIAG_EN = VOUTx = 0 3 µA
POWER STAGE
VVS ≥ 3.5 V, TJ = 25°C 165
rDS(on) On-state resistance (1) mΩ
VVS ≥ 3.5 V, TJ = 150°C 280
ICL(int) Internal current limit Internal current limit value, CL pin connected to GND 8 14 A
Internal current limit value under thermal shutdown 6.5 A
Current limit during thermal
ICL(TSD) External current limit value under thermal shutdown. The
shutdown (1) 70%
percentage of the external current limit setting value
VDS(clamp) Drain-to-source internal clamp voltage 50 70 V
(1) Value specified by design, not subject to production test

TPS4H160-Q1
Electrical Characteristics (continued)

5 V < VVS < 40 V; −40°C < TJ < 150°C, unless otherwise specified)
OUTPUT DIODE CHARACTERISTICS
VF Drain−source diode voltage IN = 0, IOUTx = −0.15 A. 0.3 0.7 0.9 V
t < 60 s, VINx = 0 V, TJ = 25°C, single channel reversed,
2.5
short-to-battery condition
Continuous reverse current from
IR(1), IR(2) t < 60 s, VINx = 0 V, GND pin 1-kΩ resistor in parallel with A
source to drain (1)
diode. TJ = 25°C. Reverse-polarity condition, all channels 2
reversed
LOGIC INPUT (INx, DIAG_EN, SEL, SEH, THER)
VIH Logic high-level voltage 2 V
VIL Logic low-level voltage 0.8 V
INx, SEL, SEH, THER, VINx = VSEL = VSEH = VTHER = 5 V 100 175 250
R(logic,pd) Logic-pin pulldown resistor kΩ
DIAG_EN. VVS = VDIAG_EN = 5 V 200 275 350
DIAGNOSTICS
Output leakage current under GND
Ilkg(GND_loss) 100 µA
loss condition
IN = 0 V, when VVS – VOUTx < t(ol,off), duration longer than
V(ol,off) Open-load detection threshold 1.6 2.6 V
t(ol,off), then open load is detected, off state
Open-load detection threshold deglitch IN = 0 V, when VVS – VOUTx < V(ol,off) , duration longer than
td(ol,off) 300 550 800 µs
time (see Figure 3) t(ol,off), then open load is detected, off state
VINx = 0 V, VDIAG_EN = 5 V, VVS = VOUTx = 13.5 V, TJ =
I(ol,off) Off-state output sink current –75 µA
125°C, open load
VOL(STx) Status low-output voltage ISTx = 2 mA, version A only 0.2 V
VOL(FAULT) Fault low-output voltage IFAULT = 2 mA, version B only 0.2 V
Deglitch time when current limit VINx = VDIAG_EN = 5 V, the deglitch time from current limit
tCL(deg) 80 180 µs
occurs (1) toggling to FAULT, STx, CS report.
(1)
T(SD) Thermal shutdown threshold 160 175 °C
Thermal shutdown status reset
T(SD,rst) 155 °C
threshold (1)
(1)
T(SW) Thermal swing shutdown threshold 60 °C
Hysteresis for resetting the thermal
T(hys) 10 °C
shutdown or thermal swing (1)
CURRENT SENSE (Version B) AND CURRENT LIMIT
K(CS) Current-sense ratio 300
K(CL) Current-limit ratio 2500
VCL(th) Current limit internal threshold (1) 0.8 V
VVS = 13.5 V, IOUTx ≥ 5 mA –65% 65%
VVS = 13.5 V, IOUTx ≥ 25 mA –15% 15%
dK(CS) / Current-sense accuracy, (ICS × K(CS) –
VVS = 13.5 V, IOUTx ≥ 50 mA –8% 8%
K(CS) IOUTx) /IOUTx × 100
VVS = 13.5 V, IOUTx ≥ 100 mA –4% 4%
VVS = 13.5 V, IOUTx ≥ 0.5 A –3% 3%
External current limit accuracy (2) VVS = 13.5 V, I(limit) ≥ 0.25 A –20% 20%
dK(CL) / K(CL)
(IOUTx – ICL × K(CL)) × 100 / (ICL × K(CL)) VVS = 13.5 V, 0.5 A ≤ I(limit) ≤ 7 A –15% 15%
VVS ≥ 6.5 V 0 4
VCS(lin) Current-sense voltage linear range (1) VVS – V
5 V ≤ VVS < 6.5 V 0
2.5
VVS ≥ 6.5 V, VCS(lin) ≤ 4 V 0 2.5
IOUTx(lin) Output-current linear range (1) A
5 V ≤ VVS < 6.5 V, VCS(lin) ≤ VVS – 2.5 V 0 2.5
VVS ≥ 7 V, fault mode 4.5 6.5 V
VCS(H) Current sense pin output voltage Min(VVS – 2,
5 V ≤ VVS < 7 V, fault mode 6.5 V
4.5)
ICS(H) Current-sense pin output current VCS = 4.5 V, VVS = 13.5 V 15 mA
Current-sense leakage current in
Ilkg(CS) VDIAG_EN = 0 V, TJ =125ºC 0.5 µA
disabled mode
(2) External current limit accuracy is only applicable to overload conditions greater than 1.5 x the current limit setting

TPS4H160-Q1
7.6 Switching Characteristics

Delay time, VOUTx 10% after VINx↑ (See VVS = 13.5 V, VDIAG_EN = 5 V, IOUTx = 0.5 A, IN rising
td(on) 20 50 90 µs
Figure 1.) edge to 10% of VOUTx
Delay time, VOUTx 90% after VINx↓ (See VVS = 13.5 V, VDIAG_EN = 5 V, IOUTx = 0.5 A, IN falling
td(off) 20 50 90 µs
Figure 1.) edge to 90% of VOUTx
VVS = 13.5 V, VDIAG_EN = 5 V, IOUTx = 0.5 A, VOUTx from
dV/dt(on) Turnon slew rate 0.1 0.3 0.55 V/µs
10% to 90%
VVS = 13.5 V, VDIAG_EN = 5 V, IOUTx = 0.5 A, VOUTx from
dV/dt(off) Turnoff slew rate 0.1 0.3 0.55 V/µs
90% to 10%
VVS = 13.5 V, IL = 0.5A. td, rise is the IN rising edge to
td(match) td(rise) – td(fall) (See Figure 1.) VOUTx = 90%. –50 50 µs
td(fall) is the IN falling edge to VOUTx = 10%.
CURRENT-SENSE CHARACTERISTICS (See Figure 2.)
VVS = 13.5 V, VINx = 5 V, IOUTx = 0.5 A. current limit = 2 A.
tCS(off1) CS settling time from DIAG_EN disabled (1) 20 µs
DIAG_EN falling edge to 10% of VCS.
VVS = 13.5 V, VINx = 5 V, IOUTx = 0.5 A. current limit is 2
tCS(on1) CS settling time from DIAG_EN enabled (1) 20 µs
A. DIAG_EN rising edge to 90% of VCS.
VVS = 13.5 V, VDIAG_EN = 5 V, IOUTx = 0.5 A. current limit =
tCS(off2) CS settling time from IN falling edge 30 100 µs
2 A. IN falling edge to 10% of VCS
VVS = 13.5 V, VDIAG_EN = 5 V, IOUTx = 0.5 A. current limit =
tCS(on2) CS settling time from IN rising edge 50 150 µs
2 A. IN rising edge to 90% of VCS
VDIAG_EN = 5 V, current sense output delay when multi-
Multi-sense transition delay from channel to
tSEx sense pins SEL and SEH transition from channel to 50 µs
channel
channel
(1) Value specified by design, not subject to production test
V INx
90% 90%
dV/dt(off)
VOUTx dV/dt(on)
10% 10%
td(on) td(off)
td(rise) td(fall)
Figure 1. Output Delay Characteristics
VINx
IOUTx
VDIAG_EN
VCS
tCS(on2) tCS(off1) tCS(on1) tCS(off2)
Figure 2. CS Delay Characteristics

TPS4H160-Q1
Open Load
VINx
VCS(H)
VCS
td(ol,off)
VSTx,VFAULT td(ol,off)
Figure 3. Open-Load Blanking-Time Characteristics
SEH
SEL
tSEx
VCS(CH 2)
VCS(CH 1)
VCS
Figure 4. Multi-Sense Transition Delay

TPS4H160-Q1
7.7 Typical Characteristics
1.6 1.7
DIAG_EN High
1.6 DIAG_EN Low
1.5
DIAG_EN Voltage (V)

IN1 High IN3 High 1.5
1.4
INx Voltage (V)
IN1 Low IN3 Low

IN2 High IN4 High 1.4
1.3 IN2 Low IN4 Low
1.3
1.2
1.2
1.1 1.1
1 1
-40 -20 0 20 40 60 80 100 120 140 -40 -20 0 20 40 60 80 100 120 140
Ambient Temperature (qC) D001
Figure 5. INx Voltage Threshold Figure 6. DIAG_EN Voltage Threshold

1.5 0.8
OUT`1
OUT2
0.75 OUT3
1.4
OUT4
Diode Voltage (V)
0.7
SEx Voltage (V)
1.3
0.65
SEx High
1.2
SEx Low
0.6
1.1
0.55
1 0.5
-40 -20 0 20 40 60 80 100 120 140 -40 -20 0 20 40 60 80 100 120 140
Figure 7. SEx Voltage Threshold Figure 8. Body-Diode Forward Voltage

64 0.3
63.5
63 0.25
62.5
Clamp Voltagge (V)
On-Resistance (:)
62 0.2
61.5
61
0.15
60.5
60
59.5 0.1
59 Ch 1
58.5 Ch 2 0.05 3.5 V
Ch 3 13.5 V
58 Ch 4 40 V
57.5 0
-40 -20 0 20 40 60 80 100 120 140 -40 -20 0 20 40 60 80 100 120 140
Figure 9. Drain-to-Source Clamp Voltage Figure 10. Channel-1 FET On-Resistance

TPS4H160-Q1
Typical Characteristics (continued)

0.3 0.3
0.25 0.25
On-Resistance (:)
On-Resistance (:)
0.2 0.2
0.15 0.15
0.1 0.1
0.05 3.5 V 0.05 3.5 V

13.5 V 13.5 V
40 V 40 V
0 0
-40 -20 0 20 40 60 80 100 120 140 -40 -20 0 20 40 60 80 100 120 140
Figure 11. Channel-2 FET On-Resistanc Figure 12. Channel-3 FET On-Resistanc
0.28 18
Ch 1
0.26 16 Ch 2
Ch 3
14 Ch 4
Current Sense Ratio (%)
0.24
On-Resistance (:)
12
0.22
10
0.2
8
0.18
6
0.16
4
3.5 V
0.14 13.5 V 2
40 V
0.12 0
-40 -20 0 20 40 60 80 100 120 140 -40 -20 0 20 40 60 80 100 120 140
Ambient Temperature (ºC) D010
Figure 13. Channel-4 FET On-Resistanc Figure 14. Current-Sense Ratio at 5 mA

2.5 1
Ch 1 Ch 1 Ch 3
2.25 Ch 2 Ch 2 Ch 4
0.8
2 Ch 3
Ch 4
0.6
1.75
1.5 0.4
1.25 0.2
1
0
0.75
-0.2
0.5
0.25 -0.4
0 -0.6
-40 -20 0 20 40 60 80 100 120 140 -40 -20 0 20 40 60 80 100 120 140
Figure 15. Current-Sense Ratio at 25 mA Figure 16. Current-Sense Ratio at 50 mA

TPS4H160-Q1
Typical Characteristics (continued)

1 1
Ch 1 Ch 1
0.8 Ch 2 Ch 2
Ch 3 0.5 Ch 3
0.6
Ch 4 Ch 4

0.4
0
0.2
0 -0.5
-0.2
-1
-0.4
-0.6
-1.5
-0.8
-1 -2
-40 -20 0 20 40 60 80 100 120 140 -40 -20 0 20 40 60 80 100 120 140
Figure 17. Current-Sense Ratio at 100 mA Figure 18. Current-Sense Ratio at 500 mA
1.5
Ch 1
1 Ch 2
Ch 3
Ch 4
0.5
-0.5
-1
-1.5
-2
-40 -20 0 20 40 60 80 100 120 140
Figure 19. Current-Sense Ratio at 1 A

TPS4H160-Q1
8 Detailed Description
8.1 Overview
The TPS4H160-Q1 device is a smart high-side switch, with internal charge pump and quad-channel integrated
NMOS power FETs. Full diagnostics and high-accuracy current-sense features enable intelligent control of the
load. The adjustable current-limit function greatly improves the reliability of whole system. The device has two
versions with different diagnostic reporting, the open-drain digital output (version A) and the current-sense analog
output (version B).
For version A, the device implements the digital fault report with an open-drain structure. When a fault occurs,
the device pulls STx down to GND. A 3.3- or 5-V external pullup is required to match the microcontroller supply
level. The digital status of each channel can report individually, or globally by connecting the STx pins together.
For version B, high-accuracy current sense makes the diagnostics more accurate without further calibration. One
integrated current mirror can source 1 / K(CS) of the load current. The mirrored current flows into the CS-pin
resistor to become a voltage signal. K(CS) is a constant value across temperature and supply voltage. A wide
linear region from 0 V to 4 V allows a better real-time load-current monitoring. The CS pin can also report a fault
with pullup voltage of VCS(H).
The external high-accuracy current limit allows setting the current-limit value by applications. When overcurrent
occurs, the device improves system reliability by clamping the inrush current effectively. The device can also
save system cost by reducing the size of PCB traces and connectors, and the capacity of the preceding power
stage. Besides, the device also implements an internal current limit with a fixed value.
For inductive loads (relays, solenoids, valves), the device implements an active clamp between drain and source
to protect itself. During the inductive switching-off cycle, both the energy of the power supply and the load are
dissipated on the high-side switch. The device also optimizes the switching-off slew rate when the clamp is
active, which helps the system design by keeping the effects of transient power and EMI to a minimum.
The TPS4H160-Q1 device is a smart high-side switch for a wide variety of resistive, inductive, and capacitive
loads, including low-wattage bulbs, LEDs, relays, solenoids, heaters, and sub-modules.

TPS4H160-Q1
8.2 Functional Block Diagram
Internal LDO Temperature Sensor Output VS

Internal Reference Clamp
Auxiliary Charge Pump
Gate Driver
and
INx Charge Pump
Protection OUT1
Oscillator
and
OUT2
Diagnostics
THER
OUT3
CS Current-Sense
Current Sense OUT4
Mux
SEH
ESD
SEL Protection
Current Limit
CL
Current Limit
Reference
FAULT
DIAG_EN 2
GND
STx Diagnosis
Temperature
4 OTP
Sensor
8.3 Feature Description

8.3.1 Pin Current and Voltage Conventions
For reference purposes throughout the data sheet, current directions on their respective pins are as shown by
the arrows in Figure 20. All voltages are measured relative to the ground plane.

TPS4H160-Q1
Feature Description (continued)
Ivs
VS Vvs
VINx IINx
INx
VSTx, ISTx, STX,

VFAULT IFAULT FAULT
IDIAG_EN
VDIAG_EN DIAG_EN IOUTx
OUTx VOUTx
VCL ICL
CL
ICS
VCS CS
ITHER
VTHER THER ISEx
SEx VSEx
GND
IGND
VGND
Ground Plane
Figure 20. Voltage and Current Conventions
8.3.2 Accurate Current Sense

High-accuracy current sense is implemented in the version-B device. It allows a better real-time monitoring effect
and more-accurate diagnostics without further calibration.
One integrated current mirror can source 1 / K(CS) of the load current, and the mirrored current flows into the
external current sense resistor to become a voltage signal. The current mirror is shared by the four channels.
K(CS) is the ratio of the output current and the sense current. It is a constant value across the temperature and
supply voltage. Each device is calibrated accurately during production, so post-calibration is not required. See
Figure 21 for more details.

TPS4H160-Q1
VBAT
VS
IOUT/K(CS)
IOUT
VCS(H)
FAULT 4x
OUTx
CS
R(CS)
Figure 21. Current-Sense Block Diagram
When a fault occurs, the CS pin also works as a fault report with a pullup voltage, VCS(H). See Figure 22 for more
details.
V CS
VCS(H)
VCS(lin)
Fault Report
Current Monitor
I OUTx
Normal Operating On-State: Current Limit, The rmal Fault

Off-State: Open Load or Short to Batte r y
or Reverse Polarity
Figure 22. Current-Sense Output-Voltage Curve
Use Equation 1 to calculate R(CS).

V VCS ´ K (CS)
R (CS) = CS =
I CS I OUTx (1)
Take the following points into consideration when calculating R(CS).
• Ensure VCS is within the current-sense linear region (VCS, IOUTx(lin)) across the full range of the load current.
Check R(CS) with Equation 2.
V VCS(lin)
R (CS) = CS £
I CS I CS (2)
• In fault mode, ensure ICS is within the source capacity of the CS pin (ICS(H)). Check R(CS) with Equation 3.
V VCS(H,min)
R (CS) = CS ³
I CS I CS(H,min) (3)

TPS4H160-Q1

8.3.3 Adjustable Current Limit
A high-accuracy current limit allows high reliability of the design. It protects the load and the power supply from
overstressing during short-circuit-to-GND or power-up conditions. The current limit can also save system cost by
reducing the size of PCB traces and connectors, and the capacity of the preceding power stage.
When a current-limit threshold is hit, a closed loop activates immediately. The output current is clamped at the
set value, and a fault is reported out. The device heats up due to the high power dissipation on the power FET. If
thermal shutdown occurs, the current limit is set to ICL(TSD) to reduce the power dissipation on the power FET.
See Figure 23 for more details.
The device has two current-limit thresholds.
• Internal current limit – The internal current limit is fixed at ICL(int). Tie the CL pin directly to the device GND for
large-transient-current applications.
• External adjustable current limit – An external resistor is used to set the current-limit threashold. Use the
Equation 4 to calculate the R(CL). VCL(th) is the internal band-gap voltage. K(CL) is the ratio of the output current
and the current-limit set value. It is constant across the temperature and supply voltage. The external
adjustable current limit allows the flexibility to set the current limit value by applications.
VCL(th) I OUT
I CL = =
R(CL) K (CL)
VCL(th) ´ K (CL)
R(CL) =
I OUT (4)
VBAT
VS
IOUT/K(CL)
±
Internal Current Limit
+
±
+ IOUT
+
VCL(th)
4x
OUT
External Current Limit
±
+
VCL(th)
CL
Figure 23. Current-Limit Block Diargam

TPS4H160-Q1

Note that if using a GND network which causes a level shift between the device GND and board GND, the CL
pin must be connected with device GND.
For better protection from a hard short-to-GND condition (when the INx pins are enabled, a short to GND occurs
suddenly), the device implements a fast-trip protection to turn off the related channel before the current-limit
closed loop is set up. The fast-trip response time is less than 1 μs, typically. With this fast response, the device
can achieve better inrush current-suppression performance.
8.3.4 Inductive-Load Switching-Off Clamp

When switching an inductive load off, the inductive reactance tends to pull the output voltage negative. Excessive
negative voltage could cause the power FET to break down. To protect the power FET, an internal clamp
between drain and source is implemented, namely VDS(clamp).
VDS(clamp) = VVS - VOUT (5)
During the period of demagnetization (tdecay), the power FET is turned on for inductance-energy dissipation. The
total energy is dissipated in the high-side switch. Total energy includes the energy of the power supply (E(VS))
and the energy of the load (E(load)). If resistance is in series with inductance, some of the load energy is
dissipated on the resistance.
E (HSS) = E (VS) + E (load) = E(VS) + E(L) - E(R) (6)
When an inductive load switches off, E(HSS) causes high thermal stressing on the device.. The upper limit of the
power dissipation depends on the device intrinsic capacity, ambient temperature, and board dissipation condition.
VBAT
VDS(clamp)
IN
L
±
OUT
R
GND
Figure 24. Drain-to-Source Clamping Structure

TPS4H160-Q1
IN
VVS
VOUT
VDS(clamp)
E(HSS)
IOUT
t(decay)
Figure 25. Inductive Load Switching-Off Diagram
From the perspective of the high-side switch, E(HSS) equals the integration value during the demagnetization
period.
t(decay )
E(HSS) =
ò0
VDS(clamp) ´ I OUT (t)dt
L æ R ´ I OUT(max) + VOUT ö
t(decay) = ´ ln ç ÷
R ç VOUT ÷
è ø
VVS + VOUT é æ R ´ I OUT(max) + VOUT öù
E(HSS) = L ´ ´ êR ´ I OUT(max) - VOUT ln ç ÷ú
R2 êë ç VOUT ÷ú
è øû (7)
When R approximately equals 0, E(HSD) can be given simply as:
1 2 VVS + VOUT
E (HSS) = ´ L ´ I OUT(max )
2 VOUT (8)
Figure 26 is a waveform of the device driving an inductive load, and Figure 27 is waveform with an expanded
time scale. Channel 1 is the IN signal, channel 2 is the supply voltage VVS, channel 3 is the output voltage VOUT,
channel 4 is the output current IOUT, and channel M is the measured power dissipation E(HSS).
On the waveform, the duration of VOUT from VVS to (VVS – VDS(clamp)) is around 120 µs. The device also optimizes
the switching-off slew rate when the clamp is active. This optimization can help the system design by keeping the
effects of transient power and EMI to a minimum. As shown in Figure 26 and Figure 27, the controlled slew rate
is around 0.5 V/µs.

TPS4H160-Q1
Figure 26. Inductive Load Switching-Off Waveform Figure 27. Inductive Load Switching-Off Expanded
Waveform
Note that for PWM-controlled inductive loads, it is recommended to add the external freewheeling circuitry shown
in Figure 28 to protect the device from repetitive power stressing. TVS is used to achieve the fast decay. See
Figure 28 for more details.
VS
Output
Clamp
OUTx
GND D
L
TVS
Figure 28. Protection With External Circuitry
8.3.5 Fault Detection and Reporting
8.3.5.1 Diagnostic Enable Function

The DIAG_EN pin enables or disables the diagnostic functions. If multiple devices are used, but the ADC
resource is limited in the microcontroller, the MCU can use GPIOs to set DIAG_EN high to enable the
diagnostics of one device while disabling the diagnostics of the other devices by setting DIAG_EN low. In
addition, the device can keep the power consumption to a minimum by setting DIAG_EN and INx low.
8.3.5.2 Multiplexing of Current Sense

For version B, SEL and SEH are two pins to multiplex the shared current-sense function among the four
channels. See Table 1 for more details.

TPS4H160-Q1

Table 1. Diagnosis Configuration Table
CS ACTIVATED
DIAG_EN INx SEH SEL CS, FAULT, STx PROTECTIONS AND DIAGNOSTICS
CHANNEL
H Diagnostics disabled, full protection
L — — — High impedance
L Diagnostics disabled, no protection
0 0 Channel 1
0 1 Channel 2
H — See Table 2 See Table 2
1 0 Channel 3
1 1 Channel 4
8.3.5.3 Fault Table

Table 2 applies when the DIAG_EN pin is enabled.
Table 2. Fault Table

STx CS FAULT
CONDITIONS INx OUTx THER CRITERION FAULT RECOVERY
(VER. A) (VER. B) (VER. B)
L L — — H 0 H —
Normal In linear
H H — — H H —
region
Current limit
Overlaod, short to ground H L — L VCS(H) L Auto
triggered
Open load (1), short to battery, VVS – VOUTx <
L H — L VCS(H) L Auto
reverse polarity V(ol,off)
Output auto-retry. Fault
L recovers when TJ < T(SD,rst) or
Thermal shutdown H — TSD triggered L VCS(H) L when INx toggles.
Output latch off. Fault recovers
H
when INx toggles.
Thermal swing H — — TSW triggered L VCS(H) L Auto
(1) An external pullup is required for open-load detection.
8.3.5.4 STx and FAULT Reporting

For version A, four individual STx pins report the fault conditions, each pin for its respective channel. When a
fault condition occurs, it pulls STx down to GND. A 3.3- or 5-V external pullup is required to match the supply
level of the microcontroller. The digital status of each channel can be reported individually, or globally by
connecting all the STx pins together.
For version B, a global FAULT pin is used to monitor the global fault condition among all the channels. When a
fault condition occurs on any channel, the FAULT pin is pulled down to GND. A 3.3-V or 5-V external pullup is
required to match the supply level of the microcontroller.
After the FAULT report, the microcontroller can check and identify the channel in fault status by multiplexed
current sensing. The CS pin also works as a fault report with an internal pullup voltage, VCS(H).
8.3.6 Full Diagnostics
8.3.6.1 Short-to-GND and Overload Detection

When a channel is on, a short to GND or overload condition causes overcurrent. If the overcurrent triggers either
the internal or external current-limit threshold, the fault condition is reported out. The microcontroller can handle
the overcurrent by turning off the switch. The device heats up if no actions are taken. If a thermal shutdown
occurs, the current limit is ICL(TSD) to keep the power stressing on the power FET to a minimum. The device
automatically recovers when the fault condition is removed.

TPS4H160-Q1
8.3.6.2 Open-Load Detection
8.3.6.2.1 Channel On
When a channel on, benefiting from the high-accuracy current sense in a small current range, if an open-load
event occurs, it can be detected as an ultralow VCS and handled by the microcontroller. Note that the detection is
not reported on the STx or FAULT pins. The microcontroller must multiplex the SEL and SEH pins to detect the
channel-on open-load fault proactively.
8.3.6.2.2 Channel Off

When a channel is off, if a load is connected, the output is pulled down to GND. But if an open load occurs, the
output voltage is close to the supply voltage (VVS – VOUTx < V(ol,off)), and the fault is reported out.
There is always a leakage current I(ol,off) present on the output due to internal logic control path or external
humidity, corrosion, and so forth. Thus, TI recommends an external pullup resistor to offset the leakage current
when an open load is detected. The recommended pullup resistance is 20 kΩ.
VBAT
Open-Load Detection in Off State
V(ol,off)
R(PU)
VDS
Load
Figure 29. Open-Load Detection in Off-State
8.3.6.3 Short-to-Battery Detection

Short-to-battery has the same detection mechanism and behavior as open-load detection, in both the on-state
and off-state. See Table 2 for more details.
In the on-state, reverse current flows through the FET instead of the body diode, leading to less power
dissipation. Thus, the worst case occurs in the off-state.
• If VOUTx – VVS < V(F) (body diode forward voltage), no reverse current occurs.
• If VOUTx – VVS > V(F), reverse current occurs. The current must be limited to less than IR(1). Setting an INx pin
high can minimize the power stress on its channel. Also, for external reverse protection, see Reverse-Current
Protection for more details.
8.3.6.4 Reverse Polarity Detection

Reverse polarity detection has the same detection mechanism and behavior as open-load detection both in the
on-state and off-state. See Table 2 for more details.
In the on-state, the reverse current flows through the FET instead of the body diode, leading to less power
dissipation. Thus, the worst case occurs in the off-state. The reverse current must be limited to less than IR(2).
Set the related INx pin high to keep the power dissipation to a minimum. For external reverse-blocking circuitry,
see Reverse-Current Protection for more details.

TPS4H160-Q1
8.3.6.5 Thermal Fault Detection

To protect the device in severe power stressing cases, the device implements two types of thermal fault
detection, absolute temperature protection (thermal shutdown) and dynamic temperature protection (thermal
swing). Respective temperature sensors are integrated close to each power FET, so the thermal fault is reported
by each channel. This arrangement can help the device keep the cross-channel effect to a minimum when some
channels are in a thermal fault condition.
8.3.6.5.1 Thermal Shutdown

Thermal shutdown is active when the absolute temperature TJ > T(SD). When thefrmal shutdown occurs, the
respective output turns off. The THER pin is used to configure the behavior after the thermal shutdown occurs.
• When the THER pin is low, thermal shutdown operates in the auto-retry mode. The output automatically
recovers when TJ < T(SD) – T(hys), but the current is limited to ICL(TSD) to avoid repetitive thermal shutdown. The
thermal shutdown fault signal is cleared when TJ < T(SD,rst) or after toggling the related INx pin.
• When the THER pin is high, thermal shutdown operates in the latch mode. The output latches off when
thermal shutdown occurs. When the THER pin goes from high to low, thermal shutdown changes to auto-retry
mode. The thermal shutdown fault signal is cleared after toggling the related INx pin.
Thermal swing activates when the power FET temperature is increasing sharply, that is, when ΔT = T(FET) –
T(Logic) > T(sw), then the output turns off. The output automatically recovers and the fault signal clears when ΔT =
T(FET) – T(Logic) < T(sw) – T(hys). Thermal swing function improves the device reliability when subjected to repetitive
fast thermal variation. As shown in Figure 30, multiple thermal swings are triggered before thermal shutdown
occurs.
Thermal Behavior After Short to GND
V THER
V INx
T(SD)
T(hys) T(SD,rst)
TJ
T(hys)
T(SW)
ICL
IOUTx ICL(TSD)
VCS(H)
VCS
VFAULT
or VST
Figure 30. Thermal Behavior Diagram

TPS4H160-Q1
8.3.7 Full Protections
8.3.7.1 UVLO Protection

The device monitors the supply voltage VVS, to prevent unpredicted behaviors when VVS is too low. When VVS
falls down to VVS(uvf), the device shuts down. When VVS rises up to VVS(uvr), the device turns on.
8.3.7.2 Loss-of-GND Protection

When loss of GND occurs, output is shut down regardless of whether the INx pin is high or low. The device can
protect against two ground-loss conditions, loss of device GND and loss of module GND.
8.3.7.3 Protection for Loss of Power Supply

When loss of supply occurs, the output is shut down regardless of whether the INx pin is high or low. For a
resistive or a capacitive load, loss of supply has no risk. But for a charged inductive load, the current is driven
from all the I/O pinss to maintain the inductance current. To protect the system in this condition, TI recommends
two types of external protections: the GND network or the external free-wheeling diode.
VBAT
VS
I/Os
MCU High-Side Switch
OUT
Figure 31. Protection for Loss of Power Supply, Method 1
VBAT
VS
I/Os
OUT
Figure 32. Protection for Loss of Power Supply, Method 2
8.3.7.4 Reverse-Current Protection

Reverse current occurs in two conditions: short to battery and reverse polarity.
• When a short to the battery occurs, there is only reverse current through the body diode. IR(1) specifies the
limit of the reverse current.
• In a reverse-polarity condition, there are reverse currents through the body diode and the device GND pin.
IR(2) specifies the limit of the reverse current. The GND pin maximum current is specified in the Absolute
TPS4H160-Q1
Maximum Ratings.
To protect the device, TI recommends two types of external circuitry.
• Adding a blocking diode. Both the IC and load are protected when in reverse polarity.
VBAT
VS
´
OUT
Load
Copyright © 2016, Texas Instruments Incorporated
Figure 33. Reverse-Current External Protection, Method 1
• Adding a GND network. The reverse current through the device GND is blocked. The reverse current through
the FET is limited by the load itself. TI recommends a resistor in parallel with the diode as a GND network.
The recommended selection are 1-kΩ resistor in parallel with an >100-mA diode. If multiple high-side
switches are used, the resistor and diode can be shared among devices. The reverse current protection diode
in the GND network forward voltage should be less than 0.6 V in any circumstances. In addition a minimum
resistance of 4.7 K is recommended on the I/O pins.
VBAT
VS
OUT
Load
Figure 34. Reverse-Current External Protection, Method 2
8.3.7.5 MCU I/O Protection

In some severe conditions, such as the ISO7637-2 test or the loss of battery with inductive loads, a negative
pulse occurs on the GND pin This pulse can cause damage on the connected microcontroller. TI recommends
serial resistors to protect the microcontroller, for example, 4.7-kΩ when using a 3.3-V microcontroller and 10-kΩ
for a 5-V microcontroller.

TPS4H160-Q1
VBAT
I/Os
VS

OUT
Load
Figure 35. MCU I/O External Protection
8.4 Device Functional Modes

8.4.1 Working Modes
The device has three working modes, the normal mode, the standby mode, and the standby mode with
diagnostics.
Note that IN must be low for t > t(off,deg) to enter the standby mode, where t(off,deg) is the standby mode deglitch
time used to avoid false triggering. Figure 36 shows a working-mode diagram.
Standby Mode
(INx Low, DIAG Low)
DIAG_EN Low
AND
INx High to Low
DIAG_EN Low to High for
t > t(off,deg)
DIAG_EN High to Low
INx Low to High
Standby Mode INx low to high Normal Mode

With Diagnostics
DIAG_EN High (INx High)
(INx Low, DIAG High)
AND
INx High to Low
for
t > t(off,deg)
Figure 36. Working Modes

TPS4H160-Q1
9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information

The TPS4H160-Q1 device is capable of driving a wide variety of resistive, inductive, and capacitive loads,
including the low-wattage bulbs, LEDs, relays, solenoids, heaters, and sub-modules. Full diagnostics and high-
accuracy current-sense features enable intelligent control of the load. An external adjustable current limit
improves the reliability of the whole system by clamping the inrush or overload current.
9.2 Typical Application

The following figure shows an example of the external circuitry connections based on the version-B device.
VBAT
VS
R(ser) LED Strings,

IN1, 2, 3, 4 OUT1 Small Power Bulbs
R(ser)
DIAG_EN
R(ser) OUT2 Solenoids, Valves, Relays
SEH
R(ser)
MCU Power-Module:
SEL OUT3 Cameras, Sensors, Displays
5V
R(pu)
R(ser) General Resistive, Capacitive,
OUT4 Inductive Loads
FAULT
CS
R(CS) CL
GND THER
R(CL)
Figure 37. Typical Application Diagram
9.2.1 Design Requirements

• VVS range from 9 V to 16 V
• Load range is from 0.1 A to 1 A for each channel
• Current sense for fault monitoring
• Expected current-limit value of 2.5 A
• Automatic recovery mode when thermal shutdown occurs
• Full diagnostics with 5-V MCU

TPS4H160-Q1
Typical Application (continued)

• Reverse-voltage protection with a blocking diode in the power-supply line
9.2.2 Detailed Design Procedure

To keep the 1-A nominal current in the 0 to 4-V current-sense range, calculate the R(CS) resistor using
Equation 9. To achieve better current-sense accuracy, a 1% tolerance or better resistor is preferred.
V VCS ´ K (CS) 4 ´ 300
R (CS) = CS = = = 1200 W
I CS I OUT 1 (9)
To set the adjustable current limit value at 2.5-A, calculate R(CL) using Equation 10.
VCL(th) ´ K (CL) 0.8 ´ 2500
R (CL) = = = 800 W
I OUT 2.5 (10)
TI recommends R(ser) = 10 kΩ for 5-V MCU, and R(pu) = 10 kΩ as the pullup resistor.
9.2.3 Application Curves

Figure 38 shows a test example of soft-start when driving a big capacitive load. Figure 39 shows an expanded
waveform of the output current.
Overcurrent Is Clamped
at the Set Value of 1 A.
VS = 12 V INx = ↑ Current limit = 1 A VVS = 12 V INx = ↑ Current limit = 1 A

Load current = 0.4 CL = 2.3 mF CH1 = INx Load current = 0.4 CL = 2.3 mF CH1 = INx
A A
CH2 = FAULT CH3 = output CH4 = output CH2 = FAULT CH3 = output CH4 = output
voltage current voltage current
Figure 38. Driving a Capacitive Load With Adjustable Figure 39. Driving a Capacitive Load, Expanded Waveform
Current Limit

TPS4H160-Q1
Typical Application (continued)

Figure 40 shows a test example of PWM-mode driving. Figure 41 shows the expanded waveform of the rising
edge. Figure 42 shows the expanded waveform of the falling edge.
VVS = 13.5 V INx = 200-Hz PWM CH1 = INx signal VVS = 13.5 V INx = 200-Hz PWM CH1 = INx signal
at 50% duty cycle at 50% duty cycle
CH2 = CS voltage CH3 = output CH4 = output CH2 = CS voltage CH3 = output CH4 = output
voltage current voltage current
Figure 40. PWM Signal Driving Figure 41. Expanded Waveform of Rising Edge
VVS = 13.5 V INx = 200-Hz PWM at 50% duty cycle CH1 = INx signal
CH2 = CS voltage CH3 = output voltage CH4 = output current
Figure 42. Expanded Waveform of Falling Edge
10 Power Supply Recommendations

The device is qualified for both automotive and industrial applications. The normal power supply connection is a
12-V automotive system or 24-V industrial system. Detailed supply voltage should be within the range specified
in the Recommended Operating Conditions.

TPS4H160-Q1
11 Layout
11.1 Layout Guidelines

To prevent thermal shutdown, TJ must be less than 150°C. The HTSSOP package has good thermal impedance.
However, the PCB layout is very important. Good PCB design can optimize heat transfer, which is absolutely
essential for the long-term reliability of the device.
• Maximize the copper coverage on the PCB to increase the thermal conductivity of the board. The major heat
flow path from the package to the ambient is through the copper on the PCB. Maximum copper is extremely
important when there are not any heat sinks attached to the PCB on the other side of the package.
• Add as many thermal vias as possible directly under the package ground pad to optimize the thermal
conductivity of the board.
• All thermal vias should either be plated shut or plugged and capped on both sides of the board to prevent
solder voids. To ensure reliability and performance, the solder coverage should be at least 85%.
11.2 Layout Examples

11.2.1 Without a GND Network
Without a GND network, tie the thermal pad directly to the board GND copper for better thermal performance.
GND 1 28 OUT1
2 27 OUT1
3 26 OUT2
4 25 OUT2
5 24
6 23 VS
7 Thermal 22 VS
PAD
8 (GND) 21 VS
9 20 VS
10 19
11 18 OUT3
GND 12 17 OUT3
13 16 OUT4
14 15 OUT4
Figure 43. Layout Example Without a GND Network

TPS4H160-Q1
Layout Examples (continued)

11.2.2 With a GND Network
With a GND network, tie the thermal pad as one trace to the board GND copper.
GND Network
GND 1 28 OUT1
2 27 OUT1
3 26 OUT2
4 25 OUT2
5 24
6 23 VS
7 Thermal 22 VS
Pad
8 (GND) 21 VS
9 20 VS
10 19
11 18 OUT3
GND 12 17 OUT3
13 16 OUT4
14 15 OUT4
Figure 44. Layout Example With a GND Network

TPS4H160-Q1
12 Device and Documentation Support
12.1 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
12.2 Community Resources

TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
12.3 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.4 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most-
current data available for the designated device. This data is subject to change without notice and without
revision of this document. For browser-based versions of this data sheet, see the left-hand navigation pane.

PACKAGE OPTION ADDENDUM
www.ti.com 6-Feb-2020
PACKAGING INFORMATION
Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) (6) (3) (4/5)
TPS4H160AQPWPRQ1 ACTIVE HTSSOP PWP 28 2000 Green (RoHS NIPDAU Level-3-260C-168 HR -40 to 125 4H160AQ
& no Sb/Br)
TPS4H160BQPWPRQ1 ACTIVE HTSSOP PWP 28 2000 Green (RoHS NIPDAU Level-3-260C-168 HR -40 to 125 4H160BQ
& no Sb/Br)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com 6-Feb-2020
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com 18-Dec-2019
TAPE AND REEL INFORMATION
*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPS4H160AQPWPRQ1 HTSSOP PWP 28 2000 330.0 16.4 6.9 10.2 1.8 12.0 16.0 Q1
TPS4H160BQPWPRQ1 HTSSOP PWP 28 2000 330.0 16.4 6.9 10.2 1.8 12.0 16.0 Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com 18-Dec-2019
*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TPS4H160AQPWPRQ1 HTSSOP PWP 28 2000 350.0 350.0 43.0
TPS4H160BQPWPRQ1 HTSSOP PWP 28 2000 350.0 350.0 43.0
Pack Materials-Page 2
GENERIC PACKAGE VIEW
TM
PWP 28 PowerPAD TSSOP - 1.2 mm max height
4.4 x 9.7, 0.65 mm pitch SMALL OUTLINE PACKAGE
Images above are just a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4224765/A
www.ti.com
PACKAGE OUTLINE
PWP0028C SCALE 2.000
TM
PowerPAD TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
6.6 C
TYP
A 6.2
PIN 1 INDEX 0.1 C
AREA SEATING
26X 0.65 PLANE
28
1
2X
9.8
8.45
9.6
NOTE 3
14
15
0.30
28X
4.5 0.19
B
4.3 0.1 C A B
SEE DETAIL A
(0.15) TYP
2X 0.95 MAX
NOTE 5
14 15
2X 0.2 MAX
NOTE 5
0.25
GAGE PLANE 1.2 MAX
5.18
4.48
THERMAL
PAD
0.75 0.15
0 -8 0.50 0.05
DETAIL A
A 20
TYPICAL
1 28
3.1
2.4
4223582/A 03/2017
PowerPAD is a trademark of Texas Instruments.
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. Reference JEDEC registration MO-153.
5. Features may differ or may not be present.
www.ti.com
EXAMPLE BOARD LAYOUT
PWP0028C TM
(3.4)
NOTE 9
(3.1)
SYMM METAL COVERED
28X (1.5)
BY SOLDER MASK
1
28X (0.45) 28
SEE DETAILS
(R0.05) TYP
26X (0.65) (5.18)
SYMM (0.6)
(9.7)
NOTE 9
SOLDER MASK (1.2) TYP

DEFINED PAD
( 0.2) TYP
VIA
14 15
(1.2) TYP
(5.8)
LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN
SCALE: 8X
SOLDER MASK METAL UNDER SOLDER MASK

METAL
OPENING SOLDER MASK OPENING
EXPOSED METAL EXPOSED METAL
0.05 MAX 0.05 MIN

ALL AROUND ALL AROUND
NON-SOLDER MASK SOLDER MASK

DEFINED DEFINED
(PREFERRED)
SOLDER MASK DETAILS
15.000
4223582/A 03/2017
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
8. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
numbers SLMA002 (www.ti.com/lit/slma002) and SLMA004 (www.ti.com/lit/slma004).
9. Size of metal pad may vary due to creepage requirement.
10. Vias are optional depending on application, refer to device data sheet. It is recommended that vias under paste be filled, plugged
or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
PWP0028C TM
(3.1)
BASED ON
28X (1.5) 0.125 THICK METAL COVERED
STENCIL BY SOLDER MASK
1
28X (0.45) 28
(R0.05) TYP
26X (0.65)
(5.18)
SYMM BASED ON
0.125 THICK
STENCIL
14 15
SYMM SEE TABLE FOR

DIFFERENT OPENINGS
FOR OTHER STENCIL
(5.8) THICKNESSES
SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL
SCALE: 8X
STENCIL SOLDER STENCIL

THICKNESS OPENING
0.1 3.47 X 5.79
0.125 3.10 X 5.18 (SHOWN)
0.15 2.83 X 4.73
0.175 2.62 X 4.38
4223582/A 03/2017
NOTES: (continued)
11. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
12. Board assembly site may have different recommendations for stencil design.
www.ti.com
IMPORTANT NOTICE AND DISCLAIMER
TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE
DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants you
permission to use these resources only for development of an application that uses the TI products described in the resource. Other
reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third
party intellectual property right. TI disclaims responsibility for, and you will fully indemnify TI and its representatives against, any claims,
damages, costs, losses, and liabilities arising out of your use of these resources.
TI’s products are provided subject to TI’s Terms of Sale (www.ti.com/legal/termsofsale.html) or other applicable terms available either on
ti.com or provided in conjunction with such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable
warranties or warranty disclaimers for TI products.
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2020, Texas Instruments Incorporated

TPS4H160-Q1 40-V, 160-mΩ Quad-Channel Smart High-Side Switch

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TPS4H160-Q1 40-V, 160-mΩ Quad-Channel Smart High-Side Switch

• Added Functional safety capable link to the Features section ............................................................................................... 1

Changes from Revision B (January 2017) to Revision C Page

• Added footnote 2 to the Electrical Characteristics table ........................................................................................................ 8

Changes from Revision A (April 2016) to Revision B Page

• Added an illustration to the first page ..................................................................................................................................... 1

Changes from Original (December 2015) to Revision A Page

• Changed data sheet from PRODUCT PREVIEW to PRODUCTION DATA .......................................................................... 1

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Product Folder Links: TPS4H160-Q1

5 Device Comparison Table

PART NO. FAULT REPORTING MODE

6 Pin Configuration and Functions

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Pin Functions (continued)

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7.2 ESD Ratings

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7.3 Recommended Operating Conditions

7.4 Thermal Information

7.5 Electrical Characteristics

(1) Value specified by design, not subject to production test

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Electrical Characteristics (continued)

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Product Folder Links: TPS4H160-Q1

7.6 Switching Characteristics

(1) Value specified by design, not subject to production test

Figure 1. Output Delay Characteristics

tCS(on2) tCS(off1) tCS(on1) tCS(off2)

Figure 2. CS Delay Characteristics

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Figure 3. Open-Load Blanking-Time Characteristics

Figure 4. Multi-Sense Transition Delay

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7.7 Typical Characteristics

DIAG_EN Voltage (V)

IN1 Low IN3 Low

Figure 5. INx Voltage Threshold Figure 6. DIAG_EN Voltage Threshold

Figure 7. SEx Voltage Threshold Figure 8. Body-Diode Forward Voltage

Figure 9. Drain-to-Source Clamp Voltage Figure 10. Channel-1 FET On-Resistance

Copyright © 2015–2019, Texas Instruments Incorporated Submit Documentation Feedback 11

Typical Characteristics (continued)

0.05 3.5 V 0.05 3.5 V

Figure 13. Channel-4 FET On-Resistanc Figure 14. Current-Sense Ratio at 5 mA

Current Sense Ratio (%)

Figure 15. Current-Sense Ratio at 25 mA Figure 16. Current-Sense Ratio at 50 mA

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Typical Characteristics (continued)

Current Sense Ratio (%)

Figure 19. Current-Sense Ratio at 1 A

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