Datasheet LTC3728L & LTC3728LX PDF

LTC3728L/LTC3728LX
Dual, 550kHz, 2-Phase

Synchronous Regulators
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FEATURES DESCRIPTIO
■ Dual, 180° Phased Controllers Reduce Required The LTC®3728L/LTC3728LX are dual high performance
Input Capacitance and Power Supply Induced Noise step-down switching regulator controllers that drive all
■ OPTI-LOOP® Compensation Minimizes COUT N-channel synchronous power MOSFET stages. A con-
■ ±1% Output Voltage Accuracy (LTC3728LC) stant frequency current mode architecture allows phase-
■ Power Good Output Voltage Indicator lockable frequency of up to 550kHz. Power loss and noise
■ Phase-Lockable Fixed Frequency 250kHz to 550kHz due to the ESR of the input capacitors are minimized by
■ Dual N-Channel MOSFET Synchronous Drive operating the two controller output stages out of phase.
■ Wide VIN Range: 4.5V to 28V Operation OPTI-LOOP compensation allows the transient response
■ Very Low Dropout Operation: 99% Duty Cycle to be optimized over a wide range of output capacitance and
■ Adjustable Soft-Start Current Ramping ESR values. The precision 0.8V reference and power good
■ Foldback Output Current Limiting output indicator are compatible with future microproces-
■ Latched Short-Circuit Shutdown with Defeat Option
sor generations, and a wide 4.5V to 28V (30V maximum)
■ Output Overvoltage Protection input supply range encompasses all battery chemistries.
■ Low Shutdown IQ: 20µA
■ 5V and 3.3V Standby Regulators A RUN/SS pin for each controller provides both soft-start
■ 3 Selectable Operating Modes: Constant Frequency, and optional timed, short-circuit shutdown. Current
Burst Mode® Operation and PWM foldback limits MOSFET dissipation during short-circuit
■ 5mm × 5mm QFN and 28-Lead Narrow SSOP conditions when overcurrent latchoff is disabled. Output
Packages overvoltage protection circuitry latches on the bottom
U MOSFET until VOUT returns to normal. The FCB mode pin
APPLICATIO S can select among Burst Mode, constant frequency mode
■ Notebook and Palmtop Computers and continuous inductor current mode or regulate a
■ Telecom Systems secondary winding. The LTC3728L/LTC3728LX include a
■ Portable Instruments power good output pin that indicates when both outputs
■ Battery-Operated Digital Devices are within 7.5% of their designed set point.
, LTC and LT are registered trademarks of Linear Technology Corporation.
■ DC Power Distribution Systems Burst Mode and OPTI-LOOP are registered trademarks of Linear Technology Corporation.
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TYPICAL APPLICATIO VIN
CIN 5.2V TO 28V
+ 1µF
22µF
4.7µF D3 CERAMIC
D4 50V
M1 VIN PGOOD INTVCC M2 CERAMIC
TG1 TG2
L1 L2
3.2µH BOOST1 BOOST2 3.2µH
CB1, 0.1µF CB2, 0.1µF
SW1 SW2
LTC3728L/
BG1 LTC3728LX BG2
fIN
500kHz PLLIN PGND
SENSE1+ SENSE2 +
RSENSE1 RSENSE2
1000pF 1000pF
0.01Ω 0.01Ω
SENSE1– SENSE2 –
VOUT1 VOSENSE1 VOSENSE2 VOUT2
5V R2 ITH1 ITH2 R4 3.3V
5A 105k CC1 CC2 63.4k 5A
COUT1 1% RUN/SS1 SGND RUN/SS2 COUT
+ 47µF R1 220pF 220pF R3 1%
56µF
+
20k RC1 CSS1 CSS2 RC2 20k
6V 6V
1% 15k 0.1µF 0.1µF 15k 1%
SP SP
M1, M2: FDS6982S

3728 F01
Figure 1. High Efficiency Dual 5V/3.3V Step-Down Converter 3728lxfa
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LTC3728L/LTC3728LX
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ABSOLUTE AXI U RATI GS (Note 1)
Input Supply Voltage (VIN)........................ 30V to – 0.3V ITH1, ITH2, VOSENSE1, VOSENSE2 Voltages ...2.7V to – 0.3V
Top Side Driver Voltages Peak Output Current <10µs (TG1, TG2, BG1, BG2) .. 3A
(BOOST1, BOOST2) .................................. 36V to – 0.3V INTVCC Peak Output Current ................................ 40mA
Switch Voltage (SW1, SW2) ........................ 30V to – 5V Operating Temperature Range (Note 7)
INTVCC, EXTVCC, RUN/SS1, RUN/SS2, (BOOST1-SW1), LTC3728LC/LTC3728LXC ....................... 0°C to 85°C
(BOOST2-SW2), PGOOD ............................ 7V to – 0.3V LTC3728LE ........................................ – 40°C to 85°C
SENSE1+, SENSE2 +, SENSE1–, Junction Temperature (Note 2) ............................ 125°C
SENSE2 – Voltages ....................... (1.1)INTVCC to – 0.3V Storage Temperature Range ................ – 65°C to 125°C
PLLIN, PLLFLTR, FCB, Voltage ........... INTVCC to – 0.3V Reflow Peak Body Temperature (UH Package) .... 260°C
Lead Temperature (Soldering, 10 sec)
(GN Package) ................................................... 300°C
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PACKAGE/ORDER I FOR ATIO
ORDER PART TOP VIEW
ORDER PART
RUN/SS1
SENSE1–
SENSE1+
TOP VIEW
PGOOD
NUMBER NUMBER
SW1
TG1
NC
NC
RUN/SS1 1 28 PGOOD
SENSE1+ 2 27 TG1 32 31 30 29 28 27 26 25
SENSE– 3 26 SW1
LTC3728LCGN VOSENSE1 1 24 BOOST1 LTC3728LCUH
VOSENSE1 4 25 BOOST1 LTC3728LEGN PLLFLTR 2 23 VIN LTC3728LEUH
PLLIN 3 22 BG1
PLLFLTR 5 24 VIN
FCB 4 21 EXTVCC
LTC3728LXCUH
PLLIN 6 23 BG1 33
ITH1 5 20 INTVCC
FCB 7 22 EXTVCC
SGND 6 19 PGND
ITH1 8 21 INTVCC
3.3VOUT 7 18 BG2
SGND 9 20 PGND
ITH2 8 17 BOOST2
3.3VOUT 10 19 BG2
9 10 11 12 13 14 15 16
ITH2 11 18 BOOST2 UH PART
VOSENSE2
NC
SENSE2–
SENSE2+
RUN/SS2
TG2
SW2
NC
VOSENSE2 12 17 SW2
MARKING
SENSE2– 13 16 TG2
SENSE2+ 14 15 RUN/SS2 UH PACKAGE
32-LEAD (5mm × 5mm) PLASTIC QFN
3728L
GN PACKAGE
28-LEAD NARROW PLASTIC SSOP
TJMAX = 125°C, θJA = 34°C/W 3728LE
EXPOSED PAD IS SGND (PIN 33),
TJMAX = 125°C, θJA = 95°C/W
MUST BE SOLDERED TO PCB
3728LX
Consult LTC Marketing for parts specified with wider operating temperature ranges.
ELECTRICAL CHARACTERISTICS The ● denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VIN = 15V, VRUN/SS1, 2 = 5V unless otherwise noted.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
Main Control Loops
VOSENSE1, 2 Regulated Feedback Voltage (Note 3); ITH1, 2 Voltage = 1.2V (LTC3728LC) ● 0.792 0.800 0.808 V
(Note 3); ITH1, 2 Voltage = 1.2V (LTC3728LE/LTC3728LX) ● 0.788 0.800 0.812 V
IVOSENSE1, 2 Feedback Current (Note 3) –5 – 50 nA
VREFLNREG Reference Voltage Line Regulation VIN = 3.6V to 30V (Note 3) 0.002 0.02 %/V
VLOADREG Output Voltage Load Regulation (Note 3)
Measured in Servo Loop; ∆ITH Voltage = 1.2V to 0.7V ● 0.1 0.5 %
Measured in Servo Loop; ∆ITH Voltage = 1.2V to 2.0V ● – 0.1 – 0.5 %
gm1, 2 Transconductance Amplifier gm ITH1, 2 = 1.2V; Sink/Source 5uA; (Note 3) 1.3 mmho
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LTC3728L/LTC3728LX
gmGBW1, 2 Transconductance Amplifier GBW ITH1, 2 = 1.2V; (Note 3) 3 MHz
IQ Input DC Supply Current (Note 4)
Normal Mode VIN = 15V; EXTVCC Tied to VOUT1; VOUT1 = 5V 450 µA
Shutdown VRUN/SS1, 2 = 0V 20 35 µA
VFCB Forced Continuous Threshold ● 0.76 0.800 0.84 V
IFCB Forced Continuous Pin Current VFCB = 0.85V – 0.50 – 0.18 – 0.1 µA
VBINHIBIT Burst Inhibit (Constant Frequency) Measured at FCB pin 4.3 4.8 V
Threshold
UVLO Undervoltage Lockout VIN Ramping Down ● 3.5 4 V
VOVL Feedback Overvoltage Lockout Measured at VOSENSE1, 2 ● 0.84 0.86 0.88 V
ISENSE Sense Pins Total Source Current (Each Channel); VSENSE1–, 2 – = VSENSE1+, 2+ = 0V – 90 – 60 µA
DFMAX Maximum Duty Factor In Dropout 98 99.4 %
IRUN/SS1, 2 Soft-Start Charge Current VRUN/SS1, 2 = 1.9V 0.5 1.2 µA
VRUN/SS1, 2 ON RUN/SS Pin ON Threshold VRUN/SS1, VRUN/SS2 Rising 1.0 1.5 2.0 V
VRUN/SS1, 2 LT RUN/SS Pin Latchoff Arming Threshold VRUN/SS1, VRUN/SS2 Rising from 3V 4.1 4.75 V
ISCL1, 2 RUN/SS Discharge Current Soft Short Condition VOSENSE1, 2 = 0.5V; 0.5 2 4 µA
VRUN/SS1, 2 = 4.5V
ISDLHO Shutdown Latch Disable Current VOSENSE1, 2 = 0.5V 1.6 5 µA
VSENSE(MAX) Maximum Current Sense Threshold VOSENSE1, 2 = 0.7V,VSENSE1–, 2 – = 5V 65 75 85 mV
VOSENSE1, 2 = 0.7V,VSENSE1–, 2 – = 5V ● 62 75 88 mV
TG Transition Time: (Note 5)
TG1, 2 tr Rise Time CLOAD = 3300pF 55 100 ns
TG1, 2 tf Fall Time CLOAD = 3300pF 55 100 ns
BG Transition Time: (Note 5)
BG1, 2 tr Rise Time CLOAD = 3300pF 45 100 ns
BG1, 2 tf Fall Time CLOAD = 3300pF 45 90 ns
TG/BG t1D Top Gate Off to Bottom Gate On Delay
Synchronous Switch-On Delay Time CLOAD = 3300pF Each Driver 80 ns
BG/TG t2D Bottom Gate Off to Top Gate On Delay
Top Switch-On Delay Time CLOAD = 3300pF Each Driver 80 ns
tON(MIN) Minimum On-Time Tested with a Square Wave (Note 6) 100 ns
INTVCC Linear Regulator
VINTVCC Internal VCC Voltage 6V < VIN < 30V, VEXTVCC = 4V 4.8 5.0 5.2 V
VLDO INT INTVCC Load Regulation ICC = 0 to 20mA, VEXTVCC = 4V 0.2 2.0 %
VLDO EXT EXTVCC Voltage Drop ICC = 20mA, VEXTVCC = 5V 100 200 mV
VEXTVCC EXTVCC Switchover Voltage ICC = 20mA, EXTVCC Ramping Positive ● 4.5 4.7 V
VLDOHYS EXTVCC Hysteresis 0.2 V
Oscillator and Phase-Locked Loop
fNOM Nominal Frequency VPLLFLTR = 1.2V 360 400 440 kHz
fLOW Lowest Frequency VPLLFLTR = 0V 230 260 290 kHz
fHIGH Highest Frequency VPLLFLTR ≥ 2.4V 480 550 590 kHz
RPLLIN PLLIN Input Resistance 50 kΩ
I PLLFLTR Phase Detector Output Current
Sinking Capability fPLLIN < fOSC –15 µA
Sourcing Capability fPLLIN > fOSC 15 µA
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LTC3728L/LTC3728LX
3.3V Linear Regulator
V3.3OUT 3.3V Regulator Output Voltage No Load ● 3.2 3.35 3.45 V
V3.3IL 3.3V Regulator Load Regulation I3.3 = 0 to 10mA 0.5 2 %
V3.3VL 3.3V Regulator Line Regulation 6V < VIN < 30V 0.05 0.2 %
PGOOD Output
VPGL PGOOD Voltage Low IPGOOD = 2mA 0.1 0.3 V
IPGOOD PGOOD Leakage Current VPGOOD = 5V ±1 µA
VPG PGOOD Trip Level, Either Controller VOSENSE with Respect to Set Output Voltage
VOSENSE Ramping Negative –6 –7.5 – 9.5 %
VOSENSE Ramping Positive 6 7.5 9.5 %
Note 1: Absolute Maximum Ratings are those values beyond which the life delivered at the switching frequency. See Applications Information.
of a device may be impaired. Note 5: Rise and fall times are measured using 10% and 90% levels. Delay
Note 2: TJ is calculated from the ambient temperature TA and power times are measured using 50% levels.
dissipation PD according to the following formulas: Note 6: The minimum on-time condition is specified for an inductor
LTC3728LUH/LTC3728LXUH: TJ = TA + (PD • 34°C/W) peak-to-peak ripple current ≥ 40% of IMAX (see minimum on-time
LTC3728LGN: TJ = TA + (PD • 95°C/W) considerations in the Applications Information section).
Note 3: The IC is tested in a feedback loop that servos VITH1, 2 to a Note 7: The LTC3728LC/LTC3728LXC are guaranteed to meet
specified voltage and measures the resultant VOSENSE1, 2. performance specifications from 0°C to 85°C. The LTC3728LE is
Note 4: Dynamic supply current is higher due to the gate charge being guaranteed to meet performance specifications over the –40°C to 85°C
operating temperature range as assured by design, characterization and
correlation with statistical process controls.
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TYPICAL PERFOR A CE CHARACTERISTICS
Efficiency vs Output Current Efficiency vs Output Current Efficiency vs Input Voltage
and Mode (Figure 13) (Figure 13) (Figure 13)
100 100 100
Burst Mode VIN = 7V
90 OPERATION
80 90 90
70 VIN = 10V
FORCED
EFFICIENCY (%)
EFFICIENCY (%)
EFFICIENCY (%)
VIN = 15V
60 CONTINUOUS 80 80
MODE (PWM)
50 VIN = 20V
40 CONSTANT 70 70
30 FREQUENCY
(BURST DISABLE)
20 60 60
VIN = 15V VOUT = 5V
10 VOUT = 5V VOUT = 5V IOUT = 3A
f = 250kHz f = 250kHz f = 250kHz
0 50 50
0.001 0.01 0.1 1 10 0.001 0.01 0.1 1 10 5 15 25 35
OUTPUT CURRENT (A) OUTPUT CURRENT (A) INPUT VOLTAGE (V)
3728L G01 3728L G02 3728L G03
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LTC3728L/LTC3728LX
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Supply Current vs Input Voltage INTVCC and EXTVCC Switch
and Mode (Figure 13) EXTVCC Voltage Drop Voltage vs Temperature
1000 200 5.05
INTVCC AND EXTVCC SWITCH VOLTAGE (V)

INTVCC VOLTAGE
5.00
EXTVCC VOLTAGE DROP (mV)

800
150
SUPPLY CURRENT (µA)
4.95
600
4.90
BOTH
CONTROLLERS ON 100
4.85
400
4.80
50
200 EXTVCC SWITCHOVER THRESHOLD
4.75
SHUTDOWN
0 0 4.70
0 5 10 15 20 25 30 0 10 20 30 40 – 50 – 25 0 25 50 75 100 125
INPUT VOLTAGE (V) CURRENT (mA) TEMPERATURE (°C)
3728L G04 3728L G05 3728L G06
Maximum Current Sense Threshold

Maximum Current Sense Threshold vs Percent of Nominal Output
Internal 5V LDO Line Regulation vs Duty Factor Voltage (Foldback)
5.1 75 80
ILOAD = 1mA
5.0 70
60
4.9
INTVCC VOLTAGE (V)
50
50
VSENSE (mV)
VSENSE (mV)
4.8
40
4.7
30
25
4.6
20
4.5 10
4.4 0 0
0 5 10 15 20 25 30 0 20 40 60 80 100 0 25 50 75 100
INPUT VOLTAGE (V) DUTY FACTOR (%) PERCENT ON NOMINAL OUTPUT VOLTAGE (%)
3728L G07 3728L G08 3728L G09
Maximum Current Sense Threshold Maximum Current Sense Threshold Current Sense Threshold
vs VRUN/SS (Soft-Start) vs Sense Common Mode Voltage vs ITH Voltage
80 80 90
VSENSE(CM) = 1.6V
80
70
76
60 60
50
VSENSE (mV)
VSENSE (mV)
VSENSE (mV)
72 40
40 30
68 20
10
20 0
64
–10
–20
0 60 –30
0 1 2 3 4 5 6 0 1 2 3 4 5 0 0.5 1 1.5 2 2.5
VRUN/SS (V) COMMON MODE VOLTAGE (V) VITH (V)
3728L G10 3728L G11 3728L G12
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LTC3728L/LTC3728LX
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Load Regulation VITH vs VRUN/SS SENSE Pins Total Source Current
0.0 2.5 100
FCB = 0V VOSENSE = 0.7V
VIN = 15V
FIGURE 13
2.0
–0.1 50
NORMALIZED VOUT (%)
ISENSE (µA)
1.5
VITH (V)
–0.2 0
1.0
–0.3 –50
0.5
–0.4 0 –100
0 1 2 3 4 5 0 1 2 3 4 5 6 0 2 4 6
LOAD CURRENT (A) VRUN/SS (V) VSENSE COMMON MODE VOLTAGE (V)
3728L G13 3728L G14 3728L G15
Maximum Current Sense Dropout Voltage vs Output Current

Threshold vs Temperature (Figure 14) RUN/SS Current vs Temperature
80 4 1.8
VOUT = 5V
1.6
78
3 1.4
DROPOUT VOLTAGE (V)
RUN/SS CURRENT (µA)

1.2
VSENSE (mV)
76
1.0
2
0.8
74 RSENSE = 0.015Ω
0.6
1
72 0.4
RSENSE = 0.010Ω
0.2
70 0 0
–50 –25 0 25 50 75 100 125 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 –50 –25 0 25 50 75 100 125
TEMPERATURE (°C) OUTPUT CURRENT (A) TEMPERATURE (°C)
3728L G17 3728L G18 3728L G25
Soft-Start Up (Figure 13) Load Step (Figure 13) Load Step (Figure 13)
VOUT
5V/DIV VOUT VOUT
200mV/DIV 200mV/DIV
VRUN/SS
5V/DIV
IL IL
2A/DIV
IL 2A/DIV
2A/DIV
VIN = 15V 5ms/DIV 3728L G19 VIN = 15V 20µs/DIV 3728L G20 VIN = 15V 20µs/DIV 3728L G21
VOUT = 5V VOUT = 5V VOUT = 5V

VPLLFLTR = 0V VPLLFLTR = 0V
LOAD STEP = 0A TO 3A LOAD STEP = 0A TO 3A
Burst Mode OPERATION CONTINUOUS MODE
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LTC3728L/LTC3728LX
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Input Source/Capacitor Constant Frequency (Burst Inhibit)
Instantaneous Current (Figure 13) Burst Mode Operation (Figure 13) Operation (Figure 13)
IIN
VOUT
2A/DIV VOUT
20mV/DIV
VIN 20mV/DIV
200mV/DIV
VSW1
10V/DIV
VSW2 IL
10V/DIV 0.5A/DIV IL
0.5A/DIV
VIN = 15V 1µs/DIV 3728L G22 VIN = 15V 10µs/DIV 3728L G23 VIN = 15V 2µs/DIV 3728L G24
VOUT1 = 5V, VOUT2 = 3.3V VOUT = 5V VOUT = 5V

VPLLFLTR = 0V VPLLFLTR = 0V VPLLFLTR = 0V
IOUT5 = IOUT3.3 = 2A VFCB = OPEN VFCB = 5V
IOUT = 20mA IOUT = 20mA
Current Sense Pin Input Current EXTVCC Switch Resistance Oscillator Frequency
vs Temperature vs Temperature vs Temperature
35 10 700
VOUT = 5V
CURRENT SENSE INPUT CURRENT (µA)
600
EXTVCC SWITCH RESISTANCE (Ω)
VPLLFLTR = 2.4V
33 8
500
FREQUENCY (kHz)
31 6 VPLLFLTR = 1.2V
400
29 4 300 VPLLFLTR = 0V
200
27 2
100
25 0 0
–50 –25 0 25 50 75 100 125 –50 –25 0 25 50 75 100 125 – 50 – 25 0 25 50 75 100 125
TEMPERATURE (°C) TEMPERATURE (°C) TEMPERATURE (°C)
3728L G26 3728L G27 3728L G28
Undervoltage Lockout Shutdown Latch Thresholds

vs Temperature vs Temperature
3.50 4.5
LATCH ARMING
4.0
SHUTDOWN LATCH THRESHOLDS (V)
3.45
UNDERVOLTAGE LOCKOUT (V)
3.5
LATCHOFF
3.40 3.0 THRESHOLD
2.5
3.35
2.0
3.30 1.5
1.0
3.25
0.5
3.20 0
–50 –25 0 25 50 75 100 125 –50 –25 0 25 50 75 100 125
TEMPERATURE (°C) TEMPERATURE (°C)
3728L G29 3728L G30
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LTC3728L/LTC3728LX
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PI FU CTIO S
VOSENSE1, VOSENSE2: Error Amplifier Feedback Input. Re- is also invoked via this pin as described in the Applications
ceives the remotely-sensed feedback voltage for each Information section.
controller from an external resistive divider across the TG2, TG1: High Current Gate Drives for Top N-Channel
output. MOSFETs. These are the outputs of floating drivers with a
PLLFLTR: Filter Connection for Phase-Locked Loop. Al- voltage swing equal to INTVCC – 0.5V superimposed on
ternatively, this pin can be driven with an AC or DC voltage the switch node voltage SW.
source to vary the frequency of the internal oscillator.
SW2, SW1: Switch Node Connections to Inductors. Volt-
PLLIN: External Synchronization Input to Phase Detector. age swing at these pins is from a Schottky diode (external)
This pin is internally terminated to SGND with 50kΩ. The voltage drop below ground to VIN.
phase-locked loop will force the rising top gate signal of BOOST2, BOOST1: Bootstrapped Supplies to the Top Side
controller 1 to be synchronized with the rising edge of the Floating Drivers. Capacitors are connected between the
PLLIN signal. boost and switch pins and Schottky diodes are tied be-
FCB: Forced Continuous Control Input. This input acts on tween the boost and INTVCC pins. Voltage swing at the
both controllers and is normally used to regulate a boost pins is from INTVCC to (VIN + INTVCC).
secondary winding. Pulling this pin below 0.8V will force BG2, BG1: High Current Gate Drives for Bottom (Synchro-
continuous synchronous operation. nous) N-Channel MOSFETs. Voltage swing at these pins is
ITH1, ITH2: Error Amplifier Output and Switching Regulator from ground to INTVCC.
Compensation Point. Each associated channels’ current PGND: Driver Power Ground. Connects to the sources of
comparator trip point increases with this control voltage. bottom (synchronous) N-channel MOSFETs, anodes of the
SGND: Small Signal Ground. Common to both con- Schottky rectifiers and the (–) terminal(s) of CIN.
trollers, this pin must be routed separately from high INTVCC: Output of the Internal 5V Linear Low Dropout
current grounds to the common (–) terminals of the
Regulator and the EXTVCC Switch. The driver and control
COUT capacitors.
circuits are powered from this voltage source. Must be
3.3VOUT: Lnear Regulator Output. Capable of supplying decoupled to power ground with a minimum of 4.7µF tanta-
10mA DC with peak currents as high as 50mA. lum or other low ESR capacitor.
NC: No Connect. EXTVCC: External Power Input to an Internal Switch Con-
nected to INTVCC. This switch closes and supplies VCC
SENSE2 –, SENSE1 –: The (–) Input to the Differential
power, bypassing the internal low dropout regulator, when-
Current Comparators.
ever EXTVCC is higher than 4.7V. See EXTVCC connection
SENSE2 +, SENSE1 +: The (+) Input to the Differential in Applications section. Do not exceed 7V on this pin.
Current Comparators. The ITH pin voltage and controlled
VIN: Main Supply Pin. A bypass capacitor should be tied
offsets between the SENSE– and SENSE+ pins in conjunc-
between this pin and the signal ground pin.
tion with RSENSE set the current trip threshold.
PGOOD: Open-Drain Logic Output. PGOOD is pulled to
RUN/SS2, RUN/SS1: Combination of soft-start, run con-
ground when the voltage on either VOSENSE pin is not
trol inputs and short-circuit detection timers. A capacitor
within ±7.5% of its set point.
to ground at each of these pins sets the ramp time to full
output current. Forcing either of these pins back below Exposed Pad (UH Package Only): Signal Ground. Must be
1.0V causes the IC to shut down the circuitry required for soldered to the PCB, providing a local ground for the
that particular controller. Latchoff overcurrent protection control components of the IC, and be tied to the PGND pin
under the IC.
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LTC3728L/LTC3728LX
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FU CTIO AL DIAGRA
PLLIN
INTVCC VIN
FIN PHASE DET
DUPLICATE FOR SECOND DB
50k BOOST
CONTROLLER CHANNEL
PLLFLTR
TG CB
CLK1 DROP TOP +
RLP OUT CIN
OSCILLATOR D1
CLK2 DET BOT FCB
CLP
TOP ON SW
– 0.86V
S Q
+ SWITCH
R Q INTVCC
VOSENSE1 LOGIC
PGOOD BG
–
BOT
+ 0.74V
COUT
PGND
– 0.86V 0.55V +
B + VOUT
+ –
SHDN RSENSE
VOSENSE2
–
+ 0.74V INTVCC
INTVCC I1 I2
3V + –
4.5V – – ++ – +
0.18µA BINH – +
+ 30k SENSE
R6 FCB 3mV
0.86V
+ 4(VFB) –
30k SENSE
FCB
R5 –
SLOPE
COMP 45k 45k
3.3VOUT 0.8V 2.4V VOSENSE

VFB R2
+ VREF
–
– EA
+ 0.80V R1
VIN OV
+
VIN
– 0.86V
4.8V + CC
ITH
5V 1.2µA
EXTVCC – LDO
REG SHDN RUN
RST CC2 RC
SOFT
INTVCC 6V 4(VFB) START
5V
+ RUN/SS
SGND (UH PACKAGE PAD) INTERNAL

SUPPLY CSS
3728 FD/F02
Figure 2
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OPERATIO (Refer to Functional Diagram)
Main Control Loop inductor current at which I1 resets the RS latch is con-
trolled by the voltage on the ITH pin, which is the output of
The IC uses a constant frequency, current mode step-
each error amplifier EA. The VOSENSE pin receives the
down architecture with the two controller channels oper-
voltage feedback signal, which is compared to the internal
ating 180 degrees out of phase. During normal operation,
each top MOSFET is turned on when the clock for that reference voltage by the EA. When the load current in-
creases, it causes a slight decrease in VOSENSE relative to
channel sets the RS latch, and turned off when the main
the 0.8V reference, which in turn causes the ITH voltage to
current comparator, I1, resets the RS latch. The peak
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LTC3728L/LTC3728LX
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increase until the average inductor current matches the temporarily inhibit turn-on of both output MOSFETs until
new load current. After the top MOSFET has turned off, the the output voltage drops. There is 60mV of hysteresis in
bottom MOSFET is turned on until either the inductor the burst comparator B tied to the ITH pin. This hysteresis
current starts to reverse, as indicated by current compara- produces output signals to the MOSFETs that turn them
tor I2, or the beginning of the next cycle. on for several cycles, followed by a variable “sleep”
interval depending upon the load current. The resultant
The top MOSFET drivers are biased from floating boot-
output voltage ripple is held to a very small value by
strap capacitor CB, which normally is recharged during
each off cycle through an external diode when the top having the hysteretic comparator after the error amplifier
gain block.
MOSFET turns off. As VIN decreases to a voltage close to
VOUT, the loop may enter dropout and attempt to turn on Frequency Synchronization
the top MOSFET continuously. The dropout detector de-
tects this and forces the top MOSFET off for about 400ns The phase-locked loop allows the internal oscillator to be
every tenth cycle to allow CB to recharge. synchronized to an external source via the PLLIN pin. The
output of the phase detector at the PLLFLTR pin is also the
The main control loop is shut down by pulling the RUN/SS DC frequency control input of the oscillator that operates
pin low. Releasing RUN/SS allows an internal 1.2µA over a 260kHz to 550kHz range corresponding to a DC
current source to charge soft-start capacitor CSS. When voltage input from 0V to 2.4V. When locked, the PLL aligns
CSS reaches 1.5V, the main control loop is enabled with the the turn on of the top MOSFET to the rising edge of the
ITH voltage clamped at approximately 30% of its maximum synchronizing signal. When PLLIN is left open, the PLLFLTR
value. As CSS continues to charge, the ITH pin voltage is pin goes low, forcing the oscillator to minimum frequency.
gradually released allowing normal, full-current opera-
tion. When both RUN/SS1 and RUN/SS2 are low, all Constant Frequency Operation
controller functions are shut down, including the 5V and
3.3V regulators. When the FCB pin is tied to INTVCC, Burst Mode operation
is disabled and the forced minimum output current
Low Current Operation requirement is removed. This provides constant frequency,
discontinuous current (preventing reverse inductor cur-
The FCB pin is a multifunction pin providing two func- rent) operation over the widest possible output current
tions: 1) to provide regulation for a secondary winding by range. This constant frequency operation is not as efficient
temporarily forcing continuous PWM operation on as Burst Mode operation, but does provide a lower noise,
both controllers; and 2) to select between two modes of constant frequency operating mode down to approxi-
low current operation. When the FCB pin voltage is below mately 1% of the designed maximum output current.
0.8V, the controller forces continuous PWM current
mode operation. In this mode, the top and bottom Continuous Current (PWM) Operation
MOSFETs are alternately turned on to maintain the output
voltage independent of direction of inductor current. Tying the FCB pin to ground will force continuous current
When the FCB pin is below VINTVCC␣ –␣ 2V but greater than operation. This is the least efficient operating mode, but
0.8V, the controller enters Burst Mode operation. Burst may be desirable in certain applications. The output can
Mode operation sets a minimum output current level source or sink current in this mode. When sinking current
before inhibiting the top switch and turns off the synchro- while in forced continuous operation, current will be
nous MOSFET(s) when the inductor current goes nega- forced back into the main power supply potentially boost-
tive. This combination of requirements will, at low cur- ing the input supply to dangerous voltage levels—
rents, force the ITH pin below a voltage threshold that will BEWARE!
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LTC3728L/LTC3728LX
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INTVCC/EXTVCC Power This built-in latchoff can be overridden by providing a
Power for the top and bottom MOSFET drivers and most >5µA pull-up at a compliance of 5V to the RUN/SS pin(s).
other internal circuitry is derived from the INTVCC pin. This current shortens the soft start period but also pre-
When the EXTVCC pin is left open, an internal 5V low vents net discharge of the RUN/SS capacitor(s) during an
dropout linear regulator supplies INTVCC power. If EXTVCC overcurrent and/or short-circuit condition. Foldback cur-
is taken above 4.7V, the 5V regulator is turned off and an rent limiting is also activated when the output voltage falls
internal switch is turned on connecting EXTVCC to INTVCC. below 70% of its nominal level whether or not the short-
This allows the INTVCC power to be derived from a high circuit latchoff circuit is enabled. Even if a short is present
efficiency external source such as the output of the regu- and the short-circuit latchoff is not enabled, a safe, low
lator itself or a secondary winding, as described in the output current is provided due to internal current foldback
Applications Information section. and actual power wasted is low due to the efficient nature
of the current mode switching regulator.
Output Overvoltage Protection
THEORY AND BENEFITS OF 2-PHASE OPERATION
An overvoltage comparator, OV, guards against transient
overshoots (>7.5%) as well as other more serious condi- The LTC1628 and the LTC3728L family of dual high
tions that may overvoltage the output. In this case, the top efficiency DC/DC controllers brings the considerable ben-
MOSFET is turned off and the bottom MOSFET is turned on efits of 2-phase operation to portable applications for the
until the overvoltage condition is cleared. first time. Notebook computers, PDAs, handheld termi-
nals and automotive electronics will all benefit from the
Power Good (PGOOD) Pin lower input filtering requirement, reduced electromag-
The PGOOD pin is connected to an open drain of an internal netic interference (EMI) and increased efficiency associ-
MOSFET. The MOSFET turns on and pulls the pin low when ated with 2-phase operation.
either output is not within ±7.5% of the nominal output Why the need for 2-phase operation? Up until the 2-phase
level as determined by the resistive feedback divider. family, constant-frequency dual switching regulators op-
When both outputs meet the ±7.5% requirement, the erated both channels in phase (i.e., single-phase opera-
MOSFET is turned off within 10µs and the pin is allowed to tion). This means that both switches turned on at the same
be pulled up by an external resistor to a source of up to 7V. time, causing current pulses of up to twice the amplitude
of those for one regulator to be drawn from the input
Foldback Current, Short-Circuit Detection capacitor and battery. These large amplitude current pulses
and Short-Circuit Latchoff increased the total RMS current flowing from the input
The RUN/SS capacitors are used initially to limit the inrush capacitor, requiring the use of more expensive input
current of each switching regulator. After the controller capacitors and increasing both EMI and losses in the input
has been started and been given adequate time to charge capacitor and battery.
up the output capacitors and provide full load current, the With 2-phase operation, the two channels of the dual-
RUN/SS capacitor is used in a short-circuit time-out switching regulator are operated 180 degrees out of
circuit. If the output voltage falls to less than 70% of its phase. This effectively interleaves the current pulses
nominal output voltage, the RUN/SS capacitor begins drawn by the switches, greatly reducing the overlap time
discharging on the assumption that the output is in an where they add together. The result is a significant reduc-
overcurrent and/or short-circuit condition. If the condition in total RMS input current, which in turn allows less
tion lasts for a long enough period as determined by the expensive input capacitors to be used, reduces shielding
size of the RUN/SS capacitor, the controller will be shut requirements for EMI and improves real world operating
down until the RUN/SS pin(s) voltage(s) are recycled. efficiency.
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5V SWITCH
20V/DIV
3.3V SWITCH
20V/DIV
INPUT CURRENT
5A/DIV
INPUT VOLTAGE
500mV/DIV
IIN(MEAS) = 2.53ARMS DC236 F03a IIN(MEAS) = 1.55ARMS DC236 F03b
(a) (b)
Figure 3. Input Waveforms Comparing Single-Phase (a) and 2-Phase (b) Operation for Dual Switching Regulators
Converting 12V to 5V and 3.3V at 3A Each. The Reduced Input Ripple with the LTC1628 2-Phase Regulator Allows
Less Expensive Input Capacitors, Reduces Shielding Requirements for EMI and Improves Efficiency
Figure 3 compares the input waveforms for a representa- regulators, why hasn’t it been done before? The answer is
tive single-phase dual switching regulator to the LTC1628 that, while simple in concept, it is hard to implement.
2-phase dual switching regulator. An actual measurement Constant-frequency current mode switching regulators
of the RMS input current under these conditions shows require an oscillator derived “slope compensation” signal
that 2-phase operation dropped the input current from to allow stable operation of each regulator at over 50%
2.53ARMS to 1.55ARMS. While this is an impressive reduc- duty cycle. This signal is relatively easy to derive in single-
tion in itself, remember that the power losses are propor- phase dual switching regulators, but required the develop-
tional to IRMS2, meaning that the actual power wasted is ment of a new and proprietary technique to allow 2-phase
reduced by a factor of 2.66. The reduced input ripple operation. In addition, isolation between the two channels
voltage also means less power is lost in the input power becomes more critical with 2-phase operation because
path, which could include batteries, switches, trace/con- switch transitions in one channel could potentially disrupt
nector resistances and protection circuitry. Improvements the operation of the other channel.
in both conducted and radiated EMI also directly accrue as These 2-phase parts are proof that these hurdles have
a result of the reduced RMS input current and voltage. been surmounted. They offer unique advantages for the
Of course, the improvement afforded by 2-phase opera- ever-expanding number of high efficiency power supplies
tion is a function of the dual switching regulator’s relative required in portable electronics.
duty cycles which, in turn, are dependent upon the input
3.0
voltage VIN (Duty Cycle = VOUT/VIN). Figure 4 shows how SINGLE PHASE
the RMS input current varies for single-phase and 2-phase 2.5 DUAL CONTROLLER
operation for 3.3V and 5V regulators over a wide input

INPUT RMS CURRENT (A)
2.0
voltage range.
It can readily be seen that the advantages of 2-phase 1.5
2-PHASE
operation are not just limited to a narrow operating range, 1.0
DUAL CONTROLLER
but in fact extend over a wide region. A good rule of thumb

for most applications is that 2-phase operation will reduce 0.5
VO1 = 5V/3A
the input capacitor requirement to that for just one channel VO2 = 3.3V/3A
0
operating at maximum current and 50% duty cycle. 0 10 20 30 40
INPUT VOLTAGE (V)
A final question: If 2-phase operation offers such an 3728 F04
advantage over single-phase operation for dual switching Figure 4. RMS Input Current Comparison
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APPLICATIO S I FOR ATIO
2.5
Figure 1 on the first page is a basic LTC3728L/LTC3728LX
application circuit. External component selection is driven
2.0
by the load requirement, and begins with the selection of
PLLFLTR PIN VOLTAGE (V)

RSENSE and the inductor value. Next, the power MOSFETs
1.5
and D1 are selected. Finally, CIN and COUT are selected.
The circuit shown in Figure 1 can be configured for 1.0
operation up to an input voltage of 28V (limited by the
external MOSFETs). 0.5
RSENSE Selection For Output Current 0

200 300 400 500 600
RSENSE is chosen based on the required output current. OPERATING FREQUENCY (kHz)
The current comparator has a maximum threshold of 3728 F05
75mV/RSENSE and an input common mode range of SGND Figure 5. PLLFLTR Pin Voltage vs Frequency
to 1.1(INTVCC). The current comparator threshold sets the
peak of the inductor current, yielding a maximum average
is increased the gate charge losses will be higher, reducing
output current IMAX equal to the peak value less half the
efficiency (see Efficiency Considerations). The maximum
peak-to-peak ripple current, ∆IL.
switching frequency is approximately 550kHz.
Allowing a margin for variations in the IC and external
component values yields: Inductor Value Calculation
The operating frequency and inductor selection are inter-
50mV
RSENSE = related in that higher operating frequencies allow the use
IMAX of smaller inductor and capacitor values. So why would
anyone ever choose to operate at lower frequencies with
When using the controller in very low dropout conditions,
larger components? The answer is efficiency. A higher
the maximum output current level will be reduced due to
frequency generally results in lower efficiency because of
the internal compensation required to meet stability crite- MOSFET gate charge losses. In addition to this basic
rion for buck regulators operating at greater than 50% trade-off, the effect of inductor value on ripple current and
duty factor. A curve is provided to estimate this reduction low current operation must also be considered.
in peak output current level depending upon the operating
duty factor. The inductor value has a direct effect on ripple current. The
inductor ripple current ∆IL decreases with higher induc-
Operating Frequency tance or frequency and increases with higher VIN:
The IC uses a constant frequency phase-lockable architec-  V 
1
ture with the frequency determined by an internal capaci- ∆IL = VOUT  1 – OUT 
tor. This capacitor is charged by a fixed current plus an ( f)(L)  VIN 
additional current which is proportional to the voltage
Accepting larger values of ∆IL allows the use of low
applied to the PLLFLTR pin. Refer to Phase-Locked Loop
inductances, but results in higher output voltage ripple
and Frequency Synchronization in the Applications Infor-
and greater core losses. A reasonable starting point for
mation section for additional information.
setting ripple current is ∆IL=0.3(IMAX). The maximum ∆IL
A graph for the voltage applied to the PLLFLTR pin vs occurs at the maximum input voltage.
frequency is given in Figure 5. As the operating frequency
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The inductor value also has secondary effects. The transi- The peak-to-peak drive levels are set by the INTVCC
tion to Burst Mode operation begins when the average voltage. This voltage is typically 5V during start-up (see
inductor current required results in a peak current below EXTVCC Pin Connection). Consequently, logic-level
25% of the current limit determined by RSENSE. Lower threshold MOSFETs must be used in most applications.
inductor values (higher ∆IL) will cause this to occur at The only exception is if low input voltage is expected
lower load currents, which can cause a dip in efficiency in (VIN < 5V); then, sub-logic level threshold MOSFETs
the upper range of low current operation. In Burst Mode (VGS(TH) < 3V) should be used. Pay close attention to the
operation, lower inductance values will cause the burst BVDSS specification for the MOSFETs as well; most of the
frequency to decrease. logic level MOSFETs are limited to 30V or less.
Inductor Core Selection Selection criteria for the power MOSFETs include the “ON”
resistance RDS(ON), Miller capacitance CMILLER, input volt-
Once the value for L is known, the type of inductor must age and maximum output current. Miller capacitance,
be selected. High efficiency converters generally cannot CMILLER, can be approximated from the gate charge curve
afford the core loss found in low cost powdered iron usually provided on the MOSFET manufacturers’ data
cores, forcing the use of more expensive ferrite, molyper- sheet. CMILLER is equal to the increase in gate charge along
malloy, or Kool Mµ® cores. Actual core loss is indepen- the horizontal axis while the curve is approximately flat
dent of core size for a fixed inductor value, but it is very divided by the specified change in VDS. This result is then
dependent on inductance selected. As inductance in- multiplied by the ratio of the application applied VDS to the
creases, core losses go down. Unfortunately, increased Gate charge curve specified VDS. When the IC is operating
inductance requires more turns of wire and therefore in continuous mode the duty cycles for the top and bottom
copper losses will increase. MOSFETs are given by:
Ferrite designs have very low core loss and are preferred VOUT
at high switching frequencies, so design goals can con- Main Switch Duty Cycle =
VIN
centrate on copper loss and preventing saturation. Ferrite
core material saturates “hard,” which means that induc- VIN – VOUT
tance collapses abruptly when the peak design current is Synchronous Switch Duty Cycle =
VIN
exceeded. This results in an abrupt increase in inductor
ripple current and consequent output voltage ripple. Do The MOSFET power dissipations at maximum output
not allow the core to saturate! current are given by:
Molypermalloy (from Magnetics, Inc.) is a very good, low
VOUT
( )( )
loss core material for toroids, but it is more expensive than 2
PMAIN = IMAX 1 + δ RDS(ON) +
ferrite. A reasonable compromise from the same manu- VIN
facturer is Kool Mµ. Toroids are very space efficient, 2 I 
especially when you can use several layers of wire. Be- ( ) ( )(
VIN  MAX  RDR C MILLER •
 2 
)
cause they generally lack a bobbin, mounting is more
 1 
difficult. However, designs for surface mount are available
that do not increase the height significantly. 
1
+
 VINTVCC – VTHMIN VTHMIN 
f ()
Power MOSFET and D1 Selection
VIN – VOUT
( ) (1+ δ)RDS(ON)
2
Two external power MOSFETs must be selected for each PSYNC = IMAX
controller in the LTC3728L/LTC3728LX: One N-channel VIN
MOSFET for the top (main) switch, and one N-channel
MOSFET for the bottom (synchronous) switch. Kool Mµ is a registered trademark of Magnetics, Inc.
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where δ is the temperature dependency of RDS(ON) and of 30% to 70% when compared to a single phase power
RDR (approximately 4Ω) is the effective driver resistance supply solution.
at the MOSFET’s Miller threshold voltage. VTHMIN is the
The type of input capacitor, value and ESR rating have
typical MOSFET minimum threshold voltage.
efficiency effects that need to be considered in the selec-
Both MOSFETs have I2R losses while the topside N-channel tion process. The capacitance value chosen should be
equation includes an additional term for transition losses, sufficient to store adequate charge to keep high peak
which are highest at high input voltages. For VIN < 20V the battery currents down. 20µF to 40µF is usually sufficient
high current efficiency generally improves with larger for a 25W output supply operating at 200kHz. The ESR of
MOSFETs, while for VIN > 20V the transition losses rapidly the capacitor is important for capacitor power dissipation
increase to the point that the use of a higher RDS(ON) device as well as overall battery efficiency. All of the power (RMS
with lower CMILLER actually provides higher efficiency. The ripple current • ESR) not only heats up the capacitor but
synchronous MOSFET losses are greatest at high input wastes power from the battery.
voltage when the top switch duty factor is low or during a
Medium voltage (20V to 35V) ceramic, tantalum, OS-CON
short-circuit when the synchronous switch is on close to
and switcher-rated electrolytic capacitors can be used as
100% of the period.
input capacitors, but each has drawbacks: ceramic voltage
The term (1+δ) is generally given for a MOSFET in the form coefficients are very high and may have audible piezoelec-
of a normalized RDS(ON) vs Temperature curve, but tric effects; tantalums need to be surge-rated; OS-CONs
δ = 0.005/°C can be used as an approximation for low suffer from higher inductance, larger case size and limited
voltage MOSFETs. surface-mount applicability; electrolytics’ higher ESR and
The Schottky diode D1 shown in Figure 1 conducts during dryout possibility require several to be used. Multiphase
the dead-time between the conduction of the two power systems allow the lowest amount of capacitance overall.
MOSFETs. This prevents the body diode of the bottom As little as one 22µF or two to three 10µF ceramic capaci-
MOSFET from turning on, storing charge during the dead- tors are an ideal choice in a 20W to 35W power supply due
time and requiring a reverse recovery period that could to their extremely low ESR. Even though the capacitance
cost as much as 3% in efficiency at high VIN. A 1A to 3A at 20V is substantially below their rating at zero-bias, very
Schottky is generally a good compromise for both regions low ESR loss makes ceramics an ideal candidate for
of operation due to the relatively small average current. highest efficiency battery operated systems. Also con-
Larger diodes result in additional transition losses due to sider parallel ceramic and high quality electrolytic capaci-
their larger junction capacitance. tors as an effective means of achieving ESR and bulk
capacitance goals.
CIN and COUT Selection In continuous mode, the source current of the top N-chan-
The selection of CIN is simplified by the multiphase archi- nel MOSFET is a square wave of duty cycle VOUT/VIN. To
tecture and its impact on the worst-case RMS current prevent large voltage transients, a low ESR input capacitor
drawn through the input network (battery/fuse/capacitor). sized for the maximum RMS current of one channel must
It can be shown that the worst case RMS current occurs be used. The maximum RMS capacitor current is given by:
[V (V )]
when only one controller is operating. The controller with 1/ 2
the highest (VOUT)(IOUT) product needs to be used in the OUT IN − VOUT
formula below to determine the maximum RMS current CIN RequiredIRMS ≈ IMAX
VIN
requirement. Increasing the output current, drawn from
the other out-of-phase controller, will actually decrease This formula has a maximum at VIN = 2VOUT, where
the input RMS ripple current from this maximum value IRMS = IOUT/2. This simple worst case condition is com-
(see Figure 4). The out-of-phase technique typically re- monly used for design because even significant deviations
duces the input capacitor’s RMS ripple current by a factor do not offer much relief. Note that capacitor manufacturer’s
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LTC3728L/LTC3728LX
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ripple current ratings are often based on only 2000 hours The first condition relates to the ripple current into the
of life. This makes it advisable to further derate the ESR of the output capacitance while the second term
capacitor, or to choose a capacitor rated at a higher guarantees that the output capacitance does not signifi-
temperature than required. Several capacitors may also be cantly discharge during the operating frequency period
paralleled to meet size or height requirements in the due to ripple current. The choice of using smaller output
design. Always consult the manufacturer if there is any capacitance increases the ripple voltage due to the dis-
question. charging term but can be compensated for by using
capacitors of very low ESR to maintain the ripple voltage
The benefit of the LTC3728L/LTC3728LX multiphase clock-
at or below 50mV. The ITH pin OPTI-LOOP compensation
ing can be calculated by using the equation above for the
components can be optimized to provide stable, high
higher power controller and then calculating the loss that
performance transient response regardless of the output
would have resulted if both controller channels switched
capacitors selected.
on at the same time. The total RMS power lost is lower
when both controllers are operating due to the interleaving Manufacturers such as Nichicon, United Chemi-Con and
of current pulses through the input capacitor’s ESR. This Sanyo can be considered for high performance through-
is why the input capacitor’s requirement calculated above hole capacitors. The OS-CON semiconductor dielectric
for the worst-case controller is adequate for the dual capacitor available from Sanyo has the lowest (ESR)(size)
controller design. Remember that input protection fuse product of any aluminum electrolytic at a somewhat
resistance, battery resistance and PC board trace resis- higher price. An additional ceramic capacitor in parallel
tance losses are also reduced due to the reduced peak with OS-CON capacitors is recommended to reduce the
currents in a multiphase system. The overall benefit of a inductance effects.
multiphase design will only be fully realized when the In surface mount applications multiple capacitors may
source impedance of the power supply/battery is included need to be used in parallel to meet ESR, RMS current
in the efficiency testing. The drains of the two top MOSFETS handling and load step requirements. Aluminum electro-
should be placed within 1cm of each other and share a lytic, dry tantalum and special polymer capacitors are
common CIN(s). Separating the drains and CIN may pro-
available in surface mount packages. Special polymer
duce undesirable voltage and current resonances at VIN. surface mount capacitors offer very low ESR but have
The selection of COUT is driven by the required effective lower storage capacity per unit volume than other capaci-
series resistance (ESR). Typically once the ESR require- tor types. These capacitors offer a very cost-effective
ment is satisfied the capacitance is adequate for filtering. output capacitor solution and are an ideal choice when
The output ripple (∆VOUT) is determined by: combined with a controller having high loop bandwidth.
Tantalum capacitors offer the highest capacitance density
 1  and are often used as output capacitors for switching
∆VOUT ≈ ∆IL  ESR +  regulators having controlled soft-start. Several excellent
 8 fCOUT 
surge-tested choices are the AVX TPS, AVX TPSV or the
Where f = operating frequency, COUT = output capacitance, KEMET T510 series of surface mount tantalums, available
and ∆IL= ripple current in the inductor. The output ripple in case heights ranging from 2mm to 4mm. Aluminum
is highest at maximum input voltage since ∆IL increases electrolytic capacitors can be used in cost-driven applica-
with input voltage. With ∆IL = 0.3IOUT(MAX) the output tions providing that consideration is given to ripple cur-
ripple will typically be less than 50mV at the maximum VIN rent ratings, temperature and long term reliability. A
assuming: typical application will require several to many aluminum
electrolytic capacitors in parallel. A combination of the
COUT Recommended ESR < 2 RSENSE
above mentioned capacitors will often result in maximiz-
and COUT > 1/(8fRSENSE) ing performance and minimizing overall cost. Other ca-
pacitor types include Nichicon PL series, Panasonic SP,
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NEC Neocap, Cornell Dubilier ESRE and Sprague 595D current drawn from the internal 3.3V linear regulator. To
series. Consult manufacturers for other specific recom- prevent maximum junction temperature from being
mendations. exceeded, the input supply current must be checked
operating in continuous mode at maximum VIN.
INTVCC Regulator
An internal P-channel low dropout regulator produces 5V EXTVCC Connection
at the INTVCC pin from the VIN supply pin. INTVCC powers The IC contains an internal P-channel MOSFET switch
the drivers and internal circuitry within the IC. The INTV CC connected between the EXTVCC and INTVCC pins. When
pin regulator can supply a peak current of 50mA and must the voltage applied to EXTVCC rises above 4.7V, the inter-
be bypassed to ground with a minimum of 4.7µF tanta- nal regulator is turned off and the switch closes, connect-
lum, 10µF special polymer, or low ESR type electrolytic ing the EXTVCC pin to the INTVCC pin thereby supplying
capacitor. A 1µF ceramic capacitor placed directly adja- internal power. The switch remains closed as long as the
cent to the INTVCC and PGND IC pins is highly recom- voltage applied to EXTVCC remains above 4.5V. This
mended. Good bypassing is necessary to supply the high allows the MOSFET driver and control power to be derived
transient currents required by the␣ MOSFET gate drivers from the output during normal operation (4.7V < VOUT <
and to prevent interaction between channels. 7V) and from the internal regulator when the output is out
Higher input voltage applications in which large MOSFETs of regulation (start-up, short-circuit). If more
are being driven at high frequencies may cause the maxi- current is required through the EXTVCC switch than is
mum junction temperature rating for the IC to be ex- specified, an external Schottky diode can be added be-
ceeded. The system supply current is normally dominated tween the EXTVCC and INTVCC pins. Do not apply greater
by the gate charge current. Additional external loading of than 7V to the EXTVCC pin and ensure that EXTVCC␣ <␣ VIN.
the INTVCC and 3.3V linear regulators also needs to be Significant efficiency gains can be realized by powering
taken into account for the power dissipation calculations. INTVCC from the output, since the VIN current resulting
The total INTVCC current can be supplied by either the 5V from the driver and control currents will be scaled by a
internal linear regulator or by the EXTVCC input pin. When factor of (Duty Cycle)/(Efficiency). For 5V regulators this
the voltage applied to the EXTVCC pin is less than 4.7V, all supply means connecting the EXTVCC pin directly to VOUT.
of the INTVCC current is supplied by the internal 5V linear However, for 3.3V and other lower voltage regulators,
regulator. Power dissipation for the IC in this case is additional circuitry is required to derive INTVCC power
highest: (VIN)(IINTVCC), and overall efficiency is lowered. from the output.
The gate charge current is dependent on operating fre-
The following list summarizes the four possible connec-
quency as discussed in the Efficiency Considerations
tions for EXTVCC:
section. The junction temperature can be estimated by
using the equations given in Note 2 of the Electrical 1. EXTVCC Left Open (or Grounded). This will cause INTVCC
Characteristics. For example, the IC VIN current is ther- to be powered from the internal 5V regulator resulting in
mally limited to less than 67mA from a 24V supply when an efficiency penalty of up to 10% at high input voltages.
not using the EXTVCC pin as follows: 2. EXTVCC Connected directly to VOUT. This is the normal
TJ = 70°C + (67mA)(24V)(34°C/W) = 125°C connection for a 5V regulator and provides the highest
efficiency.
Use of the EXTVCC input pin reduces the junction tempera-
ture to: 3. EXTVCC Connected to an External supply. If an external
supply is available in the 5V to 7V range, it may be used to
TJ = 70°C + (67mA)(5V)(34°C/W) = 81°C
power EXTVCC providing it is compatible with the MOSFET
The absolute maximum rating for the INTVCC Pin is 40mA. gate drive requirements.
Dissipation should be calculated to also include any added
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4. EXTVCC Connected to an Output-Derived Boost Net- Output Voltage
work. For 3.3V and other low voltage regulators, efficiency The output voltages are each set by an external feedback
gains can still be realized by connecting EXTVCC to an resistive divider carefully placed across the output capaci-
output-derived voltage that has been boosted to greater
tor. The resultant feedback signal is compared with the
than 4.7V. This can be done with either the inductive boost internal precision 0.800V voltage reference by the error
winding as shown in Figure 6a or the capacitive charge
amplifier. The output voltage is given by the equation:
pump shown in Figure 6b. The charge pump has the
advantage of simple magnetics.  R2 
VOUT = 0.8V 1 + 
Topside MOSFET Driver Supply (CB, DB)  R1
External bootstrap capacitors CB connected to the BOOST where R1 and R2 are defined in Figure 2.
pins supply the gate drive voltages for the topside MOSFETs.
Capacitor CB in the functional diagram is charged though SENSE+/SENSE– Pins
external diode DB from INTVCC when the SW pin is low.
The common mode input range of the current comparator
When one of the topside MOSFETs is to be turned on, the
sense pins is from 0V to (1.1)INTVCC. Continuous linear
driver places the CB voltage across the gate-source of the
operation is guaranteed throughout this range allowing
desired MOSFET. This enhances the MOSFET and turns on
output voltage setting from 0.8V to 7.7V, depending upon
the topside switch. The switch node voltage, SW, rises to
the voltage applied to EXTVCC. A differential NPN input
VIN and the BOOST pin follows. With the topside MOSFET
stage is biased with internal resistors from an internal
on, the boost voltage is above the input supply: VBOOST =
2.4V source as shown in the Functional Diagram. This
VIN + VINTVCC. The value of the boost capacitor CB needs
requires that current either be sourced or sunk from the
to be 100 times that of the total input capacitance of the
topside MOSFET(s). The reverse breakdown of the exter- SENSE pins depending on the output voltage. If the output
voltage is below 2.4V current will flow out of both SENSE
nal Schottky diode must be greater than VIN(MAX). When
pins to the main output. The output can be easily preloaded
adjusting the gate drive level, the final arbiter is the total
input current for the regulator. If a change is made and the by the VOUT resistive divider to compensate for the current
comparator’s negative input bias current. The maximum
input current decreases, then the efficiency has improved.
current flowing out of each pair of SENSE pins is:
If there is no change in input current, then there is no
change in efficiency. ISENSE+ + ISENSE– = (2.4V – VOUT)/24k
VIN VIN
+
1µF
OPTIONAL EXTVCC
CONNECTION
5V < VSEC < 7V
+ +
CIN CIN
BAT 85 BAT85 0.22µF BAT85

VIN VSEC VIN
LTC3728L/ + LTC3728L/
LTC3728LX 1µF LTC3728LX BAT85
TG1 VN2222LL
TG1
RSENSE RSENSE
N-CH VOUT N-CH VOUT
EXTVCC SW T1 EXTVCC SW L1
1:N
R6
+ +
FCB BG1 COUT BG1 COUT
R5 N-CH N-CH
SGND PGND PGND
3728 F06a 3728 F06b
Figure 6a. Secondary Output Loop & EXTVCC Connection Figure 6b. Capacitive Charge Pump for EXTVCC
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Since VOSENSE is servoed to the 0.8V reference voltage, we VIN INTVCC
3.3V OR 5V RUN/SS
can choose R1 in Figure 2 to have a maximum value to RSS* RSS*
D1
absorb this current. RUN/SS
CSS
 0.8V 
R1(MAX) = 24k  CSS
 2.4V – VOUT 
*OPTIONAL TO DEFEAT OVERCURRENT LATCHOFF
for VOUT < 2.4V (a) (b) 3728 F07
Regulating an output voltage of 1.8V, the maximum value Figure 7. RUN/SS Pin Interfacing
of R1 should be 32k. Note that for an output voltage above
2.4V, R1 has no maximum value necessary to absorb the ramp up slowly providing the soft-start function. Each
sense currents; however, R1 is still bounded by the RUN/SS pin has an internal 6V zener clamp (See Func-
VOSENSE feedback current. tional Diagram).
Soft-Start/Run Function Fault Conditions: Overcurrent Latchoff
The RUN/SS1 and RUN/SS2 pins are multipurpose pins The RUN/SS pins also provide the ability to latch off the
that provide a soft-start function and a means to shut controller(s) when an overcurrent condition is detected.
down the LTC3728L/LTC3728LX. Soft-start reduces the The RUN/SS capacitor, CSS, is used initially to turn on and
input power source’s surge currents by gradually increas- limit the inrush current. After the controller has been
ing the controller’s current limit (proportional to VITH). started and been given adequate time to charge up the
This pin can also be used for power supply sequencing. output capacitor and provide full load current, the RUN/SS
An internal 1.2µA current source charges up the CSS capacitor is used for a short-circuit timer. If the regulator’s
capacitor. When the voltage on RUN/SS1 (RUN/SS2) output voltage falls to less than 70% of its nominal value
reaches 1.5V, the particular controller is permitted to start after CSS reaches 4.1V, CSS begins discharging on the
operating. As the voltage on RUN/SS increases from 1.5V assumption that the output is in an overcurrent condition.
to 3.0V, the internal current limit is increased from 25mV/ If the condition lasts for a long enough period as deter-
RSENSE to 75mV/RSENSE. The output current limit ramps mined by the size of the CSS and the specified discharge
up slowly, taking an additional 1.25s/µF to reach full current, the controller will be shut down until the RUN/SS
current. The output current thus ramps up slowly, reduc- pin voltage is recycled. If the overload occurs during start-
ing the starting surge current required from the input up, the time can be approximated by:
power supply. If RUN/SS has been pulled all the way to tLO1 ≈ [CSS (4.1 – 1.5 + 4.1 – 3.5)]/(1.2µA)
ground there is a delay before starting of approximately:
= 2.7 • 106 (CSS)
tDELAY =
1.5V
1.2µA
( )
C SS = 1.25s / µF C SS If the overload occurs after start-up the voltage on CSS will
begin discharging from the zener clamp voltage:
tLO2 ≈ [CSS (6 – 3.5)]/(1.2µA) = 2.1 • 106 (CSS)
tIRAMP =
3V − 1.5V
1.2µA
( )
C SS = 1.25s / µF C SS This built-in overcurrent latchoff can be overridden by
providing a pull-up resistor to the RUN/SS pin as shown
By pulling both RUN/SS pins below 1V, the IC is put into in Figure 7. This resistance shortens the soft-start period
low current shutdown (IQ = 20µA). The RUN/SS pins can and prevents the discharge of the RUN/SS capacitor
be driven directly from logic as shown in Figure 7. Diode during an over current condition. Tying this pull-up resis-
D1 in Figure 7 reduces the start delay but allows C SS to tor to VIN, as in Figure 7a, defeats overcurrent latchoff.
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LTC3728L/LTC3728LX
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Diode-connecting this pull-up resistor to INTV CC, as in ∆IL(SC) = tON(MIN) (VIN/L)
Figure 7b, eliminates any extra supply current during The resulting short-circuit current is:
controller shutdown while eliminating the INTV CC loading
from preventing controller start-up. 25mV 1
ISC = – ∆IL(SC)
Why should you defeat overcurrent latchoff? During the RSENSE 2
prototyping stage of a design, there may be a problem
with noise pickup or poor layout causing the protection Fault Conditions: Overvoltage Protection (Crowbar)
circuit to latch off. Defeating this feature will easily allow
The overvoltage crowbar is designed to blow a system
troubleshooting of the circuit and PC layout. The internal
input fuse when the output voltage of the regulator rises
short-circuit and foldback current limiting still remains
much higher than nominal levels. The crowbar causes
active, thereby protecting the power supply system from
huge currents to flow, that blow the fuse to protect against
failure. After the design is complete, a decision can be
a shorted top MOSFET if the short occurs while the
made whether to enable the latchoff feature.
controller is operating.
The value of the soft-start capacitor CSS may need to be
scaled with output voltage, output capacitance and load A comparator monitors the output for overvoltage condi-
current characteristics. The minimum soft-start capaci- tions. The comparator (OV) detects overvoltage faults
tance is given by: greater than 7.5% above the nominal output voltage.
When this condition is sensed, the top MOSFET is turned
CSS > (COUT )(VOUT) (10 – 4) (RSENSE) off and the bottom MOSFET is turned on until the overvolt-
The minimum recommended soft-start capacitor of age condition is cleared. The output of this comparator is
CSS = 0.1µF will be sufficient for most applications. only latched by the overvoltage condition itself and will
therefore allow a switching regulator system having a poor
Fault Conditions: Current Limit and Current Foldback PC layout to function while the design is being debugged.
The bottom MOSFET remains on continuously for as long
The current comparators have a maximum sense voltage
as the OV condition persists; if VOUT returns to a safe level,
of 75mV resulting in a maximum MOSFET current of
normal operation automatically resumes. A shorted top
75mV/RSENSE. The maximum value of current limit gener-
MOSFET will result in a high current condition which will
ally occurs with the largest VIN at the highest ambient
open the system fuse. The switching regulator will regu-
temperature, conditions that cause the highest power
late properly with a leaky top MOSFET by altering the duty
dissipation in the top MOSFET.
cycle to accommodate the leakage.
Each controller includes current foldback to help further
limit load current when the output is shorted to ground. Phase-Locked Loop and Frequency Synchronization
The foldback circuit is active even when the overload The IC has a phase-locked loop comprised of an internal
shutdown latch described above is overridden. If the voltage controlled oscillator and phase detector. This
output falls below 70% of its nominal output level, then the allows the top MOSFET turn-on to be locked to the rising
maximum sense voltage is progressively lowered from edge of an external source. The frequency range of the
75mV to 25mV. Under short-circuit conditions with very voltage controlled oscillator is ±50% around the center
low duty cycles, the controller will begin cycle skipping in frequency fO. A voltage applied to the PLLFLTR pin of 1.2V
order to limit the short-circuit current. In this situation the corresponds to a frequency of approximately 400kHz. The
bottom MOSFET will be dissipating most of the power but nominal operating frequency range of the IC is 260kHz to
less than in normal operation. The short-circuit ripple 550kHz.
current is determined by the minimum on-time tON(MIN) of
each controller (typically 100ns), the input voltage and
inductor value:
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LTC3728L/LTC3728LX
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The phase detector used is an edge sensitive digital type Minimum On-Time Considerations
which provides zero degrees phase shift between the
Minimum on-time tON(MIN) is the smallest time duration
external and internal oscillators. This type of phase detec- that each controller is capable of turning on the top
tor will not lock up on input frequencies close to the MOSFET. It is determined by internal timing delays and the
harmonics of the VCO center frequency. The PLL hold-in gate charge required to turn on the top MOSFET. Low duty
range, ∆fH, is equal to the capture range, ∆fC: cycle applications may approach this minimum on-time
∆fH = ∆fC = ±0.5 fO (260kHz-550kHz) limit and care should be taken to ensure that
The output of the phase detector is a complementary pair
VOUT
of current sources charging or discharging the external tON(MIN) <
filter network on the PLLFLTR pin. A simplified block VIN (f)
diagram is shown in Figure 7.
If the duty cycle falls below what can be accommodated by
If the external frequency (fPLLIN) is greater than the oscil- the minimum on-time, the controller will begin to skip
lator frequency f0SC, current is sourced continuously, cycles. The output voltage will continue to be regulated,
pulling up the PLLFLTR pin. When the external frequency but the ripple voltage and current will increase.
is less than f0SC, current is sunk continuously, pulling
down the PLLFLTR pin. If the external and internal fre- The minimum on-time for each controller is approximately
quencies are the same but exhibit a phase difference, the 100ns. However, as the peak sense voltage decreases the
current sources turn on for an amount of time correspond- minimum on-time gradually increases up to about 150ns.
ing to the phase difference. Thus the voltage on the This is of particular concern in forced continuous applica-
PLLFLTR pin is adjusted until the phase and frequency of tions with low ripple current at light loads. If the duty cycle
the external and internal oscillators are identical. At this drops below the minimum on-time limit in this situation,
stable operating point the phase comparator output is a significant amount of cycle skipping can occur with
open and the filter capacitor CLP holds the voltage. The IC’s correspondingly larger current and voltage ripple.
PLLIN pin must be driven from a low impedance source
FCB Pin Operation
such as a logic gate located close to the pin. When using
multiple ICs for a phase-locked system, the PLLFLTR pin The FCB pin can be used to regulate a secondary winding
of the master oscillator should be biased at a voltage that or as a logic level input. Continuous operation is forced on
will guarantee the slave oscillator(s) ability to lock onto the both controllers when the FCB pin drops below 0.8V.
master’s frequency. A DC voltage of 0.7V to 1.7V applied During continuous mode, current flows continuously in
to the master oscillator’s PLLFLTR pin is recommended in the transformer primary. The secondary winding(s) draw
order to meet this requirement. The resultant operating current only when the bottom, synchronous switch is on.
frequency can range from 300kHz to 500kHz. When primary load currents are low and/or the VIN/VOUT
ratio is low, the synchronous switch may not be on for a
The loop filter components (CLP, RLP) smooth out the
sufficient amount of time to transfer power from the
current pulses from the phase detector and provide a
output capacitor to the secondary load. Forced continuous
stable input to the voltage controlled oscillator. The filter
operation will support secondary windings providing there
components CLP and RLP determine how fast the loop
is sufficient synchronous switch duty factor. Thus, the
acquires lock. Typically RLP =10kΩ and CLP is 0.01µF to
FCB input pin removes the requirement that power must
0.1µF.
be drawn from the inductor primary in order to extract
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LTC3728L/LTC3728LX
U U W U
power from the auxiliary windings. With the loop in loop is reduced depending upon the maximum load step
continuous mode, the auxiliary outputs may nominally be specifications. Voltage positioning can easily be added to
loaded without regard to the primary output load. either or both controllers by loading the ITH pin with a
resistive divider having a Thevenin equivalent voltage
The secondary output voltage VSEC is normally set as
shown in Figure 6a by the turns ratio N of the transformer: source equal to the midpoint operating voltage range of
the error amplifier, or 1.2V (see Figure 8).
VSEC ≅ (N + 1) VOUT
The resistive load reduces the DC loop gain while main-
However, if the controller goes into Burst Mode operation taining the linear control range of the error amplifier. The
and halts switching due to a light primary load current, maximum output voltage deviation can theoretically be
then VSEC will droop. An external resistive divider from reduced to half or alternatively the amount of output
VSEC to the FCB pin sets a minimum voltage VSEC(MIN): capacitance can be reduced for a particular application. A
complete explanation is included in Design Solutions 10.
 R6 (See www.linear-tech.com)
VSEC(MIN) ≈ 0.8V 1 + 
 R5
INTVCC
where R5 and R6 are shown in Figure 2.
RT2
If VSEC drops below this level, the FCB voltage forces ITH
LTC3728L/
temporary continuous switching operation until VSEC is RT1 RC LTC3728LX
again above its minimum. CC
In order to prevent erratic operation if no external connec- 3728 F08
tions are made to the FCB pin, the FCB pin has a 0.18µA Figure 8. Active Voltage Positioning
internal current source pulling the pin high. Include this Applied to the LTC3728L/LTC3728LX
current when choosing resistor values R5 and R6.
Efficiency Considerations
The following table summarizes the possible states avail-
able on the FCB pin: The percent efficiency of a switching regulator is equal to
Table 1 the output power divided by the input power times 100%.
FCB Pin Condition
It is often useful to analyze individual losses to determine
0V to 0.75V Forced Continuous Both Controllers
what is limiting the efficiency and which change would
(Current Reversal Allowed— produce the most improvement. Percent efficiency can be
Burst Inhibited) expressed as:
0.85V < VFCB < 4.3V Minimum Peak Current Induces
Burst Mode Operation
%Efficiency = 100% – (L1 + L2 + L3 + ...)
No Current Reversal Allowed where L1, L2, etc. are the individual losses as a percentage
Feedback Resistors Regulating a Secondary Winding of input power.
>4.8V Burst Mode Operation Disabled
Constant Frequency Mode Enabled Although all dissipative elements in the circuit produce
No Current Reversal Allowed losses, four main sources usually account for most of the
No Minimum Peak Current losses in LTC3728L/LTC3728LX circuits: 1) IC VIN current
(including loading on the 3.3V internal regulator), 2)
Voltage Positioning INTVCC regulator current, 3) I2R losses, 4) Topside MOSFET
transition losses.
Voltage positioning can be used to minimize peak-to-peak
output voltage excursions under worst-case transient 1. The VIN current has two components: the first is the DC
loading conditions. The open-loop DC gain of the control supply current given in the Electrical Characteristics table,
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22
LTC3728L/LTC3728LX
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which excludes MOSFET driver and control currents; the 4. Transition losses apply only to the topside MOSFET(s),
second is the current drawn from the 3.3V linear regulator and become significant only when operating at high input
output. VIN current typically results in a small (<0.1%) loss. voltages (typically 15V or greater). Transition losses can
2. INTVCC current is the sum of the MOSFET driver and be estimated from:
control currents. The MOSFET driver current results from I 
( ) ( )
2
switching the gate capacitance of the power MOSFETs. Transition Loss = VIN •  MAX  RDR •
Each time a MOSFET gate is switched from low to high to  2 
 1 
( )( )
low again, a packet of charge dQ moves from INTVCC to 1
ground. The resulting dQ/dt is a current out of INTVCC that CMILLER f  + 
 5V – VTH VTH 
is typically much larger than the control circuit current. In
continuous mode, IGATECHG =f(QT+QB), where QT and QB Other “hidden” losses such as copper trace and internal
are the gate charges of the topside and bottom side battery resistances can account for an additional 5% to 10%
MOSFETs. efficiency degradation in portable systems. It is very impor-
Supplying INTVCC power through the EXTVCC switch input tant to include these “system” level losses during the de-
from an output-derived source will scale the VIN current sign phase. The internal battery and fuse resistance losses
required for the driver and control circuits by a factor of can be minimized by making sure that CIN has adequate
(Duty Cycle)/(Efficiency). For example, in a 20V to 5V charge storage and very low ESR at the switching frequency.
application, 10mA of INTVCC current results in approxi- A 25W supply will typically require␣ a minimum of 20µF to
mately 2.5mA of VIN current. This reduces the mid-current 40µF of capacitance having a␣ maximum of 20mΩ to 50mΩ
loss from 10% or more (if the driver was powered directly of ESR. The LTC3728L 2-phase architecture typically halves
from VIN) to only a few percent. this input capacitance requirement over competing solu-
tions. Other losses including Schottky conduction losses
3. I2R losses are predicted from the DC resistances of the during dead-time and inductor core losses generally ac-
fuse (if used), MOSFET, inductor, current sense resistor, count for less than 2% total additional loss.
and input and output capacitor ESR. In continuous mode
the average output current flows through L and RSENSE, Checking Transient Response
but is “chopped” between the topside MOSFET and the
The regulator loop response can be checked by looking at
synchronous MOSFET. If the two MOSFETs have approxi-
the load current transient response. Switching regulators
mately the same RDS(ON), then the resistance of one
take several cycles to respond to a step in DC (resistive)
MOSFET can simply be summed with the resistances of L,
load current. When a load step occurs, VOUT shifts by an
RSENSE and ESR to obtain I2R losses. For example, if each
amount equal to ∆ILOAD (ESR), where ESR is the effective
RDS(ON) = 30mΩ, RL = 50mΩ, RSENSE = 10mΩ and RESR
series resistance of COUT. ∆ILOAD also begins to charge or
= 40mΩ (sum of both input and output capacitance
discharge COUT generating the feedback error signal that
losses), then the total resistance is 130mΩ. This results in
forces the regulator to adapt to the current change and
losses ranging from 3% to 13% as the output current
return VOUT to its steady-state value. During this recovery
increases from 1A to 5A for a 5V output, or a 4% to 20%
time VOUT can be monitored for excessive overshoot or
loss for a 3.3V output. Efficiency varies as the inverse
ringing, which would indicate a stability problem. OPTI-
square of VOUT for the same external components and
LOOP compensation allows the transient response to be
output power level. The combined effects of increasingly
optimized over a wide range of output capacitance and
lower output voltages and higher currents required by
ESR values. The availability of the ITH pin not only allows
high performance digital systems is not doubling but
optimization of control loop behavior but also provides a
quadrupling the importance of loss terms in the switching
DC coupled and AC filtered closed loop response test
regulator system!
point. The DC step, rise time and settling at this test point
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23
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truly reflects the closed loop response. Assuming a pre- should be controlled so that the load rise time is limited to
dominantly second order system, phase margin and/or approximately 25 • CLOAD. Thus a 10µF capacitor would
damping factor can be estimated using the percentage of require a 250µs rise time, limiting the charging current to
overshoot seen at this pin. The bandwidth can also be about 200mA.
estimated by examining the rise time at the pin. The ITH
external components shown in the Figure 1 circuit will Automotive Considerations: Plugging into the
provide an adequate starting point for most applications. Cigarette Lighter
The ITH series RC-CC filter sets the dominant pole-zero As battery-powered devices go mobile, there is a natural
loop compensation. The values can be modified slightly interest in plugging into the cigarette lighter in order to
(from 0.5 to 2 times their suggested values) to optimize conserve or even recharge battery packs during operation.
transient response once the final PC layout is done and the But before you connect, be advised: you are plugging into
particular output capacitor type and value have been the supply from hell. The main power line in an automobile
determined. The output capacitors need to be selected is the source of a number of nasty potential transients,
because the various types and values determine the loop including load-dump, reverse-battery, and double-bat-
gain and phase. An output current pulse of 20% to 80% of tery.
full-load current having a rise time of 1µs to 10µs will Load-dump is the result of a loose battery cable. When the
produce output voltage and ITH pin waveforms that will cable breaks connection, the field collapse in the alternator
give a sense of the overall loop stability without breaking can cause a positive spike as high as 60V which takes
the feedback loop. Placing a power MOSFET directly several hundred milliseconds to decay. Reverse-battery is
across the output capacitor and driving the gate with an just what it says, while double-battery is a consequence of
appropriate signal generator is a practical way to produce tow-truck operators finding that a 24V jump start cranks
a realistic load step condition. The initial output voltage cold engines faster than 12V.
step resulting from the step change in output current may
not be within the bandwidth of the feedback loop, so this The network shown in Figure 9 is the most straightforward
signal cannot be used to determine phase margin. This is approach to protect a DC/DC converter from the ravages
why it is better to look at the ITH pin signal which is in the of an automotive power line. The series diode prevents
feedback loop and is the filtered and compensated control current from flowing during reverse-battery, while the
loop response. The gain of the loop will be increased by transient suppressor clamps the input voltage during
increasing RC and the bandwidth of the loop will be load-dump. Note that the transient suppressor should not
increased by decreasing CC. If RC is increased by the same conduct during double-battery operation, but must still
factor that CC is decreased, the zero frequency will be kept clamp the input voltage below breakdown of the converter.
the same, thereby keeping the phase shift the same in the Although the LTC3728L/LTC3728LX have a maximum
most critical frequency range of the feedback loop. The input voltage of 30V, most applications will also be limited
output voltage settling behavior is related to the stability of to 30V by the MOSFET BVDSS.
the closed-loop system and will demonstrate the actual
overall supply performance. 50A IPK RATING
VIN
A second, more severe transient is caused by switching in 12V
LTC3728L/
loads with large (>1µF) supply bypass capacitors. The LTC3728LX
discharged bypass capacitors are effectively put in parallel TRANSIENT VOLTAGE
SUPPRESSOR
with COUT, causing a rapid drop in VOUT. No regulator can GENERAL INSTRUMENT
1.5KA24A
alter its delivery of current quickly enough to prevent this
sudden step change in output voltage if the load switch 3728 F09
resistance is low and it is driven quickly. If the ratio of

CLOAD to COUT is greater than1:50, the switch rise time Figure 9. Automotive Application Protection
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Design Example Choosing 1% resistors: R1 = 25.5k and R2 = 32.4k yields
As a design example for one channel, assume VIN = an output voltage of 1.816V.
12V(nominal), VIN = 22V(max), VOUT = 1.8V, IMAX = 5A, The power dissipation on the top side MOSFET can be
and f = 300kHz. easily estimated. Choosing a Fairchild FDS6982S dual
The inductance value is chosen first based on a 30% ripple MOSFET results in: RDS(ON) = 0.035Ω/0.022Ω, CMILLER =
current assumption. The highest value of ripple current 215pF. At maximum input voltage with T(estimated) =
occurs at the maximum input voltage. Tie the PLLFLTR pin 50°C:
to a resistive divider from the INTVCC pin, generating 0.7V
( ) [1+ (0.005)(50°C – 25°C)] •
1.8V
for 300kHz operation. The minimum inductance for 30% 2
PMAIN = 5
ripple current is: 22V
2 
∆IL =
VOUT  VOUT 
 1– 
(0.035Ω) + (22V)  52A  (4Ω)(215pF) •
( f)(L)  VIN 
 1 1 
A 4.7µH inductor will produce 23% ripple current and a 
 5 – 2. 3
+
2. 3
(
)
 300kHz = 332mW
3.3µH will result in 33%. The peak inductor current will be
the maximum DC value plus one half the ripple current, or A short-circuit to ground will result in a folded back current
5.84A, for the 3.3µH value. Increasing the ripple current of:
will also help ensure that the minimum on-time of 100ns
is not violated. The minimum on-time occurs at maximum 25mV 1  120ns(22V)
VIN: ISC = –   = 2.1A
0.01Ω 2  3.3µH 
VOUT 1.8V
tON(MIN) = = = 273ns with a typical value of RDS(ON) and δ = (0.005/°C)(20) = 0.1.
VIN(MAX)f 22V(300kHz) The resulting power dissipated in the bottom MOSFET is:
22V – 1.8 V
The RSENSE resistor value can be calculated by using the
maximum current sense voltage specification with some
PSYNC =
22V
( 2.1A ) (1.125)(0.022Ω)
2
accommodation for tolerances: = 100mW

which is less than under full-load conditions.
60mV
RSENSE ≤ ≈ 0.01Ω
5.84A CIN is chosen for an RMS current rating of at least 3A at
temperature assuming only this channel is on. COUT is
Since the output voltage is below 2.4V the output resistive chosen with an ESR of 0.02Ω for low output ripple. The
divider will need to be sized to not only set the output output ripple in continuous mode will be highest at the
voltage but also to absorb the SENSE pin’s specified input maximum input voltage. The output voltage ripple due to
current. ESR is approximately:
VORIPPLE = RESR (∆IL) = 0.02Ω(1.67A) = 33mVP–P
 0.8V 
R1(MAX) = 24k  
 2.4V – VOUT 
 0.8V 
= 24k   = 32k
 2.4V – 1.8V 
3728lxfa
25
LTC3728L/LTC3728LX
U U W U
PC Board Layout Checklist 2. Are the signal and power grounds kept separate? The
When laying out the printed circuit board, the following combined IC signal ground pin and the ground return of
checklist should be used to ensure proper operation of the CINTVCC must return to the combined COUT (–) terminals.
IC. These items are also illustrated graphically in the The path formed by the top N-channel MOSFET, Schottky
layout diagram of Figure 10. The Figure 11 illustrates the diode and the CIN capacitor should have short leads and
current waveforms present in the various branches of the PC trace lengths. The output capacitor (–) terminals
2-phase synchronous regulators operating in the continu- should be connected as close as possible to the (–)
ous mode. Check the following in your layout: terminals of the input capacitor by placing the capacitors
next to each other and away from the Schottky loop
1. Are the top N-channel MOSFETs M1 and M3 located described above.
within 1cm of each other with a common drain connection
at CIN? Do not attempt to split the input decoupling for the 3. Do the LTC3728L/LTC3728LX VOSENSE pins’ resistive
two channels as it can cause a large resonant loop. dividers connect to the (+) terminals of COUT? The resistive
divider must be connected between the (+) terminal of
RPU
VPULL-UP
(<7V)
RUN/SS1 PGOOD PGOOD
L1 RSENSE
SENSE1 + TG1 VOUT1
R2 SENSE1 – SW1
R1 CB1
M1 M2
VOSENSE1 BOOST1 D1
PLLFLTR VIN
fIN
COUT1
PLLIN BG1 1µF
RIN
+
CERAMIC
INTVCC FCB EXTVCC
LTC3728L/LTC3728LX CVIN GND
+
ITH1 INTVCC CIN

+
+
VIN
CINTVCC
SGND PGND COUT2
1µF
CERAMIC
3.3V 3.3VOUT BG2
M3 M4
ITH2 BOOST2 D2
CB2
VOSENSE2 SW2
R3 R4 RSENSE
SENSE2 – TG2 VOUT2
L2
SENSE2 + RUN/SS2
3728 F10
Figure 10. LTC3728L/LTC3728LX Recommended Printed Circuit Layout Diagram
3728lxfa
26
LTC3728L/LTC3728LX
U U W U
SW1 L1 RSENSE1 VOUT1
+
D1 COUT1 RL1
CERAMIC
VIN
RIN +
CIN
SW2 L2 RSENSE2 VOUT2
+
BOLD LINES INDICATE D2 COUT2 RL2
HIGH SWITCHING CERAMIC
CURRENT. KEEP LINES
TO A MINIMUM LENGTH.
3728 F11
Figure 11. Branch Current Waveforms
COUT and signal ground. The R2 and R4 connections An additional 1µF ceramic capacitor placed immediately
should not be along the high current input feeds from the next to the INTVCC and PGND pins can help improve noise
input capacitor(s). performance substantially.
4. Are the SENSE – and SENSE + leads routed together 6. Keep the switching nodes (SW1, SW2), top gate nodes
with minimum PC trace spacing? The filter capacitor (TG1, TG2), and boost nodes (BOOST1, BOOST2) away
between SENSE + and SENSE – should be as close as from sensitive small-signal nodes, especially from the
possible to the IC. Ensure accurate current sensing with opposites channel’s voltage and current sensing feedback
Kelvin connections at the SENSE resistor. pins. All of these nodes have very large and fast moving
signals and therefore should be kept on the “output side”
5. Is the INTVCC decoupling capacitor connected close to
of the LTC3728L/LTC3728LX and occupy minimum PC
the IC, between the INTVCC and the power ground pins?
trace area.
This capacitor carries the MOSFET drivers current peaks.
3728lxfa
27
LTC3728L/LTC3728LX
U U W U
7. Use a modified “star ground” technique: a low imped- Short-circuit testing can be performed to verify proper
ance, large copper area central grounding point on the overcurrent latchoff, or 5µA can be provided to the RUN/
same side of the PC board as the input and output SS pin(s) by resistors from VIN to prevent the short-circuit
capacitors with tie-ins for the bottom of the INTVCC latchoff from occurring.
decoupling capacitor, the bottom of the voltage feedback Reduce VIN from its nominal level to verify operation of the
resistive divider and the SGND pin of the IC. regulator in dropout. Check the operation of the under-
voltage lockout circuit by further lowering VIN while moni-
PC Board Layout Debugging
toring the outputs to verify operation.
Start with one controller on at a time. It is helpful to use a
Investigate whether any problems exist only at higher
DC-50MHz current probe to monitor the current in the
output currents or only at higher input voltages. If prob-
inductor while testing the circuit. Monitor the output
lems coincide with high input voltages and low output
switching node (SW pin) to synchronize the oscilloscope
currents, look for capacitive coupling between the BOOST,
to the internal oscillator and probe the actual output
SW, TG, and possibly BG connections and the sensitive
voltage as well. Check for proper performance over the
voltage and current pins. The capacitor placed across the
operating voltage and current range expected in the appli-
current sensing pins needs to be placed immediately
cation. The frequency of operation should be maintained
adjacent to the pins of the IC. This capacitor helps to
over the input voltage range down to dropout and until the
minimize the effects of differential noise injection due to
output load drops below the low current operation thresh-
high frequency capacitive coupling. If problems are en-
old—typically 10% to 20% of the maximum designed
countered with high current output loading at lower input
current level in Burst Mode operation.
voltages, look for inductive coupling between CIN, Schottky
The duty cycle percentage should be maintained from and the top MOSFET components to the sensitive current
cycle to cycle in a well-designed, low noise PCB imple- and voltage sensing traces. In addition, investigate com-
mentation. Variation in the duty cycle at a subharmonic mon ground path voltage pickup between these compo-
rate can suggest noise pickup at the current or voltage nents and the SGND pin of the IC.
sensing inputs or inadequate loop compensation. Over-
An embarrassing problem, which can be missed in an
compensation of the loop can be used to tame a poor PC
otherwise properly working switching regulator, results
layout if regulator bandwidth optimization is not required.
when the current sensing leads are hooked up backwards.
Only after each controller is checked for its individual
The output voltage under this improper hookup will still be
performance should both controllers be turned on at the
maintained but the advantages of current mode control
same time. A particularly difficult region of operation is
will not be realized. Compensation of the voltage loop will
when one controller channel is nearing its current com-
be much more sensitive to component selection. This
parator trip point when the other channel is turning on its
behavior can be investigated by temporarily shorting out
top MOSFET. This occurs around 50% duty cycle on either
the current sensing resistor—don’t worry, the regulator
channel due to the phasing of the internal clocks and may
will still maintain control of the output voltage.
cause minor duty cycle jitter.
3728lxfa
28
LTC3728L/LTC3728LX
U
TYPICAL APPLICATIO S
59k 1M
100k VPULL-UP MBRS1100T3 +

(<7V) T1, 1:1.8 33µF
10µH 25V
RUN/SS1 PGOOD PGOOD
0.1µF 0.015Ω VOUT1
SENSE1 + TG1 5V
M1 3A; 4A PEAK
180pF 1000pF
8
105k, 1% SENSE1 – SW1
5
20k
0.1µF Q1 Q2 LT1121 ON/OFF
1%
VOSENSE1 BOOST1 D1
3 2 1
220k VOUT3
PLLFLTR VIN 12V
120mA
BG1 150µF, 6.3V
33pF
PLLIN
PANASONIC SP
+ 1µF
10Ω 22µF 100k
+
CMDSH-3TR 50V 25V
FCB EXTVCC
LTC3728L/LTC3728LX 0.1µF GND
+
ITH1 INTVCC +
15k 1µF
1000pF 10V 4.7µF 180µF, 4V
SGND PGND PANASONIC SP VIN
33pF CMDSH-3TR M2 7V TO
28V
3.3V 3.3VOUT BG2
Q3 Q4
ITH2 BOOST2 D2
15k 0.1µF
1000pF
VOSENSE2 SW2
20k
1% VOUT2
SENSE2 – TG2 3.3V
63.4k 1000pF 0.01Ω 5A; 6A PEAK
L1
1%
180pF SENSE2 + RUN/SS2 6.3µH
0.1µF
3728 F12
VIN: 7V TO 28V
VOUT: 5V, 3A/3.3V, 6A/12V, 150mA
SWITCHING FREQUENCY = 250kHz
MI, M2: FDS6982S OR VISHAY Si4810DY
L1: SUMIDA CEP123-6R3MC
T1: 10µH 1:1.8 — DALE LPE6562-A262 GAPPED E-CORE OR BH ELECTRONICS #501-0657 GAPPED TOROID
Figure 12. LTC3728L/LTC3728LX High Efficiency Low Noise 5V/3A, 3.3V/5A, 12V/120mA Regulator
3728lxfa
29
LTC3728L/LTC3728LX
U
TYPICAL APPLICATIO S
VPULL-UP
(<7V)
RUN/SS1 PGOOD PGOOD L1
4.3µH
0.1µF 0.008Ω
VOUT1
SENSE1 + TG1
5V/4A
180pF 105k 1000pF
20k 1% SENSE1 – SW1
1% 0.1µF
Q1 Q2
VOSENSE1 BOOST1
PIN 4
M1
0.01µF PLLFLTR VIN 1µF 50V
10k 1000pF
fSYNC PLLIN BG1
100pF
+
10Ω 22µF
CMDSH-3TR 50V
FCB EXTVCC
0.1µF 150µF, 6.3V
LTC3728L/LTC3728LX GND
ITH1 INTVCC
+
+
8.06k 1µF 1µF 50V
1500pF 4.7µF, 10V
SGND PGND 180µF, 4V
100pF VIN
CMDSH-3TR
7V TO
3.3V 3.3VOUT BG2 28V
PIN 4
ITH2 BOOST2 Q3 Q4
4.75k 0.1µF
1000pF
VOSENSE2 SW2
20k M2
1% VOUT2
–
SENSE2 TG2 3.3V/5A
63.4k 1000pF 0.008Ω
L2
180pF 1%
SENSE2 + RUN/SS2 4.3µH
0.1µF 3728 F13
VIN: 7V TO 28V SWITCHING FREQUENCY = 250kHz TO 550kHz L1, L2: SUMIDA CDEP105-4R3MC-88
VOUT: 5V, 4A/3.3V, 5A M1, M2: FDS6982S OR VISHAY Si4810DY OUTPUT CAPACITORS: PANASONIC SP SERIES
Figure 13. LTC3728L/LTC3728LX 5V/4A, 3.3V/5A Regulator with External Frequency Synchronization
3728lxfa
30
LTC3728L/LTC3728LX
U
PACKAGE DESCRIPTIO (For purposes of clarity, drawings are not to scale)
GN Package
28-Lead Plastic SSOP (Narrow .150 Inch)
(Reference LTC DWG # 05-08-1641)
.386 – .393*
.045 ±.005 (9.804 – 9.982) .033
(0.838)
28 27 26 25 24 23 22 21 20 19 18 17 1615 REF
.254 MIN .150 – .165

.229 – .244 .150 – .157**
(5.817 – 6.198) (3.810 – 3.988)
.0165 ± .0015 .0250 TYP

RECOMMENDED SOLDER PAD LAYOUT 1 2 3 4 5 6 7 8 9 10 11 12 13 14
.015 ± .004
× 45° .053 – .069 .004 – .009
(0.38 ± 0.10)
(1.351 – 1.748) (0.102 – 0.249)
.0075 – .0098 0° – 8° TYP
(0.191 – 0.249)
.016 – .050 .008 – .012 .0250

(0.406 – 1.270) (0.203 – 0.305) (0.635)
NOTE: BSC
1. CONTROLLING DIMENSION: INCHES
INCHES
2. DIMENSIONS ARE IN
(MILLIMETERS)
GN28 (SSOP) 0502
3. DRAWING NOT TO SCALE
*DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
**DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
UH Package
32-Lead Plastic QFN (5mm × 5mm)
(Reference LTC DWG # 05-08-1693)
BOTTOM VIEW—EXPOSED PAD
0.57 ±0.05 0.75 ± 0.05 R = 0.115

5.00 ± 0.10 0.40 ± 0.10
0.00 – 0.05 TYP
(4 SIDES) 31 32
PIN 1
TOP MARK 1
5.35 ±0.05 2
4.20 ±0.05
3.45 ±0.05 3.45 ± 0.10
(4 SIDES) (4-SIDES)
(UH) QFN 0102
0.23 ± 0.05 PACKAGE 0.200 REF 0.23 ± 0.05

OUTLINE NOTE: 0.50 BSC
0.50 BSC
1. DRAWING PROPOSED TO BE A JEDEC PACKAGE OUTLINE
RECOMMENDED SOLDER PAD LAYOUT M0-220 VARIATION WHHD-(X) (TO BE APPROVED)
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
3728lxfa
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.

However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tation that the interconnection of its circuits as described herein will not infringe on existing patent rights. 31
LTC3728L/LTC3728LX
U
TYPICAL APPLICATIO
IIN
12VIN
CIN
I1 IIN*
0° BUCK: 2.5V/15A
OPEN PHASMD TG1
180° 2.5VO/30A I1
U1 TG2 BUCK: 2.5V/15A
LTC3729
90° I2 I2
CLKOUT
I3 I3
1.5VO/15A
90° BUCK: 1.5V/15A
TG1 I4
270° 1.8VO/15A
U2 TG2
BUCK: 1.8V/15A
LTC3728L/
*INPUT RIPPLE CURRENT CANCELLATION
90° LTC3728LX I4 INCREASES THE RIPPLE FREQUENCY AND
PLLIN REDUCES THE RMS INPUT RIPPLE CURRENT
3728 F14 THUS, SAVING INPUT CAPACITORS
Figure 14. Multioutput PolyPhase Application
RELATED PARTS
PART NUMBER DESCRIPTION COMMENTS
LTC1628/LTC1628-PG/ 2-Phase, Dual Output Synchronous Step-Down Reduces CIN and COUT, Power Good Output Signal, Synchronizable,
LTC1628-SYNC DC/DC Controller 3.5V ≤ VIN ≤ 36V, IOUT up to 20A, 0.8V ≤ VOUT ≤ 5V
LTC1629/ 20A to 200A PolyPhaseTM Synchronous Controllers Expandable from 2-Phase to 12-Phase, Uses All
LTC1629-PG Surface Mount Components, No Heat Sink, VIN up to 36V
LTC1702A No RSENSE 2-Phase Dual Synchronous Step-Down 550kHz, No Sense Resistor
Controller
LTC1708-PG 2-Phase, Dual Synchronous Controller with Mobile VID 3.5V ≤ VIN ≤ 36V, VID Sets VOUT1, PGOOD
LT1709/ High Efficiency, 2-Phase Synchronous Step-Down 1.3V ≤ VOUT ≤ 3.5V, Current Mode Ensures
LT1709-8 Switching Regulators with 5-Bit VID Accurate Current Sharing, 3.5V ≤ VIN ≤ 36V
LTC1735 High Efficiency Synchronous Step-Down Output Fault Protection, 16-Pin SSOP
Switching Regulator
LTC1736 High Efficiency Synchronous Controller with 5-Bit Mobile Output Fault Protection, 24-Pin SSOP,
VID Control 3.5V ≤ VIN ≤ 36V
LTC1778/LTC1778-1 No RSENSE Current Mode Synchronous Step-Down Up to 97% Efficiency, 4V ≤ VIN ≤ 36V, 0.8V ≤ VOUT ≤ (0.9)(VIN),
Controllers IOUT up to 20A
LTC1929/ 2-Phase Synchronous Controllers Up to 42A, Uses All Surface Mount Components,
LTC1929-PG No Heat Sinks, 3.5V ≤ VIN ≤ 36V
LTC3708 Dual, 2-Phase, DC/DC Controller with Output Tracking Current Mode, No RSENSE, Up/Down Tracking, Synchronizable
LTC3711 No RSENSE Current Mode Synchronous Step-Down Up to 97% Efficiency, Ideal for Pentium® III Processors,
Controller with Digital 5-Bit Interface 0.925V ≤ VOUT ≤ 2V, 4V ≤ VIN ≤ 36V, IOUT up to 20A
LTC3728 Dual, 550kHz, 2-Phase Synchronous Step-Down Dual 180° Phased Controllers, VIN 3.5V to 35V, 99% Duty Cycle,
Controller 5x5QFN, SSOP-28
LTC3729 20A to 200A, 550kHz PolyPhase Synchronous Controller Expandable from 2-Phase to 12-Phase, Uses all Surface Mount
Components, VIN up to 36V
LTC3731 3- to 12-Phase Step-Down Synchronous Controller 60A to 240A Output Current, 0.6V ≤ VOUT ≤ 6V, 4.5V ≤ VIN ≤ 32V
No RSENSE and PolyPhase are trademarks of Linear Technology Corporation. Pentium is a registered trademark of Intel Corporation.
3728lxfa
LT/TP 0104 1K REV A • PRINTED IN USA
32 Linear Technology Corporation

1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 ● FAX: (408) 434-0507 ●
www.linear.com  LINEAR TECHNOLOGY CORPORATION 2002

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LTC3728L/LTC3728LX

Dual, 550kHz, 2-Phase

M1, M2: FDS6982S

Figure 1. High Efficiency Dual 5V/3.3V Step-Down Converter 3728lxfa

INTVCC AND EXTVCC SWITCH VOLTAGE (V)

EXTVCC VOLTAGE DROP (mV)

Maximum Current Sense Threshold

Maximum Current Sense Dropout Voltage vs Output Current

RUN/SS CURRENT (µA)

VOUT = 5V VOUT = 5V VOUT = 5V

VOUT1 = 5V, VOUT2 = 3.3V VOUT = 5V VOUT = 5V

Undervoltage Lockout Shutdown Latch Thresholds

3.3VOUT 0.8V 2.4V VOSENSE

SGND (UH PACKAGE PAD) INTERNAL

IIN(MEAS) = 2.53ARMS DC236 F03a IIN(MEAS) = 1.55ARMS DC236 F03b

operation for 3.3V and 5V regulators over a wide input

but in fact extend over a wide region. A good rule of thumb

PLLFLTR PIN VOLTAGE (V)

RSENSE Selection For Output Current 0

BAT 85 BAT85 0.22µF BAT85

for VOUT < 2.4V (a) (b) 3728 F07

again above its minimum. CC

In order to prevent erratic operation if no external connec- 3728 F08

resistance is low and it is driven quickly. If the ratio of

accommodation for tolerances: = 100mW

ITH1 INTVCC CIN

Figure 10. LTC3728L/LTC3728LX Recommended Printed Circuit Layout Diagram

SW1 L1 RSENSE1 VOUT1

SW2 L2 RSENSE2 VOUT2

Figure 11. Branch Current Waveforms

100k VPULL-UP MBRS1100T3 +

0.1µF 3728 F13

.254 MIN .150 – .165

.0165 ± .0015 .0250 TYP

.016 – .050 .008 – .012 .0250

0.57 ±0.05 0.75 ± 0.05 R = 0.115

(UH) QFN 0102

0.23 ± 0.05 PACKAGE 0.200 REF 0.23 ± 0.05

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.

Figure 14. Multioutput PolyPhase Application

LT/TP 0104 1K REV A • PRINTED IN USA

32 Linear Technology Corporation

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