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VSRD-IJEECE, Vol. 2 (6), 2012, 330-336

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Modelling of Operational Amplifier by

Using CMOS Technology
1
Raghava Katreepalli* and 2Mukku Venkateswarlu

ABSTRACT
A CMOS single output two stage operational amplifier is presented here, which operates at 3 V power supply at
0.18 micron (i.e., 180 nm) technology. It is designed to meet a set of provided specifications. The unique
behavior of the MOS transistors in sub- threshold region not only allows a designer to work at low input bias
current but also at low voltage. This op-amp has very low standby power consumption with a high driving
capability and operates at low voltage so that the circuit operates at low power. The op-amp provides a gain of
20.4dB and a -3db bandwidth of 202 kHz and a unity gain bandwidth of 2.15MHz for a load of 5 pF capacitor.
This op-amp has a PSRR (+) of 85.0 dB and a PSRR (-) of 60.0 dB. It has a CMRR (dc) of -64.4 dB, and an
output slew rate of 12.465 v/µs. The power consumption for the op-amp is 1.18mW. The presented op-amp has
an Input Common Mode Range(ICMR) of -1V to 2.4V. The op-amp is designed in the 180 nm technology using
the umc 180 nm technology library. The layout for the above op-amp had been designed and the post layout
simulations are compared with the schematic simulations.

The proposed op-amp is a simple two stage single ended op-amp. The input stage of the op-amp is a differential
amplifier with an NMOS pair. The second stage of the op-amp is a simple PMOS common source amplifier.
The second stage is used to increase the voltage swing at the output. The op-amp uses a -3v Vdd and a -3v Vss
and consumes a power of around 0.6mW (as per post layout simulations).

Keywords : CMOS, Operational Amplifier, Input Common Mode Range, NMOS, PMOS.

1. INTRODUCTION
The operational amplifier is undoubtedly one of the most useful devices in analog electronic circuitry. Op-amps
are built with vastly different levels of complexity to be used to realize functions ranging from a simple dc bias
generation to high speed amplifications or filtering. With only a handful of external components, it can perform
____________________________
1,2
Assistant Professor, Department of Electronics & Communication Engineering, Vignan Institute of Management &
Technology for Women, Hyderabad, Andhra Pradesh, INDIA. *Correspondence : [email protected]
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a wide variety of analog signal processing tasks. Op-amps are among the most widely used electronic devices
today[8,10,14,15], being used in a vast array of consumer, industrial, and scientific devices. Operational
Amplifiers, more commonly known as Op-amps, are among the most widely used building blocks in Analog
Electronic Circuits. Op-amps are used equally in both analog and digital circuits. [1,2,9,13]

Op-amps are linear devices which has nearly all the properties required for not only ideal DC amplification but
is used extensively for signal conditioning, filtering and for performing mathematical operations such as
addition, subtraction, integration, differentiation etc . Generally an Operational Amplifier is a 3-terminal device.
It consists mainly of an Inverting input denoted by a negative sign, ("-") and the other a Non-inverting input
denoted by a positive sign ("+") in the symbol for op-amp. Both these inputs are very high impedance. The
output signal of an Operational Amplifier is the magnified difference between the two input signals or in other
words the amplified differential input. Generally the input stage of an Operational Amplifier is often a
differential amplifier.[13,14,15]

Our aim is to create the physical design and fabricate a low power Op-amp .An ideal op-amp having a single-
ended out is characterized by a differential input, infinite voltage gain, infinite input resistance and zero output
resistance. In a real op-amp however these characters cannot be generated but their performance has to be
sufficiently good for the circuit behavior to closely approximate the characters of an ideal op-amp in most
applications. With the introduction of each new generation of CMOS technologies design of op-amps continues
to pose further challenges as the supply voltages and transistor channel lengths scale down.[4-6,15]

2. SYSTEM OVERVIEW
The Op-amps used in many useful applications, rather a surprisingly large number of applications, the actual
amplifier performance is closely approximated by an idealized amplifier model. Indeed quite frequently circuits
are designed explicitly to insure acceptability of this approximation. And in other cases where the idealization is
not a sufficiently accurate approximation nevertheless it often provides a starting point for an iterative process
low power operational amplifier. Consider the 741 amplifier, an older but proven industry-standard device,
which has a voltage gain exceeding 105 in normal operation. To cause an output voltage change between
representative saturation voltage limits of ±15 volts, i.e., a full thirty-volt output change, the input voltage
change involved is less than 0.3millivolt. Such a small voltage difference often may be neglected, i.e.,
approximated as zero, when compared to other circuit voltages with which it is associated in a KVL loop
equation. [1,4,7,12,15]

An amplifier with the general characteristics of very high voltage gain, very high input resistance, and very low
output resistance generally is referred to as an op-amp. Most analog applications use an Op-Amp that has some
amount of negative feedback. The Negative feedback is used to tell the Op-Amp how much to amplify a signal.
And since op-amps are so extensively used to implement a feedback system, the required precision of the closed
loop circuit determines the open loop gain of the system.[10,12,14]

A basic op-amp consists of 4 main blocks :

a. Current Mirror

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b. Differential Amplifier

c. Level shift, differential to single ended gain stage

d. Output buffer

2.1. Practical Structure Of OP-AMP

The practical structure of op-amp consists of 3 main blocks :

(a) The first block is input differential amplifier, which is designed so that it provides very high input
impedance, a large CMRR and PSRR, a low offset voltage, low noise and high gain. Its output should preferably
be single ended, so that the rest of the op-amp need not contain symmetrical differential stages. Since the
transistors in the input stage operate in their saturation regions there is an appreciable dc voltage difference
between input and output signals of the input stage.

Fig. 1 : Practical Op-Amp

(b) The second stage performs one or more of the following functions:

Level Shifting : This is needed to compensate for the dc voltage change occurring in the input stage, and thus to
assure the appropriate dc bias for the following stages.

Added Gain : The gain provided by the input stage is not sufficient and additional amplification is required.

Differential to Single Ended Conversion : In some circuits, the input stage has a differential output, and the
conversion to single ended signals is performed in a subsequent stage.

(c) The third block is the output buffer. It provides the low output impedance and larger output current needed to
drive the load of the op-amp. It normally does not contribute to the voltage gain. If the op-amp is an internal
component of a switched-capacitor filter, then the output load is a capacitor, and the buffer need not provide
very large current or very low output impedance. However if the op-amp is at the filter output, then it may have
to drive a large capacitor and/or resistive load. This requires large current drive capability and very low output
impedance which can only be attained by using large output devices with appreciable dc bias currents.

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Finally the full op-amp schematic designed using the previous designed current mirror and differential
amplifiers and the common source amplifier circuit is as shown in figure 2 below :

Fig. 2 : Proposed System

………

Fig. 3 : Full Schematic of Proposed System

3. RESULT AND SIMULATION

The designed op-amp was simulated to find the different characteristics of the designed op-amp. Further the
layout of the designed op-amp was created and the parasitic capacitance and resistance was extracted. The
extracted designs were then simulated with the parasitic values and compared with the schematic. Later in the
chapter we also compare the obtained parameters of the device through simulation to the specifications for the
device and with the post layout simulation results. The different results are presented here.

3.1. Offset Voltage

It is the voltage obtained at the output terminals, when the input terminals are connected to ground terminal, i.e.,
0 volts. Here the offset voltage calculated for the op-amp is -603mv.

Fig. 4 : Offset Voltage Simulation

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3.2. Slewrate
It is the maximum rate of change of output voltage. Here the slope of the curve. We calculated as 12.5 v/µs.

Fig. 5 : Simulated Slew Rate

3.3. Gain
It is defined as the ratio of the output to the input. Here the input voltage given as 1 volts sine wave. Hence the
gain is calculated as 10.4v/v

Fig. 6 : Simulated Gain

3.4. Bandwidth
It is the maximum allowable range of the frequencies. Here the bandwidth of this op-amp calculated as 2.16
MHz for unity gain and 202 kHz at -3dB.

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Fig. 7 : Simulated Bandwidth

4. CONCLUSION
The proposed design has been able to satisfy most of the specifications provided for the op-amp.

The proposed op-amp is a two stage single output op-amp. The input stage is a differential amplifier and a
common source stage forms the second stage of the op-amp. The layout of the design has been made and
simulated. The post layout simulations abide by the given specification. The entire design has been done in
UMC 180 nm technology.

The gain of the op-amp can be increased further by the use of cascade device in the input stage. The voltage
swing may be increased by using a double ended output.

The gain and phase plot of the op-amp has been plotted during post layout simulations and we obtain a phase
margin of about 93 degrees. So we can conclude that the op-amp is stable.

5. REFERENCES
[1] Schlogl, F.; Dietrich, H.; Zimmermann, H. “High-gain high- speed operational amplifier in digital 120nm
CMOS”, IEEE Conference 2004, Pages: 316 – 319.
[2] Sarbishaei, H.; Kahookar Toosi, T.; Zhian Tabasy, E.; Lotfi, R. “A high-gain high- speed low-power class
AB operational amplifier”, IEEE Conference 2005, Pages: 271- 274 Vol. 1
[3] Raikos, G.; Vlassis, S., “Low-voltage differential amplifier”, IEEE Conference 2009, Page(s): 136 – 139.
[4] Pletersek, A.; Strle, D.; Trontelj, J., “Low supply voltage, low noise fully differential programmable gain
amplifiers”, IEEE Conference 1995 , Page(s): 105 – 112.
[5] J.Mahattanakul and J.Chutichatuporn, “Design Procedure for Two-Stage Cmos Op-amp Flexible noise
power balancing scheme” IEEE trans. Circuits syst. I fundam. Theory App vol 52 no.8 pp 1508-1514 Aug
2005.
[6] J.Mahattanakul ,“Design Procedure for Two-Stage Cmos Opamp employing current buffer” IEEE trans.
Circuits syst. II Fundam. Theory App vol. 52 no.8 pp 1508-1514 Nov 2005.

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[7] Behzad Razavi, Design of CMOS Analog Integrated Ckts, Mc-Graw Hill College, 2001.
[8] S.S. Rajput and S.S. Jamuar, "Low voltage, low power high performance current mirror for portable
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[9] Loikkanen. M, Kostamovaara. J, “High current CMOS operational amplifier”, IEEE Conference 2005.
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[11] Schlogl, F.; Dietrich, H.; Zimmermann, H. “120nm CMOS operational amplifier with high gain down to
±0.3V supply”, IEEE Conference 2003, Pages: 121 – 124.
[12] Kaulberg, T. “A CMOS current-mode operational amplifier”, IEEE Journal 1993, Pages: 849 – 852.
[13] Schlogl, F.; Zimmermann, H. “Low-voltage operational amplifier in 0.12 µm digital CMOS technology”
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[14] Maryam Borhani, Farhad Razaghian, “Low Power Op-Amp Based on Weak Inversion with Miller-
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[15] Ming-Dou Ker; Jung-Sheng Chen, “Impact of MOSFET Gate-Oxide Reliability on CMOS Operational
Amplifier in a 130-nm Low-Voltage Process”, IEEE Journal 2008.

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