2017 IEEE 13th International Conference on Electronic Measurement & Instruments ICEMI’2017

Research on the influence of vias on signal transmission in multi-layer PCB

Gao Dong, Yang Biao, Duan Xidong, Li Yuan
The 41st Research Institute of CETC
Science and Technology on Electronic Test & Measurement Laboratory
Qingdao 266000, China
Email:[email protected]

AbstractüVias are widely used in printed circuit board (PCB) indicate the radius of via-hole, pad, and anti-pad
nowadays especially in multi-layer PCB design for connecting respectively [3].
signals from different layers and ground planes. Although vias
make interconnection easy, they also give rise to discontinuity
problem. As frequency increases, via can cause reflection
that seriously affects system performance and the integrity of
signal. In this paper, we use the full wave simulation software
HFSS to model and simulate a multi-layer PCB via. The impact
on signal integrity of the size of via (via radius, pad radius and
anti-pad radius) is analyzed. Then an optimization method is
proposed. The simulation results can be practical guidance
for multi-layer PCB design.
KeywordsüVia, PCB, Signal integrity, Ground-hole

I. INTRODUCTION Fig. 1 Via structure

Vias through the ground plane will produce
Currently, the high-speed propagation of the parasitic capacitance, expressed as follows:
H U7'  '   '  
signals and the miniaturization of the printed circuit
board size have become the key tendencies in PCB & (1)
industry, which need higher performance of PCB. Where ѓr is the dielectric constant, D1 is pad diameter,
Multi-layer PCB is widely used because of its unique D2 is anti-pad diameter, T is the thickness of the media.
technical advantages in the manufacturing of The parasitic capacitance of via can prolong the rise
electronic equipment. Vias are often used in time of high frequency signals, and reduce the speed
high-speed multi-layer design. Electrical connection of the circuit, which is particularly important in high
between different layers of PCB or between frequency signal transmission.
components and alignment is achieved through vias Via also has parasitic series inductance which will
[1-2]
. Along with the rapid growth of signal speed and reduce the effect of supply bypass capacitor filtering.
wiring density, many factors will affect the signal For the designers of digital circuit, the influence of
integrity, and via is one of the key factors affecting the parasitic series inductance is more serious than
quality of signal transmission. parasitic capacitance. Series inductance is mainly
In this paper, the via structure and parasitic determined by the the via depth h and the via diameter
parameters are given. Then a series of simulation is d, expressed as follows:
done through changing the via radius R1, pad radius R2 ª § K · º
and anti-pad radius R3 partly with the frequency / K «OQ¨¨ ¸¸  »
¬ ©G ¹ ¼ (2)
ranging from DC up to 10GHz. Lastly, an
optimization method is proposed, which can improve As a discontinuous structure, via will make
the signal integrity of via at the frequency up to transmission performance poorer for its parasitic
20GHz effectively. capacitance and inductance. Different sizes of via-hole,
pad and anti-pad will lead to impedance changes,
II. STRUCTRRE AND PARASITIC which will directly affect the signal integrity
transferred through via [4].
PARAMETERS OF VIA

Vias are used to connect different layers of PCB. III. MODELING AND SIMULATION OF
Fig.1 depicts a typical via structure. R1, R2 and R3 VIA

978-1-5090-5035-2/17/$31.00 ©2017 IEEE In this paper, we use full-wave simulation software


2017 IEEE 13th International Conference on Electronic Measurement & Instruments ICEMI’2017

HFSS to build the model of via, and simulate vias in Figure 3 shows the S21 and S11 simulation curves
multi-layer PCB, scanning frequency ranges from DC in the conduction that via radius R1 changes from
to 10GHz [5]. 0.2mm to 0.3 mm. The pad radius is 0.4 mm and
The model of via in HFSS shows in Fig.2. The anti-pad radius is 0.6 mm. From the simulation result
PCB has 8 layers, made of 4 core board of RO4350B we can see that S21 and S11 get worse along with R1
which ѓr = 3.66 and 3 prepreg board of RO4450B. increasing from 0.2mm to 0.3mm in the condition of
This via connects top layer and bottom layer. Layer 2, R2 and R3 unchanged. So when we design vias in PCB,
4 and 7 are ground and the remaining layers are used we should set the via-hole radius as small as possible
for signal transmission. In this way, each signal layer in accordance with the requirements of process
has a reference plane which can mask interference conditions.
from layers and external. The actual manufacturing Figure 4 shows the S21 and S11 simulation curves
process of via is drilling, so the section of via, pad and in the conduction that pad radius R2 changes from 0.3
anti-pad are circular. to 0.4 mm. The via radius is 0.2 mm and anti-pad
radius is 0.6 mm. From the simulation result we can
see, S21 and S11 get worse along with R2 increasing
from 0.3mm to 0.4mm in the condition of R1 and R3
unchanged. Similarly, when we design vias in PCB,
we should set the pad radius as small as possible in
accordance with the requirements of process
conditions.

Fig. 2 Model of via in HFSS

Fig. 4 S21 and S11 simulation curves along with the change
of R2
Figure 5 shows the S21 and S11 simulation curves
in the conduction that anti-pad radius R3 changes from
0.55 to 0.7 mm. The via radius is 0.2 mm and pad
radius is 0.4 mm. From the simulation result we can
see, S21 and S11 get better along with R3 increasing
from 0.55mm to 0.7mm in the condition of R1 and R2
Fig. 3 S21 and S11 simulation curves along with the change
of R1 unchanged. Contrary to via-hole radius and pad radius,


2017 IEEE 13th International Conference on Electronic Measurement & Instruments ICEMI’2017

we should set the anti-pad radius as large as possible, the frequency is larger than 10GHz.
but generally less than two times the pad radius R2.

Fig. 6 S21 and S11 simulation curves with the frequency up

to 20GHz

Fig. 5 S21 and S11 simulation curves along with the change
of R3
In summary, the insertion loss S21 and return loss
S11 of via is inversely proportional to the via radius
R1 and pad radius R2, and directly proportional to the
Fig. 7 Simulation result of electric field of via
anti-pad radius R3 to a certain extent. Because of that
via hole radius R1 is subject to the manufacturing In order to solve the problem, a measure is taken.
process of PCB, so R1 is impossible to minimize We place several ground holes around the via, as
without limitation. Therefore when we use vias in shown in Fig.8. With these ground holes, the electric
PCB design, we must make a reasonable design of via field of signal passing though the via is restricted
size. effectively. Thus, the signal integrity is improved.
Fig.9 shows the simulation result of electric field of
IV. OPTIMIZATION SCHEME via with ground holes.

With the development of manufacturing process of

multi-layer PCB, the frequency PCB can works at is
higher and higher. Then what will happen when a
20GHz signal passes through a via? Fig.6 shows the
result at the condition of R1=0.2mm, R2=0.6mm,
R3=0.8mm.
From Fig.6 we can see that when the frequency of
signal passing through a via is extended to 20GHz,
resonance occurs. And the signal quality gets worse
than the signal less than 10GHz. Fig.7 shows the
simulation result of electric field of the via. Due to the
lack of restraint, the electric field of via is divergent
when signal passing through the via. This is one of the
reasons that cause the signal integrity problem when Fig. 8 Model of via with ground holes around in HFSS


2017 IEEE 13th International Conference on Electronic Measurement & Instruments ICEMI’2017

V. CONCLUSION AND FUTURE WORK

The impact of via parasitic parameters on the

transmission quality and signal integrity should not be
ignored. The design of vias is an important factor in
high-speed PCB design. This paper contains the
theory and simulation of via which has some guiding
significance for multi-layer PCB design. From the
simulation results we can see that the electrical
properties of vias is inversely proportional to the via
radius R1 and pad radius R2, and directly proportional
to the anti-pad radius R3 to a certain extent. So when
we use vias in PCB design, we must make a
reasonable design of via size. In addition, the use of
Fig. 9 Simulation result of electric field of via with ground ground-holes optimization scheme can effectively
holes
improve signal integrity of via at the frequency up to
The simulation curves of via with ground holes is 20GHz.
shown in Fig.10. Compared with Fig.6, an obvious In this paper, we only toke a qualitative analysis of
improvement is shown. The resonance has via model and proposed an optimization scheme. In
disappeared, and the signal quality at the frequency future research we should make intensive research
larger than 10GHz has been greatly improved. continuously, such as parameter optimization, etc.

REFERENCES

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Fig. 10 S21 and S11 simulation curves of via with ground 2008: 21-24.
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