VPX3-152

Power Architecture QorIQ T2080 Single Board Computer

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Overview
Curtiss-Wright Defense Solutions’ VPX3-152 is the latest OpenVPX ™-
compliant 3U processor that combines the performance and the
advanced I/O capabilities of the NXP ® Power Architecture ® QorIQ ™
quad-core AltiVec ™-enabled T2080 processor with an extensive I/O
complement to provide a single board computer (SBC) processor.
Designed for space-constrained applications, the VPX3-152
represents the latest step in the evolution of commercial off-the-
shelf (COTS) modules for rugged, embedded applications, whether
Key Features commercial, aerospace, or military.
• NXP T2080 quad-core 64-bit CPU
up to 1.8 GHz with AltiVec The challenge of high-density computing is to pack the greatest
functionality into the smallest standard form factor, with the lowest
• Up to 16 GB DDR3 memory power possible while retaining maximum flexibility. In conjunction with
• x4 PCIe Gen2 XMC site its processing power, the VPX3-152 easily meets this challenge by
offering an impressive complement of I/O capability in order to satisfy
• Support for Linux® and Wind River® the most demanding application needs with a low power footprint.
VxWorks® 7 For applications that demand the highest levels of hardware and
software protection, the VPX3-152 provides information assurance
• NXP Secure Boot
with NXP Secure Boot technologies and capabilities.
Applications The VPX3-152’s integral high-speed backplane and XMC connectivity
• Commercial allow for multi-GBps data flows from board-to-board through the
backplane interface and from the backplane to XMC site. This
• Control computers
supports the acquisition, processing, and distribution of sensor
• Mission computer applications data such as video, radar, and sonar data. The VPX3-152’s rich I/O
complement includes two Gigabit Ethernet (GbE) ports, four serial
• ISR applications
channels, up to 4 bits of LVTTL discrete digital I/O (DIO) inputs and
• Controllers up to 4 bits of LVTTL outputs, Universal Serial Bus (USB) 2.0 ports,
and an XMC site with 64 bits of I/O mapped to the backplane.
The VPX3-152 is supported by a wealth of software, including
Curtiss-Wright developed U-Boot, Wind River VxWorks 7 and Linux.

INFO: CURTISSWRIGHTDS.COM
EMAIL: [email protected]
 VPX3-152

PABS Temp RTC Elapse

MVRAM
UART
IPMC

PLD
NOR FLASH

4/8

SPI I2C

LOCAL BUS GPIO SPI I2C

4-16 GB
DDR3 SerDes
SDRAM T2080

4-64 GB SATA
eMMC
UART USB SGMII EMIx

x4 PCIe x4 PCIe
Gen2 Gen2

GbE Pn5
PHY
VITA 42 PCIe Switch
24-lane/
XMC
24-port
Pn6

24s x4 x4
20d
(2) x4 PCIe
Gen2
Up to
(8) x1 PCIe
Gen2
P0

P1

P2
(2) (2) MDC/ (2) (2) 1000-KX Card_Fail# PCIE
(2) (2) XMC I/O I2C DIO
RS422/ 1000-BT Or
RS232 USB 1000-BX MDIO SATA
(2) 10GE-KR
DataPlane
RS232

Figure 1: VPX3-152 block diagram

Features
• NXP QorIQ T2080 up to 1.8 GHz • 256 MB of contiguous direct-mapped Flash memory
+ 4 x dual threaded e6500 processor cores + Hardware Flash write protection jumper
+ Each core has AltiVec vector processor • Permanent Alternate Boot Site (PABS) provides back-up
boot capability
+ Each core has 64 KB L1 cache
• 512 KB MRAM NVRAM
+ Shared 2 MB L2 cache
• PCIe fabric ports on the VPX P1 connector, mapped as per
+ 1 x DDR3 memory controllers with 512 KB L3 front side
VITA 65, that can be configured as:
cache ECC
+ Four x2 lane PCIe Gen2 ports, transparent mode
+ 2 x GbE controllers
+ Two x4 lane PCIe Gen2 ports, one non-transparent
+ 2 x DUART controller
capable
+ 2 x I2C channels
+ Eight x1 lane PCIe Gen2 ports, two non-transparent
+ 3 x PCI Express® (PCIe) interfaces capable (other configurations possible, consult factory)
+ Integrated DMA controllers • 1 x XMC (VITA 42.3) site on independent PCIe bus
• Single, high-speed 64-bit DDR3 SDRAM controller with ECC + x4 lane PCIe Gen2 interface
to correct single-bit errors and detect double-bit errors on
+ PN6 pinned out to backplane P2 following VITA 46.9
single memory controller
P2w1-X24s+X8d+X12d
• Up to 16 GB of DDR3 SDRAM with ECC
• Conduction-cooling of XMC site optimized with primary and
• Up to 64 GB of eMMC Flash (optional) secondary thermal interfaces

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 VPX3-152

• Two 1000BASE-T GbE interfaces on P1 and P2 connector

mapped Form Factor
• Two 1000BASE-KX also configurable as 10GBASE-KR on VPX Module Format
P1 connector as per VITA 65
The Versatile Performance Switching (VPX) module format,
• Up to two SATA 2.0 ports
governed by the VITA 46 and VITA 65 specifications and
• 2 x asynchronous EIA/TIA RS-232 serial ports the associated VITA 48 Ruggedized Enhanced Design
• 2 x asynchronous EIA/TIA RS-422 serial channels Implementation (REDI), was established to address the
fundamental requirement to provide open-architecture
+ Configurable as EIA/TIA RS-232
modules that incorporate high-speed serial interconnect
• Up to 4 x 5V-tolerant LVTTL DIO inputs, with interrupt technology that is becoming pervasive in high-performance
capability computing. The VPX standard was developed by the
• Up to 4 x 5V LVTTL DIO outputs leading providers of military COTS modules to address the
major issue of high-speed serial interconnect, as well as
• Up to two USB 2.0 ports
incorporating numerous improvements learned after years
• General purpose DMA controllers provided by the T2080 of integrating VME and CompactPCI® (cPCI) modules. The
• 2 x avionics-style watchdog timers with external watchdog VPX module format provides many benefits to integrators
event indicator provided by the Safety Monitor PLD of high-performance multi-processor systems for radar, ISR,
mission computers, and other applications. In short, the
• 2 x on-board temperature sensors with alarm interrupt plus
VPX standard provides:
a processor temperature sensor
• Elapsed Time Counter (ETC) to record the total power-on • 3U and 6U Eurocard form factors that preserve chassis
time across product’s life span mechanical designs
• Status LEDs • Support for various high-speed serial interfaces as the
primary dataplane fabric
• +5V operation
• Support for higher power modules and improved
• Curtiss-Wright’s U-Boot firmware providing a comprehensive
cooling
suite of system debug, exerciser, and update functions, plus
BIT and non-volatile memory sanitization function • Improved logistics with two-level maintenance and
keying
• Circuit card assembly is lead-free as per Class 3 standards
of IPC-A-610C, Acceptability of Electronic Assemblies
• Standard conformal coating is acrylic Processor
• Available in a range of ruggedization levels
NXP Power Architecture QorIQ
+ Air-cooled Level 0 and 100
The VPX3-152 supports NXP’s latest generation of QorIQ
+ Conduction-cooled Level 200 per VITA 46.0 highly integrated system on chip processors, the quad
+ Conduction-cooled Level 300 per VITA 48.2, Type 1 card core, 64-bit dual threaded T2080. The T2080 provides an
with top and bottom covers extensive amount of I/O capability and processing power
• Available software packages in a low power footprint, making it ideal for size, weight and
power (SWaP)-sensitive applications.
+ 64-bit VxWorks 7
+ 64-bit NXP Yocto-based SDK.18 Linux BSP The T2080 processor with four Power Architecture dual
threaded 64-bit e6500 cores up to 1.8 GHz, each core with:
+ VxWorks 653 3.0.1.1 BSP from Curtiss-Wright
+ DO-178C BSPs available from software partners (Green • 32 KBs L1 data cache with parity
Hills, Lynx Software and SYSGO) • 32 KBs L1 instruction cache with parity
• 2 MB shared L2 cache with ECC
• 512 KB shared L3 cache
• AltiVec Vector engine

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 VPX3-152

Table 1 below compares the key characteristics and performance gains of the T2080 to the VPX3-133 SBC based on the
QorIQ processor.

TABLE 1 VPX3-152 to VPX3-133 product comparison

FEATURE VPX3-152 VPX3-133
Processing nodes 1 1
Processor T2080 up to 1.8 GHz T2080 up to 1.8 GHz
Number of cores 4 x dual threaded e6500 cores with AltiVec 4 x dual threaded e6500 cores with AltiVec
1 x up to 16 GB 1 x up to 8 GB
Memory banks
(One memory controller, up to two ranks) (One memory controller)
Memory bandwidth Up to 1866 MT/s Up to 1600 MT/s
2 x EIA-232, 2 x EIA-422, USB, DIO, 4 x GbE, 2 x EIA-232, 2 x EIA-422, USB, DIO, 2 x GbE,
I/O
SATA (support for 10GBASE-KR) SATA
CPU data path
x4 lane PCIe Gen2 x8 lane PCIe Gen2
(to switch)
Two x4 lane ports (default) Two x4 lane ports (default)
Data plane
Other user-selectable configurations available Other user-selectable configurations available
IPMC Yes Yes
I/O ROUTING
24 x single-ended + 20 x differential pairs
XMC sites 24 x single-ended + 20 x differential pairs
(See Note 1)
Note 1: This is dependent on the variant. Contact factory for details.

Memory
Double Data Rate (DDR3) SDRAM For absolute security against inadvertent Flash programming
or corruption, a hardware jumper is provided to disable
The T2080 provides a single memory controller supporting
writing to Flash. The firmware provides Flash programming
DDR3 SDRAM, which the VPX3-152 uses to provide up to
functions with support for downloading Flash images over
16 GB DDR3 SDRAM. The DDR3 interface operates at a rate
Ethernet.
of 1866 MT/s for 4GB variants and 1600 MT/s for 8 and
16GB variants.
NAND Flash
To preserve data integrity, the VPX3-152 takes advantage of
For applications requiring more non-volatile memory storage
the processor’s memory controller’s ECC circuitry to correct
than can be supported by the NOR Flash memory, the VPX3-
single-bit errors and detect double-bit errors. The DDR is
152 provides up to 64 GB of eMMC NAND flash.
accessible from the processor, as well as the Ethernet and
PCIe interfaces.
Permanent Alternate Boot Site (PABS)
Flash Memory The VPX3-152 is equipped with a Permanent Alternate Boot
Site (PABS) SPI NOR Flash. PABS provides a backup boot
The VPX3-152 is configured with 256 MB of NOR Flash
capability in the event that the firmware in the main Flash
Memory. The Flash will retain data for 20 years at +85°C.
becomes corrupted. This can occur because of an error
Note: these figures assume the sector the data is in has less
during reprogramming or an incorrect image being loaded.
than 1,000 erase cycles. The data retention drops as erase
PABS provides users with a convenient mechanism to
cycle count increases. After 10,000 cycles, data retention is
recover from corruption of the main Flash without removing
for 10 years. After 100,000 cycles, data corruption will likely
the card from the system in which it is installed. An on-board
be noticeable in one year. Read performance of the Flash
jumper is provided to cause the card to boot from PABS,
array is optimized in order to minimize system boot up time
thus allowing a user to reinstall the standard firmware load.
for applications such as avionics mission computers where
fast restarts after power interruptions are critical.

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 VPX3-152

MRAM NVRAM configurations which are user selectable:

An EVERSPIN MR20H50 Magnetoresistive Random Access • Four x2 lane PCIe Gen2 ports, transparent mode
Memory (MRAM) provides 512 KB fast, non-volatile storage
• Two x4 lane PCIe Gen2 ports, one non-transparent
of mission data that must not be lost when power is removed.
capable
Data retention is greater than 20 years, with unlimited write
endurance. Automatic data protection is provided on power • Eight x1 lane PCIe Gen2 ports, two non-transparent
loss. capable
• Other configurations possible. Consult factory.
Non-volatile Memory Security Note that a PCIe Gen2 port is also capable of running at
The VPX3-152 provides for the management of non-volatile Gen1 speeds, hence these ports can be used to connect to
memory devices in classified circumstances. All of the other cards that are only Gen1 capable. Other configurations
non-volatile devices NOR and NAND Flash, NVRAM may are also supported. Please consult the factory for any
be individually write-protected by a hardware jumper. The configurations not listed.
jumpers may be visually inspected to conform to security
procedures. SATA
The U-Boot firmware provides a non-volatile memory Depending on the variant, the VPX3-152 provides SATA 2.0
scrub function to perform a secure erase per NISPOM ports directly off the T2080 to the backplane.
requirements.
Two EIA-232 Serial Ports
The VPX3-152 I/O System The VPX3-152 provides two EIA-232 serial channels. The
EIA-232 serial ports support asynchronous communications
The VPX3-152 features a large number of I/O interfaces with one transmit and one receive signal. One serial port
including EIA-232, EIA-422 serial, USB, Ethernet, and LVTTL supports a cable detect signal to automatically detect the
DIO. The details of the I/O interfaces are described in the connection of a data terminal and can be used to control the
following paragraphs. The VPX3-152 is pin-out compatible boot-up sequence of the card if desired. Both ports utilize
with the VPX3-127, VPX3-131, VPX3-133, and VPX3-1257, the processor’s DUARTs. The Baud rate of both ports can be
variant dependent. set independently from 300 to 115200 KBaud.

Gigabit Ethernet Interfaces Two EIA-422 Serial Ports

The VPX3-152 provides two 10/100/1000BASE-T Ethernet The VPX3-152 provides two EIA-422 serial channels. Both
interfaces, both implemented within the processor with an of the serial ports support asynchronous communication
external PHY and transformers. One port is routed to P1 with baud rates of 300 to 115200 in EIA-232 or 422 modes.
backplane connector and the other port to P2 backplane
connector. The Ethernet controllers integrate a number of LVTTL Discrete DIO
features designed to minimize processor loading due to
Ethernet traffic. These include dedicated DMA engines, The VPX3-152 provides up to 4x 5V-tolerant LVTTL DIO
support for jumbo packets up to 9 KB, efficient buffer inputs, and up to 4x 5V LVTTL DIO outputs. Each input DIO
management schemes, checksum calculation for IP, TCP, bit is capable of generating an interrupt upon a change of
and UDP, and interrupt coalescence. Depending on the state, programmable to detect either edge. No protection is
configuration option ordered, the VPX3-152 can also provided on DIO. See the user manual for more details.
support two 1000BASE-KX in addition to two 1000BASE-T
Ethernets. The two 1000BASE-KX ports can also be Two USB 2.0 Ports
configured to operate a 10GBASE-KR. The VPX3-152 provides two USB 2.0 ports from the
processor. Each port can handle high speed (480 Mbps), full
Fabric Ports speed (12 Mbps), and low speed (1.5 Mbps) operation. When
operating at low speed or full speed, each port is managed
The VPX3-152 supports PCIe fabric ports to the backplane
by independent EHCI-compliant controllers internal to the
on P1 as per VITA 46 and VITA 65. Refer to Table 3 for the list
device. One EHCI compliant controller manages any ports
of supported VITA 65 OpenVPX module profiles.
operating in high-speed mode. One USB port is accessible
The backplane ports are connected from the processor on the P1 connector and the other is accessible on the P2
to the backplane through a PCIe switch. The switch connector. The VPX3-152 provides a current limited +5V
fans the processor downstream ports into the following output to power external USB devices such as keyboards.

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 VPX3-152

Safety Monitor General Purpose DMA Controllers

The VPX3-152 provides a variety of safety functions to The processor provides three 8-channel DMA engines that are
monitor proper board function. The Safety Monitor on available for general purpose use. The DMA subsystem can
the VPX3-152 includes a watchdog timer, clock monitors, be used for transferring blocks of data between the SDRAM,
voltage monitors and temperature monitors. The monitor Flash memory, Gigabit Ethernet, and the PCIe interfaces.
also serves as a decode of address space for Flash and The DMA controllers support direct and descriptor-driven
non-volatile memory, and access DIO. chained operation. The DMA controllers can support source
and destination striding. The DMA controllers also feature a
The watchdog timer uses, a single programmed time period, bandwidth management feature to allow the user to control
which defines a maximum interval between writes to the the distribution of bandwidth between the DMA channels.
watchdog register.
Elapsed Time Counter
Avionics Watchdog Timers
The VPX3-152 provides an Elapsed Time Counter (ETC)
Each watchdog timer is a pre-settable down-counter with device connected to the T2080’s I2C bus to record the total
a resolution of 1μsec. Time-out periods from 1 msec to power-on time across product’s life span.
32 seconds can be programmed. Initialization software
can select whether a watchdog exception event causes a
software interrupt, a processor reset, a card reset, or a system
reset. Once enabled to cause a reset, the watchdog cannot
be disabled. For development and maintenance purposes,
the reset from a watchdog time out can be disabled. One
of the four DIO can be configured as a watchdog event
indicator signal, outputting to the backplane in the event of
a watchdog timeout.

Extensive Timing Resources

The VPX3-152 provides a large number of timing resources to facilitate precise timing and control of system events. The list
of available timers is given in the table below.

TABLE 2 VPX3-152 timing resources

TICK RATE/ MAXIMUM
TIMER IMPLEMENTATION TYPE SIZE
PERIOD DURATION
PowerPC time base Four (one per 37.5 MHz/
Free-running counter 64-bit
register physical core) 26.67 nsec
PowerPC Eight (one per 37.5 MHz/
Presettable, readable down counter 32-bit 114.5 sec
decrementer thread) 26.67 nsec
Presettable, readable down counter with 37.5 MHz/
General purpose #0-7 T2080 MPIC auto-read and stop options, divide by 8, 31-bit 26.67 nsec 57.26 sec
16, 32 and 64 (default)
1 Hz/
RTC alarm RTC Alarm interrupt - 200 years
1 sec
Presettable, readable down counterwith 1 MHz/
Watchdog timer Monitor PLD 25-bit 33.55 sec
interrupt or reset on terminal count 1 usec
Safety Watchdog LTC6993 Timer Blox Factory configured reset time - 1 usec 3 sec

DS1682 Elapsed Factory programmed total elapsed time

Elapsed Time Counter 32-bit 0.25 sec 34 years
Timer Counter recorder

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 VPX3-152

XMC Site interface for on-chip debugging. Consult the Hardware

User’s Manual for more information if you need to use a COP
The VPX3-152 is equipped with one mezzanine site, emulator with the VPX3-152.
capable of supporting VITA 42.3 XMC modules. The XMC
site supports the VITA 46.9 X24s+X8d+X12d pin-out of Temperature Sensors
20 differential pairs and 24 single-ended signals. The XMC
interface is a x4 lane PCIe Gen2 connection direct to the The VPX3-152 provides temperature sensors to measure
processor following the VITA 42.3 pinout. board and processor temperatures. There are two sensors to
measure temperature on the card and one sensor to directly
XMC Power Routing measure the die temperature of the processor using its
thermal diode feature. The sensors can be read by software
The XMC site is provided with 5V (Vs3), 3.3V (Vs2), +3.3VAUX, and may be configured to generate an interrupt in case of an
+12VAUX, and -12VAUX power from the backplane as defined over temperature condition.
in VITA 46 for 3U basecards.

Conduction-cooled XMC Modules Software Support

To support the industry drive to open standards on
conduction-cooled cards, the XMC site mechanical U-Boot Firmware and Monitor
interfaces follow the VITA 20-2001 (R2005) conduction- The monitor provides a command line interface over
cooled PCI Mezzanine Card (PMC) standard. To optimize serial port to allow a user to perform a variety of system
the thermal transfer from XMC modules to the basecard, integration activities with the card. The monitor provides
the standard VPX3-152 thermal frame incorporates both debug and display commands, diagnostic results display
the primary and secondary thermal interfaces as defined by and exerciser controls, non-volatile memory programming
VITA 20-2005. and declassification and programming of parameters used
to control boot-up and diagnostics.
The combination of the secondary thermal interfaces, the
mid-plane thermal shunt, and the Curtiss-Wright TherMax™ Built-in-Test (BIT) - a library of diagnostic routines to support
thermal frame design provides optimum cooling for Power-up BIT (PBIT) and Initiated BIT (IBIT) are designed to
conduction-cooled XMC modules, allowing for higher power provide 95% fault coverage.
XMCs and/or increased long-term reliability through lower
component temperatures. For safety-certifiable applications, a boot loader will be
provided through partnership with associated OS vendors.
XMC Specifications
Operating System Software
• PCIe interface: 4-lane PCIe Gen2 as per VITA 42.3
The VPX3-152 is supported with an extensive array of
• Pn6 I/O: 20 different pairs and 24 single-ended to VITA software items, which cover all facets of developing
46.9 P2w1-X24s+X8d+X12d. When four Ethernets are application code for the board. Users have the option of
supported, the single end support is only x16s. choosing to develop with a variety of operating systems and
• Differential routing: 100 Ohm differential, 50 Ohm for Pn6 development tools. The following operating systems are
I/O signals supported for the VPX3-152:
• 3.3V power: Provided from backplane 3.3V (Vs2) • 64-bit VxWorks 7.x from Curtiss-Wright
• VPWR power: Drawn from backplane 5.0V (Vs3) • 64-bit NXP QorIQ Linux SDK v2.0 BSP from Curtiss-
• +/-12 VAUX, 3.3V: Routed to XMC site but not used by Wright
card + The Linux BSP does not support the same level of BIT
• Maximum supported XMC power: 20W as does the VxWorks BSPs
• Deos certifiable BSP in partnership with DDC-I
Status Indicators and Controls
• INTEGRITY tuMP certifiable BSP to DAL A in partnership
The VPX3-152 SBC provides fail status by illuminating a red with Green Hills Software
front panel LED in the event the diagnostics detect a card
failure. The SBC also provides a user-controllable, green • LynxOS certifiable BSP in partnership with Lynx Software
front panel status LED. Technologies
• PikeOS certifiable BSP in partnership with SYSGO
COP Emulator Interfaces • VxWorks 653 3.x certifiable BSP to DAL A in partnership
The VPX3-152 provides access to the processor COP with Wind River

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 VPX3-152

Thermal Cooling
TherMax-style thermal frame Full-width thermal interface to back-side slot wall
Applicable to conduction-cooled cards, a TherMax thermal To minimize the temperature rise from the mating slot
frame provides an unbroken metallic path from the XMC sites wall of conduction-cooled enclosures to the back-side
and shunted components to the back-side cooling surface thermal interface region of the VPX3-152, the thermal frame
of the card, thereby minimizing the temperature rise to these maximizes the thermal interface area by extending the frame
devices. In comparison, a typical thermal frame simply sits to the full width of the card, as illustrated in Figure 3. This
on top of the PWB and forces heat to flow through the PWB, deviation from the IEEE 1101.2 standard, which calls for
which has a high thermal resistance compared to aluminum. the thermal frame to be notched for compatibility with card
guides in standard air-cooled chassis, has the benefit of
Typical Thermal Frame
lower card operating temperatures and increased long term
Wedgelocks reliability. During test and integration activities where it may
XMC Module be desirable to install a conduction-cooled VPX3-152 into
an air-cooled card-cage, this can normally be accomplished
simply by removing the card guides.
Thermal Frame
Heat Flow

T IEEE 1101.2
Basecard PWB Card-edge
SHIM Heat Rise Profile
Through PWB

TherMax Thermal Frame

Wedgelocks
XMC Module

Thermal Frame
Heat Flow

Basecard PWB
VPX3-152
No PWB
Card-edge
Heat Rise
Profile
Figure 2: TherMax diagram
A TherMax thermal frame eliminates the PWB heat rise Figure 3: Card-edge profile deviates from IEEE 1101.2
inherent in a standard thermal frame VPX3-152 card-edge profile is optimized to provide a full-
width thermal interface to the back-side slot wall

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 VPX3-152

Rear Transition Module Note: Air-flow is specified for sea-level conditions. The
temperature refers to the inlet temperature at the card.
To gain access to the backplane I/O signals of the VPX3- The air-flow specifications are for worst case (highest
152, the RTM3-152 rear transition module (RTM) is available power) conditions, with a 20W XMC installed. Curtiss-
to access I/O in a lab environment. There are several variants Wright can supply additional recommendations for specific
of the RTM to match the VPX3-152 variants. Please contact power/temperature/altitude scenarios and pressure drop
the factory for more information. characteristics of the VPX3-152 support the design and
testing of cooling subsystems. Please contact the factory
for assistance.
Specifications
Ruggedization Levels
VPX3-152 Air-cooled Cooling Requirements • Air-cooled cards are available in Levels 0, 100.
• Configuration: Power estimates are for VPX3-152 with no • Conduction-cooled cards are available in Levels 200,
mezzanine installed 300.
• Temperature range: -40°C to 71°C Please see the Curtiss-Wright Ruggedization Guidelines
• Air-flow: 20 CFM product sheet for more information.

TABLE 3 Dimensions and weight

OPTION DIMENSIONS WEIGHT (grams) - Estimates
Air-cooled Level 0 per VITA 46/IEEE 1101.1 275
Air-cooled Level 100 per VITA 46/IEEE 1101.1 439
Conduction-cooled
per VITA 46/IEEE 1101.3 463
L200
Conduction-cooled
per VITA 48.2 535
L300 LRM
RTM3-131 per VITA 46 164
Notes:
1. The air-cooled format is designed to fit a chassis with 1.0” slot pitch, and shipped with 1” faceplates. A 0.8” variant can be available upon
customer request.
2. Air-cooled cards available in temperature ranges L000 and L100.
3. Refer to the deviation from IEEE 1101.2 in Figure 3.
4. Refer to Ruggedization Guidelines product sheet for more information.

TABLE 4 Power requirement estimates

VOLTAGE RUGGEDIZATION LEVEL TYPICAL TYPICAL MAX
Level 0 Air-cooled 25W 30W
5V (Vs3) Level 100 Air-cooled 29.3W 35W
Level 200 Conduction-cooled 29.7W 35W
3.3V (Vs2) Only routed to XMC
+3.3VAUX 0.5W, and is routed to XMC site
12V (Vs1) Note used
+/-12VAUX Only used by XMC
Notes:
1. Power estimates are for VPX3-152-xxxA134. No mezzanine installed.
2. All power rails defined as in VITA 46.0 for 3U basecards

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Ordering Information
The VPX3-152 is ordered with the following part numbers. VPX3-152-UVWXYPZ, where U, V, W, X, Y, P and Z denote cooling
method, temperature range, mechanical format and functional configuration respectively. Not all possible configurations are
offered, consult Curtiss-Wright for available configurations.

TABLE 5 Ordering information - VPX3-152-uvwxypz

PART NUMBER AVAILABLE OPTIONS
3U VITA 46 and 48
VPX3
form factor
Model number 152
A: Air-cooling
u: Cooling method
C: Conduction-cooling
0: L0 (0 to 50ºC)
1: L100 (-40 to 71ºC)
v: Ruggedization level 2: L200 (-40 to 85ºC)
3: L200 (-40 to 85ºC) with 2-level maintenance covers
9: Customized
1: 0.80” pitch (4)
3: 0.85” pitch, with 2-level maintenance covers
w: Mechanical format 5: 1” pitch (3)
9: Customized
Others: Reserved
A: Two x4 Gen2 ports (software configurable)
Four x2 Gen2 ports (software configurable)
x: Data Plane mode Eight x1 Gen2 ports with 2 NTB (software configurable)
B: Eight x1 Gen2 ports with 6 NTB (factory configurable)
Others: Reserved
0: 1x 1000BASE-T, 2x 1000BASE-KX 3: 2x 1000BASE-T, 2x 10G-KR
y: Ethernets/Control
1: 2x 1000BASE-T, 2x 1000BASE-KX 9: Customer specific
Plane mode
2: 1x 1000BASE-T, 2x 10G-KR Others: Reserved
0: 1.5 Ghz, 4 GB 4: 1.8 Ghz, 8 GB
p: Process/Memory 1: 1.5 Ghz, 8 GB 5: 1.8 Ghz, 16 GB
Config 2: 1.5 Ghz, 16 GB Others: Reserved
3: 1.8 Ghz, 4 GB
0: XMC with X24s+X8d+X12d, one SATA2, two EIA232, two EIA422, two DIO-in, two DIO out, two USB
1: XMC with X24s+X8d+X12d, one SATA2, two EIA232, two EIA422, four DIO-in, four DIO out
2: XMC with X12s+X8d+X12d, two SATA2, two EIA232, two EIA422, two DIO-in, two DIO out, two USB
z: I/O mode
3: XMC with X12s+X8d+X12d, two SATA2, two EIA232, two EIA422, four DIO-in, four DIO out
4: XMC with X16s+X8d+X12d, one SATA2, two EIA232, two EIA422, four DIO-in, four DIO out
Others: Reserved
Notes:
1. Not all combinations of an orderable variant are available as standard product. Variants highlighted in yellow are standard product.
2. Please consult your local sales office for further help in selecting the appropriate variant.
3. Air-cooled variants are delivered with a 1” faceplate. 0.8” variants are available, please consult factory.
4. Conduction-cooled variants are delivered in a 0.8” pitch.
5. Backplane configuration is default to what is specified. This can be reconfigured by customer.
6. LRM covers are only available for conduction-cooled cards.
7. I/O Modes 0 and 2 also have a an IPMC.

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