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Design and Analysis of Flipped Voltage

Follower for Different Aspect Ratio

Article · June 2016

DOI: 10.5120/ijca2016910513

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 International Journal of Computer Applications (0975 – 8887)
Volume 143 – No.13, June 2016

Design and Analysis of Flipped Voltage Follower for

Different Aspect Ratio
Sonam Gupta Rajesh Mehra Surbhi Sharma
Assistant Professor Associate Professor Assistant Professor
ECE Department ECE Department ECE Department
MIET, Jammu NITTTR,Chandigarh MIET,Jammu

ABSTRACT systems require follower to drive low impedance loads while

This paper identifies a conventional flipped voltage follower facilitating the optimized output voltage swing and low
(FVF) for high performance, low-voltage and low-power harmonic distortions [5], [6]. The circuit of basic PMOS
applications. This basic circuit is used as a voltage buffer, source follower is shown in figure 1
impedance matching and a level shifter. It presents more VDD
suppleness in contrast to the basic voltage follower as dc
voltage level can be amended by varying aspect ratio of the
MOS transistors. However, gain of the flipped voltage
follower can be altered by scaling the aspect ratio (W/L) ratio
of the transistors. This circuit is an essential building block for ISF
the analog circuits as it replicates the input voltage and
voltage accuracy is a vital factor for high performance VOUT
circuits. In this paper, proposed circuit has been designed and VIN
simulated on 45nm channel length technology. Simulated QSF
results for varying aspect ratio, W/L of 1, 2 and 3 are shown (gMsf )
in the results with the help of input and output voltage graphs.
VSS
The output voltage comes to be 95%, 90% and 85% of input
voltage for W/L ratio of 1, 2 and 3 respectively.
Fig. 1. Basic source follower
Keywords As the technology is being pushed to get downscaled by each
Analog circuits, Aspect ratio, Flipped voltage follower, passing day, the implementation of various analog circuits has
NMOS Source follower, Output impedance, PMOS Source become difficult. The power supply has been forced to lower
follower values so as to fulfill the lower power requirements of the
today’s world. As power consumption depends directly upon
1. INTRODUCTION the supply voltage, it is necessary to reduce the power supply.
CMOS is currently the most widely used IC technology for Since the downscaling of technology does not scale down the
both analog and digital as well as mixed signal applications. threshold voltage linearly, this non-linear behavior of VT
For realization of above technologies, analog building blocks seriously affects the voltage follower design [7].
are the basic and the indispensable components. For
uninterrupted transmission, conventional voltage follower is 2. VOLTAGE FOLLOWER
often used as one of the most important analog building Two different topologies of voltage follower are explained in
blocks [1], [2].
this section.
Voltage follower provides the advantage of impedance
matching between low impedance circuits and high 2.1 Basic Source Follower
impedance circuits. For achievement of high voltage gain in The circuit for basic source follower is shown in the previous
analog circuits, we generally employ common source section. It is basically a common drain amplifier circuit with
amplifier with high input impedance. If we desire this unity voltage gain. The output voltage at the source terminal
amplifier to be driven by a low impedance load, then a buffer follows the input voltage applied at the gate terminal. Input
must be placed after amplifier. This buffer or voltage buffer VIN is applied to the PMOS common drain transistor and the
will drive low impedance load with negligible loss of signal output VOUT is taken at its source terminal. The circuit has
strength [3], [4]. been designed with a PMOS transistor and an ideal current
source. We have used a resistor in place of current source. A
The voltage followers or source followers are being PMOS or NMOS can also be used as a load. The realization
incorporated in a large number of high speed or high of the above circuit with transistor provides better results and
frequency applications because of their simple intrinsic a PMOS source follower with another PMOS as current
structure.Voltage followers are also known as unity gain source is shown in the figure 2 below.
amplifiers since the output voltage follows the input voltage.
It is mainly used for impedance matching and level shifting. A
voltage follower inserted between a low impedance load and
high input impedance amplifier facilitates the efficient
coupling of a voltage signal to a larger load. In present
scenario, source follower has become an important basic cell
in analog circuit design. Now days, almost all the major

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 International Journal of Computer Applications (0975 – 8887)
Volume 143 – No.13, June 2016

VDD
VDD

VBIAS VIN

VOUT
VBIAS
VIN VOUT

VSS
Fig. 3. NMOS Source Follower
VSS
VSS The conventional basic source follower offers high simplicity
Fig. 2. PMOS Source Follower but along with its merits, it has some demerits too. Some of
For most of the analog circuits, voltage followers are operated them are large output impedance and non-linearity in output.
in saturation region. First and foremost, a constant current The flipped voltage follower is thus used to overcome many
must be provided through the output path. NMOS can also be limitations of conventional source follower.
incorporated to implement the voltage follower. The key
parameters related to voltage follower design in any 2.2 Flipped Voltage Follower
technology are voltage gain and output impedance. For this Flipped voltage follower is a high precision buffer. We can
circuit, the output impedance and voltage gain are given by also say that flipped voltage follower is a voltage buffer with
equations (1) and (2) respectively. shunt feedback. Its basic characteristics include low-power,
low-voltage and low impedance compared to basic source
1 follower. Some of the limitations of source follower are
Ro  (1)
overcome by implementing this circuit [7].
g m  g mb
The circuit for flipped voltage follower is shown in figure 4.
gm Depending upon the requirements, topology must be selected.
Av  (2)
g m  g mb VDD
Here, gm and gmb are the transconductances without and with
body effect respectively. The value of output impedance can Q1
be lowered by an enhanced body effect on the buffer but at the
cost of diminished voltage gain.
VOUT
So, there must be a tradeoff between the two values. The
values for both the voltage gain and the output impedance VIN QFVF
must be optimized as shown by the equation 3. (gmFVF)

g m  2I D  (3)

Here, β is the power dissipation and Id is the drain current. To IFVF

achieve low output impedance, drain current ID must be
raised. But, this will result in large W/L ratio, also known as VSS
aspect ratio which is not tolerable in deep submicron
technologies, since the main aim is to reduce the transistor Fig. 4. Flipped voltage follower
size [8]. Also, the power dissipation will be raised with a
boost in W/L ratio as justified by equation 4. Above is shown a PMOS based flipped voltage follower
(FVF). FVF consists of PMOS input transistor QFVF,
w nCOX transistor Q2 with shunt feedback and bias current IFVF. FVF
 (4) has restricted current sinking and soaring current sourcing
L capability [8]. The circuit shown in figure 4 operates as a
Here, W is the width of the gate, L is the length of the source follower. For the analysis, we will consider the circuit
channel, µn is the mobility and Cox is the capacitance per unit shown in figure 5.The circuit is same as that of figure 4 except
area of gate oxide.The circuit for NMOS source follower with for the current source which is replaced by an NMOS.
NMOS as current source is shown in figure 3.

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 International Journal of Computer Applications (0975 – 8887)
Volume 143 – No.13, June 2016

VDD
Q2

VOUT
VIN
Q1

VBIAS
Q3

VSS
Fig. 5. PMOS Source Follower with Current Source
The condition for the FVF is that the current through QFVF
should be held stable, independent of the output current. The
low impedance aids the high sourcing at the output node,
which is justified by equation 5.
Fig. 6. Flipped voltage follower Test bench schematic
1 4. RESULTS AND DISCUSSIONS
ro  (5)
Simulation results are taken by Cadence Software for flipped
g mFVF g m1 roFVF voltage follower using MOS transistors. Figures 7, 8 and 9
show the dc response between Vo and Vin for W/L of 120/45
Here, gmFVF and gm1 are the transconductances of QFVF
and Q1 respectively and roFVF be the output resistance of
transistor QFVF. The value of roFVF is in the order of 20–
100Ω. Note that Q1 provides shunt feedback and that QFVF
and Q1 form a two pole negative feedback loop. The output
impedance of the control transistor is minimized by the
feedback loop [9]. Minimum possible low voltage supply
required for flipped voltage follower is given by equation 6.

𝑉DD (MIN ) = 𝑉𝑇𝑃 + 2VDS (SAT ) (6)

The above equation verifies the fact that the flipped voltage
follower can be operated with low voltage supply. These
buffers do not exhibit any type of stability problems. They are
capable of producing higher currents than that of bias current.
Flipped voltage followers generally put on display superior
results when kept in contrast to a basic conventional source
follower due to their low output impedance [10]. Fig. 7. DC response for W/L of 120/45 for both PMOS
for both PMOS, for W/L of 120/45 to 240/45 for both PMOS
3. SCHEMATIC DESIGNS
Figure 6 shows the test bench schematic for the simulation and for W/L of 120/45 to 360/45 for both PMOS respectively.
purpose.
The gain of the flipped voltage follower greatly varies with
varying aspect ratio. Also if the FVF is used as a level shifter,
it exhibits more suppleness in comparison to basic source
followers since the dc value of voltage level can be adjusted
by altering aspect ratio of the MOSFETS. High-performance
VLSI designs are creating a center of attention because of
emerging need for miniaturization [11]. In the figure 6 shown
below, we can see the test bench schematic for flipped voltage
follower .

Fig. 8. DC response for W/L of 120/45 to 240/45 for PMOS

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 International Journal of Computer Applications (0975 – 8887)
Volume 143 – No.13, June 2016

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