1990 Fujitsu Channelless Gate Arrays

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Channelless Gate Arrays
=- 1990 Data Book and
Design Evaluation Guide
1990
FUJITSU
Design Information III
AU Series CMOS Gate Array Macrocell Library •
CG21 Series CMOS Gate Array Macrocell Library IIIJ

Sales Information lEI
cP
FUJITSU
CMOS Channelless Gate Arrays
1990
Data
Book
Fujitsu Umited
Tokyo. Japan
Fujitsu Microelectronics. Inc.
San Jose. California. U.S.A.
Fujitsu Mlkroelektronik GmbH
Frankfurt. ER. Germany
Fujitsu Microelectronics Pasclflc Asia PTE Limited
Kowloon. Hong Kong
Copyright© 1990 Fujitsu Microelectronics, Inc., San Jose, Califomia
All Rights Reserved.

Circuit diagrams utilizing Fujitsu products are induded as a means of illustrating typical semiconductor applications. Complete information suffi-
cient for construction purposes is not necessarily given.
The information contained in this document has been carefully checked and is believed to be reliable. However, Fujitsu Microelectronics, Inc.
assumes no responsibility for inaccuracies.
The information conveyed in this document does not convey any license under the copyrights, patent rights or trademarks claimed and owned
by Fujitsu Limited, its subsidiaries, or Fujitsu Microelectronics, Inc.
Fujitsu Microelectronics, Inc. reserves the right to change products or opacifications without notice.
No par1 of this publication may be copied or reproduced in any form or by any means, or transferred to any third party without prior written con-
sent of Fujitsu Microelectronics, Inc.
This document is published by the Publications Department, Fujitsu Microelectronics, Inc.,
3545 North First Street, San Jose, Califomia, 95134-1804; U.S.A.
Printed in the U.S.A. Edition 2.0
Ethamet™ is a registered trademark of Xerox Corporation.

EtherStar™ is a trademark of Fujitsu Microelectronics, Inc.
StarLAWM is a trademark of AT&T.
UNIXTM is a trademark of Ball Telephone Laboratories, Inc.
ViewCADTM is a trademark of Fujitsu Limited
X Window SystemTM is a trademark of Massachusetts Institute of Technology (Mm
VERILOGTM is a trademark of Gateway Automation
LASARTM is a trademark of Teradyne, Inc.
HILO® is a registered trademark of GenRad, Inc.
IKOSTM is a trademark of IKOS Systems, Inc.
SynopsysTM Design Compiler™ is a trademark of Synopys Inc.
Contents
Preface ..................................................................... v
Fujitsu ASIC Products Listing .................................................... xi
Section 1 - Design Information

Chapter 1 Fujitsu CMOS Products ............................................. 1-3
Data Sheet: AU Series CMOS Gate Arrays ............................. 1-11
Data Sheet: CG21 Series CMOS Gate Arrays .......................... 1-31
Chapter 2 Steps Toward Design. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1--49
Chapter 3 Design Procedures ............................................... 1-53
Chapter 4 Design Considerations ............................................. 1-65
Chapter 5 Delay Estimation Principles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1-79
Chapter 6 Quality and Reliability ............................................. 1-99
Chapter 7 Application Notes ................................................ 1-115
Developing Test Patterns that Work with the Physical Tester .............. 1-117
Selecting the Best Package for Your ASIC Design ...................... 1-123
Section 2 - AU Series CMOS Gate Array Unit Cell Library
Section 3 - CG21 Series CMOS Gate Array Unit Cell Library
Section 4 - Sales Information

Introduction to Fujitsu ........................................................ 4-3
Integrated Circuits Corporate Headquarters - Worldwide ............................. 4-7
FMI Sales Offices for North and South America .................................... 4-8
FMI Representatives - USA ................................................... 4-9
FMI Representatives - Canada ................................................ 4-11
FMI Representatives - Mexico ................................................ 4-11
FMI Representatives - Puerto Rico ............................................ 4-11
FMI Distributors - USA ...................................................... 4-12
FMI Distributors - Canada ................................................... 4-16
FMG Sales Offices for Europe ................................................ 4-17
FMG Distributors - Europe .................................................. 4-18
FMA Sales Offices for Asia and Australia . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-20
FMA Representatives - Asia .................................................. 4-21
FMA Distributors - Asia and Australia .......................................... 4-22
Iii
Illustrations
Figures
1-1 .. The Basic Cell .............................................................. 1-4

1-2... The Basic Cell as a 2-input NAND Gate .......................................... 1-4
1-3 .. Physical Construction ofthe Unit Cell NAND Gate .................................. 1-5
1-4 .. Channeled Gate Array Chip Structure ............................................ 1-8
1-5 .. Channelless Gate Array Chip Structure ........................................... 1-8
1-6 .. Equivalent Gate Count vs. Processing Speed, Fujitsu CMOS Gate Array Technologies ..... 1-9
1-7 .. Equivalent Gate Count, Fujitsu CMOS ASIC Technology Families ..................... 1-10
3-1 .. ASIC Design Flow with ViewCAD .............................................. 1-54
3-2 .. Generic Workstation Design flow ............................................... 1-57
3-3 .. Post-Workstation Design Process ............................................. 1-60
4-1 .. Hierarchical Organization of AUlCG21 Designs ................................... 1-66
4-2 .. Bus Driver Cell, B41 ........................................................ 1-71
4-3 .. SSO--Generated Noise ...................................................... 1-73
4-4 .. SSO Pin Assignments ....................................................... 1-75
4-5 .. Scan Circuit Configuration .................................................... 1-76
5-1 .. Delay lime vs. Loading Factor ................................................ 1-80
5-2 .. Delay Path Sample Circuit .................................................... 1-82
5-3 .. Operating Environment Factors Influencing Delay ................................. 1-86
6-1 .. Quality Control Processes at Fujitsu ........................................... 1-100
6-1 .. (Continuation) Quality Control Processes at Fujitsu ............................... 1-101
6-2 .. Distribution of Component Failure ............................................. 1-105
6-3 .. Example of Life Test Data on IC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-106
6-4 .. Acceleration Rate vs. Junction Temperature ..................................... 1-107
6-5 .. DigitallC Failures and Corrective Actions ....................................... 1-109
Figures from Chapter 7, Application Notes
CMOS ASIC Test Patterns

1... " Determining a Successful Test Cycle Length .................................... 1-115
2..... Determining Preferred Cycle Length ........................................... 1-119
3..... Input to Input Skew ............................................•........... 1-120
4 ..... Input to Output Skew ....................................................... 1-121
ASIC Packaging Considerations

1. . . .. Package Size versus Pin Count .............................................. 1-125
2.. ' " Minimizing Interconnect Length ............................................... 1-126
3 ..... Impact of Noise on Speed ......... , ......................................... 1-126
Iv
4 ..... PLCC Package Construction (Front View) ...................................... 1-129
5 ..... PLCC Lead Frame Construction (Top View) ..................................... 1-129
6..... 321-Pin Ceramic Pin Grid Array . ............................................. 1-132
7 ..... Staggered Pin Grid Array Routing ............................................. 1-133
8 ..... Flatpack Configurations ..................................................... 1-134
9 ..... Defect Caused by Difference in Thermal Coefficient of Expansion ................... 1-135
10.... PLCC Package ........................................................... 1-136
11. . .. Cross-8ection of a Plastic Small-Outline J-Lead Package . . . . . . . . . . . . . . . . . . . . . . . . . 1-136
12.... Surface Mount PGA ........................................................ 1-137
13 .... Solder Pad Design for Surface Mount Pin Grid Arrays ............................. 1-137
14.... CMOS Output Buffer Model (Totem Pole) ....................................... 1-141
15.... 1/0 Model, CMOS Input .................................................... 1-141
16.... 1/0 Model, TTL Input ....................................................... 1-142
17.... CMOS Basic Gate Structure: The Pull-up/Pull-down Network ....................... 1-142
18.... CMOS Basic Gate Structure: The Transmission Gate .............................. 1-143
19 .... Electrical Model of Simultaneously Switching Outputs ............................. 1-144
20 .... Effect of SSO Noise on Thresholds ............................................ 1-145
21 .... Variation in Inductance, Resistance, and Capacitance as a Function of Pin Position ..... 1-147
22 .... Measured Pin Capacitance by Package Position ................................. 1-148
23 .... SeH-lnductance in a Circuit .................................................. 1-149
24 .... Causes of Crosstalk ........................................................ 1-150
25 .... Heat Flow through a Cavity~own Ceramic PGAwith an Annular Fin Heat Sink ......... 1-153
Tables
1-1 .. SuperMacro Implementations for CMOS ASiC ..................................... 1-7
4-1 .. Basic Cells per Hierarchy Level ................................................ 1-67
4-2 .. Recommended Maximum 1/0 Count per Block .................................... 1-67
4-3 .. Representative Value of Output Buffers .......................................... 1-73
4-4 .. Junction Temperature Coefficient of Load ....................................... 1-74
5-1 .. AC Parameters of Unit Cells .................................................. 1-82
5-2 Estimation Table for Metal Loading ............................................. 1-83
5-3 Package Thermal Resistance in °C/W ........................................... 1-68
5-4 Power Dissipation Calculation Factors .......................................... 1-90
5-5 Input Buffer AC Power Dissipation (PACIN) Examples (in mW) ....................... 1-91
5-6 .. Output and Bidirectional Buffer AC Power Dissipation (PACOUT) Examples (in mW) ....... 1-90
5-7 .. Output and Bidirectional Buffer DC Power Dissipation (POCOUT) Examples (in mW) ...... 1-90
5-8 .. Internal Basic Cell Power Dissipation (PG) Examples .............................. 1-91
5-9 .. RAM Macro Power Dissipation (PRAW Examples .................................. 1-92
5-10 . ROM Power Dissipation (PROW Examples (in mW) ................................ 1-92
5-11 . Maximum Delay Multipliers ................................................... 1-93
5-12 . Minimum Delay Multipliers .................................................... 1-93
v
5-13 . Single and Dual-Port RAM Columnar Configurations ................' ............... 1-95
5-14 . Calculated Parameters for Single-Port 256K x 8 Bit RAM ........................... 1-96
5-15 . Delay Parameters for a Single-Port 256K x 8 Bit RAM (AU Series) .................... 1-97
6-1a . Sampling Plan for Engineering Testing: Endurance Test ............................ 1-102
6-1b . Sampling Plan for Engineering Testing: Environmental and Mechanical Test ............ 1-103
6-1c . Sampling Plan for Engineering Testing: Environmental and Mechanical Test (Optional) ... 1-104
6-1d . Sampling Plan for Engineering Testing: Continuity Test ............................ 1-104
6-2 .. Determination of Coefficient ................................................. 1-108
6-3 .. Product Defects Analysis .................................................... 1-110
6-4 .. Relationship between Failure Causes and Analytical Test Methods ................... 1-111
6-5 .. Sampling Plan for Reliability Testing ........................................... 1-112
6-6 ., Example of Reliability Testing ................................................ 1-113
6-7 Example of ElectricalTesting ................................................. 1-113
6-8 .. Example of Electrical Criteria ................................................ 1-114
Tables from Chapter 7, Application Notes
ASIC Packaging COnsiderations

1 .... Considerations for Package Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-124
2 .... Package Material Characteristics ............................................. 1-128
3 .... Fujitsu Package Types ...................................................... 1-130
4 .... PGAs Available from Fujitsu ................... ; ............................. 1-131
5 .... Comparison of Critical Features .....................................•........ 1-138
6 .... ASIC CMOS Package Types and their Characteristics ............................. 1-140
7 .... Electrical Characteristics of Each Signal Type ................................... 1-147
vi
Preface
Fujitsu Microelectronics introduced its first commercially available gate array, a bipolar chip called the
8200, in 1974 (Fujitsu had been making them for internal use since 1972). Over the years it has been so
popular that it is regarded as the world's most widely implemented gate array. Since that first array, Fujitsu
has produced over 9000 successful bipolar and CMOS custom designs.
Fujitsu designs are successful because they are implemented using the most advanced design verification
CAD systems available, allowing the production of chips with 90% cell utilization (more functional logic per
chip than the industry standard) and one of the highest performance records in the industry.
This data book provides you with the information necessary to choose an application specific integrated
circuit (ASIC) device using Fujitsu's advanced AU and CG21 channelless (sea-of-gates) CMOS gate array
technologies. The data book describes Fujitsu's AU and CG21 gate arrays, explains their benefits and
specifications, and outlines the process by which logic and circuit designers create a chip. The cell
function (unit cell) libraries for the AU and CG21 technologies are included in the second and third sec-
tions of this volume. The first volume in this data book series provides the same information for Fujitsu's
channeled gate arrays.
Fujitsu has pioneered and maintained a technological lead in the production of bipolar as well as CMOS
ASIC devices; data books describing Fujitsu's other ASIC product families, as well as any other technical
or sales-related information, may be obtained from any Fujitsu Technical Resource Center or Sales Office
listed at the end of this book or by calling or writing Fujitsu Microelectronics Inc., 3545 North First Street,
San Jose, CA 94135-1804, (408) 922-9000.
vii
Fujitsu ASIC Products Listing
CMOS Channeled Gate Arrays Data Book

UHB Series High Drive CMOS Gate Arrays - 1.511. 0.9 ns typical delay
Description Name Device Part Number
336 Gates, 58 1/0 C330UHB MB625xxx

530 Gates, 64 1/0 C530UHB MB624xxx
830 Gates, 741/0 C830UHB MOO23xxx
1,233 Gates. 88 VO Cl200UHB MOO22xxx
1,724 Gates, 102 1/0 C1700UHB MB621 xxx
2,220 Gates, 115 1/0 C2200UHB MOO20xxx
3,066 Gates, 140 1/0 C3OO0UHB MOO06xxx
4,174 Gates, 155 VO C4100UHB MOO05xxx
6,000 Gates, 1551/0 C6000UHB MB604xxx
8;768 Gates, 1881/0 C8700UHB MB603xxx
12,734 Gates, 220 1/0 Cl2000UHB MOO02xxx
CG10 Series High Drive CMOS Gate Arrays - 0.811. 0.5 ns typical delay
3,256 Gates, 108 110 CG10272 MBCG10272xxx

4,032 Gates, 123 1/0 CG10342 MBCG 10342xxx
5,072 Gates, 148 1/0 CG10492 MBCG10492xxx
6,510 Gates, 1631/0 CG10572 MBCG10572xxx
7,684 Gates, 163 1/0 CG10692 MBCG10692xxx
11,080 Gates, 188 1/0 CG10103 MBCG10l03xxx
14,720 Gates, 220 1/0 CG10133 MBCG10133xxx
CMOS Channelless Gate Arrays Data Book

AU Series CMOS Series Gate Arrays - 1.211. 0.6 ns typical delay
10,224 Gates, 108 1/0 Cl0KAU MOO37xxx

15,486 Gates, 1381/0 C15KAU MB636xxx
20,876 Gates, 1551/0 C20KAU MB635xxx
31,500 Gates, 178 1/0 C30KAU MB634xxx
41,184 Gates, 220 1/0 C40KAU MOO33xxx
52,164 Gates, 257 VO C50KAU MOO32xxx
75,140 Gates, 300 1/0 C75KAU MB631 xxx
102,144 Gates, 3321/0 Cl00KAU MOO3Oxxx
CG21 Series CMOS Series Gate Arrays - 0.8Jl, 370 ps typical delay
10,224 Gates, 1081/0 CG21103 MBCG21103xxx

15,486 Gates, 1421/0 CG21153 MBCG21153xxx
20,876 Gates, 155 1/0 CG21203 MBCG21203xxx
31 ,500 Gates, 178 1/0 CG21303 MBCG21303xxx
41,184 Gates, 220 1/0 CG21403 MBCG21403xxx
52,164 Gales, 2451/0 CG21503 MBCG21503xxx
75,140 Gates, 284 1/0 CG21753 MBCG21753xxx
102,144 Gates, 3321/0 CG21104 MBCG21104xxx
viii
Fujitsu ASIC Products Listing (Continued)
BiCMOS Gate Arrays Data Book

BC Series BICMOS Gate Arrays - 1.51111.41J., 0.65 ns typical delay
Description Name Device Pari Number
645 Gales, 52 1/0 BC400 MB211xxx

1,218 Gales, 721/0 BC800 MB212xxx
1,872 Gales, 96 I/O BC1200 MB213xxx
3,240 Gates, 112 I/O BC2000 MB214xxx
BC-H Series BICMOS Gate Arrays - 1.01110.511. 0.45 ns typical delay
4,312 Gates, 96110 BC4000H MB221xxx

8,160 Gates, 128 I/O BC8000H MB222xxx
11,968 Gates, 160 I/O BCI2000H MB223xxx
16,720 Gates, 200 VO BCI6000H MB224xxx
7,920 Gates, 200 VO with 40Kb RAM BC8040HM MB228xxx
ECl Gate Arrays Data Book

ET Series ECl Gate Arrays - 1.011. 220 ps typical delay
1,056 Gates, 64 1/0 ET750 MB121Kxxx

2,112 Gales, 881/0 ET1500 MB123Kxxx
4,224 Gates, 120 I/O ET3000 MB125Kxxx
6,l60Gates,12O I/O ET4500 MBI28Kxxx
2,640 Gates, 120 I/O with 4.6 Kb RAM ET2004M MB181/191xxx
2,640 Gates, 1361/0, with 9.2 Kb RAM ET2009M MB 1821192xxx
3,960 Gates, 1361/0, with 4.6 Kb RAM ET3004M MB 183/193xxx
H Series ECl Gate Arrays - 0,511.100 ps typical delay
9,856 Gales, 200 I/O ET10000H MB147/157xxx

9,856 Gates, 300 I/O El0000H MB 14B/158xxx
4,928 Gates, 200 1/0, wilh 5.1 Kb RAM E5005HM MBI851195xxx
Ultra High Performance ECl Gate Arrays 0.511. 75 ps typical delay
128 Gales, 23/1/0 E128H MB1800

32 Gates, 13 I/O E32 MB1700
128 Gates 16 I/O E128 MBl600
VH Series ECl Gate Arrays 0.411. 80 ps typical delay
38,948 Gates, 300 1/0 E30000VH MB1621172xxx

13,440 Gales, 290 I/o, 40Kb RAM El0040VHM MB 165/175xxx
13,440 Gales, 2941/0, 160Kb ROM El0160VHR MBI68/178xxx
CMOS Standard Cell Data Book

AU Series Standard Cells - 1.211. 0.6 ns typical delay
AS Series Standard Cells - 0.811. 370 ps typical delay

Ix
x
- - - - - - - - - - - - - - - - - - - Section 1
Design Information
I Page
1-3 Chapter Fujitsu CMOS Products
1-11 Data Sheet: AU Series CMOS Gate Arrays
1-31 Data Sheet: CG21 Series CMOS Gate Arrays
1-49 Chapter 2 Steps Toward Design
..
1-53 Chapter 3 Design Procedures
1-65 Chapter 4 Design ConSiderations
1-79 Chapter 5 Delay Estimation Principles
1-99 Chapter 6 Quality and Reliability
1-115 Chapter 7 Application Notes
1-117 Developing Test Patterns that Work with the Physical Tester
1-123 Selecting the Best Package for Your ASIC Design
Design Information CMOS Channelless Gate Arrays
1-2
CMOS Channel/ess Gate Arrays Fujitsu CMOS Products
Chapter 1 - Fujitsu CMOS Products
Contents of This Chapter

1.1 Introduction
1.2 CMOS Technology for ASICs
1.3 CMOS Gate Array Structure
1.4 Fujitsu's CMOS Gate Arrays
Data Sheet: AU Series CMOS Gate Arrays
Data Sheet: CG21 Series CMOS Gate Arrays
1.1 Introduction
This section of the data book gives an overview of CMOS technology and introduces the CMOS
channelless gate array technology families developed by Fujitsu to implement ASIC designs.
1.2 CMOS Technology for ASICs

ASICs (Application Specific Integrated Circuits) are large scale integrated circuits that provide customers
with made-to-order functions. These ICs implement the unique value designed into customer products by
producing custom semiconductor designs that allow customers to take advantage of perceived market
opportunities in a timely manner. The customized solutions offered by ASICs combine the power of
personalized electronics and the advantage of increased system efficiency.
CMOS technology has long been chosen for ASIC applications because of its low power and high density
characteristics. Advancing process technology and new production and fabrication techniques have now
allowed device speed to increase to the point where it is competitive with bipolar devices. Fujitsu CMOS
gate arrays are manufactured using advanced silicon gate technology utilizing two-layer and three-layer
metal. This fabrication process yields parts that:
a. require very low power dissipation (typically less than 500 mW per channeled array)
b. operate at speeds equaling existing bipolar technologies
c. feature higher gate densities than competing bipolar devices
d. use a single power supply of 5 volts or less
e. provide top-grade noise immunity and programmable logic levels compatible with TTL and
CMOS logic families
1.3 CMOS Gate Array Structure

Fujitsu CMOS gate arrays are configured in a matrix of basic cells in the center of the chip with
input-output (1/0) cells on the device periphery. One basic cell is equivalent to a two-input NAND gate.
The custom logic function is realized by interconnecting basic cells with double-layer metallization for the
channeled and smaller channelless arrays and triple-layer metallization for channelless arrays of over 30K
equivalent gates. Fujitsu's gate array products are fabricated using a twin-tub polysilicon CMOS process
to produce high-speed, high-density arrays consisting of 300 to 100,000 basic cells.
1.3.1 The Basic Cell

The basic cell of Fujitsu's CMOS gate array is a common building block consisting of one pair of
P-channel and one pair of N-channel MOS transistors (represented by the broken-line box in Figure 1-1).
Channelless arrays differ from the channeled arrays by the addition of four smaller N-channel transistors
also shown in Figure 1-2. The four additional transistors are isolated from the P-and N-channel pairs,
have no effect on them when the basic cells are configured as digital logic unit cells, and can be used as
1-3
Fujitsu CMOS Products CMOS Chann9lless Gate Atnlys
an area to place the metalizalion that connects the unit cells. The basic cells are assembled in pairs on
double-wide columns, and share common terminals of the two sets of four N-channeltransistors.
The four additional N-channeltransistors are used in conjunction with the "generic" portion of the basic
cell to construct RAM and ROM compiled cell modules.
,..-------, ,..-------,
L ______ _
Basic Cell #1
--------'
Basic Cell #2
Figure 1-1. The Basic Cell
Since these are "generic" basic cells, no connections are shown to the power supply (+5 volts), to ground,
or to the two common control gate terminals of the circuit. These connections are made as required during
the metalization phase of the manufacturing process. The basic cell is the building block of all functions of
the array and is often used as a unit to describe the size of an array or the complexity of a unit cell (logic
function).
Figure 1-2 shows a schematic representation of the basic cell with the addition of the custom metalization
required to convert the generic basic cell into a two-input NAND gate.
,..---------------,
r=i OA(IN)
Vco
' - - - H - -.....- F(OUT)
Vco
~B(IN)
----------------'
Figure 1-2. The Basic Cell as a 2-lnput NAND Gate
1.3.2 Basic Cell Construction

Basic cell construction varies somewhat among Fujitsu's CMOS technologies; however, an explanation
based on AV technology provides a good model of how a basic cell is fabricated in any of the CMOS
1-4
CMOS ChanneJ/ess Gale Anaya Fujitsu CMOS Products
families. In AV, the basic cell is constructed from an N-type silicon substrate upon which a P-well is
deposited. The surface of the substrate is then covered with a thin layer of silicon dioxide (glass) and two
strips of polysilicon are deposited perpendicular to the P-well and geometrically parallel. (Polysilicon is a
silicon-based compound chemically aHered so that it has good electrical conduction properties.) The
polysilicon strips serve as the gate control elements of the basic cell and also as the two electrical
interconnections between the sources of the P and N transistor pairs. See Figure 1-3.
Input Input
Output
Figure 1-3. Physical Construction of the Unit Cell NAND Gate
The silicon dioxide layer is then stripped away from all areas of the substrate not protected by polysilicon.
In two separate steps, the N-type and the P-type material of the twin tubs is diffused onto the substrate.
For the next step. N-type material is diffused or implanted into the P-well that was previously laid down. It
straddles the two strips of polysilicon close to their ends. The polysilicon resists the diffusion. which
resuHs in the formation of three pads of N-type material separated by the two strips of polysilicon
(self-aligned processing). The center pad of N-type material serves as a common drain terminal for both
N-channeltransistors. The outer pads are the separate source elements.
Then the P-type material is deposited on the the N-type substrate straddling the two polysilicon strips.
Similarly the center pad of P-type material forms the common source connection for both P-channel
transistors. The basic cell is then converted to a unit cell by application of a custom metalization pattern
that connects (or wires) various points of the basic cell, or a number of basic cells. together. NO TAG
shows the structure of a basic cell configured as a NAND gate after metalization (represented by the solid
bold line connections) has been laid down.
Cell construction in the AU and CG21 technologies requires three layers of metal to be applied. Such
layers are separated by an insulating layer of silicon dioxide. Interconnections between the metal layers
are made by means of ''vias" passing through the glass.
1.3.3 BasiC Cell Arrangement

Basic cells can be arranged in any of the following configurations:
1-5
Fujitsu CMOS Products CMOS Channel/ess Gate Arrays
a. Unit cells
b. User macros
c. Compiled cells and super macros
d. 1/0 buffer cells
1.3.4 Unit Cells

Unit cells are the fundamental logic unit or function used for logic design, including digital logic gates,
compiled cells, and 1/0 buffers.
1.3.5 User Macros

User macros are composed of unit cells to form higher level logic block functions (e.g., shift register or
decoder). Such blocks are user-defined and may contain any unit cell configuration.
1.3.6 Compiled Cells and SuperMacros

Compiled cells and supermacros are MSI and LSI macros that perform memory functions (RAM and
ROM) and such logic functions as adders and multipliers. Compiled cells are automatically generated by
Fujitsu using proprietary compilers. Their building block approach and functional compatibility with
common MSI and LSI devices can simplify construction of large and complicated designs. These cells are
currently available for the AU and CG21 technologies; the status and design requirements of the super
macros should be verified with a Fujitsu Sales Office or Technical Resource Center.
Selected compiled cells include:
Dual-port RAM
Triple-port RAM
Single-port RAM
- ROM
MuHiplier
- Barrel shifter
-FIFO compiler
SuperMacros
Fujitsu's next step upward in ASIC functionality is embodied in the concept of supermacros. SuperMacros
are large functional organizations implemented as an integral part of a chip. SuperMacros can be
large-scale compiled cells or core cells, as well as generic or proprietary LSI functions. Reduction of board
space, reduction of cost, and reduction of design cycle time, as well as extended functionality, reliability,
performance, and security of design are all advantages of supermacros. Since supermacros are not
bound to a particular technology, they may be migrated from one technology to another.
Fujitsu provides customers with gate and behavioral level models, macro symbols, and data
sheets/specifications as well as kit parts in order to provide complete support from development to system
integration. The supermacros listed below are the first to be developed for Fujitsu's CMOS supermacro
library.
1-6
Table 1-1. SuperMacro Implementations for CMOS ASIC

Function Compatible Device Technology Gate Complexity
Universal Synchronous/Asynchronous UHB/AUlCG21
8251A 2900
ReceiverlTransmHter (USART)
Universal Asynchronous UHB/AUlCG21 TBD
ReceiverlTransmHter (UART) 8868
Programmable Interval Timer 8253 UHB/AUlCG21 5680
Programmable Peripheral Interface 8255A UHB/AU/CG21 784-1403'
Programmable Interrupt Controller 8259 UHB/AUlCG21 2205
Programmable DMA Controller 8237 UHB/AU/CG21 5100
Clock Generator/Driver 8284 UHB/AUlCG21 99
Bus Controller 8288 UHB/AU/CG21 250
Programmable Internal Timer 8254 UHB/AU/CG2t 3500
CRT Controller 6845 UHB/AU/CG21 2843
SCSI Protocol Controller 870302 UHB/AUlCG21 3600
EtherNet Controller3 870122 UHB/AUlCG21 -3900
4-bit Arithmetic logic Unit (AlU) Slice
Carry lookahead
Status and Shift Control
2901
2902
2904
UHB/AUlCG21
UHB/AU/CG21
UHB/AUlCG21
917
33
-500
10
12-bit Microprogram Controller 2910 UHB/AU/CG21 1100
'Several options are aVailable (Mode O,s 785 gates)
2Full-featured Fujitsu proprietary supermacro
3Under consideration
1.3.71/0 (Input/Output) Buffer Cells

The 1/0 buffer cell is composed of both extemal and internal VO cells. External 1/0 cells are located on the
periphery of the gate array. Internal 1/0 cells are ordinary unit cells located in the main cell matrix of the
gate array. There are a variety of 1/0 buffer designs including input, output, and bidirectional buffers.
Input buffers convert external voltage levels to internal CMOS levels. Input buffers include:
Low-drive input buffers with pull-up or pull-down resistance
Schmitt trigger input buffers
High-drive clock input buffers
Output buffers convert internal CMOS levels to external voltage levels and are available with 3.2 rnA,
8 mA, 12 mA, and 24 mA current sink capability, and optional noise-limiting resistance (edge rate control).
Output buffers include:
Output buffers with noise-limiting resistance
3-state output buffers
The bidirectional buffer is a combination of an input buffer and a 3-state output buffer in the same unit cell.
1.3.8 Structure of the Chip

The arrangement of the basic cells on the chip differs according to the technology. The fundamental chip
layout is a matrix of basic cells surrounded by a perimeter of VO cells. In the channeled arrays, basic
cells can be arranged in single columns, with the channels between the columns used for routing unit cell
interconnections, as in AV, AVB, AVL, and AVM technologies, or in double columns, as in UHB technology.
See Figure 1-4. In the channelless or sea-ol-gates technologies (AU and CG21), the cells are positioned
with no wiring channels between the double columns, allowing the wiring to go over the cells, rather than
between the cells. See Figure 1-5.
1-7
Fujitsu CMOS Products CMOS Channel/ess Gate Arrays
I Basic Cell (Double Column)
DO 0 4------------------. DOD mlr=t ........................................ ElImImI

~ B
0 0
0 D
t
I
I
I > Basic Cell Columns _
Basic Cells
0
t
I
I
I
II ~ Wiring Channels I
I
I I
I
I
+.I I;
II
•
0 0 0
0 0 D
o 0 0 4----------------------.qo 0 mlar .. ...................................... mlim
D
Typical AV Chip Layout, Typical UHB Chip Layout,
Single Column Structure " External 110/ Double Column Structure
Figure 1-4. Channeled Gate Array Chip Structure
Basic Cell (Pair)

I II I I I I I I I I I I
f- II -
t::~
f-
. . . '7 -
~
~
0 --
. ---
r0-
--------- 0
o
0
o
r0-
r0- o
r0-
r0-
---------
o
0
o
0
--
~ 0
-
~
0
~ Double Column
0
f-
f-
0
0 ....
;-
~ I I I I I I I I I I I I I
External 110 Cell
Typical Channelless Gate Array Chip Layout,
Double Column Structure wtth No Wiring Channels
Figure 1-5 Channelless Gate Array Chip Structure
Larger gate arrays depart from the fundamental layout scheme by partitioning the basic cell matrix into
four blocks. In some instances the designer may define the size of each block within certain limitations,
while in other cases the block size is fixed. The purpose of chip partitioning is to improve speed
performance by controlling wire length. Each block can be looked at as a small gate array, with four such
gate arrays inside one package. (Smaller arrays exhibit less delay than larger ones.) In the AU and CG21
technologies, a block can be devoted to RAM or ROM for special applications requiring memory.
1-8
1.4 Fujitsu'S CMOS Gate Arrays

Fujitsu's channelless CMOS gate arrays are described in detail in the data sheet that follows at the end of
this chapter. Complete information on Fujitsu's channeled CMOS gate array families is provided in a
separate data book.
All offer the same high reliablility, fast turnaround on design, simplified customer interface, full support by
Fujitsu ViewCAD system design software if requested, full design support on other major CAE
workstations, and a wide variety of packaging options.
The number of gates in relationship to the processing speed of each new CMOS technology is shown in
Figure 1--6. Figure 1-7 shows in tabular form the equivalent gate count for each technology family.
Gate Delay
(in ns/gale)
r------------------------------------------------,5ooK
III
10~------------------------------~~~----------~100K
r-------------------~~~~------~~~------_iOK
O.IL-~~~~~~~~~~~-L~~~~~~~~~~~~IK
1975 1980 1985 1990 1992

Gale Length Year of Production Start Gate Count
(in microns) (Gates/Chip)
• = Gale Count
o = Gate Length (in microns)
• = Gate Delay (in nslgate)
Figure 1--6. Equivalent Gate Count vs. Processing Speed,

Fujitsu CMOS Gate Array Technologies
1-9
Fujitsu CMOS Products CMOS Channelless Gate A"ays
Increasing Gate
Count
100K : : :I~: C-100KAU CG21104
11;:::1 11
1'[111
7SK ::::::::: C-7SKAU CG217S3
[11'\1 111
SOK ,::::,1 11 C-SOKAU CG21S03

40K :I I: :~ C-40KAU CG21403
30K ::::1:::: C-30KAU CG21303
11111'111
20K C-20KAU CG21203'
111 ::,1 11
1SK :::,:::::
C-1SKAU CG211S3'
12K 1111'11111
C-12000UHB
::::,::::
1':::,111
10K C-10KAU CG211 03'
C-8000AV C-8700UHB
8K 1111':::1
111'\1111
C-6600AV
6K 1111:11111
1111'111
C-6000UHB
SK 1111'11111
C-SOOOAV
11111'111
C-4100UHB
4K ::::::::: C-4002AVM
';1';:,1 11 C-3900AV
:1 1 ~: 1
3K 1111'[1111
C-3201AVM C-3000UHB
1111\111
11111'1111
11111~11
11111,111
2K 11111',11 C-2000AVB/L C-2200UHB
IIII~IIII
11111'111
11111[111
C-1600AVB/L C-1700UHB
IIII111111
11111'111
C-1S02AVM
1111'[111
IIIIIII111
lilll:,111 C-1200AVM C-1200UHB
1K 1111;1111
liI',111
11111'1111
C-8S0AVB/L C-830UHB
800 1111111~1
11111'1111
C-S40AVB/L C-S30UHB
SOO 1111:1111
1111,111
C-3S0AVB/L C-330UHB
300 ::::::11:
Increasing
Speed
AVL Version UHB Version AU Version
2.9 ns/gate 0.9 ns/gate 0.8 ns/gate CG21 Version
(Sea of Gates) 0.37 nslgate
AV/AVB/AVM Version
1.4 ns/gate (Sea of Gates)
'planned
Figure 1-7 Equivalent Gate Count, Fujitsu CMOS ASIC Technology Families
1-10
January 1990
OJ
Edition 1.1
PRODUCT PROFILE
FUJITSU
AU Series CMOS Gate Arrays
DESCRIPTION
The AU series of 1.21!m CMOS gate arrays, available in eight device types with from 10Kto 100K gates, achieves the ultra fast
speed of 0.6 ns per gate. Thanks to the channel·free structure of the AU gate array, AU basic cells can be used for logic cells,
memory cells, orwiring area in order to implement the desired functions. The full utilization of the array surface and the three-layer
metal interconnect technology produce a 75 percent maximum gate usability ratio.
The logic and 110 cells forthe AU series are functionally compatible with Fujitsu's UHB series of gate arrays as well as with the new
CG21 arrays to simplify upgrading. User-specifiable RAM and ROM configurations are also available. These gate arrays facilitate
the implementation of large-scale devices such as computer and graphic processors on single chips.
•
FEATURES
1.2 micron CMOS sea-of-gates technology
-3 layer metal interconnect for C30KAU to Cl OOKAU
-2-layer metal interconnect for C30KAU to C20KAU
Ultra high speed
- 0.8 nslgate for 2-input NAND
- 0.6 nslgate for power 2-input NAND
•
•
High current clock drivers
-Low-skew clock signal distribution
Extensive unit cell library (logic cell, RAM, ROM)
-Unit cells functionally compatible with Fujitsu's UHB
gate array series and new CG21 series
Automatic test pattern generation optional
..
• High basic cell usage • On-chip pull-uplpull-down resistors
- 75% maximum for logic with RAMIROM • High pin count plastic and ceramic packages
- 50% maximum for logic only • High-density RAM and ROM compilers
• High sink current capability - up to 18K bit RAM compilation
- sink current up to 24 mA - up to 64K ROM compilation
• Minimum delay clock buffer true option
PRODUCT FAMILY
BCs on Chip Max

Device
Part (2-inpul gale Usable BCs Signal
Number
+4 N-ch Tr) I/O
C-l0KAU MB637xxx 10,224 108
C-15KAU MB636xxx 15,486 75% max. for 138

Logic with
RAM,ROM
C-20KAU M8635xxx 20,876 155
50% max. for

C-30KAU M8634xxx 31,500 178
Logic only
C-40KAU M8633xxx 41,184 (Preliminary 220

values, 10 be
C-50KAU MB632xxx 52,164 upgraded) 245
C-75KAU M8631 xxx 75,140 300
C-l00KAU MB630xxx 102,144 332

Corner of 100KAU after metallization
Copywr~e © 1990 by FUJITSU LIMITED and Fujitsu Microelectronics. Inc
1-11
AU Series
ELECTRICAL CHARACTERISTICS
ABSOLUTE MAXIMUM RATINGS1

Rating Symbol Minimum Maximum Unit
Supply Vo~age Voo Vss·~·5 6.0 V
input Voltage V, Vss·~·5 Voo +0.5 V
OutputVo~e Vo Vss·~·5 Voo +0.5 V
Storage Temperature Ceramic -65 +150

Plastic TIIg -40 +125 °C
Temperature Under Bias Ceramic -40 +125

Plastic Tbloa -25 +85 °C
Notes: 1Permanent device damage may occur if absolute maximum ratings are exceeded. Functional operation should be
restricted to the condnions as detailed in the operation sections of the data sheet. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
'Vss * 0 V.
RECOMMENDED OPERATING CONDITIONS

Paramatar Symbol Minimum TYpical Maximum Unit
Supply Vo~age Voo 4.75 5.0 5.25 V
Input High Voltage for Normal Input V'H 2.2 - - V
Input Low Voltage for Normal Input V'l - - 0.8 V
Input High Voltage for CMOS Input VIH Voox 0.7 - - V
Input Low Voltage for CMOS Input V'l - - Voox 0.3 V
Operating Temperature TA 0 - 70 °C
CAPACITANCE (TA =25°C, VDD =VI =VO, F =1 MHZ)

Parameter Symbol Minimum TYpical Maximum Unit
Input Pin Capacitance C'N - - 16 pF
Output Pin Capacitance CaUl - - 16 pF
1/0 Pin Capacnance Coo - - 16 pF
1-12
AU Series
ELECTRICAL CHARACTERISTICS (Continued)
DC CHARACTERISTICS
(Recommended Operating Conditions unless otherwise noted)
Parameter Symbol Condition Minimum Typical Maximum Unit
Power Supply Current lcos Steady State1 - - 0.2 rnA
Output High Vonage for
Normal Output (101. =3 mAl Voo 100 --2 mA 4.0 - Vee V
Output High Vonage for Driver Output

(10\. = 12 mAl Voo 100 _-4 mA 4.0 - Vee V
Output Low Voltage for

Normal Output VOL 100 -3.2mA Vss - 0.4 V
Output Low Vonage for

Driver Output VOl. IoH -12.0 mA Vss - 0.4 V
Input Hi~h Voltage for

Normal nput
VIH - 2.2 - - V
Input Low Voltage for

Normal INput
VIL - - - O.S V
In~ut High Voltage lor

C OS Input
VIH - Vee x 0.7 - - V
In~ut Low Vonage for

C OS Input
VIL - - - Voox 0.3 V
Input Leakage Current III VI - OV-Voo -10 - 10 IlA

3-state
Input Leakage Current ILZ
VI-OV-Voo
-10 - 10 IlA
Input Pull-up/Down Resistor Rp VIH =Voo 100
25 50 kQ
VOL - Vss
Note: lV IH _ Voo. V IL • Vss • and RAM inactive.
AC CHARACTERISTICS
Rating Symbol Minimum Maxlmum2 Unit
tpLH
Propagation Delay Time
tPHL
tpZl.
Enable Time (Typ) x 0.40 1 (Typ) x 1.60 1 ns
IpZH
tpLZ
Disable Time
tpHZ
Notes: lValues lor post-layout simulation. with O°C < Tj s 70°C (Tj: Estimated Junction Temperature). 0.35 and 1.70 are used
for pre-layout simulation.
2'fhis value is determined by the junction temperature. which is a function of power dissipation. thermal resistance of
the selected package. and operating environment (power supply voltage and ambient temperature). Please refer to
Chapter 5 of this section or the Design Manual for the details.
1-13
AU Series
CHIP STRUCTURE
CHIP LAYOUT
On the CG21 gate array chip, the basic cells are configured in a matrix arranged in double parallel columns with no wiring chan-
nel between the double columns. External I/O cells are located around the basic cell matrix. Interconnection wires go over and
across the columns of basic cells.
Basic Cell (Double Column

I III I I I I I I I I I I
The structure of each device type is as follows:
- II III ,-
C-10KAU 48 rows x 213 columns = 10,224BC - ~~ .....
f.o-~ .....
··· r-
'-
C-15KAU 58 rows x 267 columns = 15,486 BC
'- '-
C-20KAU
---------
····
68 rows x 307 columns = 20,876 BC r-
C-30KAU 84 rows x 375 columns = 31,500 BC
~ r-
~ ~
C-40KAU 96 rows x 429 columns = 41,184 BC ~
~ ····
~
~
C-50KAU
C-75KAU
108 rows x 483 columns
130 rows x 578 columns
= 52,164 BC
= 75,140 BC
~
~
---------
··· ~
~
C-l00KAU 152 rows x 672 columns = 102,l44BC ~

~ ··~
~
Double
Column
~ 1111111111111
External I/O Cell
CELL STRUCTURE
The basic cell is the structural element of the AU gate arrays. One basic cell consists of two pairs of P-channel and N-channel
transistors and four small N-channeltransistors. One basic cell can form a 2-input gate, 1 b~ for RAM or 4 bits for ROM.
r-------, r-------,
_ _ _ _ _ _ _ ..J I
Basic Cell #1 Basic Cell #2
1-14
AU Series
UNIT CELL AC CHARACTERISTICS

(Representative Values for Respresentative Unit Celis)
Propagation Delays (In ns)
Unit Cell Unit Cell Equivalent Out~ut NOI (Fan-out)
Function Name Gate Count Transtlon
1 2 3 4 5
Inverter V1N 1 L~H 0.58 0.83 1.08 1.29 1.48
H~L 0.55 0.72 0.86 0.97 1.07
Power Inverter V2B 1 L~H 0.39 0.52 0.66 o.n 0.87
H~L 0.39 0.52 0.66 0.74 0.80
2-lnput NAND N2N 1 L~H 0.65 0.90 1.15 1.36 1.55
H~L 0.75 0.96 1.17 1.34 1.51
Power 2-lnput NAND N2B 3 L~H 1.07 1.20 1.34 1.45 1.55
H~L 1.22 1.28 1.34 1.39 1.43
Power 2-lnput NAND N2K 2 L~H 0.49 0.62 0.76 0.87 0.97
H~L 0.53 0.67 0.81 0.91 1.00
3-lnput NAND N3N 2 L~H o.n 1.02 1.27 1.48 1.67
H~L 0.95 1.24 1.53 1.n 1.99
Power 3-lnput NAND N3B 3 L~H 1.22 1.35 1.49 1.60 1.70
H~L 1.44 1.50 1.56 1.61 1.65
2-lnputNOR R2N 1 L~H 0.94 1.38 1.82 2.19 2.53
H~L 0.60 0.75 0.89 1.00 1.10
Power 2-lnput NOR R2B 3 L~H 1.28 1.41 1.55 1.66 1.76
H~L 1.08 1.14 1.20 1.25 1.29
Power 2-lnput NOR R2K 2 L~H 0.66 0.87 1.08 1.25 1.42
H~L 0.50 0.59 0.69 o.n 0.84
3-lnput NOR R3N 2 L~H 1.56 2.19 2.82 3.35 3.84
H~L 0.64 0.81 0.95 1.06 1.16
H~L 1.18 1.24 1.30 1.35 1.39
4-lnputNOR R4N 2 L~H 2.15 2.97 3.79 4.48 5.12
H~L 0.67 0.85 0.99 1.10 1.20
H~L 1.15 1.21 1.27 1.32 1.36
Non-SCAN FD2 7 L~H 1.51 1.64 1.78 1.89 1.99
Power D FF (CK~ 0) H~L 1.60 1.75 1.90 1.99 2.05
SCAN l-Input D FF SDA 12 L~H 2.74 2.87 3.01 3.12 3.22

wnh Clock Inhibit (CK ~ 0) H~L 2.59 2.72 2.86 2.93 2.97
Note: TYPICal at Voo = 5 V and TJ = 25°C
Estimated metal loading for C-30KAU (Level 4. Main Block)
1-15
AU Series
INPUT BUFFER AC CHARACTERISTICS
Propagation Delays
Unit Cell Unit Cell Equivalent out~ut NDI (Fan-out)
Function Name Gate Count Transtlon
1 2 3 4 5
Input Buffer 12B 4 L~H 0.93 0.99 1.05 1.10 1.14
(True) H~L 1.55 1.61 1.67 1.72 1.76
Clock Input Buffer ILB 6 L~H 1.82 1.84 1.86 1.87 1.89
(True) H~L 2.48 2.50 2.52 2.53 2.55
Note: TYPical at Voo = 5 V and TJ = 25°C
Estimated metal loading for C-30KAU
OUTPUT BUFFER AC CHARACTERISTICS

Propagation Delays
Unit Cell Unit Cell Equivalent Output
Function Name Gate Count Transition CL =10pF CL =20pF CL = 30 pF CL = 40 pF CL =50pF
Output Buffer 02B 2 L~H 1.93 2.40 2.87 3.34 3.81
(True) H~L 2.56 3.59 4.62 5.65 6.68
Power Output Buffer 02L 2 H~H 2.18 2.50 2.82 3.14 3.46
(True) H~L 2.37 2.71 3.05 3.39 3.73
3-state Output Buffer 04T 4 L~H 2.79 3.26 3.73 4.20 4.67
(True) H~L 3.63 4.66 5.69 6.72 7.75
Power 3-state 04W 4 L~H 3.02 3.34 3.66 3.98 4.30
Output Buffer (True) H~L 5.15 5.51 5.87 6.23 6.59
NOTE: TYPical at V = 5 V and TJ = 25°C
Estimated metal loading for C-30KAU
1-16
AU Series
AU CMOS Gate Array Package Options
DEVICE NAME
Package Package
Nama Material Co10KAU Co15KAU Co20KAU c-30KAU C-40KAU C-SOKAU Co75KAU Co100KAU
PGA-64 Ceramic a a a - - - - -
PGA-88 Ceramic a a a - - - - -
PGA-l35 Ceramic a a a a a a a a
PGA-179 Ceramic - - a a a a a a
PGA-208 Ceramic - - - a a a a a
PGA-256 Ceramic - - - - a a a a
PGA-299 Ceramic - - - - - 0 0 0
PGA-321 Ceramic - - - - - - 0 0
PGA-361
PGA-401
OFP-64
Ceramic
Ceramic
Plastic a
-
-
-
-
a a
-
-
-
-
-
-
-
-
-
-
-
0
-
-
0
0
-
III
OFP-80 Plastic a a a - - - - -
OFP-l00 Plastic a a a - - - - -
OFP-120 Plastic a a
•a a a - - -
OFP-160 Plastic - a a a - - -
PLCCo68
PLCC-84
SDIP-64
Plastic
Plastic
Plastic
a
a
a
a
a
a
•
a
a
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Nota: a E Available
o _ Under Development
- - Not Available
1-17
AU Series
AU CMOS Gate Array Package Descriptions
Pad. for
Decoupllng 9JA(TYP)
(C°1W)
Package Malerlal Cavity Pin Arrangemenl Capacitor Devk:e alOmla al3 mi.
C-2OKAU 80 50
SDIP-a4 Plastic None 70 mil Lead Pitch None C-15KAU 80 55
C-l0KAU 85 60
C-2OKAU 50 35
PLCC-OS Plastic None 70 mil Lead Pitch None C-15KAU 55 40
GuO-wing C-l0KAU 60 40
C-20KAU 50 35
PLCC-a4 Plastic None 30 mil Lead Pitch None C-15KAU 50 35
Gull-wing C-l0KAU 55 40
C-2OKAU 80 55
OFP-a4 Plastic None 100 mil Lead Pitch None C-15KAU 85 60
C-2OKAU 80 55
OFP-aO Plastic None O.S mm Lead Pitch None C-15KAU 85 60
C-2OKAU 80 55
OFP-l00 Plastic None 0.65 mm Lead Pitch None C-15KAU 85 60
GuU-wing C-l0KAU 90 65
OFP-12O Plastic None O.S mm Lead Pitch None C-40KAU

GuO-wing C-30KAU 65 40
C-20KAU 70 50
C-15KAU
C-l0K
OFP-I60 Plastic None 0.65 mm Lead Pitch Yes C-40KAU

Gull-wing C-30KAU 59 39
C-2OKAU 70 50
C-15KAU
C-l0KAU
P~4 Ceramic Up 100 mil Pin Pitch Yes C-15KAU 40 20
Through hole C-2OKAU
C-l0KAU
PGA-aS Ceramic Up 100 mil Pin Pitch Yes C-15KAU 40 20
Through hole C-2OKAU
PGA-I35 Ceramic Up 100 mil Pin Pitch Yes All AU 30 15

Through hole
C-30KAU- 25 13
PGA-I79 Ceramic Up 100 mil Pin Pitch Yes C-l00KAU
Through hole
C-20KAU 30 15
PGA-208 ~ramic Up 100 mil Pin Pitch Yes C-30KAU- 23 12

Through hole C-l00KAU
1-18
AU Series
AU CMOS Gate Array Package Descriptions (Continued)
Pad. for
Decoupllng OJA(TYP) (C°1W)
Packaga Material Cavity Pin Arrangement Capacitor Device atOmi. at3 mi.
PGA-256 Ceramic Up 100 mil Pin Pitch Ves C-30KAU-
Through hole C-l00KAU 19 9
PGA-299 Ceramic Down 100 mil Pin Pitch Ves C-50KAU- 19 9

PGA-321 Ceramic Down 70 mil Stagger Ves C-75KAU- 22-24 11-13

PGA-361 Ceramic Down 70 mil Stagger Ves C-75KAU- 22-24 11-13

PGA-401 Ceramic Down 70 mil Stagger Ves C-l00KAU 22-24 11-13

Through hole
1-19
AU Series
FUNCTIONAL INDEX OF UNIT CELL LIBRARY

Note: The load unit (Iu) Is a normalized loading unit d capacitance representing the inpulload of an inverter without metal
interconnection.
1-20
AU Series
FUNCTIONAL INDEX OF UNIT CELL LIBRARY (Continued)
10
1-21
AU Series
1-22
AU Series
.\ ti "'. ":;::.
Unit Cell Basic Drive Bit
Name Type Description Cell. (Iu) SeIseR Output Width
P24" 2:1 n",,, !lAIAcln, 12 36 S.XS a 4.

T2E 2:1 Dual Selector 5 18 S xa 2
T2F 2:1 Selector 8 18 S xa 4
T2B" 2:1 Selector 2 18 S,XS xa 1
T2C" 2:1 Selector 4 18 S,xs xa 2.
T2D" 2'1 Selector 2 14 SXS XC
T5A" 4'1 SAlector 5 g S XS XO
V3A" 1:2 Selector 2 14 S.XS xa 1
V3B" 1:2 Dual Selector 4 14 S.XS xa 2
" These are I gate devices whose outputs can be tied because they call be inhib~ed w~h ' selects,
),. .,·.'·.<i.,> < . i < . }) ,. . '·..i< i ( ?
Unit Cell
Name Type Description
Basic
Cells
Drive
(Iu)
Active Level
Outputs Enable
10
DE2 2:4 Decoder 5 18 low -
DE3 3:8 Decoder 15 14 Low -
.-
DE4 2:4 Decoder 8 14 low
-
low
-
DE6 3:8 Decoder 30 18 Low 1 High
2 Low
Unit Cell Basic Drive

~
Name Type Description Cells (Iu) Bus Size Enable
.E!.11 l-bi-,.Bus Driver 5 36 1 low

B21 2-bit Bus Driver 9 36 2 Low
841 4-bit Bus Driver 17 36 4 Low
B12 I-bit Block Bus Driver 7 72 1 Low
B22 2-bit Block Bus Driver 13 72 2 Low
842 4-bit Block I
..\. < .. '.' .. "ii\ •. ....,.............
Unit Cell Basic
Name Description Cell. Drive (Iu) En.ble Bit. Output Clear
YL2 Data Latch with TM 5 36 High 1 a
YL4 Data Latch Wl1ll TM 14 36 High 4 (.;I -
LTK Data Latch 4 18 Low 1 a,xa Async
LTL Data Latch with Clear 5 18 Low 1 a,xa Async
LTM Data Latch with Clear 16 18 Low 4 a.xa -
LTI S-R Latch with Clear 4 18 Low 1 a,xa Async
LT4 Data Latch 14 18 Low 4 a.xa -
Note: V-type latches incorporate inhib~ inputs and transparent mode (TM) to facilitate scan implementation.
1-23
AU Series
FJD Non-ScanPower J-K Flip-Hop 12 36 a,xa
Note: Synchronous flip-flops may be constructed by adding a simple AND gate (such as N2P) to the input of a flip-flop to
create a synchronous clear.
1-24
AU Series

, .i>., · · . i < , }
•\i .i
~I: Basic Drive Carry Upl

Name Description Cell. (Iu) Bit. Outputa' Load Clear Enable In Down
~~:::;~;;';;:e~~= ~~~i
SC72
62 36 4 Sync - Low High Up
~~.::'.::;;~;;;;:i~ ~o~~i
SC82
66 36 4 Sync - High Low Down
11· Non-Scan Flip-nap for Counter 18 - a,xa - - - - -
C41 Non-Scan Bin~ounter
24 18 4 a,(AI Async Up
C42
~~n-scan Bi~~unter 32 18 4 ,Async Up
a
C43
Non-Scan Bi~~unter
48 18 4 a,CO(S) Sync Async High High Up
C45
C4,
Non-Scan Binary Synchronous
Counter
Non-Scan Binary : Counter
48
68
18
18
4
4
a,co
a, CC
Sync
Async
iSync
!-
High
Low
High
Low
Up
Ip/Down III
'?_; .
SC432 Scan: , Binary Counter 59 18 4 a,co Sync I Async High High Up
S~· Scan ,Binary Counter 78 18 4 a,co Async 1- Low Low Up/Down
•
Notea: 1. ~Al indica,,! !he
.~~~::\~c .
,t,jn;.L il!.~i~r.'~~~~1!,~~~iiv8
'~~;-n
Basic
:C~~'
Drive Bit
non-Scan counters CDR = 18 lu
"'iii,;,/<', ......,..'
.,.···..ic .•· ·'.'• • "• ·"i·'·,i
Clock
Description Cells (Iu) Width Load Outputs Polarity
Name
FSI Serial-in Parallel-out Shift
Register 18 16 4 "'. O-Parallel Neg
FS2 Shift Re9iste~ :~
30 16 4 Sync-High O-Parallel Neg
FS3 Shift Register ,::d 34 18 4 Async-Low O-Parallel Pas
SRI Serial-in Parallel-out Shift
Register with Scan 36 36 4 Serial-In only O-Parallel Pas
~""':""""""""" '.' ····.ii . ,. ' '. ','..'.i ',;f '.•.• .• . . "',:< .•'/</. "')" .' '.' ,',', . " i , » :.• '
Unit Cell Basic Drive Bit
Name Cella (Iu) Width Outputs Carry In
MC4 Magnitude 1&~~) A>B,A=B,A<B A~R,A=RAIR
AlA I-bit Hall Adder 5 36 1 S,CO -

A1N I-bit Full Adder 8 18 1 S,CO CI
A2N 2-bit Full Adder 16 14 2 S,CO CI
A4H 4-bit Binary Full Adder wlFast Carry 48 1~~ 4 S,CO CI
PE5 Even Parity 12 36 5 EVEN,OUO -
POS Odd Parity' 12 36 5 ODD, EVEN -
PE8 Even Parity 18 18 8 EVEN.OUO -
P08 Odd Parity 18 18 8 ODD,EVEN -
PE9 Even Parity 22 18 9 EVEN,OUO -
P09 Odd Parity 22 18 9 ODD,EVEN
1-25
AU Series
ILCU IKC with Pull-up Resistance 6 200 CMOS Clock True

ILCD IKC with Pull-down Resistance 6 200 CMOS Clock True
Note: A "U' suffixed to the name of an input buffer indicates pull-up resistance of 501«} (typical) and a "0"
indicates a pull-down resistance of the equivalent value.
1-26
AU Series
III
Example of Open Drain Output
Rpullup (min) =Voo (max) In x Out

ZOI IOL (rated)
o l l
Provides "'-.r'V'I-L_ Out 1 Z H
Wire AND
Internal External
Example Of Open Source Output

Rpulldn (min) = Voo(max) In x Out
Provides ~) o H H
Wire AND ~-..:..:. .-Out 1 Z l
zoo
Internal
1-27
AU Series
Unit
Cell
Name
H6T 3-state Output and Input Buffer a 3.2mA TIL No True

H6TU H6T with Pull-up Resistance a 3.2mA TIL No True
H6TD H6T with Pull-down Resistance a 3.2mA TIL No True
H6W Power 3-state Output and Input Buffer a 12mA TIL No True
H6WU H6W with Pull-up Resistance a 12mA TIL No True
H6WD H6W with Pull-down Resistance a 12mA TIL No True
Interface Input Buffer a 3.2mA CMOS No True

H6CU H6C with Pull-up Resistance a 3.2mA CMOS No True
H6CD H6C with Pull-down Resistance a 3.2mA CMOS No True
H6E Power 3-state Output and
Interface Input Buffer a 12mA CMOS No True
H6EU H6E with Pull-up Resistance a 12mA CMOS No True
H6ED H6E with Pull-down Resistance a 12mA CMOS No True
CMOS True
12mA TIL Yes True

9 12mA TIL Yes True
Interface Input Buffer 9 3.2mA CMOS Yes True

Hacu HaC with Pull-up Resistance 9 3.2mA CMOS Yes True
HaeD HaC with Pull-down Resistance 9 3.2mA CMOS Yes True
Note: A "U· suffixed to the name of a bidirectional buffer indicates a pull-up resistance of son (typical) and a
"0" indicates a pull-down resistance of the equivalent value.
1-28
AU Series

.......
!::l'~lrectI9Q'lllOButfer. (Bp!il~~rcontlnlied /
Unit Input Edge Inpulf
Cell Basic Drive logic Rate Output
Name Description Cella (Iou Level Control Polarity
H8E Power 3-state Output Buffer and
Interface Input Buffer 9 12mA CMOS Yes True
H8EU H8E with Pull-up Resistance 9 12mA CMOS Yes True
H8ED H8E with Pull-down Resistance 9 12mA CMOS Yes True
H8S 3-state Output and Schmitt
Trigger Input Buffer 13 3.2mA CMOS Yes True
H8SU H8S with Pull-up Resistance 13 3.2mA CMOS Yes True
H8SD H8S with Pull-down Resistance 13 3.2mA CMOS Yes True
H8R 3-state Output and Schmitt
Trigger Input Buffer 13 3.2mA TIL Yes True
H8RU H8R with Pull-up Resistance TIL
10
13 3.2mA Yes True
H8RD H8R with Pull-down Resistance 13 3.2mA TIL Yes True
H6TF 3-state Output and Schmitt
Trigger Input Buffer 8 8mA TIL No True
H6TFU H6TF with Pull-up Resistance 8 8mA TIL No True
H6TFD H6TF with Pull-down Resistance 8 SmA TIL No True
H6CF 3-state Output and Input Buffer 8 8mA CMOS No True
H6CFU H6CF with Pull-up Resistance 8 8mA CMOS No True
H6CFD H6CF with Pull-down Resistance 8 8mA CMOS No True
H8TF 3-state Output and Input Buffer 9 8mA TIL Yes True
H8TFU H8TF with Pull-up Resistance 9 8mA TIL Yes True
H8TFD H8TF with Pull-down Resistance 9 8mA TIL Yes True
H8CF 3-state Output and Input Buffer 9 8mA CMOS Yes True
H8CFU H8CF with Pull-up Resistance 9 8mA CMOS Yes True
H8CFD H8CF with PUll-down Resistance 9 8mA CMOS Yes True
H8W2 3-state Output and Input Buffer 8 24mA TIL Yes True
H8Wl H8W2 with Pull-up Resistance 8 24mA TIL Yes True
H8WO H8W2 with Pull-down Resistance 8 24mA TIL Yes True
H8E2 3-state Output and Input Buffer 8 24mA CMOS Yes True
H8El H8E2 with Pull-up Resistance 8 24mA CMOS Yes True
HaEO H8E2 with Pull-down Resistance a 24mA CMOS Yes True
Note: While all outputs are totem-pole type, Open Drain and Open Source types can easily be defined for all
3-state type outputs, which includes all bidirectional buffers.
1-29
AU Series
1-30
January 1990 00
Edition 1.1
PRODUCT PROFILE
FUJITSU
CG21 Series D.8-micron CMOS Gate Arrays
DESCRIPTION
The CG21 series of 0.81JIl1 CMOS gate arrays are currently available in five device types wtth from 30Kto lOOK gates. Three more
0021 arrays, ranging from 10K to 20K gates, are now underdevelopment. These arrays achieve the ultra fast speed of 0.37 ps per
gate. Thanks to the channel-free (sea-of-gates) structure of the 0021 gate array, 0021 basic cells can be used for logic cells,
memory cells, or wiring area in order to implement the desired functions. The full utilization of the array surface and the three-layer
metal interconnect technology produce a 75 percent maximum gate usabiltty ratio.
The logic'llnd I/O cells forthe 0021 series are functionally compatible with Fujttsu's AU, UHB, and CGl 0 series of gate arrays to
simplify upgrading. User-specifiable RAM and ROM configurations are also available. These gate arrays facil~ate the
implementation of large-scale devices such as computer and graphic processors on single chips.
FEATURES
•
•
0.8 micron CMOS sea-of-gates technology
-3 layer metal interconnect
U~ra high speed
•
•
High current clock drivers
-Low-skew clock signal distribution
Extensive unit cell library (logic cell, RAM, ROM)
III
- 0.37 nslgate for 2-input NAND wtth FlO = 2 -Unit cells functionally compatible with Fujitsu's AU,
- 0.55 nslgate for power 2-input NAND wtth FlO = 2 UHB, and CG10 gate array series
• High basic cell usage • Automatic test pattern generation optional
- 75% maximum for logic wtth RAMIROM • On-chip pull-up/pull-down resistors
- 45% maximum for logic only • High pin count plastic and ceramic packages
• High sink current capability • High-density RAM and ROM compilers
- sink current up to 12 mA, 24 mA planned - up to 18K bit RAM compilation
• Minimum delay clock buffer true option - up to 64K ROM compilation
PRODUCT FAMILY
BCs on Chip Max Available Packages'
Part (2-lnput gate Signal
Device Number +4 N-ch Tr) Usable BCa 1/0 Plastic Ceramic
CG21103 MBCG21103xxx" 10,224 108 SDIP-64, OFP-64, ..so, PGA-64, 88, -135
-100, -120, PLCC-68,-84
CG21153 MBCG21153xxx" 15,486 75% max. for 142 SDIP-64, OFP-64, -80
-100, -120, -160, PLCC..s8,-84 PGA-64, -88, -135
Logicwilh
RAM,ROM SDIP-64, OFP-64, ..so,
CG21203 MBCG21203xxx3 20,876 155 -100, -120, -160, PLCC-68,-84 PGA-64, -88, -135, -179
45% max. for
CG21303 MBCG21303xxx 31,500 178 OFP-120, -160 PGA-88, -135, -179, 208
Logic only
OFP-12O, -160
CG21403 MBCG21403xxx 41,184 (Preliminary 220 SOFP-1762 , -208 2 PGA-135, -179, 208, -256
values, to be OFP-12O, -160, -1962 PGA-135, -179, 208, -256,
CG21503 MBCG21503xxx 52,164 upgraded) 245 SOFP-1762 , -2082 -299'
OFP-I962 , -232' PGA-135, -179, 208, -256,
CG21753 MBCG21753xxx 75,140 284 SOFP-1762 , -2082 -299', -321 2 , -361 2
OFP-lgs2, -232' PGA-135, -179, 208, -256,
CG21104 MBCG21104xxx 102,144 332 SOFP-2OS2, -2562 -299, -321 2 , -361, -401 2
'SDIP =Skinny dual In-line package, PGA =Pin grid array, OFP =Quad flat package, PLCC =Plasuc leadless chip carrier, SOFP =Skinny
quad flat package
'Planned
3Under development
Copjwrlle © '990 by FUJITSU LIMITED and FuJlsu Mlaoolactronlcs, Inc
1-31
CG21 Series
ELECTRICAL CHARACTERISTICS
ABSOLUTE MAXIMUM RATlNGS1

Rating Symbol Minimum Maximum Unit
Supply Vo~age VOO Vss2 -O.5 6.0 V
Input Voltage VI Vss2 -O.5 Voo +0.5 V
Output Voltage Vo Vss2 -O.5 Voo +0.5 V
Ceramic ~5 +150
Storage Temperature Tstg °C
Plastic -40 +125
Ceramic -40 +125
Temperature Under Bias
Plastic Tbl.. -25 +85 °C
Notes: 'Permanent device damage may occur ff absolute maximum ratings are exceeded. Functional operation should be
restricted to the conditions as detailed in the operation sections of the data sheet. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
2Vss = 0 V.
RECOMMENDED OPERATING CONDITIONS

Parameter Symbol Minimum Typical Maximum Unit
Supply Vo~age Voo 4.75 5.0 5.25 V
Input High Vo~age for Normal Input VIH 2.2 - - V
Input Low Vo~age for Normal Input VIL - - 0.8 V
Input High Vo~age for CMOS Input VIH VooxO.7 - - V
Input Low Vo~age for CMOS Input VIL - - VODX 0.3 V
Operating Temperature TA 0 - 70 °C
CAPACITANCE (TA = 25°C, Voo = VI = VO, F = 1 MHZ)

Parameter Symbol Minimum Typical Maximum Unit
Input Pin Capacitance CIN - - 16 pF
Output Pin Capacitance CaUT - - 16 pF
1/0 Pin Capacitance ClIO - - 16 pF
1-32
CG21 Series
ELECTRICAL CHARACTERISTICS (Continued)

DC CHARACTERISTICS
Parameter Symbol Condition Minimum TYPical Maximum Unit
Power Supply Current loos Steady State 1 - - 0.2 mA
Output High VoHage for
Normal Output (1oL = 3 mA or 8 mAl
VOH IOH --2 mA 4.0 - Voo V
Output High VoHage for Driver Output

(loL = 12 mAl
VOH IOH --4mA 4.0 - Voo V
Output Low VoHage for 1ot.-3.2mA

Normal Output (1oL = 3 mA or 8 mAl Va. or8mA Vss - 0.4 V
Output Low VoHage for

Driver Output (IoL = 12 mAl Va. IOL -12.0 mA Vss - 0.4 V
Input HiVrh Voltage for

Normal nput l'IH - 2.2 - - V
Input Low Voltage for

Normal INput
Input High Voltage for
V1L
V1H
-
-
-
Voo x 0.7
-
-
0.8
-
V
V
10
CMOS Input
In~ut Low VoHage for
C OS Input
V 1L - - - Voox 0.3 V
Input Leakage Current III VI-OV-Voo -10 - 10 IJ.A

3-state
Input Leakage Current ILZ
VI-OV-Voo
-10 - 10 IJ.A
Input PUIl-uptDown Resistor Rp VIH - Voo 25 50 100 W
VOL - Vss
Note: 'V1H = Voo, V1L = Vss, and RAM inactive.
AC CHARACTERISTICS
Rating Symbol Minimum Maximum' Unit

tpLH
Propagation Delay Time
tpHL
tpZL
Enable Time (Typ) x 0.402,3 (Typ) X 1.552 ns
IpZH
(Typ) x 1.603
tpLZ
Disable Time
IpHZ
Notes: 'This value is determined by the junction temperature, which is a function of power dissipation, thermal resistance of
the selected package, and operating environment (power supply voHage and ambient termperature).
2Values for post-layout Simulation, w~h Tj s 70°C (Tj: Estimated Junction Temperature.) 0.35 and 1.70 are used for
pre-layout simulation.
3Values for post-layout simulation with Tj oS 60°C. 0.35 and 1.65 are used for pre-layout simulation.
1-33
CG21 Series
CHIP STRUCTURE
CHIP LAYOUT
On the 0021 gate array chip, the basic cells are configured in a matrix arranged in double parallel columns with no wiring chan-
nel between the double columns. External va cells are located around the basic cell matrix. Interconnection wires go over and
across the columns of basic cells.
Basic Cell (Double Column)
I II I I I I I I I I I I
The structure of each device type is as follows: - ~~ r-
r-
- f.:-f-'-
-
--------- .
CG211 03 48 rows x 213 columns z 10,224BC
, r-
0021153 58 rows x 267 columns • 15,486BC - r-
- r-
CG21203 68 rows x 307 columns • 20,876 BC - r-
CG21303 84 rows x 375 columns • 31,500 BC - r-
- r-
CG21403 96 rows x 429 columns .41,184BC - --------- r-
0021503 108 rows x 483 columns • 52,164 BC - r-
- r-
CG21753 130 rows x 578 columns .75,140BC
- r- 130uble
CG21104 152 rows x 672 columns = 102,144BC - r- Column
I I I I I I I I I I LJ I
"
~xternal va Cell
CELL STRUCTURE
The basic cell is the structural element of the 0021 gate arrays. One basic cell consists of two pairs of P-channel and N-channel
transistors and four small N-channel transistors. One basic cell can form a 2-input gate, 1 bit for RAM or 4 bits for ROM .
.... -------, .... -------,
Basic Cell #1 Basic Cell #2
1-34
CG21 Series
Package Options
DEVICE NAME
Package Package CG211 03 Number Number
C~5~~ C~1~~
'7:0~~ '7;o~ '7;;~~ C(~~~~-:-'
CG21403
Name Malerlal (10K) 20K (40K) OfVDD' ofVss'
PGA-64 Ceramic
• • • - - - - - 2(2) 4(2)
PGA-88 Ceramic
• • • 4(4) 6(4)
PGA-135 Ceramic
•- •- • • • • • • 8 12
PGA-179 Ceramic
• • • • • • 8 16
PGA-208 Ceramic - - - • • • • • 12 18
PGA-256
PGA-299
Ceramic
Ceramic
-
-
-
-
-
-
-
- -
• • • • 16
21
20
21
0 0 0
PGA-321 Ceramic - - - - - - 0 0 20 32
PGA-361 Ceramic - - - - - - 24 36
PGA-401
OFP-64
Ceramic
Plastic
-
•
-
•
-
•
-
-
-
-
-
-
-
-
0
-
0
0 28
2 (2)
40
4(2) III
OFP-80 Plastic
• • • -
-
- - -
-
-
-
2(2) 6(4)
OFP-100 Plastic
• • • - -
-
4(4) 8(4)
OFP-120 Plastic
•
- • • • • -
- -
-
-
6(4) 12(8)
OFP-l60 Plastic
-
• • •
-
• 8(6) 14(12)
OFP-l96 Plastic -
- -
-
- -
0 0
• 10 18
OFP-232
OFP-176
Plastic
Plastic
-
- - - - 0 0
0
0
• 14
8
20
16
OFP-208 Plastic - - - - 0 0 0 0 12 18
OFP-256 Plastic - - - - - - - 0 16 20
PLCC-68 Plastic • • • - - - - - 2(2) 4(2)
PLCC-84 Plastic
• • • - - - - - 4(2) 6(4)
SDIP-64 Plastic
• • • - - - - - 2 (2) 4(2)
Notes: • = Available
o = Under Development
- = Not Available
'The values in parentheses show the number of Voo and Vss pins provided in the a~ernate pin assignment (U-type) packages,
which have fewer VooNss pins than in normally configured packages.
1-35
CG21 Series
Package Descriptions
Pad. for
Decoupllng 8JA(TYP)
(C°1W)
Package Material Cavity Pin Arrangement Capacitor DevIce atOml. at3 mi.
CG21103' 80 50
SDIP~ Plastic None 70 mil Lead Pitch None CG21153' 80 55
CG21203' 85 60
CG21103' 50 35
PlCC-68 Plastic None 70 mil Lead Pitch None CG21153" 55 40
Gull-wing CG21203' 60 40
CG21103' 50 35
PlCC-84 Plastic None 30 mil Lead Pitch None CG21153' 50 35
CG21103' 80 55
OFP-64 Plastic None 100 mil Lead Pitch None CG21153' 85 60
CG21103' 80 55
OFP-80 Plastic None 0.8 mm Lead Pitch None CG21153' 85 60
CG21103' 80 55
OFP-l00 Plastic None 0.65 mm lead Pitch None CG21153' 85 60
OFP-l20 Plastic None 0.8 mm Lead Pitch Nona CG21303

Gull-wing CG21403 65 40
CG21503
CG21103'
CG21153' 70 50
CG21203'
OFP-l60 Plastic None 0.65 mm lead Pitch None CG21303 59 39

Gull-wing CG21403
CG21503
CG21153 70 50
CG21253
OFP-l96" Plastic None TBD None CG21503 TBD TBD

GuO-wing CG21753
CG21104
OFP-232" Plastic None TBD None CG21753 TBD TBD

Gull-wing CG21104

Gull-wing CG21503
CG21753

Gull-wing CG21503
CG21753
CG21104

Gull-wing
Conttnued on next page

• planned device
"package under development
1-36
CG21 Series
Package Descriptions (Continued)
Pad. for
Dacoupllng 9JA{TYP) (C°1W)
Packaae Malerial Cavltv Pin Arranaemenl Capacllar Device alOm/s al3 mi.
CG211 03'
PGA~4 Ceramic Up 100 mil Pin Pitch Yes CG21153' 40 20
Through hole CG21203'
CG21103'
PGA-88 Ceramic Up 100 mil Pin Pitch Yes CG21153' 40 20
CG21303
AIICG21
PGA-I35 Ceramic Up 100 mil Pin Pitch Yes 30 15
Through hel,\
CG21203' 30 15
10
CG21303 25 13
PGA-I79 Ceramic Up 100 mil Pin Pitch Yes CG21403
Through hole CG21503
CG21753
CG21104
PGA-208 Ceramic Up 100 mil Pin Pitch Yes CG21303

Through hole CG21403 23 12
CG21503
CG21753
CG21104
PGA-256 Ceramic Up 100 mil Pin Pitch Yes CG21403

CG21753
CG21104
PGA-299 Ceramic Down 100 mil Pin Pitch Yes CG21503

CG21104
PGA-321 Ceramic Down 70 mil Stagger Yes CG21753 22-24 11-13



Through hole
1-37
CG21 Series
FUNCTIONAL INDEX OF UNIT CELL LIBRARY

Note: The load unn (Iu) is a normalized loading un~ of capacitance representing the input load of an inverter without metal
interconnection.
...../
jpY~!1~~~P~ Bl}~i~rf:'amny . ......
.....·.t./< Ji.. . > ••
...
. .... ... ... . ........)
Unit Cell
Name Description Basic Cells Drive (Iu) Polarity
V1N Inverter 1 18 Neg
V2B Power Inverter 1 36 Neg
BIN True Buffer 1 18 Pos
BD3 True Delay Buffer (>5ns) 5 18 Pos
BD4 Delay Cell (>4ns) 4 6 Pos
BD5 Delay Cell (>10ns) 9 18 Pos
BD6 Delay Cell (>22 ns) 17 18 Pos
. . . ...C········ ..... •.................. :. . :/. >..> ..•. .. ..
.CI99kQ~ffer f~~iIY ..........•.
.i
... :. .
Unit Cell
Name Description Basic Cells Drive (Iu) Polarity
K1B True Clock Buffer 2 36 Pos
K2B Power Clock Buffer 3 55 Pos
~B Gated Clock (ANOI Buffer 2 36 Pos
K4B Gated Clock (OR) Buffer 2 36 Pos
K5B Gated Clock (NAND) Buffer 3 36 Neg
KAB Block Clock OR) Buffer 3 55 Pos
KBB Block Clock (OR x 10) Buffer 30 55 Pos
KDB Block Clock (OR x 10) Buffer 32 55 Pos
KEB Block Clock Buffer 23 55 Pos
V1L Inverting Clock Buffer 2 55 Neg
........ .......
NANDJEamUy .........>.... ··i
Unit Cell
Name Description Basic Cells Drive (Iu)
N2N 2-input NAND 1 18
1\J2B Power 2-input NAND 3 36
N2K Fast Power 2-input NAND 2 36
N3N 3-input NAND 2 14
N3B Power 3-input NAND 3 36
N4N 4-input NAN 0 2 10
NCB Power 12-input NAND 10 36
NGB Power 16-input NAND 11 36
1-38
CG21 Series
Unit Cell
Name Baalc Cella Drive (Iu)
R2N 2-inpulNOR I 14
R2B Power 2-inpul NOR 3 36
R2K Power 2-inpul NOR 2 36
R3N 3-inpu1NOR 2 10
R4N 4-inpu1NOR 26
R4B Power4-inpul NOR 4 36
R6B Power 6-inPlII NOR 5 36
RCB Power 12-inpul NOR 10 36
RGB Power l6-inpul NOR
/i
Un11Ce11
Name Descrlpllon Baste Cells Drive (Iu)
N2P Power 2-inpul AND 2 36
N3P lAND 3 36
N4P -u...., .-", .... IAND 3 36
Name Description Basic Cells Drive (Iu)

R2P Pnwor ~_;n'" 'lOR 2 36
R3P lOR 3 36
R4P lOR 3 36
ASP lOR
UnllCeIl
Name Descrlpllon Basic Cells Drive (Iu) Polarlly
XIN Exclusive NOR 3 18 Neg
XIB Power Exclusive NOR 4 36 Neg
~N Exclusive OR 3 14 Pos
X2B Power I 4 36 Neg
X3N 3-inpul Exclusive NOR 5 14 Neg
X3B : Exclusive NOR 6 36 Neg
X4N 3-inpul Exclusive OR 5 14 Pos
X4B PCo ...... 3-u '....' Exclusive OR 6 36 Pos
1-39
CG21 Series
1-40
CG21 Series
-
Unit Cell
Name
P24'
...
Type
2:1
Description
:.:":::::::::::::: ....•.
Data Selector
Basic
Cella
12 S,XS
Drive
(Iu)
36 a
"
...,......
Selecta
{/
Output
"··",·,·,.·.·//i;,,i
Bit
Width
4
r2~ 2:1 Dual Selector 18 5 S xa 2
T2F 2:1 Selector 18 8 S xa 4
T2B' 2:1 Selector 18 2 S,XS xa 1
T2C' 2:1 Selector 18 4 S,XS xa 2
T2D' 2:1 Selector 14 2 S.XS xa
T5A' 4:1 Selector 9 5 S.XS XQ 1
V3A' 1:2 Selector 14 2 S.XS XQ 1
V3B' 1:2 Dual Selector 4 14 S,XS xa 2
, These are· I (late device! whose outputs can be tied because they can be inhibited wnh t,,, .r., I selects.
i . I.··'·····• • ··,.,··· ·• >i. · . I ··..i . i.·· . / >
Unit Cell
Name Type Description
i ••••
Bsslc
Cells
Drive
(Iu)
Active Level
Outputs Enable
III
DE4 2:4 Decoder 8 14 Low Low
-- --
DE6 3:8 Decoder 30 18 Low 1 High
2 Low
"·'ii'···" '.\i}"·. .. ,',.. ))(........,.•...
Unit Cell Basic Drive

Name Type Description Cella (Iu) BuaSlze Enable
Bll I-bit Bus Driver 5 36 1 Low

B21 2-bil Bus Driver 9 36 2 Low
881 B-bit Bus Driver 33 36 8 Low
B12 I-bit Block Bus Driver 7 72 1 Low
B22 2-bit Block Bus Driver 13 72 2 Low
~_~~~:;r
25 72 4 Low
i..'·i)i . ·. .·,' '·<\ii (i·ii(i . ··',,?I· ·.·i •. •• • V

UnltCsll Basic
Name Description Cella Drlvs(lu) Enable Bits Output Clear
YL2 Data Latch with TM 5 36 High 1 Q -
YL4 Data Latch with rM ..14_ 36 High 4 a -
LTK Data Latch 18 4 Low 1 a,xa Async
LTL Data Latch with Clear 18 5 Low 1 a,xa Async
LTM Data Latch with Clear 18 16 Low 4 a,xa -
LTI S-R Latch with Clear 18 4 Low 1 a,xa Async
LT4 Data Latch 18 14 Low 4 a,xa -
, ..
Note: V-type latches Incorporate Inhibit Inputs and transparent mode (TM) to facilitate scan ImplementatIOn,
..
1-41
CG21 Series
FUNCTIONAL INDEX OF UNIT CEll LIBRARY (Continued)
Note: Synchronous flip-flops may be constructed by adding a simple AND gate (such as N2P) to the input of a flip-flop to
create a synchronous clear.
1-42
CG21 Series
-
ii/··. .·. t . }) i.· •. ......::........................................... :.. .:...... ../? i < \

Unit
Cell B••ic Drive C~ry Up!
Name Description Cella (Iu) Blla OUlpu..1 Load Clear Enable Down
~Q~~;
SCr-' Scan Synchronous Binary
Counter with Parallel Load 62 :36 ~ ~ync - . Low . Hig" Iup
:U~terwith paral;:i~~ ~o~~;

SC8'
66 36 4 Sync - High ' Low I Down
SC432 I Scan , Binary Counter 59 t8 4 a,co Sync Async High High IUp
SC4T' Scan , Binary Counter
....... ..
::.....::
\i
78 18 4 a,co
.........c:. ii /:/<i<·.·.··.:·
Async - Low
...
, Low IUpDown
..·.<i ii.i
~[e Description ~:~~c Drive
(Iu) BI.. OUlpu..1 Laac Clear Enable
Carry
In
Up!
Down
C11 3
C41
C42
Non-5can Flil>-floD for Counter
~~n-scan Bin:ciounter
Non-Scan Bi~~:!:mter
11
24
32
18
18
18 14
-
4
a.xa
a,(A)
a
- -
Async
Asvnc
- I- I-
Iup
IUD
m
C43
Non-5can Bi~~unter
48 18 '4 a.CO(S) SYnc Async Hiah Hiah IUD
C45 Non-Scan Binary Synchronous
Counter 48 18 14 a,co Sync Sync High High Iup
C47 Non-5can Binary ,Counter 68 18 :4 a,co Async - Low Low IUpIDown
NOles: 1. (S), (A) indicate the counter is (S)ynchronous or (A)synchronous.

=
2. Scan counters include clock inhibit end high drive (CDR 36lu). For non-Scan counters CDR = 181u
3. Cll may by used for purposes olher than counters.
g:::
Name
Description
Basic
Cells
Drive Bit
Width Load Oulputs
Clock
Polarity
FSI Serial-in Parallel-oul Shift

Register 18 16 4 Serial-In only O-Parallel Neg
FS2 Shift Re9iSI~ ~~
30 16 4 Sync-High O-Parallel Neg
FS3
34 18 4 Async-Low O-Parallel Pos
SRI Serial-in Parallel-out Shift
Register with Scan 36 36 4 Serial-In only O-Parallel Pos
1-43
CG21 Series
1-44
CG21 Series
name
indicates a pull-<lown resistance of the equivalent value.
1-45
CG21 Series
Example Of Open Drain Output
f\,ullup (min) - Veo (max) In X Out

Z01 liii:"[rai9a)
0 L L
Provides Out 1 Z H
Wire AND
Internal External
Example Of Open Source Output

I f\,ulldn (min) - Veo (max) In X Out
~
Provides
liii:"[rai9a ) 0 H H
Wire AND Oul 1 Z L
ZOO I
IN I
Internal 'External
1-46
CG21 Series
'",. >? . ""i

Edge
WE:~~
Unit
Cell Basic /:je logic Rata
Name Calla Lavel Control
H6T 3-stata Output and Input Buffer 0 3.2mA TTL No True

H6TU H6T with Pul~up Rasistance 0 3.2mA TTL No True
H6TD H6T with Pull-down Rasistance 0 3.2mA TTL No True
H6W vng, ~ .~.d Output and Input
Buller 0 12mA TTL No True

H6WU H6W with Pull-up Rasistance 0 12mA TTL No True
H6WD H6W with Pull-down Rasistance 0 12mA TTL No True
H6C 3-stata ' I CMOS
Intarlace Input Buffer 0 3.2mA CMOS No True
H6CU H6C with Pull-up Rasistance 3.2mA
III
8 CMOS No True
H6CD H6C with Pull-down Rasistance 8 3.2mA CMOS No True
H6E Power 3-stata Output and CMOS
Intarface Input Buffer 0 12mA CMOS No True
H6EU H6E with Pull-up Rasistance 0 12mA CMOS No True
H6E~ H6E with Pull-down Rasistance 8 12mA CMOS No True
H6S 3-stata Output and Schmitt
Trigger Input Buffer 12 3.2mA CMOS No True
H6SU H6S with Pull-up Resistance 12 3.2mA CMOS I No True
H6SD H6S with Pull-down Resistance 12 3.2mA CMOS No True
H6R 3-stata Output and Schmitt
ITrigger Input Buffer 12 3.2mA TTL No True
H6RU H6R with Pull-up Resistance 112 3.2mA TTL No True
H6RD H6R with Pull-down Rasistance 12 3.2mA TTL No True
HOT 3-stata Output and Input Buller 9 3.2mA TTL Yes True
HOTU HOT with Pull-up Resistance 9 3.2mA TTL Yes True
HOTD HOT with Pull-down Rasistance 9 3.2mA TTL Yes True
HOW .n~ v' .~..; Output and Input
Buffer 9 12mA TTL Yes True

HOWU HOW with Pull-up Rasistance 9 12mA TTL Yes True
HOWD HOW with Pull-down Rasistance 9 12mA TTL Yes True
HOC 3-stata Output Buffer and CMOS
Intarlace Input Buffer 9 3.2mA CMOS Yes True
HOCU HOC with Pull-up Rasistance 9 3.2mA CMOS Yes True
HOCD HOC with Pull-down Rasistance 9 3.2mA CMOS Yes True
Note: A "U· suffixed tol the name of a bidirectional buffer indicates a pull-up resistance of SOn (typical) and a
"0" indicates a pull-down resistance of the equivalent value.
1-47
CG21 Series
Unit Input
Cell Ba8lc Drive ....glc
Name Deacrlptlon Cella (ioL) Laval
H8E Power 3-state Output Buffer and
Interface Input Buffer 9 12mA CMOS Yes True
H8E with Pull-up Resistance 9 12mA CMOS Yes True
9 12mA CMOS Yes True
13 3.2mA CMOS Yes True

13 3.2mA TTL Yes True

8 8mA TTL No True

TTL No True
1-48
CMOS Channe//ess Gate Arrays Steps Toward Design
Chapter 2 - Steps Toward Design

2.1 Introduction
2.2 Choosing Fujitsu as your ASIC Manufacturer
2.3 Choosing a Device
2.4 Choosing a Package
2.5 Technical Review
2.6 Design Interface Options
2.1 Introduction
This section of the data book takes a look at the issues that must be considered before a design is ready
to be entered on a computer-aided engineering (CAE) workstation.
2.2 ChOOSing FujHsu as Your ASIC Manufacturer

The first step in implementing a given ASIC design is to choose the manufacturer that offers semi-
III
conductor processes capable of actualizing the performance requirements of the IC. The manufacturer
should also offer consistent and easily accessible customer support, timely transfer of the design into
Silicon, and a highly reliable end product.
The data sheet and supplementary information in Chapter 1 enable customers to determine whether their
requirements fall within the broad range of Fujitsu·s technical capability.
The second step is to discuss the design requirements with one of Fujitsu's Field Applications Engineers
at either a Regional Sales Office or a Technical Resource Center. Regional Sales Office and Technical
Resource Center addresses and telephone numbers are listed at the back of this volume. Fujitsu·s Field
Applications Engineers work with each customer to determine which technology would be most suitable
for a given design, taking into account the factors outlined in more detail below.
Fujitsu's highly developed software tools, high-capacity manufacturing facilities (the largest in the world)
and long history of excellence in the field (Fujitsu has been producing custom gate arrays commercially
since 1974) enable customers to turn designs into highly reliable products in a cost-effective time frame.
2.3 Choosing A Device

Speed is usually the deciding factor in choosing the technplogy for a design, but sometimes special
requirements such as package availability, on-chip memory (available in the AU and CG21 technologies),
or the necessity for battery power (a feature of the AVL technology) influence the final decision.
Usually the device type is a requirement of the design and Is chosen before the package size is
determined. The size of the package will depend on array size, partitioning, the number of power and
ground pins required by the SSOs (simultaneously switching outputs) used in the design, and the high
power drive buffers and clock inputs used in the design.
To determine the most suitable device within a given technology, the designer must determine the gate
count and pinout requirements from the schematic diagram of the design to be implemented.
The functions in the schematic or logic block diagram may be described using standard logic functions,
programmable logic, or Fujitsu's Unit Cell Library.
Gate counts are calculated in terms of how many basic cells make up each component function (unit cell).
This number is given for each unit cell in the unit cell library for each technology. By adding up the number
of basic cells used in each logic element in a design, a designer can arrive at a good first estimate of the
design complexity.
1-49
CMOS Channel/ess Gate A"ays Steps Toward Design
In the double-column channelless array technologies (AU and CG21), unit cells may take up parts of two
adjacent columns. It is recommended that no more than 50 percent of the basic cells in a channelless
array be used; 75 percent may be used if memory is included on the Chip. Respecting this limitation
facilitates fully automated layout.
2.4 Choosing a Package

Before the final chOice of an array can be made, however, the choice of a package must be considered.
The intended use of the IC generally detennines the type of package used: packaging issues are
discussed in detail in the application note "Choosing the Best Package for Your ASIC Design" included in
Chapter 7 of Section 1 of this data book. The types of packages available for Fujitsu's CMOS channelless
arrays are shown in the data sheet in Section 1 and in Appendix D of the AU Unit Cell Library (Section 2)
and Appendix D of the CG21 Unit Cell Library (Section 3).
The size of the package chosen is regulated by the number of inputs and outputs required, the number of
Vss and VDD pins required, and the number of simultaneously switching outputs (SSOs) included in the
design.
Package Size vs. SSOs

The number of SSOs can influence the size of the package chosen because additional ground pins are
sometimes required in a design that has more simultaneously switching outputs than is acceptable for a
given package type. Simultaneously switching outputs are those that switch from a logic low or a high
impedance (Z) to a logic high or from a logic high or Z state to a logic low within 20 nanoseconds of each
other.
A general rule is to use one ground pin for each group of 10 simultaneously switching low power outputs
or for 20 non-simultaneous outputs. Chapter 4 of Section 1 of this book and the Package Pin ASSignments
section of the Design Manuals cover pin requirement issues in more detail.
Although the Vss and VDD pins are preassigned in each package and cannot be changed, alternate
packages are available offering varying numbers of power and ground pins.
2.5 Technical Review

When the CMOS technology, the device, and the package have been decided upon, the customer and
Fujitsu's Field Applications Engineer hold a technical review to ensure that all the information necessary
to implement the design is available and to allow Fujitsu to derive a schedule and price.
2.6 Design Interface Options

The next step is to detennine which computer-aided engineering (CAE) workstation will be used to enter
the design. The desired result of entering the design on a CAE workstation is the generation of a
successful net list Or Fujitsu Logic Description Language (FLDL) file and a list of test vectors or Fujitsu
Test Description Language (FTDL) file. These two files (which may be generated on any of several
different CAE workstation systems) enable Fujitsu~s host mainframe to perform automated layout and
rigorous test and simulation of the design.
Four popular dedicated CAE workstation systems (Valid, Mentor, Daisy, and the HP 9000) as well as
several hardware-independent CAE packages support Fujitsu's design software. In addition, Fujitsu now
offers design support on ViewCADTM, a computer-aided engineering system originated by Fujitsu for ASIC
designs.
ViewCAD is written in the C programming language and runs on any UNI)(TM platform that supports the
X Window System™ (such as the Sun 3 or 4 series of workstations). It includes in one package all of the
necessary functions for the design, Simulation, and analysis of an ASIC design. ViewCAD makes use of a
graphics-oriented interface that allows visual examination of all circuits, circuit test data, and simulation
results. Its final product is the logic and test data description files (FLDL and FTDL) that are required by
the host mainframe computer to process a design.
1-50
CMOS Channel/sss Gate Arrays Steps Toward Design
Through long experience, Fujitsu has found that by far the most efficient way to achieve a trouble-free end
product is for customersio implement the design on a workstation themselves. This can be done:
a. on CAD equipment that the customer is already using (Fujitsu provides cell library
information files and the expertise to help write a conversion program to produce the FLDL
and FTDL files if necessary)
b. on one of the design systems that specifically support Fujitsu software (Daisy, Mentor, Valid,
HP 9000) either at the customer's workplace or in one of the Technical R,esource Centers
c. on ViewCAD either on the customer's own Sun equipment or at a Technical Resource
Center.
1-51
CMOS Channs/less Gate AfJaYS Steps Toward Design
1-52
CMOS Channe//ess Gate Arrays Design Procedures
Chapter 3 - Design Procedures
Contents of ThIs Chapter

3.1 Introduction
3.2 ViewCAD Design Procedures
3.3 Generic Workstation Design Procedures
3.4 Post-Design Process
3.5 Post-Design Simulation and Test
3.6 Engineering Sample Testing
3.7 ATG and SCAN Testing
3.1 IntroductIon
This section of the data book explains the steps necessary to implement an ASIC design in one of
Fujitsu's CMOS technologies using a CAE (computer-aided engineering) workstation. Designs can be
implemented with Fujitsu's YiewCAD design software or with one of the CAE systems or software
applications that support Fujitsu designs.
3.2 VlewCAD DesIgn Procedures

Fujitsu developed the ViewaAD design software to complement a wide range of customer third party
deSign tools. It includes:
• A schematic capture module utilizing the X Window System
• A logic design rule check module that screens for design violations in the areas of fanout and drive,
gate count, I/O requirements, etc.
• A test data or waveform entry module for test vector entry
• An interactive simulation module that replicates the Fujitsu mainframe for both functional and
timing simulation
• Conversion modules to define the net list and test vectors in the FLDl (Fujitsu logic DeSCription
language) and FTDl (Fujitsu Test Data Description language) formats required by Fujitsu's host
mainframe.
Figure 3-1 shows the ASIC design flow using. ViewCAD. This design flow includes the use of schematic
capture and test data generated on other workstations as well as on ViewCAD. The numbers on the left
side of Figure 3-1 correspond to the numbers of the paragraphs below that explain the corresponding
portion of the figure.
1-53
Design PfOCfKkJres CMOS Channs/less GaIB AmlYs
Figure 3-1. ASIC Design Flow with VlewCAD
3.2.1 Schematic capture

ViewCAD users accomplish logic circuit entry (schematic capture) through the Fujitsu Schematic Editor
(FED) module. After running a setup utility requiring the entry of the design name, tech",logy series, and
package type, users can insert unit cells and connect them to create circuit diagrams and see a graphic
representation of the resulting schematic. The Schematic Editor also provides a basic verification routine.
If the schematic has already been entered in another CAE system, it can be converted to ViewCAD-
compatible data by the FLDL-to-ViewCAD translator (FlI) module. A library Editor (LED) module is
available to specify design hierarchies, create user macros, and implement blocks in partitioned arrays.
ViewCAD allows the user to go back and forth between LED and FED to facilitate the development of
complex hierarchical designs.
1-54
CMOS Channel/ess Gate Arrays Design Procedures
The designer then uses a Page/Module Linker (PML) module to link pages, ensuring connectivity between
the pages of the schematic.
3.2.2 Logic Design Rule Check

DRC, ViewCAD's Design Rule Check module, examines the data files produced by the editor and page
linker modules for conformity to the design rules of the CMOS technology in which the design is executed.
Subsequently a Module/Network Linker (MNL) is run on the PML file to expand macros and link the levels
of the design hierarchy to prepare the data for the logic simulator.
3.2.3 Circuit Test Data Entry

The designer then provides the Test Data Editor (TED) with test Signals for the simulator. Like the
schematic capture module, the test data generator displays the data graphically. It allows the user to
create and modify Signal data and to prepare the data for the simulator module by saving it in a format
that the simulator understands. If test data has already been prepared on another CAE system, it can be
converted to data usable to the Test Data Editor.
The Simulation Module Linker (SML), which takes the output of the Module/Network Linker and generates
the delay estimates for the logic Simulator, is run before the logic simulator can be executed.
10
3.2.4 Simulation and Analysis
The Logic Simulator Module (LSM) reads the data created by SML and combines it with the test
information in the TED file to run a simulation of the design.
The Test Data Editor Converter (CVT) then converts the output of the simulation module (LSM) back into
a TED file. It provides the path from the simulator back to TED so that output that was previously given an
undefined value of "X" can be assigned actual simulated values.
The Simulation Analyzer Converter (CVS) translates the output of the logic simulator (LSM) into an
acceptable format for the simulation analyzer.
The Simulation Analyzer Module (SAN) analyzes the output from the simulator to determine whether it
performs as intended. SAN allows the user to display the simulation output and manipulate the display to
help the user analyze the output.
3.2.5 Data Conversion for Mainframe Interface

The last step in the implementation of an ASIC design on ViewCAD is the generation of the all-important
FLDL (Fujitsu Logic Description language) and FTDL (Fujitsu Test DeSCription Language) files.
After any design errors that may have been found by simulation and analysis have been corrected in the
schematic capture module, the designer runs the Fujitsu Logic Language Output Generator (flO) module
to convert the schematic data into an FlDL file for use on Fujitsu's host mainframe.
If any errors in test data are discovered during the simulation analysis process, the test data can be sent
back to the Test Data Editor Converter Module to be reconverted into a form that the test Data Editor
understands (since the errors must be corrected in the Test Data Editor module). After error correction or
if no errors are[ found, the designer sends the test data file to the Fujitsu Test Description Language
Output Generator (FTO) module for conversion into an FTDL file for use on the mainframe.
1-55
Design Procedures CMOS Channe/less Gats Arrays
3.3 Generic Workstation Design Procedures

Fujitsu provides ASIC Design Software Kits for designers using some of the popular design tools on
generic workstations. The kits offer support for Daisy, Mentor, Valid, and HP9000 and include:
• Fujitsu symbol model libraries for the CAE system's schematic capture module
• A Fujitsu logic design rule check module
• Fujitsu timing model libraries for the system's simulator
• A delay calculator module
• Conversion modules to define the net list and test vectors in the FLDL (Fujitsu Logic DeSCription
Language) and FTDL (Fujitsu Test Description Language) formats required by host mainframe
computer.
In addition, Fujitsu now offers FAME (Fujitsu's ASIC Managem~nt Environment), a menu-driven design
management program that enables the user to select the technology, the approximate gate count and 1/0,
pinout, and the package requirements, and to create a design database that is referenced by the other
modules to assure correct-by-construction design. FAME includes a test vector module that creates test
vectors automatically for complex functions, assists in defining test groupings, cycle times, and strobe
settings, and checks created test files against restrictions.
Fujitsu designs are also supported by several high-performance third party CAE tools. These include:
• Verilog-XLTM (Gateway Design Automation) mixed-mode system simulator
• LASARTM Version 6 (Teradyne) design simulator and test program generator with fault simulation
• HILO® (GenRad) design verification, fault simulation, and test generation tools
• IKOSTM 800 logic validation hardware accelerator
• SynopsysTM DeSign Compiler™ interactive behavioraVlogic synthesizer
Figure 3-2 shows a flowchart of the generic workstation-based design process. Because the function and
file names used by each different CAE system may differ, generalized names lor each operation are used
rather than system-specific names in the following list of steps.
1-56
CMOS Channe/less Gate Anays Design Procedures
Design Entry
~
Inputs OutpUt module counter (elk, data, out)
A1 = Btr + Bc C B A GZ inputclk;
A2 = C· 0 + A1 + E XXX H Z input [7 : 0) data;
A3 =O(B+C)+(DEj L L L L 00 output [7 : 0) out;
L L H H 01 wire elki, [7 : 0) datai;
Boolean Equation Truth Table Schematic Capture Behavioral Description

t
~~
t
I I Logic Data Conwrsion
ctH
NetUst LORC t
t
I
I
Back Annotation
,
I --....-.....-..
Functional Simulation!
Timing Analysis
~
I I
TestOata
Conwrsion
I
I
$ Vectors
Pre-layout
Simulation
~ and correction
r------------- 1
Customer
Approval
I
I Layout
t
I
I Post-layout
Simulation
I --------1
r' Customer
Approval
I
I Prototypes
Figure 3-2. Generic Workstation Design Flow

I
3.3.1 Design Entry
Design entry (schematic capture) is the first step in the generic design automation process, The designer
Ican use the drawing editor program of the applicable workstation software and Fujitsu-supplied symbol
1-57
Design Procedures CMOS Channel/ess Gate Arrays
model libraries for schematic capture. In most of the Fujitsu-compatible CAE applications, as in ViewCAO,
circuits can be defined as macros, for use as sub-parts of other circuits. Design entry can also be
accomplished using Boolean equations, truth tables, or behavioral descriptions.
3.3.2 Logic Design Rule Check

The Logic Design Rule Check (LDRC) module is Fujitsu software, written specifically for each technology
to check gate array designs. This program is run before simulation because it catches errors that,
undetected under normal workstation design rules, often cannot be tolerated in a Fujitsu gate array. Even
a seemingly small design flaw undetected prior to simulation may be severe enough to invalidate the
functional simulation of the design and any test signal data that may be generated from as a result. LORC
checks that the design conforms to the logic design rules applicable to all Fujitsu deSigns, to those unique
to a technology and to those required by the chosen package type. When hierarchy is used, LORC checks
for hierarchy violations.
In order to tailor the LDRC to a particular technology, device, and package, the customer enters required
information via an LDRC Control File, which supplies the device and package name and sets the LDRC to
output information in the form of a report either on all nets or on only nets that contain errors.
LDRCReport
When the LDRC is finished running, it produces a report containing the following information:
a. errors, alarms, and warnings of detected violations
b. chip information such as:
number of basic cells used vs. cells available
number of unit cells and of different unit cell types
total number of unit cell terminals vs. number of connected unit cell terminals
total number of nets
total number of external input, output, and bus terminals
package name
signal pins used and maximum number of signal pins available
c. loading unit check list (a list of the load units associated with each input and output signal)
Errors detected during LDRC can now be corrected before the Logic Simulation Program is run.
3.3.3 Functional Simulation

The steps that make up the functional simulation process vary between workstations. For some
workstations, functional simulation is all one step, while for others it is three separate steps:
a. logic simulator data base file compilation
b. delay calculation
c. logic simulation
logic Simulator Data Base File

The logic simulator data base file uses a Fujitsu-supplied library to apply behavioral characteristics such
as component functions. delay parameters, loading factors, and minimum pulse width, set-up time, and
hold time for flip-flops. These values are supplied by the Fujitsu libraries for the appropriate technology.
Input stimulus to the circuit is supplied by the deSigner in the form of the Control File.
Delay Calculator
Fujitsu provides the program for performing the delay timing calculations. The execution of the program
calculates the delay times unique to each net in accordance with the loading condition (fan-out and
1-58
CMOS Channel/ess Gate Arrays Design Procedures
hierarchy) in the schematic data file. These calculated delays are representative of pre-layout loading
conditions.
The calculations for metal loading are based on the same look-up tables and load equations used in the
Design Manual. These loads are subject to change after layout, reflecting the actual metal loads
experienced.
Logic Simulator
The event-driven logic simulator evaluates the outputs of each gate as a function of its inputs and displays
the results as either a wavefonn drawing or as a data file. Workstation simulations performed under the
influence of the Delay Calculator are vitally important to verification of design functionality and to the
creation of successful test vectors. Using in-circuit application stimulus from the Logic Simulator Data
Base File, simulations are executed in minimum, nominal, and maximum modes, with timing checks
enabled, to ensure that the design is responding as expected and is stable under all conditions. The
results are written to a print-on-change file, which is a list of the signals that changed state, their new
state, and the time at which they changed.
3.3.4 Logic Conversion (FLDL Generator)

Any errors found by the logic simulation process can be corrected at this point before Fujitsu's Logic
III
Design Language generator (FLDLGEN) program is run on the schematic data file to create the FLDL file.
The purpose of the FLDL file is to provide information to the host mainframe for automatic layout and logic
simulation. An FLDL control file must be created by the customer containing the customer's name, the
workstation type, the revision, the date, and the designer. The FLDLGEN program receives input from the
FLDL control file and the schematic data base file created at schematic capture and amended if
necessary according to the results of the LDRC and Logic Simulation. The FLDLGEN program can then
create a Logic Description (FLDL) file that describes the customer's design for the mainframe software.
3.3.5 Test Data Conversion (FTDL Generator)

The FTDL Generator (FTDLGEN) is a conversion program that translates the Logic Simulator's output file
into Fujitsu's Test Description Language. In the process of doing this, it applies Fujitsu tester restrictions to
the simulator results. Hany signal or timing violations are detected, the operator is informed so that the
necessary changes can be made to the data file. The final output file of the FTDL Generator becomes the
FTDL File, that is, the test vectors for the mainframe simulator as well as for the LSI tester.
3.4 Post-Design Process

At this point, the customer has gone as far as possible in designing a CMOS gate array on a CAE
workstation. Now the design is transferred to the mainframe environment at one of the Technical
Resource Centers for mainframe simulation on a Fujitsu M780 35 mips computer. Figure 3-3 describes
the post-design process in flowchart form.
1-59
Design Procedures CMOS Channa/less Gate Arrays
CusIomeT Fujitsu
Workstation Environment
Design Support
Mainframe Environment
Error Report
for Corrections
-------------------------------- ------
Manufacturing Environment
Sample Fabrication
Approval and P.O.
~'";:0,""??<,,1 = optional
Figure 3-3. Post-workstation Design Process
3.5 Post Design Simulation and Testing
3.5.1 LDRC and TDRC

The FLDL and FTDLfiles are provided to a Technical Resource Center usually in the form of magnetic
tape or floppy disk. On the mainframe, the FLDL is checked by the mainframe's Logic DeSign Rule Check
(LORC) to confirm the validity of the logic data and for formatting errors, unconnected inputs and outputs,
loading conditions, etc. The FTDL file is checked by a similar mainframe program called the Test Data
Rule Check (TDRC), which flags any violations of the published test data restrictions.
1-60
CMOS Channe//ess Gate Arrays Design Procedures
3.5.2 Pre-layout Simulation

After the LDRC and TDRC have been run successfully on the FLDL and FTDL, the mainframe pre-layout
simulation can be performed. This is a logic simulation run at nominal, minimum, and maximum
propagation delay times using estimated metalization capacitance values. If there is no discrepancy
between simulation results and the expected outputs, the design is presumed to be correct. One of two
simulators, LBS6 or ViewCAD, runs functional simulations and timing verification including the checking of
set-up and hold time, pulse width, and removal times.
3.5.3 Automatic Layout

After a successful pre-layout simulation has taken place and customer approval has been obtained, a
proprietary Fujitsu mainframe application performs automatic placement and metal interconnection
routing.
3.5.4 Fault Grading

After post-layout simulation is completed, customers have the option of requesting that Fujitsu subject the
test data to a process called fault grading. This CPU-intensive process analyzes the customer's circuit
and test data to calculate the percentage of fault coverage. The input test data is analyzed to determine
the adequacy of the stimulus patterns to detect any ''stuck'' (malfunctioning) nodes. The result, a report of
all nodes not tested by the stimulus provided, is given to the customer. The customer then has the option
of either changing the test vectors or acknowledging that the untested nodes are acceptable.
3.5.5 Post-Layout Simulation

Post-layout simulation, also known as final validation, is again performed at nominal, minimum, and
maximum propagation delay times, but using actual calculated capacitance based on the metal
interconnection routing resulting from automatic layout.
3.5.6 Sample Fabrication

After a successful post-layout simulation has been performed and customer approval has again been
obtained, engineering samples of the array are fabricated for customer evaluation.
3.6 Engineering Sample Testing
3.6.1 LSI Tester

Once sample chips have been fabricated, they are tested on the LSI Tester, a test instrument located at
the manufacturing facility. Sample chips are tested with input test patterns and expected outputs obtained
from the FTDL file.
One of the most important tasks of post-layout simulation is to validate the test vectors for later use on the
LSI Tester. For this reason, simulation is executed under conditions adhering as closely as pOssible to the
conditions imposed by the tester. A device that passes all phases of simulation is likely to pass the LSI
tester.
The limitations of the LSI Tester places various restrictions upon test data. These restrictions must be
respected when preparing the test data pattern and when creating the (stimulus) Controllile for running
workstation simulations. A "Summary of Test Data Restrictions" for AU Gate Array technology is included
in the AU Design Manual.
Test data restrictions involve such issues at the numbers of test patterns acceptable for each test type, the
minimum test cycle length, input signal timing, output strobe timing, bidirectional buffer simulation, input
and output cycle timing, tester skew, and the treatment of data signals.
1-61
Design Procedures CMOS Channel/ess Gate Arrays
Tests performed on the LSI Tester Include the function test, the delay test, the DC test, and the high
impedance ("Z function") test. Specific data found in the AU Design Manual must be included in FTDL to
perform each of these tests.
3.6.2 Function Test

The function test guarantees the designed function of the gate array by exercising as many of the intemal
nodes as possible and detecting functional failures. Fujitsu requires the function test because it is the
primary means of determining if an ASIC is functioning properly as it comes from manufacturing.
In the course of the function test, input signals are applied in accordance with customer timing
specifications, using worst-case input voltage at a clock frequency not to exceed 16 MHz (a period of 63
ns). The dynamic performance of this test also partially verifies the AC characteristics of the device.
T~e function test may be run in multiple units (blocks), allowing changes to be made in the test vectors to
assure thorough testing of the device. The transition from one block to the next requires that the device be
powered off, adjustments made to the tester and pins regrouped as required. After all changes have been
made, the test is restarted. For this reason, each test block must re-initialize the circuit.
3.6.3 Z-Function Test

The Z-Function test is administered in the last block(s) of the function test. Its purpose is limited to the
verification of the high-impedance function of 3-state and bidirectional output buffers. The Z-function test
is necessary only when there are two or more logic combinations that can generate the high-impedance
slate for a given I/O cell. The test can verify all these logic combinations. If only one logic combination
generates the high-impedance condition, then the DC test is adequate.
3.6.4 DC Test
The DC test, as its name implies, verifies the DC characteristics of the array. It is not intended to check
circuit functionality, but it can be used as a function test of 3-state circuits having only one signal path that
generates the high-impedance condition.
The designer supplies the sequence of input signals and expected outputs in the FTDL. These test
patterns must generate every possible state for every type of output and input buffer being used (high,
low, and high-impedance).
The DC test applies the specified inputs to measure the following DC parameters:
a. Steady state power supply current (Ioos)
b. Output high voltage (VOH)
c. Output low voltage (VoLl
d. Input leakage current (Ill)
e. High-impedance output leakage current (1[2)
3.6.5 Delay Test

The delay test is optional. It is used to verify critical paths or as a means to characterize the device by
performing this test on a small number of paths. The purpose of the test is to check that signal paths from
various inputs of the chip to their respective outputs meet the customer's standards for minimum and/or
maximum delay times. The paths may be sequential and/or combinatorial but only the propagation delay,
not the toggle frequency, is measured.
1-62
CMOS Channelless Gate Arrays Design Procedures
3.7 ATG Testing and Scan Design

ATG testing is a special technique that supplements the customer's submitted test patterns (FTDL) to
assure both Fujitsu and the customer of a highly reliable gate array by achieving a high degree of fault
coverage. ATG testing is implemented by using scan design techniques described at the end of the
Design Considerations Chapter. Scan test patterns (both applied input stimulus and expected outputs) are
automatically generated by Fujitsu's Automatic Test Generator (ATG) software. ATG is offered by Fujitsu
for partitioned arrays of the UHB technology and for all arrays in the channelless gate array technologies.
1-63
CMOS Channel/ess Galli Anays
1-64
Design Considerations CMOS Channel/ess Gate Arrays
Chapter 4 - Design Considerations

4.1 Introduction
4.2 Basic Cell Usage
4.3 Physical Design Consideration
4.4 Designing for Reliability and Testability
4.5 Clock Networks
4.6 Internal Bus Circuits
4.7 Transmission Gate Circuits
4.8 110 Pin Assignments
4.9 Scan Test Technology
4.10 Compiled Cell Testing
4.1 Introduction
Chapter 4 gives an overview of the design hierarchy scheme and the logic and 110 design considerations
with which designers need to be familiar in order to optimize a design in Fujitsu's chanelless CMOS Gate
Array technologies. This chapter also covers design techniques necessary to implement automated scan
path testing of logic circuits and automated testing of compiled cells.
..
4.2 Basic Cell Usage
In order to benefit from fully automated layout, a designer may use no more than 50 percent of the actual
cell count of an AU gate array, 45 percent for CG21 arrays, or 75 percent if the array includes memory or
other compiled cells. The actual cell count is the number of basic cells used in the device. AU and CG21
gate arrays utilize internal basic cells as components for 110 buffers; this means that the number of inputs
and outputs and therefore input and output buffers required can limit the number of basic cells available
for logic design. The utilization guidelines are based on the following formula:
Basic cells available for unit cells and 110 cells = (total on-chip basic cells - compiled cell basic
cells) x 50 percent for AU designs or x 45 percent for CG21 designs.
4.3 Physical Design Considerations

In general, signal delays are caused by the signal having to travel through more gates or over longer
distances, especially to enter a different block in gate arrays having block architecture (partitioned arrays)
or through thicker interconnect wiring. Delay is proportional to length (and thickness) of interconnection
metal along which the signal must travel. The following recommendations are therefore made to optimize
overall design speed by minimizing the interconnect metal length and the use of thicker interconnection
wiring.
4.3.1 Hierarchical Design

Devices that are partitioned allow the designer to control relative path lengths. AU and CG21
technologies, therefore, require a hierarchical design approach that divides the cells into blocks and the
blocks into sub-blocks so that functional groups of unit cells are laid out in close proximity and signals
have less far to travel. When it becomes necessary to link blocks, the use of high-power "high-drive" unit
cells is recommended to drive signals in the inter-block metal.
1-65
CMOS Channe//ess Gate Arrays Design Considera6ons
The basic cells in the gate arrays are partitioned into as many as eight blocks. Additional blocks are
required to accommodate RAM and ROM modules, when used. Blocks of basic cells used exclusively for
digital logic gates can have as few as 4,500 basic cells or as many as 10,000.
The physical layout of all AU and CG21 gate arrays is similar. Required block partitioning is a function of
software and is not a physical characteristic.
A hierarchical design method not only offers optimal control of path lengths, but also provides a
convenient method of design. Hierarchical design allows the designer to divide the circuit into major
macro functions and to follow a step-by-step approach in describing their interconnection.
The hierarchical structure is different for unit cells and compiled cells. Figure 4-1 illustrates the
hierarchical structure of an AU or CG21 design.
Figure 4-1. Hierarchical Organization of AUlCG21 Designs
4.3.2 The Digital Logic Hierarchical Structure

The CHIP level is the highest level in the hierarchy and represents the entire Chip. All I/O cells are defined
immediately below the CHIP level, along with any clip cells they may require.
Level 1 blocks must be defined immediately beneath the CHIP level and cannot exceed eight in number
(when used for digital logic). Neither unit cells nor compiled cells can be described immediately beneath
the CHIP level.
Level 2 is defined beneath the Level 1 blocks, Level 3 beneath Level 2, etc. Levels must always be.
defined in numerical order. There is no limit to the number of Level 2, Level 3, or Level 4 blocks that may
1-66
be used (when defined below a higher block level). Unit cells may be defined beneath Levels 2, 3, or 4,
but the lower in the hierarchy the unit cells are defined, the greater the designer's control of delay will be.
Any level may be the first defined under the CHIP level and any of the levels may be omitted; however,
the more the designer deviates from the standard structure, the greater the differences between estimated
pre-layout delay and actual post-layout delay will be.
The recommended number of basic cells for each hierarchical level is shown in Table 4-1. It is highly
recommended that the designer adhere to the guidelines in this table since the tables of estimated
metallization load for the cells are based on these block sizes. The basic cell level counts overlap from
level to level. The designer may select either of the levels covered by the cell count, but must also use the
appropriate table of estimated metallization load for delay calculations.
Table 4-1. Basic Cells per Hierarchy Level
BLOCK under CHIP Basic Cell Count: Basic Cell Count:

AU30K to AU100K AU10K to AU20K
Levell
CG21303 to CG21104
4500 to 10,000·
CG21103 to CG21203
800 to 2500 III

Level 2 1800 to 5500 300 to 1200
Level 3 400 to 2200 80to 500
Level 4 maximum 600 maximum 120
• Any block exceeding the recommended maximum of 10,000 basic cells must be designated Level 1.
4.3.3 The Compiled Cell Hierarchical Structure

Each compiled cell (RAM or ROM) must be defined under the level block which resides directly beneath
the CHIP level (whether it is a Level 1, 2, 3, or 4). It must be the only cell beneath the level appropriate for
the number of basic cells (as defined in Table 4-2) required for that particular compiled cell. The test
,circuit for a RAM or ROM block cannot be defined in the same block as the RAM or ROM itself. The test
circuit should be defined in a block physically close to the RAM or ROM block.
In the CG21 technology, the reccomended number of cell liDs per block is restricted as shown in
Table 4-2. The numbers shown in parentheses in the table is the maximum number of unit cell outputs
that can be connected to 110 unit cells (110 buffers).
Table 4-2. Recommended Maximum 1/0 Count per Block
Block under CHIP CG21103 to CG21303 CG21303to CG21104

Levell 130 (70) 500 (140)
Level 2 80 (50) 300 (90)
Level 3 50 (90) 100 (60)
Level 4 30 (20) 50 (30)
1-67
CMOS Channel/ess Gate Arrays Design Considerations
4.4 Designing for Reliability and Testability

The following general considerations must be made to ensure maximum testability and therefore reliability
of a design:
a. External signal paths must be interfaced to the array by an VO buffer.

b. The outputs of a unit cell other than 3-state bus macros and transmission gates may not be
wire-ANDed. Generally, if output functions must be tied together, they must be combined
through a logic function.
c. Only one I/O buffer cell can be connected to an external terminal.
d. Inputs to the same cell may not be tied together.
e. Unused inputs must be tied high or low, never left floating.
f. At least one output of a unit cell must be connected.
g. Functions such as one-shots and other monostable or astable circuits cannot be
incorporated into a Fujitsu CMOS gate array. All logic state changes detected at the output
of the array must be predictable for the purpose of test, and as such, be the direct result of
changes of input stimulus. Series inverters must not be used for the purpose of creating a
delay.
h. Circuits incorporating sequential devices for instance, flip-flops, counters, shift registers, and
so on must have a traceable method of initialization designed into the circuit, independent of
feedback loops.
i. No logic function should be incorporated within the array if it cannot be directly or indirectly
set or initialized from a primary input. Designers have two choices for initialization:
1. Supply an external signal for CLEAR, LOAD, etc.
2. Supply known inputs and allow time for them to propagate through the circuit. If the
propagation method is used, UNKNOWN ( "X" state) must be an acceptable output
state until the initialization is completed.
The information contained in the following sections relates to more detailed aspects of gate array design.
4.5 Clock Networks

A clock network is a circuit used for the efficient distribution of an external clock signal to the clock input of
internal sequential and combinatorial unit cells. Skew is the differential delay of a signal as it proceeds
through a system. In the context of gate arrays, skew is the effect of a common clock pulse being applied
to sequential and combinatorial unit cells at different points in time, because the unit cells are located at
different relative positions from the clock pulse origin.
Within a gate array, clock networks may utilize high-frequency and power (HFP), low frequency (LF), or
low power (LP) input circuits. Clock networks should be optimized for both internal and inter-chip clock
signal distribution applications to minimize skew and to assure high-speed, synchronized operation.
1-68
Design Considera~ons CMOS Channel/ess Gate Arrays
Optimization of clock networks is made possible by the use of the following:

• High-drive input buffers (also called clock input buffers) for HFP and LF input circuits
• Low-drive input buffers (also called data input buffers) for LP input circuits
Dedicated unit cells (also called clock distribution buffers) driven by HFP, LF, and LP clock input
circuits
Up to eight clock input buffers can be used per hierarchical block under the CHIP level and up to 16 clock
buffers can be used per design.
4.5.1 High-drive Input Buffers (Clock Input Buffers)

There are two types of high-<lrive input buffers used for HFP and LF input networks: IKB ( an inverting
clock input buffer) and ILB (a non-inverting clock input buffer). The IKB and ILB unit cells each have two
variations: one incorporates a pull-up resistor on the unit cell input (IKBU and ILBU) and the other features
a pull-down resistor (IKBD and ILBD). All have a CDR of 200 lu.
4.5.2 Low-clrlve Input Buffers

Low-drive input buffers for LP input networks are also available with pull-up and pull-down resistors. Input
III
buffers IB, 11C, 12B, and 12C have a CDR of 36; input buffers 11S, 12S, 11 R, 12R feature a Schmitt trigger
input and a CDR of 18.
4.5.3 Clock Distribution Buffers

Clock distribution buffers are used to minimize skew by isolating groups of loads from each other and to
provide a facility for balancing one group of loads against another. Clock distribution buffers also provide
additional drive capability to the clock signal.
Clock distribution buffers must be used immediately following high-drive input buffers in AU and CG21
gate array networks connected to the CK-input of any unit cell.
There are two categories of clock distribution buffer used in AU and CG21 designs: high-<lrive, with a CDR
of 55 and low-<lrive, with a CDR of 36.
Hlgh-drlve Clock Distribution Buffers

There are five high-drive clock distribution buffers:
KAB - Block Clock Buffer
KBB - Block Clock (OR x 10) Buffer
KDB - Block Clock (OR x 10) Buffer
K2B - PowerlClock Buffer
V1 L - Inverting Clock Buffer
These high-drive clock distribution buffers are restricted to clock signal distribution applications.
These clock distribution buffers must be driven only by the following:
High-<lrive input buffers (clock input buffers)
Low-drive input buffers (data input buffers)
Schmitt trigger input buffers (maximum signal frequency 13 MHz)
HFP input networks must have KDB clock distribution buffers connected to the outputs of their high-drive
input buffers (IKB and ILB) within certain limitations. The maximum number of KDB clock distribution
buffers permitted per gate array is also limited by array size. These limitations are set out in full in the
1-69
CMOS Channe//ess Gate Arrays Design Considerations
appropriate Design Manual. Use of other clock distribution buffers is unlimited, regardless of the type of
input network.
Low-drive Clock Distribution Buffers

There are four low-drive clock distribution buffers (CDR = 36):
K1B - Non-inverting Clock Buffer
K3B - Ga,ed (AND) Clock Buffer
K4B - Gated (OR) Clock Buffer
K5B - Gated (NAND) Clock Buffer
Low-drive clock distribution buffers may be driven by the following:

High-drive input buffers(clock input buffers)
Low-drive input buffers (data input buffers)
Schmitt Trigger input buffers (maximum signal frequency 0113 MHz)
Any other unit cell, including high-drive or low-drive distribution buffers
Low-drive clock distribution buffers K1 B, K3B, K4B, and K5B may be used in any application, clock or
non-clock, that includes regular data signal buffering.
4.6 Internal Bus Circuits

High-performance internal 3-state buses are a feature of AU and CG21 gate arrays using transmission
gates for 3-state control. Bus terminator cells are provided to keep the 3-state bus from floating when not
being driven. FuJitsu's design software automatically connects the bus terminator cells to the 3-state bus,
where they serve to maintain the last logic level applied to the bus prior to the last bus driver's switching
to its high-impedance state. This last logic level will be maintained until any bus driver begins to drive the
bus line.
The following bus drivers are available:

B11 1-bit Bus Driver
881 8-bit Bus Driver
B12 1-bit Block Bus Driver
Figure 4-2 shows a typical bus driver cell.
Overall, the total loading factor should be less than the output driving factor for any clock network design.
Taking clock skew into consideration, it is recommended to limit the total input loading factor of clock input
buffers to 16 lu (N FlO S 16) and to limit the total input loading factor of clock buffers to 25 lu (N FlO S 25).
1-70
r-----------c;,---------' # Internal Circu~
I • -:..:...1:....:- ,
I "
AO--~~.~ )o-.--~ Xo
I .-------..
+ I BO
I
: --::r--- ~
II •TGXCo
______ ,
Symbol
I
A1 --;---:
~-------:
~
. XI
I .-------.
XO I BO
AO
AI XI I
I •
A2 B41 X2 A2--+-- X2
A3 X3 I •
C
I BO
I
I •
A3~ X3
I •
I BO XCo • .!9_ - -- ~
I Co
I .-------.
c~· Co
~: XCo
I .-------. I
I _____________________
L OC I ~
Figure 4-2 Bus Driver Cell, B41

A bus line and associated bus drivers Bll, B21, B41, and B81 must reside within the same Levell block,
immediately below the CHIP level in the design hierarchy. At this time, only a 3-state bus line driven by
one of the Block Bus Drivers (BI2, B21, and 841) can connect two different blocks. Capacitive loading on
bus signal nets is calculated by adding the metal load per the net (NDI land the load factor for all unit cell
inputs and bus driver outputs connected to the net where:
ND/ = (number of unit cell inputs) + (Number of bus drivers - 1)
NF/o = (sum·of NF/oS of all unit cells) + (sum of all bus driver Output Load Factors)
The total load driven by the output of a bus driver must not exceed 2CDR.
4.7 Transmission Gate Circuits

Transmission gates (TGs) allow the selection of two or more input signals, one at a time, to be extended
to the TG output. Certain TGs have more than one output, facilitating the switching of one input of each of
two or more groups to each of the respective group outputs. There are, for example, four outputs on the
T2F TG. One input of four different input groups can be switched Simultaneously to their respective group
outputs. Selector terminals on the TGs allow direct control of the internal switches by the designer.
4.8 1/0 Pin Assignments
4.8.1 Predetermined 1/0 Pin Locations

The locations of the following gate array pins are predetermined and cannot be changed:
1-71
CMOS Channa/less Gats AtTays Design Considerations
Voo (+5 voltS)

Vss (Ground)
Scan inputs and outputs
The maximum output low current (Iou must not exceed 70 mA per Vss pin output sink current. All Voo
and Vss pins must be connected to power and ground.
If scan testing is included in the design see section 4.9 of this chapter., six. scan test pins are assigned
predetermined package pin locations.
When scan testing is to be employed, five of the six scan test pins must be dedicated to scan functions
and cannot be used or multiplexed with any other signal in the design. If scan testing is not part of the
design, the gate array pins otherwise reserved for the scan test pins can be used as inputs.
4.8.2 General 110 Placement Recommendations

The following general parameters apply to the assignment of I/O pins:
a. All Vss pins must be tied to ground.
b. All Voo pins must be tied to 5 volts.
c. Voltage and ground pins are predetermined by the package type and cannot be altered.
d. Pins designated "No Connection" cannot be used.
e. Additional Vss and Voo pins may not be assigned by the designer without first negotiating the
change with Fujitsu.
f. Fujitsu recommends that the designer assign the pin numbers to the circuit in the' ASSIGN or
'OPTION section of FLDL or submit the complete pin assignment table with the d ::.i9i1. It is
also possible to allow the Technical Resource Center to do the assiQnment automatically on
the mainframe or manually from a customer-supplied form.
4.8.3 Simultaneously Switching Outputs (SSOs)

Outputs are defined as switching simultaneously when they switch either from a logic low or a
high-impedance state. to a logic high, or from a logic high or a high-impedance state. toa logic low within
20 nanoseconds of each other. When an output switches, the gate array either sources current or sinks
current, owing to the charge or discharge of the extemal capacitive load. This charge/discharge current
flows through the self-inductance of the power and ground leads of the gate array, producing induced
transient voltages across them.
Simultaneously switching outputs increase the momentary charge/discharge current flow at the gate array
and cause noise in the form of momentary spikes or ringing in the power and ground lines. The greater
the number of SSOs, the greater the noise produced. These spikes and ringing may appear as signals to
the CMOS logic, and therefore must be avoided.
When the ground level is raised by the noise, the input threshold voltage of the gates is also raised,
relatively, for the duration olthe impulse (as illustrated in Figure 4-3). If VTH rises, momentarily, above the
VIHmin level, a logic high with a level just above VIHmin will be recognized as a low level for the duration of
the spike. Similar problems are experienced when the ground level is depressed by the noise, affecting
logic low levels close to VILmax.
1-72
Design Considerations CMOS ChsnneJ/ess Gats Arrays
v V1H V1H(nin') = -2.2 V
~------~ II ,----------
I
VTH
V
o "
I
V1L V1Llmax.) = .08 V
u
GNDLevel
1-
Figure 4-3. SSO-Generated Noise

The severity of the effect of SSOs is determined by:
• The number of SSOs
• The density and distribution of SSOs in the package
• The size of the load capacitance. being driven
The number of SSOS allowed in a package is restricted by the number of ground (VSS)pins available, the
drive capability of the output buffers, and the location of ground pins on the package (See the Available
Package and Pin Assignments section in the appropriate Design Manual). Representative values have
been assigned to the effects of output buffers per single ground pin. Output buffers are capable of either
3.2mA or 12rnA drive capability, and each may be selected with an optional noise-limiting resistance
(NLR) value to minimize generated switching noise. The representative values are given in Table 4.3.
Table 4-3. Representative Value of Output Buffers
Output Buffer Represenatlve Values (per Output)

Normal Drive with NLR (IOL =3.2 rnA) 7
High Drive with NLR (IOL =8 rnA) 12
Normal Drive with NLR (IOL =3.2 rnA) 10
High Drive with NLR (IOL = 12 rnA) 20
The sum of the represenative values for each of the SSOs used in a design must not exceed 80 per Vss
pin, regardless of the type of package used.
4.8A Maximum Load per Ground Pin

The maximum total output load per ground pin is limited as a function of the output switching frequency.
The product of the output switching frequency in MHz. and the total output load in pF. per ground pin
cannot exceed 12,700 pF x (frequency in MHz), at the maximum junction temperature, Tjmax, of 70·C. As
the junction temperature increases, the allowable maximum load per ground pin decreases per the
following formula:
C x f S ( 12,700 x Kt.) pF x (f [MHz} /(number of ground pins)
where C = the output load, in pF
1-73
CMOS Channe//ess Gale Anays Design ConsideraUons
( = the output switching frequency, in MHz

Kt = the junction temperature coefficient of load, a constant determined from Table 4-4.
Table 4-4. Junction Temperature Coefficient of Load
T)(_.)OC Kt
70 1.0
85 0.7
100 0.5
125 0.3
150 0.2
4.8.5 Maximum Load per Output Pin

The maximum total output load per output pin is limited as a function of the output switching frequency.
The product of the output switching frequency in MHz. and the total output load in pF. of any pin cannot
exceed 1200 pF x (MHz, at a maximum junction temperature, Tj(max.), of 70°C. As the junction temperature
increases, the allowable maximum load per output pin decreases per the following formula:
C x (S (1200 x Kt.}pF x «([MHz) /(number o( ground pins)
where
C = the output load, in pF
( = the output switching frequency, in MHz
Kt = the junction temperature coefficient of load, a constant determined from Table 4-2.
4.8.6 Pin Assignment Guidelines
The locations of all Vss and Voo pins are predetermined and fixed. Since the placement of SSOs on any
package is critical, SSOs must be assigned within certain pin groups. Within these pin groups, other
restrictions apply regarding the separation of SSOS from each other or their proximity to the Vss pins.
As noted above, the total representative value of any SSO group shown in Table 4-4 must not exceed 80.
The SSO pin groups differ between packages. The package outlines and deSignated grouping of SSO
pins for specific devices are shown in the Available Packages and Pin Assignment section of the
appropriate Design Manual.
As a general rule, however, the pins available for SSOs between two Vss pins are assigned as follows
refer to Figure 4-4.
,D
Vss
/
D
~~____________U__'~:_D__________D__-J~
I
NPins
¥
Vss
Figure 4-4. SSO Pin Assignments

1-74
• Assume that N pins exist between adjacent Vss pins

• Find the center point on the package between the two Vss pins
• There are N/2 pins in the area between the center point and the first Vss pin (part A), and N/2
pins in the area between the center point and the second Vss pin (part B).
• The SSOS must be equally distributed between parts A and B, within ± 1.
4.8.7 The Location of HFP Network Input Buffers

The placement of input buffers for HFP input networks is critical because of the special metalization
required. Complete sets of tables in the Available Package and Pins ASSignments section of the
appropriate Design Manual cover the placement of HFP input buffers, reset, preset, and clear pin
assignments.
4.8.8 SSO Pin Placement Summary

The following is a general summary of recommendations for the placement of pins.
a. SSOs must be placed in close proximity to Vss pins.
b. High-drive SSOs should be placed closer to Vss pins than normal-drive SSOs.
c. Asynchronous inputs such as clocks, presets, and clears should be kept away from SSOs. It
is preferable that these inputs be placed close to Vss pins, if available, and away from SSOs.
d. Clock, preset, and clear inputs must not be placed on the corners of a package, especially
when the array is packaged in a DIP.
e. Output signals to be used as clock, preset, or clear for other devices must be kept away from
SSOs and close to a Vss pin.
f. SSOs should not be placed in the outer row of pins of PGA packages.
4.8.9 Test Pins

To facilitate testing, external pins should be provided whenever conditions warrant. The addition of
supplementary test pins often allows the reduction of the overall test complexity for a Circuit, thus reducing
the number of test patterns required and the time necessary to determine functionality of the circuit.
4.9 Scan Test Technology

Scan testing is a supplementary, optional test technique that, when used in conjunction with the function
and DC test required of the deSigner, allows greatly increased fault coverage. This increased fault
coverage assures both Fujitsu and the designer of a highly reliable gate array.
4.9.1 Scan Test Design

The designer implements scan testing by arbitrarily connecting all the sequential logic elements to form an
enormous shift register. This shift register can contain up to 3000 stages and is formed by connecting the
a-output of one stage to the dedicated scan input (SI )of the next. If the a-output cannot be used for this
purpose, then the xa-output may be used, but an inverter must be placed between the XQ-output and the
SI input of the following state in order that the data not be inverted.
1-75
CMOS Channs/less Gate Anays Desig(l CO(lsiderati(](ls
To implement scan testing, designers use special scan-compatible unit cells for all sequential logic
functions. With the use of the serial scan method, the difficult problem of testing a logic circuit containing
both combinatorial and sequential logic is simplified 'to testing combinatorial logic and a shift register, as
shown in Figure ~ below.
SFF 5FF 5FF V1N 5FF
a
.
~-------.
51 :
.
Figure ~. Scan Circuit Configuration
Dedicated scan inputs are also used to isolate elements that are not part of the scan test path. Some of
these elements can also be tested during the scan test cycle by the use of an alternate scan test mode.
The scan chain design can be considered a data carrier with the ability to carry test input stimulus
provided by the LSI tester deep into the design and to apply it to the unit cells under test. Once a unit cell
has been tested, its output test result may be stored in the scan data chain and be carried out of the
design for comparison to that which was expected. To the designer, can unit cells perform exactly the
same as non-scan unit cells, the only difference being the provision of additional basic cells to facilitate
the scan test.
Scan testing usually entails an extra 8 to 20010 basic cell count, requires the use of seven extra I/O pins,
and can cause some degree of propagation delay. Nevertheless, when absolute reliability is the issue,
designers find that these considerations are within an acceptable range.
4.9.2 Test Pattern Generation
A circuit that is designed for scan testing in this way allows Fujitsu automatic test pattern generation
(ATG) software to generate the scan test patterns automatically (both applied input stimulus and
expected outputs). The ATG software uses the logic design data from the FLDL file as input from which it
generates the test patterns for scan tests. The process requires that all sequential unit cells be of the scan
type with the exception of data latches YL2 and YL4. Inclusion of non-scan sequential circuits constructed
with combinatorial logic, (I.e., NAND-gate flip-flops, NOR-gate flip-flops, etc.), are discouraged in a scan
design because they reduce the overall fault coverage attainable with scan testing. If their use is
unavoidable, they must be disabled or isolated by one of the scan test signals discussed below during the
ATG process and the scan test.
Scan testing is optional and is applicable only to digital logic unit cells. Compiled cells such as RAM and
ROM are tested using a different technique, which is covered in section 4.10 of this chapter and in the
Logic DeSign section of the appropriate DeSign Manual.
4.9.3 Scan Test Signals

Scan test implementation requires the assignment of a dedicated output pin and up to seven input pins,
six of which are in predefined package locations. The package locations for these pins in each device type
are shown in the Available Package and Pin Assignment section of the appropriate Design Manual.
1-76
Design Considerations CMOS Channelless Ga'" Arrays
Input Pins Description

1. XACK is the scan input, scan output (SISO) A·clock signal. It is generated by the LSI tester and is
applied, inverted, to all scan devices at their A-clock input. It writes data from the unit cell's
scan input to the master latch.
2. BCK is the SISO B-clock signal. It is generated by the LSI tester and is applied, inverted, to all scan
devices at their B-clock input. It transfers data between the unit cell's master and slave latches
(the output of the device).
3. XSM is the SISO mode signal. It is used for set-up of bidirectional buffers, bus drivers, and RAM. If
bidirectional buffers or bus drivers are not used, then XSM is not required and need not be
included in the design.
4. XTST is the scan test signal. It is used to reconfigure the array to make it suitable for scan test and
to establish all conditions required for the use of FUjitsu's ATG software. This includes the
isolation or removal of certain circuits unsuitable for scan testing, such as non-scan sequential
functions and the asynchronous inputs of all sequential elements. (Since they are inaccessible
to scan testing, these circuits and disabled functions must, therefore, be tested with
user-prepared test patterns.)
XTST disengages all connections between RAM macro data outputs and RAM macro inputs
by inserting scan flip-flops in the paths. It causes the internal compiled cell test circuit to select
RAM and ROM address and enable lines and RAM wire enable inputs.
If all sequential functions utilize scan type unit cells, if no asynchronous functions are
employed (including direct sets and clears), and if circuit isolation is not required, then XTST is
not required and is not provided for.
5. XTCK is the TC mode clock signal. It is generated by the LSI tester. It is applied, inverted, to the
IH-inputs of all sequential unit cells.
6. SOl is the serial data input port to the first device of the scan path from outside the Chip. It is
connected to the SI port of the unit cell. Test data entering the SI input subsequent devices in
the scan path is derived either from the Q-Output of the immediately previous state or via an
inverter from the XQ-output.
SOl is the only one of the scan test ports that may be used for another function. The designer
may also use SOl as a principal input by paralleling the user input with the scan data input.
7. SOO is the serial data output port from the last device of the scan-configured shift register to the
environment outside the Chip. Test data from SOO is taken from the Q-output of the last stage
(or from the XQ-output via an inverter) of the giant scan shift register. SOO is the only one of
the scan test ports whose location is not fixed; SOO may be placed by the deSigner at any
convenient location.
4.9.4 Scan Test Modes

Scan testing consists of two modes of operation: SISO (Scan inpuvscan output) mode and TC (test clock)
mode. Sequential logic is primarily addressed by SISO and combinatorial logic is addressed by TC; the
two modes are alternated during the scan test.
The SISO Mode

This mode causes all elements of the scan path to be written to and read from. In this mode of operation,
the following occurs:
1-77
CMOS Channel/ess Gate AlTBys Design ConsideraUons
a.The scan SISO path is activated by making XSM = 0

b.The scan clocks XACK and BCK are supplied
c.The data to be written is supplied to SOl serial data input
d.The data is read out of SDO and compared with the expected values
These writing and reading operations are performed in parallel.
The TC Mode
This mode tests the array as a normally configured device, but the data is clocked by special clocks
provided to the gate array by the LSI tester. In this mode of operation, the following occurs:
a. The scan SISO path is disabled by making XSM = 1.
b. All normal system clocks are disabled, forcing the clock inputs (CK) of all scan unit cells to a
logic low.
c. Input signals are applied to normal input pins principal inputs.
d. The TC system clock, XTCK, is applied to the unit cells' IH-inputs.
e. Output signals are read from normal output pins principal output and compared with the
expected values.
The alternation of these two modes allows the correct functioning of logic elements not directly accessible
from a principal input to be verified. The data scanned in is especially useful in providing control inputs to
otherwise difficult-to-control internal logic. Prior to the input of the data to the scan path, some detectable
faults can be observed externally by application of inputs to some non-scan external inputs. After data has
been clocked into the scan path, other detectable faults can be observed extemally. The remaining
detectable faults are observable extemally after the data has been clocked into the scan path, the TC
system clock (XTCK) has been applied, and the resultant data shifted out of the scan path.
4.10 Compiled Cell Testing

Compiled cells (RAM and/or ROM) are tested by accessing the cellI/Os from principal inputs and principal
outputs. Some designs may have the data inputs and outputs, the address lines, Read Enable, Write
Enable, etc., connected directly to principal inputs and principal outputs, making the test of such macros
very straightforward. In most designs, however, some or all of the above are embedded deep in the
design, the input signals being derived either from other RAMs or ROMs or from the digital logic unit cells.
To gain access to these RAM or ROM I/O ports, the designer must build test access circuits with input and
output selectors around the macros.
With the test access circuits in place, Fujitsu prepares the test vectors for all RAM compiled cells.
In the case of ROM compiled cells, Fujitsu tests to determine that the permanently stored data pattern
specified by the designer is properly stored and accessible. The deSigner, therefore, prepares all ROM
test vectors.
Test Signals from the LSI tester access the RAM and/or ROM macros through principal inputs and
principal outputs, and are usually multiplexed with the designer's logic. The multiplexing is accomplished
by means of the input selectors and output selectors. Input and output selectors allow the LSI tester to
access the deSigner's logiC or the compiled RAM or ROM cells individually to perform the appropriate
tests.
Compiled cell testing can take place whether or not scan path testing has been implemented in the design
and dedicated scan I/O pins assigned.
1-78
Delay Estimation Principles CMOS Channelless Gate Arrays
Chapter 5 - Delay Estimation Principles

5.1 Introduction
5.2 Choosing Critical Paths
5.3 Load Unils and Loading Guidelines
5.4 The Delay Equation
5.5 Estimating Gate Delay
5.6 Estimating Total Circuit Delay
5.7 Delay Calculations when Load Exceeds CDR
5.8 Clock Loading
5.9 Delay Multipliers
5.10 Calculation of Array Power Dissipation for Delay Multipliers
5.11 Calculating Delays for Test
5.12 Delay Parameters for Compiled Cells
5.1 Introduction
III
This section of the data book gives an overview of the delay estimation principles important to the design
of an ASIC using Fujitsu's channelless CMOS gate array technologies. Included are the loading rules for
AU and CG21 gate arrays and a demonstration of how to estimate the delay through a circuil. In addition
to the basic delay equation, this chapter also considers the loading limitations for clock signals and the
effects of the operating environment on typical delay figures.
5.2 Choosing Critical Paths
A crilical path is a logic path whose timing requirements must be satisfied to ensure proper system
function. In an ordinary synchronous CirCUit, data propagates from one register through combinatorial logic
into another register. For the circuit to function properly, the sum of the clock-to-Q delay of the source
register, the propagation delay through the logic, and the set-up time on the target register must be less
than the worst-case system clock skew. Correct timing of the Signal along the crilical path guarantees that
this condilion is met.
Usually, the critical path is the one with the greatest number of gate levels. However, if such a path is
speeded up by redesign, another, less complex path may become the new critical path.
For example, in a design in which a path has eight levels of gating, the designer may determine upon
inspection that two groups of NAND-NAND structures can be changed to AND-OR inverter cells, an
efficient CMOS implementation that noticeably increases the speed of the path. In this case, after applying
DeMorgan's theorem and reducing the result, the designer finds that another path is now the critical path.
Since each logic state sensilizes different branches, logic paths must be analyzed using the inputs (rising
or falling) that will actually be applied to them (since rising and falling delays are not equal) to determine
the longest path that will be sensitized and ensure that it meets critical path requirements.
In this section, a path delay calculation is worked through to show how a designer can analyze each
element of a Fujitsu CMOS circuil to make sure the design meets critical path requirements. In this
example, the effect of a rising input on the sample circuit is calculated as it would be if this were a crilical
path and the rising input were forcing the transition of interest.
1-79
CMOS Channelless Gate Arrays Delay Estimation Principles
5.3 Load Units and Loading Guidelines
The Fujitsu CMOS load unit (Iu) is the input capacitance of an inverter used as the basic unit for
measurement and calculation of capacitive loads presented to unit cells within the gate array. Both the
output drive factor of a unit cell and its input load factor are defined in terms of load units.
5.3.1 Output Drive Factor (CDR)
The output drive factor (CDR) is a parameter expressing the load driving capability of a unit cell. The
output drive factor is provided in the Unit Cell Library for each unit cell in load units. Unit cells can drive
loads greater than the output drive factor; however, the performance of CMOS circuits degrades
exponentially with increased loading. If too great a load is driven, an exaggerated increase in delay
through the unit cell may be experienced.
It is permissible for the load to exceed CDR if the associated additional delays are anticipated and
tolerable. Additional calculation factors are required to estimate delays of loads greater than CDR.
Figure 5-1 indicates the delays that may be generated when the load exceeds these guidelines.
lpel
(ns)
to
o
o COR 2C OR 3C OR 4C OR C(lu)
TOlal Load (C)
Figure 5-1. Delay Time vs. Loading Factor
5.3.2 Input Load Factor
The input load factor is the value in load units of the load placed on a network by the connection of the
input of the unit cell in question. The input load factor for each unit cell is provided in the Unit Cell Library.
5.3.3 Total Input Load Factor (NF/O)
The total input load factor or fanout (NF/O) is the sum of the input load factor of each of the unit cells
connected to the output of the unit cell in question.
5.3.4 Total Unit Cell Load
The delay factor of each unit cell is made up of two types of capacitive loading:
a. Load capacitance inherent in the input of each cell it must drive (NFIO)
b. Load capacitance due to the metal interconnection of the unit cells (CLl
1-80
The total load (C) presented by a unit cell is estimated by adding the total cell input load or NF/o (the input
loading factors of all other cells connected to the output network of the cell in question) to the total metal
load (CLl,
5.3.5 Number of Driven Inputs (NOI)
The total metal load (CLl depends on the number of driven inputs (NOI), that is, the number of other cells
to which the output of the unit cell in question is connected. Given the value of NOI a value for CL is
available from the Estimation Tables for Metal Loading in Appendix C of the applicable Unit Cell Library
(reprinted in Sections 2 and 3 of this Data Book). For each value of NOI, CL varies according to
hierarchical level of the cell in question (Level 1 , Level 2 etc.) and to its functional logic block status as a
main block or a subblock.
5.3.6 Networks
A network or net is considered to be the metal wiring that connects the output of a unit cell to the input(s)
of all unit cells that it is driving. Interconnect metal refers to the metal wiring, also called routing metal, that
makes up each network. Networks that are not connected to any unit cell clock input are generally
classified as data networks and are limited to a maximum load of 3 CDR or 72 lu. It is good design practice
III
to limit loads on data networks to less than 2 CDR during the design phase, otherwise the load may
exceed 3 CDR after chip layout.
A network that is connected to the clock input of any unit cell is classified as a clock network and is limited
to a maximum load of CDR. A prudent designer will limit loads on a clock network to much less than CDR.
5.3.7 Functional Logic Blocks
In the interest of optimizing critical paths and minimizing interconnect wiring length, logic is divided into
functional logic blocks to facilitate unit cell output loading calculation. A block is regarded as a main block
or a subblock with respect to a given signal net.
A main block has all of the following:

• the complete network
• the unit cell or block driving the network
• all unit cells or blocks driven by the network
A subblock has some, but not all, of the above characteristics and is a component part of the main block.
The assignment of main block and subblock designations to segments of a circuit facilitates the notation
of inter- and intra-hierarchical propagation of signals. The delay values given in the Estimation Tables for
Metal Loading (appended to the Unit Cell Libraries) are different for main blocks and subblocks, owing to
the difference in the estimated average path lengths encountered in each.
5.4 The Delay Equation
The basic delay equation combines the AC parameters of a cell and its associated capacitive loads to
estimate the delay time through the cell. The rise and fall time of a unit cell may not be symmetrical due to
differences in the transconductivity of the Nand P transistors as well as to differences in the arrangement
of the transistors to form unit cells. The same equation is used with different variables for positive-going
and negative-going signals at the unit cell output. These signal polarity variables must be considered
separately.
1-81
CMOS Channellsss Gale Anays Delay Estimation Principles
~ .. bJe + KcLup(NFIO + CL)

bt = ~ + KcLdn(NFIO + CL)
where:
tlxx is the circuit delay through the unit cell under no-load conditions (a value given in ns for
each cell In the unit cell library).
KcLxx is the load derating constant or delay time per loading unit conversion factor (ns/pF) (a value
defined for each unit cell in the unit cell library).
NFIO is the sum total of the Input loads of all unit cells driven in the network (expressed in load
units).
Ct. is the amount of loading. in load units. on the unit cell output due to interconnect metal
(metal load).
5.5 Estimating Gate Delay
Figure 5-2 shows a sample circuit for the purposes of demonstrating how the total accumulated delay
(tpd) through a short path is estimated.
A B c D
INo--+-~
OUT
V2B
t t
Figure 5-2. Delay Path Sample Circuit
Ordinarily a deSigner looks up the the specifications of each unit cell in the unit cell library of the
applicable technology. For this example. however. all of the necessary specifications have been
assembled in Table 5-1. using the values for AU technology.
Table 5-1. AC Parameters of Unit Cells
Basic Input Output Propagation Dalay Time

Cell
Function
Cell
Name
Cells
Used
Load
Factor
Drive
Factor to
t ..
KcL "'.
to KcL
2-lnputNOR R2K' 2 2 36 0.36 0.11 0.36 0.05
2-lnput NAND N2N 1 1 18 0.30 0.13 0.45 0.11
3-lnput NAND N3B' 3 1 36 1.03 0.07 1.36 0.03
Inverter V2B 1 2 36 0.20 0.07 0.20 0.04
, These are high drIVe cells that operate faster than their low dnve equivalents under these circumstances.
The delays for rising (~) and falling (bt) edges of a pulse can differ widely. Digital pulses are either
lengthened or shortened while passing through a unit cell. It Is therefore important to calculate the pulse
1-82
Delay Estima~on Principles CMOS Channel/ess Gate A"ays
width variations along the entire signal path to verify that pulse width is sufficient to pass through each
gate.
In the example that follows, based on Figure 5-2, calculations are based on a rising pulse entering the
input of unit cell A and changing state several times as it proceeds through the sample circuit. To find the
total delay for the circuit, it would be necessary to calculate the values resulting from the opposite case, in
which a falling pulse enters the circuit at unit cell A.
5.5.1 Delay Parameter for Rising Edge (~p)
The unit cell library shows that the delay time (~) for an upward transitioning signal at the unit cell output
(~p) for R2K, a 2-input NOR. is 0.36. It shows that the load/delay conversion factor for an upward
transitioning signal (KcLup) for R2K is 0.11.
5.5.2 Number of Fan-outs (N,o/O)
The sample schematic in Figure 5-2 shows that the NF/O, the number of cells that the R2K must drive, is
one (an N2N). The unit cell library shows that the N2N has an input load factor of 1 lu.
5.5.3 Number of Driven Inputs (NOI) and Metal Load (Cl)
The value for Ct. is based on the number of inputs the cell in question must drive and is derived from the
Estimation Tables for Metal Loading appended in this Data Book to each unit cell library. Table 5-2 is a
sample metal load table for a 50KAU device at the sub-block level. Each technology and device has
unique load/delay characteristics and the AU and CG21 technologies further divide loading values into
main block values and subblock values and then into values for each hierarchical level. Since this sample
circuit is very small, it will be assumed to be at a Level 4 in a subblock in the design hierarchy. Because
the number of driven inputs (or NDI) for R2K, N2N, and V2B in Table 5-2 is one, the amount of loading
due to metallization (CLl is 1.0 lu. The NDI for N3B in Table 5-2 is three; therefore the Ct. is 2.8.
Table 5-2. Estimation Table for Metal Loading
C-50KAU (Subblock)
CL(lu)
NO!
LEVEL 1 LEVEL 2 LEVEL 3 LEVEL 4
1 4.7 3.3 2.2 1.0
2 8.6 6.1 3.9 1.9
3 12.6 8.9 5.7 2.8
4 15.2 10.8 7.0 3.4
5 17.2 12.2 7.8 3.8
6 18.8 13.3 8.6 4.2
7 20.6 14.8 9.5 4.7
8 21.8 15.5 9.9 4.9
9 22.5 15.9 10.2 5.0
10 23.1 16.4 10.5 5.2
11 23.1 16.4 10.5 5.2
12 23.4 16.6 10.7 5.2
13 23.9 16.9 10.9 5.3
14 24.5 17.4 11.2 5.5
15 24.5 17.4 11.2 5.5
16-30 26.8 19.0 12.2 6.0
31-50 31.1 22.1 14.1 7.0
51-75 32.1 22.7 14.6 7.2
76-100 35.5 25.2 16.1 8.0
1-83
CMOS Channalless Gate Amlys Delay Estimation Principles
The value given for Ct. in the Estimation Tables for Metal Loading is an estimate of the loading effect of
the metalization capacitance on the output based on Fujitsu's careful statistical analysis of typical designs.
Actual metal loading is based on the effect of the routing and therefore may vary from these estimates. To
compensate for this uncertainty, Fujitsu incorporates a ±5% variation into the pre layout delay multipliers.
After routing, another set of simulations is run to verify the effect of the actual metal routing.
Additional metal loading tables in the Design Manual provide delay values for signals passing between
exterior and interior I/O cells and for such signals routed through the heavier metal interconnect wiring
required by high frequency signals.
5.6 Estimating Total Circuit Delay
Based on the values from Table 5-1 and Table 5-2, the propagation delay for R2K in the sample circuit is:
tdn(A) = fodn + KOLein (NF/o + CL)

tdn 0.36 + 0.05 (1 +1.0)
tdn 0.36 + 0.05 (2.0)
tdn 0.36 + 0.10
tdn 0.46
tdn(A) 0.5 (rounded up to the next O. 1 ns)
The propagation delay for N2N, found by following the same procedure, is:
tup (8) = tOup + KCLup (NF/o + CL)

tup =0.30 + 0.13(1+1.0)
tup = 0.30 + 0.13 (2.0)
tup = 0.30 + 0.26
tup = 0.56
tup (8) = 0.6 (rounded up to the next O. 1 ns)
The propagation delay for N3B, found by following the same procedure, is:
teln(O) = tOdn + KCLeIn(NF/o + CL)

teln = 1.36 + 0.03 (3 + 2.8)
teln = 1.36 + 0.03 (5.8)
teln = 1.36 + 0.174
teln = 1.534
teln (0) = 1.6 (rounded up to the next 0.1 ns)
The propagation delay for V2B, found by following the same procedure, is:
tup (DJ = tOup + KCLup (NF/o + CL)

tup = 0.20 + 0.07 (1 + 1.0)
tup = 0.20 + 0.07(2.0)
tup =0.20 + 0.14
tup = 0.34
tup(D) 4 0.4 (rounded up to the next O. 1 ns)
Therefore, the total delay for the sample circuit shown in Figure 5-2 is:
tpd tdn (A) + tup (8) + tdn(C) + tup(O)

tpd 0.5 + 0.6 + 1.6 + 0.4
tpd 3.1 ns
1-84
5.7 Delay Calculations When Load Exceeds CDR
Fujitsu CMOS gate arrays are capable of driving loads beyond their published Output Drive Factor (CDR).
It must be emphasized, however, that the delays that result from this practice are considerably increased.
Unit cells may be loaded beyond their CORS provided that the increased delay is acceptable.
Anticipation of the effects of loading beyond the published COR requires recalculation of delay. The
general formulas for loading beyond CDR are listed below; different delay equations must be used
depending on the degree that the loading exceeds CDR.
The Sea-of-Gates technologies, AU2 and CG21, require two additional parameters to "fine-tune"
calculations of unit cell delay under conditions of very light loads. These parameters, COR2 and KC12 are
defined for some selected unit cells.
COR2: Initial output driving factor-if undefined, then COR2= 0)
KCL2: Initial delay time per load unit-if undefined, then KC12= 0)
When C is CDR or less:
When C is between COR2 and CDR:

tpd = to + KC12 * COR2 + KCL * (C - COR2)
When C is between CDR and 2COR:
tpd=to+KCL2* COR2 + KCL* (COR-COR2)+ 1.5KcL* (C-COR)
When C is between 2COR and 3COR:
tpd= to+ KCL2* COR2+KcL* (COR-COR2) + 1.5KcL* COR + 3KCL* (C-2COR)
5.8 Clock Loading
It is acceptable, though not a recommended design practice, to load the output of a unit cell that does not
carry a clock signal beyond its Output Drive Factor (CDR). To ensure maximum clock accuracy, however,
unit cells that output clock signals must never be loaded beyond CDR. Having different loading limitations
for clock and non-clock unit cells can lead to "race conditions," in which the clock signal arrives at a
flip-flop before the data signal set-up time has elapsed. It is therefore most important, when loading a unit
cell beyond CDR, to modify the fundamental delay equation using the extra delay factors explained in the
previous section.
5.9 Delay Multipliers
The delay times considered so far are typical delays derived from typical unit cell data. Typical data,
however, does not take into account the environmental, thermal, and electrical variations of the real world
operating environment. It is necessary, therefore, to simulate worst-case conditions during the simulation
and test phases of circuit design. Revised estimates of delay under these harsher circumstances may be
arrived at by multiplying the typical delay figures by delay multipliers.
5.9.1 Operating Environment
The operating environment of the array can cause variations from the calculated typical delay figures.
Influencing factors include ambient temperature, applied voltage, and variations in the manufacturing
processes. Figure 5-3 shows how supply voltage and temperature affect the performance of a sample
array when temperature or supply voltage varies beyond the published operating condition specifications
for the device. The actual multipliers used depend on the device type.
1-85
Propagation Delay vs.

Propagation Delay vs. VDD
Ambient Temperature
(normalized) (normalized)
1.4 1.4
1.3 '1.3
1.2 i'.. 1.2
V'"
i""'.. ..".,,-
1.1 ....... 1.1
tpd
(ns) 1.0
~ tpd
(ns) 1.0
~
0.9
r---.. ..... 0.9
~
........ r-
0.8 0.8
0.7 0.7
0.6 0.6
4 4.5 5 5.5 6 o 25 75 100

Voo(V)
Figure 5-3. Operating Environment Factors Influencing Delay
Maximum and minimum pre-layout simulation delays are derived from delay multipliers applied to the
calculated typical delays. Post-layout simulation delay multipliers are based on the capacitance of the
actual metalization routing calculated as a function of the layout program.
5.9.2 Minimum and Maximum Delay Factors
Minimum/maximum delay factors for AU and CG21 technologies CMOS gate arrays are as follows:
Minimum Maximum
5V±5%,~OC 5 V ±5%, s60°C
Pre-Layout 0.35 1.S5
Post-Layout 0.40 1.55
5.9.3 Factors Affecting Maximum Delay Multipliers
The normal operating temperatures of most arrays. however. will be in excess of SO°C and therefore the
delay multipliers for maximum pre- and post-simulation delays must be scaled by junction temperature
factors.
Junction temperature is a function of the power dissipated by the array. the thermal resistance of the
package selected for the die. and the maximum ambient temperature. The power dissipated by the array
becomes a serious consideration in AU and CG21 technology because the gate count and the operating
speed of these gate arrays are appreciably higher than those of earlier. channeled arrays.
1-86
Delay Estimation Principlas CMOS Channellass Gate Arrays
5.9.4 calculating Junction Temperature (TO
The junction temperature of an array is determined by the following formula:

Junction Temperature (Ti) = TallAX + Gja * Pd ('C)
The factors affecting junction temperature are as follows:
TallAX = the maximum expected ambient temperature (OC)
Gja the thermal resistance of the package (OC/W)
pdthe power dissipated by the array (W)
Maximum Ambient Temperature
The maximum expected ambient temperature (Tamax) must be determined by the designer from the
application.
Package Thermal ReSistance (Gja)
The maximum junction temperatures for AU gate array packages are as follows:
Ceramic packages: 150°C
Plastic packages 125°C
The thermal resistance (Gja) of the chosen package type should be able to dissipate enough power so that
the junction temperature (~) does not exceed the maximum junction temperature capability of the
package.
Table 5-3 lists the thermal resistances of the larger AU and CG21 gate array PGA packages.
Power Dissipation
The method by which the designer determines the power dissipated by an array is discussed in the
following section. .
1-87
CMOS Channs/less Gate Anays Delay Estimation Principles
Table s-3. Package Thennal Resistance In ·C/W
Package Part Number Array Size Air Flow (meters/sec.)

0 1 3
MB630K C-l00KAU
MB631K C-75KAU
PGA-135 MB632K C-50KAU 30 20 15
MB633K C-40KAU
MB634K C-30KAU
MB630K C-l00KAU
MB631K C-75KAU
PGA-179 MB632K C-50KAU 25 19 13
MB633K C-40KAU
MB634K C-30KAU
MB630K C-l00KAU
MB631K C-75KAU
PGA-208 MB632K C-50KAU 23 17 12
MB633K C-40KAU
MB634K C-30KAU
MB630K C-l00KAU
PGA-256 MB631K C-75KAU 19 13 9
MB632K C-50KAU
MB633K C-40KAU
MB630K C-l00KAU
PGA-299 MB631K C-75KAU 19 13 9
MB632K C-50KAU
MB630K C-l00KAU
PGA-321 221024 161018 11 to 13
MB631K C-75KAU
MB630K C-l00KAU
PGA-361 221024 161018 111013
MB631K C-75KAU
PGA-401 MB630K C-l00KAU 221024 161018 111013
5.10 Calculation of Array Power Dissipation (Pd) for Delay MuHlpllers
The worst-case power dissipation of the gate array is the sum of the power dissipations of the individual
elemental groups of the array, multiplied by a factor (CIi) determined by the power supply variation
(tolerance). This factor, Cv, is 1.10 for a 5 V ±5% tolerance power supply. The individual elemental groups
of the design for which typical power dissipation must be calculated (in mW) are shown in Table 5-4.
Table 5-4. Power Dissipation calculation Factors

Functional Group Factor Name
1I0bufiers PIO
Intemallogic gates PG
RAM (compiled) cells PRAM
ROM (compiled) cells PROM
1-88
Delay Estimation Principles CMOS Channel/ass Gate Arrays
Typical power dissipation is calculated using the following formula:

Pr = P/O + PG + PRAM + PROM (mW)
Worst case power dissipation:
Pd=Pr * Cv(mW)
The formulas used to calculate each of these elements of typical power dissipation (P7) are listed in the
following sections. A table showing values for a representative range of design elements is given following
each formula.
I/O Buffer Power Dissipation (PIG)
In the calculation of PIO, both AC power dissipation (PAC) and DC power dissipation (PDC) must be
considered, as in the following formulation:
P/O = PAC + PDC (mW)
where
PAC is the active (or switching) power dissipation of an I/O buffer and Poc is the power dissipation of an
I/O buffer caused by loads sourcing and sinking current external to the array.
Estimation of I/O Buffer AC Power Dissipation (PAC)
The AC power dissipation is proportional to the number of I/O buffers switching each cycle at the
maximum switching frequency. A decimal factor representing the percentage of buffers switching in each
cycle is indicated in the equations below by an asterisk.
In the formulas for the derivation of PAC shown below, 0.20 is used for the percentage of buffers switching
in each cycle, reflecting Fujitsu's observation that in the average design, 20 percent of all buffers switch in
each cycle. If every buffer switched at the system frequency, this factor would be 1.00.
The AC power dissipation of input buffers = 0.110 mW/MHz

PACIN (mW) =0.11 * (total input buffer count) * f * 0.20
where f =the maximum system frequency

0.20 = fraction of buffers switching in each cycle
Table 5-5 shows a representative range of values for PACIN.
Table 5-5. Input Buffer AC Power Dissipation (PAClN) Examples (In mW)
Average Number Average Input Frequency

of Simultaneously
Switching Inputs 1 MHz 5 MHz 10 MHz 20 MHz 30 MHz 40 MHz
12 1 7 13 26 40 53
25 3 14 28 55 83 110
50 6 28 55 110 165 220
75 8 41 83 165 248 330
100 11 55 110 220 330 440
125 14 69 138 275 413 550
150 17 83 165 330 495 660
1-89
The AC power dissipation of output and bidirectional buffers =0.030 mW/MHz

PAcour (mW) = 0.030.. (total output buffer count).. f.. C.. 0.20
+ 0.030.. (total bidirectional buffer count).. f.. C.. 0.20
where f =the maximum system frequency
C = the output load capacitance in pF
0.20 = fraction of buffers switching in each cycle
Table 5-6 shows a representative range of values for PAcour.
Table 5-6. Output and Bidirectional Buffer AC Power Dissipation (PACOUT) Examples (In mW)
Average Number pF • MHz (per output)'

of Simultaneously
SWitching Outputs 31 63 125 250 500 850 1200
6 5.58 11.34 22.50 45.00 90.00 153.00 216.00

12 11.16 22.68 45.00 90.00 180.00 306.00 432.00
25 23.25 47.25 93.75 187.50 375.00 637.50 900.00
50 46.50 94.50 187.50 375.00 750.00 1275.00 1800.00
75 69.75 141.75 281.25 562.50 1125.00 1912.50 2700.00
'pF .MHz - SUM (loading for each pin In largest SSO group)' SUM (toggle frequency of each output
PAC = PACIN + PACOUr
Estimation of I/O Buffer DC Power Dissipation (Poe)
The DC power dissipation of input buffers is so small as to be considered negligible and is not calculated.
The DC power dissipation of output and bidirectional buffers is determined by the following formula:
Poe = Number of Output Buffers «Vll.. IOL.. tL) + (Voo - VOH) .. IOH.. tH) (Mw)
+ Number of Bidirectional Buffers «Vll.. IOl .. tl) + (VOO - VOH) .. IOH .. tH) (Mw)
where the terms VOL and (VDD - VOH) are typically assumed to be 0.30V, when used for the determination
of Poco The terms tH and tL are decimal numbers determined by the duty cycle of the output waveform.
They represent, respectively, the waveform's high and low periods.
Table 5-7 shows a representative range of values for POCOUT.
Table 5-7. Output and Bidirectional Buffer DC Power Dissipation (POCOUT) Examples· (In mW)
Average Number OUtput Drive Strength (loJ

of Outputs 3.2mA SmA· 12mA
25 36 80 100
50 72 160 200
75 108 240 300
100 144 320 400
125 180 400 500
150 216 480 600
175 252 560 700
'assumlng 50% duty cycle
1-90
Delay Estimation Principles CMOS Channel/ess Gate Arrays
5.10.2 Internal Gate Power Dissipation
The power-dissipation of one internal basic cell is 0.010 mW/MHz.

PG = 0.010 * n * f* 0.20 (mW)
where
n= the total number of basic cells used for internal logic design, including internal basic cells
for I/O buffers
t= the maximum system frequency
0.20 = factor reflecting Fujitsu's observation that in the average design, 20 percent of all buffers
switch in each cycle.
Table 5--8 shows representative range of values for PG.
Table 5-8. Internal Basic Cell Power Dissipation (PG) Examples
System Clock Frequency

Active Gates'
1 MHz 5 MHz 10 MHz 20 MHz 30 MHz 40 MHz
200 2 10 20 40 60 80
400 4 20 40 80 120 160
800 8 40 80 160 240 320
1600 16 80 160 320 480 640
3200 32 160 320 640 960 1280
6400 64 320 640 1280 1920 2560
12800 128 640 1280 2560 3840 5120
25600 256 1280 2560 5120 7680 10240
..
Note:'Actlve Gate count IS typically (Utilized gates). (Activity Factor) (usually 20%)
5.10.3 RAM Cell Power Dissipation
When the RAM enable input (RE) is at a logic high, the RAM is disabled and the power dissipated by the
RAM (PRAM) = 0 mW.
When the RAM enable input is at a logic low, the RAM is enabled and power is dissipated by the RAM.
Assuming that half of the address input terminals are switching at the RAM operating frequency (RAM, the
power dissipation of a RAM cell is determined by the following formula:
PRAM = (0.63 + (0.008 * wp) + (0.036 + (O.045/c)) * bp * tRAM
+ (7.5) + 01. 13/c) * bp * 1.2 mW
where
wp = the physical word length (in basic cells) of the RAM
c the columnar structure of the RAM (how many physical words wide it is)
bp = the physical bit size (in basic cells)
Table 5-9 shows a representative range of values for PRAM where tRAM = 25 MHz and c = 2.
1-91
CMOS Channe/less Gate Arrays Delay Estimation Principles
Table 5-9. RAM Macro ,Power Dissipation (PRAM) Examples
RAM Macro Power Estimate Table

Depth
Bit Width
4 8 16
32 40.45 57.45 91.45
64 43.65 60.65 94.65
128 50.05 67.05 101.05
256 62.85 79.85 113.85
512 88.45 105.45 139.45
1024 139.65 156.65 190.65
5.10.4 ROM Cell Power Dissipation
When the ROM enable input (RE) is at a logic high, the ROM is disabled and the power dissipated by the
ROM (PRoM) = 0 mW.
When the ROM enable input is at a logic low, the ROM is enabled and power is dissipated by the ROM.
Assuming that haH of the address input terminals are switching at the ROM operating frequency fROM, the
power dissipation of a ROM cell is determined by the following formula:
PROM = (0.81 + (0.007... wp) + (0.001 + (0.200/c))... bp... fROM
where
wp = the physical word length (in basic cells) of the ROM
c = the columnar structure of the ROM (hOW many physical words wide it is)
bp = the physical bit size (in basic cells)
Table 5-10 shows a representative range of values for PROM where fROM = 25 MHz and c = 2.
Table 5-10. ROM Power Dissipation (PROM) Examples (In mW)
ROM Macro Power Estimate Table

Depth
Bit Width
4 8 16
32 43.075 63.075 103.075
64 45.875 65.875 105.875
128 51.475 71.475 111.475
256 62.675 82.675 1222.675
512 85.075 105.075 145.075
1024 129.875 149.875 189.875
1-92
5.10.5 Determination of Maximum Delay Multipliers
Once the maximum junction temperature of the array has been calculated, Table 5-11 must be consulted
for the appropriate maximum delay multiplier.
Table 5-11. Maximum Delay Multipliers
Junction Pre-layout Post-layout

Temperature
(TJ) SV±S% 5 V±10% SV±S% SV±10%
Tjs.60°C 1.65 1.75 1.55 1.65
60°C <Tj s.70°C 1.70 1.BO 1.60 1.70
70°C <Tj s.BO°C 1.75 1.B5 1.65 1.75
BO°C <Tj s.90°C l.BO 1.90 1.70 l.BO
90°C <Tj s..1 05°C 1.B5 1.95 1.75 1.B5
105°C <lj s..120°C 1.90 2.00 1.80 1.90
120°C <lj s..130°C 1.95 2.05 1.B5 1.95
130°C <lj s..140°C 2.00 2.10 1.90 2.00
140°C <lj s.150°C 2.05 2.15 1.95 2.05
5.10.6 Determination of Minimum Delay Multipliers
The minimum delay multipliers are almost exclusively dependent on the range of ambient temperature.
For each ambient temperature range in which the gate array will be used, Table 5-12 shows the minimum
delay multiplier. The power supply variation from 5 percent to 10 percent has no noticeable effect.
Table 5-12. Minimum Delay Multipliers
Lowest Ambient Pre-layout Post-layout

Temperature
(TA) 5V±!i% 5 V±10% 5V±5% 5V±10%
°C<TA<70°C 0.35 0.35 0.40 0.40
-20°C <TA<70°C 0.30 0.30 0.30 0.30
-40°C <TA<70oC 0.25 0.25 0.25 0.25
-4Q°C <TA<85°C 0.25 0.25 0.25 0.25
-55°C <TA<125°C 0.20 0.20 0.25 0.25
1-93
CMOS Charme//sss Gate Armys Delay Estimation Princip/ss
5.11 Calculating Delays for Test
5.11.1 Pre-layout Delay Calculations for Delay Test (AC Test)
The minimax delays for the delay test are determined by taking the sum of the typical delays and
multiplying it by the appropriate minimum or maximum delay factor. The maximum delay figure must be
rounded up to the next highest 0.1 ns, while the minimum delay figure must be rounded down to the next
lowest 0.1 ns. The equation shown for typical delay calculation is repeated here and also shown in its
modified form. The delay factors used are those for pre-layout in the AU and CG21 technologies. For
simplicity's sake, the maximum delay multipliers in this example are unmodified by junction temperature
factors. The figures used in this example are those derived from the delay calculations for the sample
circuit in Figure 5-2 at the start of this chapter.
Typical delay:
ted = 0.5 + 0.6 + 1.6 + 0.4 =3.1 ns
Maximum delay (rounded upto 0.1 ns):

fed = (0.5 + 0.6 + 1.6 + 0.4) x 1.65 = 5.115 = 5.2 ns
Minimum delay (rounded down to 0.1 ns):
tpd= (0.5+ 0.6+ 1.6+ 0.4) x 0.35= 1.085= 1.1 ns
5.11.2 Pre-layout Delay Calculations for DC Test, Function Test, and High Impedance Test
The minimum and maximum delays for these tests are determined by multiplying the typical delays for
each cell individually by the delay factors. The resulting figures for both maximum and minimum delays
are rounded up to the next 0.1 ns for each cell. The final figures for each unit cell of the path are totaled.
The delay calculation used earlier is repeated here and is also shown calculated for the DC, Function, and
High Impedance tests. The delay factors used are those for pre-layout in the AU and CG21 technologies.
Typical delay (rounded up to 0.1 ns):

fed = 0.5 + 0.6 + 1.6 + 0.4 =3.1 ns
Maximum delay (delay for each gate rounded up to the next 0.1 ns):
fed = (0.5 x 1.65) + (0.6 x 1.65) + (1.6 x 1.65) + (0.4 x 1.65)
= 0.825 + 0.99 + 2.64 + 0.66
= 0.9+ 1.0+2.l+0.l=5.3ns
Minimum delay (delay for each gate rounded up to the next 0.1 ns):
fed = (0.5 x 0.35) + (0.6 x 0.35) + (1.6 x 0.35) + (0.4 x 0.35)
= 0.175 + 0.21 + 0.56 + 0.14
= 0.2+0.3+0.6+0.2= 1.3ns
Minimum/maximum delays are also calculated this way for minimum clock pulse width, minimum data
set-up time, minimum data hold time, preset timing, and clear timing. The values of the maximum and
minimum delay multipliers shown above apply to pre-layout calculations only; different factors are used for
post-layout analysis.
1-94
Delay Estimation Principles CMOS Channel/ess Gate Arrays
5.12 Delay Parameters for Complied Cells
5.12.1 Complied Cell Construction
The compiled cell is a RAM or a ROM that is automatically generated by Fujitsu-proprietary compilers. It
is recommended that no more than four compiled cells be employed within a gate array. Since the
compiled cell is a hardware macro, it is important that its dimensions allow it to be placed within the area
of the basic cell matrix. It is also required that the remainder of the basic cell matrix be left as close to
rectangular as possible (no T- or L-shapes) to facilitate the automatic routing of unit cell interconnections.
Space must also be reserved along the outer edges of the macros for internal 1/0 cells. Unused address
inputs of all compiled cells and unused data input terminals of RAM must be tied low to ZOO cells.
5.12.2 Complied Cell Configuration
..
The macro's logic parameters must be converted to physical parameters in order that the macro be laid
out in the most efficient manner. The resulting compiled cell, or macro, will be physically distributed across
a number of columns of basic cells and, within limits, may be one, two, four, or eight words wide,
regardless of the number of bits per word.
This columnar configuration (the width of the memory matrix in words) is referred to as the "c" value for
the purposes of this discussion. This c value determines the physical (in basic cells) word and bit length
(not logical length). In many cases, more than one value of c can be used, allowing alternate
configurations of the macro. For example, Table 5-13 below shows the allowable c values for single- and
dual-port RAM. For a 256 (word) x 8(bit) RAM, any value (c = 1 through c = 8) can be used.
Table. 5-13. Sing le- and Dual-pon RAM Columnar Configurations
Number of
Number of Words Bits/Word cValue
4to 256 81072 1
810512 41036 2
16101024 21018 4
32102048 1109 8
Procedures detailed in the Design Manual allow the size of the phYSical word, the size of the physical bit,
the basic cell count, and the number of address lines needed to be derived from the c value.Table 5-14
below illustrates the calculated parameters for a single-port 256 x 8 RAM.
1-95
CMOS Channe//ess Gate AITBYS Delay Estimaffon Principles
Table 5-14. calculated Parameters for Slngle·Port 256 x 8 RAM
cValue
Parameter Symbol 1 2 4 8 Unit
Physical Word wp 256 128 64 32 BC
Number of Address Lines t 8 8 8 8 units
Physical Bit bp 8 16 32 64 BC
Total Basic Cells - 6000 4592 4392 5016 BC
X-Dimension X 20 28 44 76 BC
V-Dimension Y 300 164 98 66 BC
Power Dissipation P 89.9 158.2 302.5 595.0 mW
The optimum configuration must be determined by the requirements of the design itself. As the table
above shows, a macro configured with a smaller c value will use more basic cells but will require less
power dissipation than a macro configured with a larger c value. The difference in power consumption at
each end of the spectrum of possible configurations varies much more widely than does the difference in
the number of basic cells used.
If the array design contains compiled cells, additional delay parameters, set out in full in the appropriate
Design Manual, must be added to the basic delay equation explained in the previous section. Table 5-15
below shows the delay parameter for a single-port 245 x 8 RAM. As the table shows, the columnar
configuration (c value) of a compiled cell has minimal influence on the basic delay times of the macro.
1-96
Delay EstimaNon Princip/as CMOS Channel/ess Gate Arrays
Table 5-15. Delay Parameters for a Single-Port 256 x 8 RAM (AU Series)
Chosen Value of "e"

Parameter Symbol
1 2 4 8
i
Read Cycle Time tAc 21.72 21.44 21.41 21.37
Address Access Time 20.79 20.64 20.65 20.71
apr
tAA
RAM Enable Access Time 19.79 19.71 19.68 19.83 Read

tAA
Output Hold from Address Change 5.95 5.84 5.94 6.34
toH
Output Hold from Enable Change 2.85 2.86 2.87 2.90
tAH
Write Cycle Time 21.72 21.44 21.41 21.37
twe
Enable to End of Write 15.27 14.94 14.87 14.88
tAW
Address Valid to End of Wr~e
Address Setup Time
Write Pulse Width

tAW
tAS
twp
18.57
3.30
11.82
18.24
3.30
10.94
18.17
3.30
10.54
18.18
3.30
10.38
1 III
Write
Operation
Data Setup Time tow 10.17 9.28 8.84 8.61
Write Recovery Time
Data Hold Time
Frequency of Operation: 5MHz

tWA
tOH
3.15
3.59
3.14
3.66
3.19
3.81
All un~s
3.24
4.11
are In ns
1
1-97
CMOS Channe/less Gate AlTars Delay Eslimalion Principles
1-98
CMOS Channe//ess Gat" Arrays Quality and R"/iabi/iry
Chapter 6 - Quality and Reliability

6.1 Introduction
6.2 Engineering Testing
6.3 In-process Inspection and Quality Control
6.4 Reliability Theory
6.5 Reliability Testing
6.6 Test Methods and Criteria
6.1 Introduction
Fujitsu's integrated circuits work. The reason they work is Fujitsu's single-minded approach to built-in
quality and reliability, and its dedication to providing components and systems that meet exacting
requirements allowing no room for failure.
Fujitsu's philosophy is to build quality and reliability into every step of the manufacturing process. Each
design and process is scrutinized by individuals and teams of professionals dedicated to perfection.
10
The quest for perfection does not end when the product leaves the Fujitsu factory. It extends to the
customer's factory as well, where integrated circuits are subsystems of the customer's final product.
Fujitsu emphasizes meticulous interaction between the individuals who design, manufacture, evaluate,
sell, and use its products.
Quality control for all Fujitsu products is an integrated process that crosses all lines of the manufacturing
cycle. The quality control process begins with inspection of all incoming raw materials and ends with
shipping and reliability tests following final test of the finished product. Prior to warehousing, Fujitsu
products have been subjected to the scrutiny of man, machine, and technology, and are ready to serve
the customer in the designated application.
1-99
Quality and Reliability CMOS Channelles Gate AITSYs
Process
Inspection 01 Incoming Material

Check Items Waler Processing
InsJl8C1!ion of Wafers,
MasKs, Packages, Piece DiffusiOn/Ion Implantation
Parts, Chemicals, Etc
Wafer Surface Inspection and Photoetching
Sample Tests of Thickness,
Surface Resistance, Diffusion
Depth, Electrical Parameters, and Doping
Wafer Surface and Pattem Inspection
Wafer Surface Inspection, Passivation (Insulating Layer Formation)
Monitor Test of Film Thickness
Wafer Surface Inspection,
Monitor Test of Film Thickness
Wafer Shipping Inspection
Test of Electrical Characteristics, Stress Test
Dicing (CHIP Separation)
Wafer Surface and Pattem CHIP Selection

Sampling Inspection
CHIP Shipping Inspection
Sample Surface Inspection
Bond-Welling and Surface Inspection, Monitor Test 01 jot un

for Machine Calibration Pre-Cap Visual
Bond-Position and Surface Inspection, Sample Wire Bond Strength Test, Inspection
Monitor Test of Sample run for Machine Calibration
Intemal Visual Inspection Intarnal Merchant
Inspection
Intemal Sampling Visual Inspection
Quality Control Processes at Fujitsu
1-100
CMOS Channel/ess Gate Arrays Quality and Reliability
Sealing or Molding
Aging (After Encapsulation)
leak Test (Hermetic Package Only)
Fine and Gross leak Tests
External Sampling Visual Inspection
External Visual Inspection

Curing
External Visual Inspection
External Mechanical Inspection

..
Shipping Tests
Test of AC/DC Characteristics and Functions
Reliability Tests
Hermeticity (Fine and Gross leak Tests), External and Marking Inspections,......./
Electrical Characteristics Tests, All Sampling Tests U lot Tests/Periodic Tes
legend:
Endurance and Environmental Tests 0 Warehousing
o Production Process
o TesVlnspection
IQI Production Process

and TesVlnspection
<>
Note:
QC Gate (Sampling)
The flow sequence may vary slighUy

with individual product type.
Quality Control Processes at Fujitsu (Continued)
1-101
Quality and Reliability CMOS Channe/fes Gate Arrays
6.2 Engineering Testing

Engineering testing is the heart of reliability and quality control. The reliability engineering department
plans and performs most engineering testing. Whenever a device is developed, it must undergo
engineering approval tests. After the device passes these tests, production engineering approval tests are
performed on a representative sample of the device. All factors that could influence production of the
device are examined. Only if all conditions are favorable and the device passes thorough testing, can the
new device go into production.
Tables 6-1 a through 6-1d show a sampling plan for engineering testing. These tests are in compliance
with MIL-STD-883, Class B. When a change in production (e.g., a material change) is needed,
engineering tests are performed on specific items for the change.
Since the representative samples tested must accurately reflect the reliability of the device,the following
conditions must also be satisfied: the functions performed by the same basic circuit; the same processing
techniques, materials, parts and packages used; and the same processing followed at the same factory.
Table 6-1a. Sampling Plan for Engineering Testing: Endurance Test

Test Items MIL-$TD-883 LTPD· Acceptance Note
(%) numb....•
High-temperature storage lS00C l008C 7 1

High-temperature continuous operation l00S0 7 1
150°C or 12SoC
High-temperature continuous operation 12SoC lOSS 0 S 2
Low-temperature continuous operation -5SoC (10SSCorO) 7 1 As applicable
High-temperature high-humidity storage - 7 1 Plastic package only
85°C,85%RH
High-temperature high-humidity continuous (l00S CorO) 7 1 Plastic package only
operation 85°C, 85% RH
Lot test percent defects
Number of failures permitted per lot
- 1-102
CMOS Charme//ess Gate Arrays Quality and Reliability
Table 6-1b. Sampling Plan for Engineering Testing: Environmental and Mechanical Test
T••tltema MIL-STD-883 LTPD Acceptance Note

(%) number
External visual inspection 2009 15 1 Same sample

Physical dimensions 2016 15 1
Radiophotography 2012 3 devices 0
Intemal visual inspection 2013 15 0
Lead integrity: Devices which failed

Tension 2004 A 15 0 in electrical
Bending stress B 15 0 characteristics test
Lead fatigue B 15 0 are acceptable to
this test. Each test
is perfo,,",ed on one
third of the leads of
each sample.
Resistance to solderina heat - 7 1 Same sample
Temperature cycling 1010C 7 1
Thermal shock 1011 A 7 1
Vibration, variable-freauency 2007 A
Mechanical shock 2oo2B 10 1
Constant acceleration 2001 D
Hermetic package
Seal: (Fine and gross leak checks) 1014A 7 1 only
C 7 1
Resistance to solvents 2015 40 devices 1 Devices which failed

in electrical
characteristics test
are acceptable to
this test.
Solderability (260°C) 2003 15 1 Devices which failed

in electrical
are acceptable to
this test.
Solderability (230°C) - 15 1 Devices which failed

in electrical
are acceptable to
this test.
Internal water-vapor content 1018 3 devices 0 Hermetic package

only
Electrostatic discharge sensitivity 3015A 15 1
Pressure-Temperature-Humidity Storage - 15 1 Plastic package only
(PTHS) 121°C, 2 atm.
1-103
Quality and Reliability CMOS Channelles Gate Arravs
The following tests are performed only when required or when requested by the customer.
Table 6-1c. Sampling Plan for Engineering Testing:
Environmental and Mechanical Test (Optional)
LTPD Acceptance
Testltems MIL.sTI).883 (%) number Note
Bond strength 2011 o (or C) 15 2 wires 34 wires/4 devices

Die shear strength 2019 3 devices 0 Hermetic package
onlv
Moisture resistance 1004 15 0
Salt atmosphere (corrosion) 1009 A 15 0
Vibration fatiaue 2005 15 0
Immersion l002B 15 0
SEM inspection of metallization 2018 3 devices 0
Particle impact noise detection (PIND) test· 2020 B 15 1 Hermetic package
onlv
Ud torque 2024 Frit sealed package
onlv. as applicable
Adhesion of lead finish 2025 As applicable
Table 6-1d. Sampling Plan for Engineering Testing: Continuity Test
LTPD Acceptance
Teslilem MIL·STI).883 (%) number Nole
Continuity check - 5 2 Plastic package only
6.3 In-process Inspection and Quality Control

Every department involved in the manufacturing process is responsible for the quality-control inspection in
its sphere of operation. In-process checks, sampling tests, and other inspections are assigned so that
each department has certain allotted tasks for which it takes full responsibility. This total control system
has rationalized overall operations dramatically.
6.3.1 In-process Checks (Including screening)

In-proces~ checks are performed after each step critical to the next process in wafer processing and
assembly. Defective or substandard products are weeded out at an early stage. Testing falls into the
following three categories:
(a) Probe testing, chip selection, and final testing. These are defined for each process.
(b) Voluntary checks. These include inspection of the wafer surface after window opening (before
the diffusion process) and inspection of the wafer surface after the metallization.
(c) 100 percent screening. This includes the aging and visual inspection performed during
wafer processing and assembly.
6.3.2 In-process Sampling Test

The in-process sampling test is performed as a part of process quality control. The Manufacturing ,and QC
departments check randomly drawn samples at key points in the manufacturing process to check process
and facility conditions. This helps in maintaining product quality at the customary high level. The following
items are checked in these sampling inspections or monitoring:
(a) Surface resistance after diffusion, film thickness, evaporated or sputtered electrode thickness,
and device characteristics
1-104
(b) Product quality (checked by visual inspection of the chip surface)

(c) Bonding machine calibration, visual inspection and bond strength after wire bonding, product
appearance, marking permanency
6.3.3 In-process Inspection

The Manufacturing and QC departments perform stringent quality checks between major processes to
ensure the highest quality. The following four types of inspections are performed:
(a) Incoming materials, parts, and chemicals Inspection
(b) Wafer shipping inspection
(c) Chip shipping inspection
(d) Shipping test
6.3.4 Lot Configuration

A "lot" consists of the same devices produced over a stated period, having the same design and using the
same processing techniques, materials, and production line. In addition to the Fujitsu logo, part number,
and other markings, each device is marked with a lot code as shown below.
Lolcode
xx xx
Last two digits of the year --=r """"L- Week cod.
6.4 Reliability Theory
6.4.1 Estimating the Failure Rate

The graph of a component failure distribution is usually a downward-bowed curve, often called the
bathtub curve (Figure 6-2). Life tests show that the instantaneous failure rate decreases with time and
graphs as a straight line on a Weibull probability chart (Figure 6-3). Shape parameter m, which shows the
instantaneous failure rate, is between 0.3 and 0.7. (In an exponential distribution, the instantaneous failure
rate does not change and m = 1. As m becomes smaller than 1, the instantaneous failure rate decreases
with time.)
Instantaneous
failure rate
I ::::~::aJlur. I Random lallure period I w..,_

failure period
TIME
Figure 6-2. Distribution of Component Failure
1-105
Quality and Reliabl7ity CMOS Channelles Gate Arrays
Usually, the failure rates during the initial and random failure periods are the most important for
semiconductors. Figure 6-3 shows an example of life test data graphed on a Weibull probability chart.
n
Cumulative -2.0 -1.0 0.0 1.0 2.0 3.0 4.0
failure
rate 99.9 2.0
99.0
95.0 1.0
90.0
70.0 0.0
50.0 -0.53
30.0 -1.0
~ Sample size: 855
l
20.0 Inln-l-
15.0 t-- Test temperature: 150°C l-F(t)
Test time: 1000 hrs. -2.0
1
10.0
F(t) 5.0 -3.0
[%]
3.0 m-l
~.O
-
Exponential distribution - -4.0
.5
.."
1.0
~ Q I>-"""" m=O.53 -5.0
0.5
0.3 -6.0
0.2 -6.2
0.15
0.1 -7.0
0.1 0.2 0.3 0.5 0.7 1 2 3 5 7 10 20 30 50 70 100
FIgure 6-3. Example of LIfe Test Data on IC
6.4.2 Accelerated LIfe Test

Modern applications require an extremely low failure rate for semiconductors. To guarantee such strict
quality requirements, Fujitsu uses an accelerated life test. There is no fixed acceleration rate for
semiconductors but, since semiconductor failure is usually caused by physical and chemical changes in
materials, an acceleration rate can be calculated from the Arrhenius equation below for the progress
speed of phYSical and chemical phenomena (assuming the R is proportional to the degradation speed):
R = A exp(-EalkT)
where:
R: Reaction rate
A: Proportionality constant
Ea: Activation energy
k: Boltzmann constant
T: Absolute temperature
The proportionality constant A corresponds to the component reliability. The activation energy, Ea,
depends on the component's materials and their combination, but it ranges from 0.3 to 1.35 eV for
semiconductors. This equation does not fit the data perfectly because it asllumes that the failure rate is
affected only by temperature when, in fact, there are many contributing factors. However, the equation
does give a good rough fit. Using the equation on data from the accelerated life test, engineers can
estimate and guarantee the field failure rate with reasonable accuracy.
The calculation method for the field1failure rate is given below for Fujitsu semiconductor products.
Although this method is not generally accepted yet, it has been found to be useful.
(1) Calculate the junction temperature (Tj(op)) for actual use from the temperature rise (Tj) and
the ambient temperature (Ta) under an average load (do not use the worst~ase 10ad),Tj(op) =
ATj + Ta.
(2) Calculate the junction temperature (Tjt) for a life test. For a high-temperature storage test, Tjt
equals Ta (the storage temperature). For a continuous operation test, the temperature rise
1-106
CMOS Channelless Gate Arrays Quality and Reliabifity
under load plus the ambient temperature (25°C except for high-temperature operation) for an
operating temperature, Tjt = ~Tj + Ta.
(3) Calculate the acceleration rate (ex) from the difference of Tj(op) and Tjt using Figure 6-4.
Acceleration
Rate
10,000
8.000
6.000
4.000
2,000
,
I\..
"
\ Ea_O.7aV
1,000 \.
800
800
400
200
~
'" Ea-O.5eV
,
~t'. Ea. 0.35.;;- \
100
, ,
80
60
40
20
..."1
~"'"
,,~ ~\:
"-
, III
10
~ ~~
,,-
~
8 .'- '-
"' ~'" ~ i'\,,~ ~

~,
1.B
250 200 175 150
2.0 2.2
,
2.4
"
120 100
2.62.8
80
I
60 50 40 T(OC)
Junction rs",*ature at testing
,
3.0 3.2 3.4

Slanted lines show junction 18rJ1)91'ature at operation
Reciprocal of absolute Junction tell1)9l'ature lIT) (10-3t<)
Figure 6-4. Acceleration Rate VS. Junction Temperature
(4) If planning reliability testing or calculating reliability in the field from data obtained in steps (1)
to (3), determine the coefficient yfor the 60% confidence level in Table 6-2 from the number of
defective units allowed or from the total number of failures found in the test.
Reliability = aff.r x y x 109 [FIT]
where:
N: Number of samples
T: Total test time (hrs)
n: Number of failed samples in test
1-107
Quality and Reliability CMOS Channel/es Gate AtTars
Table 6-2. DetermInatIon of CoeffIcIent

Confidence level
No. of failures
60% 90%
0 (0.92) (2.30)
1 2.02 3.89
2 1.55 2.66
3 1.39 2.23
4 1.31 2.00
5 1.26 1.85
6 1.22 1.76
7 1.20 1.68
8 1.18 1.62
9 i.16_ _1.58
10 1.15 1.54
The above equation applies only when ntN is equal to or less than 10% for the total test time, T. If ntN
exceeds 10 percent, use the following method of calculation: divide the total test duration time, T, into
subsactions, l\ti (i = 1,2, ... , m), so that for each l\ti the failure rate, (ni+l - ni)/(N - nil (where ni is the
cumulative number of failed samples for l\d), does not exceed 10 percent. Calculate (N - nil l\\i for each
time section l\ti. Calculate the summation l:(N - nil l\ti for all the time sections In T. The summation
E(N - nil l\ti must then be substituted for NT in the above equation.
6.4.3 Failure and Causes

Circuit format differences, package types, and operating environments can change the mechanisms of IC
failures, so it is difficult to foresee which factor will be the most important in a failure mechanism. Figure
6-5 shows specific electrical failures for ICs, their most common causes, and general corrective actions.
Causes of IC failures are largely the same as for planar transistor failures, but the following problems are
more common or specific to ICs:
(a) Surface degradation
(b) Flaws in an evaporated or sputtered metal film
(c) Contact failures due to an increased number of wire bondings per package
(d) Package failures due to an increased number of external leads
Table 6-3 lists failures with their most common causes, and Table 6-4 shows the relationship between
operating environments and failure causes. Test items can be listed only if the failure cause can be
pinpointed by the test.
1-108
Poor WI;~ bonding Bonding process
EvaporatiollIsputtering
Misaligned bonding proi::ess
Incomplete metallization Designllayoul
Oxide filmproWss
Figure 6-5. DlgltallC Failures and Corrective Actions
1-109
Quality and Reliability CMOS Channel/es Gale Arravs
Table 6-3. Process Defects Analysis
Defect Defect mechanism Frequency Source

Area
Factory
Process Manuf. Operator User
Design Control Tech. Skill Application
Junction Junction failure due to current crowding High • •
(Internal) Metal migration Low • • • •
Junction
(Surface)
Oxide film imperlection (Pinhole. crack. void. etc.) Medium • •
Impurity contamination High • • •
Metal peeling Medium • • •
Mask misalignment Medium •
Inter-
Incomplete metallization Medium • • •
connection Improper metallization Medium
Metal over-stress High •
Aluminum corrosion Medium • • •
Wire
Aluminum migration
Bonding peel
Medium
High
•
•
·•
Purple plague Medium • • •
Wire over-stress High • •
Particlelwire short Low •
Leakage Medium • •
Package Die bond failure Low • • •
Lead breakage Medium • •
OIhers Package corrosion Medium • • • •
Chip crack Medium • • •
Seal contamination Low • •
1-110
CMOS Channelless Gate Arrays Quality and Reliability
Table 6-4. Relationship between Failure causes and Analytical Test Methods
Test
Bato-
T""-- Vbratlon. ITIIIIric Sal
_ure
Acc:eI.,atlon ~h~lc:a .requency
Solder- 81ure Thormal Constanl variable Load Molature armoo- Yll><arlon Vbratlon
Failure Cause ablHIy Cycling shock .arlgue reduced f81lItance pher8 .arlgue noise
(2C03_2) (1010.2) (1011.2) (2001.2) (2002.2) (2007.1) (2004.2) (1001) (1004.2) (1008.2) (2005_1) (2006.1)
Bond integrity
(Chip or wire) • • • • • • •
Cracked chip • • • •
Internal
structural defect
Contamination-/
contact-induced
• ·
short • • • • • •
Wire or chip
breakage • • • •
Glass crack • • • • • •
Lead fatigue •
contamination of
junction (Surface) • • • •
Thermal fatigue •
Seal integrity •
Seal contamination • • • •
Leakage • • • • • •
Package/material
integrity • • • • • •
6.5 Reliability Testing

Reliability testing includes three types of tests-iot tests, periodic tests, and "occasional" tests. This
section explains the details of each test in turn.
6.5.1 Lot Tests

There are two types of lot tests, Group A and Group B. Group A and Group B tests are performed on
items that are tested regularly, usually every week. Table 6-5 lists the specific lot tests.
Details of individual tests vary with the product under test, but all samples are selected at random from
every weekly lot. Tests are not performed in any particular order unless specified, but are performed for
each device type.
Note that the high-temperature storage and continuous-operation tests for Group B usually take 500
hours, although they may take only 168 hours in special cases. Good samples are returned to their lots
after non-destructive testing. No-good samples and samples that have undergone destructive testing are
destroyed.
6.5.2 Periodic Tests

Particulars of the periodic tests are also listed in Table 6-5. There are two types of periodic tests: Group C
tests and Group D tests. Group C tests are performed on items that are tested regularly, usually every 13
weeks. Group D tests include special reliability tests and very long life tests. The Group D tests are
usually done once every 26 weeks.
1-111
Quality alld Reliability CMOS Channelles Gate AITaYs
Details of individual tests vary with the product under test, but all samples are selected at random. Tests
are not performed in any particular order unless specified, but are performed for each device type. Note
that the high-temperature storage and continuous-operation tests for Group C take 1000 hours and those
for Group D take 3000 hours.
Table 6-5. Sampling Plan for Reliability Testing
Group Subgroup
Device classification Device group 1 I Device group 2
Test Items Sampling plan
A1 Extemaillisual inspection 100% test of sampled devices (All sampled devices)
A
A2 Function test LTPD 5% Ac=O
A3 Electrical Static characteristics LTPD 5% Ac=O
Characteristics DynamiclSwitching
A4
characteristics LTPD 5% Ac=O
Sample Acceptance Sample Acceptance
size number size number
B1 Physical dimensions 9 1 6 1
Resistance to solvant
+temp-cycling 9 18 9 18
B2 Environmental
tests Thermal shock test 9 18 9 18
Mechanical
B3 9 1 9 1
environmental test
B4-1 Solderability (230°C, 5s)' 9 1 3 1
B4-11 Solderability (260°C, 5s)' 9 1 3 1
B5 Lead integrity' 9 1 3 1
Pressure-temperature-humidity
storaae2 9 1" 3 1"
B
B6 Pressure-temperature-humidity 17 17
bias!! 9 3
B7 High-temperature storage 14 l' 7 l'

B8 Continuous operation 24 l' 11 l'
B9 High-humidity storage
24 l' 11 l'
8S'C 85%RH2
C1
High-temperature
storage 14 15 7 15
C2
C Endurance Continuous operation 24 15 11 15
test High-humidity storage
C3 24 15 11 15
8S'C 85%RH2
D1 High-temperature
storage6 14 - 7 -
D
D2 Continuous operation 24 - 11 -
High-humidity storage
D3
8S'C 85% RH2.6
24 - 11 -
Test cycle: Group A and B for every weekly lot, Group C every 13 weeks, Group D every 26 weeks
Notes
'Electrical reject devices can be used in this test.
2These tests are performed on resin-sealed devices.
3This test takes 96 hours.
<These tests normally take 500 hours. But if no defects are found in the first 168 hours, the /ot can be passed
and the test may be terminated.
5These tests take 1000 hours.
·These tests take 3000 hours.
7This test takes 48 hours.
sThese tests take 100 cycles.
1-112
6.5.3 Occasional Tests

Occasional tests are performed on products whenever necessary. The tests are similar to periodic tests,
but their details are specified by the QC/Reliability Engineering Division according to the purpose of the
test.
6.6 Test Methods and Criteria

The reliability of Fujitsu ICs is assured by severe environmental and endurance testing. Test methods are
usually based on Japan Industrial Standards (JIS), the standards of the Electronic Industrial Association
of Japan (EIAJ), and MIL standards.
Reliability tests are performed for two reasons. Firstly, they check or guarantee the reliability of a type or a
lot according to specified standards. Secondly, they are used to determine the failure rate or mode. The
most appropriate test method is chosen for each test, and test results are processed in the most suitable
manner. Fujitsu usually performs the tests listed in Tables 6-6, 6-7, and 6-8.
Table 6-6. Example of Reliability Testing

Test Items Mll-6TD-a83 Condition
Resistance to soldering heat
Temperature cvdina
Thermal shock
-
1010C
1011 A
260°C, lOs
-SSoC (30 min.l to IS00C (30 min.l. 100 cvcles
OOC (5 min.) to 100°C (S min.), 100 cycles
III
Vibration, variable-frequency 2007 A 20 to 2,OOOHz, 20G
Mechanical shock 20028 ~ ,SOOG, O.Sms
Constant acceleration 2001 E 30,OOOG, 1 min, V, only
Fine leak' 1014A, Using compressed helium 99.S psig, 4 hrs.
Gross leak' 1014C Using fluorocarbon 7S psig, 1 hr., 12SoC
- 230°C, Ss
Solderability
2003 260°C, Ss
Lead fatigue 2004 82 0.2Skgf, 90°, twice
PTHSlPTH82 - 121°C, 2 aim
High-temperature storage 1008C 150°C, 1,000 hrs.
Continuous operation l00SA to D 12SoC, 1,000 hrs.
High-humidity storage> - 8SoC,8S%RH, 1,000 hrs.
Notes: 1 Applies to hermetic packages.

2 Applies to plastic packages.
Table 6-7. Example of Electrical Testing

Circuit classillcation Characteristics Bipolar MOS
Gates DC VOH, VOL, IIH' ilL, Icc (lEE) VOH, VoL, I'H, I,L, 100 (I.ub)
AC Function Function
Flip-flops DC VOH, VOL, I'H, I,L, IOH' Icc (IEEl VOH, VOL, I'H, I,L, 100 (I.ub)
Shift registers DC VOH, VOL, I'H, ilL, IOH, Icc (lEE) VOH. VOL, IIH, I,L, 100 (I.ub)
Memories DC VOH, VOL, IIH, I,L, ICC (lEE) VOH, VOL, I'H, ilL, (IOH),(loL)
AC Function IDO (I.ub) Function
Random-logic devices DC VOH, VOL, I'H, I,L, Icc (lEE) VOH, VOL, I'H, I,L, (IOH),(loLl
AC Function 100 (I sub) Function
Analog devices DC VIQ, 110, I,. VOM, VOH,VOL, -
AC A K." N.
1-113
QuaRty and Reliabl7ity CMOS Channa/fes Gate Arrays
Table 6-8. Example of Electrical Criteria

Umll value (In muiliplea of Ihe abaolule value)
Parameler
Upper Lower
VOH - LxO.9
VOL Ux 1.1 -
Ux2
IH (No leak: Ux
1.1)
-
U x2
IL (Leak: U x2 -
IoH Ux2
1cc(IEE) (Leak: U x2 -
Icc (Isus)
..
"11" and "L" sland for the upper and /ower RmitS
1-114
CMOS Channel/ess Gate Arrays Application Note
Chapter 7 - Application Notes

Developing Test Patterns That Work with the Physical Tester
Selecting the Best Package for Your ASIC Design
III
1-115
Application Note CMOS Channe//ess Gate AtTars
1-116
March 1990
Edition 1.1
cP
APPLICATION NOTE
FUJITSU
Developing Test Patterns

That Work with the Physical Tester
by J. Scott Runner
Fujitsu Microelectronics, Inc.
Copyright© 1990 by FUjitsu Microelectronics, Inc.

Imroductlon
This application note briefly describes the process of developing test patterns for the simulation and test of
Fujitsu CMOS ASIC designs. This information supplements testing information found in the Design Manual for
the appropriate Fujitsu CMOS ASIC technology.
Tests to be Created
Fujitsu supports the following five types of test
a. DC test
b. Dynamic function test
c. High impedance test (Z-function test)
d. Delay test (AC test)
e. Scan test (optional for certain Fujitsu technologies)
The DC test measures DC characteristics such as Ions. VO", Ill, and ILL while the function test screens for
manufacturing faults (metal and transistor faults, principally). The Z-function test augments the DC test and is
required for circuits in which one or more enable signals from a 3-state buffer can be generated by logic deeper than
one gate of complexity within the ASIC device. The delay test may be used to verify critical timing paths that are
necessary for proper system operation.
Scan test methods are used to simplify the [process of testing for manufacturing defects traditionally uncovered by
the function test. Automatic test generation is supported in conjunction with scan testing in the UHB/CGI0 and
AU/CG21 technologies as an option.
1-117
Application Notes CMOS Channel/ess Gate Arrays
Overview of Test Vector Creation

For each set pf test patterns defined as a test block, the customer must specify input states and output
states (in either vector or wave format), and the timing of inputs and outputs (with bidirectionals being
considered both an input and an output). Many designers rely on one of the Fujitsu-supported CAE work-
stations when generating test vectors, easing the burden of test pattern development. In these cases, the
customer creates input stimuli for the workstation simulator, which then generates a print-on-change file
containing the resulting output response and the associated input stimulus previously defined by the de-
signer. The print-on-change file is converted by Fujitsu's workstation software into FTDL (Fujitsu Test De-
scription Language), which is the accepted test pattern description format regardless of the method by
which patterns are created.
Developing the Tester Timing Information

Whether or not the patterns are generated on the CAE workstation, it is necessary for the customer to gen-
erate in the FTDL file a Common Block file, containing administrative information and the test type, and a
Test Block file, containing the timing information for all chip inputs and outputs by group (discussed fur-
ther in the Design Manual). The definition of this overall timing is critical to the success of the test pro-
gram itself. For example, input timing defines when input signals will transition, while output timing de-
fines when outputs will be compared with their expected values or measured at a transition point.
The designer is responsible for specifying the following timing parameters for the Test Block, depend-
ing on the specific type of test:
a. Test cycle
b. Grouping of inputs and, if necessary, outputs and bidirectionals
c. Delay-to-transition (DT) time for each input group of non-return to zero (NRZ) signals
d. Propagation time (Ip) and pulsewidth (Wp) times for the positive-going pulse (PP) and nega-
tive-going pulse (NP) for each input group of return to zero (RTZ) signals
e.* Delay-to-strobe time (STB) point for each output group
f.* DT and STB times for bidirectionals
g.** T time in the SPATH statement for AC tests
*Specified in DC, function, and Z-function tests

••Applicable only to AC tests.
This timing is established for the entire test block and is invariant until another test block is invoked.
Therefore, test pattern timing is periodic, that is, a group of inputs may only transition at the time speci-
fied in the Test Block, which is relative to the beginning of the test cycle. This delay to transition time for
inputs is programmed for each input group with the t" parameter in the FTDL INTIM or BUSTIM state-
ment.
Similarly, common output groups are strobed, or sampled, periodically at a time determined by ,the test
cycle and the delay-ta-strobe time specified in the OUTTIM or BUSTIM statement, or the Tp parameter in
the FTDL SPATH statement in the case of an AC test.
Determining Input and Output Timing Parameters

During the function test, outputs should stabilize before being strobed. Therefore, the minimum permissi-
ble test cycle programmed by the TIMING statement in the Test Block should be set with consideration of
the maximum propagation delay from any input to any output, and the respective DT and STB times for
those groups should be set far enough apart in time to assure that the outputs are stable under maximum
1-118
CMOS Channe//ess Gate Arrays Application Notes
conditions. Similarly, if the output is strobed before the transition, it must be stable under minimum delay
conditions.
Test patterns are reqUired to be invariant over minimum and maximum delay conditions. This is verified
in simulation by scaling the typical delays by multipliers representing process, temperature, and power
supply variations. Similarly, the strobed or expected output states must be identical under typical, maxi-
mum, and minimum conditions. If a propagation delay from input to output is greater than the test cycle
defined, output states may not fulfiIl this requirement (see Figure 1). Furthermore, designers should be
careful that glitches or short pulses do not occur anywhere within this minimum/maximum window (see
Figure 2).
FAILED
,, ,,
FAILED LUCKY
,, ,,
IN 1 , ,
OUT 1 (MIN) []]
OUT 1 (TYP) []]
OUT 1 (MAX)
(]]: : []]
I : : I I
STROBE ,, ,,
STROBE VALUE ..
,,, ,,,
11' • •
Test Cycle
TooShortG)
Successful Test Cycle Length ~
X - State When Strobed; X - 0 or 1 as indicated.

The minImax variation results in inconsistent values being strobed Hthe test cycle is too short (1) or the strobe is
poorly located. Successful test programs therefore require the determination of a reasonable test cycle length. (2)
Figure 1. Determining a Successful Test Cycle Length
MIN
CASE OUT 1
STROBE I I
STROBE VAL [Q] IJgJ]
TYP
CASE OUT 1 I I
STROBE
STROBE VAL [Q] I!£[I
MAX ,
CASE OUT 1 I L
STROBE
[Q]
,,
STROBE VAL It&n
Dangerous Cycle Length Preferred Strobe Range
Preferred Cycle Length
X - State when Strobed - X - 0 or 1 as indicated.
The output contains a pulse that goes undetected at minimum, typical or maximum simulations. However, since
any pulse or glitch appearing over the range of minimum to maximum may be strobed by the tester, or appear in
the end system, all pulses of this kind must be considered when placing the strobe and determining cycle length.
Figure 2. Determining Preferred Cycle Length
1-119
Generating Functional Input Stimulus Given Test Pattern Timing

One issue that must be considered when detennining test pattern timing is the relationship between input
signals, such as clock/data pairs, which must satisfy set-up and hold times. Other considerations guiding
the timing definition are dependent on the particular circuit being tested, and on restrictions imposed by
the tester. These restrictions are published in the Summary of Test Data Restriction section of Fujitsu's De-
sign Manuals.
Tester Skew and Its Compensation of Test Timing

The designer must pay particular attention to the issue of tester skew when determining input and output
timing for Test Blocks; otherwise, the timing will not correctly represent the behavior of the device under
test. Tester skew, Specified for each technology in the Summary of Test Data Restrictions, is a result of the
variation in the time at which a given signal generator triggers a transition or a comparator measures an
output state. Several timings are affected by this skew.
Input·to-Input Skew
For the purpose of estimating the skew between two signal generators, (one driving data and the other
driving its clock, for example), the driver skew, linearity of clocks, clock-to-clock skew, and jitter are col-
lectively called driver accuracy, denoted tnSKEW.
In the case of data/clock pairs, the clocked data may fail either a set-up or hold time, depending on the
direction of the skew. Therefore, when determining DT and tp for data/clock pairs, the designer should
adjust times to satisfy the following relationships (see Figure 3):
Set-up Time Criteria for Testing: (tp(CLOCK) - DT(DATA» >= ts(MIN) + 2 * tosKEW
Hold Tune Criteria for Testing: (DT(DATA) - tp(CLOCK» >= IH(MIN) + 2 * tVSKEW
Where ts(MIN) and IH(MIN) are the worst case set-up and hold times, respectively, sensitized from the
internal circuit to the inputs, toSKEW is not directly specified in the Summary of Test Data Restriction;
however, TACC, the overall system timing accuracy, is specified and can be substituted for toSKEW (see Sec-
tion 7.2).
Expected Actual
'l( '/
TLD
D Q
DATA
DT
:~---------- ..:,---------;
IOSKEW
D
~xpectw:
I
Actual
CK
'*I
•
Ip
ClK ClK
CK r-------------------------~I
'.
I
--: i-- Is
Figure 3. Input·to-Input Skew
1-120
CMOS Channel/ess Gate Arrays Application Notes
Input-to-Output Skew
In addition to the skew incurred by the signal driver, skew is also introduced by the output comparator of
the tester. This skew is dependent on the linearity of the strobe, pin-to-pin skew, skew between dual com-
parators, and the driver-to-comparator timing error. All factors are considered in the overall system tim-
ing accuracy, tACC, which in tum affects output timing as shown in Figure 4.
Ipo (MIN) or Ipo (MAX)
IN -G>---II LOGIC I-I------i~---- OUT
DT (Exoectedl ,
IN
•
:..:~;::;~======::;:;---::-:-::_
\Po ",
--, ~ - _, Actual Output
Possible
IOSKEW
_='r--'7"'II!!..'- _- - - Expected Output
............. -
OUT Actual Strobe
STB
• ' " .. ' Possible
•• , , ,
---
__ - Expected Strobe
ID
IACC = IOSKEW + ICSKEW
Driver Plus Com aralor Skew

Figure 4. Input-to-Output Skew
Skew Effect on Input/Output Pairs - Minimum Delay Case

The STB (or T parameter in the SPATH statement) should expect an output transition at a time relative to
the stimulated input transition dictated by
(STB - DT) >=jpDlMIN) - tACC
where STB is the strobe point of the output under consideration, DT is the DT time of the stimulating in-
put of interest, and tpD(M1N) is the minimum propagation delay from this input to the strobed (or meas-
ured) output. In the case of the AC test, the quantity (STB - DT) should be replaced by the minimum T
parameter in the SPATH statement. Note that if the path delay spans a test cycle boundary, STB should be
set to STB plus the test cycle period.
Skew Effect on Input/Output Pairs - Maximum Delay Case

The complementary case occurs for maximum delay measurements, as described by
(STB - DT) <= tpdlMAX) + tACC
Note that these gUidelines regarding the specification of test data timing as affected by tester skew apply
to DC and Z-function tests as well. In these cases, the same rules apply as for the function test.
Again, for the specific values of tACC, and tvSKEW, please refer to the Summary of Test Data Restrictions in
the Fujitsu Design Manual for the appropriate technology. A designer interested in a methodical approach
to the generation and verification of a good set of test vectors must consider the tester hardware on which
it is running. Fujitsu has simplified designer responsibility by providing this information as part of the
Test Block Information.
However, a lack of implementation and careful analysis of the timing characteristics of the circuit may re-
sult in a poor or unfeasible test, resulting in schedule delays or reduced device yield. Therefore, plan a test
approach early, design for testability, and consider the effect and operation of the physical tester.
1-121
1-122
March 1990
Edition 1.1
cO
APPLICATION NOTE
FUJITSU
Selecting the Best Package

for Your ASIC Design
by J. Scott Runner
1.0 Introduction
Copyright© 1990 by Fujitsu Microelectronics, Inc.
III
The widely varying degrees of complexity (gate count) of Fujitsu's CMOS and BiCMOS devices and the flexibility of
their I/O configurations combine to produce devices that take advantage of the broad selection of packages available
from Fujitsu. However, the requirements for package selection go far beyond pin count as the sole determinant of the
best package. Selection issues include surface mount versus through-hole, plastic versus ceramic, and exotic versus
conventional packaging. In fact, Fujitsu offers over 100 packages and 1000 package-die combinations from which to
choose. Compounding the selection problem is the effect of increasingly faster outputs coupled with higher drive and
wider bus structure, resulting in greater numbers of simultaneously switching outputs (and thereby greater amounts of
noise).
The result is that designers are finding ASIC packaging implementation to be an increasingly complex task. This
application note provides information about ASIC packaging that is meant to simplify the designer's task. It provides
designers with a review of the various Fujitsu packages and their electrical, ithermal, and mechanical characteristics, as
well as some problem-solving strategies for their use. Sections 2.0 and 3.0 address system requirements and package
availability; Sections 4.0 and 5.0 discuss noise and thermal issues.
1-123
Application Notes CMOS Channelless Gate AITBYs
2.0 How System Requirements Affect Package Choice

Section 2.0 presents considerations involved in the selection of packages from a system designer's per-
spective. Table 1 lists issues a designer must consider when determining the optimal packaging for an
ASIC design.
Table 1. Considerations for Package Selection
Manufacturing and Cost Speed Requirements

Board Integration Package and Interconnect Delays
Double-sided Component Mounting The Effect of Package on Noise
Number of Packages Thermal Considerations
Package Outline Area
Power Densny Limnations
Produclblllty Quality
Board Layout Package Quality and Reliabilny
Package Construction Number of Devices
Packaging Complexity Noise
Manufacturing Flow Thermal Considerations
2.1 Manufacturing and Cost

The manufacturing-related factors discussed below, although not directly related to the design of the de-
vice or the number of power and ground pins it requires, are nonetheless important in the choice of an
ASIC package.
2.1.1 Board Area

One of the most important issues is the board area consumed by a circuit. Some of the factors affecting
overall board density are:
Integration (gates per square inch of board)
Double-sided mounting capability (integration)
Number of packages
Package outline area
Additional board space required (for spacing, resistors, capacitors, probe areas, etc.)
Power density area (discussed in Section 5.0)
The critical issue in board area reduction, however, is overall integration. For example, surface mount de-
vices (SMDs) can be densely mounted on both sides of the board, making them ideal f.or systems demand-
ing high package integration. But a large design integrated into a few very large Sea-of-Gates arrays, even
if packaged in large, through-hole packages, may wen consume less board space than the same design
using surface mount plastic }-leaded chip carriers (PLCCs). The PLCC version would require more space
because the PLCCs, al though small in outline, cannot house as large a die and therefore require the design
to be partitioned into a greater number of devices.
Figure 1 illustrates the board area taken up by the outline of each kind of package Fujitsu offers, excluding
any area around the package necessary for spacing, decoupling capacitors, series damping resistors, or
solder pads.
1-124
100
50 Mil Pin Grid Array (PGA) I _____________ _
100 Mil Pin Grid Array (PGA) I _____________ _
Flat Pack Type (FPT) I _____________ _
Leadless Chip carriefJ~~~t ________ _
50milLCC
50
20 mil FPT --- _ - -100 mil PGA
--- 50 mil PGA
_-==============- Bonding
4 mil Tape(TAB)
Automated
Package
Outline (mm) Pin Count
Figure 1. Package Size versus Pin Count
2.1.2 Board Layout

Restrictions in board layout or construction must be identified and resolved early in the design process.
For example, a design containing large buses (16 bits or 32 bits or more) must be split up to avoid too high
a concentration of simultaneously switching outputs per ground pin. Splitting up the buses, however,
may result in variations in signal trace length and require extra care in routing. Similarly, flatpacks, a form
of SMDs, are a convenient way to support high pin counts in relatively inexpensive plastic packages.
However, with pin pitches as narrow as 15 mils, they demand extremely accurate positioning of solder
pads. Dense PGAs, on the other hand, provide a spacious lOO-mii pin separation, but because of the num-
ber of rows of pins, normally require a large number of board layers.
2.2 Producibillty
Though some unusual packages may appear to promise ultra-high speed or dense integration or mini-
mized component/board cost, the designer must always keep manufacturability in mind. The cost of a
system is only partially dependent on materials and labor costs per unit; it is also highly dependent on the
manufactUring yield of the end product. Therefore, design and production engineers must jointly consider
the choice of package in order to guarantee that the chosen package conforms to existing (or purchasable)
manufacturing equipment and that the manufacturing process can meet yield goals.
2.3 Speed Requirements

The speed requirements of a system strongly affect package choice. If the interconnect lengths in the sys-
tem (both inter- and intra-board) can be reduced, system speed may be increased. Reducing interconnect
lengths may involve reducing the required number of packages, choosing packages with smaller outlines,
changing to double-sided, modular, or piggy-backed mounting, using small form factors, reorganizing
boards, and even changing the number of metal routing layers of the board. See Figure 2.
1-125
Board interconnect at midpoints

may reduce interconnect length,
but may increase noise. Splitting boards on oppos~e
sides of the mother board can
reduce by haH the length
of the board.
Devices mounted
double-sided on
mother board, which
contains the backplane.
Coax or ribbon connectors between boards
w~h mother board connections at oppos~e
ends reduces board interconnection length
Perpendicular organization of boards to a mother board compared to conventional organization helps to reduce
trace length, on the average, by a factor of 2. Interconnection directly between boards avoids delays down the
length of the board and across the backplane.
Figure 2. Minimizing Interconnect Length
2.3.1 The Effect of Noise on Speed

There are various sources of noise that can affect an integrated circuit (lC), each with its own effect; all
forms of noise influence signal speed, quality, and consequently, system reliability. Certain types of noise
arise between a chip I/O and ground or power, while other forms of noise are coupled to the power rails
and influence system power and ground lines, propagating noise throughout the entire system. Noise ap-
pears to an input buffer (receiver) relative to the receiver's ground. Any noise on this referenced signal is
superimposed onto the incoming signal itself, as shown in Figure 3. The VIH or input threshold level of
the receiver indicates when the input will switch, if the signal is stable at that level. Therefore, although
the input voltage ordinarily would switch 4 ns after the driver switches, when the signal first crosses the
threshold, the designer must assume it will not switch until it is stable; in this case at 8 ns, producing a
loss of 4 ns due to noise.
~
IH ••••• • ••••••••••••••••••••• : •••• :• • • • • • • • • •
..
I
, 6t
-, ,
'
Smooth trans~ion Signal must settle before ~
can be considered to sw~ch
.s:s~e.m.g~o~:d•• •~ • • • • • • ' .... ~ .....}

IR drop and
ground bounce
(relative to Chip ground

/ _--...,~l :
Setting time to'
will dynamically
change V1H and V1L
systelll1 ground)
:~41----'s;;.;t;;;ab;;;l;;;e...gc.;ro:;.:u;;.n;;;d.;.:
Setting time
including ground rise
Figure 3. Impact of Noise on Speed
1-126
2.3.2 Controlling Noise through Package Selection

Each fonn of noise is dependent not only on current or its first derivative with respect to time, but also on
the real and imaginary components of impedance: resistance (R), inductance (L), and capacitance (C). One
solution to noise can be to minimize the package Land R and to locate high drive pins where they will
minimize Land R.
2.3.3 The Effect of Thermal Characteristics on Speed

The speed perfonnance of a CMOS or BiCMOS circuit degrades with temperature rise. Therefore, in very
high speed systems, it is sometimes necessary to reduce the junction temperature (Til or die temperature
as a way to improve speed. Certain packages offer better cooling properties than others, making them
more suitable for high speed systems. Thennal issues are discussed in Section 5.0.
2.4 Quality
Reliability refers to the defects or failures that appear during the lifetime of a device. Quality, on the other
hand, refers to the frequency of occurrence of defects or faults in a device as a result of the manufacturing
process. Quality defects are revealed by testing immediately after manufacturing, while reliability defects
are revealed by speciallong-tenn or intensive test sequences or by time.
2.4.1 How Package Type Affects Quality Testing

Conventional (through-hole) packages lend themselves to simplified testing because it is easy to access the
leads in order to force a state (1 or 0) at a node and/ or to observe the state of the node. These tests are per-
fonned with board-level in-circuit or functional testers. Such tests facilitate the manufacture of high-qual-
ity systems by ensuring proper connectivity and function.
Surface mount devices, however, generally provide poor probe access, and are known to occasionally pos-
sess faulty joints that make temporary connections during probe. Through-hole packages also have occa-
sional bad solder joints, although their node access is fairly good.
2.4.2 How Device Integration Affects Reliability

Total system reliability is related to the reliability of the individual devices and to their configurations.
Systems may be configured as a series in which all devices are interdependent, in which case anyone fail-
ure will cause overall system failure, or they may be configured in parallel, in which case all devices must
fail for the system to fail. Parallel configuration is used in redundant or fault-tolerant systems.
The reliability of a system also depends on the reliability of the devices that comprise the system. The
long-tenn reliability of a single device is defined as an inverse natural log function in a variable lambda,
which is the failure rate of the device in the region of lifetime operation characterized by a constant failure
rate. In the first hours of a device's life (the infant mortality period), the failure rate declines. The majority
of a device's life is characterized by random failures (expressed as lambda), and the end of a device's life
exhibits an increasing failure rate. Today's ICs, however, are designed so that wearout does not even begin
to occur for at least several hundred years, and can be considered never to occur.
To understand how the partitioning of a system into circuits can affect the reliability of a system, consider
a system in which N components are configured in series. Although the density of ASIC devices has in-
creased by two orders of magnitude in the last decade, the reliability of the devices has remained roughly
constant. Therefore, it can be assumed that the failure rate of each of the components is constant. The reli-
ability of systems and subsystems in which components are series-dependent is the product of the indi-
vidual reliability tenns for each component. The reliability function of the system just described is there-
fore:
R(t)sys = R(t)l * R(t)2 * ...R(t)N
1-127
Application Notes CMOS Channelless Gate Arrays
where
R(t)N = e - NAt, t is the independent variable time, and A. is lambda, the failure rate.
Since all components have the same failure rate, the reliability function of the system is:
R(t)sys =e - NAt
Because the number of packages affects the reliability more than the integration factor does, a designer's
goal in constructing a reliable system should be to maximize integration and thereby reduce part count.
The disadvantage is that increased integration may in tum increase the package pin count, requiring a
more complex package, which usually costs more than a simpler, smaller package. Additionally, the larger
die sizes cost slightly more per gate than the smaller ones, although the total non-recurring engineering
charges (NRE) would typically be lower.
2.4.3 How Noise Affects Reliability

Even when Schmitt trigger input buffers are used to receive clock signals, noise may go beyond the hys-
teresis value of the input buffer and cause a counter to be incorrectly clocked or other circuit malfunction.
Noise is in this sense a threat to reliability as well as to speed and must be considered in the package
choice as well.
2.4.4 How Thermal Issues Affect Reliability

While the junction temperature of a device affects its speed, it also affects reliability expressed as mean
time between failures (MTBF) or the mean time a device will operate in a given environment before fail-
ure occurs. Figure 6--4 in the previous chapter, Quality and Reliablility, illustrates this concept by plotting
life test failures as a function of junction temperature. System reliability goals, then, restrict the desired
maximum junction temperature in a manner that affects the choice of package according to its thermal
characteristics, the chosen type of system thermal management (cooling), and the maximum allowable
device power dissipation.
2.4.5 How Package Material Affects Reliability

The different materials used in package construction each have distinct thermal and mechanical proper-
ties. The most common materials and their characteristics are listed in Table 2 below.
Table 2. Package Material Characteristics

Thermal Thermal Dielectric
Coefficient of Conductivity Constant
Package 1'(pe Body Material Expansion (ppm/5C) (W/m* 5C) (K)
Ceramic AI2 0 3 (Alumina) 7.0 20 10
Plastic PGAs Epoxy Fiberglass 14-18 0.16 4.5-5.0
Other plastic packages Poly imide Epoxy 15 -18 0.38 4.5-5.0

(DIP, PLCC, Flatpack)
To better understand the different characteristics of plastic and ceramic packages, it is helpful to know
something about the way they are constructed. Packages provide electrical connection from the Ie to the
system and isolate the device from destructive elements of the environment. The choice of materials and
construction of a package affect its final dimensions, thermal characteristics, and electrical characteristics,
as well as device reliability. Fujitsu carefully determines the most appropriate manufacturing methods for
a given package and then performs extensive qualification tests to determine its success.
1-128
The largest part of the package is the body; which houses the die. The die may be affixed to a lead frame,
which physically supports the die and provides the leads that electrically connect the die to the system by
means of bonding wires or tab leads. Alternatively; the die may be supported by a cavity on the body of
the package or attached to the bottom of the body by a chip carrier.
The die is attached to the surface of the lead frame or to the metallized surface of the cavity or carrier with
gold or silver paste, or eutectic. After the die is attached to the lead frame, cavity; or carrier and the bond-
ing pads are bonded to the leads, the assembly is encapsulated. In plastic packages, an epoxy resin is
molded around the assembly. In ceramic packages, a cap is sealed onto the lower part of the body or carri-
er using a frit glass or metal seal (the metal seal has a higher melting temperature than the glass). A solder
seal can be used if the cap is metal.
To ensure that the device is completely isolated from its environment, the surface of the die is then coated
with glass (Si~) and then polyimide or other coating that prevents gas and moisture from coming in con-
tact with the surface of the die. Figure 4 shows a frontal cross section of the structure of a PLCC package;
Figure 5 provides a top view.
Gold bonding wires
Carrier and arm, molded

into the body for support
Figure 4. PLCC Package Construction (Front View)
Figure 5. PLCC Lead Frame Construction (Top View)

Each of the various packaging methods has its advantages and disadvantages; for instance each body type
and each type of seal has a different maximum case temperature. While plastic packages can tolerate tem-
1-129
peratures up to 125°C and high humidity levels with outstanding reliability. ceramic packages are the
most reliable for harsh extremes of cold.
Each package type also responds differently to the thermal environment of the board to which the device
is attached. Heat can cause thermal stress on the device when different materials expand at different rates,
a particularly important factor when surface mount packages are involved.
Different packages also exhibit different electrical characteristics. As the speed and gate densities of
CMOS devices rise, the avoidance of electrical parasitics in the form of package delays and noise becomes
an increasingly important factor in choosing a package type.
Fujitsu's plastic PGA provides a good example of the tradeoffs involved in package construction. In 1986,
FUjitsu introduced the plastic version of its ceramic PGA. The plastic configuration proved to have several
advantages over the ceramic version. The body is formed from glass epoxy (VG-lO) with an aluminum
cap and an epoxy resin sealer. This combination of materials has the same rate of expansion as the PC
boards onto which it is mounted; it is also less expensive than ceramic.
Ceramic PGAs have a hermetic seal of solder between the metal lid and the cavity. but plastic PGAs are
sealed by filling the cavity with epoxy resin to form an inner seal, then placing a resin sheet over the inner
seal to form an outer seal, and then securing an aluminum cap over the outer seal. The aluminum cap pro-
vides the necessary rigidity to support the fragile glass epoxy, as well as improving the thermal conductiv-
ity of the package.
Connections from the bonding wires to the pins are provided by copper traces designed to minimize mu-
tual and self inductance. Because the plastic PGA is a large package, however, and generally houses a
large die, the thermal coefficient of expansion (TCE) difference between the die and the cavity can exert
stress on the bonding wires and the die attach. Table 3 lists the package types discussed in this section and
the materials used to construct each type.
Table 3. Fujitsu Package Types
Package lead frame! Body Seal
Type Metallization Lead/Pad Lead Finish Cap Material Material Malerlal
Plastic DIP le-NiorCu Same Solder Dipped -- Resin Resin
Alloy Lead frame
Ceramic DIP Tungsten Kovar or Fe- Au/Sn Plated Metal or Alu- Laminated Solder.
Metallization Ni minum Alumina Glass Frit
CERDIP Fe-Ni Alloy Fe-Ni Sn Plated Alumina Alumina Glass Frit
Lead frame
Plastic Fe-NiAlloy Same Sn Plated -- Resin Resin
Flatpack Lead frame
Ceramic Fe-Ni or Kovar Same Au Plated Metal or Alu- Laminated Solder or
Flatpack Lead frame minum Alumina Glass Frit
Cerpack Fe-NiAlloy Same Sn Plated and Alumina Alumina Glass Frit
Lead frame Solder Dipped
PlasticPGA Cu Conductor on Ni Plated and Aluminum Epoxy Glass Resin
Kovar
Epoxy glass Solder Dipped
Ceramic PGA Tungsten Au Plated and Metal or Laminated Glass Frit
Kovar
Metallization Solder Dipped Alumina Alumina
PlasticLCC CuAlloy
Lead frame Same Solder Plated -- Resin Resin
Ceramic LCC Tungsten Tungsten Au Plated Metal or Alu- Laminated Solder,

Metallization Metal Pad mina Alumina Glass Frit
..
Note: All above packages are hermetic. Alumina IS a ceramic. Solder IS PbSn. Fe-NilS ferrous (Iron) nickel. Kovar IS an alloy of
oobalt, iron, and nickel. Bonding wires are gold in the case 01 molded packages (epoxy resin PLCCs, DIPs, Flatpacks) and gold or
aluminum for the other cases. Cerpack is the ceramic flatpack equivalent of CERDIP.
1-130
CMOS Channelless Gate Arrays Application Notes
2.4.6 Package Qualification to Ensure Reliability

Fujitsu performs extensive six-month minimum qualification tests for every package-die combination.
After such qualification is performed, the package die-combination is added to a package matrix in the
Design Manual for the appropriate technology. The designer can be assured that Fujitsu has considered
the issues presented here, as well as others, when releasing an approved package-die combination.
3.0 Package Types

Very large scale integration (VLSI) ASIC devices are supported by a wide variety of packages, of both sur-
face mount and through-hole types. Through-hole devices, induding DIPs and PGAs, are a proven tech-
nology and are supported by widely available production equipment. The pins of these devices are in-
serted though holes in the PC board to form electrical contact with traces (usually copper) which are em-
bedded in the. board or applied to the surface and are routed to drilled pin holes. Solder applied by reflow
or wave technique then completes the connection.
3.1 Through-hole Packages
3.1.1 Dual In-line Packages (DIPs)

DIPs have two rows of pins spaced 300 mils to 900 mils apart, with a pin spacing of 70 to 100 mils. Since
the length of the package increases as each p<'lir of pins is added, the size of a DIP tends to be unmanage-
able over 64 pins. The lead width and length of a DIP varies widely, causing variation in the input and
output response of the device and thus, skew. Also, due to their high pin inductance, DIPs tend to be
noisy, the degree of noise being a function of the location of outputs and sensitive inputs.
The DIP is relatively simple for manufacturing to support, thanks to a large installed base of well-proven
equipment and is one of the least expensive packages available. Furthermore, DIPs, being well estab-
lished, come in many JEDEC-approved options (see JEDEC Standard 95), and are available in both ce-
ramic and plastic cases.
3.1.2 Pin Grid Arrays (PGAs)

Although PGAs are usually through-hole (Fujitsu also offers SMD versions), they differ from DIPs in that
pins are arranged in rows on all four sides. While the pin spacing is usually the same as for DIPs (70 to 100
mils), nesting the pins in rows permits a larger number of pins to be contained within a smaller area al-
lowing PGAs to support high pin counts of more than 300 pins. See Table 4 for a list of Fujitsu PGAs.
Table 4. PGAs Available from Fujitsu

Package Type Construction Number of Pins
PGA - 64C, 64P Through-hole Ceramic/Plastic 64
PGA-135C, 135P Through-hole Ceramic/Plastic 135
PGA-208C Through-hole Ceramic 208
PGA-256C Surface Ceramic 256
PGA-321C Staggered Ceramic 321
Through-hole =100 mil through-hole
Surface =50 mil surface mount PGA
Staggered =71 mil staggered PGA
1-131
Although PGAs are generally easy to support from a manufacturing standpoint, they may also raise prob-
lems. The PC board designer may find it difficult to route signals to and from the inner rows of the PGA,
sin~e it has only 100 mils spacing between pins. Additionally, the large cluster of pins confined to a small
area tends to create trace congestion and may require boards of up to six layers to be used to support the
PGAs. Manufacturing engineers find the solder joints for the pins of inner rows are difficult to inspect,
forcing them to rely on the results of "bed-of-nails" in-circuit testers, or sophisticated inspection tech-
niques such as x-ray or infrared.
Although more expensive than DIPs, PGAs have corne down in cost with the introduction of plastic PGAs
(previous PGAs were usually ceramic). These plastic PGAs are generally constructed of G-lO glass-type
epoxy with the traces routed through the epoxy the way they are routed on a typical PC board. (The elec-
trical characteristics are, of course, tightly controlled). Although the reliability of plastic PGAs was initially
in question, Fujitsu built them using special construction techniques employing metal lids and heat
spreaders to provide rigidity and heat dissipation. Their excellent reliability history up to this point seems
to indicate that plastic PGAs will continue to be popular. The widely-used epoxy thick-film substrate,
once a quality and reliability concern, has the same TCE as the most common PC boards, and reduces the
stress of expansion and contraction that is typically a concern with larger packages. (The distance of ex-
pansion per unit change in temperature increases with the size of the package.)
3.1.3 Advances In Through-hole Packaging at Fujitsu

The demand for high pin-count plastic packages cannot be satisfied by merely increasing the number of
pins a package supports. As size increases, so do the problems inherent in these lower-cost packages.
These problems include greater lead inductance and thermal expansion mismatch between die and pack-
age. Ceramic flatpacks can support more pins than plastic packages, but they require special manufactur-
ing capabilities, and are difficult to work with since they may have pin pitches down to lO mils. Surface
mount PGAs (discussed in Section 3.2) can support a large number of pins, but require difficult manufac-
turing processes.
Fujitsu's answer to these problems, for the customer who wants high levels of integration without the
need for exotic manufacturing methods, is the staggered PGA, shown in Figure 6.
[[] m J£0000000000000000000,00000000~
0000000000000000000000000,0000000000000
000000000000000000000000000000000000000000
000000 00000"
00°0000 000°000
000000 000000
000000 0000000
000000 000000
0000000 000000
000000 0000000
000000 0000000
000000 0000000
000 00000
0000000000000000000000000000000000000
ogoOOOOOOOQ~O~O~~~~QO~OQO~~POO~_
~ rp l QOOOOOOOO~O~O°<!t°<!t°O ?OO~Q.OO~ - T :0. 10
"- /
On-board decoupling capacitor pads (Capacitors
not included)
( ,'-',
0.100 0.100
:-: .....,
,
0.050
,
~,
0.070
As with all Fujitsu PGAs. corner pins have seating
rings
Figure 6. 321-Pln CeramiC Pin Grid Array

1-132
Figure 7 illustrates the footprint of the staggered PGA and the method for routing traces through the
leads. Note that the routing is oblique, with the traces offset 45 degrees compared to traditional routing.
At this angle, the lead spacing is 71 mils, providing the trace density available with standard through-hole
devices, while reducing the package outline by approximately 40 percent.
Two 32-bit buses routed through the PGA orthogonally

on two layers perm~s high interconnect density
Traces routed at
45°. Pass-through
clearance between
pins is 0.070'
...
..•...••...••...••..•.•..
·•··.•...•..
····•....•....• III
··•·•..•.•..•.•
.•...•.. . . . . . . . . .
• •
• • • ••• • • • ••••••••• • •••• O-!#'ii'!!I~&'!!=+= Traces routed at
• . . . . . . . .0.
• • • • • • • • • • • •
• 0 0 0 • • • • • 0 •
" 90°, pass-through
clearance between
pins is 0.050'
Figure 7. Staggered Pin Grid Array Routing

The lead configuration of a package affects the pin assignment of the ASIC device. For example, Figure 7
shows a situation in which a 32-bit address bus and a 32-bit data bus are routed through the device, with
one offset 90 degrees from the other. If you assign consecutive bit significance to the bus, you will notice
that the resulting pinout is quite different from an equivalent circuit packaged in a traditional orthogonal
PGA. High drive buses can still be distributed around the ground pins, but the associated pads are not
concentrated in one specific area of the die, reducing the concentration of SSOs, thereby reducing signal
noise.
3.2 Surface Mount Devices (SMDs)

The demands of military applications, space-constrained systems, and boards containing large numbers of
memory devices were initially responsible for the development of surface mount technology (SMT). How-
ever, the accelerated push for physically reduced systems, the appearance of higher pin count ASICs, and
the cost of pin grid arrays have encouraged many more designers to consider surface mount options. Eas-
ing the strain of the migration to SMT is the broader availability of pick and place, vapor phase soldering,
and other necessary SMTequipment, as well as the availability of SMDs for an increasing percentage of
devices on the boards. SMT for VLSI is gaining momentum due to the smaller board area consumption,
smaller profile, and proven reliability.
3.2.1 Flatpacks
Plastic flatpacks have been popular for years with manufacturers of peripherals in which the board area is
constrained and height is restricted. And recently, the low cost of flatpacks (in plastic) has made them an
attractive alternate to PGAs and even to DIPs in cases of higher pin count. As the following figures show,
1-133
Application Notes CMOS Channel/ess Gate AITBYs
flatpacks come in several lead type and location configurations. Figure 8a illustrates a small outline inte-
grated circuit (SOIC), with gullwing leads on two sides, Figure 8b illustrates a quad flatpack (QFPT) with
gullwing leads on four sides. Flatpacks with axial leads require special assembly, and are generally used
only for ECL circuits in which leads may have to be trimmed and formed to tune impedance.
Sa. Small Outline IC Sb. Quad Flatpack
Sc. Ceramic Leadless Chip Carrier
Figure 8. Flatpack Configurations

Because flatpacks feature pin pitches (pin spacing from center to center) down to 10 mils, they can support
high pin counts within a small board area. However, the narrow pin spacing means that accuracy in de-
vice placement, pad size and placement, and solder paste application tolerance are all more critical. PC
board designers also need to determine whether the true package dimensions are in metric or English di-
mensions, and, when converting between the systems of measure, ensure that enough precision is main-
tained so that pins on the end of large packages won't roll off due to inaccuracies in pad location.
Probing devices with fine pin pitches can be difficult because the pins do not pierce the bottom of the
board, and if probes are attached to the leads, they can easily slip off and short adjacent leads.
3.2.2 Leadless Chip Carriers (LCCs)

Ceramic leadless chip carriers (CLCCs), such as the example shown in Figure Be, have a long history in
surface mount packaging. Ceramic packages perform well in high temperature environments, explaining
their popularity in military applications. The term "chip carrier" comes from the process of mounting the
die directly to a thick-film chip carrier, which also has pads for external connection on the opposite side of
the substrate. This configuration differs from that of the PGA, in which the die is housed in the cavity of
the package, or the flatpack, in which the die is held by the lead frame and molded with the package.
CLCCs are available in pad counts ranging from 28 to 84 and beyond.
Pads, not leads, are located on the bottom of the carrier and are generally spaced at a 40-mil pitch (stan-
dard). Solder paste is applied to the pads on the board to which the device will be mounted, usually by
screen printing, and the board is then vapor phase or infrared reflow soldered. Because the pads are 10-
1-134
cated beneath the package, they are typically very difficult to probe and are subject to manufacturing de-
fects such as solder voiding (gas bubbles in solder formed during reflow).
The most challenging problem inherent to LCC devices relates to TCE mismatch between the chip carrier
and the board to which it is mounted. As the temperature of boards and packages rises, the materials ex-
pand at different rates. This difference translates to mechanical shear force at the solder joint. This force
temporarily deforms the leads of PLCCs and flatpacks, but CLCCs have no leads. Consequently, the force
is directed at the solder joint, tending to promote thermal fractures, (shown in Figure 9).
Difference in thermal coefficient of expansion results in shear force applied at the solder joint.
Thermal Fracture
..
TeE pcB • ~T
Figure 9. Defect Caused by Difference In Thermal Coefficient of Expansion
Even though CLCC SMDs cost more than equivalent plastic packages, their resistance to high tempera-
tures, availability in hermetically sealed (moisture resistant> packages, and low profile of the CLCC SMDs
make them very useful for applications in extreme environments. The TCE mismatch problem affecting
LCCs is less severe when they are mounted to ceramic hybrids or PC boards, making their disadvantages
acceptable in many circumstances.
3.2.3 Plastic J·leaded Chip Carriers (PLCCs)

If cost and TCE mismatch are a significant deterrent to the use of LCCs, leaded chip carriers may be more
attractive. Though the chip is still mounted on a carrier (see Figure 10), the electrical connections of PLCCs
are through pins that deform to absorb the TCE-induced thermal stress. Furthermore, while solvents used
in the post-soldering cleaning process may be retained beneath the low profile of the CLCC and flatpack,
the board offset of the PLCC permits it to remain free of these contaminants. In addition, the LCC in a
plastic package costs less than the equivalent CLCe.
When more pins are necessary (in the 44-, 68-, 84-pin packages necessary for ASICs), the LCC is called a
PLCe. It is also available in a ceramic body version; both are available in pin counts of 28 to 84 and be-
yond.
1-135
Figure 10. PLCC Package

This package is termed a small outline ]-lead (SOJ) when its bent leads are located on only two sides
(Figure 11). The leads are bent into the form of a J in order to permit it to be placed on top of the solder
pad.
Metallic lead frame
Figure 11. Cross-Section of a Plastic Smail-Outline J-Iead Package

On the list of drawbacks of the PLCC is its limited ability to withstand high case temperatures, and its un-
availability as a hermetic package. It is nevertheless very well suited for industrial and commercial envi-
ronments. With a 50-mil pin pitch and only slightly greater height and width, the profile of the PLCC is
nearly equivalent to the corresponding CLCC.
3.2.4 Advances In Surface Mounted Packages

While smaller process geometries themselves have few disadvantages, the associated increase in integra-
tion, speed, power, and particularly pin count place heavy burdens on packaging. The greatest challenges
CMOS faces is supporting pin counts in excess of 300 in packages with low lead inductance, capacitance,
and resistance.
To respond to these demands, Fujitsu has developed a clever solution in packaging to obtain the highest
average pin density per board area yet achieved. This is accomplished with surface mount PGAs, which
rely on narrow pin pitch (SO and even 25 mils) in a dense grid of multiple rows of pins. Since through-hole
packages cannot effectively support pin pitches narrower than 70 mils, these PGAs must be surface
mounted, though they still possess pins (see Figure 12).
1-136
Surface mount PGAs offer the greatest pin density and lowest inductance
"": "I: e': I . . .

,'''
,..,.-
I ........
e e"' , , ...
....
..
6' : ••
6 •
"_ I
,.:.....•
......
e' , , .
6,,$
Figure 12. Surface Mount PGA

The surface mount technology also permits traces to run beneath the package leads, increasing available
trace density. Figure 13 shows the solder pad design required by these high-pin-density packages.
:.. 50 MIL
,
' .. .., Mernatively.
0.6 mm
Diameter an octagonal
pad geometry
may be employed
---:- t -200-300 11m
i solder paste
- - thickness
Figure 13. Solder Pad Design for Surface Mount Pin Grid Arrays
1-137
Application Notes CMOS Channelless Gate Arrays
Table 5 provides an item-by-item comparison between PGAs, surface mount PGAs, and flatpacks of simi-
lar pin counts.
Table 5. Comparison of Critical Features
PIN DENSITY
PACKAGE TYPE PIN PITCH OUTLINE (MAX) (Pins Per Sq Inch)
FPT-160 Surface 25 mil 1.276" x 1.276" (1.63 sq In) 98

PGA-256 Through 100 mil 2" x 2" (4 sq In) 64
PGA-256 Surface 50 mil 1" x 1"(1 sq In) 256
PGA-321 Staggered 71 mil 1.72" x 1.72" (2.96 sq In) 109
PGA-401 Staggered 71 mil 1.922" x 1.922" (3.69 sq In) 109
The numerous electrical and mechanical advantages of surface-mount PGAs would seem to outweigh
their disadvantages. However, the general state of high volume manufacturing has not kept pace with the
rapid advances in semiconductor packaging. This is partly due to the requirement for state-of-the-art
manufacturing equipment, which is quite expensive, and also to the need to maintain board yields with
such complex devices. Therefore, in order to establish these packages as an attractive alternative, Fujitsu
personnel are available to assist customers in the mounting and inspecting of these highly complex pack-
ages.
3.3 A Comparison of Through-hole and Surface Mount Devices

SMDs provide improved electrical performance and reduced system size and costs. Furthermore, with
plastic flatpacks of up to 160 pins and beyond available, SMDs show promise in supporting the rapidly
advancing gate size complexities and high pin count of today's ASIC products at a substantially lower
cost than the large ceramic PGAs. However, as the manufacturing complexities that have just been re-
viewed indicate, surface mounting large ASIC devices may be difficult and risky, and the designer should
be cautious in their use.
If board space constraints are not critical, if the economic impact of scaling down the end system is not
great, if optimal electrical characteristics in packaging are not a critical concern, then through-hole packag-
ing may be the best solution. On the other hand, if speed and integration requirements dictate the use of
very dense gate arrays, PGAs or SMT PGAs provide both through-hole and surface mount alternatives.
3.3.1 Socketing Surface Mount Devices

Some benefits of SMDs are available to manufacturers employing through-hole packages through the use
of sockets for SMDs. Sockets are available for QFPTs, small outline packages (SOPs), CLCCs and PLCCs;
however, the use of QFPT and SOP sockets is normally restricted to prototyping and bum-in, while low-
cost, reliable production sockets are more commonly available for PLCCs and CLCCs. These production
sockets house the SMD (they are tightly tailored to the specific package) in one of two ways. Flatpacks and
LCCs use low / zero insertion force with a lid that closes down on the package. PLCCs use pressured sock-
et contacts that drive a pin into the underside of the socket. Socket pins are arranged like those of PGAs:
they are through-hole, they have lOO-mil spacing (generally), and they are most commonly oriented in a
grid of two rows.
One advantage of these sockets is that in applications where through-hole packaging is required and the
choice of through-hole packages is limited to PGAs, a plastic SM package plus the production socket will
cost less than the through-hole PGA. The scenario typically occurs when the reqUired number of pins is
between 40 and 84 for PLCCs and LCCs and up to 160 or more for the flatpacks.
1-138
CMOS ChannelJess Gate A"ays Application Notes
Another significant reason to socket SMDs results from the manufacturing difficulties of SMDs that were
presented earlier. ASIC devices are usually among the largest in the system, and the most vital and expen-
sive. For the purpose of field maintenance, many companies feel it is more economical and reliable not t9
risk running an ASIC device through wave or reflow solder and risking stress fractures or other damage.
Furthermore, the test probing difficulties alluded to earlier are alleviated with sockets, which usually pro-
vide easy access to the contacts. Often, once reliability of the system is proven, the boards are re-Iaid out
with surface mount devices. Therefore, simply because a manufacturing facility isn't geared up for SMT
does not mean that SMT devices cannot be used there.
3.3.2 NoIse Problems With Sockets

Sockets for SMDs are convenient for manufacturers not yet ready to go to SMT, or for initial prototyping
where the device may frequently be removed. Socketing permi ts the user to gain many of the benefits of
SMDs, such as reduced profile and support of high pin counts in plastic, while avoiding the drawbacks,
..
such as special manufacturing equipment and lead probing difficulties. Unfortunately a major electrical
advantage of SMDs, low pin inductance, is compromised when sockets are used. The primary result is
greatly increased noise, which adversely affects overall speed and signal quality. In fact, a socketed SMD
generally has a higher lead inductance than an equivalent through-hole PGA.
3.4 Summary of the Packaging Alternatives

Having reviewed the package selection alternatives presented in Section 2.0 and the various tradeoffs be-
tween the packages discussed in this section and summarized in Table 6 below, the designer can weigh the
benefits and limitations of the various packages and arrive at an optimal packaging scheme.
1-139
Application Notes CMOS Chimnelless Gate Arrays
Table 6. ASIC CMOS Package Types and their Characteristics

Thermal Relative
Package Range of Physical Electrical Characteristics Usable Cost
Type Dimensions Characteristics' rC/Watt) Gates3 (per Pin)
Ceramic/Plastic
Through- # Pins: 16t064 R: Medium eJA2: Upto
Hole Pin pnch: 100 mils L: High 17K gates 1
70 - 401
Dip Body Length: .75" to 2.3" C:Low 120- 80
Body Width: .300" to .700"
Ceramic/Plastic
Surface # Pins: 16t028 R: Medium eJA2: Upto 6500
Mount Pin Pitch: 10 mils L: Medium gates 1
110 - 801
SOIC Body Length: 50 to 70 mils C:Low 130 - 105
Body Width: .300" to .400"
Plastic
Surface # Pins: 48 to 260 R: Medium eJA2: 95 - 60 Upto 17K
Mount Pin Pitch: 10 mils L: Medium gates 1
QFPT Body Width: .65" to 1.7" C: Low
Ceramic
Surface # Pins: 28 to 84 R: Medium eJA2: 70 -45 Upt025K

Mount Pin Pitch: 40 to 50 mils L: Medium gates 5
CLCC Body Width: .45" to .97" C: Medium
Plastic
Surface # Pins: 28 to 84 R: Medium eJN: 65 - 50 Upto 17K

Mount Pin Pitch: 50 mils L: Medium gates
PLCC Body Width: .49" to 1.19" C: Low 1.05
Ceramic/Plastic Ceramic/Plastic Ceramic/Plastic
Through- # Pins: 64 to 299 R: Low/Low eJN Upt075K

Hole Pin Pitch: .100 mils, 70 mils L: LowlLow 40 -19/ gates
PGA Body Width: 1.033" to 1.7" C: High/Low 46 -38 11/3.5-5
Notes: 'R = Resistance, L = Inductance, C = Capacitance

2Assuming Static Airflow
3Assuming 1.5~ CMOS Technology
4.0 Electrical Considerations for the Assignment of Signal, Power, and Ground Pins
,Driven by the continual demand for high speed systems, CMOS ASICs that exhibit output drive levels,
rise and fall times, and propagation delays comparable to yesterday's ECL circuits are now being devel-
oped. Consequently, the problems intrinsic to ECL design (even thermal management> are now appearing
in CMOS designs. These problems, based on noise and its effect on the device, are introduced in this sec-
tion and possible solutions are discussed.
4.1 Sources and Magnitude of NOise

CMOS circuits operate by charging and discharging node capacitances through pull-up or pull-down
transistor networks constructed of P channel and N channel enhancement mode (normally off) MOSFET
transistors. As a result, these circuits generate noise when switching. The follOwing review of basic CMOS
circuits and how they work explains this phenomenon in greater depth.
1-140
4.1.1 Basic CMOS Circuits

Figure 14 shows a CMOS totem pole output buffer, the typical implementation for CMOS circuits, while
Figure 15 illustrates a CMOS-compatible input buffer, and Figure 16 depicts a CMOS input buffer config-
ured to be TIL compatible.
Rp-ON
Bonding
Pad
Interconnect
cL
Figure 14. CMOS Output Buffer Model (Totem Pole)

T
Input 1KO
Package Bonding Pad Wire and Input Gate

Capac~ance Capac~ance Capac~ance
Figure 15.110 Model, CMOS Input
1-141
The sw~ching threshold of an inverter is de-

pendent on the supply voltages and mobility
(Il) of the P and N type transistors, as well as
the W to l (transistor width to gate length)
ratio of the Nand P transistors. By varying
the effective width (W) of the P and N tran- External Internal
sistors, it is possible to devise inverters (in- Input Array
put buffers) that will switch at TTl levels
even though they are implemented with
FETs.
1+ -fA
Vw, VTN = Thresholds of
P and N transistors
Voo= Supply voHage
j.lp Wp • LN
~. l p . WN
Figure 16. I/O Model, TTL Input

Internal CMOS circuits, such as the NAND gate shown in Figure 17 are typical of CMOS logic deSigns,
which can be represented as a pulJ-up network and a pulJ-down network, each with its own logic and
analog characteristics.
Pull-up
Network
Output
Pull-down
Network
General Structure:
Output Is e~her pulled up or down. Inputs
are never active or inactive simultaneously An Example of a 2-lnput NAND Gate
Figure 17. CMOS Basic Gate Structure: The Pull-up/Pull-down Network
1-142
The other type of element used in CMOS circuits is the transmission gate, or T-gate, which is useful for the
efficient construction of multiplexers and sequential circuits (D-flops, latches, etc.) as shown in Figure 18.
-L SEL OUT
t
P Transistor
0 Hi-Z (floating)
IN 0 o OUT IN (pass)
I N Transistor
I SEL
Transmission gates either pass a signal or inhibit it by floating, permitting another, active transmission gate to
drive the bus to which muttiple transmission gates are often tied. Transmission gates are useful for constructing
muttiplexers and flip-flops. 10
Figure 18. CMOS Basic Gate Structure: The Transmission Gate
4.1.2 Output SwItching Noise and Simultaneous Switching Outputs (SSOs)

The greatest source of noise in a CMOS circuit is the result of an output switching either high to low or
low to high, particularly into or out of a high capacitive load. CMOS outputs drive two types of loads,
either CMOS loads, which are high in capacitance but low in leakage current, or TTL loads, which are
lower in capacitance but higher in leakage current. Therefore, the AC and DC currents that the buffers see
when they switch depend greatly on the type of driven load and its capacitance. When this load dis-
charges through the N-type transistor of the totem pole output, as illustrated in Figure 14, the effect is that
of a capacitor discharging through resistance. Consequently, the initial current is high and decreases over
time as the output node capacitance becomes charged. Similar currents may be observed when charging
the node capacitance, as in the case of a low-to-high transition.
1-143
Figure 19 shows the characteristic resistance and capacitance of various parts of the output of an ASIC
device.
Chip Power Plane
0- •••••
d~ and i,
'--f--Chip Ground Plane
n---------------------~~--~--~
=- Vss
System Ground Plane
SSO noise is proportional to the number of SSOs, the current switched by each in a common
direction (H to L in this case), and the inductance between the load and the system ground. This
is represented as
di
i'J. V (ground bounce) = (- L) N dt.
where N is the number of SSOs, assuming all have the same dildt.
Figure 19. Electrical Model of Simultaneously Switching Outputs
Although small, the total inductance becomes a critical factor when discharging or charging output ca-
pacitance, since the instantaneous current (i) is high. Recall that the self-induced voltage in an inductance,
(L) is expressed by
L *di
i'J.VINDUCED = --ar-
where t is time and d is rate of change.
In a high-drive CMOS device driving high loads, such as 200 pF, through a voltage swing approaching
5 volts with a rise/ fall time of < 2 ns, the instantaneous current may be
i =C • dv. ... C • i'J.v (average over rise and fall time)

dt .M
This induced voltage appears as noise on the receiving end of the signal as referenced to the ground. The
current on a high-to-Iow transition is sunk into ground, causing the current to "bounce" or rise relative to
other signals referenced to it. This ground bounce phenomenon may also apply to power on low-to-high
transitions, yielding a similar noise problem.
Noise on signals may cause false triggering on the input buffer(s) being driven, or at least create a win-
dow of ambiguity in the time at which the driven input should switch (see Figure 20). Therefore, noise
may result in degradation in speed resulting from adding settling time to a delay and may even result in
1-144
CMOS Channe//ess Gate A"ays Application Notes
functional effects if false triggering occurs. Furthennore, if N multiple outputs under this condition switch
simultaneously, the induced voltage is increased as a multiple of the number of outputs
di
nV =N* L * dt
VIN • E------~----+~=~------
2.0V
O.BV
O.OV
•
Noise Margin Reduction Due to Ssos
In this example, outputs switching H to L resu~ in a ground bounce or rise in the chip ground relative to
system ground.
11.1
• The rise appears as Hthe input signal vottage levels are reduced proportionally. If the bounce is too
great, the input voltage is below V1H causing false triggering.
• In the L to H case, it is the low input levels (VIL ) that are affected.
Figure 20. Effect of SSO Noise on Thresholds

Not only inductance but also characteristic resistance can create noise problems. The following para-
graphs summarize the types of noise that exist in CMOS systems and explain how packaging impacts this
noise.
4.1.3 Self-Induced Noise

Self-induced noise results when high-speed, high-drive outputs switch and introduce a spike on the signal
relative to ground. The SSO effect, discussed previously, is an example of the level of self-induced noise
that can occur. It is predicted by
where L is the inductance between the pin and ground as well as the trace inductance. I1i is the instantane-
ous current and llt is the fall/rise time.
4.1.4 Mutually Induced Noise

Mutually induced noise (a fonn of crosstalk) occurs when a signal trace that has been running parallel to
another for some distance switches, inducing a voltage into the adjacent wire. Since both inductive and
capacitive coupling occur only during signal transition and propagation, the effect is additive, as the sig-
nal propagates down the trace. Resultant noise propagates in both the forward and backward directions
down the line. The forward crosstalk has a pulse duration equal to the rise and fall of the signal, with an
amplitude equal to the difference between the capacitive and inductive coupling. Backward crosstalk has
a pulse duration equal to the transition time down the trace and an amplitude dependent on the sum of
the inductive and capacitive coupling as well as the trace length.
1-145
4.1.5 Capacitive Coupled Noise

Another form of crosstalk resulting from mutual signal coupling, this noise occurs in proportion to the
dielectric constant of the board, the distance of trace separation, and the trace length and width. Acting as
two thin parallel plates, these traces couple switching current as integrated over time.
4.1.6 Ringing on Signals

From basic circuit theory, the designer will recall that if the signal line impedance does not match the out-
put impedance of the buffer, then the signal is not naturally dampened. If the impedance of the load is less
than that of the buffer, the signal is over-damped and will have a slow rise/ fall time. However, if the
buffer possesses lower impedance, then the signal is under-damped and may ring, as illustrated by
Figure 3. Typically, signal line impedances are in the range of 50 to 250 Q, while in the past buffers pos-
sessed "on" resistances of 500 Q to 2 K.Q. However, due to the need for higher current sourcing/sinking
and faster switching speeds, "on" resistances of output buffers have corne down to the 10- to 50- Q range,
requiring the use of special termination techniques, discussed in the Fujitsu Application Note "Interfacing
CMOS and BiCMOS VLSls."
4.1.7 iR Drop
Up to this point, the sources of noise discussed have depended on inductance or capacitance. Since the DC
current that a ground pin may sink, or that a power supply pin may source can be significant, the familiar
voltage drop across a resistor, as current passes through it, is also a source of noise. This iR drop is the
phenomenon that limits the sum of source and sink currents through power and ground pins respectively.
Ohm's Law describes the effect of this noise source in the following equation defining voltage rise or drop
due to iR effects:
N-l
~V=R * L in
n=O
where
R is the output pin-to-ground (sink) resistance, or power pin return-loop (source) resistance (in-
cluding the "on" resistance of the respective N or P channel device) and
in is the current through the nth output pin connected to this common ground or power pin.
4.1.8 Current Spiking or "Crowbar Noise"

As Figure 14 illustrated, a CMOS output buffer is constructed as a totem pole in which the output is taken
from the common source (P type) and drain (N type) with the drain of the P type connected to power and
the source of the N type connected to ground. When the input to the totem pole (the P and N gates)
switches, the Miller capacitance of the gate causes the gates to charge or discharge at some specified time
constant. It is possible that both transistors can be on, one in saturation and the other passing through the
linear region, creating a current path between power and ground that can damage the device. This is less a
concern for internal transistors than it is for the "beefy" transistors at the I/O. This current spiking can not
only introduce noise on the power and ground planes, but may damage the device as well. For this rea-
son, Fujitsu has taken precautions in the design of the CMOS output buffers to prevent this problem from
occurring.
4.2 Recommended Strategy for Pin Assignment

The assignment of Clock, Scan, and other signals, as well as power and ground, to specific pins on the
package affects electrical behavior (speed, noise, reliability, etc.), board manufacturing requirements, and
device reliability. Therefore, optimal pin assignment strategies should consider the variables over which
the user has control (placement of non-scan inputs, outputs and bi-directionals) and the variables over
1-146
which the vendor has control (power, ground and scan signal placement). Out of these relationships a
method of placement can be developed, using the following approach:
(a) Prioritize the signals whose placement is most critical.
(b) Establish guidelines for the location of these signals, both in absolute position and relative to
other signals.
4.2.1 Prioritization of Signals for Placement

Noise minimization is used to establish signal prioritization. All of the various forms of noise discussed in
the last section are dependent on either i or di/ dt, and L, M, R, or C. The signals affect i and di/ dt, while
the package pin location affects L, Rand C. Figure 21 provides an illustration of how electrical characteris-
tics vary by pin position.
~
L R C t Increasing
C::::::::::
~
I
Iincreasing
L RC l
Figure 21. Variation In Inductance, Resistance, and Capacitance
as a Function of Pin Position
In general, the further a pin's external contact is from the die connection, the greater its resistance, imped-
ance, and capacitance. Therefore, signal prioritization is established according to current or its time de-
rivative, while location is guided by package pin characteristics. Input signals are classified by their noise
sensitivity. If a spike on an input could be disastrous (as with a clock), that signal should be carefully lo-
cated. Table 7 classifies signal type by electrical characteristics.
Table 7. Electrical Characteristics of Each Signal Type

Signal Type Current Characteristics (General)
Ground Highest i, DC, and dildt
Power High i, DC, and ditdt
High drive outputs High ditdt
Clocks Highest noise sensitivity
Low drive outputs --
Other Signals --
4.2.2 Characteristics of Package Pins by Location

The inductance, capacitance, and resistance, all of which are critical to minimizing noise, are related not
only to board construction, but also to the pin position on given packages, and the circuit to which the
pins are bonded. The pin, lead frame, bonding wires, pads, and buffers (input, output or bi-directional) all
influence the characteristic L, R, and C of the line. See Figure 22.
1-147
0 • • 0
0 • • 0
0 • • 0
0 • • 0
0 • • 00
0
• •
0
• • 00
0 • •
0 • • 0
0
0
•• • 00
• 0
0 • •
0 • • 00
0 • •
I II I I I I I I I I I I I I I
76543210 01234567
(pF) (pF)
• Package Pin Capacitance
Totail/a Pin Capacitance
Figure 22. Measured Pin Capacitance by Package Position
4.2.3 Relating Signal Type to PIn Location

Since power and ground pins demand a large DC current (i), iR drops are of great concern. Therefore,
Fujitsu assigns power and ground to pins with minimum resistance (and inductance). High-drive outputs
exhibit a large di/dt, resulting from high capacitive loading, so the best pins for these signals are those of
minimum inductance. Furthermore, adjacent pins possess the greatest M, and thus couple the most M di/
dt noise. This means that noise-sensitive inputs, such as clock inputs, should be isolated from pins that
handle high di/ dt, such as high-drive outputs.
4.2.4 MInImizing IR Drops on Power and Ground Pins

Placement of ground pins is critical because noise on ground affects the voltage level of all signals refer-
enced to it. For this reason, Fujitsu has preassigned power (V DD) and ground (V55) signals for all packages
in a given gate array family according to the electrically optimal locations. Preassigning power pins per-
mits Fujitsu to develop load boards (which interface the packaged device to the tester) advanced enough
to carry out high-speed functional testing of devices with high I/O count and to drive devices with rela-
tively low noise. Fujitsu also took into consideration manufacturing issues such as adjacent pin shorting
due to probes and package rotation. The predefined power and ground assignments for Fujitsu devices
are found in the Package Pin Assignment Guide in the Design Manual for the appropriate gate array fam-
ily, and are used in conjunction with the Package Matrix to determine pin assignment.
4.2.5 MInImIzing the Self·lnductance of a Signal

Fujitsu believes that an ASIC designer concerned about designing a mini-computer, PC, mainframe or
other complex system should not have to be concerned with determining specific on-chip noise issues,
particularly since board-level noise issues are demanding enough. Therefore, Fujitsu developed a straight-
forward grouping scheme for the placement of various types of signals. relative to their distance from the
nearest power and ground pins. As Figure 23 shows, the self-inductance associated with a given signal is
1-148
a function of the length of wire between it and its nearest ground (for a falling transition) or power (for a
rising transition).
T
Second-order model of an output driving interconnect metal and four input buffers.
As wire·length increases, so does inductance and resistance.
Figure 23. Self-Inductance In a Circuit

Since di/ dt can vary greatly for outputs within a group, there are some general restrictions relating to
SSOs and their total current to the number of grounds on the chip. This is done by summing representa-
tive values like those shown in Table 5-4 in Chapter 4, which are weighed depending on the IOL of the
given output buffer. Notice that, if the output buffer employs noise limiting circuitry (edge rate grading)
then di/ dt is less and the representative value is also less, meaning more of these outputs can be sup-
ported per ground pin.
In summary, to ensure that the iR drops and the ground bounce effect (L di/ dt) are within reasonable
limitations, Fujitsu has established guidelines for determining the number of necessary grounds and de-
fining the pinout.
4.2.6 Placement of Clock and Asynchronous Clear/Preset Signals

In addition to causing the ground bounce and iR drops that can deteriorate an output signal's quality and
alter the ground reference, output switching can also couple noise into adjacent sensitive inputs by mutual
inductance, as shown in Figure 24. For that reason, the designer should ensure that clocks and asynchro-
nous clear and preset signals are not placed near outputs, particularly high drive outputs. To further iso-
late inputs from noise, the designer should minimize the inductance (length) of the return loop from the
input buffer to ground by placing this type of input near a ground pin. The mutual inductance of the in-
put buffer itself can be minimized if it, and any outputs nearby, are not assigned to high inductance pins.
As discussed in Section 4.2.1, the center pins of a DIP, f1atpack, or PLCC possess the lowest Land R, as do
the inner rows of PGAs, making them most suitable for VDD, Vss and high drive outputs. But the edges of
the package, while suitable for data Signals, should be avoided when placing clock and other sensitive
signals, as they exhibit a high mutual inductance and large iR drop.
1-149
Applicalion Noles CMOS Channel/ess Gale Arrays
,,
INput
Signal
0'"
: : :', fS1\
--J.--t:v-
, , 0
0"
1",0
fs2\
,:
I I • I
Ignored for simplicity
Noise is introduced on the adjacent lead S2 as Sl is driven in a manner described by Faraday as
di 51
Vs= -M-ri/
where M is the mutual inductance between the adjacent leads.
If S2 is also being driven. then the mutually induced noise is superimposed on the
seH induced noise already present. as described by
di 51 di 52
VS2 = -M -cit + L2-cit
Figure 24. Causes of Crosstalk
4.3 Summary: Choosing the Package and Assigning the Pins

This discussion of noise as related to packaging and its effect on pinout should help the designer appreci-
ate the care Fujitsu has taken to ensure that noise margins within the device are restricted to maximize
system reliability. It should also provide the designer with a basis for establishing optimum pin assign-
ments. A step-by-step procedure for choosing an optimal package and assigning pins to it follows.
4.4 Package Selection Checklist

When selecting a package for an ASIC device, the designer should consider the following points:
a. Define a subset of the Fujitsu packages that can be supported by your company's manufactur-
ing capabilities.
b. Estimate, as closely as possible, the gate and I/O counts of the circuit(s) to be packaged.
c. Determine the number of power and ground pins required by considering the following:
1. Representative value limitations for SSOS
2. Limitation of the sum of the sink current (IOL) per ground pin
3. Limitation of instantaneous current per ground pin to satisfy metal migration
restrictions
d. Using the package and pin assignment section of the Design Manual, determine the packages
that satisfy the signal, power, and ground pin requirements of the circuit.
e. Make sure that the electrical, mechanical, and thermal properties of the chosen packages are
suitable for the application.
f. Check the mechanical dimensions in Fujitsu's ASIC Package Catalog and the power and
ground pin assignment tables and grouping charts in the appropriate package and pin assign-
ment tables for the chosen technology. Please contact Fujitsu regarding pricing trade-offs when
evaluating packages or partitioning the system.
1-150
CMOS ChanneJ/ess Gate Affays Application Notes
4.5 Pin Assignment Checklist

a. Follow Fujitsu's pin assignments in the Package and Pin Assignment section of the Design
Manuals. Although multiple pinouts of the same package may be offered in some cases, alI
power and ground signals indicated on the chosen package must be connected on the board.
b. Assign input pins (in excess of 5 MHz) and high power output buffers (lOL =24 rnA) accord-
ing to the appropriate pin assignment table.
c. Place alI high-drive (power and high power) outputs near ground pins; the higher the drive,
the closer they should be placed. SSOs should be placed particularly close to ground pins.
d. Place SSOs in groups belonging to given ground pins.
e. Distance noise-sensitive signals such as clock and asynchronous clear and preset signals away
from SSOs and high-drive outputs. Also, assign them to pins with low inductance and resis-
tance, preferably near a ground, if one is available away from SSOs or high-drive outputs.
f. Place SSOs on low inductance pins, such as those located on the inner rows and middle posi-
tion of the PGAs.
These guidelines assist the designer in choosing the best package for the application, resulting in a device
with reliable and predictable electrical performance and without harmful DC and AC effects on the sys-
tem. There are other system interface issues such as device decoupling and termination that should be
10
considered during design. These are discussed in Fujitsu's application note, "Interfacing CMOS and BiC-
MOSVLSIs."
5.0 Thermal Issues in CMOS ASIC Packaging

CMOS has traditionally been associated with low power, one of the classic advantages it has over ECL.
While ECL continualIy draws high current to supply its internal differential amplifiers and emitter-fol-
lower circuits, CMOS draws current primarily when it is switching. The total power dissipation of a
CMOS device is dependent on the number of gates, the switching frequency, and the loading on the out-
put of the gates. The revolution in CMOS technology that has resulted in densities of lOOK gates has been
accompanied by increases in all of the factors influencing power dissipation. Prior to 1985, when Fujitsu
introduced the world's first 20,000 gate array, the C2ooo0UH, CMOS gate arrays were not of sufficient in-
tegration density to warrant concerns about thermal control, but advancing CMOS technologies have
forced this issue to the surface.
Because power is the product of current and voltage, power dissipation is important when defining the
necessary power supply currents. Propagation delays and reliability of a device are also dependent on the
temperature at which the die operates, as discussed in Sections 2.3.3 and 2.4.4. To ensure that speed and
reliability requirements are satisfied, the designer needs to estimate the power dissipation of the device
and, from this information, choose appropriate packages and system cooling techniques.
5.1 Estimation of Power Dissipation In CMOS Circuits

There are two constituent factors in the power dissipation of a semiconductor device: the DC power,
which is dependent on the steady-state (quiescent) current, and the AC or dynamic power.
5.1.1 Estimation of Dynamic (AC) Power Dissipation

CMOS circuits are constructed of PETs, which possess very small leakage currents. Therefore, CMOS pos-
sesses a low quiescent or steady-state current. CMOS dissipates power primarily while it is charging or
discharging node capacitance, or drawing switching current, which occurs as a gate changes state. This
can be modeled as the familiar pull-up/pull-down circuit discussed in Section 4.1, charging and discharg-
ing a node capacitance, CL (shown in Figure 14). This model holds true whether the node is internal or
off-chip.
1-151
Application Notes CMOS Channel/ess Gate AITBYs
The switching current is a result of charging and discharging the node capacitance which, for periodic sig-
nals, occurs twice a cycle: once while charging the capacitance, and once while discharging it. The energy
involved in charging or discharging a capacitance is 1/2(CLV2). The power is the energy divided by the
period of time between successive changes (the clock period, TI, multiplied by the two transitions that
occur per cycle. Therefore, the dynamic or switching current of a CMOS circuit is defined as
• (CL' V2)
Pd-dyn=2
2 • T
where V is the supply voltage and f is the frequency of the given signal.
This is the power calculation for a single gate. The power dissipation for entire chip, however is much
more complicated, since not all gates are simultaneously active. The degree of switching activity varies
greatly within a circuit and depends on the nature of the circuits (synchronous sequential gates tend to
switch concurrently, while combinatorial gates switch more randomly), the input stimulus (whether the
circuit is stimulated at a periodic interval or asynchronously), and other design-dependent issues. Based
on Fujitsu's experience, gate activity is on the average about 20 percent. This same figure is applied to the
power estimation for output and input buffers.
5.1.2 Estimation of Quiescent (DC) Power Dissipation

There are two sources/sinks of OCcurrent in a CMOS ASIC: the leakage current of the gates (gate leak-
age) and the DC current that flows through output and bidirectional buffers in output mode. The gate
leakage in CMOS devices, even dense ones, is in the range of tens of microamperes, and is negligible. The
DC current of the output buffers is the current that the buffer sources or sinks in steady state. This current
level depends on the leakage currents of the driven loads, but for simplicity will be assumed to be equiva-
lent to the IOL and IOH rating of the buffers. The DC power can be estimated for each output buffer by
analyzing:
a. the product of source current times the voltage difference from the power rail (VDD - VOH), and
b. the sink current times the low-level voltage (VOL).
This calculation is valid provided the duty cycle, or the portion of the cycle in which the output is low ver-
sus the portion of the cycle in which the output is high, weighs the sum of the two components. The total
DC power may be determined by extending this method to each output and bidirectional buffer.
5.1.3 Estimation of Total Power Dissipation

The total power dissipation of a circuit is the sum of the DC and AC components. I/O buffers dissipate
both DC and AC power when switching, while internal gates may be considered for the sake of simplicity,
to dissipate only AC. The theory behind CMOS power dissipation is simple; however, the task of calculat-
ing the power dissipation can be tedious and prone to error. Therefore, Fujitsu has devised methods for
estimating the power dissipation for each CMOS technology. These methods are presented in the Design
Manual for the appropriate technology, available through the Field Applications Engineers at local Fujitsu
Sales Offices or Technical Resource Centers.
5.2 The Relationship Between Power Dissipation and Temperature

A device draws current through the power supply-pins and the I/O buffers. As it does so, it dissipates
thermal energy proportional to the power dissipated in the device. Assuming that the power dissipation
of a device has been estimated as Pd, using the method described in Section 5.1.1, how can one relate this
power to the temperature of the die and the package, and also determine the warming effect on the sur-
rounding environment?
The answer lies with two principles of heat transfer: conduction and convection. When an object is in a
state of thermal equilibrium it is isothermal, seeing a constant temperature across its body. As the tem-
1-152
CMOS Channe//ess Gate Arrays Application Notes
perature of one end of the object is raised by the introduction of energy, it is no longer in equilibrium; heat
begins to flow from the warmer region to the cooler region through the process of conduction.
When a lake in winter is filled with water at a constant temperature, just above 32°F, it may still freeze. It
will freeze at the surface, however, not the bottom. This is because heat is drawn from the water into the
air through convection, the act of cooling by a gas.
These same mechanisms, conduction and convection, act upon a packaged semiconductor device and de-
termine its junction temperature, the package or case temperature, and the warming effect on the sur-
roundings.
5.2.1 Determining the Junction Temperature of a Device

Figure 25 shows the paths through which heat flows in a packaged device. Each interface of materials
with different properties of thermal conduction must be considered when determining the flow of heat
from the die to the surroundings. The back side of the die is attached to a lead frame or slug, usually by
means of a eutectic bond (material heat bonded with some conductive material, such as silver). Heat flows
through this path from the die to the package, then from the package to the surrounding air.
10
Figure 25. Heat Flow through a Cavity-down Ceramic PGA with an Annular Fin Heat Sink
From the die junction to the package, there is some associated thermal impedance (or resistance to the
flow of heat). This impedance can be calculated, but may also be estimated in the following way. Operate
a device and determine its power dissipation. Then, using some mechanism such as a thermal diode,
whose forward bias voltage tracks linearly with temperature, determine the junction temperature. Then,
after measuring the case temperature, determine the thermal impedance along the path from the die junc-
tion to the case (package body) using the following equation:
. (Te-Tj)
9,e = P4
where Te and Tj are the case and junction temperatures, respectively.

A similar procedure is followed when determining the thermal impedance between the junction and the
ambient environment, except that the case temperature is replaced by the measurement of the ambient
temperature
1-153
While Bjc relies on conduction as its cooling mechanism, Bj. reflects convective cooling. Therefore, aj. var-
ies with airflow and is specified at a given airflow, or as static (= 0).
Since thermal impedance depends on the heat conduction path between the die and some other interface,
it can be modeled the same way as current flowing through real impedance or resistance. TherFfore, as in
circuit theory, when multiple interfaces are oriented in parallel, the thermal impedance is lowered. How-
ever, the situation is different from circuit theory in that when a very low impedance interface, such as a
heat sink, is placed in the conduction path the flow capacity is increased, with the heat sink pulling heat
out at a faster rate, lowering the thermal impedance.
5.2.2 Using Thermal Impedance Data

Thermal impedance information and power dissipation information are used to estimate junction tem-
perature and ambient temperature rise. Which impedance figure to use is based on how the device is to be
cooled. If the device is air cooled (convective), then aja should be applied, while ajc should be used if con-
ductive techniques such as heat pipes or cold plates are employed. For example, the junction temperature
may be obtained by multiplying the power dissipation of the device by the appropriate 9ja and adding
the ambient temperature. It is not surprising that this indicates that a small thermal impedance is desir-
able to achieve a low junction temperature.
Junction temperature is used to determine worst case delay multipliers and the package options for
Fujitsu's CMOS AU (Sea-<>f-Gates) family. The junction temperature also indicates whether reliability
goals are being met. The designer can trade off packages (which exhibit varying thermal impedances)
with cooling techniques (such as varying the amount of airflow in a system) to achieve the desired junc-
tion temperature and consequently, worst case delay multiplier and reliability targets.
5.3 Summary of Thermal Issues

Although thermal factors in CMOS design have not previously been an issue, the increased frequency and
density of current generations of CMOS devices require such considerations to be made. This section has
surveyed some of the issues involved in applying thermal analysis to CMOS devices and using the infor-
mation gained from such analysis to determine the appropriate packaging and cooling techniques.
6.0 Summary of the Note

As VLSI circuits increase in complexity, pin count and die size increase as well, placing greater demands
on packaging, board layout, and manufacturing. Fujitsu has addressed these problems with exotic forms
of packaging such as the surface mount PGA and the staggered PGA, while also stressing the importance
of other surface mount packages. But simply making these packages available is not enough; Fujitsu must
also provide the technical support necessary to ensure that these packages can be used successfully by our
customers. Field Applications support in the local sales offices, technical information such as this Applica-
tion Note, and packaging consultants at Fujitsu's San Jose headquarters all provide this support.
1-154
References
Applications Engineering Staff. Points and Problems on Reliability and Mounting of Surface Mount ICs. Fujitsu
Limited, 1988.
Hoshino, H. and K. Gotanda. Reliability of Surface Mount ICs. Fujitsu Limited, 1987.
Kane, Jim. Surface Mount Technology. Santa Clara: Fujitsu Microelectronics Inc.; August 1986.
Fujitsu Limited, Semiconductor Marketing. Integrated Circuits Quality and Reliability. Tokyo, Japan: Fujitsu
Limited, 1984.
Mather, John C. "A Status Report on Multilayer Circuit Boards." Proceedings, 30th Electronic Components
Conference. 1980, pp 302-306.
Vest, Roger. "How to Design a Fine Pitch Footprint." Nepcon East: 1988.
1-155
ApPlication Notfls CMOS Channelless Gate AITBYs
1-156
Section 2
AU Series CMOS Gate Array

Unit Cell Library
I Page Contents
2-2 Unit Cell Specification Information

2-5 Inverter and Buffer Family
2-15 NAND Family
2-29 NOR Family
2-43 AND Family
2-49 OR Family
2-55 EXNOR/EXOR Family
2-65 AND-OR-Inverter Family
2-73 OR-AND-Inverter Family
2-81 Multiplexer Family
2-103 Clock Buffer Family
2-117 Scan Flip-Flop (Positive Edge Type) Family
2-179 Non Scan Flip-Flop Family
2-207 Binary Counter Family
2-247 Adder and ALU Family
2-255 Data Latch Family
2-273 Shift Register Family
2-285 Parity Generator/Selector/Decoder Family
2--313 Bus Driver Family
2--323 Clip Cell Family
2--327 I/O Buffer Family
2-439 Single-Port RAM Specification
2-445 Dual-Port RAM Specification
2-451 Triple-Port-RAM Specification
2-457 ROM Specification
2-461 Appendix A: General AC Specifications
2-463 Appendix B: Hierarchical Structure
2-465 Appendix C: Estimation Tables for Metal Loading
2-473 Appendix D: Available Package Types
2-475 Appendix E: TTL 7400 Function Conversion Table
2-479 Appendix F: Alphanumeric Index of Unit Cells
AU Series Unit Cel/ library CMOS Channel/ass Gate Arrays
Unit Cell Specification Information
This section contains specifications for all the unit cells available forthe CG21 Series CMOS Gate Arrays. The
unit cell (gate array) is a functional group of one or more basic cells or gates. A basic cell contains one pair of
P-channel and one pair of N-channel transistors (and two pairs of smaller N-channel resistors used for com-
piled cell construction).
How to Read a Unit Cell Specification
The following paragraphs numbered 1-10 explain how the information given in the CG21 Unit Cell Library is
organized. Each of the numbers corresponds to an area of the Unit Cell Library page illustrated on the right.
1. The unit cell name appears in the upper left corner of the page.
2. The unit cell function is given on the same line as the unit cell name.
3. The number of basic cells (Be) or equivalent that make up the unit cell is shown in the upper right
corner of the page.
4. Propagation delay parameters for the unit cell are given in a table on the upper right side of the
page. The basic delay time of the unit cell (to) is given in ns. KCL, the delay constant for the cell (de-
g lay time per load unit) is given in ns/pF. KCL2 and COR2 are a delay constant and an output driving
factor used to calculate delay when a unit cell is loaded beyond its published output driving factor
(CDR)·
5. The cell symbol (logic symbol) is shown in the top left box under the cell name.
6. Clock parameters (in ns) for unit cells such as flip-flops and counters that make use of clock signals
are given in a table directly below the propagation delay parameters.
7. The input loading factor of each input of the unit cell are shown in a table directly under the cell sym-
bol box on the left side of the page. The input loading factor is the value of the load placed on a net
by the connection of the unit cell input. Unit cell loading factors are shown in load units (Iu). The
Fujitsu CMOS load unit is the input capacitance of an inverter used for the measurement and calcu-
lation of capacitive loads presented to unit cells within the gate array.
8. The output drive factorof each output of the unit cell is shown directly under the input loading factor.
The output drive factor is the maximum number of load units the unit cell can drive while performing
at published specifications.
9. The function table (truth table), if applicable, is shown in a box at the lower left side of the page.
10. The unit cell schematic, or equivalent circuit, illustrates how discrete components would be con-
nected to perform the unit cell function. It is shown in the lower right corner of the page or on the
page following.
2-2
CMOS Channel/ess Gate Arrays AU Series Unit Cel/ Library
FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION I AU Version

Cell Name Function Number of BC
1 T2D 2:1 srlector 2
Cell Symbol
I Propagation Delay Parameter
2 tup tdn
Path
3 to KCL to KCL KCL2 CDR2
4 0.50 0.15 0.56 0.10 A,B~X

0.54 0.15 0.41 0.10 S~X
5
A -
B~ p-X
S1
S2-
'--
6 Parameter Symbol Typ (ns)'
7 Pin Name
Input Loading
Factor (Iu)
A,B 1
S 1
8 Output Driving
Pin Name Factor (Iu)
X 14
. Minimum values for the typical operating conditon .
The values for the worst case operating condition
are given by the maximum delay multiplier.
Function Table Equivalent Circuit
Inputs Output
t~,
A B S1 S2 X
9 A
L X L H H
H X L H L
X L H l H
X
L
L
H
H
H
H
H
L
L
H
L
H
l
H
l
l
H
L
H
l
INHIBIT
INHIBIT
INHIBIT
INHIBIT
S1
B
t;J--
10 S2
AU-T2D-E2 Sheet 1/1 I I Page 17-17
2-3
AU Series Unit Cell Ubrary CMOS Channelless Gate Arrays
CMOS Channel/ess Gate Arrays AU Series Unit Cell Ubra!}'
Inverter, Buffer Family
Unit Cell Basic

Page Name Function Cells
2-7 V1N Inverter

2~ V2B Power Inverter
2-9 V1L Inverting Clock Buffer 2
2-10 B1N True Buffer 1
2-11 BD3 Delay Cell S
2-12 BD4 Delay Cell 4
2-13 BDS Delay Cell 9
2-14 BD6 Delay Cell 17
2-5
AU Series Unit Cell Ubrary CMOS Channel/ess Gate AITBYs
2-6
Cell Name I Function I Number of BC
V1N
Cell Symbol
I Inverter
Pro~agation Delay Parameter
I 1
tup tdn
to KCL to KCL KCL2. CDR2. Path
0.2.3 0.13 0.2.8 0.07 0.10 4 A -+ X
A -[)o- X
Parameter Symbol Typ(ns)'"
Input Loading
Pin Name Factor (R.u)
A 1
Output Driving
X 18
* Minimum values for the typical operating condition.

AU-V1N-E2. I Sheet 1/1 I I Page 1-1
2-7
FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION I "AU Version
V2B
Cell Symbol
I Power Inverter Pro~agation Delay Parameter
I 1
tup tdn
to KCL to KCL KCL2 CDR2 Path
0.20 0.07 0.20 0.04 0.07 7 A-+X
A
-+- X
Parameter Symbol Typ(ns)*
Input Loading
Pin Name Factor (Rou)
A 2
Output Driving
X 36
AU-V2B-E2 I Sheet 1/1 I I Page 1 2
2-8
VIL
Cell Symbol
I Inverting Clock Buffer agation Delay Parameter
Pro~
I 2
tup tdn
0.28 0.03 0.54 0.03 A .. X
A -{>o- X
Parameter Symbol Typ(ns)t'
Input Loading
A 4
Output Driving
X 55

AU-VlL-E2 I Sheet 1/1 I I Page 1-3
2-9
B1N
Cell Symbol
I True Buffer Propagation Delay Parameter
I 1
tup tdn
0.47 0.13 0.55 0.07 A .. X
A -{>- X
Input Loading
A 1
Output Driving
X 18
AU-B1N-E2 I Sheet 1/1 I Page 1-4
2-10
FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION I AU" Version
BD3
Cell Symbol
I Delay Cell Propagation Delay Parameter
I 5
tup tdn
4.27 0.13 3.77 0.10 0.11 4 A .. X
A~X
Parameter Symbol Typ(ns)'·'
Input Loading
A 1
Output Driving
X 18

The values for the ~orst case operating condition
AU-BD3-E2 I Sheet 1/1 I I Page 1-5
2-11
BD4
Cell Symbol
I 4
tup tdn
2.85 0.46 3.28 0.25 0.29 4 A ... X
A-[>-X
Input Loading
Pin Name Factor (.tu)
A 4
Output Driving
X 6
AU-BD4-E2 I Sheet 1/1 I I Page 1-6
2-12
FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION I "AU" Version
BDS
Cell Symbol
I 9
tup tdn
8.74 0.13 8.28 0.08 0.12 4 A-+X
A --[>-x
Parameter Symbol Typ(ns)'~
Input Loading
A 1
Output Driving
X 18

AU-BDS-E2 I Sheet 1/1 I J Page 1-7
2-13
BD6
Cell Symbol
1 17
tup tdn
17.6 0.14 17.46 0.07 0.11 4 A'" X
A -{>--X
Input Loading
A 1
Output Driving
X 18

AU-BD6-E2 I Sheet 1/1 I Page 1-8
2-14
CMOS Channel/ess Gate Arrays AU Series Unit Cell Ubrary
NAND Family
Unit Cell Basic

2-17 N2N 2-input NAND 1

2-18 N2B Power 2-input NAND 3
2-19 N2K Power 2-input NAND 2
2-23 N4B Power 4-inpul NAND 4
2-25 NBB Power 8-input NAND 6
2-27 NCB Power 12-input NAND 10
2-28 NGB Power 16-input NAND 11
2-15
AU Series Unit Cell Ubrary CMOS Channe/less Gate AlTays
2-16
N2N
Cell Symbol
I 2-input NAND Propagation Delay Parameter
I 1
tup tdn
0.30 0.13 0.45 0.11 A~ X
A1
A2 =V- X
Input Loading
Pin Name Factor (9.u)
A 1
Output Driving
X 18
1, Minimum values for the typical operating condition.

I
AU-N2N-E2 I Sheet 1/1 I I Page 2-1
2-17
FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION J "AU Version
Cell Name .1 Function I Number of BC
N2B
Cell Symbol
I Power 2-input NAND Propagation Delay Parameter
I 3
tup. tdn
0.88 0.07 1.14 0.03 A->X
Al
A2 =P- X
Input Loading
A 1
Output Driving
X 36

AU-N2B-E2 I Sheet 1/1 I 1 Page 2-2
2-18
N2K
Cell Symbol
I 2
tup tdn
0.30 0.07 0.35 0.06 0.07 7 A .. X
Al
A2 =[}- X
Input Loading
A 2
Output Driving
X 36

AU-N2K-E2 I Sheet 1/1 J [Page 2-3
2-19
N3N
Cell Symbol
I 3-input NAND Propal?;ation Delay Parameter
I 2
tup tdn
0.42 0.13 0.55 0.15 A ... X
Al
A2
A3 =v- X
Input Loading
Pin Name Factor (R,u)
A 1
Output Driving
Pin Name Factor Uu)
X 14
,', Minimum values for the typical operating condition.

2-20
Cell Name I Function 1 Number of BC
N3B
Cell Symbol
I 3
tup tdn
1.03 0.07 1.36 0.03 A ... X
~
A1
A2 X
A3
Input Loading
A 1
Output Driving
X 36

AU-N3B-E2 I Sheet. 1/1 I I Page 2-5
2-21
N4N
Cell Symbol
I 4-input NAND Pro~agation Delay Parameter
I 2
tup tdn
0.50 0.13 0.59 0.19 A ... X
Al
A2
A3
A4 m- X
Input Loading
A 1
Output Driving
X 10
"k Minimum values for the typical operating condition.
2-22
N4B
Cell Symbol
I Power 4-input NAND Proj:agation Delay Parameter
I 4
tup tdn
1.11 0.07 1.52 0.03 A ... X
ill-
Al
A2
X
A3
A4
Input Loading
A 1
Output Driving
X 36

AU-N4B-E2 I Sheet 1/1 I I Page 2-7
2-23
N6B
Cell Symbol
I Power 6-input NAND
Propagation Delay Parameter
I S
tup tdn
1.10 0.07 1. 62 0.03 0.06 7 A ... X
Al
ID--
A2
A3
X
A4
AS
A6
Input Loading
Pin Name Factor (tu)
A 1
Output Driving
X 36
,~ Minimum values for the typical operating condition.

are given by the maximum delay mul ti~1ier.
Equivalent Circuit
Al
A2
A3
X
A4
AS
A6
AU-N6B-E2 I Sheet 1/11 I Page 2-8
2-24
Ce1l Name I Function I Number of BC
N8B
Ce1l Symbol
Power 8-input NAND
I 6
tup tdn
1.15 0.07 1.77 0.03 0.06 7 A ... X
Al _r'\
A2 -
A3 -
A4 - p-- X
A5 -
A6 -
A7 -
A8 -l../
Input Loading
A 1
Output Driving
X 36

Equivalent Circuit
Al _ r ' \
A2 -
A3 -
A4 - l . . /
X
A5 _ r ' \
A6 -
A7 -
A8 - l . . /
AU-N8B-E2 Sheet 1/1 I Page 2-9
2-25
N9B
Cell Symbol
I 8
tup tdn
1.14 0.07 2.13 0.04 0.07 7 A ... X
A1-~
A2 -
A3 -
A4 -
AS - ~X
A6 -
A7 -
AS -
A9 -L/
Input Loading
Pin Name Factor (£u)
A 1
Output Driving
X 36
..'r Minimum values for the typical operating condition .
Equivalent Circuit
Al
A2
A3
A4
AS X
A6
A7
AS
A9
AU-N9B-E2 I Sheet 1/1 I I Page 2-10
2-26
NCB
Ce 11 Symbol
Power l2-input NAND
Propagation Delay_ Parameter
I 10
tup tdn
1.22 0.07 2.29 0.04 0.07 8 A -> X
_f'
Al
A2 -
A3 -
A4 -
AS -
A6 - J--- X
A7 -
A8 -
A9 -
AlO -
All -
Parameter Symbol Typ(ns)>"
A12 --"
Input Loading
Pin Name Factor (J1u)
A 1
Output Driving
Pin Name Factor (J1u)
X 36

Equivalent Circuit
Al _ f '
A2 - p..-
A3 -
A4 - l . . /
AS _ f '
A6 -
A7 - X
AS - l . . /
A9 - '
A10- p..-
All-
A12 - -"
AU-NCB-E2 I Sheet 1/1 I I Page 2-11
2-27
NGB
Cell Symbol
Power 16-input NAND
I 11
tup tdn
to KCL to' KCL KCL2 CDR2 Path
_["I 1.23 0.07 2.78 0.05 0.07 8 A-+X
Al
A2 -
A3 -
A4 -
A5 -
A6 -
A7 -
A8 - ::r--- X
A9 -
AIO -
All -
A12 -
A13 - Symbol
A14 - Parameter Typ(ns)'~
Al5 -
A16 -v
Input Loading
A I
Output Driving
X 36
"O': Minimum values for the typical operating condition.
Equivalent Circuit
Al -"'"
A2 -
A3 - P--
A4-v
AS -"'"
A6 -
A7 -
AS - v
fLS ~
L-c
"'
X
A 9-W
AIO- -<:v
All-
A12- v
Al3~
A14
Al5
Al6
AU-NGB-E2 I Sheet 1/1 I I Page 2-12
2-28
NOR Family
Unit Cell Basic

2-31 R2N 2-inputNOR

2-32 R2B Power 2-input NOR 3
2-33 R2K Power 2-input NOR 2
2-34 R3N 3-inputNOR 2
2-36 R4N 4-input NOR 2
2-41 RCB Power 12-input NOR 10
2-42 RGB Power 16-input NOR 11
2-29
AU Series Unit Cell Ubrary CMOS ChannelJess Gate Atrays
2-30
R2N
Cell Symbol
I 2-input NOR Pro~agation Delay Parameter
I 1
tup tdn
0.32 0.23 0.35 0.07 0.09 4 A ... X
Al
A2 =t>- X
Parameter Symbol Typ(ns)1'
Input Loading
A 1
Output Driving
X 14

AU-R2N-E2 I Sheet 1/1 I I Pal>;e 3-1
2-31
R2B
Cell Symbol
I Power 2-input NOR Pro~a~ation Delay Parameter
I 3
tup tdn
1.09 0.07 1.00 0.03 A ... X
Al
A2 =V- X
Parameter Symbol Typ(ns)~'
Input Loading
Pin Name Factor (iu)
A 1
Output Driving
X 36

are l?;iven by the maximum delay multiplier.
I
'U-R2B-" I Shoo< 1/1 I I Pa gc::e---,3=--~2,---,
2-32
R2K
Cell Symbol
I Power 2-input NOR Propagation Delay Parameter
I 2
tup tdn
0.36 0.11 0.36 0.05 A -> X
Al
A2 =f}- X
Par·ameter Symbol Typ(ns)'"
Input Loading
Pin Name Factor (J1.u)
A 2
Output Driving
X 36
~, Minimum values for the typical operating condition.

AU-R2K-E2 I Sheet 1/1 I I Page 3-3
2-33
Cell Name IFunction I Number of BC
R3N
Cell Symbol
I 3-input NOR Propagation Delay Parameter
I 2
tup tdn
0.67 0.33 0.37 0.07 0.10 4 A ... X
=&-
.U
A2 X
A3
Input Loading
A 1
Output Driving
X 10
~'r Minimum values for the typical operating condition.
AU-R3N-E2 I Sheet 1/1 I I Page 3-4
2-34
R3B
Cell Symbol
I 3
tup tdn
1.59 0.07 1.10 0.03 A -> X
=&-
Al
A2 X
A3
Input Loading
A 1
Output Driving
X 36
oJ: Minimum values for the typical operating condition.
AU-R3B-E2 I Sheet 1/1 I ~Page 3-5
2-35
Cell Name I Function I Number of Be
R4N
Cell Symbol
I 4-input NOR Propagation Delay Parameter
I 2
tup tdn
0.99 0.43 0.37 0.07 0.11 4 A-+X
~
A1
A2
X
A3
A4
Input Loading
A 1
Output Driving
X 6

are J!:iven by the maximum delay multiplier.
AU-R4N-E2 I Sheet 1/1 I I PaJ!:e 3-6
2-36
R4B
Cell Symbol
I Power 4-input NOR Pro~agation Delay Parameter
I 4
tup tdn
2.00 0.07 1.07 0.03 A" X
~
Al
A2
X
A3
A4
Input Loading
A 1
Output Driving
X 36
are given by_ the maximum delay multiplier.
AU-R4B-E2 I Sheet 1/1 I I Page 3-7
2-37
R6B
Cell Symbol
I Power 6-input NOR
Pro~al(ation Delay Parameter
I S
tup_ tdn
1.80 0.07 1.19 0.03 A .. X
i-
Al
A2
A3
A4 X
AS
A6
Input Loading
A 1
Output Driving
X 36
* Minimum va~ues for the typical operating condition.

Equivalent Circuit
A1--F\
A2
A3
-tJ
X
A4-f\
AS
A6
-t!
AU-R6B-E2 I Sheet 1/1 I I Page 3-8
2-38
Cell Name Function I Number of BC
RBB
Cell Symbol
Power B-input NOR
I 6
tup tdn
2.27 0.07 1. 21 0.03 A ... X
Al -P-
A2 - r-
A3 - r-
A4 - r-t>-- X
AS - r-
A6 - r-
A7 - r-
AB -t:;>
Input Loading
A 1
Output Driving
X 36

Equivalent Circuit
Al -P-
A2 - r-
A3 - I-
A4 - b
X
AS -P-
A6 - r-
A7 - r-
AB - b
AU-R8B-E2J Sheet 1)1 I I Page 3-9
2-39
FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION 1 AU Version
R9B
Cell Symbol
Power 9-input NOR
I 8
tup tdn
1. 99 0.07 1. 35 0.03 A ... X
Al -~
A2 -r-
A3 - -
A4 - -
AS X
A6 - r-
A7 - ~
A8 - ~
A9 -0
Input Loading
A I
Output Driving
X 36
,:'(
Minimum values for the typical operating condition.
Equivalent Circuit
Al -A.
A2 -bf
~
A3
A4 -A.
-b!
r
AS X
A6
A7 -A.
A8
A9
----bf
AU-R9B-E2 I Sheet 1/1 I .1 Page 3-10
2-40
FUJITSU CMds GATE ARRAY UNIT CELL SPECIFICATION I "AU Version
RCB
Cell Symbol
I 10
tup tdn
2.19 0.07 1.40 0.03 A ... X
A1 -~
A2 -r-
A3 - r-
A4 - I-
AS - I-
-
~P--
A6
- X
A7
A8 - I-
A9 - I-
A10 - I-
All - r-
A12 -17
Input Loading
A 1
Output Driving
X 36

Equivalent Circuit
A1 - n
A2
A3 --bf
A4 - n
AS
A6
--bf l L-cP
A7 - n
A8
A9 --bf
I -< 17t---l>o- X
A10-n
All
A12--bf
AU-RCB-E2 I Sheet 1/1 I I Page 3-11
2-41
RGB
Cell Symbol
Power 16-input NOR
I 11
tup tdn
-P> 2.75 0.07 1.46 0.03 A ... X
Al
A2 - I-
A3 - I-
A4 - I-
AS - I-
A6 - I-
A7 - r-
A8
A9
-
- :=p.- X
AIO - I-
A11 - I-
Al2 - r-
Al3 - I-
A14 - I- Parameter Symbol Typ(ns)'"
Al5 - I-
Al6 -t::;>
Input Loading
Pin Name Factor (fu)
A I
Output Driving
X 36

are .e;iven .})y the maximum delay multiplier.
Equivalent Circuit
A1 -P>
A2 -
A3 - ~
A4 - b
AS -:::::,
A6 -ll
A7 - -
A8 -::;; Lc:::::'}-C>o- X
A9 -1J
AIO-r-
A11-r-
--(t::;>
Al2 -t::;>
A13 -P>
A14-
AIS- ~
A16-b
AU-RGB-E2j Sheet 1/1 I I Page 3-12
2-42
CMOS Channs/less Gats Arrays AU Series Unit Cell Ubrary
AND Family
UnH Cell Basic

2-45 N2P Power 2-input AND 2

2-43
AU Series Unit Cell UbraJy CMOS Channel/ess Gats AITBYs
2-44
N2P
Cell Symbol
I Power 2-input AND
I 2
tup tdn
0.81 0.07 0.69 0.03 0.05 7 A -+ X
Al
A2 =D- X
Input Loading
A 1
Output Driving
X 36

AU-N2P-E2 I Sheet 1/11 I Page 4-1
2-45
N3P I
Cell SYJllbol
Power 3-input AND
Proj!agation Delay Parameter
I 3
tup tdn
to iKCL to KCL KCL2 CDR2 Path
1.06 0.07 0.86 0.03 0.05 7 A->X
Al
A2
A3 =v- X
. Parameter Symbol Typ(ns)'~
Input Loading
A 1
Output Driving
X 36

2-46
Ce11 Name I Function I Number of BC
N4P
Ce11 Symbol
I Power 4-input AND Propagation Delay Parameter
I 3
tup tdn
1. 27 0.07 0.95 0.03 0.05 8 A ... X
Al
A2
A3
A4 m- X
Input Loading
Pin Name Factor (Qu)
A I
Output Driving
X 36
')': Minimum values for the typical operating condition.
2-47
. Cell Name I Function I Number of BC
N8P
Cell Symbol
Power 8-in.put AND
I 6
tup tdn
to RCL to RCL RCL2 CDR2 Path
1.38 0.11 1.16 0.03 0.05 6 A -+ X
A1 -"'"
A2 -
A3 -
A4 - -X
AS -
A6 -
A7 -
A8 -v
Input Loading
A 1
Output Driving
X 36
"" Minimum values for the typical operating condition.

are given bv the maximum delay multiplier.
Equivalent Circuit
A1 -"'"
A2 -
A3 -
A4 - . . /
X
AS -"'"
A6 -
A7 -
A8 -..-'
AU-N8P-E2 I Sheet 1/1 I I Page 4-4
2-48
OR Family
Unit Cell Basic

2-51 R2P Power 2-input OR 2

2-49
AU Series Unit Cell Ubrary CMOS Channelless Gate AITBYs
2-50
R2P
Cell Symbol
I Power 2-input OR ProFagation Delay Parameter
I 2
tup tdn
to KCL to KCL KCL2 CDRZ Path
0.63 0.07 0.91 0.04 0.06 8 A -+ X
Al
A2 =f}- X
Input Loading
A 1
Output Driving
X 36

are l1;iven by the maximum delay multiplier.
AU-R2P-E2 I Sheet 1/1 I I Page 5-1
2-51
FUJITSU CMOS GATE ARRAY VNIT CELL SPECIFICATION I AU Version
R3P
Cell Symbol
I Power 3-input OR Propagation Delay Parameter
I 3
tup tdn
0.72 0.07 1.47 0.05 0.07 8 A -+ X
=9-
Al
A2 X
A3
·Parameter Symbol Typ(ns)*
Input Loading
A 1
Output Driving
X 36

2-52
R4P
Cell Symbol
I Power 4-input OR
I 3
tup tdn
0.72 0.07 2.02 0.06 0.08 8 A .. X
~
Al
A2
X
A3
A4
Input Loading
A 1
Output Driving
X 36

2-53
R8P
Cell Symbol
Power 8-input OR
I 6
tup tdn
0.79 0 .. 07 2.15 0.07 0.08 8 A ... X
Al -P-
A2 - ~
A3 - ~
A4 - ~f-- X
AS - ~
A6 - ~
A7 - ~
A8 -0
Input Loading
Pin Name Factor (Jl.u)
A 1
Ell
Output Driving
X 36

are_given by the maximum delay multiplier.
Equivalent Circuit
Al -::::.
A2 - ,---
A3 - ;-
A4 -:7
X
AS -P-
A6 - I-
A7 - I-
A8 - 0
AU-R8P-E2 Sheet 1/1 I _. Page 5-4
2-54
EXNOR/EXOR Family
Unit Cell Basic

2-57 X1N Exclusive NOR 3

2-58 X1B Power Exclusive NOR 4
2-59 X2N Exclusive OR 3
2-60 X2B Power Exclusive OR 4
2-61 X3N 3-input Exclusive NOR 5
2-62 X3B Power 3-input Exclusive NOR 6
2-63 X4N 3-input Exclusive OR 5
2-64 X4B Power 3-input Exclusive OR 6
2-55
fJI
2-56
X1N
Cell Symbol
I Exclusive NOR
Proj:agation Delay Parameter
I 3
tup tdn
0.93 0.23 0.77 0.11 0.13 4 A .. X
A1
A2 =t{}- X
Parameter Symbol Typ(ns )",
Input Loading
Pin Name Factor (.Q.u)
A 2
Output Driving
Pin Name Factor (.Q.u)
X 18
f< Minimum values for the typical operating condition.

are ~iven by_ the maximum delay multiplier.
Equivalent Circuit
~
A1
A2
I
cV-x
AU-XlN-E2 I Sheet 1/1 I .- I Page 6-1
2-57
X1B
Cell Symbol
I Power Exclusive NOR Pro~agation Delay Parameter
I 4
tup tdn
1.19 0.07 1.42 0.04 0.07 7 A'" X
A1
A2 =+if- X
Input Loading
A 2
Output Driving
X 36

Equivalent Circuit
~
A1
A2
I
~X
AU-XlB-E2 I Sheet 1/1 I Page 6-2
2-58
X2N
Cell Symbol
I Exclusive OR
I 3
tup tdn
0.89 0.23 0.94 0.11 0.13 4 A ... X
Al
A2 =©- X
Input Loading
A 2
Output Driving
X 14
.:: Minimum values for the typical operating condition.
are given bv the maximum delay multiplier.
Equivalent Circuit
Al
A2
If I
tY- X
AU-X21\-E2 I Sheet 1/1 I Page 6-3
2-59
X2B
Cell Symbol
I Power Exclusive OR
I 4
tup tdn
1.15 0.07 1. 31 0.04 0.06 7 A ... X
A1
A2 =ID-- X
Input Loading
A 2
Output Driving
X 36

are given by the maximum delav multiplier.
Equivalent Circuit
~
Al
A2
I
~X
AU-X2B-E2 LSheet 1/1 I I Page 6-4
2-60
FUJITSU CMOS GATE ARRAY UNIT CELL SPEC IFI CATION I AU" Version
X3N
Ce11 Symbol
I 3-input Exclusive NOR
I 5
tup tdn
2.18 0.23 1.86 0.11 0.13 4 A" X
A1
A2
A3 =ID- X
Parameter Symbol Typ(ns)t'
Input Loading
A 2
Output Driving
X 18
'i, Minimum values for the typical operating condition.

Equivalent Circuit
~
A2
A3
X
Al
AU-X3N-E21 Sheet 1/ll I Page 6-5
2-61
FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION I 'AU Version
X3B
Cell Symbol
I Power 3-input Exclusive NORPropagation Delay Parameter I 6
tup tdn
2.11 0.07 2.71 0.04 0.07 7 A ... X
=t&-
A1
A2 X
A3
Input Loading
A 2
Output Driving
X 36

Equivalent Circuit
~
A2
A3
X
A1
AU-X3B-E2 I Sheet 1/1 I I Page 6-6
2-62
X4N
Cell Symbol
I 3-input Exclusive OR
I 5
tup tdn
2.26 0.23 2.03 0.11 0.13 4 A ... X
Al
A2
A3 =s- X
Parameter Symbol Typ(ns »"
Input Loading
A 2
Output Driving
X 14
...,: Minimum values for the typical operating condition .
Equivalent Circuit
~
A2
A3
X
Al
AU-X4N-E2 I Sheet 1/1 I Page 6-7
2-63
X4B
Cell Symbol
I Power 3-input Exclusive ORPropagation Delay Parameter I 6
tup tdn
1.98 0.07 2.51 0.04 0.06 7 A ... X
Al
A2
A3 =ar X
Parameter Symbol Typ(ns);'
Input Loading
Pin Name Factor (J/.u)
A 2
Output Driving
Pin Name Factor (J/.u)
X 36

Equivalent Circuit
~
A2
A3
X
Al
AU-X4B-E2 I Sheet 1/1 I Page 6-8
2-64
AND-OR-Inverter Family
Unit Cell Basic

2-67 023 2-wide 2-ANO 3-input AOI 2
2-72 044 2-wide 2-0R 2-ANO 4-input AOI 2
2-65
AU Series Unit Cel/ Ubrary CMOS Channel/ess Gate Arrays
2-66
D23
Cell Symbol
I 2-wide 2-AND 3-input AOI
I 2
tup tdn
to KCL to . KCL KCL2 LD2 Path
0.59 0.23 0.55 0.11 A -+ X
0.30 0.18 0.30 0.07 0.10 4 B -+ X
~
A1
A2
X
B
Input Loading
A 1
B 1
Output Driving
X 14

k-D23-E2 I Sh.o< 1/1 I I Page 7-1
2-67
D14
Cell Symbol
I 2-wide 3-AND 4-input AOI Prot: agation Delay Parameter I 2
tup tdn
0.72 0.23 0.56 0.15 0.17 4 A -+ X
0.26 0.16 0.29 0.07 0.10 4 B -+ X
~
Al
A2
A3
B X
Input Loading
A 1
B 1
Output Driving
X 14

AU-D14-E2 I Sheet 1/1 I I Paj(e 7-2
2-68
D24
Cell Symbol
I 2-wide 2-AND 4-input AOI
Propagation DelllY Parameter
I 2
tup tdn
0.43 0.18 0.50 0.11 A -+ X
0.54 0.18 0.67 0.11 B -+ X
>
Al
A2
X
B1
B2
Input Loading
A 1
B 1
Output Driving
X 14
* Minimumvalues for the typical operating condition.

AU-D24-E2 LSheet 1/1 I Page 7-3
2-69
D34
Cell Symbol
I 3-wide 2-AND 4-input AOI ProIagation'DelaY,Parameter I 2
tup tdn
0.92 0.33 0.59 0.12 A .. X
0.50 0.28 0.35 0.07 0.10 4 B .. X
~
A1
A2
B1 X
B2
Input Loading
A 1
B 1
Output Driving
X 10

AU-D34-E2 I Sheet 1/1 I Page 7-4
2-70
D36
Cell Symbol
I 3-wide 2-AND 6-input AOI Propagation Delay Parameter I 3
tu~ tdn
0.62 0.23 0.58 0.11 A .. X
0.79 0.23 0.70 0.11 B .. X
0.94 0.23 0.82 0.11 C .. X
Al
A2
Bl
X
B2
Cl
C2
Input Loading
A 1
B 1
C 1
Output Driving
X 10

are given by the maximum delay mu1tij>lier.
AU-D36-E2 I Sheet 1/1 I Page 7-5
2-71
D44
Cell Symbol
I 2-wide 2-0R 2-AND 4-input AO! Pro~agation Delay Parameter
I 2
tup tdn
0.83 0.33 0.63 0.11 A -+ X
0.83 0.33 0.51 0.11 B -+ X
0.79 0.23 0.39 0.07 0.09 4 C -+ X
~
Al
A2
B
C X
Input Loading
A 1
B 1
C 1
Output Driving
X 10

AU-D44-E2 I Sheet 1/1 I JPage 7-6
2-72
CMOS Channelless Gale Arrays AU Series Unit Cell Ubrary
OR-AND-Inverter Family
Unit Cell Basic

2-75 G23 2-wide 2-0R 3-input OAI 2

2-79 G44 2-wide 2-AND 2-0R 4-input OAI 2
2-73
AU Series Unit Cell Ubrary CMOS Channel/ess Gate Arrays
2-74
G23
Cell Symbol
I 2-wide 2-0R 3-input OAI ProJ:agation Delay Parameter
I 2
tup tdn
0.58 0.23 0.44 0.11 A->X
0.23 0.13 0.44 0.11 B -> X
~
Al
A2
X
B
Input Loading
A 1
B 1
Output Driving
X 18

AU-G23-E2 I Sheet 1/1 I I Page 8-1
2-75
G14
Cell Symbol
I 2-wide 3-0R 4-input OAI ProJagation Delay Parameter
I 2
tup tdn
0.96 0.34 0.52 0.11 A"'X
0.20 0.13 0.52 0.11 B ... X
~
A1
A2
A3
X
B
Input Loading
A 1
B 1
Output Driving
Pin Name Factor _tR.u)
X 10

are ltiven bv the maximum delay multiplier.
2-76
G24
Cell Svrnbol
I 2-wide 2-0R 4-input OAI
I 2
tup tdn
0.40 0.23 0.56 0.11 A ... X
0.72 0.23 0.48 0.11 B ... X
>
Al
A2
X
Bl
B2
Parameter Symbol Ty~(ns)'"
Input Loading
Pin Name Factor (.eu)
A 1
B 1
Output Driving
X 10
2-77
G34 I 3-wide 2-0R 4-input OAI

Cell SYlIIbol Pro):agation Delay Parameter
I 2
tup tdn
0.76 0.23 0.56 0.15 A" X
0.56 0.15 0.36 0.13 B .. X
~
A1
A2
B1 X
B2
Input Loading
A 1
IfJII B 1
Output Driving
X 10
i, Minimum values for the typical operating condition.

2-78
FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION j "AU Version
G44
Cell Symbol
I 2-wide 2-AND 2-0R 4-input OAI Pro~agation Delay Parameter
I 2
tup tdn
0.59 0.23 0.69 0.15 A -+ X
0.35 0.23 0.50 0.15 B -+ X
0.40 0.13 0.42 0.11 C -+ X
~
Al
A2
B
X
C
Parameter Symbol Typ(ns)":
Input Loading
Pin Name Factor (Jtu)
A 1
B 1
C 1
Output Driving
Pin Name Factor (Jtu)
X 14
1: Minimum values for the typical operating condition.

2-79
CMOS Channel/ess Gale Arrays AU Series Unit Cell Ubraty
2-80
AU Series Unit Cell Ubrery CMOS Channelless Gats AITBYs
Multiplexer Family
UnH Cell BasIc

Page Name FunctIon Cells
2-83 T24 Power 2-AND 4-wide Multiplexer 6

2-93 T54 Power 4-2-3-2 AND 4-wide Multiplexer 10
2-94 U24 Power 2-0R 4-wide Multiplexer 6
2-81
CMOS Channel/ess Gate Arrays AU Series Unit Cell Ubral)'
2-82
Cel1 Name I Function I Number of BC
T24
Cell Symbol
I Power 2-AND 4-wide Multiplexer
Prot:agation Delay Parameter
I 6
tup tdn
1.30 0.07 1. 22 0.03 A -+ X
1.44 0.07 1.41 0.03 B -+ X
1.27 0.07 1. 31 0.03 C -+ X
Al 1.38 0.07 1.51 0.03 D -+ X
A2
Bl~~
B2 r-
Cl ~r--P-X
t7
C2
D1
D2 Parameter Symbol Typ(ns)'"
Input Loading
A 1
B 1
C 1
D 1
Output Driving
X 36
>" Minimum values for the typical operating condition.

Equivalent Circuit
!:=c~
Bl = C
B2 ..........
::) X
g=ccJ
D1=C
'"'l.../
D2
AU-T24-E2 I Sheet 1/1 I I Page 9-1
2-83
FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION Version
T26 Power 2-AND 6-wide 10

Cell S Dela Parameter
tu tdn
to to KCL KCL2 CDR2 Path
Al 1.51 1.26 0.03 A'" X
A2 1.66 1.45 0.03 B ... X
1.51 1.33 0.03 C ... X
Bl 1.63 1.54 0.03 D"'X
B2 1.52 1.47 0.03 E"'X
1.65 1.67 0.03 r ... x
Cl
C2
x
D1
D2
El
E2 Parameter (ns)*
Fl
F2
Input Loading
A 1
B 1
C 1
D 1
E 1
F 1
Output Driving
x 36
* Minimum values for the typical oper&ting condition.
are the maximum dela multi lier.
Equivalent Circuit
Al
A2
B1
B2
Cl
C2
X
D1
D2
E1
E2
Fl
F2
AU-T26-E2 Pa e 9-2
2-84
T28
Ce1l Symbol
I 11
tup tdn
1. 70 0.07 1.22 0.03 A ... X
1. 86 0.07 1.44 0.03 B ... X
1. 70 0.07 1.35 0.03 C ... X
1. 83 0.07 1.57 0.03 D ... X
1. 76 0.07 1.73 0.03 E ... X
1. 89 0.07 1.67 0.03 F ... X
1. 76 0.07 1.54 0.03 G ... X
1.89 0.07 1.75 0.03 H ... X
Input Loading
A 1
B 1
C 1
D 1
E 1
F 1
G 1
H 1
Output Driving
x 36
* Minimum values for the typical operating .condition.

AU-T28-E2 I Sheet 1/2 I Page 9-3
2-85
FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION AU Version
Cell Name
T28
Equivalent Circuit
Al
A2
Bl
B2
Cl
C2
Dl
D2
x
El
E2
F1
F2
Gl
G2
HI
H2
AU-T28-E2 Pa e 9-4
2-86
FUJITSU CMOS GATR ARRAY UNIT CELL SPECIFICATION J "AU Version
T32
Cell Symbol
Pro'fagation Delay Parameter
I 5
tup tdn
to KeL to KCL KCL2 CDR2 Path
1. 22 0.07 1.35 0.03 A ... X
1.22 0.07 1.44 0.03 B ... X
A1
A2
A3
X
B1
B2
B3
Parameter Symbol Tvp(ns)1<
Input Loading
A 1
B 1
Output Driving
X 36

'The values for the worst case operating condition
Equivalent Circuit
A1
A2
A3 ..r---
J X
Bl -.....-
B2
B3
2-87
T33
Cell Symbol
I 7
tup tdn
1.40 0.07 1.33 0.03 A -> X
i.40 0.07 1.43 0.03 B -> X
1.40 0.07 1.56 0.03 C -> X
Al
A2
A3
B1
B2 X
B3
C1
C2
C3 Parameter Symbol Typ(ns)i'
Input Loading
A 1
B 1
C 1
Output Driving
X 36
i, Minimum values for the typical operating condition.

AU-T33 E2 I Sheet 1/1 I I Page 9-6
2-88
T34
Cell Symbol
I 9
tup tdn
to RCL to RCL KCL2 CDR2 Path
A1
A2
A3
=D- 1. 67
1.67
1. 75
1. 75
0.07
0.07
0.07
0.07
1.38
1.51
1.60
1. 61
0.03
0.03
0.03
0.03
A-+X
B -+ X
C -+ X
D -+ X
B1~ c::,
B2
B3
C1=iYr
C2
-::;;
=r- X
C3
D1
D2
D3
=D- Parameter Symbol Typ(ns)1'
Input Loading
A 1
B 1
C 1
D 1
Output Driving
X 36

Equivalent Circuit
A1
A2
A3
B1
B2 L-cP
r<J---(>o-
B3
X
C1
C2
C3
D1
D2
D3
2-89
T42
Cell Symbol
Power 4-AND 2-wide Multiplexer
Profagation Delay Parameter
I 6
tup tdn
1.28 0.07 1.51 0.03 A" X
1.28 0.07 1.60 0.03 B .. X
Al _r--.
A2 - I
A3 -
A4 -1../
X
Bl _f""\
B2 -
B3 - I
B4 -1../
Input Loading
A 1
B 1
Output Driving
X 36

Equivalent Circuit
Al - ,
A2
A3 --
A4 -1../
h ..J"'-
Bl
B2 -
B3 -
-1J ::J
"'l../
X
B4 -1../
AU-T42-E2 Sheet 1/1 I I Page 9-8
2-90
T43
Cell Symbol
Power 4-AND 3-wide Multiplexer
I 10
tup tdn
1.51 0.07 1.54 0.03 A -> X
Al _ r " I 1.51 0.07 1.63 0.03 B -> X
A2 - 1.51 0.07 1. 76 0.03 C -> X
t-
A3 -
A4 - L , /
BI _ r " I
B2 - Lf\ X
B3 -
B4 - L , / rb!
CI _r"I
C2 - t- Parameter Symbol Typ(ns)~'
C3 -
C4 - L , /
Input Loading
A I
B 1
C 1
Output Driving
Pin Name Factor (.I'.u)
X 36
Equivalent Circuit
Al _r"I
A2 -
A3 - p--
A4 - L , /
BI _r"I
B2 -
B3 -
:-:fl. X
B4 - L , / ~
Cl ----
C2 -
C3 - p--
C4 -,../
AU-T43-E21 Sheet 1/1 I I Page 9-9
2-91
T44
Cell Symbol
Power 4-ANO 4-wide Multiplexer
Pro a2ation Delay Parameter
1 11
tup tdn
Al -""" 1. 73 0.07 1.54 0.03 A-+X
A2 - l- I. 73 0.07 1.31 0.03 B -+ X
A3 - .1.73 0.07 1.76 0.03 C-+X
A4 -1./ 1. 73 0.07 1.86 0.03 D-+X
Bl-I""-
B2 -
B 3 - ~ po Parameter Symbol Typ(ns)*
B4 - 1 . /
r-p.-
l- X
C I - Y rD
C2 -
C3 -
C4 - 1 . /
DI-I""'I
D2 - I-
D3 -
D4-V
Input Loading
Pin Name Factor Clu)
A I
B I
C I
D I
Output Driving
Pin Name Factor (lu)
X 36 * Minimum values for the typical operating condition.
The values for the worst.case operating condition
are Riven by the maximum del~ mult:!Jl.lier.
Equivalent Circuit
Al _ r "
A2 -
A3 -
A4 -L.-
Bl _I"""
B2- h P
B3 -
B4 - v L( }----t>o- X
C1
CZ -
C3 -
1}-J r~D
C4 -
Dl _1""'1
DZ -
D3 -
D4 - v
AU-T44-E3 I Sheet 1/1 I iPage 9-10
2-92
FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION J "AU" Version
T54
Cell SYlllbol
Power 4-2-3-2 AND 4-wide Multiplexer
Pro~agation Delav Parameter
I 10
tUl) tdn
1.65 0.07 1.57 0.03 A ... X
Al _I"'- 1.54 0.07 1.31 0.03 B ... X
A2 - I- 1.65 o.in 1.65 0.03 C ... X
A3 - 1.54 0.07 1.51 0.03 D ... X
A4 - 1 /
B1~
B2
P.
~
C 1 = i f rb
X
C2
C3
D1
D2
==D- Parameter SYlllbol Typ(ns)*
Input Loading
A 1
B 1
C 1
D 1
Output Driving
X 36
Equivalent Circuit
Al
A2 -
-L
A3 -
A4 - 1 /
f
B1 -<~
~t---f»-
B2
X
Cl -<
C2
C3
D1
D2
AU-T54 E3 I Sheet 1/1 I t Palte 9-11
2-93
U24
Cell Symbol
I Power 2-0R 4-wide Multiplexer
I 6
tup tdn
. to RCL to RCL RCL2 CDR2 Path
1.60 0.07 1.44 0.04 0.07 7 A -> X
1.15 0.07 1.40 0.04 0.07 7 B -> X
1.52 0.07 1.43 0.04 0.07 7 C -> X
Al 1.11 0.07 1. 36 0.04 0.07 7 D->X
A2
BI
B2 ~~
C1
C2
=Yl---I>- X
D1
D2 Parameter Symbol Typ(ns)~'
Input Loading
A 1
B 1
C 1
D 1
Output Driving
X 36

AU-U24-E2 I Sheet 1/1 I I Page 9-12
2-94
U26
Cell Symbol
ProIagation Delay Parameter
I 9
tup tdn
Al
A2
=t}- 1.60
1.24
0.07
0.07
1.87
1.81
0.04
0.04
0.07
0.07
7
7
A'" X
B ... X
1.63 0.07 1.92 0.04 0.07 7 C .. X
B1 1.27 0.07 1.92 0.04 0.07 7 D'" X
B2 1.31 0.07 2.07 0.04 0.07 7 E ... X
....., 1.68 0.07 2.07 0.04 0.07 7 F .. X
C1~
C2
::r-- X
D1~
D2
./
E1
E2 Parameter Symbol Typ(ns)1'
F1
F2
=t}-
Input Loading
A 1
B
C
D
1
1
1
If)
E 1
F 1
Output Driving
X 36

AU-U26-E2 I Sheet 1/1 I Pa.e;e 9-13
2-95
U28
Cell Symbol
I Power 2-0R 8-wide Multiplexer Pro~agation Delay Parameter
I 11
tup tdn
Al~ 1.69 0.07 2.55 0.05 0.08 7 A ... X
A2 - - b ' - 1.24 0.07 2.51 0.05 0.08 7 B ... X
1.21 0.07 2.25 0.05 0.08 7 C"'X
Bl~ 1.66 0.07 2.29 0.05 0.08 7 D ... X
B2 --b' . 1.69 0.07 2.51 0.05 0.08 7 E ... X
1.24 0.07 2.47 0.05 0.08 7 F"'X
C1~ -.., 0.07 2.03 0.05 0.08 7

1.17 G ... X
C2 1.63 0.07 2.11 0.05 0.08 7 H ... X
~~ =t}-E
D--- X
~~~~
Fl l../
F2
G1~
G2 --b'-
H1~
H2 --b'-----
Input Loading
A 1
B 1
C 1
D 1
E 1
F 1
G 1
H 1
Output Driving
x 36

are given by the maximum delay mult~lier.
2-96
U32
Cell Symbol
I 5
tup tdn
1.72 0.07 1.33 0.04 0.07 7 A~ X
1.69 0.07 1. 31 0.04 0.07 7 B~ X
>x
Al
A2
A3
Bl
B2
B3
Parameter S~bol "fy~(ns)*
Input Loading
A 1
B 1
Output Driving
X 36
...': Minimum values for the typical operating condition .
are_given by the maximum delay multiplier.
2-97
U33
Cell Symbol
Pro.agation Delay Parameter
I 7
tup tdn
1.83 0.07 1.83 0.04 0.09 7 A .. X
1.80 0.07 1.91 0.04 0.09 7 B .. X
1.85 0.07 2.02 0.04 0.08 7 C .. X
Al ---Fl
A2
A3
--1:)
Bl
B2
--n
---bI X
B3
Cl
C2
---n
---bI
C3 Parameter Symbol Typ(ns)'"
Input Loading
A 1
B 1
C 1
Output Driving
X 36
AU-U33-E2 I Sheet 1/1 I Page 9-16
2-98
U34
Cell Symbol
I 9
tup tdn
1.69 0.07 2.39 0.05 0.08 7 A -+ X
1.71 0.07 2.40 0.05 0.08 7 B -+ X
Al --Fl 1.54 0.07 1.95 0.05 0.08 7 C -+ X
A2
A3
-b' 1.69 0.07 2.15 0.05 0.08 7 D -+ X
Bl=sJ
B2
B3
~
=91
Cl
C2
C3
L/
P- X

Dl--Fl
D2
D3
-----bI
Input Loading
A 1
B 1
C 1
D 1
Output Driving
X 36

are given by the .maximum delay multiplier.
2-99
U42
Cell Symbol
ProI=agation Delay Parameter
I 6
tup tdn
2.08 0.07 1.37 0.04 0.07 7 A'" X
2.03 0.07 1.31 0.04 0.07 7 B ... X
AI-:=::'
A2 - -
A3 - - Parameter Symbol Typ(ns)'~
A4 -::;;;
X
B1 -:=::.
B2 - -
B3 - -
B4 -::;;;
Input Loading
A 1
B 1
Output Driving
Pin Name Factor eRu)
ilre given by the maximum delay multiplier.
2-100
Cell Name I Function -' Number of BC
U43
Cell Symbol
I 9
tup tdn
2.06 0.07 1.71 0.05 0.07 7 A ... X
2.10 0.07 1.81 0.05 0.07 7 B ... X
A1 -P> 2.16 0.07 1.91 0.05 0.07 7 C ... X
A2 - f-I-
A3 - f-
A4-b
"-}D-
B2 - f -
B3 - f -
B4 -I::;;>
X
C1 -P>
C2 - f-f--
C3 - f-
C4 -I::;;>
Input Loading
A 1
B 1
C 1
Output Driving
2-101
Cell Name IFunction I Number of BC
U44
Cell Symbol
Pro):agation Delay Parameter
I 11
tup tdn
A1-P
A2 -rt
A3 - I -
A4 -17
2.19
2.18
2.11
2.14
0.07
0.07
0.07
0.07
2.40
2.31
1.95
2.15
0.04
0.04
0.04
0.04
0.09
0.09
0.09
0.09
7
7
7
7
A .. X
B .. X
C .. X
D .. X
B1 - Pj
B2 - I -
B3-~ ....... Parameter Symbol Typ(ns)*
B4 -17
p-- X
C1-~
C2 - I - ../
C3 - I -
C4 -17
D3
D4
-1-
Dl - P
D2 -I-
-17
Input Loading
A 1
B 1
C 1
D 1
Output Driving
Pin Name FactorJR.u)
X 36 1, Minimum values for the typical operating condition.
are given by the maximum delay multiplier .
AU-U44-E2 I Sheet 1/1 I . 1 Page 9-20
2-102
CMOS Channe/less Gate Arrays AU Series Unit Cell Ubrary
Clock Buffer Family
Unit Cell Basic

2-105 K1B True Clock Buffer 2

2-106 K2B Power Clock Buffer 3
2-107 K3B Gated Clock (AND) Buffer 2
2-108 K4B Gated Clock (OR) Buffer 2
2-109 K5B Gated Clock (NAND) Buffer 3
2-110 KAB Block Clock (OR) Buffer 3
2-111 KBB Block Clock (OR x 10) Buffer 30
2-113 KDB Block Clock (OR x 10) Buffer 32
2-115 KEB Block Clock Buffer 23
2-103
AU Series Unit Cell Ubrary CMOS CharmelJess Gate Armys
2-104
K1B
Cell Symbol
I True Clock Buffer
I 2
tup tdn
0.58 0.07 0.69 0.03 A ... X
A
-i>- X
Input Loading
A 1
Output Driving
X 36
Equivalent Circuit
A~ X
AU-K1B-E2 I Sheet 1/1 I I Page 10-1
2-105
K211
Cell Symbol
I Power Clock Buffer Propagation Delay Parameter
I 3
tllp tdn
0.85 0.03 0.96 0.03 A-+X
A -{>- X
Input Loading
A 1
Output Driving
X 55
Equivalent Circuit
A -{>o--+- X
2-106
K3B
Cell Symbol
I Gated Clock (AND) Buffer
I 2
tup tdn
0.80 0.07 0.80 0.03 A .. X
Al
A2 =D- X
Input Loading
A 1
Output Driving
X 36

are J:iven by the maximum delay multiplier.
Equivalent Circuit
Al
A2 ==D>--V- X
AU-K3B-E2 J Sheet 1/1 I I Page 10-3
2-107
K4B
Ce1l Symbol
I Gated Clock JOR} Buffer Pro.agation Delay Parameter
I 2
tup tdn
0.63 0.07 0.91 0.04 0.06 8 A-+X
Al
A2 ={J- X
Parameter Symbol Tvp(ns)'~
Input LO;lding
A 1
Output Driving
X 36
'i: Minimum values for the typical operating condition.
are R;iven by the maximum delay multiplier.
Equivalent Circuit
Al
A2 =t>---4>--- X
AU-K4B-E2 I Sheet 1/11 I PaR;e 10-4
2-108
K5B
Cell Symbol
I Gated Clock (NAND) Buffer
ProJagation Delay Parameter
I 3
tup tdn
0.91 0.07 1.19 0.03 A-+X
Al
A2 =I>- X
Input Loading
A 1
Output Driving
X 36

Equivalent Circuit
~
Al
X
A2
2-109
FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION J "AU Version
KAB
Cell Symbol
I Block Clock (OR) Buffer Pro~agation Delay Parameter
I :3
tup tdn
0.87 0.03 1.48 0.03 A .. X
~
Al
A2 X
Input Loading
A 1
Output Driving
X 55
* Minimumvalues for the typical operating condition.

Equivalent Circuit
~
Al
A2 X
AU-KAB-E2 I Sheet 1/1 I I Page 10-6
2-110
KBB
Cell Symbol
I Block Clock Buffer (OR x ProJ:agation
10)
Delay Parameter
I 30
tup tdn
1.07 0.03 1.67 0.03 CK .. X
0.87 0.03 1.48 0.03 IH .. X
CK -
IHO - r - XO
IHI - r - Xl
IH2 - - X2
IH3 - - X3
IH4 - - X4
IHS - - XS
IH6 - - X6
IH7 - - X7
IH8 - - X8 Parameter Symbol Typ(ns)'·'
IH9 - - X9
Input Loading
Pin Name Factor (~u)
CK 10
IH 1
Output Driving
X 55

AU-KBB-E2 I Sheet 1/2 I j-Page 10-7
2-111
Cell Name
KBB
Equivalent Circuit
CK
IHO XO
~------------------~
IHl Xl
f------------------i
X2
IH2
~------------------~
IH3 X3
f------------------i
IH4 X4
~------------------~
X5
IH5
f------------------~
X6
IH6
~------------------~
IH7 X7
f------------------~
X8
IH8
~------------------~
X9
IH9
AU-KBB-E2 Pa e 10-8
2-112
KDB
Cell Symbol
I Block Clock Buffer (OR x 10) Pro~agation Delay Parameter
I 32
tup tdn
1.90 0.04 2.80 0.02 CK ... X
0.90 0.04 1.85 0.02 IH ... X
CK -
IHO - - XO
1H1 - - Xl
1H2 - - X2
IH3 - - X3
1H4 - - X4
IH5 - - X5
IH6 - - X6
IH7 - - X7
IH8 - - X8 Parameter Symbol Typ(ns)*
IH9 - - X9
Input Loading
CK 1
IH 1
Output Driving
X 55

are _given by the maximum delay multiplier.
AU-KDB-E2 I Sheet 1/2 I I Page 10-9
2-113
Cell Name
KDB
Equivalent Circuit
CK
IHO------------~--~~~ ,,, XO
, I
; ___________________ J
,,
,
IH1--------------+-~~,--~r
Xl
,, .,
,,~---------_---------1
,
IH2----------~r_~~" ,,, X2
, ,
~-_-------_---------1
X3
IH3------------~--~~~-
,
,~-------------------~, ,,
,
IH4------------~--~~~-
X4
,L___________________ , ~
,
I
X5
IH5----------~--~~,r
___________________ 1
,
,,
I
X6
IH6------------+--+--~ ,,
l ___________________ 1
,, ,,
, ,,
IH7--------------t-~,---+~
X7
,,L ___________________ , ~
, ,,
,,
, XB
IHB------------~--~~~
, ,,,
~-------------------~
,I
X9
IH9--------------~,--~r
,,
t ___________________ ~
AU-KDB-E2 Pa e 10-10
2-114
KEB
Cell Symbol
I Block Clock Buffer ProJ;agation Delay Parameter
I 23
tup tdn
1.25 0.04 1.38 0.02 0.04 18 CK -+ X
CK - - XO
- Xl
- X2
- X3
- X4
r-- X5
r-- X6
r-- X7
r-- X8 Parameter Symbol 'ryp(ns) *
r-- X9
Input Loading
CK 6
OUtput Driving
X 55

Note: The KEB is an eqUivalent of the KDB and the KBB, and it must be treated
in the same manner as the KBB and the KDB in the logic circuit design.
AU-KEB-E2 I Sheet 1/2 I I PaSte 10-11
2-115
Cell Name
KEB
Equivalent Circuit
CK XO
Xl
X2
X3
X4
X5
X6
X7
X8
X9
Pa e 10-12
2-116
CMOS Channelless Gate Arrays AU Series Unit Cell Ubrary
Scan Flip-flop (Positive Edge Type) Family
Un" Cell Basic

2-119 SOH Scan 2-input 0 Flip-flop with Clear and Clock InhibH 14
2-122 SOJ Scan 4-input 0 Flip-flop wHh Clear and Clock Inhibit 15
2-125 SDK Scan 6-input 0 Flip-flop wHh Clear and Clock Inhibit 16
2-128 SJH Scan J-K Flip-flop wHh Clear and Clock Inhibit 16
2-131 SOD Scan 2-lnput 0 Flip-flop with Clear, Preset, and
Clock Inhibit 16
2-135 SOA Scan 1-input 0 Flip-flop with Clock Inhibit 12
2-138 SOB Scan 1-input 4-bit 0 Flip-flop with Clock Inhibit 42
2-142 SHA Scan 1-input 8-bit 0 Flip-flop with Clock Inhibit 68
2-145 SHB Scan 1-input 8-bit 0 Flip-flop with Clock Inhibit
and QOutput 62
2-148 SHC Scan 1-input 8-bit 0 Flip-flop with Clock Inhibit
and XQ Output 62
2-151 SHJ Scan 8-bH 0 Flip-flop with Clock Inhibit and 2-t0-1
Data Multiplexer 78
2-154 SHK Scan 8-bit 0 Flip-flop with Clock Inhibit and 3-t0-1
Data Multiplexer 88
2-157 SFOM Scan 1-input 0 Flip-flop with Clock Inhibit 10
2-160 SFOO Scan 1-input 0 Flip-flop with Clear and Clock Inhibit 11
2-163 SFOP Scan 1-input 0 Flip-flop with Clear, Preset,
and Clock Inhibit 12
2-167 SFOR Scan 4-input 0 Flip-flop with Clear and Clock Inhibit 36
2-171 SFOS Scan 4-input 0 Flip-flop wHh Clock Inhibit 31
2-175 SFJD Scan J-K Flip-flop with Clock Inhibit 14
2-117
2-118
SDH
Cell Symbol
I SCAN 2-input DFF with Clear & Clock-Inhibit
Delay Parameter
Pro~agation
I 14
tup tdn
2.98 0.07 2.39 0.03 0.07 7 CK, IH -+ Q
1.88 0.07 1. 72 0.05 0.10 7 CK,IH -+ XQ
3.03 0.07 0.86 0.03 0.07 7 CL .. Q,
- XQ
Al - Q
A2 - -
CK -
IH -
SI -
A-
B-( D- XQ
Parameter Symbol Typ(ns»~
Clock Pulse Width tCW 4.4
Clock Pause Time tCWH 4.0
CL
Data Setup Time tSD 3.0
Data Hold Time tHD 0.8
Clear Pulse Width tLW 4.0

Clear Release Time tREM 2.4
Input Loading Clear Hold Time tINH 1.2
A1,A2 1
CK 1
IH 1
CL 3
SI 1
A,B 2
Output Driving
Q 36 'k Minimum values for the typical operating condition.
XQ 36 The values for the worst case operating condition
Function Table
MODE INPUT OUTPUT
CLK CL D A B SI Q XQ
CLEAR X L X X X X L H
CLOCK L..H H Di L L X Di Di
H H X L L X Qo XQo
SCAN H H X L-+H"L H Si Qo XQo
H H X L H-+L-+H X Si Si
Note : CLK = CK + IH
D = Al x A2
AU-SDH-E3 J Sheet 1/3 I Page 11-1
2-119
Cell Name
SDH
Equivalent Circuit
CLK XBCK XCLK

-L -L -L
Al
A2 Q
CL
XCLK ACK CLK

-L -L -L
II
CLK XACK
XACK
-L
SI I
XBCK
I XQ
ACK
..
A o---~~----- ACK
:= XCLK
~XACK
... XBCK
B o>-~~-----
~BCK
AU-SDH-E3 Pa e 11-2
2-120
FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION 1 "AU Version
Cell Name J
SDH J
Definitions of Parameters
i) Clock Mode
I--tCWH ---,J
-tcw-
Clock ---...
Data -tSD ~tHD""
-tpd - - 0
Q, XQ
(Output)
ii) Clear Mode
CK tREM ...
Clear I--tLW-
~
-tpd ....
Q, XQ
(Output)
-
tINH
CL
AU-SDH-E3 I Sheet 3/3 I I Page 11-3
2-121
SDJ
Ce11 Symbol
I SCAN 4-input DFF with ClearPropagation
& Clock-Inhibit
Delay Parameter
I 15
tup tdn
2.20 0.07 2.42 0.03 0.07 7 CK,IH ... Q
1. 89 0.07 1.71 0.05 0.10 7 CK,IH ... XQ
;--- 2.99 0.07 0.85 0.03 0.07 7 CL ... Q,
Al - f- Q XQ
A2 -
BI -
B2 -
CK -
IH -
SI -
A-
B-< P- XQ Parameter Symbol Tvp(ns)*
CL

AI,A2 I
Bl,B2 1
CK I
IH 1
CL 3
SI I
A,B 2
Output Driving
Pin Name Factor (Roul
Q 36 1, Minimum values for the typical operating condition.
Function Table
MODE INPUT OUTPUT
CLEAR X L X X X X i:. H
CLOCK L...H H Di L L X Di Di
H H X L L X Q. XQ.
SCAN H H X L..H->L H Si Q. XQo
H H X L H"L->H X Si Si
D = (AI x A2) + (Bl x B2)
AU-SDJ-E3J Sheet 1/3 I I Page 11-4
2-122
Cell Name
SDJ
Equivalent Circuit
Al
A2
BI
B2
Q
CL
XCLK ACK CLK

-.L -.L -.L
IT
CLK XACK
XACK
-.L
51 I
XBCK
I XQ
ACK
CK~
IH
~ : eLK
XCLK
AO
c;== XACK
B0
c;=n~
BCK
Pa e 11-5
2-123
Cell Name I
SDJ I
i) Clock Mode
~tCWH ---I
Clock ---.... I<-- tcw ----0
Data ..... tSD I<- tHO ....
I<-tpd ---.
Q. XQ
(Output)
ii) Clear Mode
CK tREM ....
Clear
---- -tLW--
I<- tpd'"
Q. XQ
(Output)
tINH
CL
AU-SDJ-E3 I Sheet 3/3 I I Page 11-6
2-124
SDK
Cell Symbol
I SCAN 6-input DFF with ClearProJ:agation
& Clock-Inhibit
Delay Parameter
I 16
tup tdn
to KCL to KCL KCL2. CDR2. Path
2..96 0.07 2.40 0.03 0.07 7 CK,IH .. Q
- 1.86 0.07 1. 73 0.05 0.10 7 CK, IH .. XQ
Al - f- 2.99 0.07 0.82. 0.03 0.07 7 CL .. Q,
A2. - Q XQ
B1 -
B2. -
Cl -
C2. -
CK -
IH -
SI - Typ(ns»',
A- Parameter Symbol
B -< P-- XQ Clock Pulse Width tCW 4.4

CL Data Hold Time tHD 0.4

Clear Release Time tREM 2..4
AI,A2. 1
Bl,B2. 1
Cl,C2. 1
CK 1
IH 1
CL 3
SI 1
A,B 2.
Output Driving
Q 36 ..': Minimum values for the typical operating condition.
Function Table
MODE INPUT OUTPUT
CLEAR X L X X X X' .L H
CLOCK L..H H Di L L X Di Di
H H X L L X Qo XQo
SCAN H H X L"H-+L H Si Qo XQo
H H X L H-+L-+H X Si Si
D = (AI x A2.) + (Bl x B2.) + (Cl x C2.)
AU-SDK-E3 I Sheet 1/3 I I Page 11-7
2-125
Cell Name
SDK
Equivalent Circuit
Al
A2
Bl
B2
Cl
C2
Q
CL
XCLK ACK CLK

--L --L --L
II
CLK XACK
XACK
--L
fII SI I
XBCK
I XQ
ACK
. . ACK
A O>--..,.~-----
~XACK
B o-,..~----- XBCK
~BCK
AU-SDK-E3 Pa e 11-8
2-126
Cell Name I
SDK I
i) Clock Mode
-tCWH--
Clock
- o-tcw ---I
Data ~tSD <- tHD ....
Io-tpd - - !
Q. XQ
(Output)
ii) Clear Mode
CK i"tREM ...
Clear
-----... I<--tLW-
I<- tpd ....
Q. XQ
(Output)
tINH
CL
AU-SDK-E3 I Sheet 3/31 I Pa.e:e 11-9
2-127
Cell Name I Function .1 Number of BC
SJH
Cell Symbol
I SCAN J-K FF with Clear & Clock-Inhibit
Pro}:agation Delay Parameter
I 16
tup tdn
3.39 0.07 2.70 0.03 0.07 7 CK,IH'" Q
1.89 0.07 1. 73 0.05 0.10 7 CK,IH -+ XQ
3.01 0.07 1.11 0.03 0.07 7 CL -+ Q,
- XQ
J - r- Q
K-<
CK-
IH- tCWH
SI- Clock Pause Time 4.0
A-
B -< P- XQ Data Setup Time (J) tSD 3.6
Data Setup Time (K) tSD 3.9
Data Hold Time (J K) tHO 0.4
CL
Clear Hold Time tINH 1.2
Input Loading
J,K 1
CK 1
IH 1
CL 3
SI 1
A,B 2
Output Driving
Q 36 * Minimum values for the typical operating condition.
Function Table
INPUT OUTPUT
MODE
CLK CL J K A B SI Q XQ
CLEAR X L X X X X X L H
L-+H H L L L L X L H
L-+H H H H L L X H L
CLOCK L-+H H L H L L X Qo XQo
L..H H H L L L X XQo Qo
H H X X L L X Qo XQo
SCAN H H X X L-+H-+L H Si Qo XQo
H H X X L H-+L-+H X Si Si
AU-SJH-E3 I Sheet 1/3 I 1Page 11-10
2-128
Cell Name
SJH
Equivalent Circuit
Q
K
CLo-----+
XACK
-L
SI T
XBCK
XQ
T
ACK
A o-....~----- ACK
L-f>o-- XACK
B o-....~---~- XBCK
L-f>o-- BCK
Pa e 11-11
2-129
Cell Name I
SJH I
i) Clock Mode
~tCWH-
<--tcw-
Clock ----.
Data <-tSD <- tHD'"
<--tpd ---0
Q. XQ
(Output)
ii) Clear Mode
CK tREM ...
Clear -tLW-
~
~ tpd'"
Q. XQ
(Output)
tINH
CL
AU-SJH-E3 I Sheet 3/3 I I Page 11-12
2-130
Cell Name I Function Number of BC
SDD
Cell Symbol
I SCAN 2-input DFF with Clear Preset & Clock-Inhibit
Delay Parameter
Pro~aJtation
16
tup tdn
PR 2.96 0.07 2.58 0.03 0.07 7 CK,IH -. Q
2.12 0.07 1.71 0.05 0.10 7 CK,IH -. XQ
3.60 0.07 0.82 0.03 0.07 7 CL -. Q,
Al - XQ
r- Q 3.07 0.07 1.88 0.05 0.10 7 PR -+ Q,
A2 -
XQ
CK -
IH -
SI - Parameter Symbol _T~{nsl*
A- Clock Pulse Width tCW 4.4
B-< P- XQ Clock Pause Time tCWH 4.0
Al,A2 1 Preset Pulse Width tPW 5.5
CK 1 Preset Release Time tREM 3.0
IH 1 Preset Hold Time tINH 0.8
CL 3
PR 3
SI 1
A,B 2
Output Driving
Function Table
MODE INPUT OUTPUT
CLK CL PR D A B SI Q XQ
CLEAR X L H X X X X L H
PRESET X H L X X X X H L
CLOCK L-+H H H Di L L X Di Di
H H H X L L X Q. XQ.
SCAN H H H X L-.H-+L H Si Q. XQ.
H H H X L H-.L-+H X Si Si
CL/PR X L L X X X X Prohibited
D = Al x A2
AU-SDD-E4 I Sheet 1/4 I I Page 11-13
2-131
Cell Name
SDD
Equivalent Circuit
Al
A2
CL Q
II
CLK XACK
XACK
-L
SI I
XBCK
I XQ
L--_ _ _..., ACK
PR
o>--"-r--.
----
:= XCLK
A
L-f>o---
ACK
XACK
B o-""r------ XBCK
L-f>o--- BCK
Pa e 11-14
2-132
Cell Name I
SDn I
i) Clock Mode
i--tcwx
-
---0
-tcw-
Clock
Data ~tSD' I-- tHD"

x=:
i-tpd --0
Q. XQ
(Output)
ii) Clear Mode
CK tREM"
Clear
- Io--tLW-
~tpd"
Q. XQ
(Output)
tINH
Clear
AU-SDD-E4 I Sheet 3/4 I PHe 11-15
2-133
FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION i AU Version
Cell Name I
.SDD I
iii) Preset Mode
~REM" ~ _ _ _ _ _ _ _ _ __
CK
Preset
Q, XQ
(Output)
tINH
Preset
AU-SDD-E4 I Sheet 4/4 I I Pqe 11-16
2-134
SDA
Cell Symbol
I SCAN I-input DFF with Clock-Inhibit
Pro]:agation Delay Parameter
I 12
tup tdn
2.55 0.07 2.40 0.03 0.07 7 CK,IH ... Q
1.87 0.07 1. 74 0.05 0.10 7 CK,IH ... XQ
.--
D - I-Q
CK -
IH -
SI -
A -
B -C ~XQ Parameter Symbol Typ(ns)'~
'--- Clock Pulse Width tCW 4.4

Input Loading
D 1
CK 1
IH 1
SI 1
A,B 2
Output Driving
Function Table
MODE INPUT OUTPUT

CLK D A B SI Q XQ
CLOCK L...H Di L L X Di Di
H X L L X Qo XQo
SCAN H X L"'H...L H Si Qo XQo
H X L H...L->H X Si Si
Note : CLK '" CK + IH
AU-SDA-E3 I Sheet l/3 I I Page 11-17
2-135
FUJITSU CMOS GATE ARRAY "UNIT CELL SPECIFICATION AU Version
Cell Name
SDA
Equivalent Circuit
CLK XBCK XCLK
-.L -.L -.L
D Q
I
XCLK
I I
BCK CLK
XCLK ACK CLK
-.L -.L -.L
II
CLl{ XACK
XACK
-.L
SI I
XBCK
I XQ
ACK
V2B
AO----.,..~----- ACK
~XACK
--
B O----.,..~---. XBCK
~BCK
AU-SDA-E3 Pa e 11-18
2-136
Ce11 Name I
SDA I
i) Clock Mode
..... ,It-- tcw

___ - - _ - tCWH ----0
Clock
Data ~tSD <-tHD'"

--------,I/----+---~I';-----·r_------------~
-tpd --0
Q. XQ ;-~------------------
(Output)
AU-SDA-E3 I Sheet 3/3 I I Page 11-19
2-137
...
FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION J AU Version
SDB
Cell Symbol
J SCAN I-input 4-bit DFF withPropagation
Clock-Inhibit
Delav Parameter
I 42
tUJ) tdn
3.39 0.07 3.15 0.03 0.07 7 CK,IH -+ Q
2.60 0.07 2.66 0.05 0.10 7 CK,IH -+ XQ
D1-
- f- Q1
D2- P- XQ1
D3 - ~ Q2
D4- P- XQ2
f - Q3
CK-
IH- P- XQ3
SI -
- Q4 Parameter Symbol Typ(ns)*
:>- XQ4 Clock Pulse Width tCW 5.5
A -
B --< Clock Pause Time tCWH 4.0
- Data Setup Time tSD 1.8
Input Loading
D 1
CK 1
IH 1
SI 1
A,B 2
Output Driving
Function Table
MODE INPUT OUTPUT

CLK Dn A B SI,Qn-1 Qn XQn
CLOCK L-+H Di L L X Di DI
H X L L X Qno XQno
SCAN H X L-+H-+L H Si Qno XQno
H X L H-+L-+H X Si Si
Note : CLK=CK+IH
n = 1 4N
AU-SDB-E4 I Sheet 1/4 I I Page 11-20
2-138
Cell Name
SDB
Equivalent Circuit
D1 D2 D3 D4
XQl Ql XQ2 Q2 XQ3 Q3 XQ4 Q4
D XQ f>- D XQ f>- D XQ :>- D XQ b-

sIo-____________ ~S
QI--
CK 0-- CK CLK I---t-ICLK _CLK _CLK ,.----CLK

IH 0-- IH XCLK XCLK ; - - XCLK ;----XCLK _XCLK
ACK ACK .-- ACK _ACK .--ACK
A 0-- A XACK XACK __ XACK _XACK ,--XACK
BCK BCK ,- BCK r- BCK _BCK
B 0-< i XBCK XBCK XBCK XBCK XBCK
FFO
Equivalent Circuit (FFO)
CK
IH X>----CLK
XCLK
A OI-----M~ ACI B O---,....i~ DOK
4>0--------.. XACK 4>0-----.. BCK
Pa e 11-21
2-139
Cell Name
SDB
Equivalent Circuit (FFl)

CLK XBCK XCLK
-L -L -.L
D Q
XCLK
CLK XACK t-----oQa
T
ACK
T
XBCK
XQ
V2B
AU-SDB-E4 Pa e 11-22
2-140
FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION i AU Version
Cell Name 1
SDB 1
i) Clock Mode
I<-- tcw - - - - tCWl{ -

Clock ~
Data ~ tSD -I-- tHD ...
-------J,~~~-JI~~-----------JC::
Io--tpd - 0
Q, XQ 1,--+------------------
(Output)
AU-SDB-E4 1 Sheet 4/4 1 iPqe 11-23
2-141
FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION l"AU" Version
SHA
Cell Symbol
I SCAN I-input 8-bit DFF withPrOFagation
Clock-Inhibit
Delay Parameter
I 68
tup tdn
to KCL 100 KCL KCL2 CDR2 Path
,-- 3.78 0.13 3.78 0.07 0.08 4 CK,IH -+ Q
D1- r-- Q1 3.30 0.13 3.20 0.11 0.15 4 CK,IH -+ XQ
D2 - p- XQ1
D3 - r-- Q2
D4 - P-- XQ2
D5 - r-- Q3
D6 - P-- XQ3
D7 - r-- Q4
D8 - P-- XQ4
r-- Q5
p- XQ5
r-- Q6
CK- P-- XQ6 Parameter Symbol Typ(ns)~'
IH - r-- Q7 Clock Pulse Width tCW 5.8
SI - P-- XQ7 Clock Pause Time tCWH 4.4
A - I--- Q8
B --C p- XQ8 Data Setup Time tSD 1.5
'-- Data Hold Time tHD 2.7
Input Loading
D I
CK 1
IH 1
SI 1
A 1
B 1
Output Driving
Q 18
XQ 18 * Minimum values for the typical operating condition.
AU-SHA-E2 Sheet 1/3 I I Page 11 24
2-142
Cell Name
SHA
Equivalent Circuit
Dl D2 DB
CK
IH CKI
XCKI FF. FF. FF.

CKI CKI
XCKI XCKI
AI AI ~
: XAI XAI XAI
BI BI
AI XBI XBI
XSI. XSO. XSI. XSO. XSI.
X X X
:::1
SI Ql Q2 Q8
XQl XQ2 XQ8
Equivalent
D.
,-----OXSO.
)O----oQ.
XAI II
--L CKI XAI
XSI. 0 - - - - 1
I BI
I XCKI --L
AI
T
XBI
Pa e 11-25
2-143
Ce11 Name I
SHA I
i) Cloc.k Mode
_ io-- tC\tl --0/0-- tC\tIH ----

Clock
Data !'- tSD .... tHD ..
-------JI'-__+-__ I~--r-----------JC::
Q. XQ
(Output)
AU-SHA-E2 I Sheet 3/3 I I Page 11-26
2-144
SHB
Cell Symbol
I SCAN I-input 8-bit DFF with Clock-Inhibit & Output I
Delay Parameter
Pro~agation
Q 62
tup tdn
3.46 0.13 3.54 0.07 0.08 4 CK,IH -+ Q
-
Dl- ~ Q1
D2 - ~ Q2
D3 - ~ Q3
D4 - ~ Q4
D5 - I--- Q5
D6 - ~ Q6
D7 - ~ Q7
D8 - ~ Q8
CK -
IH -
SI - Parameter Symbol Typ(ns)'"
A - Clock Pause Time tCWH 4.4
B --<
-
Dllta Setup Time tSD 1.6
Input Loading
D 1
CK 1
IH 1
SI 1
A 1
B 1
Output Driving
Q 18
AU-SHB-E2 I Sheet 1/3 I I Page 11 27
2-145
Cell Name
SHB
Equivalent Circuit
01 02 08
CK
IH CKI
XCKI FFo FFo FFo

CKI CKI
= CKI
A~C;O
XCKI XCKI XCKI
AI AI ~ AI
: XAI XAI XAI XAI
BI BI BI
AI XBI XBI XBI
XSlo XSOo XSlo XSOo XSIo
B~C;O Q
:::1
SI Q1 Q2 Q8
D
Equivalent Circuit (FFo)
CKI XBI XCKI
~ ~ ~
Do
XSO o
Qo
XAI I I
CKI XAI
~
XSlo
I
AI
I
XBI
AU-SHB-E2 Pa e 11-28
2-146
Cell Name I
SHB I
i) Clock Mode
~ tcw - - - - tCWH -
Clock ~
Data ~tSD ... tHD ....
I<--tpd ---I
Q. XQ r-~------------------
(Output)
AU-SHB-E2 I Sheet 3/3 I I Pa.ll:e 11-29
2-147
FUJITSU CMOS GATE ARRAY UNIT. CELL SPECIFICATION J "AU" Version
SHC Clock-Inhibit & XQ Output I
I SCAN I-input 8-bit DFF withProj:agation 62
Cell Sy_mbol Delay Parameter
tup tdn
3.35 0.13 3.28 0.11 0.15 4 CK,IH" XQ
r---
Dl - P-- XQI
D2 - P-- XQ2
D3 - b-- XQ3
D4 - P--XQ4
D5 - b--XQ5
D6 - D--XQ6
D7 - P--XQ7
DB - D--XQB
CK:-
IH-
SI - Parameter Symbol Typ(ns)*
Clock Pulse Width tCW 5.B
B ---c
'---
Input Loading
D I
CK 1
IH 1
SI I
A 1
B 1
Output Driving
XQ IB
AU-SHC-E2 I Sheet 1/3 I I Page 11-30
2-148
Cell Name
SHC
Equivalent Circuit
D1 DB
CK
IH )()-----. CKI
XSIo XSOo XSIo XSOo XSIo

X X X
SI
L----oXQ1 L----oXQ2 L----oXQB
Equivalent
Do
~---{)XSOo
XAI II CKI
-.L CKI XAI -.L
XS10 o - - - - j
I
AI
I
XBr
Pa e 11-31
2-149
Cell Name I
SHC I
i) Clock Mode
__ _ tcw ----<-- tCWH ---0
Clock
Data
Q. XQ
_______________+~
__·t~p~d~~,_~--------------------
(Output)
AU-SHC-E2 I Sheet 3/3 I I Page 11-32
2-150
Cell Name I Function J Number of BC
SHJ
I
SCAN 8-bit DFF with Clock-Inhibit
& 2-to-1 Data Multiplexer I
78
Cell Symbol Propagation Delay Parameter
tup tdn
3.86 0.13 3.87 0.07 0.10 4 CK,IH -+ Q
- 3.30 0.13 3.20 0.09 0.16 4 CK,IH -+ XQ
A1- t--Q1
B1 - P-- XQ1
A2 - t--Q2
B2 - P-- XQ2
A3 - r--Q3
B3 - P-----
XQ3
A4 - r--Q4
B4 - )-- XQ4
AS - -Q5
B5 - )--XQ5
A6 - -Q6
B6 - )-- XQ6
A7 - -Q7
B7 - )-- XQ7
AB - -Q8
BB - )-- XQ8
AS ---c
BS ---c
CK -
1H -
in - Parameter Symbol Typ(ns»~
A - Clock Pulse Width tCW 5.B
B ---c Clock Pause Time tCWH 4.4
'----

Input Loading
An,Bn 1
(n=1-8)
AS,BS 1
CK 1
1H 1
SI 1
A,B 1
Output Driving
Q 18
XQ 18 ~, Minimum values for the typical operating condition.
AU-SHJ-E2 I Sheet 1/3 I I Page 11-33
2-151
Cell Name
SHJ
Equivalent Circuit
Al Bl A2 B2 A8 B8
CK
IH CKI
Ao Bo Ao Bo Ao Bo
XCKI ITo
A~LC>O ::1 ~
B~LC>O
::1 XSIo XSOo
XQo
------- XSIo XSOo
Qo XQo
ASo---{)o- AS o
Ql XQl Q2 XQ2 Q8 XQ8
Ell BSo---{)o- BS o
SI
Equivalent Circuit (FFo)

XBI XCK1
--L --L
Ao XQo
AS o
Bo
BS o
, . . - - - - - 0 XSOo
XCK1 B1 CKI
X>----0Qo
CK1 XA1
XS10 o-------l
I B1.
I XCKI --L
AI
I
XBI
AU-SHJ-E2 Pa e 11-34
2-152
Cell Name I
SHJ
Definitions of .Parameters
i) Clock Mode
Clock
Data ~tSD ~tHD'"
Q. XQ
(Output)
AU-SHJ-E2 I Sheet 3/3 I I Page 11-35
2-153
SHK
I
SCAN 8-bit DFF with Clock-Inhibit
& 3-to-1 Data Multiplexer I 88
Cell Symbol ProJ:agation Delay Parameter
tup tdn
- to KCL to KCL KCL2 CDR2 Path
A1 _ 3.71 0.13 3.68 0.07 0.08 4 CK,IH -> Q
B1 _ ,----- Q1 3.27 0.13 3.20 0.11 0.15 4 CK,IH -> XQ
C1 _
0-- XQ1
A2 _
B2 _ -Q2
C2 _
0-- XQ2
A3 _
B3 _ -Q3
C3 _
A4 _ o--XQ3
B4 _ -Q4
C4 _
AS _ P-- XQ4
BS _ -Q5
C5 _
b-- XQ5
A6 _
B6 _ r--- Q6
C6 _
A7 _ p-- XQ6
B7 _ I-- Q7
C7 _
A8 _ P--- XQ7
B8 _ I--Q8
fJI C8 _
AS
BS
--C
--C
p-- XQ8
CS --C
CK -
IH - Parameter Symbol Typ(ns)'"
SI - Clock Pulse Width tCW 5.8
B --C
'--- Data Setup Time tSD 3.1
Input Loading
An,Bn,Cn 1
(n=1-8)
AS,BS,CS 1
CK 1
IH 1
SI 1
A,B 1
Output Driving
Q 18
AU-SHK-E2 I Sheet 1/3 I I Page 11-36
2-154
Cell Name
SHK
Al BI CI A2 B2 C2 A8 B8 C8
Equivalent Circuit
CI< CK1
1H Ao Bo Co Ao Bo Co Ao Bo Co
XCI<1 FFo
Ao-{lo L!> ::]

AS o
.o-{lo L!> : ::1

XSOo
XQo
XSOo
XQo
BS o
CS o
XS10 XSOo
Qo XQo
ASo---i)o- AS o
QI XQI Q2 XQ2 Q8 XQ8
BSo---i)o- BS o
CSO---i)O- CS o
S1
Equivalent
Ao
AS o
Bo
BS o
Co
CS o , - - - - { ) XSOo
(VlN)
XAI II
-L CKI XAI
XS10
I BI
I XCI<I -L
AI
I
XBI
Pa e 11-37
2-155
Cell Name I
SHK I
i) Clock Mode
_____ 0-- tcw ---<_- tCWH ~

Clock
Data I-- tSD'~ tHD ...
Q. XQ
______________~~--'tp~d~--t~~--~-----------------
(Output)
AU SHK-E2 I Sheet 3/3 I I Page 11-38
2-156
SFDM
Ce11 Symbol
SCAN I-input DFF with Clock-Inhibit
Pro]:agation Delay Parameter
I 10
tup tdn
1.85 0.13 1.90 0.08 0.14 4 CK .. Q
2.35 0.13 2.31 0.07 0.08 4 CK .. XQ
D-
-
f--Q
CK-
IH- P---XQ
SI - f--SO
A-
D --<
'---
Parameter Symbol Typ(ns) *


Input Loading
D 2
CK 1
IH 1
SI 2
AB 2
Output Driving
Q 18
SO 18 * Minimum values for the typical operating condition.
AU-SFDM-Ell Sheet 1/3 I I PaJ!:e 11-39
2-157
Cell Name
SFDM
Equivalent Circuit
CLK XBCK XCLK
-L -L -L
no------1 XQ
II
CLK XACK
XACK
-L
Slo-----I I
XBCK
I Q
ACK
so
Ao-r--
:= XCLK
L-{)o----- XACK
ACK
B o-...
~----- XBCK
L-{)o----- BCK
Pa e 11-40
2-158
Cell Name J
SFDM I
i) Clock Mode
Clock ---.. - tcw - - - - - tCWH - -
Data .- tSD·~ tHD ...
I<--tpd - - 0
Q. XQ 1,--+------------------
(Output)
AU-SFDM-Ell Sheet 3/3 I I Page 11-41
2-159
SFDO
Cell Symbol
I SCAN I-input DFF with ClearProJagation
and Clock Inhibit
Delay Parameter
I 11
tup tdn
to XCL to XCL XCL2 CDR2 Path
2.14 0.14 2.04 .0.09 0.15 4 CX .. Q
2.37 0.13 2.62 0.07 0.08 4 CX .. XQ
2.51 0.13 2.18 0.09 0.15 4 CL .. Q,XQ
;---
D- -Q
CK-
IH- :>-XQ
51 - -SO
A-
B --<
Parameter Symbol 1'yp(ns}*

CL Clock Pulse Width tCW 4.0
Input Loading Clear Pulse Width tLW 4.0

Pin Name Factor (tu) Clear Release Time tREM 1.6
D 2 Clear Hold Time tINH 3.9
CK,IH 1
51 2
A,B 2
CL 2
Output Driving
Q 18
XQ 18
AU-SFDO-E1 Sheet 1/3 I I Page 11-42
2-160
Cell Name
SFDO
Equivalent Circuit
CLK XBCK XCLK

--L --L --L
D XQ
CLK XACK
XACK
--L
510-----1 I
XBCK
I Q
ACK
SO
:=
A o-~~----- ACK
L-{>o-- XACK
XCLK
B o-~~----- XBCK
L-{>o--BCK
Pa e 11-43
2-161
Cell Name I
SFDO I
i) Clock Mode
i'--tCWH ----0
I<-- tcw ----0
Clock ~
Data ~tSD .... tHD ....
-tpd-
Q. XQ
(Output)
ii) Clear Mode
CK tREM ->
Clear I<-tLW-
~
<-tpd->
Q. XQ
(Output)
tINH
CL
AU-SFDO-Ell Sheet 3/3 I I Page 11-44
2-162
SFDP
Cell SJ'lIIbol
SCAN I-input DFF with Clear,Preset,and Clock Inhibit
I 12
tup tdn
2.16 0.14 2.03 0.09 0.15 4 CK -+ Q
PR 2.86 0.13 2.62 0.07 0.08 4 CK -+ XQ
2.91 0.13 2.15 0.09 0.15 4 CL -+ Q,XQ
3.64 0.14 0.83 0.07 0.08 4 PR -+ Q,XQ
D- r--Q
CK-
IH- P--XQ
SI - r--SO
A-
B --<


Pin Name Factor (iu) Clear Release Time tREM 1.6
CK,IH 1
SI 2 Preset Pulse Width tPW 4.9
A,B 2 Preset Release Time tREM 0.8
CL PR 2 Preset Hold Time tINH 4.9
Output Driving
Q 18
XQ 18
AU-SFDP-Ell Sheet 1/4 I I Page 11-45
2-163
Cell Name
SFDP
Equivalent Circuit
CLo---------------~--~--------------------------_,
CLK XBCK XCLK
-L -L -L
D XQ
II
CLK XACK
PRo-----------~--------------J
XACK
-L
BIo----i I
XBCK
I Q
ACK
SO
~~~--h~ :C~
A o>--...~--------- ACK
~XACK
XCLK
B o-,..~--------- XBCK
~BCK
Pa e 11-46
2-164
Cell Name I
SFDP I
i) Clock Mode
-tCWH ----I
I>-- tcw ----t
Clock ----'\
Data --tSD i'-tlID ...
Io-tpd - 0
Q. XQ
(Output)
ii) Clear Mode
CK tREM "'
Clear I'--tLW-
----'\
10- tpd"'
Q. XQ
(Output)
tINH
Clear
AU-SFDP-Ell Sheet 3/4 I I Page 11-47
2-165
Cell Name I
SFDP I
iii) Preset Mode
CK ~tREM~1~-----------------------
Preset ~ ~tPW~I~ __ ~ ___________________________
Q, XQ
(Output)
tINH
Preset
AU-SFDP-Ell Sheet 4/4 I i Pa.Ae 11-48
2-166
SFDR
Cell S~bol
I
SCAN 4-injlut DFF with Clear and Clock Inhibit
I 36
tup tdn
2.98 0.14 3.00 0.09 0.15 4 CK ... Q
r---- - - 3.07 0.09 0.16 4 CL ... Q
DA - -QA
DB - -QB
DC - -QC
DD- -QD
CK-
IH-
SI - -SO
A-
B --<

Data Steup_ Time tSD 0.9


Pin Name Factor (iu) Clear Release Time tREM 2.3
CK,IH 1
SI 2
A,B 1
CL 1
Output Driving
Q 18
SO 18
AU-SFDR-E11 Sheet 1/4 I I Page 11-49
2-167
Cell Name
SFDR
Equivalent Circuit
DA DB DC DD
QA QB QC QD
(
D D D D
510-____________-4 5
Q~IS Q~15 QI-T 5 Q-
Q. ---.J Q. ---.J Q. 50 _
no no no n1
CK 0--CK CLK I---..-ICLK r- CLK r- CLK _CLK
IH 0--IH XCLK XCLK _XCLK _XCLK r---- XCLK
ACK ACK ;-- ACK ;--ACK _ACK
A0-- A XACK XACK r-- XACK __ XACK r-- XACK SO
BCK BCK :- BCK :- BCK _ BCK
B ~ B XBCK XBCK XBCK XBCK XBCK
~ CLo CLo CLo CLo
CLo
Equivalent Circuit (CNTO)
CK
IH X>----CLK
XCLK
AO---4~ACK B o>---~ XBCK

. L
.______
. XACK
BCK
Pa ell-50
2-168
Cell Name
SFDR

CLK XBCK XCLK
~ ~~
1---1----1 X } - - - t - - - ( l Qo
CLo
XACK I I
~ CLK XACK
I
ACK
I
XBCK
Q
Equivalent Circuit (FF1)

CLK XBCK XCLK
~ ~ ~
CLo
XACK II
~ CLK XACK
I
ACK
I
XBCK
Q
80
Pa ell-51
2-169
Cell Name I
SFDR J
i) Clock Mode
io---tCWH ---0
!<--tcw-
Clock -----.
Data <-tSD ~tHD'"
I<--tpd -.
Q. XQ
(Output)
ii) Clear Mode
CK ~tREM ...
Clear
-- I<--tLW-
.... tpd ....

Q. XQ
(Output)
tINH
CL
AU SFDR-El Sheet 4/4 I I Page 11-52
2-170
SFDS
Cell Symbol
SCAN 4-input DFF with Clock Inhibit
I 31
tup tdn
to KCL to' KCL KCL2· CDR2 Path
2.46 0.13 2.42 ~.08 0.13 4 CK ... QA-QC
2.63 0.13 2.60 0.08 0.13 4 CK'" QD
.---
DA- I--QA
DB - I--QB
DC - r--QC
DD- I--QD
CK-
IH-
SI - I--SO
A-
B --C Parameter Symbol Typ(ns)*
- Clock Pulse Width tCW 4.0
Clock Pause Time tCWlI 4.0
Data Hold Time tHO 1.8
Input Loading
D 2
CK,IH I
SI 2
A,B I
Output Driving
Q 18
SO 18
are given bj'_ the maximum delay multiplier.
AU-SFDS-ElI Sheet 1/4 I I Page 11-53
2-171
Cell Name
SFDS
Equivalent Circuit DA QA DB QB DC QC DD QD
51 ~-----------'.
CK so
IH
A
B
CLK
XCLK
ACK
~ttQ FFI
QO
XACK
BCK
XBCK Equivalent Circuit (FFl)
CLK Q
-L
D 1--+---1 >0-_------'0 QO
BCK CLK
CLK
-L
5
I II XdLK BCK
ACK CLK XACK -L
CK CLK
IHA n X C L K T
CNTO ACK XBCK
B XACK
BCK
XBCK Equivalent Circuit A~~V=ACK
(CNTO)
CK '---~-~XACK
)()-----~ CLK
IH
XCLK
'--__
~K
~-~BCK
Pa ell-54
2-172
Cell Name
SFOS
0t]=
S
CLK
XCLK
ACK
FF2
Q
SO
XACK
BCK
XBCK

SO
CLK
Q
--L
o
BCK CLK
CLK
--L
S
II BCK
ACK CLK XACK --L
I
XBCK
Pa ell-55
2-173
Cell Name I
SFDS
i) Clock Mode
Clock
Data -tSD iO-tHD ....
Q. XQ
(Output)
AU-SFDS-Ell Sheet 4/4 I I Page 11-56
2-174
SFJD
Cell Symbol
SCAN J-K FF with Clock Inhibit
ProJ:agation Delay Parameter
J 14
tup tdn
2.59 0.14 2.40 0.10 0.16 4 CK -+ Q
2.77 0.13 3.03 0.07 0.08 4 CK -+ XQ
2.24 0.13 1.98 0.07 0.14 4 CL -+ Q,XQ
r--
J- -Q
K-
e>-- XQ
CK-
IH-
SI - -SO
A-
B --C
CL
Data Setup Time (J) tSD 3.0
Data Hold Tima (J) tHO 0.5
Input Loading Data Setup Time (K) tSD 2.6

Pin Name Factor (.tu) Data Hold Time (K) tHO 0.1
J,K 1
CK,IH 1 Clear Pulse Width tLW 4.0
SI 2 Clear Release Time tREM 1.6
A,B 2 Clear Hold Time tINH 3.5
CL 2
Output Driving
Q 18
XQ 18
AU-SFJD-ElI Sheet 1/3 I I Page 11-57
2-175
Cell Name
SFJD
Equivalent Circuit
XQ
Ko---'
CLo-------------~~=+--~-------+--~~-=~+--------,
XACK
-L
IfII SI T
XBCK
Q
T
ACK
SO
~ 4==
0
CK~
IH
:=
XCLK
A
XACK
0
B
4=n~
BCK
AU-SFJD-El Sheet 2 3 Pa e 11-58
2-176
FUJITSU ·CMOS GATE ARRAY UNIT CELL SPECIFICATION I AU Version
Ce11 Name I
SFJD J
i) Clock Mode
i<-tCWH--
-----...
-tcw ----0
Clock
/
Data ~tSD' .... tHD ...
-tpd-
Q. XQ
(Output)
if) Clear Mode
CK tREM ..
Clear Io--tLW ----0

~
... tpd"
Q. XQ
(Output)
tINH
CL
AU-SFJD-Ell Sheet 3/3 I I Page 11-59
2-177
AU Series Unit Cell Ubrary CMOS Channel/ess Gate AmlYs
2-178
CMOS Channel/ess Gate Arrays AU Series Unit CeD Ubrary
Non Scan Flip-flop Family
Unit Cell Basic

2-181 FDM Non-Scan 0 Flip-flop 6

2-183 FDN Non-Scan 0 Flip-flop with Set 7
2-185 FOO Non-Scan 0 Flip-flop with Reset 7
2-187 FOP Non-Scan 0 Flip-flop with Set and Reset 8
2-190 FOQ Non-Scan 4-bit 0 Flip-flop 21
2-192 FOR Non-Scan 4-bit 0 Flip-flop with Clear 26
2-195 FOS Non-Scan 4-bit 0 Flip-flop 20
2-197 FD2 Non-Scan Power 0 Flip-flop 7
2-199 F03 Non-Scan Power 0 Flip-flop with Preset 8
2-201 F04 Non-Scan Power 0 Flip-flop with Clear and Preset 9
2-203 FD5 Non-Scan Power 0 Flip-flop with Clear 8
2-205 FJD Non-Scan Positive Edge Clocked
Power J-K Flip-flop with Clear 12
2-179
AU Series Unit Cell Ubrary CMOS Channs/less Gale Arrays
2-180
FDM
Cell Symbol
I Non-SCAN DFF Propagation Delay Parameter
I 6
tup tdn
1.40 0.13 1.44 0.07 CK -+ Q
1. 73 0.13 1.89 0.07 CK -+ XQ
D=Q='
CK
XQ


Input Loading
D 2
CK 1
Output Driving
Q 18
XQ 18
Function Table
Inputs Outputs
D CK Q XQ
H t H L
L t L H
AU-FDM-E3 J Sheet 112 I I Page 12-1
2-181
Cell Name
FDM
Equivalent Circuit
eLK XCLK
Q
.....L .....L
D XQ
T T
XCLK CLK
XCLK CLK
.....L .....L
ICLK I
XCLK
CK~CLK
XCLK
Definition of Parameters
!<-- tcWH ----0
I<---tcw -
CK
r---
I<--tSD- tHD ....
D
I<- tpd-
Q,XQ
AU-FDM-E3 Pa e 12-2
2-182
FDN
Cell Symbol
I Non-SCAN DFF with SET
I 7
tup tdn
t~ KCL to KCL KCL2 CDR2 Path
1.44 0.13 1.40 0.07 0.10 4 CK ... Q
1. 97 0.13 1. 94 0.07 CK ... XQ
S 1. 79 0.13 0.86 0.07 S ... Q,XQ
D
CK
=6=:Q

Input Loading Set Pulse Width tSW 4.0

Pin Name Factor (.eu) Set Release Time (S) tREM 0.3
D 2 Set Hold Time tINH 3.1
S 2
CK 1
Output Driving
Q 18
XQ 18
Function Table
Inputs Outputs
S D CK Q XQ
L X X H L
H H t H L
H L t L H
AU-FDN-E3 I Sheet 1/2 I I Page 12-3
2-183
Cell Name
FDN
Equivalent Circuit
S
CKO XCKO Q
-L -L
o---~--~ Xr-----~XQ
D
CKO
-L
ICKO IXCKO
CK~CKO
XCKO
1) tcw, tCWH, tSD, tHD and tpd (CK ~ Q,XQ)
CK
Q,XQ
2) tsw, tREM, tINH and tpd (S ~ Q,XQ)
tcw
CK ))---/
tsw 1r--+------)) <-- t INH ------> ,..--
s
. - - - + - - - - - ) ) ............, . - - - -
Q
--+-~ ~
XQ
))---+.....
~--+-----))""""'" ."------
AU-FDN-E3 Pa e 12-4
2-184
FDO
Cell Symbol
I Non-SCAN DFF with RESET Propagation Delay Parameter
I 7
tup tdn
1.55 0.13 1.43 0.08 CK .. Q
1. 73 0.13 2.07 0.07 CK .. XQ
1. 60 0.13 1.31 0.08 R .. Q,XQ
D
CK
=0=:, R Parameter Symbol Typ(ns)*


Input Loading Reset Pulse Width tRW 4.0

Pin Name Factor (iu) Reset Release Time (R) tREM 0.8
D 2 Reset Hold Time tINH 2.7
R 2
CK 1
Output Driving
Q 18
XQ 18
Function Table
Inputs Outputs
R D CK Q XQ
L X X L H
H H t H L
H L t L H
AU-FDO-E3 I Sheet 1/2 I I Page 12-5
2-185
Cell Name
FDO
Equivalent Circuit
CKO XCKO
-.L -.L Q
D ~----~ xr----~~ ~~--vXQ
I I
~CKO CKO XCKO
CK • L
XCKO
1) tcw, tCWH, tSD, tHD and tpd (CK ~ Q,XQ)
CK
Q,XQ
2) tRW, tREM, tINH and tpd (R ~ Q,XQ)
tCW
CK ~~_...../
tREM
~-----~~
R
~)---+-;.
Q >-----+_ _ _ _ _ ~~o 0 0 0 0 0 0 0 0 0 0 o~_ __
r-----+-----~~o ° 0 0 0 0 0 000 ° 0,.-----

XQ
-~~ ~
AU-FDO-E3 Pa e 12-6
2-186
FDP
Cell Symbol
I Non-SCAN DFF with Set andPro.agation
Reset
Delay Parameter
I 8
tup tdn
1.57 0.13 1.41 0.08 CK .. Q
1.96 0.13 2.00 0.07 CK .. XQ
.s 1. 79 0.13 1. 27 0.08 R .. Q.XQ
2.03 0.13 0.81 0.07 S .. Q.XQ
D- r--Q
CK -
~XQ
R Parameter Symbol Typ(ns)*


Input Loading Set Pulse Width tSW 4.0

Pin Name Factor (tu) Set Release Time (S) tREM 0.3
D 2 Set Hold Time tINH 3.1
S 2
R 2 Reset Pulse Width tRW 4.0
CK 1 Reset Release Time (R) tREM 0.8
Reset Hold Time tINH 2.7
Output Driving
Q 18
XQ 18
Function Table
InJluts Outputs
S R D CK Q XQ
H L X X L H
L H X X H L
L L X X Inhibited
H H H t H L
H H L t L H
AU-FDP-E3 I Sheet 1/3 I Page 12-7
2-187
Cell Name
FDP
Equivalent Circuit
CKO XCKO Q
--L
D XQ
XCKO I
CKO
XCKO CKO
--L --L
I I
CKO XCKO
CK
AU-FDP-E3 Pa e 12-8
2-188
Cell Name
FDP
1) tCW. tCWH, tSD, tHO and tpd (CK ~ Q,XQ)
-tcw tCWH-
CK ----..
~
~tSD- tHO •
D
~tpd--
Q,XQ
CK ))---'
1r--+------))
R
))--+~
Q lI.....-..--+_ _ _ _ _ )) ............'---_ __
XQ ·············ir---t-----))············,-----
))
3) tSW, tREM, tINH and tpd (5 ~ Q,XQ)
:' +-':~~--~~=i:tI~ =t-

I,,--tp_d
............. i,.....------~~ ......... j

Q
XQ
l . - -_ _ _ _ _ ~~ ~}.....
......... _ __
Pa e 12-9
2-189
Cell Name I Function lNumber of BC
FDQ
Cell Symbol
I Non-SCAN 4-bit DFF Pro~agation Delay Parameter
I 21
tup tdn
2.70 0.13 2.19 0.07 CK -+ Q
DA DC
I Dr IDf
f"--QA
CK -< f"--QB
f--QC
f--QD

Clock Pause Time tCWL 4.0

Input Loading
D 1
CK 1
Output Driving
Q 18

are ~gIven by the maximum delay mul tiplier.
Function Table
Input Output
CK D Q
•• H
L
H
L
AU-FDQ-E3 I Sheet 1/2 I Page 12-10
2-190
Cell Name
FDQ
Equivalent Circuit
r-------------------------,
XCKO CKO I
-L -L
DA o---------.-i QA
~
I
CK I
CKO I
I
XCK0 1
I XCKO CKO
~-------------------------~
DB 0 - - - - - - ' - -LoQB
I
~-------------------------4
I
DC 0 - - - - - - ' - ~QC
~-------------------------~
DD 0 - - - - - - ' - -Lo QD
I I
L _________________________ ~
----tcw tCWL - -
~
CK
-tSD ---" ~tHD ->

D
.... tpd.....
Q
Pa e 12-11
2-191
FDR
Cell Symbol
I Non-SCAN 4-bit DFF with CLEAR
Propagation 'Delay Parameter
I 26
tup tdn
2.11 0.13 2.90 0.07 CK -to Q
- - 1.75 0.07 CL -to Q
DA DC
,Dj (f
-QA
-QB
CK-
-QC
-QD
CL
I Parameter
Clock Pulse Width
Symbol
tCW
Typ(ns)*
4.0


Pin Name Factor (R.u) Clear Release Time tREM 1.2
CK 1
CL 1
Output Driving
Q 18
are,given by, the maximum delay multiplier.
Function Table
Inputs Output
CK D CL Q
X X L L
t L H L
t H H H
AU-FDR-E3 I Sheet 1/3 I I Pa.l!;e 12-12
2-192
Cell Name
FDR
Equivalent Circuit
r-------------------------,
I CKO XCKO I
....l... ....l... CLO
DA O - - - - - - , - j QA
I
I
XCKO
~
I
CK I
CK0 1
I I
XCK0 1 I CLO I I
CLo--{)o--{>:O~ ______ ~K~ _________ X~K~ ______ ~

DBo ~QB
I
~-------------------------~
DC O f - - - - - - - ' -II ...L.o
I QC
~-------------------------~
DD O > - - - - - - L ~ QD
IL _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ I
~
Pa e 12-13
2-193
Ce1l Name
FDR
1) tCW. tCWH. tSD. tHD. and tpd (CK~QA-QD)
tcw
CK
QA-QD
2) tLW. tREM. tINH and tpd
tcw
CK ))
tREM
tLW )) tINH
CL
tpd
QA-QD ......... . . . . .. ...
)S
SS··········· .
AU-FDR-E3 Pa e 12-14
2-194
FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION L "AU" Version
FDS
Cell Symbol
Non-SCAN 4-bit DFF
I 20
tup tdn
2.43 0.13 1. 96 0.07 CK ... Q
DA DB DC DD
CK
n QB
Q
QC
QD
•


Input Loading
D 2
CK 1
Output Driving
Q 18

* The values for the worst case operating condition
Function Table
Im:uts Outputs
CK D Q
t L L
t H H
AU-FDS-E3 I Sheet 1/2 I I Page 12-15
2-195
Cell Name
FDS
Equivalent Circuit
r-----------------------,
1 CLK XCLK
1 -L -L r - - - i X~--r---oQA
1
I
DAO-------------rl
i
1
II I
:XCLK CLK
o---f:>o-tI»-:
CK
. LK XCLK
-L
CLK
-L
XCLK I
ICLK I
XCLK
I- - - - - - - - - - - - - - - - - - - - - - - _-_-1----;0 QB
DBO~-----------L
I I
1-------------------------1
~_ _ _ _ _ _.J..I ~QC
DC 0-
I
I I
I- - - - - - - - - - - - - - - - - - - - - - - ~ QD
DD 0>----------'-1 I
I
1L _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ I
~
CK tcw ---r:;:::::..':!~-=:;:]
DA-DD
QA-QD
AU-FDS-E3 Page 12-16
2-196
FD2
Cell Symbol
I Non-SCAN Power DIT Projlagation Delay_ Parameter
I 7
tup tdn
1.32 0.07 1.38 0.04 0.08 7 CK .. Q
2.04 0.07 1.87 0.03 0.06 7 CK" XQ
DU'
CK
XQ

Clock Pause Time tCW 4.0

Input Loading
D 2
CK I
Output Driving
Q 36
XQ 36
Function Table
Inputs Outputs
CK D Q XQ
+ H H L
+ L L H
AU-FD2-E4 I Sheet 1/2 I I Page 12-17
2-197
Cell Name
FD2
Equivalent Circuit
CKO XCKO
Q
-L -L
D XQ
I" I"
XCKO CKO
XCKO CKO
-L -L
ICKO
" I"
XCKO
CK~XCJ<O
CKO
Io---tcw tCWL -
eK V-
I---tSD- I-tHD ....

D
... 'tpd......
Q.XQ
Pa e 12-18
2-198
FD3
Cell Symbol
I Non-SCAN Power DFF with Preset
I 8
tup_ tdn
1.37 0.05 1.39 0.03 0.08 7 CK ... Q
PR 2.24 0.05 2.00 0.03 0.06 7 CK ... XQ
0.06 7 PR ... Q,XQ
n1J=c
1. 91 0.05 0.73 0.03
CK
XQ


Input Loading Preset Pulse Width tPW 4.0

Pin Name Factor (Rou) Preset Release Time tREM 0.3
D 2 Preset Hold Time tINH 3.1
CK I
PR 2
Output Driving
Q 36
XQ 36
,'r Minimum values for the typical operating condition.
Function Table
Inputs Outputs
PR CK D Q XQ
L X X H L
H + H H L
H + L L H
AU-FD3-E3 I Sheet 1/2 I Page 12-19
2-199
Cell Name
FD3
Equivalent Circuit
PR
XCKO CKO r-+---------~ xr-----oQ
--L --L
~--~~xr-----oXQ
D
XCKO
--L
IXCKO ICKO
CK~CKO
XCKO
_tcw tCWL-
CK r-
----- tSD- tHD->

D
....tpd -0
Q,XQ
I'-tREM ...
PR ~tINH-
tpw
PR
Q,XQ
AU-FD3-E3 Pa e 12-20
2-200
FD4
Cell Symbol
I Non-SCAN Power DFF with Clear and Preset
I 9
tup tdn
1.52 0.06 1.38 0.04 0.08 7 CK .. Q
PR 2.25 0.05 2.18 0.03 0.06 7 CK .. XQ
1. 98 0.05 1.17 0.04 0.08 7 CL .. Q,XQ
1. 99 0.06 0.74 0.03 0.06 7 PR .. Q,XQ
D- I--Q
CK---(
P--XQ
CL

Input Loading Preset Pulse Width tPW 4.0

Pin Name Factor (R.u) Preset Release Time tREM 0.3
D 2 Preset Hold Time tINH 3.1
CK 1
CL 2 Clear PaIse Width tLW 4.0
PR 2 Clear Release Time tREM 0.8
Clear Hold Time tINH 2.7
Output Driving
Q 36
XQ 36
Function Table
InJ:uts Outputs
PR CL CK D Q XQ
L H X X H L
H L X X L H
H H ~ H H L
H H ~ L L H
AU-FD4-E3 I Sheet 1/2 I Page 12-21
2-201
Cell Name
FD4
Equivalent Circuit
PR
XCKO CKO Q
--L
D XQ
CKO I
XCKO
CKO XCKO
--L --L
I I
XCKO CKO
CL
CK~,--------------:CKO
~XCKO
-tcw tCWL -----;

CK r-
J::=. t SD -----; tHD->

D
f
....tpd ->
Q,XQ
I'-tREM ->
PR I<--tINH ----!
CL
PR
CL
Q,XQ
AU-FD4-E3 Pa e 12-22
2-202
FD5
Cell Symbol
I Non-SCAN Power DFF with CLEAR
I 8
tup tdn
1.51 0.07 1.37 0.04 0.08 7 CK" Q
2.06 0.07 2.06 0.03 0.06 7 CK .. XQ
1.89 0.07 1.22 0.04 0.08 7 CL ... Q.XQ
-
D- r--Q
CK--<
P--XQ
CL
Parameter Symbol 1VP(ns)*


Pin Name Factor (R.u) Clear Release Time tREM 1.2
CK 1
CL 2
Output Driving
Pin Name Factor _LR.u}
Q 36
XQ 36
are Riven by the maximum delay multiplier.
Function Table
Inputs Outputs
CL CK D Q XQ
L X X L H
H + H H L
H + L L H
AU-FD5-E4jSheet 1/2 I I Page 12-23
2-203
Ce11 Name
FDS
Equivalent Circuit
CKO XCKO
-L -L Q
D
XQ
;{)o-ri)o-- XCKO ICKO I

XCKO
CK • L
CKO
CL
-tcw tCWL - -
CK ',r-
-----/
~tSD"" tHO
D
I'-tpd-l
Q.XQ
CL - -tINH -
- tLW
r-
0..- - t p d -
Q.XQ
AU-FDS-E4 Pa e 12-24
2-204
FJD
Cell Symbol
I Non-SCAN Positive edge clocked Power JKFF with Clear I
12
tup tdn
3.52 0.07 2.37 0.04 0.07 7 CK .. Q
3.55 0.07 1. 99 0.04 0.07 7 CK .. XQ
1.92 0.07 1. 03 0.04 0.07 7 CL .. Q,XQ
J
CK
K =Q=:Q
CL Parameter Symbol Typ(ns)'~
J,K Setup Time tSD 2.0

J,K Hold Time tHD 1.0

Pin Name Factor (.tu) Clear Release Time tREM 2.0
CL 2 Clear Hold Time tINH 3.6
J 1
K 1
CK 1
Output Driving
Q 36
XQ 36
Function Table
Inputs Outputs
CL CK J K Q XQ
L X X X L H
H t L L Qo XQo
H t L H L H
H t H L H L
H t H H XQ. Qo
AU FJD-E2 I Sheet 1/2 I I Page 12-25
2-205
Cell Name
FJD
Equivalent Circuit
XQ
CK
CL Q
-tcw tCWH-
CK
----- "---
<-tSD ..... io-tHD •
J,K
E- tpd---->
Q,XQ
-tINH -
~- tLW
CL V"-
I<-- !--tpd - -
Q,XQ
AU-FJD-E2 Pa e 12-26
2-206
Binary Counter Family
Unit Cell Basic

2-209 SC7 Scan 4-bit Synchronous Binary

Up Counter with Parallel Load 62
Down Counter with Parallel Load 66
2-219 C11 Non-Scan Flip-Flop for Counter 11
2-221 C41 Non-Scan 4-bit Binary Asynchronous Counter 24
2-224 C42 Non-Scan 4-bit Binary Synchronous Counter 32
2-227 C43 Non-Scan 4-bit Binary Synchronous Up Counter 48
2-235 C47 Non-Scan 4-bit Binary Synchronous Up/Down Counter 68
2-239 SC43 Scan 4-bit Synchronous Binary Up Counter with
Asynchronous Clear 59
2-243 SC47 Scan 4-bH Synchronous Binary Up/Down Counter 78
2-207
2-208
SCAN 4-bit Synchronous Binary
SC7
Cell Symbol
IUp Counter with Parallel Load
I 62
tup tdn
2.64 0.07 2.44 0.05 0.12 7 CK,1H ... Q
4.63 0.07 4.27 0.05 0.12 7 CK,1H ... XQ
6.24 0.07 4.19 0.03 - - CK,IH ... CO
DA - 1.60 0.07 0.08 0.03 - - C1 ... CO
-QA
DB -
DC -
::r--- XQA
-QB
DD -
::r--- XQB
CK- -QC
1H - ::r--- XQC
L --C -QD
Symbol Typ(ns)'·'
CI - ::r--- XQD Parameter
EN -
-CO Clock Pause Time tCWH 5.8
SI -
A - tSD 1.6
Data Setup Time
B --C tHD
Data Hold Time 2.7
Load Setup Time tSL 5.1

Load Hold Time tHL 2.9
Input Loading CI Setup Time tSC 5.8

Pin Name Factor (tu) CI Hold Time tHC 2.2
D 1
CK 1 EN Setup Time tSE 5.8
IH 1 EN Hold Time tHE 2.2
L 1
CI 2
EN 1
S1 1
A,B 1
Output Driving
Q 36
XQ 36
CO 36 ~, Minimum values for the typical operating condition.
AU-SC7-E2 I Sheet 1/5 I J Page 13-1
2-209
Cell Name
SC7
Equivalent Circuit
DA QA XQA DB QB XQB DC QC XQC DD QD XQD
XCKI XCKI
CKI CKI
LDI LDI
XLDI XLDI
XAI XAI
AI AI
BI BI
XBI XBI
S Qo H-----i
XTG
SI
EN
CI
CO
~ XAI
CK o---+-,,~ ) O - - - -.... CKI
IHo---+-·r AO>---------1t>o
XCKI ~AI
L O>---------1t>o ~ LDI B O"---t>o ~BI
~XLDI ~XBI
AU-SC7-E2 Pa e 13-2
2-210
Cell Name
SC7
Equivalent Circuit (FFu)
Q
D
XQ
XCKI BI CKI QO
XAI XCKI AI
I -.L -.L -.L
XLDI
s
I II
AI CKI XAI I
XBI
XTG o--+--------+--i X)----t
Pa e 13-3
2-211
Cell Name
SC7
Function
Load L LJ
DA
DB
Data
Input DC
DD
Clock CK+IH
Enable EN
Carry in CI
L-J
QA ~
QB ~
Data
QC
Output
I
0 QD
CO n
Mode
Inhibit Load Count Inhibit
AU-SC7-E2 Pa e 13-4
2-212
Cell Name
SC7
i) Clock Mode
tcw --I"--tCWH
Clock
tSD tHO
Data
CI
EN
AU-SC7-E2 Pa e 13-5
2-213
SCAN 4~bit Synchronous Binary
SC8
Cell Symbol
IDown Counter with ParaHel Load
I 66
tup tdn
2.70 0.06 2.55 0.05 0.11 7 CK,IH ... Q
3.52 0.05 3.46 0.03 CK,IH'" XQ
5.13 0.07 6.70 0.03 CK,IH'" BO
DA- 1.19 0.07 1.82 0.03 BI ... BO
-QA
DB - :)-- XQA
DC -
-QB
DD -
0 - - XQB
CK - -QC
IH - :)-- XQC
L --< -QD
BI --< 0 - - XQD
EN --<
SI - o--BO Clock Pause Time tCWH 5.5
A ---
B --<:

Input Loading EN Setup Time tSE 6.5

Pin Name Factor (Rou) EN Hold Time tHE 1.5
D 1
CK 1 BI Setup Time tSB 6.5
IH 1 BI Hold Time tHB 1.5
L 1
BI 2
EN 1
SI 1
A,B 1
Output Driving
Q 36
XQ 36
BO 36 * Minimum values for the typical operating condition.
AU-SC8-E2 I Sheet 1/5 I I Page 13-6
2-214
Cell Name
SCB
Equivalent Circuit
DA DB DC DD
SI
EN
BI
~XAI
CKo---+-"'. )()----.... CKI
IH o---+--r AO>----t>o
XCKI ~AI
L O>------lt>o ~ LDI BO
t>o ~BI
~XLDI ~XBI
Pa e 13-7
2-215
Cell Name
SC8
V2B
Q
D
XQ
XCKI BI CKI XQO
XAI XCKI AI
I ...l ...l...l
XS
I II
Ell AI CKI XAI I
XBI
XTGo-+-------------~~ xr--~
AU-SC8-E2 Pa e 13-8
2-216
Cell Name
SCB
Function
Load L LJ
DA
DB
Data
Input DC
DD
Clock CK+IH
EN
Enable ,
Carry in BI I
QA ~
QB ~
Data
QC
Output
QD
BO LJ
Hade
Inhibit Load Count down Inhibit
Pa e 13-9
2-217
Cell Name
SC8
i) Clock Mode
tcw --+jol-- tCWH
Clock
Data
EN
BI
AU-SC8-E2 Pa e 13-10
2-218
C11
Cell Symbol
I Non-SCAN Flip-Flop for Counter
Propaga'tion Delay Parameter
I 11
tup tdn
1.52 0.13 1.40 0.08 CK .. Q
2.03 0.13 2.38 0.08 CK .. XQ
2.10 0.13 1. 39 0.08 CL .. Q,XQ
r--
D-
L- '--Q
CK-
TG - P--XQ

CL
Clear Hold Time tINH 0,4
Input Loading
Pin Name Factor (tu) Load Setup Time (CK) tSL 1.9
L 2 Load Hold Time (CK) tHL 0.4
TG 2
CL 2 Data Setup Time (CK) tSD 2.0
D,CK 1 Data Hold Time (CK) tHD 0.4
Output Driving TG Setup Time (CK) tST 2.4

Pin Name Factor (tu) TG Hold Time (CK) tHT 0,0
Q 18
XQ 18
are .I1;iven by the maximum delay multiplier,
Function Table
L D TG CL CK Q(Qo)
X X X L X L
H H X H t H
H L X H t L
L X L H t Q(Qo)
L X H H t Q(Q.)
AU-C11-E3 I Sheet 1/2 I I Page 13-11
2-219
Cell Name
Cll
Equivalent Circuit CL
XLO
-L
Q
D
XQ
LO
TCKO T
XCKO
CL
TG o--t--+!
CK~CKO
• L-XCKO
CK
CL
CL tINH
tSL tHL
L
tSD tHD
D
tHT
TG
Pa e 13-12
2-220
C41
Cell Symbol
I Non-SCAN 4-bit Binary Asynchronous Counter
I 24
tup tdn
1. 60 0.11 1.49 0.08 - - CK .. QA
2.94 0.11 2.63 0.08 - - CK .. QB
4.11 0.11 3.80 0.08 - - CK .. QC
5.28 0.11 4.96 0.08 - - CK ... QD
-
r--QA
- - 3.35 0.08 - - CL ... Q
f--QB
-QC
-QD
CK -

CL
CK 1
CL I
Output Driving
Q 18

Function Table
In~uts Outputs
CL CK Q
H t Count up
L X L
AU-C41-E3 I Sheet 1/3 I I PaRe 13-13
2-221
Cell Name
C41
Equivalent QA QB QC QD
Circuit
CKO
FTO FTO ITO FTO
XCKO
CLO
CK~CKO
v L- xcKO
FTO (Flip-Flop for Counter) (not Unit Cell)

Symbol Function Table
Q CLO CKO Q
8
CKO
QO L X L
XCKO
XQO H t Qn-1
CLO
CKO CLO XCKO

Q
QO
I I
XCKO CKO
XCKO CKO
-.L -.L
I I
CKO XCKO
CLO
L-----------------------------~--__oXQO
AU-C41-E3 Pa e 13-14
2-222
Cell Name
C41
CK
CL
AU-C41-E3 Pa e 13-15
2-223
C42
Cell Symbol
I Non-SCAN 4-bit Binary Synchronous Counter
I 32
tup tdn
2.55 0.11 1.87 0.07 0.10 4 CK .. Q
- - 2.69 0.07 0.10 4 CL .. Q
-
-QA
-QB
-QC
-QD
CK -

Clock Pulse Width tCW 4,0
CL
CL 1
CK 1
Output Driving
Q 18

Function Table
Inputs Outputs
CL CK Q
H t Count up
L X L
2-224
Cell Name
C42
Equivalent QA QB QC QD
Circuit
CKO CKO CKO CKO
XCKO
CLO
. . XCKO
CK o---{)o>-----+---1~ CKO CL~CLO
FT2 (Flip-Flop for Counter)(not Unit Cell)
Function Table
Inputs Output
CLO XTG CKO Q(QO)
CKO Q
FT2 L X X L
XCKO
H H t Qn-l
XTG QO
H L t Qn-l
CLO
AU-C42-E3 Pa e 13-17
2-225
Cell Name
C42
Equivalent Circuit of FT2
CLO
CKO XCKO Q
--L
QO
CLO
I XCKO CKO CKO
XCKO --L --L
I I
CKO XCKO
XTG 0--+---t--1
tcw --+-- tCWH

CK
))---/
tREM
lr--t------ S) tINH
CL
AU-C42-E3 Pa e 13-18
2-226
C43
Cell Symbol
I Non-SCAN 4-bit Binary Synchronous Up_ Counter
Delay Parameter
I
Pro~aj?;ation
48
tup tdn
2.37 0.13 1. 92 0.07 CK -+ Q
4.48 0.13 2.85 0.07 CK -+ CO
1. 28 0.13 0.65 0.07 CI -+ CO
-- - 3.11 0.07 CL -+ Q
DA -
r--
r-QA
- 2.11 0.07 CL -+ CO
DB - I--QB
DC - f-QC
DD- f-QD
L --C
CK -
EN-
CI - f-CO
CL tSD
Data Setup Time 2.1
Input Loading Load Hold Time tHL 1.1
Pin Name Factor (.I'.u) CI Setup Time tSC 3.5
D 1 CI Hold Time tHC 0.8
L,EN 1 EN Setup Time tSE 3.5
CK,CL 1 EN Hold Time tHE 0.8
CI 2 Clear Pulse Width tLW 4.5
Output Driving Clear Hold Time tINH 6.7
Q 18
CO 18
-.': Minimum values for the typical operating condition.
Function Table
Inputs Outputs
CL L D EN CI CK Q
L X X X X X L
H L H X X t H
H L L X X t L
H H X X L X No Counting
H H X L X X No Counting
H H X H H t Count up
Note : The CO output produces a high level

output data when the counter overflows.
AU-C43-E2 I Sheet 1/4 I Page 13-19
2-227
..------.F""u;-.J"T'IT;;;;s;;;u,--;;cvM~OS"'G;-;A-;;;TE;;::-A~R~R;-;A7,Y-..,U;;;N:;-:I~T;-;;C~EL;-;L;-;:S;;;P"'"EC"i':I""F"'I'""C'"'"A"'T""'IO"'N-;--------,-,' AU "--Ver 5 ion---
Cell Name
C43
Equivalent Circuit
DA QA DB QB DC QC DD QD
LO LO LO LO
XLO XLO
CKO CKO
XCKO XCKO
CLO CLO
CL o--j)o- CLO
L xr~~------~ LO
CK~ XCKO
CKO
XLO
AU-C43-E2 Pa e 13-20
2-228
FUJITSU CMOS GATE ARRAYA UNIT CELL SPECIFICATION AU Version
Cell Name
C43
FT3 (Flip-Flop for Counter) (not Unit Cell)
D LO D XTGO CLO CK Q(QO)

LO Q
X X X H X L
XLO Qo H H X L t H
CKO H L X L t L
L X H L t Q(QO)
XCKO L X L L t QCQO)
XTGO
CLO
Eguivalent Circuit of FT3

CLO
XLO
-L
D Q
QO
LO 0
CKO XCKO
XTGO 0--+-+-1
Pa e 13-21
2-229
Cell Name
C43
tcw tCWH
CK
))
tSD ))
D
))
tREM
tLW o--tINH-
CL
))
L
S)
CI SS
tSE tHE
EN
SS
f.JI
AU-C43-E2 Pa e 13-22
2-230
FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION L AU Version
C45
Cell Symbol
I Non-SCAN 4-bit Binary Synchronous Up Counter
Propagation Delay Parameter·
I 48
tup tdn
2.14 0.11 1.50 0.07 0.11 4 CK .. Q
4.06 0.14 2.26 0.07 CK .. CO
1.53 0.14 1. 09 0.07 CI .. CO
~
DA- -QA
DB - -QB
DC - -QC
DD- -QD
L -C
CK -
EN-
C! - '---CO
CL
Input Loading Load Hold Time tHL 1.7
Pin Name Factor (R,u) CI Setup Time tSC 5.3
D 1 CI Hold Time tHC 1.6
L,EN 1 EN Setup Time tSE 5.3
CK,CL 1 EN Hold Time tHE 1.6
CI 2 .Clear Setup Time tSR 3.1
Clear Hold Time tHR 1.6
Output Driving
Q 18
CO 18
Function Table
In~uts Outputs
CL L D EN CI CK Q
L X X X X t L
H L H X X t H
H L L X X t L
H H X H H t Count up
Note : The CO output produces a high level

2-231
--II AU" ---yersron-·-
Cell Name
C45
Equivalent Circuit
LO LO LO LO
XLO XLO XLO
CKO CKO CKO
XCKO XCKO XCKO
CLO CLO CLO
CL o---j)o--- CLO
L LO
CK~ XCKO
eKO
)0---+ XLO
AU-C45-E3 Pa e 13-24
2-232
FUJITSU CMOS GATE ARRAYA UNIT CELL SPECIFICATION AU Version
Cell Name
C45
FTl (Flip-Flop for Counter) (not Unit Cell)
Function Table
D LO D XTGO CLO CK Q(QO)

LO Q
L X X H t L
XLO QO H H X L t H
CKO H L X L t L
L X H L t Q(QO)
XCKO L X L L t Q(QO)
XTGO
CLO
CLOo----------------.
XLO
-L
D Q
QO
LO O------------~
T T
CKO XCKO
XTGO o--+--+---l
Pa e 13-25
2-233
Cell Name
C45
tcw -->1<-- tCWH

CK
tSD
D
tHR
CL
tSL tHL
L
tsc tHC
CI
tSE tHE
EN
IfJI
Pa e 13-26
2-234
C47
Cell Symbol
I Non-SCAN 4-bit Binary Synchronous Up/Down Counter
ProIagation Delay Parameter
I 68
tup tdn
3.19 0.13 2.87 0.13 0.20 4 CK .. Q
4.33 0.09 4.90 0.07 CK .. CO
4.01 0.13 4.43 0.13 0.20 4 L .. Q
1.98 0.09 2.41 0.07 DU .. CO
r-
DA - t--QA
DB - r-QB
DC - -QC
DD - -QD
L --<
CK -
EN --<
DU - ::r-- CO
- Parameter Symbol Typ(ns)~'

Input Loading
Pin Name Factor (Rou) DU Setup Time tSU 4.3
D 1 DU Hold Time tHU 0.7
L 2
DU 1 EN Setup Time tSE 4.0
CK 1 EN Hold Time tHE 1.0
EN 3
Output Driving Clear Hold Time tINH 8.9
Q 18 Load Pulse Width tLW 4.0
CO 18
Function Table
.Inj:uts Outputs
Q L EN DU CK Q
H L X X X H
L L X X X L
X H H X t No Counting
X H L L t Count Up
X H L H t Count Down
Note : The CO output produces a low level output

pulse when the counter overflows or underflows.
AU-C47-E2 I Sheet 1/4 I 1 Page 13-27
2-235
Cell Name
C47
Equivalent Circuit
- "
u
CO
"
DU
r--
H>r- u DA 0--
r-----o QA
»-
LO-
CKO- FT7
XCKO -(
EN I--
l:V- I- L-1
,----
r-----o QB
~
LO-
DCK~
XCKO CKO - FT7
CKO -{
CKO r--
L 0-(>0-----'7LO ~
~~ I
DC 0-::--
LO-
r-----o QC
CKO - FT7
I XCKO -{
I--
~1
r--
f' DD 0-::-- QD
LO-
L---
CKO- FT7
XCKO -c
~
f----
~r-
L-/
AU-C47-E2 Pa e 13-28
2-236
Cell Name
C47
FT7 (Flip-Flop for Counter)(not Unit Cell)
Function Table
CKO
XCKO
LgEQ FT7
QO
LO
H
D
H
In~uts
TGO
X
CKO
X H
Outputs
QO(Q) Q(QO)
TGO H L X X L H
XQO
L X L t Qn-l Qn-l
L X H t Qn-l Qn-l
.----------------------oXQO
~--------~ xr-------oQ
r-+------rr ~~------~--~QO
I I
XCKO XCKO CKO CKO
~ ~
XDO DO
LO LO
CKO XCKO
TGO 0-+---+-1 A.r--...,.
D~DO
v L- XDo
Pa e 13-29
2-237
Ce11 Name
C47
tcw tCWH
CK
))-~
----~lr~II~--~~----~
D
--~~I~~I~~~~----~
EN ~_t_SE_-
__-_-~~t_~~r--------~~
tsu
DU
~---~-------------
AU-C47-E2 Pa e 13-30
2-238
SC43
I
SCAN 4-bit Synchronous Binary Up Counter
with Asynchronous Clear I
59
tup tdn
3.42 0.13 3.29 0.07 0.10 4 CK -+ Q
r--- 4.12 0.13 4.40 0.07 0.10 4 CK -+ CO
DA- -QA - - 2.09 0.07 0.10 4 CL -+ Q
DB - -QB 1.46 0.13 1.00 0.07 0.10 4 CI -+ CO
DC - -QC -- 2.86 0.07 0.10 4 CL -+ CO
DD- -QD
CK-
IH -
L --C
CI - -CO
EN-
SI - ~SO
A- Parameter Symbol Typ(ns)f'
B --C Clock Pulse Width tCW 4.1
Input LoadiIl8 CI Setup Time tSC 3.2
Pin Name Factor (tu) CI Hold Time tHC 1.4
D 2 EN Setup Time tSE 3.2
CK,IH 1 EN Hold Time tHE 1.4
L,CL,SI 1 Clear Pulse Width tLW 5.0
EN 1 Clear Release Time tREM 1.2
A-,B CI 2 Clear Hold Time tINH 4.6
Output Driving
Q 18
CO 18
are given bJ'_ the maximum delay multiplier.
AU-SC43-E1 Sheet 1/4 I I Page 13-31
2-239
Cell Name
SC43
Equivalent Circuit
SI
EN
CI
CO
AO~~ ~XAI
CKo-----f-''\...
X)-----+CKI
IH o-----1-r
XCKI Lp-AI
L 0
~~LDI BO--i~ ~BI
Lp-XLDI Lp-XBI
Pa e 13-32
2-240
Cell Name
SC43
XLDI CKI XBI XCKI

--L --L --L --L Cto
D
Q
XCKI BI CKI XQ
XAI XCKI AI
I --L --L --L
XLDI
s Cto
QO
I II
AI CKI "XAI I
XBI
XTG o - t - - - - - - - - t - - - I x>----+
Pa e 13-33
2-241
Cell Name
SC43
))
))
))
~tINH---O
))
))
L
CI ))
EN
))
Pa e 13-34
2-242
SC47
Cell Symbol
I SCAN 4-bit Synchronous Binary Up/Down Counter
I 78
tup tdn
3.60 0.13 3.76 0.15 0.20 4 CK ... Q
,-- 4.90 0.13 6.96 0.07 CK ... CO
DA- r--QA 1.88 0.13 2.35 0.07 DU ... CO
DB - r--QB
DC - -QC
DD- -QD
CK-
1H-
L --<
TH-
EN- =>-- CO
DU-
S1 -
A-
-SO Parameter Symbol ns
l"ypl *
Clock Pulse Width (H) tCWH 8.8
B --< Clock Pause Time (L) tCWL 7.3
'----
EN Setup Time tSE 6.3
EN Hold Time tHE 0.6
Input Loading DU Input Setup Time tSU 7.1
Pin Name Factor (tu) DU Input Hold Time tHU 0.4
D 2 Load Pulse Width tLW 15.4
CK,1H,TH,L 1 Load Release Time tREM 2.9
EN 3 Load Hold Time tINH 12.2
DU,A,B 1
S1 2
Output Driving
Q 18
SO 18
CO 18 * Minimum values for the typical operating condition.
AU-SC47-E1 Sheet 1/4 I I Pal!;e 13-35
2-243
Cell Name
SC47 AO-J>~XAI
Equivalent Circuit Lv-AI
-b4="
I'
,.-----
o
B
v XBI
CO
r-
DU
H>o- v DA 0-----=: r - -
=
QA
EN »-
L$- t-
SI 0--:::
-
=L-l
FFu
QB
~~
=
~FFu
=~1
~~~
QC
- FFu
-
J -L-1
-
r-,
DD 0-----=: r - - QD
v =
=L-
FFu
~ = ~ So
TM
CK~ CKO
IH XCKO
Pa e 13-36
2-244
Cell Name
SC47
D Q
LO
CKO
XCKO
S FFu
XAI •
AI
BI
XBI Qo
TGO XQo
XQO
XCKO Q
oQ
CKO CKO
~
S
DO
LO
CKO XAI XCKO
AI BI
~
TGO
Pa e 13-37
2-245
FUJITSU CMOS GATE ARRAY UNIT CELL SP.ECIFICATION AU Version
Cell Name
SC47
tcw tCWH
CK ,;------....
~~----'I
_ _---..I~~ :,..-+-t...;;;HD~""-I.I"'--_~~
D
____~I~-JI~---JII~----~
L tLW --ot/"-I-------)~ INH -..,r--

tREM
EN
___t_SE_-_-
__-~~-t~-JI~----~~
tsu
DU
I~---~-------------
AU-SC47-El Sheet 4 4 Pa e 13-38
2-246
Adder and ALU Family
Unit Cell Basic

2-249 A1A 1-bit Half Adder 5

2-250 A1N 1-bit Full Adder 8
2-253 A4H 4-bit Binary Full Adder with Fast Carry 48
2-247
2-248
. AlA
Cell Symbol
I I-bit Half Adder Propagation Delay Parameter
I 5
tup tdn
0.98 0.07 1.15 0.03 A -+ S
0.87 0.07 1.17 0.03 B -+ S
0.90 0.07 1.00 0.03 A -+ CO
1.02 0.07 0.92 0.03 B -+ CO
Input Loading
A 2
B 2
Output Driving
CO 36
S 36
A
A B CO S B
L L L L
L H L H
H L L H
H H H L
AU-AIA-E2 I Sheet 1/1 I I Page 14-1
2-249
AIN
Cell Symbol
I I-bit Full Adder Propagation Delay Parameter
I 8
tUI> tdn
2.11 0.13 2.52 0.07 A,B ... S
1.00 0.13 1. 08 0.07 CI ... S
2.39 0.13 1.91 0.07 A,B ... CO
0.82 0.13 0.94 0.07 CI ... CO
B- -CO
A- -8
cl Parameter Symbol Typ(ns)*
Input Loading
Pin Name Factor (.P.u)
A 3
B 3
CI 3
Output Driving
Pin Name Factor (.P.u)
CO 18
S 18
,., Minimum values for the typical operating condition.
A r--.
Ir--.
Inputs Outputs B II S
IV
--+tl
A B CI S CO CI
~>---J»---co
L L L L L
H L L H L
L H L H L
H H L L H
L L H H L I
V
H L H L H
L H H L H
H H H H H
AU-AIN-E2 I Sheet 1/1 I I Page 14-2
2-250
A2N
Cell Symbol
I 2-bit Full Adder Propagation Delay Parameter
I 16
tup tdn
2.28 0.23 2.25 0.11 Al -+ CO
2.19 0.23 2.30 0.11 B1 -+ CO
1. 27 0.23 1.09 0.07 0.10 4 A2 -+ CO
1.18 0.23 1. 09 0.07 0.10 4 B2 -+ CO
2.23 0.23 2.07 0.11 CI -+ CO
B2- ~CO 2.38 0.18 2.20 0.11 Al -+ Sl
A2- 2.38 0.18 2.20 0.11 B1 -+ Sl
B1- c-- S2 0.95 0.18 0.95 0.11 CI -+ Sl
A1- f - - Sl 2.26 0.18 2.20 0.11 Al -+ S2
2.49 0.18 2.36 0.11 A2 -+ S2
2.17 0.18 2.25 0.11 B1 -+ S2
I
CI
2.49
2.21
0.18
0.18
2.36
2.02
0.11
0.11
B2 -+ S2
CI -+ S2
Parameter Symbol Typ(ns)":
Input Loading
A,B 2
CI 2
Output Driving
S 14
CO 14
* Minimum values for the typical operating cqndition.
Function Table
Inputs Outputs
CI =L CI =H
Al B1 A2 B2 Sl S2 CO Sl S2 CO
L L L L L L L H L L
H L L L H L L L H L
L H L L H L L L H L
H H L L L H L H H L
L L H L L H L H H L
H L H L H H L L L H
L H H L H H L L L H
H H H L L L H H L H
L L L H L H L H H L
H L L H H H L L L H
L H L H H H L L L H
H H L H L L H H L H
L L H H L L H H L H
H L H H H L H L I:! H
L H H H H L H L H H
H H H H L H H H H H
AU-A2N-E2 I Sheet 1/2 I Page 14-3
2-251
Cell Name
A2N
Equivalent Circuit
CO
A2
B2 S2
A1
B1
S1
C1
AU-A2N-E2 Pa e 14-4
2-252
A4H
Cell Symbol
I 4-bit Binary Full Adder with Fast CarryDelay Parameter I
Pro~a.station
48
tup tdn
0.95 0.18 1.31 0.11 CI .. Sl
2.12 0.23 2.46 0.11 CI .. S2
2.43 0.23 2.39 0.11 CI .. S3
B4 - -CO 2.51 0.23 2.83 0.11 CI ".. S4
A4 - -54 2.30 0.13 2.57 0.07 CI .. CO
B3 -
A3 - -53 3.05 0.18 2.71 0.11 A1,B1 ... 51
B2 - 2.54 0.23 2.47 0.11 A1,B1 .. S2
A2 - -52 2.74 0.23 3.08 0.11 A1,B1 .. 53
B1- 3.00 0.23 3.14 0.11 A1,B1 .. 54
A1- -51 2.64 0.13 3.03 0.07 A1,B1 .. CO
I
CI
2.47
2.93
0.23
0.23
2.70
2.88
0.11
0.11
A2,B2
A2,B2
..
..
52
S3
2.99 0.23 3.24 0.11 A2,B2 .. S4
3.10 0.13 3.07 0.07 A2,B2 .. CO
Input Loading 2.25 0.23 2.28 0.11 A3,B3 .. 53

Pin Name Factor (Lu) 3.07 0.23 3.23 0.11 A3,B3 .. S4
A 2 3.04 0.13 3.06 0.07 A3,B3 .. CO
B 2
CI 2 2.32 0.18 2.41 0.07 0.10 4 A4,B4 .. S4
2.93 0.13 2.81 0.07 A4,B4 .. CO
Output Driving
Pin Name Factor (Lu)
CO 18
51,S3,S4 14
52 18
Function Table Note :

Input conditions at AI, A2, BI,
OUTPUT B2 and CI are used to
INPUT CI = L CI = H determine outputs 51 and 52
-c'2 ~ L - - -C2 ~ ii - - and the value of the inter-
Al B1 A2 B2 Sl 52 C2 Sl S2 C2 nal carry C2. The values
A3- iiJ- A4- 84- 53- 54- CO- 53- 54- CO- at C2, A3, B3, A4 and B4
are then used to determine
L L L L L L L H L L outputs S3, S4 and CO.
H L L L H L L L H L
L H L L H L L L H L
H H L L L H L H H L
L L H L L H L H H L
H L H L H H L L L H
L H H L H H L L L H
H H H L L L H H L H
L L L H L H L H H L
H L L H H H L L L H
L H L H H H L L L H
H H L H L L H H L H
L L H H L L H H L H
H L H H H L H L H H
L H H H H L H L H H
H H H H L H H H H H
AU-A4H-E3 I Sheet 1/2 I I Page 14-5
2-253
---FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION I "AU" Version
Cell Name I
A4H J
Equivalent
Circuit
r- ,---I'
~
f>---t CO
r--L/
r- rv
~ p--
B4 .--
r-L/
f""'.
A4 W rt-bJ ...f"'\
I'
P'
S4
I
-V
L--r-
-I-
HJ L-.p.-
B3
~ l - I-
~ I-
r-
ltv
t-L/
f""'.
A3 ~ rt-bJ
I'
S3
-.f",
I
P'
-V
f-U
fD ~
t-I-
t-t-
B2 t-
A2
VD
LU_rtY f""'.
f\ S2
I I
t-H::P
l./
Bl
.......
Al
rU I
v :::::.... SI
CI ~:7
AU-A4H-E3 I Sheet 2/2 I .1 P,!&e 14-6
2-254
Data Latch Family
Unit Cell Basic

2-257 YL2 1-bit Data Latch with TM 5

2-261 LTK Data Latch 4
2-263 LTL 1-bit Data Latch with Clear 5
2-265 LTM 4-bit Data Latch with Clear 16
2-268 LT1 S-R Latch with Clear 4
2-270 LT4 4-bit Data Latch 14
2-255
AU Series Unit Cell Ubral)' CMOS Channel/ess Gate Arrays
2-256
YL2
Cell Symbol
I I-bit Data Latch with TM Propagation Delay Parameter I 5
tup tdn
2.19 0.07 2.25 0.03 CK,IH -+ Q
0.93 0.07 1.03 0.03 D -+ Q
D
CK
IH
TM
D Q
Parameter Symbol Typ(ns)#

Input Loading
D 2
CK 1
IH 1
TM 1
Output Driving
Q 36

Note :
The TM terminal must be kept LOW during the SCAN Mode.
Function Table
Input Output
Mode
TM IH CK D Q
L X X D D SCAN
H H X X Q.
H X H X Q. LATCH
H L L D D
AU-YL2-E2 I Sheet 1/2 I Page 15-1
2-257
Cell Name
YL2
Equivalent Circuit
Q
CKI
--L
D
I XCKI
XCKI
--L
I
CKI
XCKI
CKI
----tcw ----l
CK
tSD tHU
t
*
D
I
~tpd.,j
Q
f
AU-YL2-E2 Pa e 15-2
2-258
YL4
Cell Symbol
I 4-bit Data Latch with TM Pro]: agation Delay Parameter I 14
tup tdn
2.67 0.07 2.75 0.03 CK,IH ... Q
0.88 0.07 1.03 0.03 D ... Q
Dl - -Ql
D2 - -Q2
D3 - -Q3
D4 - -Q4
CK -C
IH -
TM--(
Clock Pulse Width (CK) tCW 5.8
Data Setup Time (D) tSD 1.5

Data Hold Time (D) tHD 3.2
Input Loading
D 2
CK 1
IH 1
TM 1
Output Driving
Pin Name Factor (l'.u)
Q 36
"0': Minimum values for the typical operating condition.
Note :
Function Table
InIut OutIJut
Mode
TM IH CK Dn Qn
L X X D D SCAN
H H X X Qno
H X H X Qno LATCH
H L L D D
n =1 - 4
AU-YL4-E2 I Sheet 1/2 I Page 15-3
2-259
Cell Name
YL4
Equivalent Circuit
r----------------,
Q1
CKI
-L
D1
I XCKI
XCKI
-L
I
~------~~--------~
D2 I ~Q2
<>-J I
~----------------~
I ~Q3
D3 <>-J I
~----------------~ ~
I ~
D4 <>-J
L ________________
I
~
XCKI
CKI
- t c w ----
CK
tSD tJID
t
*
D
..... tpd.::!
Q
-f
AU-YL4-E2 Pa e 15-4
2-260
LTK
Cell Symbol
Data Latch
I 4
tup tdn
0.83 0.13 0.92 0.07 D .. Q
1.16 0.13 1. 31 0.07 D .. XQ
1.40 0.13 1.46 0.07 G .. Q
1. 70 0.13 1. 87 0.07 G .. XQ
G
D
=[J=:
G Input Pulse Width tGW 4.0

Input Loading
D 2
G 1
Output Driving
Q 18
XQ 18
.. Minimum values for the typical operating condition .
'(

Function Table
Inputs Outputs
D G Q XQ
X H Qo XQo
H L H L
L L L H
AU-LTK-E2 I Sheet 1/2 I I Page 15-5
2-261
Cell Name
LTI<
Equivalent Circuit
Q
CO
-.L
D XQ
I xco
xco -.L
I
CO
G o----f>o-rf»-- CO
• Lxco
(Casel)
tHD
Q,XQ ____+-____________J
(Case2)
Q,XQ
AU-LTI<-E2 Pa e 15-6
2-262
LTL
Cell Symbol
I I-bit Data Latch with ClearPropagation Delay Parameter I 5
tup tdn
to KCL to KCL KCL2 LD2 Path
1.11 0.13 0.68 0.07 CL ... Q,XQ
0.95 0.13 0.98 0.07 D ... Q
1. 22 0.13 1. 37 0.07 D ... XQ
1.57 0.13 1. 54 0.07 G ... Q
1. 78 0.13 2.01 0.07 G ... XQ
D- - Q
G --C
p---XQ
I
CL


Input Loading
D 2
G 1
CL 1
Output Driving
Q 18
XQ 18
~': Minimum values for the typical operating condition.
Funcion Table
Inputs Outputs
CL D G Q XQ
L X H L H
H X H Qo XQo
H H L H L
H L L L H
AU-LTL-E2 I Sheet 1/2 I I Page 15-7
2-263
Cell Name
LTL
Equivalent Circuit
CL~-----'
GO Q
D XQ
I
XGO
G O-~>---t"-~------:
GO
GO
XGO
Ell Definition of Parameters
(Case 1) (Case 3)
I<---- tGW --->
--4- tLW-Y-
G
CL 1"---"1
D
tHD
.......-. K=
Note 1,: G input must be high level
Q,XQ --
'\....
at the time this latch
is cleared.
tpd
(Case 2)
--.,;--"'\.
Q,XQ ----t-----..../
Pa e 15-8
2-264
LTM
Cell Symbol
I 4-bit Data Latch with ClearPropagation Delay Parameter I 16
tup tdn
1.23 0.13 0.78 0.07 CL ... P,N
0.98 0.13 1.03 0.07 D ... P
1.28 o 13 1.43 0.07 D ... N
2.09 0.13 1.96 0.07 G ... P
DA - -PA 2.19 o 13 2.52 0.07 G ... N
DB - D-NA
DC - -PB
DD - D-NB
'-- PC
G --<:
P-NC
r-- PD
P-ND
Symbol
Y Parameter
G Input Pulse Width tGW
Typ(ns)'"
4.0
CL

Input Loading
Pin Name Factor (!u)
D 2
G 1
CL 4
Output Driving
Pin Name Factor (!u)
P 18
N 18
Function Table
Inputs Outputs
CL D G P N
L X H L H
H X H Po No
H H L H L
H L L L H
AU-LTM-E2 I Sheet 1/3 I Page 15-9
2-265
Cell Name
LIM
Equivalent Circuit
r--~------------~--------,
I
CL PA
GO
--L
NA
DA
I
XGO
XGO
--L
I
GO
~------------------------~
, - - 0 PB
DB I
I L-o NB
~------------------------~
, - - 0 PC
DC I
L-o NC
~------------------------~
, - - 0 PD
DD C>-----i I
IL _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ L-o
~
ND
G~GO
• LXGO
Pa e 15-10
2-266
Cell Name
LTM
(Case1)
P,N
(Case2)
P,N
(Case3)
-tLW-
CL
--------
*G
P,N
<-tpd ...
Note *: G input must be high level at the time this latch is cleared.
Pa e 15-11
2-267
LT1
Cell Symbol
I S-R Latch with CLEAR Propagation Delay Parameter
I 4
tup tdn
1.41 0.13 0.71 0.07 S ... Q,XQ
1.25 0.13 0.83 0.07 R ... Q,XQ
1.15 0.13 0.74 0.07 CL ... Q,XQ
-
S --C I--Q
R --C P--- XQ
CL
Set Pulse Width tSW 4.0
Reset Pulse Width tRW 4.0
Input Loading
S 1
R 1
CL 1
Output Driving
Q 18
XQ 18
Function Table
Inputs Outputs
CL S R Q XQ
L H H L H
H H H Q. XQ.
H H L L H
H L H H L
H L L Inhibited
AU-LTl-E2 I Sheet 1/2 I I Page 15-12
2-268
Cell Name
LTl
Equivalent Circuit
s XQ
R Q
CL
Q, XQ
s
tJi
tpd
Q, XQ
CL
tJi
tpd
Q,XQ
AU-LTl-E2 Pa e 15-13
2-269
LT4
Cell Symbol
I 4-bit Data Latch Pro.agation Delay Parameter
I 14
tup tdn
2.00 0.13 1.83 0.07 G ... P
2.00 0.13 2.44 0.07 G ... N
0.84 o 13 0.95 0.07 D ... P
1.12 0 ..13 1.28 0.07 D ... N
DA - -PA
DB - J- NA
DC - -PB
DD - J- NB
-PC
G -< J - NC
-PD
J-ND


Input Loading
Pin Name Factor (.I'.ut
D 2
G 1
Output Driving
Pin Name Factor J.I'.u)
P 18
N 18
..,: Minimum values for the typical operating condition .
Function Table
Inputs Outputs
D G P N
H H Po No
L H Po No
H L H L
L L L H
AU-LT4-E2 I Sheet 1/3 I I Page 15-14
2-270
Cell Name
LT4
Equivalent Circuit
r---------------------~
GO PA
~
DA NA
XGO
I
GO
~---------------------4
I - i - - - O PB
DB~ - i - - - O NB
~---------------------4
DC o-------!- 0 PC
I 0 NC
~---------------------4
I 0 PD
DD~ I 0 ND
L _____________________ ~
GO)------j~-.,-------1~)-----:~:
AU-LT4-E2 Pa e 15-15
2-271
'FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION ~ AU Version
Cell Name I
LT4 I
(Case 1)
- tGW ----<
G
D ,---
~
'--
tHD
P,N ~
"-
~tpd
(Case 2)
D r-
lflii I<- tSD-> I<-tHD->

~
P,N
I<- tpd--
K=
AU LT4-E2 I Sheet 3/3 I I Page 15 16
2-272
Shift Register Family
Unit Cell Basic

2-275 FS1 4-bit Serial-in Parallel-out Shift Register 18
2-277 FS2 4-bit Shift Register with Synchronous Load 30
2-279 FS3 4-bit Shift Register with Asynchronous Load 34
2-282 SR1 4-bit Serial-in Parallel-out Shift Register with Scan 36
2-273
AU Series Unit Cell Ubrary CMOS Channel/ess Gate AITBYs
2-274
----YUjITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
FS1
Cell Symbol
I 4-bit Serial-in Parallel-out Shift Register
I 18
tup tdn
1. 94 0.13 2.51 0.07 0.10 4 CK -+ Q
SDDQA
CK QB
QC
QD
Parameter Symbol Typ(ns)"

SD Setup Time tSSD 0.5

SD Hold Time tHSD 0.2
Clock I C S 16 iu tCWL''''; 4.7

Input Loading Pause I 16 < C S 32 iu tCWU"', 6.8
Pin Name Factor (iu) Time I 32 < C ;;; 48 iu tCWL""', 8.8
SD 1
CK 1 * Minimum values for the typical operating con-
dition. The values for the worst case operating
condition are given by the maximum delay
multiplier.
Output Driving
Pin Name Factor (iu) M, The value of tCWL depends on the load(C)
r-~~Q~~~-t~~~176~~--~ connected to the output terminals, QA, QB, QC and
QD.
Function Table
Inputs
SD I CK QA I QB QC I QD
Note: 'SD = H or L
'QAn, QBn and QCn are levels of

QA, QB and QC respectively,
before the falling edge of CK, i.e.
1 bit shift by the falling edge of CK.
AU-FS1-E2 I Sheet 1/2 I I Page 16-1
2-275
Cell Name
FS1
Equivalent Circuit
i-~- -------------- --~ ----------l IIi

QA QB QC QD
T T
I I
CKO XCKO
CKO XCKO
.-L .-L
1
1
1 I I: 11
~ )_ P! 1: _____ ~~~~ _________________ ~~~ _________ 1 __ _.L ___ 1 ___ ~
CK~CKO
• LXCKO
I<--- tcw tCWL-

CK r-
tHSD
<--tss
SO
I<- tpd-
Q
AU-FS1-E2 Pa e 16-2
2-276
FS2 -' 4-bit Shift Register with Synchronous Load
Cell SYJIlbol Pro~agation Delay Parameter
I 30
tup tdn
1.86 0.13 2.51 0.07 0.10 4 CK ... Q
PA- -QA
PB - '-QB
PC - i--QC
PD - r--QD
SD -
CK --<
L- Parameter Symbol Typ(ns)'~


P Setup Time tSP 2.9

P Hold Time tHP 1.2
Input Loading
Pin Name Factor (Rou) Clock I C ::: 16 Rou tCWUd, 4.7
CK 1 Pause I 16 < C 5 32 Rou tCWL*'~ 6.8
SD 1 Time I 32 < C 548 Rou tCWL1"~ 8.8
L 1
....: Minimum values for the typical operating con-
P 1
dition. The values for the worst case operating
Output Driving condition are given by the maximum delay
Pin Name Factor (Rou) multiplier.
Q 16
",'n': The value of tCWL depends on the 10ad(C)
connected to the output terminals, QA, QB, QC and
QD.
Function Table
·Inputs Out~uts
SD L P CK QA QB QC QD
SD L X ~ SD QAr QBr QC~
X H P ~ PA PB PC PD
Note: ·SD =H or L
·QAn, QBn and QCn are levels of

QA, QB and QC respectively,
.p represents PA, PB, PC and PD .
AU-FS2-E2 Sheet 1/2 I Page 16-3
2-277
Cell Name
FS2
Equivalent Circuit
PA
i-------------~o -------------------~ --------------Tr

QA PB
r+iTrIi
PC PD
I
SD I
I
I
I
I
CKO XCKO
CKO XCKO
-L -L
I I I I :
Ll,. _bJj;__________________ ~~~~ _________________ ~~~ _________ .L ___ .:. ___ .:. ___ ~
CK o-C>t:x::
10-- tcw tCWL-

CK .r-
tHSD
-tss
SD
" r = t s p - i<-tHP->
X
P
f
L CtSL
'i..
tHL
-tpd~{
Q
f
AU-FS2-E2 Pa e 16-4
2-278
FS3 14-bit Shift Register with Asynchronous Load
Cell Symbol ProFagation Delay Parameter
I 34
tup tdn
1.83 0.14 1. 70 0.09 CK ... Q
3.71 0.14 2.80 0.09 L ... Q
1. 63 0.14 2.42 0.09 P ... Q
PA- -QA
PB - -QB
PC - -QC
PD - -QD
SD-
CK-
L --C Parameter Symbol Typ(ns)'~
Load Pulse Width tLW 5.0

Input Loading P Setup Time tSP 0.3

Pin Name Factor (R.u) P Hold Time tHP 1.9
CK 2
SD 2
L 1
P 2
Output Driving
Q 18

Function Table
Inputs Output
L P SD CK Q
L L X X L
L H X X H
H X L t L
H X H t H
2-279
Cell Name
FS3
Equivalent PA QA PB QB PC QC PD QD
Circuit
SDo------\ FFO FFO 1 - - - - 1 FFO 1 - - - - - 1 FFO
Equivalent Circuit of FFO
P Q
DO QO
DO
CKO
XCKO
XLDO
LOO
CKO XCKO
AU-FS3-E3 Pa e 16-6
2-280
Cell Name I
FS3 I
CK rI"
tcw ---->
~tCWH
J I~"------
SD
tSSD tHSD
------~~tLW-----1,r--------
L
1
----------~I/------+-~v___
P _ _ _ _ _ _ _ _ _ _-J~_ _ _ _ -+__ -J~
2-281
SRI
Cell Symbol
14-bit Serial-in Parallel-out Shift Register with SCAN
I 36
tup tdn
2.62 0.07 2.70 0.06 0.09 7 CK ... Q
2.07 0.07 2.32 0.06 0.09 7 B ... Q
;---
D- -QA
-QB
CK - -QC
IH - -QD
SI -
A-
B -C
'---

Clock Pause TIme tCWH 4.5
Data Hold Time otHD 1.2
Input Loading
Pin Name Factor _Ctu) .
D 1
CK 1
IH 1
SI 1
A,B 1
Output Driving
Q 36

AU-SRI-E2 Sheet 1/3 I Page 16-8
2-282
Cell Name
SR1
QA QB QC QD
D DO QO
SDO SQO
SI CLK
XCLK
A:CK
XACK
BCK
XBCK
FFO FFO FFO FFO
CLK XBCK XCLK

)()------o QO
-L -L -L
DO ~~-~ )()-~----oSQO
I
XCLK
XACK XCLK ACK CLK
-L -L -L
SDO
I II I
ACK CLK XACK XCLK
CLK
CK
IH I
XCLK XBCK
B~BCK
~XBCK
Pa e 16-9
2-283
Cell Name I
SR1 I
tcw --ot=~WHIL::~
CK
}'---..J
tSD-o ...tHD""
D
AU-SRI-E2 I Sheet 3/3 1 I Page 16-10
2-284
Parity Generator/Selector/Decoder Family
Unit Cell Basic

Parity Generators/Checkers
2-287 PES 5-bit Even Parity Generator/Checker 12
2-288 P05 5-bit Odd Parity Generator/Checker 12
2-289 PE8 8-bit Even Parity Generator/Checker 18
Data Selector
2-293 P24 4-wide 2:1 Data Selector 12
Decoders
2-294 DE2 2:4 Decoder 5
2-295 DE3 3:8 Decoder 15
2-297 DE4 2:4 Decoder with Enable 8
2-298 DES 3:8 Decoder with Enable 30
Selectors
2-300 T2B 2:1 Selector 2
2-301 T2C Dual 2:1 Selector 4
2-303 T2D 2:1 Selector 2
2-304 T2E Dual 2:1 Selector 5
2-305 T2F 2:1 Selector 8
2-307 T5A 4:1 Selector 5
2-309 V3A 1:2 Selector 2
2-310 V3B Dual 1:2 Selector 4
Magnitude Comparator
2-311 MC4 4-bit Magnitude Comparator 42
2-285
AU Series Unit Cell Ubrary CMOS Channelless Gale Arrays
2-286
PES
Cell Symbol
I 5-bit Even Parity Generator/Checker
I 12
tup tdn
2.10 0.07 2.73 0.03 A'" X
2.10 0.07 2.62 0.03 B ... X
3.31 0.07 3.87 0.03 C ... X
D-
A
B1
H2 X
C1
C2
Input Loading
A 2
H 2
C 2
Output Driving
X 36 I
;, Minimum values for the typical operating condition.
B1 _If""'.
Hnput X B2 II
1.../
Odd L
X
Even H
C1 Ir---
r-,.
C2 JL 1.../
AU-PES-E21 Sheet 1/11 Page 17-1
2-287
P05
Cell Symbol
I 5-bit Odd Parity Generator/Checker
Propag;ation Delay Parameter
I 12
tup tdn
2.11 0.07 2.46 0.03 A -> X
2.29 0.07 2.43 0.03 B -> X
3.35 0.07 3.65 0.03 C -> X
fi'
B1
B2
C1
C2
Parameter SYl1lbol Typ(ns)*
Input Loading
Pin Name Factor lR.u)
A 2
B 2
C 2
Output Driving
X 36

B1 r--.
Hnput X B2
"
4n
1../
Odd H
X
Even L
C1 Ir-.
r--.
C2 II
11../
AU-P05-E2 Sheet 1/1 I I Page 17-2
2-288
PE8
Cell Symbol
I 8-bit Even Parity Generator/Checker
ProFagation Delay Parameter
I 18
tup tdn
3.08 0.13 3.47 p.07 A -+ X
3.15 0.13 3.54 0.07 B -+ X
3.15 0.13 3.52 0.07 C -+ X
3.22 0.13 3.59 0.07 D -+ X
Al -
A2 -
B1 -
B2 - p-- X
C1-
C2 -
01-
D2 -
Input Loading
A 2
B 2
C 2
D 2
Output Driving
X 18

Al r-...
l:input X A2 II r-...
1../
r-...
II
Odd L B1 1../
B2 II
1../
Even H X
C1 I"
C2
D1
"1../
r-..
II
r-...
II
L./
D2 1../
AU-PE8-E2 I Sheet 1/1 I Page 17-3
2-289
P08
Ce1l Symbol
I 8-bit Odd Parity Generator/CheckerPro~agation Delay Parameter
I 18
tup tdn
3.02 0.13 3.43 0.07 A'" X
3.09 0.13 3.50 0.07 B ... X
3.10 0.13 3.37 0.07 C ... X
3.17 0.13 3.41 0.07 D ... X
Al-
A2 -
Bl -
B2 - -X
Cl-
C2 -
Dl-
D2 -
Input Loading
A 2
B 2
C 2
D 2
Output Driving
Pin Name Factor C£u)
X 18
'(

Al If'.
Hnput X A2 JL
IV r----
~
Odd H BI r----
B2 II
L./
Even L X
r----
I~
C1
C2 II
IV
D1 r---- l./
D2 +b
AU-P08-E2 I Sheet 1/1 I I Page 17-4
2-290
PE9
Cell Symbol
1 9-bit Even Parity Generator/Checker
I 22
tup tdn
4.23 0.13 4.57 0.07 A'" X
A1-
A2 -
A3 -
A4 -
A5 - ~X
.A6 -
A7 -
A8 -
A9 -
Parameter Symbol Typ(ns»"
Input Loading
A 2
Output Driving
X 18


A3
Hnput X A8
l./
A9
Odd L r-..
A1 II
A2 L/
Even H
X
A4
A5
A6
A7
AU-PE9-E2 I Sheet 1/1 I Page 17 5
2-291
P09
Cell Symbol
1 9-bit Odd Parity Generator/Checker
ProFagation Delay Parameter
I 22
tup tdn
4.16 0.13 4.57 0.07 A -+ X
Al -
A2 -
A3 -
A4 -
AS - ,-- X
A6 -
A7 -
A8 -
A9 -
Input Loading
A 2
IfII
Output Driving
X 18

* The values forthe worst case operating condition

A3
Hnput X A8
L/
A9
Odd H r--
Al II
A2 L./
Even L
X
A4
I
AS
A6
A7
AU-P09-E2 I Sheet 1/1 I Page 17-6
2-292
P24
Cell Symbol
I 4-wide 2:1 Data Selector Propagation Delay Parameter I 12
tup tdn
0.76 0.07 0.67 0.03 A .. X
0.93 0.07 0.78 0.03 B .. X
0.65 0.07 0.76 0.03 SA .. X
0.80 0.07 0.87 0.03 SB .. X
Al - -
B1 - Xl
A2 - - X2
B2 -
A3 - -
B3 - X3
A4 - -
B4 - X4
SA -
SB - Parameter Symbol Typ(ns)'"
Input Loading
A 1
B 1
S 4
Output Driving
X 36
,', Minimum values for the typical operating condition,

are given by~ the maximum delay multiplier.
Al
SA SB Xn .--
Bl Xl
L L L r-
H L An A2
L H Bn ~r-
H H An+Bn B2 X2
~
A3
~-
B3 X3
~
A4
~-
B4 X4
~
SA -
SB -
AU-P24-E2 I Sheet 1/1 I I Page 17-7
2-293
DE2
Cell Symbol
I 2:4 Decoder Pro~aR:ation Delay Parameter
I 5
tup tdn
0.63 0.13 0.87 0.11 A ... XO
0.71 0.13 0.78 0.11 A ... Xl
0.30 0.13 0.36 0.11 A ... X2.X·
Afixe
0.71 0.13 0.78 0.11 B ... XO
0.23 0.13 0.45 0.11 B ... X1,X
0.63 0.13 0.87 0.11 B ... X2
Xl
X2
B X3
Input Loading
A 3
B 3
Output Driving
X 18
Function Table
Infuts Outputs
A B X3 X2 Xl XO A XO
~
L L H H H L
L H H H L H
L Xl
H H L H H
H H L H H H
X2
~
B {>o-~
X3
AU-DE2-E2 I Sheet 1/1 I I Page 17-8
2-294
FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION J AU" Version
DE3
Cell Symbol
I 3:8 Decoder Propagation Delay Parameter
I 15
tup tdn
1.15 0.13 1. 34 0.15 A'" XO-X3
1.95 0.13 1. 95 0.15 A ... X4-X7
1.07 0.13 1. 38 0.15 B ... XO-X3
1.87 0.13 1.99 0.15 B ... X4-X7
r-XO 0.99 0.13 1.43 0.15 C ... XO-X3
A- r--X1 1. 79 0.13 2.64 0.15 C ... X4-X7
r--X2
r-X3
B-
r--X4
r--X5
C- r--X6
r-X7
Parameter Symbol Typ(ns)1,
Input Loading
A 1
B 1
C 1
Output Driving
X 14

Function Table
Inputs Outputs
A B C XO Xl X2 X3 X4 X5 X6 X7
L L L L H H H H H H H
L L H H L H H H H H H
L H L H H L H H H H H
L H H H H H L H H H H
H L L H H H H L H H H
H L H H H H H H L H H
H H L H H H H H H L H
H H H H H H H H H H L
2-295
Cell Name
DE3
Equivalent Circuit
A
XO
Xl
B
X2
- - ( ) X3
X4
C
X5
X6
X7
AU-DE3-E2 Pa e 17-10
2-296
DE4
Cell Symbol
I 2:4 Decoder with Enable Proj:agation Delay Parameter
I 8
tup tdn
0.95 0.13 1.17 0.15 G ... X
0.69 0.13 0.89 0.15 A'" X
0.86 0.13 0.91 0.15 B ... X
A
B ~xo .
Xl
X2
G X3
Input Loading
A 3
B 3
G 1
Output Driving
X 14

G A B X3 X2 Xl XO G
H X X H H H H A
~xo
L L L H H H L
L
L
L
L
H
H
H
L
H
H
H
L
H
L
H
L
H
H
H
H
H
-=!)-- Xl
B
f--=!)--X2
~X3
2-297
DE6
Cell Symbol
I 3:8 Decoder with Enable Propagation Delay Parameter
I 30
tup tdn
2.44 0.13 4.76 0.07 G .. X
2.31 0.13 2.63 0.07 S .. X
G1 - I--XO
G2 - I--X1
G3 - 1--- X2
f---- X3
S1-
f---- X4
S2 - I--X5
S3 -
I--X6
t--X7
Input Loading
G 1
S 1
Output Driving
X 18

Function Table
G1 G2+G3 S3 S2 Sl X7 X6 X5 X4 X3 X2 Xl XO
X H X X X H H H H H H H H
L X X X X H H H H H H H H
H L L L L H H H H H H H L
H L L L H H H H H H H L H
H L L H L H H H H H L H H
H L L H H H H H H L H H H
H L H L L H H H L H H H H
H L H L H H H L H H H H H
H L H H L H L H H H H H H
H L H H H L H H H H H H H
AU-DE6-E2 I Sheet 1/21 Page 17-12
2-298
Cell Name
DE6
Equivalent Circuit
Gl
XO
G20--------1~~-+----------~--~
G3 0---------+-7
Xl
X2
X3
X4
Sl0-------1
X5
X6
X7
S30-------1
AU-DE6-E2 Pa e 17-13
2-299
T2B
Cell Symbol
2:1 Selector
I 2
tup tdn
0.42 0.13 0.63 0.07 A,B .. X
0.49 0.13 0.79 0.07 S .. X
tD-x
S2
Input Loading
A,B 2
S 1
Output Driving
X 18
')': Minimum values for the typical operating condition.
Inputs Output -L
A B Sl S2 X
A
L X L H H
H X L H L
X
X
L
H
H
H
L
L L
H E- -[> X
H L L L Inhibit
B
H L H H Inhibit
L H L L Inhibit
L H H H Inhibit
Sl
-r
S2
AU-T2B-E2 I Sheet 1/1 I I Page 17-14
2-300
T2C
Cell Symbol
I
Dual 2:1 Selector
I 4
tup tdn
0.41 0.13 0.62 0.07 A,B -+ X
0.54 0.13 0.83 0.07 S -+ X
Sl S2
11
A1- P--xo
A2-
B1-
B2- P--X1
Input Loading
A,B 2
S 2
Output Driving
X 18

Function Table
Inputs Outputs
A1,B1 A2,B2 Sl S2 XO Xl
L X L H H H
H X L H L L
X L H L H H
X H H L L L
L H L L Inhibit Inhibit
H L L L Inhibit Inhibit
L H H H Inhibit Inhibit
H L H H Inhibit Inhibit
AU-T2C-E2 I Sheet 1/2 I Page 17-15
2-301
Ce1l Name
T2C
Equivalent Circuit
Al
)0----0 XO
A2 0---+-----1
Bl
X>----o Xl
B2 0---+-----1
SI
52
AU-T2C-E2 Pa e 17-16
2-302
T2D
Cell Symbol
2:1 Selector
I 2
tup tdn
0.50 0.15 0.56 0.10 A,B ... X
0.54 0.15 0.41 0.10 S ... X
t{}-x
S2
Input Loading
A,B 1
S 1
Output Driving
X 14
oJ: Minimum values for the typical operating condition.
Funct"ion Table Equivalent Circuit
In~uts Output -L
A B 81 82 X
L X L H H
A
~
H X L H L
X
X
L
H
H
H
L
L
H
L
=:E- f---ox
~
L H L L Inhibit
H H H Inhibit B
L
H L L ·L Inhibit
H L H H Inhibit
S1
I
82
AU-T2D-E2 I Sheet 1/1 I I Page 17-17
2-303
T2E
Cell Symbol
I Dual 2:1 Selector Propagation Delay Parameter
I 5
tup tdn
0.43 0.13 0.43 0.08 0.11 4 A,B ... X
1. 31 0.13 1.30 0.08 0.11 4 S ... X
A1-
::>--XO
A2 -
Bl -
::>--X1
B2 -
S -
Input Loading
A,B 2
S 1
Output Driving
X 18
Equivalet Ciruit
---:L
Al
~
--r- XO
--L-
A2
~
Bl
~
--r- Xl
--'--
B2
S
I
AU-T2E-E2 I Sheet 1/1 I

Lv Page 17-18
2-304
T2F
Cell Symbol
I 2:1 Selector ProJagation Delay Parameter
I 8
tup tdn
0.43 0.13 0.43 0.08 0.11 4 A,B,
C,D ... X
1.31 0.13 1.30 0.08 0.11 4 S .. X
Al -
A2 -
cr-- XO
B1 -
B2 - P--X1
C1 -
C2 - P--X2
D1 -
D2 - P--X3
S -
Parameter Symbol Typ(ns)#
Input Loading
A,B,C,D 2
S 1
Output Driving
X 18

AU-T2F-E2 I Sheet 1/2 I I Page 17-19
2-305
Cell Name
T2F
Equivalent Circuit
Al
XO
A2
B1
---{)o--o Xl
B2
Cl
X2
C2
D1
X3
D2
AU-T2F-E2 Pa e 17-20
2-306
T5A
Cell Symbol
14:1 Selector
I 5
tup tdn
0.80 0.19 0.80 0.13 A,B .. X
0.80 0.19 0.67 0.13 81-4 .. X
Sl 02 S3 S4 0.43 S5-6 .. X
0.45 0.19 0.13
A1_
1111
A2_
B1_ P--x
B2_
il
S5 86
Input Loading
A,B 1
8 1
Output Driving
X 9

Function Table
Inputs OutEUt
A1 A2 B1 B2 Sl 82 83 84 85 S6 X
L L H L H H
H L H L H L
L H L L H H
H H L L H L
L L H H L H
H L H H L L
L H L H L H
H H L H L L
A1~A2 .. 81=82 or S5=S6 Inhibit

B1~B2 .. 83=84 or 85=86 Inhibit
A1,A2~B1,B2 or 85=S6 Inhibit
AU-T5A-E2 I Sheet 1/2 I I Page 17-21
2-307
Cell Name
T5A
Equivalnt Circuit
Al
A2
SI
S2
x
S4
S3
Bl
B2
S5
S6
AU-T5A-E2 Pa e 17-22
2-308
V3A
Cell Symbol
1:2 Selector
Pro~agation Delav Parameter
I 2
tup tdn
0.50 0.15 0.56 0.10 A .. X
0.44 0.15 0.36 0.10 S .. X
A
Sl
S2
=CJ=XO Xl
Parameter Svmbo1 Tvp(ns)'~
Input Loading
A 1
S 1
Output Loading
X 1
Output Driving
X 14 ,', Minimum values for the typical operating condition.
Inputs Outputs I=L

~~xo
A Sl S2 XO I Xl
L L L Inhibit
L H L X H A o-{>o- =r-
L
L
L
H
H
H
H X
'--fr--o Xl
Inhibit ~
H L L Sl
H H L X L S2
H L H L X
H H H Inhibit
AU-V3A-E2 I Sheet 1/1 I Page 17-23
2-309
FUJITSU CMOS GATE ARRAY UNIT'CELL SPECIFICATION I "AU" Version
V3B
Cell Symbol
Dual 1:2 Selector
I 4
tup tdn
0.51 0.15 0.61 0.10 A,B .. X
0.46 0.15 0.39 0.10 S .. X
'Dxo
B
Sl
S2
Xl
X2
X3
Input Loading
A 1
B 1
S 2
Output Loading
X 1
Output Driving

I-l-
A~~~
Inputs Outputs
A,B Sl S2 XO, X2 I Xl X3 XO
L L L Inhibit
L H L X H
~-[} Xl
L L H H X
L H H
Inhibit
H L L
-=EJ X2
+~
H H L X L B
H L H L X
X3
H H H Inhibit
Sl -=r
S2
AU-V3B-E2 I Sheet 1/1 I I Page 17-24
2-310
Cell Name _L Function I Number of BC
MC4
Cell Symbol
I 4-bit Magnitude ComparatorPropagation Delay Parameter I 42
tup tdn
4.23 0.23 5.06 0.07 0.09 4 A ... OS
4.31 0.23 4.97 0.07 0.09 4 B ... OS
1. 89 0.23 2.23 0.07 0.09 4 IE ... OS
A3 B3:= 1.55 0.23 1.93 0.07 0.09 4 IG ... OS
A2 B2:= 4.15 0.23 5.23 0.07 0.09 4 A ... OG
A1 B1:= 4.22 0.23 5.14 0.07 0.09 4 B ... OG
AD BO:= 1.80 0.23 2.39 0.07 0.09 4 IE ... OG
1.71 0.23 1.85 0.07 0.09 4 IS ... OG
4.55 0.13 3.49 0.07 0.10 4 A ... OE
IG- f-- OG
4.47 0.13 3.56 0.07 0.10 4 B ... OE
IE- f-- OE
IS- 1.71 0.13 1.15 0.07 0.10 4 IE ... OE
f-- OS
Input Loading
A 3
B 3
IE 1
IG 1
IS 1
Output Driving
OE 18
OG 10
OS 10 * Minimum values for the typical operating condition.
Function Table
Comparing Inputs Cascading Inputs Outputs

IG IS IE OG OS OE
A3,B3 A2,B2 Al,Bl AO,BO (A>B) (A<B) (A=B) (A>B) (A<B) (A=B)
A3>B3 X X X X X X H L L
A3<B3 X X X X X X L H L
A3=B3 A2>B2 X X X X X H L L
A3=B3 A2<B2 X X X X X L H L
A3=B3 A2=B2 A1>B1 X X X X H L L
A3=B3 A2=B2 A1<B1 X X X X L H L
A3=B3 A2=B2 A1=B1 AO>BO X X X H L L
A3=B3 A2=B2 A1=B1 AO<BO X X X L H L
A3=B3 A2=B2 A1=B1 AO=BO X X H L L H
A3=B3 A2=B2 A1=B1 AO=BO H L L H L, L
A3=B3 A2=B2 A1=B1 AO=BO L H L L H L
A3=B3 A2=B2 A1=B1 AO=BO H H L L L L
A3=B3 A2=B2 A1=B1 AO=BO L L L H H L
AU-MC4-E2 I Sheet 1/2 I I Page 17-25
2-311
FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION "AU Version
Cell Name I
MC4 I V-
>-
Equivalent
A3
B3
y
y ={}- Circuit
i"'\
U OG
i"'\
~
~
r-l../
~~
A2
B2 D- f-
f- f-
i"'\
- r--
p-
IS l../
i"'\
IE OE
~ -
-l../
IG
-
i"'\
~
P-
Al ~
B1 I ../
~
'-- - - - . "
../
OS
i"'\
U
W-
~
AD
BD
AU-MC4-E2 Sheet 2/2 I

V- I Page 17-26
2-312
CMOS Channelless Gate Arrays AU Series Unit Cell Library
Bus Driver Family
Unit Cell Basic

2-315 B11 1-bit Bus Driver 5
2-319 B12 1-bit Block Bus Driver 7
2-313
2-314
Bll
Cell Symbol
I 1-bit Bus Driver Propagation Delay Parameter
I 5
tup tdn
1.15 0.06 1.1;;. 0.04 A .. X
1.30 0.06 1.30 0.04 C" X
AO
C
=[JXQ
Input Loading
A 1
C 1
Output Loading
X 1
Output Driving
X 36

Equivalent Circuit
Co
~
AO XO
T
Co
~
C Co
Co
AU-Bll-E1 I Sheet 1/1 I Page 18-1
2-315
B21
Cel1 Symbol
I 9
tup tdn
1.15 0.06 1.15 0.04 A ... X
2.15 0.06 1. 90 0.04 C'" X
AO
Al
C
=[J=xo Xl
Input Loading
A 1
C 1
Output Loading
Ell X
Pin Name
1
Output Driving
Factor (.eu)
X 36

Equivalent Circuit
Co
~--------------:i:-i
AO
,,, ,,, XO
, ,
~--------------:t:-~
Co
r------------------,,
Al ---', __________________ J,
~ Xl
C ~co
Co
AU-B21-E1 I Sheet 1/1 I J Page 18-2
2-316
B41
Cell Symbol
I 4-bit Bus Driver
Pro): aKation Delay Parameter
I 17
tup tdn
to
1.15
3.50
KCL
0.06
0.06
to
1.15
2.90
KCL
0.04
0.04
KCL2 CDR2
..
Path
A X
C ... X
AO - -XO
A1- c--X1
A2 - i--X2
A3 - i--X3
C --<
Input Loading
A 1
C 1
Output Loading
X 1
Output Drivl.ng
X 36

are .e;iven by_ the maximum delay multiplier.
Equivalent Circuit
Co
i--------------~-~
,,, ,,
AO
, ,, Xo
~--------------~-~
Co
r------------------,
, ,
A1 ---,L __________________ J, Xl
r------------------,
A2 ---,,L __________________ J,, X2
r------------------,
A3
---',L __________________ J,, X3
C ~co
Co
AU-B41-E1 I Sheet 1/1 I I Page 18-3
2-317
B81
Cell Symbol
I 33
tup tdn
LIS 0.06 LIS 0.04 A .. X
6.70 0.06 S.SO 0.04 C .. X
AO - -xo
A1- '-Xl
A2 - i--X2
A3 - i--X3
A4- r-X4
AS - r--- xs
A6 - I--X6
A7 - I--X7
C--( Parameter Symbol Typ{ns)'"
Input Loading
A 1
C 1
Output Loading
Pin Name Factor Jiu)
til X
Pin Name
1
Output Driving
Factor (iu)
X 36
Minimum values
* The for the typical operating condition.
values for the worst case operating condition
Equivalent Circuit
Co
i--------------~-i
I I
I I
AO I I XO
I I
~--------------:t:-J
CO
Al r------------------,
- - - - - - l __________________ Xl
~
------~==================~
X2
A2
A3 ------~==================~
X3
A4 ------~==================~
X4
AS ------~==================~
XS
A6 ------~==================~
X6
A7 ------~==================~
X7
C ~co
Co
AU-B81-El I Sheet 1/1 I I Page 18-4
2-318
.--
B12
Ce11 Symbol
I 1-bit Block Bus Driver Propagation Delay Parameter
I 7
tup tdn
1.15 0.04 1.95 0.02 A ... X
1.45 0.04 2.45 0.02 C ... X
AO
C
=a- xo
Input Loading
A 2
C 1
Output Loading
X 2
Output Driving
X 72

Equivalent Circuit Note : This cell is for inter-block bus

under chip level.
AO I I
Co
Co
Lp. L/
XO
c~co
Co
AU-B12-E1 I Sheet 1/1 I I Page 18-5
2-319
FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION I "AU" Vers.1. ......
B22
Cell Symbol
I 2-bit Block Bus Driver ProJ;agation Delay Parameter
I 13
tup tdn
1.15 0.04 1.95 0.02 A+X
1.60 0.04 2.80 0.02 C+ X
AO
Al
C
=[J=xo Xl
Input Loading
A 2
C 1
Output Loading
X 2
Output Driving
X 72


under chip level.
AO I I
Co
~
XO
Co
A1~ ~ Xl
C~ Co
Co
AU-B22-El I Sheet 1/1 I I Page 18-6
2-320
FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION I 'AU Version
B42
Cell Symbol
I 4-bit Block Bus Driver Pro~agation Delay Parameter
I 25
tup tdn
1.15 0.04 1.95 0.02 A-+X
2.00 0.04 3.10 0.02 C-+X
AO - r--- XO
AI- r--- Xl
A2 - r--- X2
A3 - r--- X3
C --<
Parameter Symbol Typ(nst*
Input Loading
A 2
C 1
Output Loading
X 2
Output Driving
X 72

under chip level.
AO
1 J
Co
~ XO
Co 1../
Al-1 ~ Xl
A2-1 ~ X2
A3-1
~ X3
C~ Co
Co
AU-B42-El I Sheet 1/1 I Page 18-7
2-321
2-322
Clip Cell Family
Unit Cell Basic

2-325 zoo 0 Clip o

2-326 Z01 1 Clip o
2-323
AU Series Unit Cell Ubrary CMOS ChannelJess Gate Arrays
2-324
ZOO
Cell Symbol
I o Clip
I 0
tup tdn
!
Input Loading
Output Driving
X 200

AU-ZOO-E1 I Sheet 1/1 I Page 19-1
2-325
Cell Name J Function I Number. of BC
ZOl
Cell Symbol
I 1 Clip Pro]:ag;ation Delay Parameter
I 0
tup tdn
y
X
Input Loading
Output Driving
X 200

AU-Z01-E1 I Sheet 1/1 I Page 19-2
2-326
I/O Buffer Family
Un" Cell Basic

2-331 11B Input Buffer (Inverter) 5

2-332 11BU 11 B with Pull-up Resistance 5
2-333 11BO 11 B with Pull-down Resistance 5
2-334 12B Input Buffer (True) 4
2-335 12BU 12B with Pull-up Resistance 4
2-336 12BO 12B with Pull-down Resistance 4
2-337 IKB Clock Input Buffer (Inverter) 4
2-338 IKBU IKB with Pull-up Resistance 4
2-339 IKBO IKB with Pull-down Resistance 4
2-340 ILB Clock Input Buffer (True) 8
2-341 ILBU ILB with Pull-up Resistance 8
2-342 ILBO ILB with Pull-down Resistance 8
2-343 11C CMOS Interface Input Buffer (Inverter) 5
2-344 11CU 11C with Pull-up Resistance 5
2-345 11CO 11C with Pull-down Resistance 5
2-346 12C CMOS Interface Input Buffer (True) 4
2-348 12CO 12C with Pull-down Resistance 4
2-349 11S Schmitt Trigger Input Buffer (CMOS Type, Inverter) 8
2-350 11SU 11S with Pull-up Resistance 8
2-351 1150 11S with Pull-down Resistance 8
2-352 12S Schmitt Trigger Input Buffer (CMOS Type, True) 8
2-354 12S0 12S with Pull-down Resistance 8
2-355 11R Schmitt Trigger Input Buffer 8
2-356 11RU 11 R with Pull-up Resistance 8
2-357 11RO 11 R with Pull-down Resistance 8
2-358 12R Schmitt Trigger Input Buffer (TTL Type, True) 8
2-359 12RU 12R with Pull-up Resistance 8
2-360 12RO 12R with Pull-down Resistance 8
2-361 01B1 Output Buffer (Inverter) 3
2-362 01L2 Power Output Buffer (Inverter) 3
2-363 01R1 Output Buffer (Inverter) with Noise Limit Resistance 5
2-364 015 2 Power Output Buffer (Inverter) with Noise Limit
Resistance 5
2-365 02B1 Output Buffer (True) 3
2-366 02L2 Power Output Buffer (True) 3
2-367 02R1 Output Buffer (True) with Noise Limit Resistance 4
2-368 02S 2 Power Output Buffer (True) with Noise Limit Resistance 4
2-369 O4R1 3-state Output Buffer (True) with Noise Limit
Resistance 5
2-370 O4S2 Power 3-state Output Buffer (True) with Noise Limit
Resistance 5
2-371 04T1 3-state Output Buffer (True) 6
2-372 04W2 Power 3-state Output Buffer (True) 6
2-373 H6Tl 3-state Output and Input Buffer (True) 8
2-374 H6TUl H6T with Pull-up Resistance 8
2-375 H6T01 H6T with Pull-down Resistance 8
1. IOl=3.2 mA
2. IOl= 12 mA
2-327
AU Series Unit Cell Ubrary CMOS Channelless Gate AtTays
I/O Buffer Family (Continued)
Unit eel! Basic

2-376 H6W2 Power 3-state Output and Input Buffer (True) 8

2-377 H6WU2 H6W with Pull-up Resistance 8
2-378 H6W02 H6W with Pull-down Resistance 8
2-379 H6Cl 3-state Output and CMOS Interface Input Buffer
(True) 8
2-380 H6CUl H6C with Pull-up Resistance 8
2-381 H6COl H6C with Pull-down Resistance 8
2-382 H6E2 Power 3-state Output and CMOS Interface Input
Buffer (True) 8
2-383 H6EU2 H6E with Pull-up Resistance 8
2-384 H6E02 H6E with Pull-down Resistance 8
2-385 H6S l 3-state Output and Schmitt Trigger Input Buffer
(CMOS Type, True) 12
2-386 H6SUl H6S with Pull-up Resistance 12
2-387 H6S0 l H6S with Pull-down Resistance 12
2-388 H6Rl 3-state Output and Schmitt Trigger Input Buffer
(TTL Type, True) 12
2-389 H6RUl H6R with Pull-up Resistance 12
2-390 H6ROl H6R with Pull-down Resistance 12
2-391 H8Tl 3-state Output with Noise Limit Resistance and
Input Buffer (True) 9
2-392 H8TUl H8T with Pull-up Resistance 9
2-393 H8TDl H8T WiT. Pull-down Resistance 9
2-394 H8W2 Power -state Output with Noise Limit Resistance and
2-397 H8Cl 3-state Output Buffer with Noise Limit Resistance
and CMOS Interface Input Buffer (True) 9
2-398 H8CUl H8C with Pull-up Resistance 9
2-399 H8COl H8C with Pull-down Resistance 9
2-400 H8E2 Power 3-state Output Buffer with Noise Limit
Resistance and CMOS Interface Input Buffer (True) 9
2-402 H8ED2 H8E with Pull-down Resistance 9
2-403 H8S l 3-state Output and Schmitt Trigger Input Buffer
(CMOS Type, True) with Noise Limit Resistance 13
2-404 H8SUl H8S with Pull-up Resistance 13
2-405 H8SDl H8S with Pull-down Resistance 13
2-406 H8Rl 3-state Output and Schmitt Trigger Input Buffer
(TTL Type, True) with Noise Limit Resistance 13
2-407 H8RUl H8R with Pull-up Resistance 13
2-408 H8RDl H8R with Pull-down Resistance 13
2-409 IKC CMOS Interface Clock Input Buffer (Inverter) 4
2-410 IKCU IKC with Pull-up Resistance 4
2-411 IKCD IKC with Pull-down Resistance 4
2-412 ILC CMOS Interface Clock Input Buffer (True) 6
1. IOL=3.2 rnA
2. IOL= 12 rnA
3. IOL=8mA
2-328
CMOS Channel/ess Gate Arrays AU Series Unit Cell Library
Unit Cell Basic

2-413 ILCU ILC with Pull-up Resistance 6
2-414 ILCO ILC with PUll-down Resistance 6
2-415 02BF3 Output Buffer 3
2-416 02RF3 Output Buffer with Noise Limit Resistance 4
2-417 04TF3 3-state Output Buffer (True) 6
2-418 04RF3 3-state Output Buffer (True) with Noise Limit
Resistance 5
2-419 H6TF3 3-state Output and Input Buffer (True) 8
2-420 H6TFU3 H6TF with Pull-up Resistance 8
2-421 H6TFD3 H6TF with Pull-down Resistance 8
2-422 H6CF3 3-state Output and CMOS Interface Input Buffer 8
2-423 H6CFU3 H6CF with Pull-up Resistance 8
2-424 H6CFD3 H6CF with Pull-down Resistance 8
2-425 H8TF3 3-state Output with Noise Limit Resistance
and Input Buffer True) 9
2-427 H8TFD3 H8TF with PUll-down Resistance 9
2-428 H8CF3 3-state Output Buffer with Noise Limit Resistance
2-430 H8CF03 H8CF with Pull-down Resistance 9
2-431 02S2 4 Output Buffer with Noise Limit Resistance 3
2-432 04S2 4 3-state Output Buffer (True) with Noise Limit Resistance 4
2-433 H8W2 4 3-state Output and Input Buffer with Noise Limit
Resistance and Input Buffer (TIL, True) 8
2-434 H8E2 4 3-state Output and Input Buffer with Noise Limit
Resistance and Input Buffer (TIL, True) 8
2-435 H8W1 4 3-state Output and Input Buffer with Noise Limit
Resistance and Input Buffer (TTL, True) with
Pull-up Resistance 8
2-436 H8E1 4 3-state Output and Input Buffer) with Noise Limit
Resistance and Input Buffer (CMOS, True) with
Pull-up Resistance 8
2-437 H8W04 3-state Output and Input Buffer with Noise Limit
Resistance and Input Buffer (TTL, True) with
PUll-down Resistance 8
2-438 H8E04 3-state Output and Input Buffer with Noise Limit
Resistance and Input Buffer (CMOS, True) with
PUll-down Resistance 8
1. IOL= 3.2 rnA
2. IOL = 12 rnA
3. IOL= 8 rnA
4. IOL = 24 rnA
2-329
2-330
IlB
Cell Symbol
I
Input Buffer (Inverter)
PropaR;ation Delay Parameter
I 5
tup tdn
1.28 0.03 1.23 0.03 X .. IN
X -{>o-- IN
Input Loading
Output Driving
IN 36

AU-IlB-E2 I Sheet 1/1 I Page 20-1
2-331
IlBU
I
with Pull-up Resistance I 5
Cell Symbol Propagation Delav Parameter
tup tdn
1.28 0.03 1.23 0.03 X .. IN
X --{>o- IN
Parameter Symbol Typ(ns )'"
Input Loading
Pin Name Factor (Jlu)
Output Driving
Pin Name Factor (Jlu)
IN 36

AU-IlBU-E2 I Sheet 1/1 I I Page 20-2
2-332
IlBD
I
with Pull-down Resistance I 5
tup tdn
1.28 0.03 1. 23 0.03 X ... IN
X -{>o- IN
Input Loading
Output Driving
IN 36
')t:
AU-IlBD-E2 I Sheet 1/1 I I Page 20-3
2-333
I2B
Ce11 Symbol
I
Input Buffer (True)
I 4
tup tdn
0.85 0.03 1.47 0.03 X ... IN
X -{>- IN
Input Loading
Output Driving
IN 36

AU-I2B-E2 I Sheet 1/1 I I Page 20-4
2-334
I2BU
I
Input Buffer (True)
Cell Symbol Proj:agation Delay Parameter
tup tdn
0.85 0.03 1.47 0.03 X .. IN
X --[>- IN
Input Loading
Output Driving
IN 36
~': Minimum values for the typical operating condition.
AU-I2BU-E2 I Sheet 1/1 I I Page 20-5
2-335
I2BD
I
Input Buffer (True)
tup tdn
0.85 0.03 1.47 0.03 X ... IN
X -[>- IN
Parameter Symbol Tvp(ns)*
Input Loading
Output Driving
IN 36

AU-I2BD-E2 I Sheet I/IJ I Page 20-6
2-336
IKB
Cell Symbol
I
Clock Input Buffer (Inverter)
I 4
tup tdn
2.05 0.01 1.88 0.01 X -+ CI
X -----{>o- CI
Input Loading
Output Driving
CI 200
0/, Minimum values for the typical operating condition.

AU-IKB-El I Sheet 1/1 I Page 20-7
2-337
IKBU
I
Cell Symbol Prollal!:ation Delay Parameter
tup tdn
2.05 0.01 1.88 0.01 X ... CI
X -{>o- CI
Input Loading
Output Driving
CI 200

are given bJ1 the maximum delay multiplier.
AU-IKBU-E1 I Sheet 1/1 I Pal!:e 20-8
2-338
IKBD
I
tup tdn
2.05 0.01 1.88 0.01 X -+ CI
X -{>o- CI
Input Loading
Output Driving'
CI 200

AU-IKBD-E1 I Sheet 1/1 I J Page 20-9
2-339
FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION I AU VEirsion
Cell Name I Function J Number of BC
ILB
Cell Symbol
ICI~k Input Buffer (True)
I 8
tup tdn
1 •. 09 0.01 1.49 0.01 X .. CI
X ~CI
Input Loading
Output Driving
Pin Name Factor (lul
CI 200
are ltiven bv the maximum delay multiplier.
AU ILB-E2 I Sheet 1/1 I I Page 20-10
2-340
ILBU
I
Clock Input Buffer (True)
tup tdn
1.09 0.01 1.49 0.01 X -+ CI
X
-t>- CI
Parameter Symbol Typ{ns)*
Input Loading
Output Driving
CI 200

AU-ILBU-E2 I Sheet 1/1 I I Page 20-11
2-341
ILBD
I
Cell Symbol Pro~agation Delay Parameter
tup tdn
1.09 0.01 1.49 0.01 X .. CI
X -[>-- CI
Input Loading
Output Driving
CI 200
AU ILBD-E2 I Sheet 1/1 I J Palle 20-12
2-342
IlC
Cell Symbol
I
CMOS Interface Input Buffer (Inverter)
I 5
tUj> tdn
0.65 0.03 0.29 0.03 X ... IN
X --[>0- IN
Input Loading
Output Driving
IN 36
AU-IlC-E3 I Sheet 1/1 I I Page 20-13
2-343
IlCU
I
tup tdn
0.65 0.03 0.29 0.03 X -+ IN
X ---[>- IN
Input Loading
Output Driving
IN 36

AU-IlCU-E3 I Sheet 1/1 I I Page 20-14
2-344
nCD
I
Cell S~ol Propagation Delay Parameter
tup tdn
0.65 0.03 0.29 0.03 X .. IN
X -{>- IN
Input Loading
Output Driving
IN 36

AU-nCD-E3 I Sheet 1/1 I I Page 20-15
2-345
I2C
Cell Symbol
I
CMOS Interface Input Buffer (True)
I 4
tup tdn
to KCL to . KCL KCL2 CDR2 Path
0.74 0.03 1.07 0.03 X .. IN
X --{>- IN
Input Loading
Output Driving
IN 36

AU-I2C-E2 I Sheet 1/1 I Page 20-16
2-346
I2CU
I
CMOS Interface Input Buffer
with Pull-up Resistance (True) I 4
tup tdn
0.74 0.03 1.07 0.03 X .. IN
X
-t>- IN
Input Loading
Output Driving
IN 36

AU-I2CU-E2 I Sheet 1/1 I I Page 20-17
2-347
I2CD
I
with Pull-down Resistance (True) I 4
tup tdn
0.74 0.03 1.07 0.03 X ... IN
X -[>- IN
Input Loading
Output Driving
IN 36
,;'t Minimum values for the typical operating condition.
AU-I2CD-E2 I Sheet 1/1 I I Pa£e 20-18
2~348
IlS
I
Schmitt Trigger Input· Buffer
(CMOS Type Inverter) I 8
tup tdn
3.12 0.13 2.15 0.07 X" IN
X
~ IN
Parameter SytIlbol Typ(ns)*
Input Loading
Output Driving
IN 18

AU-IlS-E2 I Sheet 1/1 I I Page 20-19
2-349
FUJITSU CMOS GATE ARRAY UNIT-CELL SPECIFICATION I AU Version
-IlSU
I
Schmitt Trigger Input Buffer
(CMOS Type,- Inverter) with Pull-up Resistance I 8
Cell Symbol Pro~agation Delav Parameter
tUj) tdn
3.12 0.13 2.15 0.07 X ... IN
X -[po- IN
Input Loading
Pin Name Factor U.u)
Output Driving
Pin Name Factor ClI.u)
IN 18

AU-IlSU-E2 I Sheet 1/1 I I Page 20-20
2-350
Cell Name 1 Function
IlSD
I
(CMOS Typ~, Inverter) with Pull-down Resistance
.1 Number of BC
I 8
Cell Symbol Pro}:agation Delay Parameter
tup tdn
3.12 0.13 2.15 0.07 X -+ IN
X
~ IN
Input Loading
Output Driving
IN 18

AU-IlSD-E2 1 Sheet 1/1 1 1 Page 20-21
2-351
FUJITSU C~OS GATE ARRAY UNIT CELL SPECIFICATION ,
AU" Version
Cell Name' Function , Number of BC
125
I
(CMOS Type. True) I 8
Cell Symbol Pro~al!;ation Delay Parameter
tup tdn
1.99 0.13 2.47 0.08 X ... IN
X
--iP- IN
.Parameter Symbol Typ(ns)'"
Input Loading
Output Driving
IN 18

AU-I25-E2 , Sheet 1/1 , , Page 20-22
2-352
I2SU
I
(CMOS Type, True) with Pull-up Resistance I 8
tup tdn
1.99 0.13 2.47 0.08
X IN
~
Input Loading
Output Driving
IN 18

are J?;iven by the maximum delay multiplier.
AU-I2SU-E2 I Sheet 1/1 I Page 20-23
2-353
Cell Name I- Function I Number of BC
I2SD
ISchmitt Trigger Input Buffer
(CMOS Type, True) with Pull'~down Resistance I 8
tup tdn
1.99 0.13 2.47 0.08 X -+ IN
X
-W- IN
Input Loading
Output Driving
IN 18

AU-I2SD-E2 I Sheet 1/1 J Page 20-24
2-354
IlR
I
(TTL Type, Inverter) I 8
tup tdn
3.59 0.13 1.89 0.07 X" IN
X --[po- IN
Input Loading
Output Driving
IN 18

The· values for the worst case operating condition
AU-IlR-E2 I Sheet 1/1 I I Page 20-25
2-355
IIRU
I
(TTL Type, Inverter) with Pull-up Resistance I 8
Cell Symbol Pro.agation Delay Parameter
tup tdn
3.59 0.13 1. 89 0.07 X -+ IN
X
--P- IN
Input Loading
Output Driving
Pin Name Factor (9-u)
IN 18

AU-IlRU-E2 I Sheet 1/1 I I Page 20-26
2-356
IlRD
I
(TTL Type, Inverter) with Pull-down -Resistance I 8
Cell Symbol Prot:agation Delay Parameter
tup tdn
3.59 0.13 1. 89 0.07 X ... IN
X ---{Po- IN
Input Loading
Output Driving
IN 18
'k Minimum values for the typical operating condition.
AU-llRD-E2 I Sheet 1/1 I I Page 20 27
2-357
I2R
I
(TTL Type True I 8
Ce11 Symbol Propagation Delay Parameter
tup tdn
1. 79 0.13 2.98 0.11 X -+ IN
X --fp---- IN
Input Loading
Output Driving
IN 18
1: Minimum values for the typical operating condition.

AU-I2R-E2 I Sheet 1/1 I I Page 20-28
2-358
FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION i "AU" Version
I2RU
I
(TTL Type 'True with Pull-up Resistance I 8
tup tdn
1. 79 0.13 2.98 0.11 X" IN
X
--f9- IN
Input Loading
Output Driving
IN 18
,., Minimum values for the typical operating condition.

AU-I2RU-E2 I Sheet 1/1 I I Page 20-29
2-359
I2RD
I
(TTL Type, True with Pull-down Resistance I 8
tup tdn
1. 79 0.13 2.98 0.11 X .. IN
X
-W- IN
Input Loading
Output Driving
IN 18

are .l!:iyen by the maximum delay multiplier.
AU-I2RD-E2 I Sheet 1/1 I I Page 20-30
2-360
01B
Cell Symbol
I
Output Buffer (Inverter)
I 3
tup tdn
1. 60 0.047 1.63 0.103 OT ... X
(4.42) (7.81)
OT --[>r- X
Input Loading
OT 2
Output Driving

Note: 1. The unit of KCL is ns/pF.
2. Output load capacitance of 60 pF is used for Fujitsu's

logic simulation.
3. The parameters in parentheses are the values applied to the simulation.
AU-01B-El I Sheet 111 I I Page 20-31
2-361
Cell Name I Func,tion I Number of BC
OIL
Cell Symbol
1
Power Output Buffer (Inverter)
ProIagation Delav Parameter
I 3
tup tdn
2_00 0.032 2.13 0.034 OT .. X
(3.92) (4.17)
OT -[>- X
Input Loading
OT 2
Output Driving
...,: Minimum values for the typical operating condition .

are_given b~ the maximum delay multiplier.
Note: 1- The unit of KCL is ns/pF.

logic simulation.
AU-OlL-El I Sheet 1/1 I t Page 20-32
2-362
01R
I
Output· Buffer (Inverter)
with Noise Limit Resistance I 5
tup tdn
3.75 0.047 6.60 0.103 OT .. X
(6.57) (12.78)
OT -{>- X
Parameter S~mbol Typ(ns)*
Input Loading
OT 1
Output Driving

Note: 1.. The unit of KCL is ns/pF.

logic simulation.
3. The p~rameters in parentheses are the values applied to the simulation.
AU-OlR-EI I Sheet 1/1 I I Page 20-33
2-363
FUJITSU CMOS GATE ARRAY UNIT CELL ,SPECIFICATION I AU Version
01S
I
Cell Symbol Pro]:a.e;ation Delay Parameter
tup tdn
4.35 0.033 8.69 0.046 OT -> X
(6.33) (11.45)
OT ---(>--- X
Input Loading
OT 1
Output Driving

are given by the maximum delay multiElier.

logic simulation.
AU-OIS-El I Sheet III I I Page 20-34
2-364
FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION L AU Version
02B
Cell Symbol
I
Output Buffer (True)
I 3
tup too
0.78 0.047 1.15 0.103 OT ... X
(3.60) (7.33)
OT -{>- X
Parameter Symbol ["YP1 ns ",
Input Loading
OT 6
Output Driving
", Minimum values for the typical operating condition.

Note: 1. The unit of KcL is ns/pF.

logic simulation.
AU-02B-E2 I Sheet III I JPage 20-35
2-365
02L
Cell Symbol
I
Power Output Buffer (True)
I 3
tup tdn
0.89 0.032 1.26 0.034 OT + X
(2.81) (3.30)
OT
-t>- X
Parameter Symbol Typ(ns}*
Input Loading
OT 6
Output Driving

Note: l. The unit of KcL is ns/pF.

logic simulation.
AU-02L-E2 I Sheet 111 I I Page 20-36
2-366
02R
I
tup tdn
3.68 0.047 6.07 0.103 OT .. X
(6.50) (12.25)
Or -{>- X
Parameter Symbol Typ(ns»~
Input Loading
OT 2
Output Driving
* Minimum values f"or the typical operating condition.

Note: l. The unit of KCL is ns/pF.

logic simulation.
AU-02R-El I Sheet 1/1 I I Page 20-37
2-367
02S
I
with Noise Limit Resistance I4
tup tdn
4.40 0.033 8.48 0.046 OT -+ X
(6.38) (11.24)
OT -[>- X
Input Loading
OT 2
Output Driving
,;'e Minimum values for the typical operating condition.


logic simulation.
AU-02S-E1 I Sheet 1/1 I Page 20-38
2-368
Cell Name 1 Function I Number of BC
I
Tri-state Output Buffer (True) ..
04R
Cell Symbol
with Noise Limit Resistance
5 I
tup tdn
3.35 0.047 6.26 0.103 OT -> X
(6.41) (12.96)
OT
-11 C
X
L -> Z Z -> L
to KCL to KCL C -> X
2.00 6.62 0.105
(13.57) ..'r: (13.45)
Input Loading
Pin Name Factor (,Q.u)
OT 2
C 2 H -> Z Z -> H
to KCL to KCL
3.20 3.40 0.048
Output Driving (13.57) -1: (13.45)
~, These values are subject to external loading condition.

Measurement circuits of propagation delay time
at LZ, ZL, HZ and Zh are as follows:
cH' =2 kl1
C
\:l lc 1'" kQ
~
2
rL
(a) Measurement of tpd at LZ and ZL. (b) Measurement of tpd at HZ and ZH.

logic simulation.
3. The parameters in parentheses are the values applied to the

simulation.
AU-04R-E1 I Sheet 1/1 I I Page 20-39
2-369
FUJITSU CMOS GATE ARRAY UNIT. CELL SPECIFICATION I AU" Version
Cell Name J Function I Number of BC
04S
I
Power Tri-state Output Buffer (True)
with Noise Limit Resistance 5 I
Cell Symbol Pro~agation Delay Paramete·r
tup tdn
4.06 0.033 8.64 0.046 OT -> X
(6.21) (11. 63)
OT
---tr- C
X
L-> Z Z -> L
to KCL to KCL C ... X
3.50 8.36 0.046
(16.80) >~ (11.35)
Input Loading
OT 2
C 2 H ... Z Z -> H
to KCL to KCL
4.00 4.30 0.033
Output Driving (16.80) ,', (11.35)
,', These values are subject to external loading condition.

at LZ, ZL, HZ and ZH are as follows:
cl
=2 kQ
~
R
C
LSI
~
lc 1,2 kQ

logic simulation.

simulation.
AU-04S-E1 I Sheet 111 I I Page 20-40
2-370
04T
Cell Symbol
I
Tri-state Output Buffer (True)
I 6
tup tdn
1.08 0.047 1.95 0.103 OT ... X
(4.14) (8.65)
OT
-cr- C
X
L ... Z Z ... L
1.86 2.44 0.105
(13.89) (9.27)
*
Input Loading
OT 6
C 2 H ... Z Z ... H
to KCL to KCL
3.77 1.23 0.048
Output Driving (13.89) (9.27)
Pin Name Factor (.tu) *
* These values are subject to external loading condition.

cl
2kn
R
-
LSI
~
C
(a) Measurement of tpd at LZ and ZL.

LSI
lc
,L 1·..·
(b) Measurement of tpd at HZ and ZH.
Note: 1- The unit of Kcr. is ns/pF.

logic simulation.

simulation.
AU-04T-E2 I Sheet 111 I I Page 20-41
2-371
Cell Name 1 Function I Number of BC
04W
Cell Symbol
I
I 6
tup too
1.49 0.032 2.34 0.036 OT ... X
(3.57) (4.68)
OT
-tr C
X
L'" Z Z ... L
2.62 2.53 0.036
(15.80) (4.87)
*
Input Loading
OT 6
C 2 H -+ Z Z ... H
to KCL to KCL
4.47 1.44 0.033
Output Driving (15.80) * (4.87)

cl
21d2
R
- I
I LSI
LSI
,.L
C
I lc
,L 1'=2'"

logic simulation.
3. The parametElrs in parentheses are the values applied to the

simulation.
AU-04W-E2 I Sheet 1/1 I I Page 20-42
2-372
Cell Name ~Function I Number of BC
H6T
Cell Symbol
I
Tri-state Output & Input Buffer (True)
Pro.agation Delay Parameter
I 10
tup tdn
0.85 0.03 1.47 0.03 X -+ IN
1.08 0.047 1.95 0.103 OT -+ X
(5.08) (10.71)
IN
OT
=cr- C
X
L -+ Z Z-+L
to KCL to KCL C -+ X
1.86 2.44 0.105
(17.00) ,~
(11.37)
Input Loading
OT 6
C 2 H-+ Z Z -+ H
to KCL to KCL
3.77 1.23 0.048
Output Driving (17.00) * (11. 37)
IN 36

cl'
=2 kll
I
I LSI I
~
C

lc
rL 1 02

kQ
Note: 1. The unit of KCL for paths QT, C to X is ns/pF.

logic simulation.

simulation.
AU-H6T-E3 I Sheet 1/1 I I Page 20-43
2-373
H6TU
I
with Pull-up Resistance 10 I
tup tdn
0.85 0.03 1.47 0.03 X ... IN
1.08 0.047 1.95 0.103 OT ... X
(5.08) (10.71)
~
IN
OT X
L ... Z Z ... L
1.86 2.44 0.105
(17.00) * (11.37)
Input Loading
Pin Name Factor (.ta)
OT 6
C 2 H ... Z Z ... H
to KCL to KCL
3.77 1.23 0.048
IN 36

w4
= 2 kSl
1-"'"
R
LSI
C lc
~ ;L
Note: 1. The unit of KCL for paths OT, C to X is ns/pF.

logic simulation.

simulation.
AU-H6TU-E3 I Sheet III I I Page 20-44
2-374
Cell Name I Function 1 Number of BC
H6TD
I
with Pull-down Resistance 10 I
Cell Symbol ProIagation Delay Parameter
tup tdn
0.85 0.03 1.47 0.03 X .. IN
1.08 0.047 1.95 0.103 OT .. X
(5.08) (10.71)
IN
OT
=cr- C
X
L .. Z Z .. L
to KCL to KCL C .. X
1.86 2.44 0.105
(11.37)
(17.00) *
Input Loading
OT 6
C 2 H .. Z Z ... H
to KCL to KCL
3.77 1.23 0.048
Output Driving (17.00) ,~
(11. 37)
IN 36

cl'
= 21dl
~
C
LSI
~
lc l' =2 kll
Note: 1. The unit of KCL for paths aT, C to X is ns/pF.
2. Output load capacitance of 85 pF is used for FUjitsu's

logic simulation.

simulation.
AU-H6TD-E3 I Sheet 1/1 I I Page 20-45
2-375
H6W
Cell Symbol
I
Power Tri-state Output & Input Buffer
Pro~aStation
(True)
Delay Parameter
I 10
tup tdn
0.85 0.03 1.47 0.03 X ... IN
1.49 0.032 2.34 0.036 OT ... X
(4.21) (5.40)
IN
OT
=cr- C
X
L'" Z Z ... L
2.62 2.53 0.036
(19.80) * (5.59)
Input Loading
OT 6
C 2 H'" Z Z ... H
to KCL to KCL
4.47 1.44 0.033
IN 36

cl
2kR
R
LSI
C
-
W lc
1'2"
rL ,I

logic simulation.

simulation.
AU-H6W-E3 I Sheet 1/1 I I Page 20 46
2-376
I Number of BC
H6WU
I
Cell Name JFunction
Power Tri-state Output & Input Buffer (True)
with Pull-up Resistance 10 J
tup tdn
0.85 0.03 1.47 0.03 X ... IN
1.49 0.032 2.34 0.036 OT ... X
(4.21) (5.40)
=rr-
IN
OT X
L'" Z Z ... L
2.62 2.53 0.036
(19.80) * (5.59)
Input Loading
OT 6
C 2 H ... Z Z ... H
to KCL to KCL
4.47 1.44 0.033
IN 36

~'
=2 kQ
,;L
C
LSI
~
lc 1'=2 kQ

logic simulation.

simulation.
AU-H6WU E3 I Sheet 111 I I Page 20-47
2-377
H6WD
I
Cell Name I Function
Power Tri-state Output & Input Buffer (True)
with Pull-down Resistance
I Number of BC
10 I
tup tdn
0.85 0.03 1.47 0.03 X .. IN
1.49 0.032 2.34 0.036 OT .. X
(4.21) (5.40)
IN
OT
=cr- C
X
L .. Z Z .. L
2.62 2.53 0.036
(19.80) * (5.59)
Input Loading
OT 6
C 2 H .. Z Z .. H
to KCL to KCL
4.47 1.44 0.033
IN 36

c:H'
=2 kQ
~
C
LSI
lc
.-L
1'=2kll

logic simulation.

simulation.
AU-H6WD-E3 I Sheet 111 I I Page 20 48
2-378
H6C
Cell Symbol
I
Tri-state Ou.J;put & CMOS Interface Input Buffer (True)
I 10
tup tdn
0.74 0.03 1. 07 0.03 X .. IN
1.08 0.047 1.95 0.103 OT .. X
(5.08) (10.71)
IN
OT
=cr- C
X
L .. Z Z .. L
1.86 2.44 0.105
(17.00) * (11.37)
Input Loading
OT 6
C 2 H .. Z Z .. H
to KCL to KCL
3.77 1.23 0.048
IN 36

cl'
= 2kll
rL
C
LSI
lc
rL
1'; 21,,,

logic simulation.

simulation.
AU-H6C-E3 I Sheet 1/1 I I Page 20-49
2-379
H6CU
I
Tri-state Output & CMOS Interface Input Buffer (True)
tup tdn
0.74 0.03 1.07 0.03 X .. IN
1.08 0.047 1.95 0.103 OT .. X
(5.08) (10.71)
~
IN
OT X
C
L .. Z Z .. L
1.86 2.44 0.105
(17.00) * (11.37)
Input Loading
OT 6
C 2 H" Z Z .. H
to KCL to KCL
3.77 1.23 0.048
*
IN 36

c:H
= 2 kn
R
~
C
LSI
lc
"I
1=2>0
Note: l. The unit of KCL for paths OT, C to X is ns/pF.

logic simulation.

simulation.
AU-H6CU-E3 I Sheet 1/1 I I Page 20-50
2-380
H6CD
I
Tri-state Output & CMOS Interface Input Buffer (True)
tup tdn
0.74 0.03 1.07 0.03 X" IN
1.08 0.047 1.95 0.103 OT .. X
(5.08) (10.71)
~
IN
OT X
L .. Z Z .. L
1.86 2.44 0.105
(17.00) (11.37)
*
Input Loading
OT 6
C 2 H .. Z Z ... H
to KCL to KCL
3.77 1.23 0.048
Output Driving (17.00) * (11. 37)
IN 36

cl'
=2 kQ
~
C
LSI
lc
,I 1=2""

logic simulation.
3. The parameters in parenthe'ses are the values applied to the

simulation.
AU-H6CD-E3 I Sheet 1/1 I I Page 20-51
2-381
H6E
I
Power Tri-state Output & CMOS Interface
Input Buffer (True) 10 I
tup tdn
0.74 0.03 1.07 0.03 X -+ IN
1.49 0.032 2.34 0.036 OT -+ X
(4.21) (5.40)
IN
OT
=cr- C
X
L-+ Z Z-+L
to KCL to KCL C-+ X
2.62 2.53 0.036
(19.80) * (5.59)
Input Loading
OT 6
C 2 H-+ Z Z -+ H
to KCL to KCL
4.47 1.44 0.033
IN 36

cl'
= 2 kSl
C
I'I LSI
lc 1. 2
k.I2
~ ~

logic simulation.

simulation.
AU-H6E-E3 I Sheet 1/1 I I Page 20-52
2-382
H6EU
I
Input Buffer (True) with Pull-up Resistance 10 I
Cell Symbol Prollagation Delay Parameter
tup tdn
0.74 0.03 1.07 0.03 X .. IN
1.49 0.032 2.34 0.036 OT .. X
(4.21) (5.40)
IN
OT
=cr- C
X
L .. Z Z .. L
2.62 2.53 0.036
(19.80) * (5.59)
Input Loading
OT 6
C 2 H .... Z Z .... H
to KCL to KCL
4.47 1.44 0.033
Output Driving (19.80) ~,
(5.59)
IN 36

eB' =2 kll
~
C
LSI
lc
rL 1'=2""
Note: 1. The unit of KcL for paths OT, C to X is ns/pF.

logic simulation.

simulation.
AU-H6EU-E3 I Sheet 111 I I Page 20-53
2-383
H6ED
I
Input Buffer (True) with Pull-down Resistance 10 I
Ce11 Symbol Pro~altation Delay Parameter
tup tdn
0.74 0.03 1.07 0.03 X -+ IN
1.49 0.032 2.34 0.036 OT -+ X
(4.21) (5.40)
IN
OT
=cr- C
X
L-+ Z Z -+ L
2.62 2.53 0.036
(19.80) * (5.59)
Input Loading
OT 6
C 2 H-+ Z Z -+ H
to KCL to KCL
4.47 1.44 0.033
Pin Name Factor (J1.u) *
IN 36

D}'- 2 kQ
1
LSI
LSI
C lc 02
kS2
rL ,I

logic simulation.

simulation.
AU-H6ED-E3 I Sheet 1/1 I I Page 20-54
2-384
H6S
I
Tri-state Output & Schmitt Trigger Input Buffer
(CMOS Type, True) 14 I
Cell Symbol Prolagation Delay Parameter
tup tdn
1.99 0.13 2.47 0.08 X -+ IN
1.08 0.047 1.95 0.103 OT -+ X
(5.08) (10.71)
~
IN
OT X
L-+ Z Z -+ L
1.86 2.44 0.105
(17.00) * (11.37)
Input Loading
OT 6
C 2 H-+ Z Z -+ H
to KCL to KCL
3.77 1.23 0.048
Pin Name Factor (lu) *
IN 18

cl
=2 k12
C
W lc
1=' kl2
rL ..I

logic simulation.

simulation.
AU-H6S-E3 I Sheet 1/1 I I Page 20-55
2-385
Cell Name J Function 1 Number of BC
H6SU
I
(CMOS Type True) with Pull-up Resistance 14 I
Cell Symbol Prot:agation Delay Parameter
tup tdn
1.99 0.13 2.47 0.08 X .. IN
1.08 0.047 1.95 0.103 OT .. X
(5.08) (10.71)
~
IN
OT X
C
L .. Z Z .. L
1.86 2.44 0.105
(17.00) * (11. 37)
Input Loading
OT 6
C 2 H" Z Z .. H
to KCL to KCL
3.77 1.23 0.048
IN 18

cH' ~
C
= 2 kS2

I' LSI I
lc
rL
l' -
'kll

logic simulation.

simulation.
AU-H6SU-E3 I Sheet 1/1 I I Pa2e 20-56
2-386
H6SD
I
(CMOS Type, True) with Pull-down Resistance
I Number of BC
14 I
tup tdn
1.99 0.13 2.47 0.08 X .. IN
1.08 0.047 1.95 0.103 OT .. X
(5.08) (10.71)
~
IN
OT X
L .. Z Z .. L
1.86 2.44 0.105
(17.00) * (11.37)
Input Loading
OT 6
C 2 H .. Z Z .. H
to KCL to KCL
3.77 1.23 0.048
Output Driving (17.00) * (11. 37)
IN 18

cH
= 2kSl
I
I
1.
R
LSI I lc 2
kSl
C
~ ~

logic simulation.

simulation.
AU-H6SD-E3 I Sheet 1/1 I I Page 20-57
2-387
H6R
I
(TTL Type True) 14 I
tup tdn
1.79 0.13 2.98 0.11 X -+ IN
1.08 0.047 1.95 0.103 OT -+ X
(5.08) (10.71)
~
IN
OT X
C
L -+ Z Z-+L
1.86 2.44 0.105
(17.00) * (11.37)
Input LQading
OT 6
C 2 H -+ Z Z -+ H
to KCL to KCL
3.77 1.23 0.048
Output Driving 0:7.00) (11.37)
Pin Name Factor (.tul *
IN 18

Measurement circuits of p=opagation delay time
cl
2kS2
R
1" "'.
-
LSI
LSI
C lc
~ rI

logic simulation.

simulation.
AU-H6R-E3 I Sheet 1/1 I I Page 20-58
2-388
H6RU
I
Tri -state Output & Schmitt Trigger Input Buffer
(TTL Type, True' with Pull-up Resistance 14 I
tup tdn
1. 79 0.13 2.98 0.11 X ... IN
1.08 0.047 1.95 0.103 OT ... X
(5.08) (10.71)
~
IN
OT X
L ... Z Z ... L
1.86 2.44 0.105
(17.00) * (11. 37)
Input Loading
OT 6
C 2 H'" Z Z ... H
to KGL to KGL
3.77 1.23 0.048
*
IN 18

cl
2 kQ
R
1=2
-
LSI
LSI
C lc kQ
~ ,I

logic simulation.

simulation.
AU-H6RU-E3 I Sheet 1/1 I I Page 20-59
2-389
H6RD
I
(TTL Type True with Pull-down Resistance 14 I
tup tdn
1. 79 0.13 2.98 0.11 X ... IN
1.08 0.047 1.95 0.103 OT ... X
(5.08) (10.71)
IN
OT
=cr- C
X
L ... Z Z ... L
1.86 2.44 0.105
(17.00) (11.37)
*
Input Loading
OT 6
C 2 H-+ Z Z -+ H
to KCL to KCL
3.77 1.23 0.048
Pin Name Factor (R.u) *
IN 18

c=H R
-
2 kg
LSI
~
C

LSI
~
lc
1='"

logic simulation.

simulation.
AU-H6RD-E3 1 Sheet 1/1 I I Page 20-60
2-390
HBT
I
Tri-state Output with Noise Limit Resistance
& In2ut Buffer (True) 9 I
Cell Symbol Pro2a~ation Delay Parameter
tup tdn
0.B5 0.03 1.47 0.03 X .. IN
3.35 0.047 6.26 0.103 OT .. X
(7.35) (15.02)
IN
OT
=cr- C
X
L ." Z ·z .. L
2.00 6.62 0.105
(16.95) (15.55)
*
Input Loading
OT 2
C 2 H" Z Z .. H
to KCL to KCL
3.20 3.40 0.048
Output Driving (16.95) 1, (15.55)
IN 36
,~ These values are subject to external loading condition.

eB' =2 kQ
C
W lc 1'=2 kQ
~ rL
2. Output load capacitance of B5 pF is used for Fujitsu's

logic simulation.

simulation.
AU-HBT-E2 I Sheet 1/1 I Page 20-61
2-391
H8TU
J
Tri-state Output with Noise Limi.t Resistance
& I~ut Buffer (True) with Pull-up Resistance
I Number of BC
9 I
Cell Symbol Pro~agation Delav Parameter
tup tdn
0.85 0.03 1.47 0.03 X .. IN
3.35 0.047 6.26 0.103 OT" X
(7.35) (15.02)
IN
OT
=cr- C
X
L .. Z Z ... L
2.00 6.62 0.105
(16.95) * (15.55)
Input Loading
OT 2
C 2 H .. Z Z ... H
to KCL to KCL
3.20 3.40 0.048
(15.55)
IN 36
,~ These values are subject to external loading condition.

~'
=2 kQ
C
W lc 1'2 kQ
~ ~

logic simulation.

simulation.
AU-H8TU-E2 I Sheet 1/1 I I Page 20-62
2-392
Cell Name 1 Function .1 Number of BC
H8TD
I
& Input Buffer (True) with Pull-do~~ Resistance 9 I
tup tdn
0.85 0.03 1.47 0.03 X" IN
3.35 0.047 6.26 0.103 OT" X
(7.35) (15.02)
IN
OT
=cr- C
X
L .. Z Z -+ L
2.00 6.62 0.105
(16.95) ,~
(15.55)
Input Loading
OT 2
C 2 H -+ Z Z .. H
to KCL to KCL
3.20 3.40 0.048
Output Driving (16.95) '".': (15.55)
IN 36

cB
=2 k12
1"'
LSI
C lc k12
,.;L ,.L

logic simulation.
3. The parameters in ·parentheses are the values applied to the

simulation.
AU-H8TD-E2 I Sheet 1/1 I 1 Page 20-63
2-393
H8W
I
Power Tri-state Output with Noise Limit Re~;istance
& Input Buffer (True) 9 I
Cell Symbol Pro}:agation Delay Parameter
tup tdn
0.85 0.03 1.47 0.03 X -+ IN
4.06 0.033 8.64 0.046 OT -+ X
(6.87) (12.55)
IN
OT
=cr- C
X
L -+ Z Z -+ L
3.50 8.36 0.046
(21. 09) * (12.27)
Input Loading
OT 2
C 2 H -+ Z Z .. H
to KCL to KCL
4.00 4.30 0.033
Output Driving (21. 09) ~,
(12.27)
IN 36

eB' =2 kQ
I
I LSI
1"'~
I lc
C
,;L rL

logic simulation.

simulation.
AU-H8W-E2 I Sheet 1/1 I Page 20-64
2-394
I
Power Tri~state Output with Noise Limit Resistance
H8WU
Cel1 Symbol
& Input Buffer (True) with Pull-up Resistance
9 I
tup tdn
0.85 0.03 1.47 0.03 X -+ IN
4.06 0.033 8.64 0.046 OT -+ X
(6.87) (12.55)
IN
OT
=cr- C
X
L-+ Z Z -+ L
3.50 8.36 0.046
(21. 09) * (12.27)
Input Loading
OT 2
C 2 H -+ Z Z -+ H
to KCL to KCL
4.00 4.30 0.033
Output Driving (21. 09) ~,
(12.27)
IN 36

01' =2 kQ
1"'
LSI
C lc kQ
~ ~

logic simulation.

simulation.
AU-HBWU-E2 I Sheet 1/1 I I Page 20-65
2-395
Cell Name .1 Function I Number of BC
H8WD
I
Power Tri~state Output with Noise .Limit Resistance
& Input Buffer (True) with Pull-down Resistance 9 I
tup tdn
0.85 0.03 1.47 0.03 X ... IN
4.06 0.033 8.64 0.046 OT ... X
(6.87) (12.55)
IN
OT
=cr- C
X
L ... Z Z ... L
3.50 8.36 0.046
(21. 09) -.': (12.27)
Input Loading
OT 2
C 2 H -+ Z Z -+ H
to KCL to KCL
4.00 4.30 0.033
Output Driving (21. 09) ,', (12.27)
IN 36

cl'
=2 kl"l
1""
LSI
C 1 C
rL ~

logic simulation.
3. The parameters in 'parentheses are the values applied to the

simulation.
AU-H8WD-E2 I Sheet 1/1 I I Page 20-66
2-396
H8C
I
Tri state Output Buffer with Noise Limit Resistance
& CMOS Interface Input Buffer (True) 9 I
tup tdn
0.74 0.03 1.07 0.03 X -+ IN
3.35 0.047 6.26 0.103 OT -+ X
(7.35) (15.02)
IN
OT
=cr- C
X
L-+ Z Z -+ L
2.00 6.62 0.105
(16.95) 'I: (15.55)
Input Loading
OT 2
C 2 H-+ Z Z -+ H
to KCL to KCL
3.20 3.40 0.048
(15.55)
IN 36
1, These values are subject to external loading condition.

cl'
=2 kR
~
C
LSI
1
--I
C
1'=2 kR

logic simulation.

simulation.
AU-H8C-E2j Sheet 1/1 I I Page 20-67
2-397
H8CU
I
Tri-state Output Buffer w/ Noise Limit Resistance &
CMOS Interface Input Buffer (True) w/ Pull-up Resistance 9
I
tup tdn
0.74 0.03 1.07 0.03 X" IN
3.35 0.047 6.26 0.103 OT .. X
(7.35) (15.02)
IN
OT
=cr- C
X
L .. Z Z .. L
2.00 6.62 0.105
(16.95) 1, (15.55)
Input Loading
OT 2
C 2 H .. Z Z .. H
to KCL to KCL
3.20 3.40 0.048
IN 36

cl
=2 kS'l
~
R
C
W
rL
lc 1'. 2
kS'l

logic simulation.

simulation.
AU-H8CU-E2 I Sheet 1/1 I I Page 20-68
2-398
H8CD
I
Tri-state Output Buffer wi Noise Limit Resistance & CMOS
Interface Input Buffer (True) wi Pull-down Resistance 9
I
·tup tdn
0.74 0.03 1.07 0.03 X -+ IN
3.35 0.047 6.26 0.103 OT -+ X
(7.35) (15.02)
IN
OT
=cr- C
X
L-+ Z Z -+ L
2.00 6.62 0.105
(16.95) (15.55)
*
Input Loading
OT 2
C 2 H -+ Z Z -+ H
to KCL to KCL
3.20 3.40 0.048
Output Driving (16.95) ,': (15.55)
IN 36

cl
=2 kQ
,.L
R
C
LSI
~
lc 1- 2
kQ

logic simulation.

simulation.
AU-H8CD-E2 I Sheet 1/1 I Pa,ge 20-69
2-399
H8E
I
Power Tri-state Output Buffer wI Noise Limit Resistance
& CMOS Interface Input Buffer (True) 9
I
Cell Symbol Prollagation Delay Parameter
tup tdn
to KCL to KCL KCL2 CDR Path
0.74 0.03 1.07 0.03 X ...IN
4.06 0.033 8.64 0.046 OT ... X
(6.87) (12.55)
~
IN
OT X
C
L ... Z Z ... L
3.50 8.36 0.046
(12.27)
(21. 09) *
Input Loading
OT 2
C 2 H ... Z Z ... H
to KCL to KCL
IfII Pin Name

Output Driving
Factor (iu)
4.00
(21. 09) *
4.30
(12.27)
0.033
IN 36

cl'
=2 kQ
I
I LSI
-L
C

I lc
,-I 1"
kQ
Note: 1- The unit of KCL for paths OT, C to X is ns/pF.
2. Output'load capacitance of 85 pF is used for Fujitsu's

logic simulation.

simulation.
AU-H8E-E2 I Sheet 1/1 I Page 20-70
2-400
H8EU
I
Power Tri-state Output Buffer wi Noise Limit Resistance ~i
CMOS Interface Input Buffer (True) wi Pull-up Resistance 9
tup tdn
to KCL to KCL KCL2 CDR Path
0.74 0.03 1.07 0.03 X-> IN
4.06 0.033 8.64 0.046 OT -> X
(6.87) (12.55)
~
IN
OT X
C-
L-> Z Z -> L
3.50 8.36 0.046
(21. 09) ,)'t (12.27)
Input Loading
OT 2
C 2 H'" Z Z ... H
to KCL to KCL
4.00 4.30 0.033
Output Driving (21. 09) (12.27)
Pin Name Factor (!u) '"
IN 36
'" These values are subject to external loading condition.

cl'
=2 kQ
rL
C
W lc
J:
1',2 kQ

logic simulation.

simulation.
AU-H8EU-E2 I Sheet 1/1 I I Page 20-71
2-401
I Power Tri state Output Buffer wi Noise Limit Resistance & el
H8ED CMOS lnterface Input Buffer (True) wi Pull-down Resistance 9
Cell Symbol Pro~altation Delay Parameter
tup tdn
0.74 0.03 1.07 0.03 X .. IN
4.06 0.033 8.64 0.046 OT" X
(6.87) (12.55)
~
IN
OT X
C
L .. Z Z .. L
3.50 8.36 0.046
(21. 09) ,~
(12.27)
Input Loading
OT 2
C 2 H ... Z Z ... H
to KCL to KCL
4.00 4.30 0.033
Output Driving (21. 09) * (12.27)
IN 36

01' =2 kQ
C
i:l lc 1'.2kl1
~ J.

logic simulation.

simulation.
AU H8ED E2 I Sheet 1/1 I Page 20-72
2-402
H8S
I
(CMOS Type True) with Noise Limit Resistance 13 I
tup tdn
1.99 0.13 2.47 0.08 X ... IN
3.35 0.047 6.26 0.103 OT ... X
(7.35) (15.02)
IN
OT
=cr- C
X
L ... Z Z ... L
2.00 6.62 0.105
(16.95) ,t: (15.55)
Input Loading
Pin Name Factor CR.u)
OT 2
C 2 H ... Z Z ... H
to KCL to KCL
3.20 3.40 0.048
IN 18
,., These values are subject to external loading condition.

cH' =2 kQ
~
C
LSI
~
lc 1'.2 kQ

logic simulation.

simulation.
AU-H8S-E2 I Sheet 1/1 ! Page 20-73
2-403
H8SU
I
Tri-state Output & Schmitt Trigger Input Buffer(CMOS TYPj
,True) wi Noise Limit Resistance wi Pull-up Resistance 13
tup tdn
1. 99 0.13 2.47 0.08 X -+ IN
3.35 0.047 6.26 0.103 OT -+ X
(7.35 ) (15.02)
=tr-
IN
OT X
L-+ Z Z -+ L
2.00 6.62 0.105
(16.95) ,~
(15.55)
Input Loading
OT 2
C 2 H-+ Z Z -+ H
to KCL to KCL
3.20 3.40 0.048
(15.55)
IN 18

cl'
=2 kQ
~
C

LSI
~
lc 1':'
kQ

logic simulation.

simulation.
AU-H8SU-E2 I Sheet 1/1 I I Page 20-74
2-404
H8SD
I
Tri-state Output & Schmitt Trigger Input Buffer(CMOS TY~i
,True) wi Noise Limit Resistance wi Pull-down Resistance 13
tup tdn
1. 99 0.13 2.47 0.08 X .. IN
3.35 0.047 6.26 0.103 OT .. X
(7.35) (15.02)
IN
OT
=t?- C
X
L .. Z Z .. L
to KCL to I<CL C .. X
2.00 6.62 0.105
(16.95) ..,: (15.55)
Input Loading
OT 2
C 2 H .. Z Z .. H
to KCL to KCL
3.20 3.40 0.048
Outpu~ Driving (16.95) <{,
(15.55)
IN 18

eJI' ~
C
=2 kSl
(a) ·Measurement of tpd at LZ and ZL.

LSI
~
lc
1-'
kSl

logic simulation.

simulation.
AU-H8SD-E2! Sheet Ill! I Page 20-75
2-405
H8R
I
(TIL Type True with Noise Limit Resistance 13 I
tup tdn
1. 79 0.13 2.98 0.11 X -+ IN
3.35 0.047 6.26 0.103 OT -+ X
(7.35) (15.02)
~
IN
OT X
C
L ... Z Z -+ L
2.00 6.62 0.105
(16.95) * (15.55)
Input Loading
OT 2
C 2 H -+ Z Z -+ H
to KCL to KCL
3.20 3.40 0.048
IN 18

01'
= 2 kQ
C
I:l lc 1"2 kQ
rL ,I

logic simulation.

simulation.
AU-H8R-E2 I Sheet 1/1 I Page 20-76
2-406
/ Tri -state Output & Schmitt Trigger Input Buffer (TTL Type '/
H8RU True) wi Noise Limit Resistance wi Pull-up Resistance 13
tup tdn
1. 79 0.13 2.98 0.11 X -+ IN
3.35 0.047 6.26 0.103 OT -+ X
(7.35) (15.02)
IN
OT
=cr- C
X
L -+ Z Z -+ L
2.00 6.62 0.105
(16.95) ,', (15.55)
Input Loading
OT 2
C 2 H -+ Z Z -+ H
to KCL to KCL
3.20 3.40 0.048
Output Driving (16.95) '1: (15.55)
IN 18

eB' =2 kQ
~
C
LSI
~
lc 1'.2 kQ

logic simulation.

simulation.
AU-H8RU-E2 I Sheet 111 I I Page 20-77
2-407
H8RD
I
Tri-state Output & Schmitt Trigger Input Buffer(TTL Type'l
True) wI Noise Limit Resistance wI Pull-down Resistance 13
tup tdn
1. 79 0.13 2.98 0.11 X ... IN
3.35 0.047 6.26 0.103 OT ... X
(7.35) (15.02)
.IN
OT
=cr- C
X
L ... Z Z ... L
2.00 6.62 0.105
(16.95) * (15.55)
Input Loading
OT 2
C 2 H ... Z Z ... H
to KCL to KCL
3.20 3.40 0.048
IN 18

cl
2 kQ
R
LSI
C
-
!:l lc 1'. 2 kO
,L ~

logic simulation.

simulation.
AU-H8RD-E2 I Sheet III I I Page 20-78'
2-408
IKC
Cell Symbol
I
CMOS Interface Clock Input Buffer(Inverter)
Pro~a,-ation Delay Parameter
I 4
tup tdn
1. 70 0.01 1.62 0.01 X ... CI
X ----{>o- CI
Input Loading
Output Driving
CI 200
AU-IKC-EI I Sheet I/l I Page 20-79
2-409
FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION -.L "AU" Version
IKCU
I
CMOS Interface Clock Input Buffer(lnverter)
with Pull-up Resistance I
I Number of BC
4
Cell Symbol Pro aRation Delay Parameter
tup tdn
1. 70 0.01 1.62 0.01 X .. CI
X
---1>-- CI
Parameter ~bol ryp(ns *
Input Loading
Output Driving
CI 200

are given by the maximum dell1Y mult~lier.
AU-IKCU-E1 I Sheet 1/1 I I Page 20-80
2-410
- FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION J AU Version
Cell Name I Function ~ Number of BC
I
CMOS Interface Clock Input Buffer(Inverter)
IKCD
Cell Symbol
Pr~a~ation Del~ Parameter
I4
tUIl tdn
1. 70 0.01 1.62 0.01 X -+ CI
X ---{>o- CI
Parameter Symbol lYPtns *
Input Loading
Pin Nallle Factor (J1.u)
Output Driving
CI 200
AU-IKCD-E1 I Sheet 1/1 I iPqe 20-81
2-411
FUJITSU CMOS GA:a: ARRAY UNIT CELL SPECIFICATION I "AU" Version
ILC
Cell Symbol
I
CMOS Interface Clock In~ut Buffer(True)
Pro a2ation Delav Parameter
I 6
tup tdn
1.53 0.01 2.12 0.01 X + CI
X -{>- CI
Parameter Symbol l"VP(ns *
Input Loading
Output Driving
CI 200
AU-ILC-El I Sheet 1/1 I (Page 20-82
2-412
ILCU
I
CMOS Interface Clock Input Buffer(True)
tup tdn
1.53 0.01 2.12 0.01 X + CI
X -{>-- CI
Input Loading
Pin Name Factor CLuJ
Output Driving
Pin Name Factor (Lu)
CI 200
AU ILCU-EI I Sheet 1/1 I I Page 20-83
2-413
Cell Name Function
ILCD
I
CMOS Interface Clock Input Buffer(True)
with Pull-down Resistance 1
I Number of BC
6
tup tdn
1.53 0.01 2.12 0.01 X -+ CI
X -[>-- CI
Input Loading
Output Driving
CI 200
are_~iven by the maximum del~ mult~lier.
AU-ILCD-El I Sheet 1/1 I -.iPage 20-84
2-414
02BF
Cell Symbol
I
Output Buffer (IOL=8mA True)
I 3
tup tdn
0.86 0.047 1.09 0.052 OT -+ X
(3.68) (4.21)
OT
-{>- X
Input Loading
OT 6
Output Driving


logic simulation.
AU-02BF-E2 I Sheet 1/1 I I Page 20-85
2-415
02RF
I
Output Buffer (IOL=8mA, True)
I Number of BC
I 4
tup tdn
3.75 0.047 7.21 0.056 OT -+ X
(6.57) (10.57)
OT -[>--- X
Parameter Symbol 1'yJ>insl*
Input Loading
OT 2
Output Driving


logic simulation.
AU-02RF-EI I Sheet 1/1 I Page 20-86
2-41~
04TF
Cell Symbol
I
Tri-state Output Buffer (IOL=8mA True)
I 6
tup tdn
1.21 0.047 2.09 0.052 OT'" X
(4.27) (5.47)
OT
--f1 C
X
L -+ Z Z ... L
to KCL to KCL C-+ X
2.55 2.32 0.054
(15.20) * (5.83)
Input Loading
OT 6
C 2 H-+ Z Z -+ H
to KCL to KCL
3.56 1.37 0.048

Measurement circui~s of propagation delay time
cH
2idl
R
LSI
C
-
W Ic l' = 2 ""
~ ~
(a> Measurement of tpd at LZ and ZL. (b) Measurement of tpd at HZ and ZH.

logic simulation.

simulation.
AU-04TF-E2 I Sheet 1/1 I I Page 20-87
2-417
'---FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION I AU Version
04RF
I Tri-state Output Buffer (IOL=8mA, True)
with Noise Limit Resistance 5 I
Ce 11 Symbo I Prollagation Delay Parameter
tup tdn
to KCL to KCL KCL2 CDR2 .Path
3.42 0.041 1.64 0.056 OT -+ X
(6.48) (11.28)
OT
-ty C
X
L-+ Z Z -+ L
to KCL to KCL C-+ X
2.69 1.12 0.056
(15.31) (11. 36)
*
Input Loading
OT 2
C 2 H .. Z Z .. H
to KCL to KCL
2.90 3.58 0.041
*

~R
= 2 kSl
1
LSI
C lc 02
kl2
,k .-L

logic simulation.

simulation.
AU-04RF-E1 I Sheet 111 I I Page 20-88
2-418
H6TF
Cell Symbol
I
Tri-state Output & Input Buffer (IOL=8mA True)
I 10
tup tdn
0.85 0.03 1.47 0.03 X 4 IN
1.21 0.047 2.09 0.052 OT 4 X
(5.21) (6.51)
IN
OT
=cr- C
X
L4 Z Z4 L
to KCL to KCL C4 X
2.55 2.32 0.054
(19.10) * (6.9l)
Input Loading
OT 6
C 2 H4 Z Z4 H
to KCL to KCL
3.56 1.37 0.048
IN 36

cl'
= 2 kQ
~
C
LSI
~
lc 1=2>0

logic simulation.

simulation.
AU-H6TF E2 I Sheet III I I Pal!:e 20-89
2-419
H6TFU
I
Tri-state Output & Input Buffer (IOL=8mA, True)
tup tdn
0.85 0.03 1.47 0.03 X .. IN
1.21 0.047 2.09 0.052 QT .. X
(5.21) (6.51)
IN
OT
=cr- C
X
L .. Z Z .. L
2.55 2.32 0.054
(19.10) * (6.91)
Input Loading
Pin Name Factor (.f.u)
OT 6
C 2 H .. Z Z .. H
to KCL to KCL
3.56 1.37 0.048
IN 36

Measurement circuits of p~opagation delay time
c:H LSI
~
R
C
-
2 kSl
LSI
lc
,I 1"""
Note: 1. The unit of KCL for paths QT, C to X is ns/pF.

logic simulation.

simulation.
AU-H6TFU-E2 I Sheet 111 I I Page 20-90
2-420
H6TFD
I
Cell Symbol ProIagation Delay Parameter
tup tdn
0.85 0.03 1.47 0.03 X ... IN
1.21 0.047 2.09 0.052 OT'" X
(5.21) (6.51)
IN
OT
=cr- C
X
L ... Z Z ... L
2.55 2.32 0.054
(19.10) (6.91)
*
Input Loading
OT 6
C 2 H ... Z Z ... H
to KCL to KCL
3.56 1.37 0.048
(6.91)
IN 36

cl'
= 2kS2
t"
LSI
C lc kll
~ ~
Note: 1- The unit of KCL for.paths OT, C to X is ns/pF.

logic simulation.

simulation.
AU-H6TFD-E2 I Sheet 1/1 I I Page 20 91
2-421
FUJITSU CMOS GATE ARRAy'-UNIT CELL SPECIFICATION I AU Version
H6CF
I
Tri-state Output & CMOS Interface Input Buffer
(IOL=8mA True) 8 I
tup tdn
0.74 0.03 1.07 0.03 X .. IN
2.39 0.047 4.30 0.051 OT" X
(6.39) (8.64)
IN
OT
=cr- C
X
L" Z ZoO L
to KCL to KCL C oO X
2.63 3.93 0.051
(18.72) * (8.27)
Input Loading
OT 4
C 2 H" Z Z ... H
to KCL to KCL
3.40 2.50 0.047
IN 36

cHR='~
LSI
;L
C

LSI
,I
lc
1='' '
Note: 1- The unit of KcL for paths OT, C to X is ns/pF.

logic simulation.

simulation.
AU-H6CF-E1 I Sheet 1/1 I I Page 20-92
2-422
FUJITSU CMOS GATE ARRAY""UNiT CELL SPECIFICATION I AU Version
H6CFU
I
with Pull-up. Resistance (IOL=8mA~ True) 8 I
Cell Symbol Propa.l!;ation Delay Parameter
tup tdn
0.74 0.03 1.07 0.03 X -+ IN
2.39 0.047 4.30 0.051 OT -+ X
(6.39) (8.64)
IN
OT
=cr- C
X
L-+ Z Z -+ L
to KCL to KCL C-+ X
2.63 3.93 0.051
(18.72) * (8.27)
Input Loading
OT 4
C 2 H -+ Z Z -+ H
to KCL to KCL
3.40 2.50 0.047
IN 36

cl'
= 21d2
I
~
.c
I LSI I
~
lc 1
02
.0

logic simulation.

simulation.
AU-H6CFU-El I Sheet 1/1 I I Pa.l!;e 20-93
2-423
FUJITSU CMOS ~ATE ARRAY UNIT CELL SPECIFICATION I "AU" Version
Cell Name Function
H6CFD
I
with Pull-down Resistance (IOL=8mA True)
I Number of BC
8 I
Cell Symbol Pro):agation Delay Parameter
tup tdn
0.74 0.03 1.07 0.03 X + IN
2.39 0.047 4.30 0.051 OT + X
(6.39) (8.64)
~
IN
OT X
C
L+Z Z+ L
to KCL to KCL C+ X
2.63 3.93 0.051
(18.72) * (8.27)
Input Loading
OT 4
C 2 H+ Z Z+H
to KCL to KCL
3.40 2.50 0.047
Pin Name Factor (lu) *
IN 36

oIR'2~
LSI
C
LSI
lc .;~R=2kn
~ ,I rTT7

logic simulation.
simulation.
AU-H6CFD-El I Sheet 1/1 I I Page 20-94
2-424
FUJITSU:CI'10S GATE ARRAY UNIT CELL SPECIFICATION I AU Version
H8TF
I
& Input Buffer (IOL=8mA True) 9 I
tUjl tdn
0.85 0.03 1.47 0.03 X .. IN
3.42 0.047 7.64 0.056 OT" X
(7.42) (12.40)
IN
OT
=er- C
X
L .. Z Z .. L
2.69 7.72 0.056
(19.69) (12.48)
*
Input Loading
OT 2
C 2 H" Z Z .. H
to KCL to KCL
2.90 3.58 0.047
IN 36

cr!'-
LSI
~
C
21d2
LSI
Ic
rL
l'=lldl

logic simulation.

simulation.
AU-H8TF-El I Sheet 1/1 I I Page 20-95
2-425
FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION 1 "AU" Version
H8TFU
I
& Input Buffer(IOL=8mA True) with Pull-up Resistance 9 I
Cell Symbol Proj:agation Delay Parameter
tup tdn
0.85 0.03 1.47 0.03 X -+ IN
3.42 0.047 7.64 0.056 OT -+ X
(7.42) (12.40)
IN
OT
=cr- C
X
L -+ Z Z -+ L
to KCL to KCL C-+ X
2.69 7.72 0.056
(12.48)
(19.69) *
Input Loading
OT 2
C 2 H -+ Z Z -+ H
to KCL to KCL
2.90 3.58 0.047
IN 36
* These value,S are subject to external loading condition.

cl
= 21d2
rL
R
C
LSI
lc
;L
t·, .

logic simulation.

simulation.
AU-H8TFU-E1 I Sheet 1/1 I I Page 20-96
2-426
Cell Name J Function I Number of BC
H8TFD
I
& Input Buffer(IOL=8mA, True) with Pull-down Resistance 9
I
Cell Symbol ProJagation Delay Parameter
tup tdn
0.85 0.03 1.47 0.03 X" IN
3.42 0.047 7.64 0.056 OT .. X
(7.42) (12.40)
IN
OT
=er- C
X
L" Z Z .. L
2.69 7.72 0.056
(19.69) (12.48)
*
Input Loading
OT 2
C 2 H .. Z Z .. H
to KCL to KCL
2.90 3.58 0.047
IN 36

cl
2kl2
R
-
I:l
LSI
~
C

Ic
,.I 1-"·

logic simulation.

simulation.
AU-H8TFD-El I Sheet 1/1 I I Page 20-97
2-427
H8CF
I
Tri-state Output Buffer with Noise Limit Resistance
& CMOS Interface Input Buffer (IOL=8mA True)
I Number of BC
9 I
tup tdn
to KCL to KCL KCL2 CDR2. Path
0.74 0.03 1.07 0.03 X -+ IN
3.42 0.047 7.64 0.056 OT -+ X
(7.42) (12.40)
=tr-
IN
OT X
L-+ Z Z -+ L
2.69 7.72 0.056
(19.69) * (12.48)
Input Loading
OT 2
C 2 H-+ Z Z -+ H
to KCL to KCL
2.90 3.58 0.047
IN 36

c=HLSI
R
C
-
21d2
~R"~ rIC
~

logic simulation.

simulation.
AU-H8CF-El I Sheet 1/1 I I Page 20-98
2-428
Tri-state Output Buffer wI Noise Limit Resistance
& CMOS Interface Input Buffer(IOL=8mA, True)
H8CFU wI Pull-up Resistance 9
Cell Symbol Pro a2ation Delay Parameter
tup tdn
0.74 0.03 1.07 0.03 X -+ IN
3.42 0.047 7.64 0.056 OT -+ X
(7.42) (12.40)
IN
OT
=cr- C
X
L-+ Z Z -+ L
2.69 7.72 0.056
(19.69) * (12.48)
Input Loading;
OT 2
C 2 H-+ Z Z-+H
to KCL to KCL
2.90 3.58 0.047
Output Driving; (19.69) * (12.48)
IN 36
* These values are subject to external loading; condition.

= 21dZ
c=H' ~
C
LSI
,I
lc 1"2 1d2

logic simulation.
3, The parameters in parentheses are the values applied to the

simulation.
AU-H8CFU-E1 I Sheet 1/1 I I Page 20-99
2-429
Cell Name Function N~ber of BC
Tri-state Output Buffer wI Noise Limit Resistance
& CMOS Interface I~put Buffer(IOL=8mA, True)
H8CFD wI Pull-down Resistance 9
Cell Svmbol ProJagation Delay Parameter
tup tdn
0.74 0.03 1.07 0.03 X ... IN
3.42 0.047 7.64 0.056 CT'" X
(7.42) (12.40)
IN
OT
=cr- C
X
L ... Z Z ... L
2.69 7.72 0.056
(19.69) (12.48)
*
Input Loading
OT 2
C 2 H ... Z Z ... H
to KCL to KCL
2.90 .3.58 0.047
IN 36

~R'2 kS2
LSI
~
C
LSI
~
lc 1". ,.lI
Note: 1. The unit of KcL for paths CT, C to X is ns/pF.

logic simulation.
simulation.
AU H8CFD-E1 I Sheet 1/1 I I Page 20-10(
2-430
FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION I " AU " Version
Cell Name I Function Number of Be
02S2
Output Buffer (IOL=24mA, True)
I 3
rup tdn
Path
to KCL to KCL KCL2 CDR2
3.60 0.024 7.69 0.041 OTtoX
(5.04) (10.15)
OT-{>-X
Parameter Symbol Typ(ns) •
Input Loading
OT 2
IfI
Output Driving
• Minimum values for the typical operating condition.

The values for the worst case operating condition are given by the maximum delay
multiplier.

2. Output load capac~ance of 60 pF is used for Fujitsu's logic simulation.
AU-02S2-E1 I Sheet 1/1 I

I Page 20-101
2-431
FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION I . AU • Version
Cell Name Function NumberofBC
0482
Cell Symbol
Tri-state Output Buffer (IOL=24mA. True)
Propagation Delay Parameler
I 4
tup teln
Path
3.60 0.024 7.90 0.041 OTto X
(5.16) (10.56)
m---tr' C
LtoZ
to
ZtoL
KCL
to KCL CtoX
3.82 8.12 0.042
(18.72) * (10.85)
Input Loading
OT 2
C 2 HtoZ ZtoH
to KCL to KCL
6.43 3.83 0.024
* These values are subject 10 external loading condition.

'Measurement circuits 01 propagation delay time
at LZ. ZL, HZ and ZH are as lollows:
DI ,.,~
l'
LSI LSI ~ R=2Kn
>
~C
".,77
(a) Measurement 01 tpd at LZ and ZL. (b) Measurement 01 tpd at HZ and ZH.
Note: 1. The unn 01 KCL is nslpF.

2. Output load capacnance 0165 pF is used lor Fujitsu's logic simulation.
Au-04S2-El Sheet 1/1 I

I Page 20-102
2-432
FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION I . AU • Version
Cell Name I Function NumberofBC
HBW2
Cell Symbol
Tri-state Output & Input Buffer (IOL=24mA)
with Noise Limit Resistance and Input Buffer (TTL, True)
I 8
IUp !dn
Path
to KCL to KCL KCl2 CDR2
0.85 0.03 1.47 0.03 XtolN
3.60 0.024 7.90 0.041 OTto X
(5.86) (11.39)
'"~
aT x
C
LtoZ ZtoL
to KCL 10 KCL CtoX
3.82
(22.50) . 8.12
(11.69)
0.042
Inpul Loading
aT 2
C 2 HtoZ ZtoH
to KCL 10 KCL
Pin Name
Oulput Driving
Factor (Iu)
6.43
(22.50) . 3.83
(11.69)
0.024
IN 36
• These values are subject to external loading condition.

Measurement circuHs 01 propagation delay time
at LZ, ZL, HZ and ZH are as lollows:
DI"'~
LSI
,Ic
LSI
Ic ~ R=2Kn
,I ""77
(a) Measurement 01 tpd at LZ and ZL. (b) Measurement 01 tpd at HZ and ZH.
Note: 1. The unH 01 KCL lor paths OT, C to X is nslpF.

2. Output load capacHance 0185 pF is used lor Fujitsu's logic simulation.
3. The parameters in parentheses are the values applied to the Simulation.
AU-H8W2-E1 Sheet 1/1

I Page 20-103
2-433
FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION I " AU "Version
Cell Name Function, Number of BC
HBE2 with Noise Limit Resistance and Input Buffer (CMOS, True)
8
\up !dn
Path
0.74 0.03 1.07 0.03 XtolN
3.60 0.024 7.90 0.041 OTto X
(5.86) (11.39)
"~
OT X
C
ltoZ ZtoL
to KCL to KCL CtoX
3.82
(22.50) . 8.12
(11.69)
0.042
Input Loading
OT 2
C 2 H toZ Zto H
to KCL to KCL
Pin Name
Output Driving
Factor (Iu)
6.43
(22.50) . 3.83
(11.69)
0.024
IN 36

Measurement circuijs of propagation delay time
DI""~
LSI
,IC
LSI
Ic
•
•
R=2Kn
,I m77
(a) Measurement of tpd at LZ and ZL: (b) Measurement of tpd at HZ and ZH.
Note: 1. The unit of KCL for paths OT, C to X is nslpF.

2. Output load capacijance of 85 pF is used for Fujitsu's logic simulation.
AU-H8E2-E1 Sheet 1/1

I Page 20-104
2-434
FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION I .. AU .. Version
Cell Name Function Numbero. BC
HBW1 with Noise Limit Resistance and Input Buffer (TIL, True) 8
with Pull-up Resistance
IUp tdn
Path
to KCl to KCl KCL2 CDR2
0.B5 0.03 1.47 0.03 Xto IN
3.60 0.024 7.90 0.041 OTto X
(5.B6) (11.39)
"=tr-
OT
C
X
to
ltoZ
KCL to
Ztol
KCL CtoX
3.B2
(22.50) . B.12
(11.69)
0.042
Input Loading
OT 2
C 2 HtoZ ZtoH
to KCl to KCL
Pin Heme
Output Driving
Factor (Iu)
6.43
(22.50) . 3.B3
(11.69)
0.024
IN 36
CJ4
Measurement circu"s of propagation delay time
R_'~
lSI LSI ~ R=2Kn
lc
I C
I "-'77
Note: 1. The un" of KCl for paths OT, C to X is nsfpF.

2. Output load capacitance of B5 pF is used for Fujitsu's logic simulation.
3. The parameters in parentheses are the values applied to the Simulation.
AU-HBW1-E1 Sheet 1/1

I Page 20-105
2-435
FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION I • AU • Version
Cell Nam. Function NumberofBC
H8E1 with Noise Limit Resistance and Input Buffer (CMOS, True) 8
Cell Symbol ProjIBgatlon Delay Parameter
tup tdn
Path
0.74 0.03 1.07 0.03 XtolN
3.60 0.024 7.90 0.041 OTto X
(5.86) (11.39)
"=tr-
OT
C
X
to
LtoZ
KCL to
ZtoL
KCL Cto X
3.82
(22.50) . 8.12
(11.69)
0.042
Input Loading
OT 2
C 2 HtoZ ZtoH
to KCL to KCL
Pin Name
Output Driving
Factor (Iu)
6.43
(22.50) . 3.83
(11.69)
0.024
IN 36

Measurement circu~s of propagation delay time
DI""~
LSI
,IC
LSI
lc :
R=2Kn
,I ","77
Note: 1. The unH of KCL for paths OT, C to X is nslpF.

2. Output load capacHance of 85 pF is used for Fujitsu's logic simulation.
AU-H8E1-E1 Sheet 1/1 I

I Page 20-106
2-436
FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION I " AU "Version
HBWO with Noise Limit Resistance and Input Buffer (TTL, True) 8
!up tdn
Path
0.85 0.03 1.47 0.03 XtolN
3.60 0.024 7.90 0.041 OTtoX
(5.86) (11.39)
"=tr-
OT
C
X
to
Ltel
KCL to
lte L
KCL CtoX
3.82
(22.50) . 8.12
(11.69)
0.042
Inpul Loading
Pin Name Faclor (Iu)
OT 2
C 2 H tel lie H
to KCL 10 KCL
Pin Name
OUlpul Driving
Faclor (Iu)
6.43
(22.50) . 3.83
(11.69)
0.024
IN 36

DI "~'"'
LSI LSI
lc
~ R"2Kn
,IC
,I rrl77
(a) Measurement of tpel at LZ and ZL. (b) Measurement of tpel at HZ and ZH.

2. Output load capacitance of 85 pF is used for Fujitsu's logic Simulation.
AU-H8Wo-E1 Sheet 1/1 I

I Page 20-107
2-437
FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION J " AU " Version
Cell Name Function NumberolBC
H8EO with Noise Limit Resistance and Input Buffer (CMOS. True)
8
Cell Symbol PropagaUon Delay Parameter
\up !dn
Path
0.74 0.03 1.07 0.03 XtolN
3.60 0.024 7.90 0.041 OTtoX
(5.86) (11.39)
"~
OT X
C
LtoZ Zto L
to KCL to KCL Cto X
3.82
(22.50) . 8.12
(11.69)
0.042
Input Loading
OT 2
C 2 HtoZ Zto H
to KCL to KCL
Pin Name
Output Driving
Factor (Iu)
6.43
(22.50) . 3.83
(11.69)
0.024
IN 36

C}f ".,~
~
LSI LSI R=2Kn
Ic '\
,IC
,I rrln
(a) Measurement of Ipd at LZ and ZL. (b) Measurement of tpd at HZ and ZH.
2. Output load capacitance of 85 pF is used for Fujitsu's logic simulation.

AU-H8EO-E1 I Sheet 1/1 I

I Page 20--108
2-438
SINGLE-PORT RAM SPECIFICATION
FEATURES
Configurable size
Non-clocked static RAM
• 1 address - 1 Read/Write port
SPECIFIC PARAMETERS
Word size range: 4to 2K words
• Bit size range: 1 to 72 bits
BLOCK DIAGRAM
AOO BL.
I MEMORY MATRIX PRE.
A(H)
ADD.
WE - - - - I WE,RE
RE BUFFER
DOO - 0 (b-1) 100 - I (b-1)
ADD. BUF. Address Buffer BLPRE. Bft Une PrlH:harge

ROW DEC. Row Decoder ATD Address Transftion Detector
COL DEC. Column Decoder RE RAM Enable Input
ADO - A (H) Address Input WE Write Enable Input
100 -I (b-1) Data Input DOO - 0 (b-1) Data Output
2-439
AU Series Unit Cell Ubtary CMOS Channe/less Gate Arrays
TIMING DIAGRAMS
READ CYCLE1
•
Address
~v
----J ~ ________________________- '~V, __________
(A) /~ /~
Data
Output
(D) /><XXXXX)<)( Data Valid
~--------------
)K X
Read Cycle: Address Controlled 2
•
RAM
Enable
(RE)
Data
Output Data Valid
(D)
Read Cycle: RE Controlled3
Notes: 1WE is High for Read Cycle.

2RE is Low for Address Controlled Read Cycle.
3Address must be valid prior to or coincident with RE transition Low.
2-440
CMOS Channel/ass Gate Arrays AU Series Unit Cel/ Library
TIMING DIAGRAMS (Continued)

WRITE CYCLE1
twc
Address
(A)
-------...)/,
----J ' -________________________- ' ;,
'- /
, _________
tRW
RAM ",,<,,."',,,, '",''-'.., "" '" \, \"",,, ""'~

Enable "'><, ""~,,,
~"" .... ~II"~"",,,: '""~'<\"",,,
"~ ~I~ ~\,.- .............. 1,'1) "'.,.""':"""',>0~'" 1._'
\ , I, ..., , , ~'I
(RE)
twp tWR
Wr~e
Enable
(WE)
tOH
Data
Input
(I) _ _ _ _ _ _ _ _ _ _ _ _- J )K Data
' ______ __ Valid
_ I.-____ )K
~ ~-----
WrHe cycle: WE Controlled2
twc
Address
(A)
• • tWR
• •
RAM
Enable
(RE)
Wr~e
Enable
(WE)
tow
Data
Input Data Valid
(I)
Write cycle: RE Controlled 3
Notes: 1The Data Output (D) is invalid in the Write mode.

:WE must be high during address trans~ions.
3RE must be high during address tran·sitions.
2-441
CELL SYMBOL AND CELL SPECIFICATION

RAMxx I Single Port SRAM (w word x b bit)
I 1
tup !dn
100 - -000 Path
101 - -001 10 I<cL 10 I<cL 1<cL2 COA2
102 -
~
-002
A -S
. 0.07 . 0.04 0.07 7 A~D
I (b-1) - 1 -D(b-1)
RE~D
AOO -
A01 -
~ A-s
A (\-1) - 1
WE -(l
RE -(l
Input Loading
til
Parameter Symbol Typ (ns)"
Read Cycle lime tAC
A4'" 1
14*** 1 Address Access lime tAA
WE 1
RE RAM Enable Access lime tAA
1
Output Hold from Address Change IoH
Output Hold from RAM Enable Change tAH
Write Cycle lime twc
RAM Enable to End of Write tAW
Address Valid to End of Write lAw
Output Driving Address Setup time lAs
Pin Name Factor (Iu) Write Pulse Width twp
04*** Data Setup lime low

36
Write Recovery lime tWA
.
Data Hold lime IoH
Refer to the Read Mode and Write Mode Tables on the following
pages.
The values for the worst case operating condition are given by
the maximum delay multiplier.
The values indicated here depend on bit-word organization and
are given in the Read Mode and Write Mode Delay lime Tables
on the following pages.
'" Pin Name
When b ort" 10, these pin names are described with two char-
acters: e.g., A9.
2-442
CMOS Channelless Galli Arrays AU Series Unit Cell Ubtaty
BASIC DELAY TIME

Read Mode
Symbol Parameter Equation (Typical Value) Unit

c-l: 0.0024' w + 0.0044' b+ 21.07
c=2: 0.0010' w + 0.0110' b + 21.10
lAC Read Cycle lime ns
c-4: 0.0006'w + 0.0176' b+ 21.12
c=8: 0.0003'w + 0.0341' b+ 21.02
c-l: 0.0024'w + 0.0044 * b+ 20.14
c=2: 0.0010' w + 0.0110 * b + 20.30
IAA Address Access lime ns
c=4: 0.0006 * w + 0.0176 * b + 20.36
c-8: 0.0003'w + 0.0341*b+ 20.36
c_l: 0.0051 * w + 0.0140 * b + 18.29
c-2: 0.0006 * w + 0.0077* b+ 19.49
IRA RAM Enable Access lime ns
c-4: 0.0003 * w + 0.0143 * b + 19.49
c-8: 0.0002* w + 0.0286 * b+ 19.55
c= 1: 0.0018' w + 0.0140 * b + 5.38
c=2: 0.0009'w + 0.0286 * b + 5.38
tOH Outpul Hold from Address Change c.4: ns
0.0004 'w + 0.0572' b + 5.38
c=8: 0.0002' w + 0.1140' b + 5.38
c= 1: 0.0010 * b + 2.84
c=2: 0.0020 * b + 2.84
IRH OUlpul Hold from RAM Enable Change ns
c=4: 0.0040' b+ 2.84
c=8: 0.0079' b+ 2.84
Example
To find the delay time for the read-mode parameters for a Single-port RAM of 512 words,
16 bits, and c 4:=
tRC - 0.0006' w + 0.0176' b+ 21.12
0.0006 * 512 + 0.0176 * 16 + 21.12
21.71 ns
tAA 0.0006 * w + 0.0176 * b + 20.36

= 0.0006' 512 + 0.0176 * 16 + 20.36
= 20.95 ns
IRA = 0.0003' w + 0.0143' b + 19.49

- 0.0003' 512 + 0.0143' 16 + 19.49
19.87 ns
IoH = 0.0004' w + 0.0572' b + 5.38

0.0004' 512 + 0.0572' 16 + 5.38
6.50 ns
IRH 0.0040 • b + 2.84

0.0040 • 16 + 2.84
2.90ns
2-443
AU Series Unit Cel/ Ubrary CMOS Channel/ess Gate Anays
BASIC DELAY TIME (Continued)

Write Mode

c= 1: 0.0024' w + 0.0044' b + 21.07
c_2: 0.0010' w + 0.0110' b + 21.10
twc Write Cycle Time ns
c-4: 0.0006' w + 0.0176' b + 21.12
c=8: 0.0003' w + 0.0341' b + 21.02
c -1: 0.0024' w + 0.0033' b + 14.63
c=2: 0.0010' W + 0.0066' b + 14.63
tRW RAM Enable to End of Wr~e ns
c-4: 0.0006' w + 0.0110'b + 14.63
c=8: 0.0003' w + 0.0220 'b + 14.63
c-l: 0.0024' w + 0.0033' b + 17.93
c-2: 0.0010' W + 0.0066' b + 17.93
tAW Address Valid to End of Wrne ns
c=4: 0.0006' W + 0.0110' b + 17.93
c=8: 0.0003' w + 0.0220' b + 17.93
c = 1: 3.30
c=2: 3.30
tAS Address Setup Time 3.30 ns
c=4:
c=8: 3.30
c= 1: 0.0070' W + 0.0022' b + 10.Q1
c=2: 0.0035' w + 0.0044' b + 10.01
twp Write Pulse Width 10.Q1 ns
c=4: 0.0018' w + 0.0088' b +
c=8: 0.0009' w + 0.0176' b + 10.01
c= 1: 0.0070' w 8.38
c=2: 0.0035' W 8.38
tow Data Setup Time ns
c=4: 0.0018' w 8.38
c=8: 0.0009' W 8.38
c= 1: 0.0011 'b + 3.14
c=2: 0.0044' b + 3.14
tWR Write Recovery Time ns
c=4: 0.0066' b + 3.14
c=8: 0.0121' b + 3.14
c= 1: 0.0094' b + 3.51
c=2: 0.0187' b + 3.51
tOH Data Hold Time ns
c=4: 0.0374' b + 3.51
c=8: 0.0748' b + 3.51
Example
To find the delay time for the write-mode parameters for a single-port RAM of 512 words,
16 bits, and c = 4:
tRC = 0.0006' W+ 0.0176' b+ 21.12 twp 0.00 ' w + 0.0088 ' b + 10.01
0.0006' 512 + 0.0176' 16 + 21.12 0.001 B' 512 + 0.0088' 16 + 10.01
21.71 ns 11.07ns
tRW = 0.0006' w + 0.0110' b+ 14.63 tow 0.0018' w + 8.38

= 0.0006' 512+ 0.0110 '16 + 14.63 = 0.0018' 512 + 8.38
= 15.11 ns 9.30 ns
tAW = 0.0006' w+O.Oll 0' b + 17.93 tWA = 0.0066' b + 3.14

0.0006' 512 + 0.0110 '16 + 17.93 = 0.0066'16+3.14
18.41 ns = 3.25ns
3.30 ns tOH - 0.0347' b + 3.51

- 0.0347'16+3.51
- 4.11 ns
2-444
Cmos Channelless Gate Arrays AU Series Unit Cell Ubrary
DUAL-PORT RAM SPECIFICATION
FEATURES
Configurable size
• Non-clocked Static RAM
• 2 address - 2 Read/Write port
SPECIFIC PARAMETERS
• Word size range: 4 to 2K words
BLOCK DIAGRAM
WEI REIA AOO~ 100~ JOO~ BOO~ RERB WEJ

A (1)-1) 1(1)-1) J (1)-1) B(1)-1)
ADD. BUF. Address Buller COL.SEL. Colurm Select

ROW DEC. Row Decoder SEN. AMP. Sense AMP.
COL. DEC. Column Decoder WRI.AMP. Write AMP.
!ADO ~ IA (\-1) Address Inpul ATD Address Transftion Detector
JBOO - JB (\-1) Address Input REIA,RERB RAM Enable Inpul
PRECHA. BI line Pr&-Chalge WEI,WEJ Write Enable Input
AOO-A(b-1) Data Output BOO - B(1)-1) Data Output
100-1(1)-1) Data 1'1lUI JOO-J(1)-1) Data 1'1lUI
2-445
AU Series Unit Cell Ubrary CMOS ChanneJ/ess Gate Arrays
TIMING DIAGRAMS
Only when both ports are in READ mode can one address be accessed by two ports in one cycle.
READCYCLE1
Address
(IA)
(JB)
Data
Output
(A)
(B)
Data Valid
x
III RAM
Enable
(REIA)
(REJB)
Dala
Output Data Valid
(A)
(B)
Notes: 1WE is High for Read Cycle.

2-446
Cmos Channel/ess Gate Arrays AU Series Unit Cell Ubrary

WRITE CYCLE1
twe
Address ~V ~V
~~~----------------~/~~-----
(IA.JB)
tRW
RAM
Enable
(REIA)
(REJB)
tAS twp tWR
Write
Enable
(WEI)
\? - - - - - " V
(WEJ) tow tOH
Data
Input
(I) ____________ ~ /
~(
"_______
Data Valid "V
~~----J/,~----
(J) I
Write cycle: WE Controlled 2
twe
Address
(IA.JB) ===>K~ ______________~)K~_____
.. .. tWR
RAM
.. ..
Enable
(REIA) " V
(REJB) ,"------:----/
twp
Write
Enable
(WEI)
(WEJ) tow tOH
Data
Input
(I) -----+-/ )K Data Valid )(
'------
(J)
Notes: 'The Data Output (D) is invalid in the Write mode.

2WE must be high during address transnions.
3RE must be high during address transitions.
2-447
AU Series Unit Cell Ubra!y CMOS Channel/ess Gate Arrays

Ceo Name I Function I Number of BC
RAMxx I DUAL Port Static RAM (w word x b bit)

I 1
CeRSymbol Propagation Delay Parameter
tup !dn
100
101
-- f-- AOO
f-- AD1 10 KcL 10 Kct. Kcu COR2
Path
A '$ J::;
?'
I (b-1)
JOO
-- f-- A (b-1)
f-- BOO
" 0.07 " 0.04 0.07 7 A~
JB~
A
B
J01 ~ f-- 801 REIA -)A
'$ J::; ;, REJB-)B
J(b-1) - f-- B(b-l)
IAOO -
IA01 ~
'$
IA(t-1) -
JBOO-
J801 ~'$
JB(t-1) -
REIA-o
REJB-o
WEI-o
WEJ-o
Input Loacing Parameter Symbol Typ (ns)""

Read Cycle Time lAC
I"" 1
J*** 1 Address Access Time IAA
IA*·* 1 RAM Enable Access Time
JB··· 1 IRA
RE 1 Output Hold from Address Change toH
WE 1
Output Hold from RAM Enable Change tRH
Write Cycle Time !we
RAM Enable to End of Write tRW
Address Valid to End of Write lAw
Output Driving Address Setup time lAs
Pin Name Factor (Iu) Write Pulse Width twp
Data Setup Time low
A··· 36
B""" 36 Write Recovery Tune tWR
Data Hold Time foH
" Reier to the Read Mode and Write Mode Tables on the foRowing
pages.
"" Minimum values for the typical operating condition.
The values to be incicated here depend on bit-word organiza-
tion and are given by the Read Mode and Write Mode Delay
Time Tables on the foRowing pages.
""" Pin Name
When boris 10, these pin names are described with two char-
acters: e.o .. A9
2-448
Cmos ChannelJess Gate Arrays AU Series Unit Cell Ubrary
BASIC DELAY TIME

Read Mode
Symbol Parameter equation (1\'plcal Value) Unit

c-l: 0.0024"w + 0.0044" b+ 22.07
c-2: 0.0010"w + 0.0110" b + 22.10
tRe Read Cycle lime c-4: 0.0006" w + 0.0176 ·b+ 22.12 ns
c-8: O.0003"w + 0.0341" b+ 22.02
c-l: 0.0024" w + 0.0044" b+ 21.14
c-2: 0.0010"w + 0.0110" b + 21.30
1M Address Access lime 0.0006"w + 0.0176" b+ 21.36 ns
c-4:
c-8: O.0003"w + 0.0341" b+ 21.36
c-l: 0.0051" w + 0.0140" b+ 19.29
c-2: 0.0006"w + 0.0077" b+ 20.49
tRA RAM Enable Access lime c_4: O.0003"w + O.Ol43"b+ 20.49 ns
c-8: 0.0002" w + 0.0286" b+ 20.55
c-l: 0.0018" w + 0.0140· b + 5.38
c_2: 0.0009· w + 0.0286· b + 5.38
IoH Output Hold from Address Change ns
c-4: 0.0004· w + 0.0572· b+ 5.38
c-8: 0.0002· w + 0.1140· b + 5.38
c _1: 0.0010· b + 2.84
c-2: 0.0020· b+ 2.84
tRH Output Hold from Ram Enable Change ns
c-4: 0.0040· b+ 2.84
c-8: 0.0079· b+ 2.84
Example
To find the delay time for the write-mode parameters for a dual-port RAM of 512 words,
16 bits, and c =4:
tRC 0.0006· w + 0.0176· b + 22.12

0.0006·512 + 0.0176·16+22.12
= 22.71 ns
tM 0.0006· w+0.0176 • b + 21.36

0.0006·512 + 0.0176· 16 + 21.36
- 21.95 ns
tRA = 0.0003· w + 0.0143 • b + 20.49

= 0.0003·512 + 0.0143 ·16 + 20.49
20.87 ns
tOH - 0.0004· w + 0.0572 • b + 5.38

0.0004·512 + 0.0572 ·16 + 5.38
= 6.50 ns
tRH 0.0040 • b + 2.84

- 0.0040· 16 + 2.84
2.90 ns
2-449
AU Series Unit Ce//Ubrary CMOS Channe/less Gate Arrays
Write Mode
c= 1: 0.0024 * w + 0.0044 * b+ 22.07

twc Write Cycle Time c-2: 0.0010 * w + 0.0110 * b + 22.10 ns
c=4: 0.0006 * w + 0.0176 * b + 22.12
c=8: 0.0003 * w + 0.0341 * b + 22.02
c-l: 0.0024 * w + 0.0033 * b+ 15.63
c=2: 0.0010 * w + 0.0066 * b+ 15.63
tRW RAM Enable to End of Wrtte ns
c-4: 0.0006 * w + 0.0110 * b + 15.63
c.8: 0.0003 * w + 0.0220 * b + 15.63
c = 1: 0.0024 * w + 0.0033 * b + 18.93
c-2: 0.0010 * w + 0.0066 * b+ 18.93
tAW Address Valid to End of Write ns
c=4: 0.0006 * w + 0.0110 * b + 18.93
c=8: 0.0003*w + 0.0220 * b+ 18.93
c= 1: 3.30
c=2: 3.30
tAS Address Setup Time ns
c=4: 3.30
c= 8: 3.30
c= 1: 0.0070* w + 0.0022 * b+ 11.01
c=2: 0.0035* w + 0.0044 * b+ 11.01
twp Write Pulse Width ns
c=4: 0.0018 * w + 0.0088 * b+ 11.01
c= 8: 0.0009* w + 0.0176 * b + 11.01
c= 1: 0.0070* w 9.38
c=2: 0.0035* w 9.38
tow Data Setup Time ns
c=4: 0.0018* w 9.38
c= 8: 0.0009* w 9.38
c= 1: 0.0011 * b + 3.14
c=2: 0.0044 * b+ 3.14
tWR Write Recovery Time ns
c=4: 0.0066 * b + 3.14
c=8: 0.0121 * b + 3.14
c= 1: 0.0094 * b+ 3.51
c=2: 0.0187 * b + 3.51
c=4: 0.0374 * b+ 3.51
c= 8: 0.0748 * b+ 3.51
Example
To find the delay time for the write-mode parameters for a dual-port RAM of 512 words, 16 bits and c = 4:
twe 0.0006 * w + 0.0176 * b + 22.12 twp = 0.0018 * w + 0.0088 * b + 11.01

0.0006 * 512 + 0.0176 * 16 + 22.12 0.0018 * 512 + 0.0088 * 16 + 11.01
22.71 ns = 12.07 ns
tRW 0.0006 * w + 0.0110 * b + 15.63 tow 0.0018 * w + 9.38

0.0006 * 512 + 0.0110 * 16 + 15.63 = 0.0018 * 512 + 9.38
= 16.11 ns 10.30 ns
tAW
=
0.0006 * w + 0.0110 * b + 18.93
0.0006 * 512 + 0.0110 *16 + 18.93
tWR - 0.0066 * b + 3.14
= 0.0066 * 16 + 3.14
19.41 ns = 3.25 ns
tAS = 3.30 ns tOH 0.0347 * b + 3.51

= 0.0347 * 16 + 3.51
= 4.11 ns
2-450
TRIPLE-PORT RAM SPECIFICATION

FEATURES
• Configurable word/bit organization
• Non-clocked static RAM
• 3 addresses - 2 Read ports and 1 ReadlWrite port
SPECIFIC PARAMETERS
• Word size range: 4 to 2048 words
• Total bit size range: 64 to 18K bits
BLOCK DIAGRAM
RERB BOO - 100 - ADO - coo - RERC

B (bo-l) I (b-l) A (b-l) C (bo-l)
ADD. BUF. Address Buffer PRECHA. Pre-Charge

ROW DEC. Row Decoder COL.SEL. CokJmn Select
COL. DEC. CokJmn Decoder SEN. AMP. Sense AMP.
IADO - IA (H) Address II1lUI WRI.AMP. Write AMP.
RBOO - RB (H) Address Input ATD Address Transftion Detector
ReOO - RC (H). Address II1lUI RERA,RERB,RERC .RAM Enable Input
WEI Write Enable Input ADO - A (bo-l) Data OUtput
BOO-B(b-l) DalaOUtput coo - C (bo-l) DalaOUtput
100 - I (bo-l) Dala Input
2-451
TIMING DIAGRAMS
READCYCLE1
tRe
Address
(IA)
(RB)
(RC)
Data
Output
(A)
(8)
(C)
Data Valid
x
•
RAM
Enable
(REIA)
(RERB)
(RERC)
Data
Output Data Valid
(A)
(B)
(C)
Notes: 'WEI is High for Read Cycle.

2-452

WRITE CYCLE1
twe
Address
(lA, RB, RC) ===>K~ ________________~)K~_____
RAM
Enable
(REIA, RERB,
RERC)
twp tWR
Write
Enable
(WEI)
~r\.
~-----'
,//
tow IOH
"<
Data
Input
(I) / )(
Dala Valid
' - - - - - . 1 - - - - / '-----
Write cycle: WE Controlled2
twe
Address ~V "V
(lA, RB, RC) ---./ r'\.'--_ _ _ _ _ _ _ _ _ _---// r'\.'--_ _ __
•lAS •
RAM • •
Enable
", ' - - - - - - - - - // v
(REIA, RERB,
RERC)
Write
Enable
(WEI)
tow tOH
Data
Input
(I) --------~
/"\k' Data Valid ,,/
I ' ' - -_ _ _ _---~/,'-----
Notes: 'The Data Output (A) is invalid in the Write mode.

2WE must be high during address transitions.
3RE must be high during address transitions.
2-453
AU Series Unit Cell Ubrary CMOS Channs/less Gate Arrays

RAMxx I Triple Port Static RAM (w word x b bit)

I I
tup tdn
100 - r-- AOO Path
101 -::; I-- AOI 10 KcL 10 Kct Kct2 COR2
I (b-l) -
'$ ::; ~
I-- A (b-I)
. 0.07 . 0.04 0.07 7 IA ~ A
IAOO - r-- BOO RB~ B
IAOI ~ I-- BOI RC~ C
::;
IA(b-I) -
'$
~B(b-I) REIA~A
RERB~B
RBOO- I-- COO RERC~C
RBOI~ I-- COl
'$
RB(t-l) - I-- C(b-I)
RCOO-
RCI -
::; '$
RC(t-1) -
REIA --<l
RERB--<l
RERC--<l
WEI - 0
Input Loading Parameter Symbol Typ (ns)"

Read Cycle TIme tRC
I I
IA I Address Access TIme tM
RB 1 RAM Enable Access TIme tRA
RC I
RE 1 Output Hold from Address Change IoH
WE I
Write Cycle TIme twc
RAM Enable t( 'end of Write tRW
""
Address Valid \( End of Write lAw
Output Driving Address Setup ti 119 tAS
Pin Name FaclOr(lu) Write Pulse Widtn twp
Data Setup TIme low
A 36
B 36 Write Recovery TIme tWR
C 36 Data Hold TIme IoH
. Refer to the Read Mode and Write Mode Tables on the following
.. pages.
Minimum values for the typical operating condition .
The values to be indicated here depend on bit-word organiza-
tion and are given by the Read Mode and Write Mode Delay
... TIme Tables on the following pages.

Pin Name
When b orts 10, these pin names are described with two char-
acters: e.a. A9.
2-454
CMOS Channe//ess Gate Arrays AU Series Unit Cell Ubrary
BASIC DELAY TIME

Read Mode

c= 1: 0.0024 * w + 0.0044 * b + 22.27
c=2: 0.0010· w + 0.0110 * b + 22.S0
IRC Read Cycle Time ns
c=4: 0.0006 * w + 0.0176 * b+ 22.S2
c= 8: O.OOOS* w + 0.OS41 * b + 22.22
c= 1: 0.0024 * w + 0.0044 * b + 21.S4
c=2: 0.001O*w + 0.0110 * b + 21.50
lAA Address Access Time ns
c=4: 0.0006* w + 0.0176 * b+ 21.56
c= 8: O.OOOS * w + 0.OS41 * b + 21.56
c= 1: 0.0051 *w+ 0.0140 * b + 19.44
c=2: 0.0006 * w + 0.0077· b+ 20.69
IRA RAM Enable Access Time ns
c=4: O.OOOS· w + 0.014S· b + 20.69
c= 8: 0.0002· w + 0.0286· b+ 20.75
c= 1: 0.0018· w + 0.0140· b + 5.S8
c= 2: 0.0009· w + 0.0286· b + 5.S8
tOH Output Hold from Address Change ns
c-4: 0.0004· w + 0.0572 * b+ 5.S8
c = 8: 0.0002· w + 0.1140· b + 5.S8
c= 1: 0.0010· b+ 2.84
c=2: 0.0020· b+ 2.84
tRH Output Hold from RAM Enable Change ns
c=4: 0.0040· b+ 2.84
c=8: 0.0079· b+ 2.84
Example
To find the delay time for the write-mode parameters for a triple-port RAM of 512 words,
16 bits, and c = 4:
tRC 0.0006 • w + 0.0176 • b + 22.32

0.0006·512 + 0.0176·16 + 22.32
22.91 ns (typ)
tAA 0.0006· w+0.0176· b + 21.56

0.0006·512 + 0.0176 * 16 + 21.56
22.15 ns (typ)
tRA 0.0003 * w + 0.0143 • b + 20.69

0.0003·512 + 0.0143·16 + 20.69
21.08 ns (typ)
tOH 0.0004 * w + 0.0572 * b + 5.38

0.0004·512 + 0.0572·16 + 5.38
6.50 ns (typ)
tRH 0.0040 • b + 2.84

0.0040 • 16 + 2.84
2.91 ns (typ)
2-455
AU Series Unit Cell Ubrary CMOS Channel/ess Gate AnayS

WrHeMode
Symbol Parameter Equation (1\'plcal Value) Unit

c-1: 0.0024*w + 0.0044 *b+ 22.27
c-2: 0.0010 * W + 0.0110 * b + 22.30
twe Write Cycle Time ns
c-4: 0.0006* W + 0.0176 * b+ 22.32
c-8: O.OOO3*w + 0.0341 *b+ 22.22
c-l: 0.0024*w + 0.0033 *b+ 15.63
c-2: 0.0010 * w + 0.0066 *b+ 15.63
tRW RAM Enable to End of Write ns
c-4: 0.0006* w + 0.0110 * b + 15.63
c-8: 0.0003*w + 0.0220 * b+ 15.63
c-1: 0.0024 * w + 0.0033 *b+ 18.93
c_2: 0.0010' w + 0.0066' b + 18.93
tAW Address Valid to End of Write ns
c-4: 0.0006' w + 0.0110' b + 18.93
c-8: 0.0003'w + 0.0220' b+ 18.93
c-1: 3.30
c-2: 3.30
tAS Address Setup Time ns
c-4: 3.30
c-8: 3.30
c_l: 0.0070' w + 0.0022' b+ 11.01
c=2: 0.0035 * w + 0.0044' b+ 11.01
twp Write Pulse Width ns
c.4: 0.0018 * w + 0.0088' b+ 11.01
c-8: 0.0009' w + 0.0176' b+ 11.01
c.l: 0.0070' w 9.38
c-2: 0.0035' w 9.38
low Data Setup Time ns
c-4: 0.0018' w 9.38
c-8: 0.0009' w 9.38
c-1: 0.0011 'b + 3.34
c-2: 0.0044' b+ 3.34
tWR Write Recovery Time 3.34 ns
c-4: 0.0066' b+
c-8: 0,0121' b+ 3.34
c-1: 0.0094' b+ 3.51"
c-2: 0.0187' b+ 3.51
c-4: 0.0374' b+ 3.51
c-8: 0.0748' b+ 3.51
Example
To find the delay time for the write-mode parameters for a triple-port RAM of 512 words, 16 bits and c = 4:
twe • 0.0006' w + 0.0176' b+ 22.32 twp - 0.0018'w+0.0088'b+ll.0l

0.0006' 512 + 0.0176 '16 + 22.32 0.0018' 512 + 0.0088 ' 16 + 11.01
22.91 ns (typ) • 12.08 ns (typ)
tRW - 0.0006'w+0.Oll0'b+15.63 tow - 0.0018' w + 9.38

= 0.0006' 512+ 0.0110' 16 + 15.63 _ 0.0018' 512+ 9.38
- 16.12 ns (typ) • 10.31 ns (typ)
tAW 0.0006'w+0.Oll0*b+18.93 tWR - 0.0066' b + 3.34

- 0.0006' 512 + 0.0110 * 16 + 18.93 _ 0.0066' 16 + 3.34
- 19.42 ns (typ) - 3.45 ns (typ)
tAS - 3.30 ns (typ) tOH - 0.0347' b + 3.51

- 0.0347' 16 + 3.51
- 4.11ns(typ)
2-456
CMOS Channe//ess Gate Arrays AU Series Unit ceO UbrSry
ROM SPECIFICATION
FEATURES
• Conflgurable size
• Non-clocked static ROM
SPECIFIC PARAMETERS
• Word size range: 16 to 2K words
BLOCK DIAGRAM
MEMORY MATRIX
ADD.
BUF.
RE
RE - - - I BUFFER
DOG~ D(b-1)
ADD. BUF. Address BuHer ATD ; Address TransHlon Detector

ROW DEC. RowDecodar RE ; ROM Enable Input
COL. DEC. CoIurm Decoder DOG ~ D (b-1) ; Data Output
ADO~A(1-1) AddreaIlnput
2-457
TIMING DIAGRAMS
Address
(A)
Oata
Output
(0) ---x Invalid
Valid
Address Contro(1
.. tRC
..
Ell RAM
Enable
(RE)
" I\... /
/
tRA
~
Data
Output
(D)
X Invalid
I\... V
/
'"
Valid
""
/
/
RE Control 2
Notes: 1ROM Enable (RE) must be Low in the address control

21n RE control, the address must be validated before ROM Enable (RE) becomes low.
2-458

I I
,roo--
ROMxx Mask ROM (w word x b bit) I

!Up !dn
Path
AOI D01 10 KcL 10 KcL KcL2 C DR2
A02 D02
, , A--)D
0.07 0.04 0.07 7
u'o-"
RE --) D
A(t-2)
A(t-1) D(b-I)
RE
Input Loading Parameter Symbol Typ (ns)"

Read Cycle lime tRc
A'" Address Access lime tAA
RE
RAM Enable Access lime tRA
Output Hold from Address Change IoH
Output Driving
D'" 36
, Refer to the Read Mode and Write Mode Tables on the following
pages.
,. Minimum values for the typical operating condition.
The values indicated here depend on bit-word organization and
are given in the Read Mode Delay lime Table on the following
... page.
Pin Name
When b or ts 10, these pin names are described with two char-
acters: e.g., A9.
2-459
BASIC DELAY TIME

Read Mode

c-4: 33.12
IRC Read Cycle Time ns
c=8: 33.02
c=4: 0.0161' w + 0.0226' b + 16.85

tM Address Access Time ns
c=8: 0.0080' w + 0.0258' b+ 17.81
c=4: 0.0173' w + 0.0290' b + 16.55

tRA RAM Enable Access Time ns
c=8: 0.0091' w + 0.0487' b+ 16.63
c=4: 0.0194' b+ 4.36

tOH Output Hold from Address Change c=8: 0.0258' b+ 4.40
ns
c=4: 0.0194 'w + 6.76

tRH Output Hold from RAM Enable Change 0.0258 'w + 6.61
ns
c = 8:
Example
To find the delay time for the Read-mode for a ROM of 512 words, 16 bits, and c = 4:
tRC 33.12
tM = 0.Q161 , w + 0.0226 ' b + 16.85

- 0.0161'512+0.0226'16+ 16.85
= 25.46 ns
tRA 0.0173' W+ 0.0290 ' b + 16.55

0.0173' 512 + 0.0290' 16 + 16.55
25.88 ns
IcH 0.0194 ' b + 4.36

0.Q194 '16 + 4.36
4.67 ns
tRH = 0.0194' b + 6.76

0.0194' 16 + 6.76
7.07 ns
2-460
Appendix A: General AC Specifications
Simulation Delay Specifications

(Recommended Operating Conditions, Ta = 0 to 70°C, Voo = 5 V±5%
Delay MuHlpllers Min. Max.

Pre·layout Simulation 0.35 tmaxB
Post·layout Simulation 0.40 tmaxA
Junction Temperature (Tj) tmaxB tmaxA

Tjs 60°C 1.65 1.55
60°C<Tjs 70°C 1.70 1.60

70°C<Tjs SO°C 1.75 1.65
SO°C<Tjs 90°C 1.S0 1.70
90°C<Tjs 105°C 1.85 1.75

105°C<Tjs 120°C 1.90 1.S0
120°C<Tjs 130°C' 1.95 1.85
130°C<Tjs 140°C2 2.00 1.90
140°C<Tjs 150°C2 2.05 1.95
NOTES: 1. This condition cannot be applied to devices in some plastic packages. If this condition is
required for devices in plastic, please consult Fujitsu.
2. This condition cannot be applied to devices in plastic packages. If this condition is required
even for ceramic packages, please consult Fujitsu.
Tj is determined by the following formula:
Tj = TaMAX + Sja x Pd re)
where
Pd: Power dissipation (W)

Sja: Thermal Resistance (OC/W). This value is determined for each package.
TaMAX: Maximum Ambient Termperature (OC)
2-461
2-462
Appendix B: Hierarchical Structure
2-463
2-464
CMOS Channelless Gate Arrays AU Series Unit Cell Library
Appendix C: Estimation Tables for Metal Loading

C-10KAU (Main Block)
CL(lu)
NOI CHIP LEVEL 1 LEVEL 2 LEVEL 3 LEVEL 4
1 4.1 2.8 1.8 1.1 0.6
2 6.2 4.3 2.7 1.7 0.8
3 8.3 5.7 3.7 2.3 1.1
4 9.7 6.7 4.3 2.7 1.3
5 10.7 7.4 4.7 2.9 1.5
6 11.6 8.0 5.1 3.2 1.6
7 12.7 8.8 5.6 3.5 1.7
8 13.2 9.1 5.8 3.6 1.8
9 13.5 9.3 6.0 3.7 1.8
10 13.9 9.6 6.1 3.8 1.9
11 13.9 9.6 6.1 3.8 1.9
12 14.1 9.7 6.2 3.9 1.9
13 14.3 9.9 6.3 3.9 1.9
14 14.6 10.1 6.5 4.0 2.0
15 14.6 10.1 6.5 4.0 2.0
16-30 15.8 10.9 7.0 4.3 2.2
31-50 18.1 12.5 8.0 5.0 2.5
51-75 18.6 12.8 8.2 5.1 2.5
76-100 20.5 14.1 9.1 5.6 2.8
C-10KAU (Sub Block)
CL(lu)
NOI LEVEL 1 LEVEL 2 LEVEL 3 LEVEL 4
1 1.9 1.2 0.7 0.4
2 3.4 2.1 1.3 0.6
3 4.8 3.1 1.9 0.9
4 5.8 3.7 2.3 1.1
5 6.5 4.1 2.5 1.3
6 7.1 4.5 2.8 1.4
7 7.9 5.0 3.1 1.5
8 8.2 5.2 3.2 1.6
9 8.4 5.4 3.3 1.6
10 8.7 5.5 3.4 1.7
11 8.7 5.5 3.4 1.7
12 8.8 5.6 3.5 1.7
13 9.0 5.7 3.5 1.7
14 9.2 5.9 3.6 1.8
15 9.2 5.9 3.6 1.8
16-30 10.0 6.4 3.9 2.0
31-50 11.6 7.4 4.6 2.3
51-75 11.9 7.6 4.7 2.3
76-100 13.2 8.5 5.2 2.6
2-465
AU Series Unit Cell Ubrary CMOS Channe/less Gate Arrays
Appendix C: Estimation Tables for Metal Loading (Continued)

CL(lu)
NDI CHIP LEVEL 1 LEVEL 2 LEVEL 3 LEVEL 4
1 5.1 2.8 1.8 1.1 0.6
2 7.7 4.3 2.7 1.7 0.8
3 10.4 5.7 3.7 2.3 1.1
4 12.1 6.7 4.3 2.7 1.3
5 13.4 7.4 4.7 2.9 1.5
6 14.4 8.0 5.1 3.2 1.6
7 15.8 8.8 5.6 3.5 1.7
8 16.4 9.1 5.8 3.6 1.8
9 16.9 9.3 6.0 3.7 1.8
10 17.3 9.6 6.1 3.8 1.9
11 17.3 9.6 6.1 3.8 1.9
12 17.6 9.7 6.2 3.9 1.9
13 17.8 9.9 6.3 3.9 1.9
14 18.3 10.1 6.5 4.0 2.0
15 18.3 10.1 6.5 4.0 2.0
16-30 19.7 10.9 7.0 4.3 2.2
31 -50 22.6 12.5 8.0 5.0 2.5
51-75 23.2 12.8 8.2 5.1 2.5
76-100 25.6 14.1 9.1 5.6 2.8
C-15KAU (Sub Block)
CL (Iu)
NDI LEVEL 1 LEVEL 2 LEVEL 3 LEVEL 4
1 1.9 1.2 0.7 0.4
2 3.4 2.1 1.3 0.6
3 4.8 3.1 1.9 0.9
4 5.8 3.7 2.3 1.1
5 6.5 4.1 2.5 1.3
6 7.1 4.5 2.8 1.4
7 7.9 5.0 3.1 1.5
8 8.2 5.2 3.2 1.6
9 8.4 5.4 3.3 1.6
10 8.7 5.5 3.4 1.7
11 8.7 5.5 3.4 1.7
12 8.8 5.6 3.5 1.7
13 9.0 5.7 3.5 1.7
14 9.2 5.9 3.6 1.8
15 9.2 5.9 3.6 1.8
16-30 10.0 6.4 3.9 2.0
31 -50 11.6 7.4 4.6 2.3
51-75 11.9 7.6 4.7 2.3
76 -100 13.2 8.5 5.2 2.6
2-466
CMOS Channel/ess Gate Arrays AU Series Unit Cell UbralY
CL(lu)
1 5.9 2.8 1.8 1.1 0.6
2 8.9 4.3 2.7 1.7 0.8
3 11.9 5.7 3.7 2.3 1.1
4 13.9 6.7 4.3 2.7 1.3
5 15.4 7.4 4.7 2.9 1.5
6 16.6 8.0 5.1 3.2 1.6
7 18.2 8.8 5.6 3.5 1.7
8 18.9 9.1 5.8 3.6 1.8
9 19.4 9.3 6.0 3.7 1.8
10 19.9 9.6 6.1 3.8 1.9
11 19.9 9.6 6.1 3.8 1.9
12 20.2 9.7 6.2 3.9 1.9
13 20.5 9.9 6.3 3.9 1.9
14 21.0 10.1 6.5 4.0 2.0
15 21.0 10.1 6.5 4.0 2.0
16-30 22.7 10.9 7.0 4.3 2.2
31-50 26.0 12.5 8.0 5.0 2.5
51-75 26.7 12.8 8.2 5.1 2.5
76-100 29.4 14.1 9.1 5.6 2.8
C-20KAU (Sub Block)
CL(lu)
1 1.9 1.2 0.7 0.4
2 3.4 2.1 1.3 0.6
3 4.8 3.1 1.9 0.9
4 5.8 3.7 2.3 1.1
5 6.5 4.1 2.5 1.3
6 7.1 4.5 2.8 1.4
7 7.9 5.0 3.1 1.5
8 8.2 5.2 3.2 1.6
9 8.4 5.4 3.3 1.6
10 8.7 5.5 3.4 1.7
11 8.7 5.5 3.4 1.7
12 8.8 5.6 3.5 1.7
13 9.0 5.7 3.5 1.7
14 9.2 5.9 3.6 1.8
15 9.2 5.9 3.6 1.8
16-30 10.0 6.4 3.9 2.0
31-50 11.6 7.4 4.6 2.3
51-75 11.9 7.6 4.7 2.3
76-100 13.2 8.5 5.2 2.6
2-467

C·30KAU (Main Block)
Cdlu)
1 9.9 7.8 5.5 3.5 1.7
2 14.9 11.6 8.3 5.3 2.6
3 20.0 15.6 11.1 7.1 3.5
4 23.4 18.3 13.0 8.3 4.1
5 25.9 20.3 14.4 9.2 4.6
6 27.9 21.9 15.5 9.9 4.9
7 30.6 23.9 17.0 10.9 5.4
8 31.8 24.9 17.6 11.3 5.6
9 32.6 25.5 18.1 11.6 5.7
10 33.4 26.2 18.6 11.9 5.9
11 33.4 26.2 18.6 11.9 5.9
12 33.9 26.5 18.8 12.0 6.0
13 34.4 26.9 19.1 12.2 6.1
14 35.2 27.6 19.6 12.5 6.2
15 35.2 27.6 19.6 12.5 6.2
16-30 38.1 29.9 21.2 13.5 6.7
31 -50 43.6 34.2 24.2 15.5 7.7
51 -75 44.9 35.1 24.9 15.9 7.9
76-100 49.3 38.6 27.3 17.5 8.7
C·30KAU (Sub Block)
CL(lu)
1 4.7 3.3 2.2 1.0
2 8.6 6.1 3.9 1.9
3 12.6 8.9 5.7 2.8
4 15.2 10.8 7.0 3.4
5 17.2 12.2 7.8 3.8
6 18.8 13.3 8.6 4.2
7 20.6 14.8 9.5 4.7
8 21.8 15.5 9.9 4.9
9 22.5 15.9 10.2 5.0
10 23.1 16.4 10.5 5.2
11 23.1 16.4 10.5 5.2
12 23.4 16.6 10.7 5.2
13 23.9 16.9 10.9 5.3
14 24.5 17.4 11.2 5.5
15 24.5 17.4 11.2 5.5
16-30 26.8 19.0 12.2 6.0
31 -50 31.1 22.1 14.1 7.0
51 -75 32.1 22.7 14.6 7.2
76 -100 35.5 25.2 16.1 8.0
2-468
CL(lu)
1 11.3 7.8 5.5 3.5 1.7
2 17.0 11.6 8.3 5.3 2.6
3 22.8 15.6 11.1 7.1 3.5
4 26.7 18.3 13.0 8.3 4.1
5 29.6 20.3 14.4 9.2 4.6
6 31.9 21.9 15.5 9.9 4.9
7 34.9 23.9 17.0 10.9 5.4
8 36.3 24.9 17.6 11.3 5.6
9 37.3 25.5 18.1 11.6 5.7
10 38.2 26.2 18.6 11.9 5.9
11 38.2 26.2 18.6 11.9 5.9
12 38.7 26.5 18.8 12.0 6.0
13 39.3 26.9 19.1 12.2 6.1
14 40.3 27.6 19.6 12.5 6.2
15 40.3 27.6 19.6 12.5 6.2
16-30 43.6 29.9 21.2 13.5 6.7
31-50 49.9 34.2 24.2 15.5 7.7
51-75 51.3 35.1 24.9 15.9 7.9
76-100 56.3 38.6 27.3 17.5 8.7
C-40KAU (Sub Block)
CL(lu)
1 4.7 3.3 2.2 1.0
2 8.6 6.1 3.9 1.9
3 12.6 8.9 5.7 2.8
4 15.2 10.8 7.0 3.4
5 17.2 12.2 7.8 3.8
6 18.8 13.3 8.6 4.2
7 20.6 14.8 9.5 4.7
8 21.8 15.5 9.9 4.9
9 22.5 15.9 10.2 5.0
10 23.1 16.4 10.5 5.2
11 23.1 16.4 10.5 5.2
12 23.4 16.6 10.7 5.2
13 23.9 16.9 10.9 5.3
14 24.5 17.4 11.2 5.5
15 24.5 17.4 11.2 5.5
16-30 26.8 19.0 12.2 6.0
31-50 31.1 22.1 14.1 7.0
51-75 32.1 22.7 14.6 7.2
76-100 35.5 25.2 16.1 8.0
2-469
AU Series Unit Cell Library CMOS Channe/less Gate AmlYs
CL(lu)
1 12.7 7.8 5.5 3.5 1.7
2 19.1 11.6 8.3 5.3 2.6
3 25.7 15.6 11.1 7.1 3.5
4 30.1 18.3 13.0 8.3 4.1
5 33.3 20.3 14.4 9.2 4.6
6 35.9 21.9 15.5 9.9 4.9
7 39.3 23.9 17.0 10.9 5.4
8 40.9 24.9 17.6 11.3 5.6
9 41.9 25.5 18.1 11.6 5.7
10 43.0 26.2 18.6 11.9 5.9
11 43.0 26.2 18.6 11.9 5.9
12 43.5 26.5 18.8 12.0 6.0
13 44.2 26.9 19.1 12.2 6.1
14 45.3 27.6 19.6 12.5 6.2
15 45.3 27.6 19.6 12.5 6.2
16-30 49.0 29.9 21.2 13.5 6.7
31-50 56.1 34.2 24.2 15.5 7.7
51-75 57.7 35.1 24.9 15.9 7.9
76-100 63.3 38.6 27.3 17.5 8.7
C-50KAU (Sub Block)
CL(lu)
1 4.7 3.3 2.2 1.0
2 8.6 6.1 3.9 1.9
3 12.6 8.9 5.7 2.8
4 15.2 10.8 7.0 3.4
5 17.2 12.2 7.8 3.8
6 18.8 13.3 8.6 4.2
7 20.6 14.8 9.5 4.7
8 21.8 15.5 9.9 4.9
9 22.5 15.9 10.2 5.0
10 23.1 16.4 10.5 5.2
11 23.1 16.4 10.5 5.2
12 23.4 16.6 10.7 5.2
13 23.9 16.9 10.9 5.3
14 24.5 17.4 11.2 5.5
15 24.5 17.4 11.2 5.5
16-30 26.8 19.0 12.2 6.0
31-50 31.1 22.1 14.1 7.0
51-75 32.1 22.7 14.6 7.2
76-100 35.5 25.2 16.1 8.0
2-470
C·75KAU (Main Block)
CL(lu)
1 15.2 7.8 5.5 3.5 1.7
2 22.8 11.6 8.3 5.3 2.6
3 30.6 15.6 11.1 7.1 3.5
4 35.9 18.3 13.0 8.3 4.1
5 39.7 20.3 14.4 9.2 4.6
6 42.9 21.9 15.5 9.9 4.9
7 46.9 23.9 17.0 10.9 5.4
8 48.8 24.9 17.6 11.3 5.6
9 50.1 25.5 18.1 11.6 5.7
10 51.4 26.2 18.6 11.9 5.9
11 51.4 26.2 18.6 11.9 5.9
12 52.0 26.5 18.8 12.0 6.0
13 52.8 26.9 19.1 12.2 6.1
14 54.1 27.6 19.6 12.5 6.2
15 54.1 27.6 19.6 12.5 6.2
16-30 58.6 29.9 21.2 13.5 6.7
31-50 67.0 34.2 24.2 15.5 7.7
51 -75 68.9 35.1 24.9 15.9 7.9
76-100 75.7 38.6 27.3 17.5 8.7
C·75KAU (Sub Block)
CL (Iu)
NOI LEVELl LEVEL 2 LEVEL 3 LEVEL 4
1 4.7 3.3 2.2 1.0
2 8.6 6.1 3.9 1.9
3 12.6 8.9 5.7 2.8
4 15.2 10.8 7.0 3.4
5 17.2 12.2 7.8 3.8
6 18.8 13.3 8.6 4.2
7 20.6 14.8 9.5 4.7
8 21.8 15.5 9.9 4.9
9 22.5 15.9 10.2 5.0
10 23.1 16.4 10.5 5.2
11 23.1 16.4 10.5 5.2
12 23.4 16.6 10.7 5.2
13 23.9 16.9 10.9 5.3
14 24.5 17.4 11.2 5.5
15 24.5 17.4 11.2 5.5
16-30 26.8 19.0 12.2 6.0
31-50 31.1 22.1 14.1 7.0
51 -75 32.1 22.7 14.6 7.2
76-100 35.5 25.2 16.1 8.0
2-471
CL (Iu)
1 17.7 7.8 5.5 3.5 1.7
2 26.5 11.6 8.3 5.3 2.6
3 35.6 15.6 11.1 7.1 3.5
4 41.8 18.3 13.0 8.3 4.1
5 46.2 20.3 14.4 9.2 4.6
6 49.9 21.9 15.5 9.9 4.9
7 54.6 23.9 17.0 10.9 5.4
8 56.8 24.9 17.6 11.3 5.6
9 58.2 25.5 18.1 11.6 5.7
10 59.7 26.2 18.6 11.9 5.9
11 59.7 26.2 18.6 11.9 5.9
12 60.5 26.5 18.8 12.0 6.0
13 61.4 26.9 19.1 12.2 6.1
14 62.9 27.6 19.6 12.5 6.2
15 62.9 27.6 19.6 12.5 6.2
16-30 68.1 29.9 21.2 13.5 6.7
31 -50 77.9 34.2 24.2 15.5 7.7
51 -75 80.1 35.1 24.9 15.9 7.9
76 -100 88.0 38.6 27.3 17.5 8.7
C-100KAU (Sub Block)
CL (Iu)
1 4.7 3.3 2.2 1.0
2 8.6 6.1 3.9 1.9
3 12.6 8.9 5.7 2.8
4 15.2 10.8 7.0 3.4
5 17.2 12.2 7.8 3.8
6 18.8 13.3 8.6 4.2
7 20.6 14.8 9.5 4.7
8 21.8 15.5 9.9 4.9
9 22.5 15.9 10.2 5.0
10 23.1 16.4 10.5 5.2
11 23.1 16.4 10.5 5.2
12 23.4 16.6 10.7 5.2
13 23.9 16.9 10.9 5.3
14 24.5 17.4 11.2 5.5
15 24.5 17.4 11.2 5.5
16-30 26.8 19.0 12.2 6.0
31-50 31.1 22.1 14.1 7.0
51-75 32.1 22.7 14.6 7.2
76-100 35.5 25.2 16.1 8.0
2-472
CMOS Channe//ess Gate Arrays AU Series Unit Cell Ubra7
Appendix 0: AU CMOS Gate Array Available Package Types
DEVICE NAME
Package Package
Name Material C-10KAU C-15KAU C-20KAU C-30KAU C-40KAU C-50KAU C-75KAU C-100KAU
PGA-64 Ceramic • • • - - - - -
PGA-88 Ceramic • • • - - - - -
PGA-135 Ceramic • • • • • • • •
PGA-179 Ceramic - - • • • • • •
PGA-208 Ceramic - - - • • • • •
PGA-256 Ceramic - - - - • • • •
PGA-299 Ceramic ...,. - - - - 0 0 0
PGA-321 Ceramic - - - - - - 0 0
PGA-361 Ceramic - - - - - - 0 0
PGA-401 Ceramic - - - - - - - 0
QFP-64 Plastic • • • - - - - -
QFP-80 Plastic • • • - - - - -
QFp-100 Plastic • • • - - - - -
QFP-120 Plastic • • • • • - - -
QFP-160 Plastic - • • • • - - -
PLCC-68 Plastic • • • - - - - -
PLCC-84 Plastic • • • - - - - -
SDIP-64 Plastic • • • - - - - -
Note: • = Available
o = Under Development
- = Not Available
2-473
AU Series Unit Cell Library CMOS Channel/ess Gate Arrays
2-474
CMOS Channe/less Gate Affays AU Series Unit Cel/ Ubrary
Appendix E: TTL 7400 Function Conversion Table
TTL 7400 Number

Series Fujitsu of Unit
Name Function BasleCelis Cells
7400 Quad 2-input NAND 4xN2N 4

7401 Quad 2-input NAND, Open Collector Outputs T24 multiplexer 6
7402 Quad 2-input NOR 4xR2N 4
7403 Quad 2-input NAND, Open Collector Outputs T24 multiplexer 6
7404 Hex Inverter 6xVIN 6
7405 Hex Inverter, Open Collector Outputs RSB 5
7406 Hex Inverter/Buller, Open Collector Outputs RSB 5
7407 Hex Buller, Open Collector Outputs 2 x N3N into R2N 5
7408 Quad 2-input AND 4xN2P 8
7409 Quad 2-input AND, Open Collector Outputs N8P 6
7410 Triple 3-input NAND 3xN3N 6
7411 Triple 3-input AND 3xN3P 9
7412 Triple 3-NAND, Open Collector Outputs T33 7
7413 Dual4-input NAND, Schmitt Trigger 2 x (4 x 12R to N4N) 68
7414 Hex Schmitt Trigger Inverter 6xllR 48
7415 Triple 3-input AND, Open Collector Outputs N8P to N2P 8
7418 Dual 4-input NAND, Schmitt Trigger 2 x(4 x 12Rto N4N) 68
7419 Hex Schmitt Trigger Inverter 6 xllR 48
7420 Dual4-input NAND 2xN4N 4
7421 Dual 4-input AND 2xN4P 6
7422 Dual4-input NAND, Open Collector Outputs 2 x N4N + N2P 6
7423 Expanded Dual 4-input NOR with Strobe R4P to 023 + R4P to R2N 9
7424 Quad Schmitt Trigger 2-input NAND 8 x 12R + 4 x N2N 68
7425 Dual 4-input NOR with Strobe 2 x (R4P + R2N) 8
7426 Quad 2-input NAND, High Voltage Output 4xN2N 4
7427 Triple 3-input NOR 3xR3N 6
7428 Quad 2-input NOR Buller 4xR2N 4
7430 8-inputNAND N8B 6
7432 Quad 2-input OR 4xR2P 8
7433 Quad 2-input NOR Buller, Open Collector
Outputs 4xR2N+N4P 7
7434 Hex Noninverter 6xB1N 6
7435 Hex Noninverter with Open Collector Outputs 2 x N3N into R2N 5
7437 Quad 2-input NAND Buller 4 xN2B 12
7438/9 Quad 2-input NAND Buller, Open Collector
Outputs 4xN2N+N4P 7
7440 Dual4-input NAND Buller 2 x N4B (N4N if not power) 8(4)
7442 BCD to Decimal Decoder 4xV2B+l0xN4N 24
7443 EX3 to Decimal Decoder 4 x V2B + 10 x N4N 24
7444 4 to 10 Une Decoder 4xV2B+l0xN4N 24
7445 BCD to Decimal Decoder/driver (30V) 4 x V2B + 10 x N4N 24
7446 BCD to 7--i;egment Decoder/Driver (30V) 4 x VIN + 11 x N2N + 10 x N3N + 4 x N3P + 3 x N2P 53
7447 BCD to 7--i;9gment Decoder/Driver (15V) 4 x VIN + 11 x N2N + 10 x N3N + 4 x N3P + 3 x N2P 53
7448 BCD to 7--i;egment Decoder/Driver 4 x VIN + 11 x N2N + 10 x N3N + 4 x N3P + 3 x N2P 53
7449 BCD to 7-segment, Open Collector Outputs 4 x VIN + 11 x N2N + 10 x N3N + 4 x N3P + 3 x N2P 53
7450 Dual 2-input, 2-wide AOI (One Expandable) 036+024 5
7451 AOI 2x 024 4
7452 Expandable 4-wide AND-OR N3N + 036 + VI N into N3N 8
7453 Expandable 4-wide AOI 036 + 023 into N2P 7
7454 4-wideAOI 2 x N3N + 2 x N2N + N4N + VIN 9
7455 2-wide 4-input AOI T42 6
7460 Dual 4-input Expander 2xN4P 6
7461 Triple 3--input Expander 3xN3P 6
7462 4-wide ANO-OR Expander 2xN3N +2x N2N + N4N 8
7464 4-2--'l-2AOI T54 10
7465 4-2-3-2 AOI (Open Collector) T54 10
2-475
Appendix E: TTL 7400 Function Conversion Table (Continued)
TIL 7400 Number

Serln Fujitsu 01 Unit
Name Function Basic Cells Cells
7470 AND-gated positive-edge JK FF with Preset

and Clear 3 x VI N + 2 x N3N + N2N + R2N + FJD 21
or: FD4 + 2 x N2N + R2N + VI N + R2P + 024 17
7471 AND-gated RS MIS FF with Preset
and Clear FD4 + 2 x N3N + 2 x 023 + 2 x VI N 19
or: LT1+ 2 x N4N + N2P 10
7472 AND-gated JK MIS FF with Preset
and Clear VI N + 2 x N3N + N2N + R2N + FJD 19
or: FD4 + N3P + N3N + VIN + 024 17
7473 Dual JK FF with Clear' 2 x FJD 24
7474 Dual positive-edge D-FF with Preset and
Clear 2 x FOP 16
7475 4-bit Bistable Latch LTM 16
7476 Dual JK FF with Preset and Clear 2 x (FJD + N2N + R2N + V1N) 30
7478 Dual JK FF with Preset and Common 2 x (FJD + N2N + R2N + V1N) 30
Clear and Clock
7480 Gated Full Adder AIN 8
7482 2-bit Binary Full Adder A2N 16
7483 4-bit Binary Full Adder with Fast Carry A4H 48
7484 4-bit Magnitude Comparator MC4 42
7486 Quad 2-input XOR 4 xX2N 12
7487 4-bit True/Complement ZeroiOne Element 4 x N2N + VI N + 4 x N2N 17
7489 64-bit (16 x 4) Memory 2 x DES + VI N + 16 x LT4 298
+ 5 x (V2B + TSA) + 10 x V2B
7490 Decade Counter 2 x (FOP + FDO + N2P + N2N + R2N) + VIN 39
(Different Implementation) 4xN2P+2xR2P+N2N+C41 +LTI 41
7491 8-bit Shift Register 2xFDS+V1N 41
7492 Divide-by-12 Counter 4 x FDO + 2 x VIN + 2 x R2N + N2N 33
7493 4-bit Binary Counter C41 + N2N (for the resets) 25
7494 4-bit Shift Register. 2 asynchronous Presets FS3 34
4-bit Shift Register. 2 asynchronous
Presets. Full Implementation 4 x FOP + 4 x 024 + 2 x VIN 42
7495 4-bit Parallel-access Shilt Register FS2+D24+2xV1N 34
7496 5-bit Shift Register 5 x FOP + 5 x N2N + VI N(dock) 46
7497 Synch 8-bit Binary Rate Multiplier FOR + 2 x FDO + 3 x VI N + 2 x N2N 122
+ 2 x N3N + 2 x N4N + 5 x N6B + 3 x N8B
+ R2B +X2N + 5 x XIB.
7498 4-bit Data SelectorlStorage Register FDQ + T2F +4x VIN 33
7499 4-bit Universal Shift Register FS2 + LTK + 2 x 024 + 4 x VIN 42
74100 8-bit Bistable Latch 2 x YL4 + 2 x VI N 30
74101 AO-gated JK Negative-Edge FF.
with Preset FD3 + VIN +3x 024 15
74102 AN D-gated JK Negative-Edge FF with
Preset and Clear FD4 + 024 + N3P + N3N IS
74103 Dual JK FF with Clear 2 x FJD + 2 x VI N (for clock) 26
or: 2 x (FD5 + 024 + V1N) 22
74106 Dual JK Negative-Edge FF with Preset
and Clear 2 x (FD4 + 024 + V1N) 24
74107 Dual JK FF with Clear 2 x (FJD + 2 x VI N) 22
and Common Clear and Clock 2 x (FD4 + 024 + V1N) 24
74109 Dual JK Positive-Edge FF with Preset and
Clear 2 x (FOP + VIN + 024) 22
74110 AND-gated JK MIS FF with Data
Lockout FOP + 024 + N3P + N3N 15
74111 Dual JK MIS FF with Data Lockout 2 x (FOP + 024 + V1N) 22
and Clear 2 x (FD4 + 024 + V1N) 24
2-476
CMOS Channe//ess Gate Arrays AU Series Unit Cell Ubrary
TTL 7400 Number

Series Fujitsu 01 Unit
Name Function BasleCells Cells
74113 Dual JK Negative-Edge FF with Preset 2 x (FD3 + 024 + V1N) 22

74114 Dual JK Negative-Edge FF with Preset and
Common Clear and Clock 2 x (FD4 + 024 + V1N) 24
74116 Dual 4-bit Latch with Clear 2xLTM 32
74120 Dual Pulse Synchronizer/Driver 2 x (N2P + LTI + 4 x N3N + 2 x N2N + 2 x VI N) 36
74125 Quad Bus Buffer with 3-5tate Output 841 9
74126 Quad Bus Buffer with 3-5tate Output 841 +4xV1N 13
74132 Quad 2--input NAND Schmitt Trigger 4 x (2 x 12R + N2N) 68
74133 13-input NAND 2 x N4N + N3N + N2N into R4P 10
74134 12--input NAND with 3-state Outputs NCB+04R 15
74135 Quad 3--input EXORlEXNOR 4xX4N 20
74136 Quad 2--input EXOR with Open-Collector
Outputs 4xX2N + R4N 14
74137 3-line to S-line Decoder with Address
Latch 3 x LTK into DE6 42
74138 3-line to lHine Decoder with Enable DE6 30
74139 Dual 2-line to 4--iine Decoder 2x DE4 16
74141 BCD-to-Decimal Decoder 4xV2B+l0xN4N 24
74145 BCD-to-decimal Decoder 4xV1N+l0xN4N 24
74147 1O-line to 4--iine BCD Priority Encoder 3 x N4N + 3 x N3N + 2 x N2N + 2 x N2P 36
+ 3 x R2N + R4N + 13 x VIN
74148 8--iine to 3--iine Octal Priority Encoder N9B + 2 x N2N + R2P + R4N + 4 x N3N 40
+ 2x N4N + G44 + 12x VIN
74150 l-to-16 Multiplexer DE3 + 2 x U28 + D24 + 2 x VIN 41
74151 l-t0-8 Multiplexer with Strobe DE3 + U28 + N2N + VIN 28
74152 1-10-8 Multiplexers DE3+ U28 26
74153 Dual 4-line to l--iine Selector/Multiplexer DE2 + 2 x U24 + 2 x R2N 19
74154 4--iine to llHine Decoder/Demultiplexer 2 x DE6 + VIN 61
or: 2 x DE4 + N2P + 16 x R2P 50
74155 Dual 2-line to 4-line Decoder/Demultiplexer
(Totem Pole) 8 x N3N + 2 x R2N + 5 x VI N 23
(Open Collector) 8 x N3N + 2 x R2N + 5 x VIN 23
74157 Quad 2-line to l--iine multiplexer T2F + 4 x R2N + Bl N 13
74158 Quad 2-line to l--iine multiplexer
(Inverter Data Outputs) 4 x 024 + VI N + 2 x R2N 11
74159 4--iine to llHine Demultiplexer 2 x DE6 + VIN (without open collector) 50
74160 Synchronous 4-bit Counter 4xCl1 + K1B+ 2 xV2B+ VIN + B1N+ 62
(Decimal with Direct Clear) N2K + 2 x R3N + R4N + 3 x R2N + N2N
74161 Synchronous 4-bit Counter (Binary
with Direct Clear) C43 48
74162 Synchronous 4-bit Counter
(Decimal with Synchronous Clear) C45 + 036 + N3P + 2 x R2N + BIN 57
with Synchronous Clear) C45 48
74164 B-bit Parallel Output Serial Shift
Register, Asynchronous Clear 2 x FOR + N2P 54
74165 B-bit Shift Register 2 x FDS + 8 x 024 + 11 x VI N + K4B + R2P 71
74166 8-bit Shift Register 2 x FOR + 8 x 024 + 10 x VIN + K4B 80
74168 4-bit Up/Down Synchronous Counter
(Decade) 4 xCII + 4 x T32 + 7 x N2N + 2 x N3N + R2N 85
+7xV2B+K1B
(Binary) C47 68
74170 4-by-4 Register File 4 x (YL4 + BIN + VIN + U24) + 2 x DE4 104
74171 Quad D-FF with Clear FOR +4 x VIN 30
74172 16-bit (8 x 2) Register File 3 x DE6 + 4 x FDS + 16 x (N2N + G34 + 348
+ VI N + 2 x R2P + 4 x U28) + 2 x VI N + 2 x R2P
2-477
AU Series Unit Cell Ubrary CMOS Channel/ess Gate AtTays
TTL 7400 Number

Name Function BaaleCaila Cella
74173 44lit D-type Register

(3-state Output) FOR +2 x R2N + 841 +6 x VIN + KIB +4 x 024 53
74174 Hex D-FF (Single Output) FDR+2xFDO 40
74175 Quad D-FF (with Clear) FDR+4xV1N 30
74176 Presetteble Decade/Binary Counter 4xFDP+2x R2N +5x N2N +4x N3N + KIB 49
74177 Presetlable Binary Counter 4 x FOP + 5 x N2N + 4 x N3N + KIB 47
74178 4-bit Universal Shift Register FS2 30
74179 4-bit Universal Shift Register
(Direct Clear) FS2 + 9x N2N + BIN 40
74180 9-bit OddIEven Parity Checker P08 + 2x 024 + VIN 23
74181 ALU/Function Generator 5xV1N + 5 x T32 + 4 x 036 + 8 x X2N +3 x T54 +
N6B + N4B + 2 x N2N + 2 x N4P 113
74182 Look-ahead Carry Generator R4P + 2 x VIN + 2 x T44 + T33 + 024 36
74183 Dual Carry-save Full Adder 2xA1N 16
74184 BCD-to-binary Code Converter These devices are ROM based
74185 Binary-to-BCD Code Converter These devices are ROM based
74190 Synch Up/Down Counter (BCD) 4 x FOP + 4 x X2N + KIB +3 x VIN + 3 x N3N
+ 9 x N2N + 2 x T32 + T43
74191 Synch Up/Down Counter (Binary) C47 68
74192 Up/Down Dual Clock Counter (BCD) 4 xCII + 4x V2B + N6B + 2x N3N + R2N 79
+ T32 + T42 + T43
74193 Up/Down Dual Clock Counter (Binary) 4 xCII + 2x N6B + 4x V2B + R2N + 024 + T32 72
+ T42
74194 44lit Bidirectional Universal Shift Register FOR +6x VIN + R2N + 4 x 036 + 023 + BIN 48
74195 44lit Parallel Access Shift Register FS2+ 024 + 2x VIN 34
74196 Preset Decade/Binary Counter/Latch 4 x FOP + 2 x R2N + 5 x N2N + 4 x N3N + KIB 49
74197 Preset Binary Counter/Latch 4 x FOP +5 x N2N +4 x N3N + KIB 47
74198 8-bit Bidirectional Universal Shift Register 2 x FOR + 024 + 10 x VI N + R2N + 8 x 036 89
74199 8-bit Bidirectional Universal Shift
Register (JK Serial Input) 2x FS2 + 024 +3 x VIN + BIN + R2N + 8x N2P 83
or: 2xFDR+ 7x 024+ T33+ 11 xV1N +R2N 85
74246 BCD-to-7-Segment Decoder/Driver
(30V. Active Low Open Collector) 4 x VIN + 11 x N2N + 10 x N3N + 4 x N3P + 3 x N2P 53
(15V. Active Low Open Collector) 4 x VIN + 11 x N2N + 10 x N3N + 4 x N3P + 3 x N2P 53
(Internal Pulf-up) 4 x VI N + 11 x N2N + lOx N3N + 4 x N3P + 3 x N2P 53
(Open Collector) 4 x VIN + 11 x N2N + 10 x N3N + 4 x N3P + 3 x N2P 53
74260 Dual 5-input NOR 2xR6B 10
74265 Quad Complementary Output Element BIN + VIN
74266' Quad 2-EXNOR. Open Collector 4xX1N 12
74273 OctailHype FF with Clear 2xFDR 52
74276 Quad J--K FF 4x (FOP + VIN + 024) + 2x BIN 46
74347 BCD-to-7-Segment Decoder/Driver 4xV1N + 11 x N2N + lOx N3N +4x N3P + 3x N2P 53
2-478
CMOS Channel/ess Gale Arrays AU Series Unit Cell Ubrary
Appendix F: Alphanumeric Index of Unit Cells
Name Function Page No.
A1A 1-bit HaH Adder 2-249

A1N 1-bit Full Adder 2-250
A4H 4-bit Binary Fu" Adder with Fast Carry 2-253
BD3 DelayCe" 2-11
BD4 DelayCe" 2-12
BD5 DelayCe" 2-13
BD6 DelayCe" 2-14
B1N True Buffer 2-10
B11 1-bit Bus Driver 2-315
B12 1-bit Block Bus Driver 2-319
16
841 4-bit Bus Driver 2-317
C11 Non-Scan Flip-flop for Counter 2-219
C41 Non-Scan 4-bit Binary Asynchronous Counter 2-221
C42 Non-Scan 4-bit Binary Synchronous Counter 2-224
C43 Non-Scan 4-bit Binary Synchronous Up Counter 2-227
C47 Non-Scan 4-bit Binary Synchronous Up/Down Counter 2-235
DE2 2:4 Decoder 2-294
DE4 2:4 Decoder with Enable 2-297
014 2-wide 3-AND 4-lnput ADI 2-68
023 2-wide 2-AND 3-lnput AOI 2-67
044 2-wide 2-0R 2-AND 4-lnput AOI 2-72
FDM Non-Scan 0 Flip-flop 2-181
FDN Non-Scan 0 Flip-flop with Set 2-183
FDO Non-Scan 0 Flip-flop with Reset 2-185
FOP Non-Scan 0 Flip-flop with Set and Reset 2-187
FDQ Non-Scan 4-bit 0 Flip-flop 2-190
FOR Non-Scan 4-bit 0 Flip-flop with Clear 2-192
FDS Non-Scan 4-bit 0 Flip-flop 2-195
FD2 Non-Scan Power 0 Flip-flop 2-197
2-479
AU Series Unit Ceil Ubwy CMOS Channeiless Gats Arravs
Appendix F: Alphanumeric Index of Unit Cells (Continued)
FD3 Non-Scan Power D Flip-flop with Preset 2-198

FD4 Non-Scan Power D Flip-flop with Clear and Preset 2-201
FD5 Non-Scan Power D Flip-flop with Clear 2-203
FJD Non-Scan Positive Edge Clocked Power J-K FK with Clear 2-205
FS1 4-bit Serial-in Parallel-out Shift Register 2-275
FS2 4-bit Shift Register with Synchronous Load 2-277
FS3 4-bit Shift Register with Asynchronous Load 2-279
G14 2-wide 3-0R 4-lnput OAI 2-76
G34 3-wide 2-0R 4-lnl?ut OAI 2-78
G44 2-wide 2-AND 2-0R 4-lnput OAI 2-79
H6C 3-state Output (IOL = 3.2 rnA) and CMOS Interface Input Buffer (True) 2-379
HI
H6CD H6C with Pull-down Resistance 2-381
H6CF 3-state Output and CMOS Interface Input Buffer (IOL = 8 mA,True) 2-422
H6CFD H6CF with Pull-down Resitance 2-424
H6CFU H6CF with Pull-up Resistance 2-423
H6CU H6C with Pull-up Resistance 2-380
H6E Power 3-state Output (IOL = 12 rnA) and CMOS Interface Input Buffer
(True) 2-382
H6ED H6E with Pull-down Resistance 2-384
H6EU H6E with Pull-up Resistance 2-383
H6R 3-state Output (IOL = 3.2 rnA) and Schmitt Trigger Input Buffer
(TTL type, True) 2-388
H6RD H6R with Pull-down Resistance 2-390
H6RU H6R with Pull-up Resistance 2-389
H6S 3-state Output (IOL = 3.2 rnA) and Schmitt Trigger Input Buffer (CMOS type, True) 2-385
H6SD H6S with Pull-down Resistance 2-387
H6SU H6S with Pull-up Resistance 2-386
H6T 3-state Output (IOL = 3.2 rnA) and Input Buffer (True) 2-373
H6TD H6T with Pull-down Resistance 2-375
H6TF 3-state Output and Input Buffer (IOL =8 rnA, True) 2-419
H6TFD H6TF with Pull-down Resistance 2-421
H6TFU H6TF with Pull-up Resistance 2-420
H6TU H6T with Pull-up Resistance 2-374
H6W Power 3-state Output (IOL = 12 rnA) and Input Buffer (True) 2-376
H6WD H6W with Pull-down Resistance 2-378
H6WU H6W with Pull-up Resistance 2-377
H8C 3-state Output Buffer (IOL =3.2 rnA) with Noise limit Resistance and CMOS
Interface Input Buffer (True) 2-397
2-480
CMOS Channel/ess Gate Arrays AU Series Unit Cel/ Ubrary
H8CF 3-state Output Buffer with Noise Limit Resistance and CMOS
Interface Input Buffer (IOL = 8 rnA, True) 2-428
H8CFD H8CF with Pull-down Resistance 2-430
H8E Power 3-state Output Buffer (IOL = 12 mAl with Noise Limit Resistance and
CMOS Interface Input Buffer (True) 2-400
H8ED H8E with PUll-down Resistance 2-402
H8EU H8E with Pull-up Resistance 2-401
H8E2 3-state Output with Noise Limit Resistance and Input Buffer, (CMOS, True) 2-436
H8E1 H8E2 with Pull-up Resistance 2-437
H8EO H8E2 with Pull-down Resistance 2-438
H8R 3-state Output and Schmitt Trigger Input Buffer (TTL type, True)
with Noise Limit Resistance 2-406
H8RD
H8RU
H8S
H8R with Pull-down Resistance
H8R with Pull-up Resistance
3-state Output and Schmitt Trigger Input Buffer (CMOS type, True)
2-408
2-407 16
H8SD H8S with PUll-down Resistance 2-405
H8T 3-state Output with Noise Limit Resistance and Input Buffer (True) 2-391
H8TF 3-state Output with Noise Limit Resistance and Input Buffer
(IOL = 8 mA, True) 2-425
H8TFU HSTF with Pull-up Resistance 2-426
HSTU H8T with Pull-up Resistance 2-392
H8W Power 3-state Output with Noise Limit Resistance and Input Buffer (True) 2-394
H8WU H8W with Pull-up Resistance 2-395
H8W2 3-state Output with Noise Limit Resistance and Input Buffer, (TTL, True) 2-433
H8W1 H8W2 with Pull-up Resistance 2-434
H8WO H8W2 with Pull-down Resistance 2-435
IKB Clock Input Buffer (Inverter) 2-337
IKBD IKB with Pull-down Resistance 2-339
IKBU IKB with Pull-up Resistance 2-338
IKC CMOS Interface Clock Input Buffer (Inverter) 2-409
IKCD IKC with Pull-down Resistance 2-411
IKCU IKC with Pull-up Resistance 2-410
ILB Clock Input Buffer (True) 2-340
ILBD ILB with Pull-down Resistance 2-342
ILBU ILB with Pull-up Resistance 2-341
2-481
AU Series Unit Cel/ Ubrary CMOS Channel/ess Gate Arravs
ILC CMOS Interface Clock Input Buffer (True) 2-412

ILCD ILC with Pull-down Resistance 2-414
ILCU ILC with Pull-up Resistance 2-413
11B Input Buffer Inverter 2-331
11BD 11 B with Pull-down Resistance 2-333
11BU 11 B with Pull-up Resistance 2-332
11C CMOS Interface Input Buffer (Inverter) 2-343
11CD 11 C with Pull-down Resistance 2-345
11CU 11 C with Pull-up Resistance 2-344
11R Schmitt Trigger Input Buffer (TTL Type, Inverter) 2-355
11RD 11R with Pull-down Resistance 2-354
11RU 11 R with Pull-up Resistance 2-356
11S Schmitt Trigger Input Buffer (CMOS Type, Inverter) 2-349
IfJII 11SD
11SU
12B
11S with Pull-down Resistance
11S with Pull-up Resistance
Input Buffer (True)
2-351
2-350
2-334
12BD 12B with Pull-down Resistance 2-336
12BU 12B with Pull-up Resistance 2-335
12C CMOS Interface Input Buffer (True) 2-346
12CD 12C with Pull-down Resistance 2-348
12CU 12C with Pull-up Resistance 2-347
12R Schmitt Trigger Input Buffer (TTL Type, True) 2-358
12RD 12R with Pull-down Resistance 2-360
12RU 12R with Pull-up Resistance 2-359
12S Schmitt Trigger Input Buffer (CMOS Type, True) 2-352
12SD 12S with Pull-down Resistance 2-354
12SU 12S with Pull-up Resistance 2-353
KAB Block Clock (OR) Buffer 2-110
KBB Block Clock Buffer(OR x 10) 2-111
KDB Block Clock Buffer(OR x 10) 2-113
KEB Block Clock Buffer 2-115
K1B True Clock Buffer 2-105
K2B Power Clock Buffer 2-106
K3B Gated Clock (AND) Buffer 2-107
K4B Gated Clock (OR) Buffer 2-108
K5B Gated Clock (NAND) Buffer 2-109
LTK Data Latch 2-261
LTL 1-bit Data Latch with Clear 2-263
LTM 4-bit Data Latch with Clear 2-265
LT1 S-R Latch with Clear 2-268
LT4 4-bit Data Latch 2-270
MC4 4-bit Magnitude Comparator 2-311
2-482
CMOS Channelless Gate Arrays AU Series Unit Cell Ubral}'
NCB Power 12-lnput NAND 2-27

NGB Power 16-lnput NAND 2-28
N2B Power 2-lnput NAND 2-18
N2K Power 2-lnput NAND 2-19
N2N 2-lnput NAND 2-17
N2P Power 2-lnput AND 2-45
N8B
N8P
N9B
Power 8-lnput NAND
Power 8-lnput AND
Power 9-lnput NAND
2-25
2-48
2-26
B
01B Output Buffer (IOl =3.2 mA Inverter) 2-361
01L Power Output Buffer (IOl = 12 rnA Inverter) 2-362
01R Output Buffer (IOl = 3.2 rnA Inverter) with Noise Limit Resistance 2-363
01S Power Output Buffer (IOl = 12 rnA Inverter) with Noise Limit Resistance 2-364
02B Output Buffer (IOl = 3.2 rnA, True) 2-365
02BF Output Buffer (IOL = 8 rnA, True) 2-415
02L Power Output Buffer (IOl = 12 rnA, True) 2-366
02R Output Buffer (IOl = 3.2 rnA, True) with Noise Limit Resistance 2-367
02RF Output Buffer (IOl = 8 rnA, True)with Noise limit Resistance 2-416
02S Power Output Buffer (IOl = 12 rnA, True) with Noise Limit Resistance 2-368
02S2 Output Buffer (IOl = 12 rnA, True) with Noise Limit Resistance 2-431
04R 3-state Output Buffer (IOl = 3.2 rnA, True) with Noise Limit Resistance 2-369
.04RF 3-state Output Buffer (IOl =8 rnA, True) with Noise Limit Resistance 2-418
04S Power 3-state Output Buffer (l0L = 12 rnA, True) with Noise Limit
Resistance 2-370
04S2 3-state Output Buffer (IOl =24 rnA, True) with Noise Limit Resistance 2-432
04T 3-state Output Buffer (IOl =3.2 rnA, True) 2-371
04TF 3-state Output Buffer (IOL = 8 rnA, True) 2-417
04W Power 3-state Output Buffer (IOl = 12 rnA, True) 2-372
PE5 5-bit Even Parity Generator/Checker 2-287
P05 5-bit Odd Parity Generator/Checker 2-288
POB 8-bit Odd Parity Generator/Checker 2-290
1'09 9-bit Odd Parity Generator/Checker 2-292
P24 4-wide 2:1 Data Selector 2-293
2-483
AU Series Unit Cell Ubraty CMOS Channe/less Gate Arrays
RCB Power 12-lnput NOR 2-41

RGB Power 16-lnput NOR 2-42
R2B Power 2-lnput NOR 2-32
R2K Power 2-lnput NOR 2-33
R2N 2-lnput NOR 2-31
R2P Power 2-lnput OR 2-51
HI R8B
R8P
R9B
Power 8-lnput NOR
Power 8-lnput OR
Power 9-lnput NOR
2-39
2-54
2-40
SC7 Scan 4-bit Synchronous Binary Up Counter with Parallel Load 2-209
SC8 Scan 4-bit Synchronous Binary Down Counter with Parallel Load 2-214
SC43 Scan 4-bit Synchronous Binary Up Counter with Asynchronous Clear 2-239
SC47 Scan 4-bit Synchronous Binary Up/Down Counter 2-243
SDA Scan 1-lnput D Flip-flop with Clock Inhibit 2-135
SDB Scan 1-lnput 4-bit D Flip-flop with Clock Inhibit 2-138
SDD Scan 2-lnput D Flip-flop with Clear, Preset, and Clock Inhibit 2-131
SDH Scan 2-lnput D Flip-flop with Clear and Clock Inhibit 2-119
SDJ Scan 4-lnput D Flip-flop with Clear and Clock Inhibit 2-122
SDK Scan 6-lnput D Flip-flop with Clear and Clock Inhibit 2-125
SFDM Scan 1-lnput D Flip-flop with Clock Inhibit 2-157
SFDO Scan 1-lnput D Flip-flop with Clear and Clock Inhibit 2-160
SFDP Scan 1-lnput D Flip-flop with Clear, Preset, and Clock Inhibit 2-163
SFDR Scan 4-lnput D Flip-flop with Clear and Clock Inhibit 2-167
SFDS Scan 4-lnput D Flip-flop with Clock Inhibit 2-171
SFJD Scan J-K Flip-flop with Clock Inhibit 2-175
SHA Scan 1-lnput 8-bit D Flip-flop with Clock Inhibit 2-142
SHB Scan 1-lnput 8-bit D Flip-flop with Clock Inhibit and Q Output 2-145
SHC Scan 1-lnput 8-bit D Flip-flop with Clock Inhibit and XQ Output 2-148
SHJ Scan 8-bit D Flip-flop with Clock Inhibit and 2-to-1 Data Multiplexer 2-151
SHK Scan 8-bit D Flip-flop with Clock Inhibit and 3-to-1 Data Multiplexer 2-154
SJH Scan J-K Flip-flop with Clear and Clock Inhibit 2-128
SR1 Scan 4-bit Serial-in Parallel-out Shift Register with Scan 2-282
T2B 2:1 Selector 2-300
T2C Dual 2:1 Selector 2-301
T2D 2:1 Selector 2-303
2-484
CMOS Chsnne/less Gate Arrays AU Series Unit Ce/I libra!}'
T2E Dual 2:1 Selector 2-304

T2F 2:1 Selector 2-305
T24 Power 2-AND 4-wide Multiplexer 2-83
T54 Power 4-2-3-2 AND 4-wide Multiplexer 2-93
T5A 4:1 Selector 2-307
U24 Power 2-0R 4-wide Multiplexer 2-94
V1L Inverting Clock Buffer 2-9
V1N Inverter 2-7
V2B Power Inverter 2-8
V3A 1 :2 Selector 2-309
V3B Dual 1:2 Selector 2-310
X1B Power Exclusive NOR 2-58
X1N Exclusive NOR 2-57
X2B Power Exclusive OR 2-60
X2N Exclusive OR 2-59
X3B Power 3-lnput Exclusive NOR 2-62
X3N 3-lnput Exclusive NOR 2-61
X4B Power 3-lnput Exclusive OR 2-64
X4N 3-lnput Exclusive OR 2-63
YL2 1-bit Data Latch with TM 2-257
ZOO o Clip 2-325
Z01 1 Clip 2-326
2-485
AU Series Unit Cell Ubmry CMOS Channelless Gats Amays
2-486
Section 3
CG21 Series CMOS Gate Array

Unit Cell Library
I Page Contents
3-2 Unit Cell Specification Information

3-5 Inverter and Buffer Family
3-15 NAND Family
3-29 NOR Family
3-43 AND Family
3-49 OR Family
3-55 EXNOR/EXOR Family
3-65 AND-OR-Inverter Family
3-73 OR-AND-Inverter Family
3-81 MuHiplexer Family
3-103 Clock Buffer Family
3-119 Scan Flip-flop (Positive Edge Type) Family
3-181 Non Scan Flip-flop Family
3-209 Scan Counter Family
3-229 Non-scan Counter Family
3-251 Adder and ALU Family
3-259 Data Latch Family
3-277 Shift Register Family
3-289 Parity Generator/Selector/Decoder Family
3-317 Bus Driver Family
3-327 Clip Cell Family
3-331 I/O Buffer Family
3-437 Appendix A: General AC Specifications
3-439 Appendix B: Hierarchical Structure
3-441 Appendix C: Estimation Tables for Metal Loading
3-447 Appendix D: Available Package Types
3-449 Appendix E: TTL 7400 Function Conversion Table
3-453 Appendix F: Alphanumeric Index of Unit Cells
CG21 Series Unit Cell Library CMOS Channelless Gate Arrays
Unit Cell Specification Information
This section contains specifications for all the unit cells available forthe CG21 Series CMOS Gate Arrays. The
unit cell (gate array) is a functional group of one or more basic cells or gates. A basic cell contains one pair of
P-channel and one pair of N-channel transistors (and two pairs of smaller N-channel resistors used for com-
piled cell construction).
How to Read a Unit Cell Specification
The following paragraphs numbered 1-10 explain how the information given in the CG21 Unit Cell Library is
organized. Each of the numbers corresponds to an area of the Unit Cell Library page illustrated on the right.
1. The unit cell name appears in the upper left corner of the page.
2. The unit cell function is given on the same line as the unit cell name.
3. The number of basic cells (BC) or equivalent that make up the unit cell is shown in the upper right
corner of the page.
4. Propagation delay parameters for the unit cell are given in a table on the upper right side of the
page. The basic delay time of the unit cell (to) is given in ns. KCL, the delay constant for the cell (de-
lay time per load unit) is given in ns/pF. KCL2 and CDR2 are a delay constant and an output driving
factor used to calculate delay when a unit cell is loaded beyond its published output driving factor
(CDR).
5. The cell symbol (logic symbol) is shown in the top left box under the cell name.
6. Clock parameters (in ns) for unit cells such as flip-flops and counters that make use of clock signals
are given in a table directly below the propagation delay parameters.
7. The input loading factor of each input of the unit cell are shown in a table directly under the cell sym-
bol box on the left side of the page. The input loading factor is the value of the load placed on a net
by the connection of the unit cell input. Unit cell loading factors are shown in load units (Iu). The
Fujitsu CMOS load unit is the input capacitance of an inverter used for the measurement and calcu-
lation of capacitive loads presented to unit cells within the gate array.
8. The output drive factor of each output of the unit cell is shown directly under the input loading factor.
The output drive factor is the maximum number of load units the unit cell can drive while performing
at published speCifications.
9. The function table (truth table), if applicable, is shown in a box at the lower left side of the page.
10. The unit cell schematic, or equivalent circuit, illustrates how discrete components would be con-
nected to perform the unit cell function. It is shown in the lower right corner of the page or on the
page following.
3-2
CMOS Channel/ess Gale Arrays CG21 Series Unit Cell Library .
FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION I CG21 K Version

1 T2D 2:1 Sflector 2
Cell Symbol I Propagation Delay Parameter

2 I !Up !dn
Path
3 \0 KCL \0 KCL KCL2 CDR2
4 0.330 0.069 0.370 0.056 A,B~X

0.357 0.069 0.271 0.056 S~X
5
A -
B - o--x
Sl --<l
S2-
'----
7 Input Loading
A,B 1
S 1
8 Output Driving
X 14 . Minimum values for the typical operating conditon.

Inputs Output
A B Sl S2 X
9 A
L X L H H
H X L H L
X L H L H
X H H L L
L H L L INHIBI:r B
L H H H INHIBIT
H L L L INHIBIT Sl
T
H L H H INHIBIT
10 S2
CG21-T2D-EO Sheet 1/1 I I Page20-17
3-3
CG21 Series Unit Cell Ubrary CMOS Channelless Gate Arrays
3-4
CMOS Channel/ess Gate A"ays CG21 Series Unit Cell Library
Inverter, Buffer Family
Unit Cell Basic

3-7 V1N Inverter

3--8 V2B Power Inverter 1
3-9 B1N True Buffer 1
3-10 B03 OelayCeli S
3-11 B04 OelayCeli 4
3-12 BOS OelayCeli 9
3-13 BOS OelayCeli 17
3-5
CG21 Series Unit CeN UbralY CMOS Channe//ess Gate A"ays
3-6
FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION I • CG21K "Version
V1N Inverter 1
Cell Symbol Propagallon Delay Parameter
tup tdn
Path
0.137 0.060 0.203 0.039 0.056 4 Ato X
A~X
Parameter Symbol Typ (ns)'
Input Loading
Pin Name
Factor (Iu)
A 1
Output Driving
Pin Name
Factor (Iu)
X 18
• Minimum values for the typical operating c:ondition.
The values for the worst case operating c:ondition are given by the maximum delay
multiplier.
C21 V1N EO I Sheet 1/1 I

I Page 1-1
3-7
FUJITSU CMOS GATE ARRAY UNITCELL SPECIFICATION I • CG21K • Version
V28 Power Inverter 1

\up teln
Path
0.119 0.032 0.145 0.023 0.039 7 AtoX
A~X
Input loading
Pin Name
Fac\or(lu)
A 2
Output Driving
Pin Name
Factor (Iu)
X 36
The values for the worst case operating condition are gillen by the maximum delay
multiplier.
C21-V2B EO I Sheet 1/1 I

1 Page 1-2
3-8
FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION I .. CG21K .. Version
B1N True Buffer 1

\Up tdn
Path
0.310 0.060 0.363 0.039 AloX
A~X
Input Loading
Pin Name
Factor (Iu)
A 1
Output Driving
Pin Name
Factor (Iu)
X 18
The values lor the worst case operating condition are given by the maximum delay
multiplier.
C21 B1N EO I Sheet 1/1 I

1 Page 1-3
3-9
FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION I " CG21K " Version
BD3 Delay Cell 5

\Up tdn
Path
2.818 0.060 2.488 0.056 0.062 4 Ato X
A-(>----X
Input loading
Pin Name
Factor (Iu)
A 1
Output Driving
Pin Name
Faclor(lu)
X 18
multiplier.
C21-BD3-EO I Sheet 1/1 I

T Page 1-4
3-10
FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION I • CG21K • Version
BD4 Delay Cell 4

\up tdn
Path
to KCL to KCL KCL2 COR2
1.881 0.211 2.165 0.140 0.162 4 Ato X
A--{>--X
Parameter Symbol Typ (ns)·
Input Loading
Pin Name
Factor (Iu)
A 4
Output Driving
Pin Name
Factor (Iu)
X 6
• Minimum values for the typical oparating condition.
The values for the worst case oparating condition are gi\'lln by the maximum delay
multiplier.
C21 BD4-EO I Sheet 1/1 I

I Page 1-5
3-11
FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION I . CG21K • Version
8DS OeJayCelJ 9
tup teln
Pa!h
5.769 0.060 5.465 0.045 0.067 4 AtoX
A-{>-X
Input loading
Pin Name
Factor (Iu)
A 1
DI Pin Name
Output Driving
Factor (Iu)
X 18
• Minimum values for !he typical operating condition.
The values for !he worst case operating condition are given by !he maximum delay
multiplier.
C21 80S-EO I Sheet 1/1 I

I Page 1-6
3-12
Cell Name Function Number 01 BC
B06 Delay Cell 17

Cell Symbol Propagation Delay Parameler
IUp IeIn
Path
11.616 0.064 11.524 0.039 0.062 4 Ato X
A-{>--X
Input loading
Pin Name
Factor (Iu)
A 1
Output Driving
Pin Name
Factor (Iu)
X 18
• Minimum values lor the typical operating con!fition.
multiplier.
C21 BOS-EO I Sheet 1/1 I

I Page 1 7
3-13
CG21 Series Unit Cen Ubraty CMOS Channa/less Gate Arrays
3-14
CMOS Channel/ess Gate Arrays CG21 Series Unit Cell Library
NAND Family
Unit Cell Basic


3-19 N2K Power 2-input NAND 2
3-27 NCB Power 12-input NAND 10
3-28 NGB Power 16-input NAND 11
III
3-15
CG21 Series Unit CeH LibraI)' CMOS Channelless Gate Anays
3-16
Cell Nama Funcllon NumberofBC
N2N 2-input NAND 1

\up teln
Path
0.179 0.060 0.326 0.062 AloX
Al=:{»-X
A2
Input Loading
Pin Name
Factor (Iu)
A 1
Output Driving
Pin Name
Faclor (Iu)
X 18
multiplier.
C21 N2N EO I Sheet 111 I

I Page 2-1
3-17
FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION I "CG21K· Version
N2B Power 2-input NAND 3

\up teln
Path
0.581 0.032 0.753 0.017 AtoX
~ ::::[»-- X
Input loading
Pin Name
Fac\or(lu)
A 1
IDI Pin Name

Output Driving
Fac\or(lu)
X 36
• Minimum velues for the typical operating condition.
The values lor the worst case operating condition are given by Ihe maximum delay
multiplier.
C21-N2B-EO I Sheet 1/1 I

I Page 2-2
FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION J • CG21K· Version
Cel/Name Function NumberofBC
N2K Power 2-input NAND 2

Cel/Symbol Propagation Delay Parameter
lOp tdn
Path
0.179 0.032 0.254 0.034 0.039 7 AtoX
A1~X
A2
Inpu1 Loading
Pin Name
Factor (Iu)
A 2
Output Driving
Pin Name
Factor (Iu)
X 36
The values for the worst case operating condition are given by !he maximum delay
multiplier.
C21-N2K EO I Sheet 1/1 I

1 Page 2-3
3-19
FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION I . CG21K' Version
N3N 3-input NAND 2

!Up tdn
Path
0.250 0.060 0.399 0.084 AtoX
A
A2 1 = O - X
A3
Input loading
Pin Name
Factor (Iu)
A 1
Output Driving
Pin Name
Factor (Iu)
X 14
• Minimum values lor the typical operating condition.
The values lor the worst case operating condiiion ara given by the maximum delay
multiplier.
C21 N3N EO I Sheet 1/1 I

I Page 2-4
3-20
FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION I • CG21K· Version

bJp teln
Path
0.680 0.032 0.898 0.017 AtoX
At=l}-
~ X
Input loading
Pin Name
Faclor(lu)
A 1
Pin Name
Output Driving
Faclor(lu)
11.1
X 36
multiplier.
C21-N3B-EO 1 Sheet 1/1 I

I Page 2-5
3-21
N4N 4-input NAND 2

tup Idn
Path
0.298 0.060 0.428 0.106 Ato X
"m- A2
A3
A4
X
Input loading
Pin Name
Factor (Iu)
A 1
Output Driving
Pin Name
Factor (Iu)
X 10
multiplier.
C21 N4N-EO I Sheet 1/1 I

I Page 2-6
3-22

!Up Idn
Path
10 KCl to KCl KCl2 CDR2
0.733 0.032 1.003 0.017 Ato X
A'~
A2
A3
A4
Parameler Symbol Typ (ns)·
Input loading
Pin Name
Factor (Iu)
A 1
Output Driving
Pin Name
Factor (Iu)
X 36
• Minimum values for lhe typical operating condidon.
The values for the worst case operaling condition are given by the maximum delay
muldplier.
C21 N4B-EO I Sheet 1/1 I

I Page 2-7
3-23
FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION I . CG21K" Version
N68 Power 6-input NAND 5

IUp !dn
Path
to KCL 10 KCL KCL2 CDR2
0.726 0.032 1.069 0.017 0.034 7 AtoX
"§}-
A2
A3
A4
AS
AS
X
Input loading
Pin Name
Factor (Iu)
A 1
Output Driving
Pin Name
Factor (Iu)
X 36
• Minimum values for the typical opereting con~tion.
multiplier.
Equivalent Circuit
Al
A2
A3
X
A4
AS
AS
C21-N6B-EO I Sheet 1/1 I

I Page 2-8
3-24
FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION • CG21K " Version
NBB Power 8-input NAND 6

!Up tdn
Path
0.759 0.032 1.16B 0.017 0.034 7 AtoX
Al-"""
A2-
A3-
A4-
AS-
:>-- X
A6-
A7-
A8-/
Input Loading
Pin Name
Factor (Iu)
A
Output Driving
Pin Name
Factor (Iu)
X 36
multiplier.
Equivalent Circuit
Al _r'I
A2-
A3-
A4-l/
X
AS _ r ' I
A6-
A7-
A8-l/
r
C21 NBB EO I Sheet 111 I

I Page 2-9
3-25
FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION I" CG21K "Version
N98 Power 9-input NAND 8

\up !dn
Path
0.753 0.032 1.406 0.023 ·0.039 7 AtoX
AI _I"'.
A2-
A3-
A4-
AS- p....-x
A6-
A7-
AS-
A9 - [ . , . I
Input loading
Pin Name
Factor (Iu)
A 1
Output Driving
Pin Name
Factor (Iu)
X 36
The values for the worst case operating condition are given by the maximum delay.
multiplier.
Equivalent Circuit
AI
A2
A3
A4
AS X
A6
A7
AS
A9
C21-N9B-EO I Sheet 111 I

Page 2-10
3-26
NCB Power 12-input NAND 10

\up teln
Palh
0.805 0.032 1.512 0.023 0.039 8 AtoX
AI _r-.
A2-
A3-
A4-
AS-
A6-
:r-X
A7-
AB-
A9-
Al0-
All-
AI2-L,...I
Input Loading
Pin Name
Factor (Iu)
A 1
Output Driving
Pin Name
Factor (Iu)
X 36
The values for Ihe worst case operating condition are given by Ihe maximum delay
multiplier.
Equivalent Circuit
"-}-
A2-
A3-
A4-,/
AS-It.
A6-
X
A7-lJ
AB-
A9-l""-l
Al0-
A12-
AI2-L,...I
r--
C21 NCB-EO I Sheet 1/1 I
1 Page 2-11
3-27
Cel/Name Function Number 01 Be
NGB Power 16-input NAND 11

!Up teln
Path
0.812 0.032 1.835 0.028 0.039 8 AtoX
Al--'"
A2-
A3-
A4-
A5-
A6-
A7-
AS-
A9-
::>-- X
Al0-
All-
A12-
A13-
A14-
A15-
A16-1...)
Input Loading
Pin Name
Factor (Iu)
A 1
III Pin Name

Output Driving
Factor (Iu)
X 36
• Minimum values for the typical operating cendi.tion.
multiplier.
Equivalent Circuit
Al-l.
A2-
A3- f
A4-./
::=hb t--f>o-.
A7-
AS - ./
4-'"
X
"-'}---rp
Al0-
All-
A12-1...)
r<./
A13-f""'I
A14- I
A15-
A16-1...)
r
C21 NGB-EO I Sheet 1/1 I
I Page 2-12
3-21:1
CMOS Channelless Gale Arrays CG21 Series Unit Cell Library
NOR Family
Unit Cell Basic

3-31 R2N 2-input NOR

3-33 R2K Power 2-input NOR 2
3-41 RCB Power 12-input NOR 10
3-42 RGB Power 16-input NOR 11
3-29
CG21 Series Unit Cel/ Ubrary CMOS Channel/ess Gale Arrays
3-30
R2N 2-input NOR 1

!Up !dn
Path
0.191 0.106 0.254 0.039 0.050 4 Ato X
Al=t»-X
A2
Input Loading
Pin Name
Factor (Iu)
A 1
Output Driving
Pin Name
Factor (Iu)
X 14
multiplier.
C21 R2N-EO I Sheet 1/1 I

1 Page 3-1
3-31
FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION I" CG21K" Version
R2B Power 2-input NOR 3

tup !dn
Pa1ll
0.720 0.032 0.660 0.017 AtoX
~=t>-x
Input loading
Pin Name
Factor (Iu)
A 1
Output Driving
Pin Name
Factor (Iu)
X 36
• Minimum values for 1IIe typical operating condition.
multiplier.
C21-R2B-EO I Sheet 1/1 I

1 Page 3-2
3-32
FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION • CG21K .. Version
R2K Power 2-input NOR 2

tup tdn
Path
0.214 0.051 0.261 0.028 AtoX
AI
A2
:::::b»- X
Input Loading
Pin Name
Factor (Iu)
A 2
Output Driving
Pin Name
Faclor(lu)
X 36
multiplier.
C21 R2K EO I Sheet 111 I

I Page 3-3
3-33
R3N 3-input NOR 2

!Up !dn
Path
to KCl to KCl KCl2 CDR2
0.399 0.151 0.268 0.039 0.056 4 Ato X
A3Al=&-
A2 X
Input loading
Pin Name
A
Factor (Iu)
1
Output Driving
Pin Name
Factor (Iu)
X 10
The values for the worst case operating concfiiion are given by the maximum delay
multiplier.
C21 R3N EO I Sheet 1/1 I

I Page 3-4
3-34
Cell Name Function Number 01 DC

tup tdn
Path
1.050 0.032 0.726 0.017 AtoX
~
Al~ X
Input loading
Pin Name
Factor (Iu)
A 1
Output Driving
Pin Name
Fac1or(lu)
X 36
multiplier.
C21 R3B EO I Sheet 1/1 I

I Page 3-5
3-35
Cell Name Function Numbarof BC
R4N 4-input NOR 2

\up tdn
Path
0.589 0.197 0.268 0.039 0.062 4 AtoX
..~ ~ X
A4
Parameter Symbol Typ (ns) *
Input loading
Pin Name
Factor (Iu)
A 1
III Pin Name

Output Driving
Factor (Iu)
X 6
multiplier.
C21 R4N EO I Sheet 1/1 I

I Page 3-6
3-36

tup teln
Path
1.320 0.032 0.706 0.017 Ato X
.. ~
~
A4
X
Input loading
Pin Name
Factor (Iu)
A 1
Output Driving
Pin Name
Factor (Iu)
X 36
multiplier.
C21-R4B-EO I Sheet 1/1 I

I Page 3-7
3-37
FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION I "CG21K" Version
R68 Power 6-input NOR 5

!up !dn
Path
1.188 0.032 0.786 0.017 Ato X
"j-A2
A3
A4
AS
A6
X
Parameter Symbol TVp (ns)'
Input loading
Pin Name
Factor (Iu)
A 1
Output Driving
Pin Name
Factor (Iu)
X 36
• Minimum values lor the typical operating cond!tlon.
multiplier.
Equivalent Circuit
Al --F\.
A2
A3
---b! I ..r-..
::J X
A4--F\
I .......
AS
AS
---b!
C21 R6B EO I Sheet 111 I

I Page 3-8
3-38
FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION • CG21K· Version
RB8 Power 8-input NOR 6

IUp tdn
Path
1.498 0.032 0.799 0.017 Ato X
Al-~
A2--
A3--
A4
:>-- X
AS- -
A6--
A7--
AS - ; : 1
Input Loading
Pin Name
Factor (Iu)
A 1
Output Driving
Pin Name
Factor (Iu)
X 36
multiplier.
Equivalent Circuit
AI-PI
A 2 - "-
A3-'1
A4-b' ..r-..
J X
"1.00'
AS-\-J
A6
A7 -
AS-b'

I Page 3-9
3-39

tu tdn
Pa!h
1.314 0.032 0.891 0.017 AtoX
A1-~
A2-f-
A3-f-
A4-f-
AS X
A6-f-
A7-f-
AS-I-
A9-1/
Input Loading
Pin Name
Factor (Iu)
A 1
Output Driving
Pin Name
Factor (Iu)
X 36
multiplier.
Equivalent Circuit
Al--F\.
A2
A3
----bf
...,......
A4--F\ ;]1
AS
A6
---b! ;:] J
.........
X
A7--F\
AS
A9 ---b!

I Page3-10
3-40
RCB Power 12-input NOR 10

IUp tdn
Path
1.446 0.032 0.924 0.017 Ato X
Al-P>-
A 2 - f-
A 3 - f-
A 4 - f-
A S - f-
AS
P--X
A7 -
A S - f-
A9 - f -
Al0 - f -
All-f-
A12-t::;.
Input Loading
Pin Name
Factor (Iu)
A 1
Output Driving
Pin Name
Factor (Iu)
X 36
The values for the worst case operating condition are given by the' maximum delay
multiplier.
Equivalent Circuit
Al -----E\
A2
A3
--bf
A4 ----F\
--t!
-<~X
AS
AS
A7--F\
AS --b/ r<=t:7
A9
Al0 --F\
All
A12
--b/
C21 RCB-EO I Sheet 1/1 I

T Page 3-11
3-41
Cell Nama Function NumberolBC
RGB Power 16-input NOR 11

tup tdn
Path
1.815 0.032 0.964 0.017 Ato X
Al-~
A2--
A3--
M--
AS--
AS--
A7--
AS
A9-
Al0--
- :r--x
All--
AI2--
AI3--
Parameter Symbol Typ (ns) ,
AI4--
AI5--
AI6-;1
Input loading
Pin Name
Factor (Iu)
A 1
III Pin Name

Output Driving
Factor (Iu)
X 36
, Minimum values lor the typical operating con~ition.
multiplier.
EqUiValan~ir:cuit
:- )
:-d
AS-~
A 6 - ....
A7 h-c=,
AS-t:;;o ~X
A9-\-J
Al0
-c :7I .
Al1-r-
A12 - t : ;
AI3-~
A14-1-
A15
AI6-t;,
C21 RGB-EO I Sheet 1/1 I
I Page3-12
3-42
CMOS Channel/ess Gate Arrays CG21 Series Unit Cell Ubrary:
AND Family
Unit Cell Basic


3-43
CG21 Series Unit Cell Library CMOS Channelless Gate AlTBYs
3-44
FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION I • CG21 K • Version
N2P Power 2-input AND 2

\up teln
Path
10 KCL 10 KCL KCl2 CDR2
0.535 0.032 0.456 0.017 0.028 7 Ato X
:=I)-x
Input loading
Pin Name
Factor (Iu)
A 1
Pin Name
Output Driving
Factor (Iu)
III
X 36
The values lor the worst case operating condition are given by !he maximum delay
multiplier.
C21 N2P EO I Sheet 1/1 I

I Page 4-1
3-45

tup tdn
Palh
to KCL to KCL KCL.2 CDR2
0.700 0.032 0.568 0.017 0.028 7 Ato X
Al=t)-
~ X
Input loading
Pin Name
Faclor(lu)
A 1
Output Driving
Pln'Name
Factor (Iu)
X 36
• Minimum values for Ihe typical operating condition.
multiplier.
C21 N3P EO I Sheet 1/1 I

I Page 4-2
3-46
Cell Name Funcllon NumberofBC

\Up tdn
Pa!h
0.838 0.032 0.627 0.017 0.028 8 Ato X
.,~
A2
A3
X
A4
Input Loading
Pin Name
Factor (Iu)
A 1
Output Driving
Pin Name
Factor (Iu)
X 36
multiplier.
C21 N4P EO I Sheet 1/1 J

I Page 4-3
3-47
NBP Power 8-input AND 6

\up teln
Path
0.911 0.051 0.766 0.017 0.028 8 Ato X
Al-""'"
A2-
A3-
A4-
A5-
-x
A6-
A7-
AB-.,)
Input Loading
A 1
IDI Pin Name

Output Driving
Factor (Iu)
X 36
• Minimum values for the typical operating ool1c1ition.
The values for the worst case operating oondition are given by the maximum delay
multiplier.
Equivalent Circuit
Al-""'"
A2-
A3-
A4-l.,)
X
A5-""I
A6-
A7-
AB-.,)
C21-N8P EO I Sheet 1/1 I

I Page 4-4
3-48
CMOS Channelless Gate Arrays CG21 Series Unit Cell Library
OR Family
Unit Cell Basic


3-49
CG21 Series Unit Cel/ Library CMOS Channel/ess Gate Arrays
3-50
R2P Power 2-inputOR 2

\up tdn
Path
0.416 0.032 0.601 0.023 0.034 8 Ato X
Al=t/-X
A2
Input Loading
Pin Name
Factor (Iu)
A 1
Output Driving
Pin Name
Factor (Iu)
X 36
multiplier.
C21 R2P EO I Sheet 1/1 I

I Page 5-1
3-51
FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION I .. CG21K" Version
R3P Power 3-input OR 3

tup tdn
Path
0.475 0.032 0.970 0.028 0.039 8 AloX
Al=9- X
A2
A3
Input Loading
Pin Nama
Factor (Iu)
A 1
Output Driving
Pin Name
Factor (Iu)
X 36
multiplier.
C21 R3P EO I Sheel1/1 I

I Page 5-2
3-52
R4P Power 4-input OR 3

tup !dn
Path
0.475 0.032 1.333 0.034 0.045 8 AtoX
.. ~
A2
A3
X
A4
Input loadIng
PIn Name
Factor (Iu)
A 1
Output DrIvIng
PIn Name
Factor (Iu)
X 36
, Minimum values for the typical operating condidon.
multiplier.

I Page 5-3
3-53
CeUName Function Number olBC
RBP Power B-input OR 6

IUp !dn
Path
0.522 0.032 1.419 0.039 0.045 8 AloX
A1-~
A2--
A3....,..---
A4- - - X
AS- -
AS-I-
A7-1-
A8-t7
Input Loading
Pin Name
Factor (Iu)
A 1
Output Driving
Pin Name
Factor (Iu)
X 36
• Minimum values lor the typical operating conc!ition.
multiplier.
Equivalent Circuit
A1-~
A2--{
A3-,
A4-";::J ..r-...
J
..,.... X
AS-\-J
AS- -
A7
AS-";::J

I Page 5-4
3-54
EXNOR/EXOR Family
Unit Cell Basic

3-57 X1N Exclusive NOR 3

3-58 X1B Power Exclusive NOR 4
3-59 X2N Exclusive OR 3
3-60 X2B Power Exclusive OR 4
3-61 X3N 3-inpul Exclusive NOR 5
3-62 X3B Power 3-inpul Exclusive NOR 6
3-63 X4N 3-inpul Exclusive OR 5
3-64 X4B Power 3-inpul Exclusive OR 6
3-55
CG21 Series Unit CeR Library CMOS Channel/ess Galli Arrays
III
3-56
Cell Name Function Number olBC
X1N Exclusive NOR 3

!Up tdn
Path
0.614 0.106 0.508 0.062 0.073 4 Ato X
Al~X
A2
Input Loading
Pin Name
Factor (Iu)
A 2
Pin Name
Output Driving
Factor (Iu)
III
X 18
• Minimum values for the typical operating oondition.
multiplier.
Equivalent Circuit
~ Ill) I s> X
C21-X1N-EO I Sheet 1/1 I

I Page 6-1
3-57
eeliName Function Number of BC
X1B Power Exclusive NOR 4

!Up tdn
Path
10 KCL 10 KCL KCL2 CDR2
0.786 0.032 0.937 0.023 0.039 7 AtoX
Al~X
A2
Inpul Loading
Pin Name
Faclor(lu)
A 2
Output Driving
Pin Name
Faclor(lu)
X 36
multiplier.
Equivalent Circuil
::lb ~x
C21-X1B-EO I Sheet 1/1 I

I Page 6-2
3-58
FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION I . CG21K· Version
X2N Exclusive OR 3
!Up Idn
Path
0.588 0.106 0.621 0.062 0.073 4 AtoX
Al=+tl-X
A2
Input Loading
Pin Name
Faclor(lu)
A 2
Pin Name
Oulput Driving
Faclor(lu)
III
X 14
multiplier.
Equivalent Circuit
::~ [j>-x
C21 X2N EO I Sheet 1/1 I

I Page 6-3
3-59
X28 Power Exclusive OR 4

tup teln
Path
0.759 0.032 0.865 0.023 0.034 7 Ato X
Al=+tJ-X
A2
Input loading
Pin Name
Factor (Iu)
A 2
Output Driving
Pin Name
Factor (Iu)
X 36
* Minimum values for the typical operating con~ition.
multiplier.
Equivalent Circuit
:; Ijl> I cP'-'t> X
C21-X2B-EO I Sheet 1/1 I

I Page 6-4
3-60
X3N 3-input Exclusive NOR 5

!Up !dn
Path
10 KCL to KCL KCL2 CDR2
1.439 0.106 1.228 0.062 0.073 4 AtoX
Al~
:~x
Input Loading
Pin Name
Faclor(lu)
A 2
Pin Name
Outpul Driving
Factor (Iu)
III
x 18
multiplier.
Equivalent Circuit
~~
A3
Al X
C21 X3N-EO I Sheet 111 I

I Page 6-5
3-61
FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION I " CG21K" Version
X3B Power 3-input Exclusive NOR 6

\up IlIn
Path
1.393 0.032 1.789 0.023 0.039 7 AtoX
A
A2 t = n r - X
A3
Input Loading
Pin Name
Factor (Iu)
A 2
Output Driving
Pin Name
FaClor (Iu)
X 36
multiplier.
Equivalent Circuit
A2
A3
X
At IV
C21 X3B-EO I Sheet 111 I

1 Page 6-6
3-62
X4N 3-input Exclusive OR 5

!Up tdn
Path
1.492 0.106 1.340 0.062 0.073 4 AtoX
A1=Ur-
A2 x
A3
Input Loading
Pin Name
Factor (Iu)
A 2
Output Driving
Pin Name
Factor (Iu)
X 14
multiplier.
Equivalent Circuit
: I~ ID '
C21 X4N EO I Sheet 1/1 I

I Page 6-7
3-63
FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION I • CG21 K· Version
X48 Power 3-input Exclusive OR 6

tup tdn
Path
1.307 0.032 1.657 0.023 0.034 7 Ato X
A1=&- X
A2
A3
Input LoadIng
PIn Name
Factor (Iu)
A 2
Output DrIvIng
PIn Name
Factor (Iu)
X 36
multiplier.
Equivalent Circuit
A2
A3
X
A1 ........
C21 X4B EO I Sheet 1/1 I

I Page 6-8
3-64
AND-OR-Inverter Family
Unit Cell Basic


3-72 044 2-wide 2-0R 2-ANO 4-input AOI 2
3-65
CG21 Series Unit CeO Library CMOS Channel/ess Gate Arrays
3-66
023 2-wide 2-AND 3-input AOI 2

!Up tdn
Path
0.351 0.106 0.399 0.062 AtoX
0.179 0.083 0.218 0.039 0.056 4 BtoX
A1~
A~ X
Input loading
Pin Name
Fac\or(lu)
A 1
B 1
Output Driving
Pin Nama
Factor (Iu)
X 14
multiplier.
C21 D23-EO I Sheet 1/1 I

1 Page 7-1
3-67
FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION I CG21K· Version
n
D14 2-wide 3-AND 4-input AOI 2

rup Idn
Path
0.429 0.106 0.406 0.084 0.095 4 AtoX
0.155 0.073 0.210 0.039 0.056 4 BtoX
.,~
A2
A3
8 X
Input loading
Pin Name
Factor (Iu)
A 1
8 1
Output Driving
Pin Name
Factor (Iu)
X 14
multiplier.
C21-D14-EO I Sheet 1/1 I

I Page 7-2
3-68
FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION J" CG21K" Version
Cell Name Function Number ofBC

\up !dn
Pa!h
0.256 0.083 0.363 0.062 Ato X
0.322 0.083 0.486 0.062 BtoX
M>
A2
Bl
B2
X
Pin Name .. Input Loading

Factor (Iu)
A 1
B 1
Output Driving
Pin Name
Factor (Iu)
X 14
multiplier.
C21 D24-EO I Sheet 1f1 I

I Page 7-3
3-69

tup tdn
Path
0.548 0.151 0.428 0.067 Ato X
0.298 0.128 0.254 0.039 0.056 4 BtoX
.,~
A2
81 X
82
Input Loading
Pin Name
Factor (Iu)
A 1
8 1
DI Pin Name
Output Driving
Factor (Iu)
X 10
• Minimum values for the typical operating conqition.
The values for the worst case operating condition ara given by the maximum delay
multiplier.
C21 D34-EO 1 Sheet 1/1 I

I Page 7-4
3-70
FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION I • CG21K" Version

tup tdn
Path
0.369 0.106 0.421 0.062 Ato X
0.470 0.106 0.508 0.062 Bto X
0.560 0.106 0.595 0.062 CloX
Al
A2
B1
X
B2
Cl
C2
Input loading
Pin Name
Factor (Iu)
A 1
B 1
C 1
Output Driving
Pin Name
Factor (Iu)
X 10
The values for the worst case operaling condition are given by the maximum delay
multiplier.
C21-D36-EO I Sheel1/1 I
I Page 7-5
3-71
D44 2-wide 2-OR 2-AND 4-input ADI 2

!Up tdn
Palh
0.494 0.151 0.457 0.062 Ato X
0.494 0.151 0.370 0.062 Bto X
0.470 0.106 0.283 0.039 0.050 4 CtoX
1~x
Parameler Symbol Typ (ns)'
Input loading
Pin Name
Faclor(lu)
A 1
B 1
C 1
Output Driving
Pin Name
Faclor(lu)
X 10
The values for lhe worst case operating condition are given by lhe maximum delay
multiplier.
C21 OM-EO I Sheet 1/1 I

I Page 7-6
3-72
CMOS Channelless Gate Arrays CG21 Series Unit Cell LibraI}'
OR-AND-Inverter Family
Unit Cell Basic


3-79 G44 2-wide 2-AND 2-0R 4-input OAI 2
3-73
IDI
3-74
G23 2-wide 2-OR 3-input OAI 2

tup tdn
Path
0.345 0.106 0.319 0.062 Ato X
0.137 0.060 0.319 0.062 Bto X
Al~
A~ X
Input Loading
Pin Name
Factor (Iu)
A 1
B 1
Output Driving
Pin Name
Factor (Iu)
X 18
multiplier.
C21 G23 EO I Sheet 1/1 I

I Page 8-1
3-75
FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION 1" CG21K· Version

IUp Idn
Path
0.571 0.156 0.377 0.062 -..-A to X
0.119 0.060 0.377 0.062 BtoX
.,~
A2
A3
B X
Input Loading
Pin Name
Factor (Iu)
A 1
B 1
Output Driving
Pin Name
Factor (Iu)
X 10
multiplier.
C21-G14-EO I Sheet 1/1 I

I Page 8-2
3-76
G24 2-wide 2-QR 4-input OAI 2

!Up !dn
Path
0.238 0.106 0.406 0.062 AtoX
0.429 0.106 0.348 0.062 BtoX
">
A2
Bl
B2
X
Input Loading
Pin Name
Factor (Iu)
A 1
B 1
Output Driving
Pin Name
Factor (Iu)
X 10
mutdplier.
C21-G24-EO I Sheet 1/1 I

I Page 8-3
3-77
Cell Name Function Number of 8C

CeIJSymbol Propagation Delay Parameter
!Up tdn
Path
0.452 0.106 0.406 0.084 AtoX
0.333 0.069 0.261 0.073 BtoX
.,~
A2
81 X
82
Input loading
Pin Name
Factor (luI
A 1
8 1
Output Driving
Pin Name
Factor (Iu)
X 10
multiplier.
, C21-G34 EO I Sheet 1/1 I

I Page 8-4
3-78
G44 2-wide 2-AND 2-OR 4-input OAI 2

IUp Idn
Path
0.351 0.106 0.500 0.084 AtoX
0.208 0.106 0.363 0.084 BtoX
0.238 0.060 0.305 0.062 CtoX
:~~x
Input loading
Pin Name
Factor (Iu)
A 1
B 1
C 1
Output Driving
Pin Name
Factor (Iu)
X 14
multiplier.
C21 G44 EO I Sheet 1/1 I

I Page 8-5
3-79
CMOS Channe/less Gate Arrays CG21 Series Unit CeR Library
3-80
CG2! Series Unit Cell Library CMOS Channel/ess Gate Arrays
Multiplexer Family
Unit Cell Basic


3-93 T54 Power 4-3-3-2 AND 4-wide Multiplexer 10
3-98
3-99
U33
U34
Power 3-0R 3-wide Multiplexer
Power 3-0R 4-wide Multiplexer
7
9
III
3-81
3-82
T24 Power 2-AND 4-wide Multiplexer 6

IUp tdn
Path
0.858 0.032 0.805 0.017 Ato X
0.951 0.032 0.931 0.017 8to X
0.838 0.032 0.865 0.017 eto X
0.911 0.032 0.997 0.017 DtoX
Al
A2
:~~~J:>--x
~~=DT~
01
Input loading
Pin Name
Factor (Iu)
A 1
B 1
C 1
0 1
III
I
Output Driving
Pin Name
Factor (Iu)
X 36
The values lor the worst ease operating condition are given by the maximum delay
multiplier.
Equivalent Circuit
~=Ch
B1=C
B2 .r-...
J
.,.... X
~=C)-l
01=C
02
C21 T24-EO I Sheet 1/1 I

I Page 9-1
3-83

!up !dn
Path
0.997 0.032 0.832 0.017 Ato X
Al=D- 1.096 0.032 0.957 0.017 BtoX
A2 0.997 0.032 0.878 0.017 Cto X
1.076 0.032 1.017 0.017 DtoX
81 1.003 0.032 0.970 0.017 EtoX
82 1.089 0.032 1.102 0.017 FtoX
p"
C l = D f r-
C2
r-~x
r-
D 1 = D T . r-
02
D
El
E2 Parameter Symbol Typ (ns)'
Fl=D-
F2
Input Loading
A 1
8 1
C 1
0 1
E 1
F 1
Output Driving
X 36 • Minimum values lor the typical operating condi~on.
multiplier.
Equivalent Circuit
::=ClJ-
81=C
82
Cl=C
C2 =t. ..l'..
:.J I X
01
02
=C::I .,..,
;:J J
;:=C)-
F1=C
F2
C21 T26-EO I Sheet 1/1 I

I Page 9-2
3-84
Cel/Name Function Number of BC

CeUSymbol Propagation Delay Parameter
!Up tdn
Path
Al~ 1.122 0.032 0.805 0.017 Ato X
A2~ 1.228 0.032 0.951 0.017 BtoX
1.122 0.032 0.891 0.017 CtoX
1.208 0.032 1.036 0.017 Oto X
1.162 0.032 1.142 0.017 Eto X
1.248 0.032 1.102 0.017 FtoX
1.162 0.032 1.017 0.017 GtoX
1.248 0.032 1.155 0.017 H to X
Gl~
G2 --t.J
Hl=D-
H2
Input Loading
Pin Name
Factor (Iu)
A
B
C
o
III
E
F
G
H
Output Driving
Pin Name
Factor (Iu)
x 36
multiplier.
C21-T28 EO I Sheet 1/2 I

I Page 9-3
3-85
FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION • CG21 K • Version
Cell Name
T28
Equivalent Circuit
Al
A2
Bl
B2
Cl
C2
01
02
X
El
E2
Fl
F2
Gl
G2
HI
H2
III
C21-T28-EO Sheet 2/2

Page 9-4
3-86
Cell Name Funcdon Number 01 BC

\up \dn
Path
0.805 0.032 0.891 0.017 AtoX
0.805 0.032 0.951 0.017 BtoX
Al
A2
A3
X
Bl
B2
B3
Parameter Symbol Typ(ns)'
Input loading
Pin Name
Factor (Iu)
A 1
B 1
Output Driving
Pin Name
Factor (Iu)
X 36
• Minimum values lor the typical oparating condition.
The values lor the worst case oparating condition are given by the maximum delay
multiplier.
Equivalent Circuit
Al
A2
AS ..r-..
:J X
Bl .....
B2
B3
C21 T32 EO I Sheet 1/1 I

I Page 9-5
3-87
FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION I • CG21 K .. Version
Cell Name Function Number 01 BC.

!Up teln
Path
0.924 0.032 0.878 0.017 AtoX
0.924 0.032 0.944 0.017 BtoX
0.924 0.032 1.030 0.017 CtoX
.,~
A2
A3
Bl
X
~~
B3
Cl
C2
C3 Parameter Symbol Typ (ns) "
Input Loading
Pin Name
Factor (Iu)
A 1
B 1
C 1
Output Driving
Pin Name
Factor (Iu)
X 36
• Minimum values lor the typical operating condilion.
The values lor the worst case operating condition are giwn by the maximum delay
multiplier.
C21 T33-EO I Sheet 111 I

-I Page 9-6
3-88
T34' Power 3-AND 4-wide Multiplexer 9

tup tdn
Palll
1.102 0.032 0.911 0.017 AloX
1.102 0.032 0.997 0.017 810 X
"=1)-
A2
A3
1.155
1.155
0.032
0.032
1.056
1.063
0.017
0.017
CloX
010 X
"=Th!
B2
B3
~
*-x
C
C2 1 = i f r
:;,
C3
"=1)- Parameter Symbol Typ (ns)·

02
03
Input Loading
Pin Name
Factor (Iu)
A 1
B 1
C 1
0 1 ,
Output Driving
Pin Name
Factor (Iu)
X 36
multiplier.
Equivalent Circuit
A1
A2
A3
B1
B2
B3
-<}+-x
C1
C2 rCt:7
C3
01
02
03
C21 T34 EO I Sheel1/1 I

I Page 9-7
3-89

!Up !dn
Path
0.845 0.032 0.997 0.017 Ato X
0.845 0.032 1.056 0.017 BloX
A1-f"",
A2-
A3-
A4-1..)
X
B1 _f""'I
82-
83-
84-1..)
Input Loading
Pin Name
Factor (Iu)
A 1
8 1
Output Driving
Pin Name
Factor (Iu)
X 36
multiplier.
Equivalent Circuit
"-Ii
A2-
A3-
A4-./ ..r-...
J
"-[}-f
X
"\/
82-
83-
84-
C21 T42 EO I Sheel111 I

I Page 9-8
3-90

!Up !dn
Path
0.997 0.032 1.017 0.017 AtoX
0.997 0.032 1.076 0.017 BtoX
A1-i""'I 0.997 0.032 1.162 0.017 Cto X
A2-
A3-
I-
A4-,-"
91-i""'I
92-
93-
f\ X
94-,-" rtf
C1-i""'I
C2-
t- Parameter Symbol Typ (ns)·
C3-
C4-,-"
Input Loading
A 1
9 1
C 1
Output Driving
Pin Name
Factor (Iu)
X 36
The values for the worst case operating condition are gilllln by the maximum delay
multiplier.
Equivalent Circuit
"-j,-
A2-
A3-
A4-,-"
91-)
,..,.....
92- ::J \
93-
94-,-"
J ;:] J
'"\/
X
C1-i""'I
C2-
C3- ~
C4-,-"

I Page 9-9
3-91

!Up !dn
Path
AI _r"> 1.142 0.032 1.017 0.017 Ato X
A2- 1.142 0.032 0.865 0.017 BtoX
P2-
I-
1.142 0.032 1.162 0.017 CtoX
A4-l-" 1.142 0.032 1.228 0.017 DtoX
Bl _r">
83- ~ ~
B2-
84-1..-"
~X
'-
Cl-Ifr
C2- ~
C3-
C4-1...1
01 _r-.
02-
03-
I-
04-l-"
Input loading
Pin Name
Factor (Iu)
A 1
B 1
C 1
0 1
Output Driving
Pin Name
Factor (Iu)
X 36
multiplier.
Equivalent Circuit
Al-
L
A2-
A3-
A4-./
r
"-11 -<1+-
B2-
83-
84-.-/
x
e'-}J
C2-
C3-
-<I:;:;'
C4-./
01-
l
02-
03-
04-.-/
r
I Page9-10
3-92
T54 Power 4-2-3-2 AND 4-wide Multiplexer .10

!Up Idn
Path
1.089 0.032 1.036 0.017 Ato X
1.017 0.032 0.865 0.017 Bto X
A<-}
A2-
A3-
1.089
1.017
0.032
0.032
1.089
0.997
0.017
0.017
CtoX
Oto X
A4-,..I
Bl~ f::l
82
rp.-x
r-
"=iff
C2
C3
Dl=D-
D
02
Input loading
Pin Name
Factor (Iu)
A 1
8 1
C 1
0 1
Output Driving
X 36
multiplier.
Equivalent Circuit
Al-r"'I
A2- h
A3-
A4-l...I
81
B2
Cl
~1+-x
C2
C3
.J
01
02
C21-T54-EO I Sheet 1/1 I

I Page 9-11
3-93
FUJITSU CMOS GATE ARRAY UNIT CEll SPECIFICATION I • CG21K· Version
U24 Power 2-OR 4-wide Multiplexer 6

Cell Symbol Propagalion Delay Parameter
tup tdn
Palll
1.056 0.032 0.951 0.023 0.039 7 AtoX
0.759 0.032 0.924 0.023 0.039 7 Sto X
1.003 0.032 0.944 0.023 0.039 7 Cto X
0.733 0.032 0.898 0.023 0.039 7 DtoX
AI
A2
Bl~r..,
B2
Cl
C2
:::tYf "'"
p.--X
01
Input Loading
Pin Name
Factor (Iu)
A 1
B 1
C 1
0 1
Output Driving
Pin Name
Factor (Iu)
X 36
The values for lIIe worst case operating oondition are given by lIIe maximum delay
multiplier.
C21 U24-EO I Sheet 111 I

I Page9-12
3-94
U26 Power 2-OR 6.,...wide Multiplexer 9

tup teln
Path
1.056 0.032 1.234 0.023 0.039 7 AtoX
Al
A2
=bl-....:... 0.819
1.076
0.032
0.032
1.195
1.267
0.023
0.023
0.039
0.039
7
7
Bto X
CtoX
0.838 0.032 1.267 0.023 0.039 7 Dto X
"~
0.865 0.032 1.366 0.023 0.039 7 Eto X
~=t;f
1.109 0.032 1.366 0.023 0.039 7 FtoX
I""'.
p--X
~!fr
El
E2
i..-'
Fl=f}-
F2
Input Loading
Pin Name
Factor (Iu)
A 1
B 1
C 1
D 1
E 1
F 1
Output Driving
Pin Name
Factor (Iu)
X 36 • Minimum values for the typical operating condition.

multiplier.
C21 U26-EO I Sheet 1/1 I

I Page9-13
3-95
U28 Power 2-OR s.,..wide Multiplexer 11

!Up tdn
Palh
A1~ 1.116 0.032 1.683 0.028 0.045 7 AtoX
A2 ----b' 0.819 0.032 1.657 0.028 0.045 7 BtoX
0.799 0.032 1.485 0.028 0.045 7 Cto X
B1~ 1.096 0.032 1.151 0.028 0.045 7 DtoX
B2~ 1.116 0.032 1.657 .0.028 0.045 7 EtoX
C1=till
C2 "'"
0.819
0.n2 0.032
1.0760.032
0.032 1.630
1.340
1.393
0.028
0.028
0.028
0.045
0.045
0.045
7
7
7
FtoX
GtoX
H to X
~!~ :>-x
~!~
==f}fF,:
F1 ~
F2
G1~
G2~
H1~
H2~--
Input loading
Pin Name
Factor (Iu)
A
B
C
D
E
F
G
H
Output Driving
Pin Name
Factor (Iu)
x 36
The values lor Ihe worst case operating condition are given by the maximum delay
multiplier.
C21-U28-EO I Sheet 111 I

I Pagel9-14
3-96
FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION r" CG21K" Version
U32 Power 3-0R 2-wide Multiplexer 5

Cen Symbol Propagalion Delay Parameter
!Up tdn
Path
1.135 0.032 0.878 0.023 0.039 7 AtoX
1.116 0.032 0.865 0.023 0.039 7 Bto X
Al - - - f l
A2~
A3
X
Bl---fl
B2~
B3
Input LoadIng
Pin Name
Factor (Iu)
A 1
B 1
Output DrIvIng
Pin Name
Factor (Iu)
X 36
multiplier.
C21 U32 EO I Sheet 1/1 I

1 Page 9-15
3-97
Cell Name Function Number 01 DC

CenSymbol Propagation Delay Parameter
tup tdn
Path
1.208 0.032 1.208 0.023 0.050 7 AtoX
1.188 0.032 1.261 0.023 0.050 7 BtoX
1.221 0.032 1.333 0.023 0.045 7 Cto X
Al--Fl
A2
A3
--bi
81--Fl
82
83
--bi X
C1--Fl
C2
C3
---bJ Parameter Symbol Typ(ns) •
Input Loading
Pin Name
Factor (Iu)
A 1
0 1
C 1
Output Driving
Pin Name
Factor (Iu)
X 36
The values lor the worst case operating condition are given bY the maximum delay
multiplier.

I Page9-16
3-98

!Up tdn
Path
1.116 0.032 1.578 0.028 0.045 7 AtoX
1.129 0.032 1.584 0.028 0.045 7 Bto X
Al ----F'\ 1.017 0.032 1.287 0.028 0.045 7 CtoX
~-bJ
1.116 0.032 1.419 0.028 0.045 7 DtoX
Bl-f'\
:!-bJt
Cl-f'\fr:
C2 -bJ
}-x
~
C3
01-f'\ Parameter Symbol Typ (ns)'
02
03
-b'
Input loading
Pin Name
Factor (Iu)
A 1
B 1
C 1
0 1
Output Driving
Pin Name
Factor (Iu)
X 36
The values for the worst case operating condition am given by the maximum delay
multiplier.
C21-U34-EO I Sheet 1/1 I

I Page9-17
3-99
FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION I . CG21K' Version
U42 Power 4-OR 2.,....wide Multiplexer 6

tup_ !dn
Path
1.373 0.032 0.904 0.023 0.039 7 Ato X
1.340 0.032 0.865 0.023 0.039 7 BtoX
Al-~
A2--
A3-~
A4 - : ; ;
X
Bl-~
B2-r-
B3-'-
B4 - : ; ;
Input Loading
Pin Name
Factor (Iu)
A 1
B 1
Output Driving
Pin Name
Factor (Iu)
X 36
• Minimum values for the typical operating condi.tion.
multiplier.

I Page 9 18
3-100

!Up tdn
Path
1.360 0.032 1.129 0.028 0.039 7 AtoX
1.386 0.032 1.195 0.028 0.039 7 BtoX
Al-P> 1.426 0.032 1.261 0.028 0.039 7 CtoX
A 2 - 1-1-
A 3 - I-
A4-1::;;'
"-}D-
82-1-
83-1-
B4-b
x
Cl-~
C 2 - 1-1-
C 3 - I-
C4-"::;1
Input Loading
Pin Name
Factor (Iu)
A 1
B 1
C 1
Output Driving
Pin Name
Factor (Iu)
X 36
multiplier.

1 Page 9-19
3-101
FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION i . CG21K' Version

\up !dn
Path
"-j-
A2--
A3--
A4 - ' ; /
1.446
1.439
1.393
1.413
0.032
0.032
0.032
0.032
1.584
1.525
1.287
1.419
0.023
0.023
0.023
0.023
0.050
0.050
0.050
0.050
7
7
7
7
Ato X
BtoX
CtoX
DtoX
Bl-~
B2-nJ
83--
e'-rr
.......
B4 - ' ; /
p--x
C2-- :/ .
C3--
C4 - ' ; /
"-}
02--
03--
04 - ' ; /
Input loading
A 1
B 1
C 1
0 1
Output Driving
X 36
multiplier.

Page 9-20
3-102
Clock Buffer Family
Unit Cell Basic

3-105 K1B True Clock Buffer 2

3-106 K2B Power Clock Buffer 3
3-107 K3B Gated Clock (AND) Buffer 2
3-108 K4B Gated Clock (OR) Buffer 2
3-109 K5B Gated Clock (NAND) Buffer 3
3-110 KAB Block Clock (OR) Buffer 3
3-111 KBB Block Clock (OR x 10) Buffer 30
3-113 KDB Block Clock (OR x 10) Buffer 32
3-115 KEB Block Clock Buffer 23
3-117 VIL Inverting Clock Buffer 2
3-103
CG21 Series Unit CeD Library CMOS Channe/less Gate AtTays
3-104
FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION I .. CG21 K" Version
CeJlName Function NumberolBC
K1B True Clock Buffer 2

!up !dn
Palll
0.383 0.032 0.456 0.017 AtoX
A~X
Input Loading
Pin Name
Factor (Iu)
A 1
Output Driving
Pin Name
Factor (Iu)
X 36
• Minimum values lor lIIe typical operating condition.
The values lor lIIe worst case operating condition are given by lIIe maximum delay
multiplier.
Equivalent Circuit
At --[)o----<{>- X
C21 K1B EO I Sheet 1/1 I

I Page 10-1
3-105
K2B Power Clock Buffer 3

\up tdn
Path
0.561 0.014 0.634 0.017 AloX
A--{>--X
Parameter Symbol Typ(ns)'
Input Loading
Pin Name
Factor (Iu)
A 1
Output Driving
Pin Name
Factor (Iu)
X 55
• Minimum values for the typical operating condilion.
multiplier.
Equivalent Circuit
Al~X
C21-K2B EO I Sheet 1/1 I

I Page 10-2
3-106
K3B Gated Clock (AND) Buffer 2

!Up tdn
Path
0.528 0.032 0.528 0.017 AtoX
Al~X
A2
Input Loading
Pin Name
Factor (Iu)
A 1
Output Driving
Pin Name
Factor (Iu)
X 36
multiplier.
Equivalent Circuit
Al~X
A2
C21-K3B EO I Sheet 1/1 I

I Page 10-3
3-107
FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION I " CG21 K " Version
Cell Name Funcllon NumberolBC
K4B Gated Clock (OR) Buffer 2

!up tdn
Path
0.416 0.032 0.601 0.023 0.034 8 Ato X
Al
A2
:::::t>-- X
Parameter Symbol Typ (ns) "
Input Loading
Pin Name
Factor (Iu)
A 1
III Pin Name

Output Driving
Factor (Iu)
X 36
" Minimum values for the typical operating condition.
multiplier.
Equivalent Circuit
Al~X
A2
C21-K4B-EO J Sheet 1/1

I Page 11l-4
3-108
K58 Gated Clock (NAND) Buffer 3

!Up IeIn
Palll
0.601 0.032 0.786 0.017 AtoX
AI
A2
::::f)-x
Input loading
Pin Name
Factor (Iu)
A 1
Output Driving
Pin Name
Faclor(lu)
X 36
• Minimum values for lIle typical operating condition.
The values for lIle worst case operating condition are gi\l9n by !he maximum delay
multiplier.
Equivalent Circuit
AI
A2
::::t)---c[>--- X
C21 K5B-EO I Sheet 1/1 I

I Page 10-5
3-109
KAB Block Clock (OR) Buffer 3

CenSymbol PropagaUon Delay Parameter
\up teln
Pa!h
0.574 0.014 0.977 0.017 AtoX
Al=t>-X
A2
Parameter Symbol Typ Ins)·
Input loading
Pin Name
Factorllu)
A 1
Output Driving
Pin Name
Factor (Iu)
X 55
• Minimum values lor !he typical operating conQjlicn.
The values lor !he worst case operating condition are given by !he maximum delay
muldplier.
Equivalent Circuit
Al~X
A2
C21 KAB-EO I Sheet 1/1 I.

I Page 10-6
3-110
FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION I " CG21K· Version
KBB Block Clock Buffer (OR x 10) 30

!Up tdn
Path
to KCL to KCL KCl2 COR2
0.706 0.014 1.102 0.017 CKtoX
0.574 0.014 0.977 0.017 IHto X
CK-
IHO- f-- XO
IH1- f-- Xl
IH2- f-- X2
IH3- f-- X3
IH4- f-- X4
IH5- r-- X5
IH6- r-- X6
IH7- I--- X7
IH8- f - - X8
IH9- f - - X9
Input loading
Pin Name
Factor (Iu)
CK 10
IH 1
Output Driving
Pin Name
Factor (Iu)
X 55
multiplier.
C21 KBB EO I Sheet 112 I

I Page 10-7
3-111
FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION .. CG21K" Version
eel/Name
KBB Equivalent Circuit

r--------,
CK I
XO
IHO
Xl
IHI
X2
IH2
X3
IH3
X4
IH4
X5
IH5
X6
IH6
X7
IH7
X8
IH8
DI IH9
X9
C21-KBB-EO Sheet 2/2

Page 10-8
3-112
KDB Block Clock Buffer (OR x 10) 32

\up tdn
Path
1.254 0.019 1.848 0.011 CKtoX
0.594 0.019 1.221 0.011 (Hto X
CK-
IHO- I - - XO
IH1- I--Xl
IH2- I - - X2
IH3- I - - X3
IH4- I - - X4
IH5- I - - X5
IH6- I - - X6
IH7- I - - X7
IH8- I - - X8 Parameter Symbol Typ (ns)'
IH9- I - - X9
Input Loading
Pin Name
Factor (Iu)
CK 1
IH 1
Output Driving
Pin Name
Factor (Iu)
X 55
multiplier.
C21 KDB EO I Sheet 1/2 I

1 Page 10-9
3-113
Cell Name
KDB Equivalent Circuit
.... --------,
CK I
I XO
11-10 I
I----------i
I
I Xl
IHl I
I----------i
I
I X2
IH2 I
I----------i
I
X3
IH3 I
I----------i
I
I X4
IH4 I
I----------i
I
I X5
IH5 I
I----------i
I
I X6
IH6 I
I----------i
I
I X7
IH7 I
I----------i
I
I XB
IHB I
I----------i
I
X9
IH9 L ________ I
~
C21-KDB-EO Sheet 212

Page 10-10
3-114
Cell Name FuncUon NumberofBC
KEB Block Clock Buffer 23

!Up tdn
Path
0.825 0.019 0.911 0.011 0.023 18 CKtoX
CK- I-- XO
I-- Xt
I-- X2
I-- X3
I-- X4
I-- X5
I-- X6
I-- X7
I-- X8
I-- X9
Input Loading
Pin Name
Factor (Iu)
CK 6
Output Driving
Pin Name
Factor (Iu)
X 55
The values for the worst case operating condition ana given by the maximum delay
multiplier.
C21 KEB EO I Sheet 1/2 I

I Page 10-11
3-115
FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION "CG21K" Version
Cell Name
KEB Equivalent Circuit
CK n - - - < l XO
b - - - O Xl
b - - - O X2
b - - - O X3
n---<lX4
b---o X5
b---o X6
Y).---.(] X7
) 0 . - - - . 0 X8
b---o X9
C21-KEB-EO Sheet 212

Page 10-12
3-116
V1L Inverting Clock Buffer 2

\up tdn
Path
0.167 0.014 0.392 0.017 Ato X
A-1)o--X
Input loading
Pin Name
Factor (Iu)
A 4
Output Driving
Pin Name
Factor (Iu)
X 55
• Minimum values for the typicai operating condition.
multiplier.
C21 V1L EO I Sheet 1/1 I

I Page 10-13
3-117
CG21 Series Unit CeU Library CMOS .Channe/less Gate Arrays
3-118
CMOS Channe/less Gate A"ays CG21 Series Unit CeR Library
Scan Flip-flop (Positive Edge Type) Family
UnH Cell BaSic

3-121 SDH Scan 2-input D Flip-flop with Clear and Clock Inhibit 14
3-124 SDJ Scan 4-input D Flip-flop with Clear and Clock Inhibit 15
3-127 SDK Scan 6-input D Flip-flop with Clear and Clock Inhibit 16
3-130 SJH Scan J-K Flip-flop with Clear and Clock Inhibit 16
3-133 SDD Scan 2-input D Flip-flop with Clear, Preset, and
Clock Inhibit 16
3-137 SDA Scan 1-input D Flip-flop with Clock Inhibit 12
3-140 SDB Scan 1-input 4-bit D Flip-flop with Clock Inhibit 42
3-144 SHA Scan 1-input 8-bit D Flip-flop with Clock Inhibit 68
3-147 SHB Scan 1-input 8-bit D Flip-flop with Clock Inhibit
and QOutput 62
3-150 SHC Scan 1-input 8-bit D Flip-flop with Clock Inhibit
and XQ Output 62
3-153 SHJ Scan 8-bit D Flip-flop with Clock Inhibit and 3-to-1
Data Multiplexer 78
3-156
3-159
SHK
SFDM
Scan 8-bit D Flip-flop with Clock Inhibit and 3-to-1
Data Multiplexer
Scan 1-input D Flip-flop with Clock Inhibit
88
10
III
3-162 SFDO Scan 1-input D Flip-flop with Clear and Clock Inhibit 11
3-165 SFDP Scan 1-input D Flip-flop with Clear, Preset,.
and Clock Inhibit 12
3-169 SFDR Scan 4-input D Flip-flop with Clear and Clock Inhibit 36
3-173 SFDS Scan 4-input D Flip-flop with Clock Inhibit 31
3-177 SFJD Scan J-K Flip-flop with Clock Inhibit 14
3-119
CG21 Series Unit CeO Library CMOS Channe//ess Gate Arrays
3-120
SDH SCAN 2-input DFF with Clear & Clock-Inhibit 14

CeliSymboJ Propagation Delay Parameter
tup tdn
Path
to KCL to KCL KCL2 CoR2
1.967 0.032 1.575 0.017 0.039 7 CK,lHto Q
1.241 0.032 1.135 0.028 0.056 7 CK,lHto XQ
2.000 0.032 0.568 0.017 0.039 7 CLtoQ,XQ
-
Al-
-0
A2-
CK-
IH-
51 -
A-
B--<:
::>-- XO

Clock Pulse Width tew 3.2
CL Clock Pause Time tewH 2.5
Data SetllpTime tso 2.2


Pin Name
Factor (Iu) Clear Release Time tREM 1.8
Al,A2 1 Clear Hold Time tlNH 0.9
CK 1
IH 1
CL 3
I
51 1
A,B 2
Output Driving
Pin Name
Factor (Iu)
0 36
* Minimum values lor the typical operating condi!ion.
XO 36
multiplier.
Function Table
INPUT OUTPUT
MODE
CLK CL 0 A B 51 0 XO
LtoX H Oi L L X Oi oi
CLOCK
H H X L L X 00 XOo
H H X LIoHIoL H Si 00 XOo
5CAN
H H X L HtoLloH X 5i 5i
Note: CLK = CK+ IH

o =AlxA2
C21 SOH-EO I Sheet 1/3 1

I Page 11-1
3-121
Cell Nam.
SOH
Equivalent Circuit
ClK XBCK XClK
-L -L -L
Al
A2
b - -......--I 'X>--o Q
Cl
XClK ACK ClK

-L -L -L
I I
ClK XACK
XACK
-L
51
IACK IXBCK
XQ
~~~
Dt: : C~
XClK
AO
[>0
: '"XACK
BO
: XBC'
[>0 BCK
C21-SDH-EO Sheet 213

Page 11-2
3-122
Cell Name
SOH
i) CLOCK MODE
I __
CWH
I+--- lew
CLOCK ,1\
,
f4- Iso .. . . IHO"
DATA If
+-Ipd_
a,xa
(OUTPUT)
i i) CLEAR MODE
I+- IREM--
CK V
J
I-- I LW---'I
~
CLEAR
I-Ipd--
a,xa ,
(OUTPUT) J
~IINH-
V
CL
C21-SDH-EO Sheet 3/3

Page 11-3
3-123
CeIlNBme Function NumberolBC
SOJ SCAN 4-input DFF with Clear & clock-Inhibit 15

!Up tdn
Path
1.452 0.032 1.597 0.017 0.039 7 CK,lHtoQ
1.248 0.032 1.129 0.028 0.056 7 CK,lHto XQ
1.974 0.032 0.561 0.017 0.039 7 CLtoQ, XQ
Al-
-
A2-
1--0
Bl-
B2-
CK-
IH-
SI -
A-
::>-- xo
B--<
Clock Pause Time tewH 2.5
CL
Data Setup Time tso 2.7

Pin Name
Factor (Iu) Clear Release Time t REM 1.8
Al.A2 1 Clear Hold Time tlNH 0.9
Bl, B2 1
CK 1
IH 1
CL 3
SI 1
A,B 2
Output Driving
Pin Name
Factor (Iu)
.- • Minimum values lor the typical operating condition.
a 36
XO 36
multiplier.
Function Table
INPUT OUTPUT
MODE
CLK CL 0 A B SI a XO
Lto H H Oi L L X Oi Oi
CLOCK
H H X L l X 00 XOo
H H X LtoHtoL H Si 00 XOo
SCAN
H H X l HtoLtoH X Si Si
Note: ClK = CK + IH
o = (Al xA2)+(Bl x B2)
C21 SDJ EO I Sheet 1/3 I

I Page 11-4
3-124
Cell Name
SDJ
Equivalent Circuit
At
A2
Bt
B2
P--..-I )()--<> Q
Clo---i
XClK ACK
CLK
--L --L --L
I
ClK
I
XACK
XACK
--L
510---1
IACK IXBCK
XQ
III
~~~
~ : ,~
XClK
AO
[)o
: >OK
XACK
BO
[)o
: ,,..
BCK
C21-S0J-EO Sheet 2/3

Page 11-5
3-125
FUJITSU,CMOS GATE ARRAY UNIT CELL SPECIFICATION I • CG21K· Version
CalrName
SDJ
i) CLOCK MODE
_lew ICWH_
CLOCK , J
~ISD .. ... tHO ..
DATA
_tpd_
a,xa
(OUTPUT)
i i) CLEAR MODE
.... IREM ....
CK
J
_ILW_
CLEAR
, J
.... tpd ....
a,xa
(OUTPUT)
,
J
_I,NH_
'I
CL
C21-8DJ-EO I Sheet 3/3 I

I Page 11-6
3-126
FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION I .. CG21 K· Version
SDK SCAN 6-input OFF with Clear & Clock-Inhibit 16

tup tdn
Path
1.954 0.032 1.584 0.017 0.039 7 CK,lHto Q
1.228 0.032 1.142 0.028 0.056 7 CK,lHtoXQ
Al-
- 1.974 0.032 0.541 0.017 0.039 7 CLto Q, XQ
f---O
A2-
BI-
B2-
CI-
C2-
CK-
IH-
SI -
A-
B--<
t>-- XO
CL Data SetuD Time ho 2.9

Input Loading Clear Pulse Width ILW 2.5

PIn Name
Factor (Iu) Clear Release Time I REM 1.8
AI,A2 1 Clear Hold Time IINH 0.9
BI, B2 1
CI,C2 1
CK 1
IH 1
CL 3
SI 1
A,B 2
Outpul DrIving
Pin Name
Factor (Iu) • Minimum values for the typical operating condition.
0 36 The values for the worst case operating condition are given by the maximum delay
XO 36 multiplier.
Function Table
INPUT OUTPUT
MODE
ClK CL D A B SI 0 XO
llo H H Oi L l X Di Di
CLOCK
H H X l l X 00 XOo
H H X LtoHtol H Si 00 XOo
SCAN
H H X l HIoLtoH X Si Si
Note: ClK = CK + IH
D = (AI xA2)+ (BI x B2) + (el xC2)
C21 SDK EO I Sheet 1/3 I

I Page11-7
3-127
Cel/Name
SDK Equivalent Circuit
A1
A2
B1
B2
C1
C2
\:)--..-1 Ar--V Q
CLQ--......
XCLK ACK CLK

-L -L -L
I I
CLK XACK
XACK
-L
510---1
IACK IXBCK
L...-------I A.r---v XQ
~~ ~
D>-t ::~~ AO
[>0
: '"'
XACK
BO
:XBCX
[>0 BCK
C21-SDK-EO Sheet 2/3

Page 11-8
3-128
FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION .. CG21K· Version
Cell Name
SDK
i) CLOCK MODE
~ICW ICWH---I
CLOCK 'I
1\
j4-lsD oil 1+ I HO oil
DATA V
j
of-- Ipd -to
a,xa
(OUTPUT) 1\
i i) CLEAR MODE
1+-1 REM-iI
CK V
J
~ ILW----'
~ V
CLEAR
j4-- Ipd-l
a,xa
(OUTPUT)
!4-1,NH-
CL
C21-SDK-EO Sheet 3/3

Page 11-9
3-129
FUJITSU CMOS GATE ARRAY UNIT CEll SPECIFICATION I "CG21K" Version
SJH SCAN J-K FF with Clear & Clock-Inhibit 16

tup !dn
Path
2.238 0.032 1.782 0.017 0.039 7 CK,lHtoQ
1.248 0.032 1.142 0.028 0.056 7 CK,lHtoXQ
1.987 0.032 0.733 0.017 0.039 7 CltoQ,XQ
r---
J-
f--O
K--(
CK-
IH-
SI -
A-
B --(
P-- XO
Clock Pulse Width tcw 3.2
CL
Clock Pause Time tcWH 2.5
Data Setup Time (Jl tso 2.7

Data Setup Time (Kl tso 2.9
Data Hold Time (J Kl tHO 0.3
Input Loading
Pin Name
Factor (Iu) Clear Pulse Width tLW 2.5
J,K 1 Clear Release Time tREM 1.8
CK 1 Clear Hold Time tlNH 0.9
IH 1
CL 3
SI 1
A,B 2
Output Driving
Pin Name
Factor (Iu)
a 36
XO 36
multiplier.
Function Table
INPUT OUTPUT
MODE
CLK CL J K A B SI 0 XO
CLEAR X L X X X X X L H
LtoH H L L L L X L H
LtoH H H H L L X H L
CLOCK LtoH H L H L L X 00 XOo

LtoH H H L L L X XOo 00
H H X X L L X 00 XOo
H H X X LtoHtoL H Si 00 XOo
SCAN
H H X X L HtoLtoH X Si Si
Note: CLK = CK + IH
C21 SJH EO I Sheet 113 I

I Page 11-10
3-130
FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION " CG21 K " Version
Cell Name
SJH
Equivalent Circuit
D---+--i )(:>---0 a
K
TACK T
XBCK
xa
1m
~~ ~
Drt :
,~
XClK
AO
[>a
: ACK
XACK
BO
: ,.OK
[>a BCK
C21-SJH-EO Sheet 213

Page 11-11
3-131
Cell Name
SJH
i) CLOCK MODE
I+--tcw tCWH_
CLOCK ,1\ J
'I
:'tso ... .. tHO ....
DATA If
4-'"- tpd ___
a,xa If
(OUTPUT) 1\
i i) CLEAR MODE
... tREM .....
CK
I--- tLW_
CLEAR -
~tpd"'"
a,xa
(OUTPUT)
,
J
_tINH_
If
CL
J
C21-8JH EO I Sheet 3/3 I

I Page 11-12
3-132
SDD SCAN 2-input OFF with Clear, Preset & Clock-Inhibit 16

tup tdn
Path
1.954 0.032 1.703 0.017 0.039 7 CK,IHtoa
1.399 0.032 1.129 0.028 0.056 7 CK,lHtoXa
PR 2.376 0.032 0.541 0.017 0.039 7 CLtoa, xa
2.026 0.032 1.241 0.028 0.056 7 PRtoa,Xa
Al-
1--0
A2-
CK-
IH-
SI -
A-
~XO
B--<:

CL

Input loading Clear Pulse Width tLW 2.5

Pin Name
Factor (Iu) Clear Release Time t REM 1.8
Al,A2 1 Clear Hold Time tlNH 0.9
CK 1
IH 1 Preset Pulse Width tpw 4.0
CL 3 2.2
PR 3 Preset Release Time t REM
51 1 Preset Hold Time tlNH 0.6
A,B 2
Output Driving
Pin Name
Factor (Iu)
• Minimum values lor the typical operating conc!ition.
a 36
XO 36
multiplier.
Function Table
INPUT OUTPUT
MODE
CLK CL PR 0 A B 51 a XO
CLEAR X L H X X X X L H
PRESET X H L X X X X H L
LtoH H H Oi L L X Oi Oi
CLOCK H H H X L L X 00 XOo
H H H X ltoHtoL H Si 00 XOo
SCAN
H H H X l HtoLtoH X Si Si
CLiPR X l l X X X X Prohibited
Note: ClK = CK + IH
o =AlxA2
C21 SOD-EO I Sheet 1/4 I

I Page 11-13
3-133
Cell Name
SDD
Equivalent Circuit
A1 o--~
A2 o--~
CL o---,.~
I I
ClK XACK
XACK
-L
SI
L...-_ _ _---.
IACK IXBCK
L.-_ _ _ _+~ 'X>--o xa
PR
~~ ~
DY : cw
XClK
AO
t>o
:ACK
XACK
BO
:~
t>o BCK
C21-SDD-EO Sheet 214

Page 11-14
3-134
Cell Name
SDD
i) CLOCK MODE
_lew 'CWH-
CLOCK
~'so ... ""HO ...
DATA
-'pd-
Q,XQ
(OUTPUT)
i i) CLEAR MODE
"'-'REM---
CK If
f4-- 'LW-
CLEAR
~ If
1\ J
f4-- ,pd ....

Q,XQ
(OUTPUT)
-'INH-
CLEAR
J
C21-8DD-EO I Sheet 3/4 I

I Page 11-15
3-135
Cell Name
SDD
iii) PRESET MODE ~tREM __
CK 'I
PRESET
a,xa 'I
(OUTPUn
____~--J~~-------+--------------------------
I+-- tlNH_
PRESET
C21 SOD-EO I Sheet 4/4 I

TPage 11-16
3-136
SDA SCAN 1-input DFF with Clock-Inhibit 12

!Up tdn
Path
to KCl to KCl KCL2 CDR2
1.683 0.032 1.584 0.017 0.039 7 CK,lHloQ
1.234 0.032 1.149 0.028 0.056 7 CK,IHIO XQ
-
D-
~o
CK-
IH-
SI -
A-
:>- XQ
B ---<
-
Data SeluD Time tso 2.1

Input Loading
Pin Name
Factor (Iu)
D 1
CK 1
IH 1
SI 1
A,B 2
Output Driving
Pin Name
Factor (Iu)
a 36
xo 36 • Minimum values for the typical operating condition.
multiplier.
Function Table
INPUT OUTPUT
MODE
ClK D A B SI a XO
ltoH Di l l X Di Di
CLOCK
H X L L X 00 XOo
H X ltoHtoL H Si 00 XOo
SCAN
H X L HtoLtoH X Si Si
Note: CLK = CK + IH
C21 SDA EO I Sheet 1/3 I

I Page 11-17
3-137
FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION • CG21K" Version
Cell Nam.
SDA
Equivalent Circuit
ClK XBCK XClK
-L -L -L
0 Q
IXClK I
BCK
I
ClK
XClK ACK
ClK
-L -L -L
I I
ClK XACK
XACK
-L
51
IACK IXBCK
XQ
V2B
~~~
DY : e~
XClK
AO
[>a
:~
XACK
BO
: ,"eK
[>a BCK
C21-SDA-EO Sheet 213

Page 11-18
3-138
Cell Name
SDA
i) CLOCK MODE
- lew --.jI4-- ICWH _ _
CLOCK
J
DATA
,
__________~I~--~~--JJ~----+_------------~
_Ipd_
a,xa ,
(OUTPUn
________________~----~JI'-~---------------------
C21 SDA EO I Sheet313 I

I Page 11-19
3-139
SDB SCAN Hnput 4- bit OFF with Clock-'-Inhibit 42

tup tdn
Path
2.238 0.032 2.079 0.017 0.039 7 CK,IHtoQ
1.716 0.032 1.756 0.028 0.056 7 CK,IHtoXQ
01-
- ~01
02- p-- XOI
03- ~ 02
04- o--XQ2
r-Q3
CK-
o--XQ3
IH-
-04
51 -
o--X04
A-
B-<
- Parameter
Clock Pulse Width
Symbol
tcw
Typ (ns)'
4.0
Data SetuD Time tso 1.3

Input Loading
Pin Name
Factor (Iu)
0 1
CK 1
IH 1
SI 1
A,B 2
Output Driving
Pin Name
Factor (Iu)
a 36
XO 36 • Minimum values for the typical operating condition.
multiplier.
Function Table
INPUT OUTPUT
MODE
CLK On A B SI,On-l a XOn
L to H Oi L L X Oi OJ
CLOCK
H X L L X Ono XOno
H X LtoHtoL H 5j Ono XOno

SCAN
H X L HtoLtoH X Sj 51
Note: CLK = CK+ IH

n = 1-4
C21 SOB EO I Sheet 1/4 I

I Page 11-20
3-140
FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION I • CG2tK· Version
Cell Name
SDa
Equivalent Circuit
01 02 03 04
C)
X010l X0202 X0303 X0404
) C
o XO D o XO D o XO o XO D
51 0--------1 5 0-
00
FFI FFI FFI FFI
CKe- CK CLK 1----..1 ClK r - - - ClK r-- ClK - ClK

IHe- IH XClK XClK - XCLK - XClK . - - - XClK
ACK ACK r - - ACK r - - ACK ,......- ACK
A 0-- A XACK XACK - XACK - XACK r-- XACK
BCK 1-1++i-H BCK , BCK , BCK - BCK
B 0-< B XBCK XBCK XBCK XBCK XBCK
FFO
~~g~~ClK
~XClK
AO~~ACK BO~""-~=K
~XACK ~-----+BCK
C21 SOB-EO I Sheet 2/4 I

I Page 11-21
3-141
Cell Name
SDB Equivalent Circuit (FF1)

ClK XBCK XClK
-L -L -L
0 Q
IXClK I
BCK
I
ClK
XClK ACK
ClK
-L -L -L
I I
ClK XACK
XACK
-L
S
IACK IXBCK
XQ
V2B
C21-SDB-EO Sheel3/4
Page 11-22
3-142
Cell Name
SOB
i) CLOCK MODE
I--- Icw -_M--
,
ICWH - - -
CLOCK
~ ~
DATA W
_ _ _ _- - - I ~'___+_-JJ~'----+--------J
_Ipd_
a,xa w
(OUTPUT)
-----------~------'~~~-----------------
C21 SDS EO I Sheet 4/4 I

I Page 11-23
3-143
SHA SCAN 1-input 8-bit OFF with Clock-Inhibit 68

tup teln
Path
10 KCL to KCL KCl2 CDR2
r-- 2.495 0.060 2.495 0.039 0.045 4 CK,lHtoQ

01- -01 2.178 0.060 2.112 0.062 0.084 4 CK,lHto XQ
02- :>-- XOI
03- -02
04- :>--XQ2
05- - 03
06- :>--XQ3
07- -04
08- :>--XQ4
- 05
:>--XQ5
-as
CK- :>--X06
IH- -07
SI - :>-- X07
A- -as Clock Pause Time tcww 3.2
B--( :>--xas
'---
Data SetuD Time Iso 1.1
Input loading
Pin Name
Factor (Iu)
0 1
CK 1
IH 1
SI 1
A 1
B 1
Output Driving
Pin Name
Factor (Iu)
0 18
XO 18 • Minimum values for the typical operating ccndition.
The values for the worst case operating ccndition are given by the maximum delay
multiplier.
C21-SHA-EO I Sheet 113 I

I Page 11-24
3-144
Cell Name
SHA
Equivalent Circuit
01 02 08
CKo-~~
CKI
IHo-~-r
Do
XCKI
FFo FFo FFo
:~
CKI CKI CKI
XCKI XCKI ~ XCKI
AI AI AI
XAI XAI XAI
BI BI BI
::.
XBI XBI XBI
XSlo XSOo XSlo XSOo XSlo

XOo 00 XOo 00 XO 00
SI 01 02 08
' - - - - 0 XOI ' - - - - 0 X02 L..---O X08
XBI
III
X > - - - - - - o XOo
Do 0----;
XCKI AI
IXCKI I I .-------0 XSOo
--L --L BI CKI (V1N)
X>---O 00
XAI I I CKI
--L
CKI XAI --L
XSlo o----~
I AI
I XBI
C21-SHA-EO Sheet 2/3

Page 11-25
3-145
Cell Name
SHA
i) CLOCK MODE
~ tcw-~I4-- tCWH _ _
CLOCK '(
DATA
, ,
__________J/~__~__-J/I'-----~--------------J
I--- tpel -
Q,XQ
(OUTPUn ________________ ~----..-J
III
C21-SHA EO I Sheet 3/3 I

I Page 11-26
3-146
FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION I "CG21 K" Version
Cell Name Function Number 01 se
SHB SCAN Hnput 8-bit OFF with Clock-Inhibit & Q Output 62

Cell Symbol Propagation Delay Para,meter
!Up teln
Path
2.284 0.060 2.337 0.039 0.045 4 CK,lHto Q
-
01- -01
02- -02
03- -03
04- r--04
05- r--05
06- r--06
07- r--07
08- r-- Q8
CK-
IH-
SI -
A-
B--<
Clock Pause Time tcW!! 3.2
'---

Input loading
Pin Name
Factor (Iu)
0 1
CK 1
IH 1
SI 1
A 1
,
B 1
Output Driving
Pin Name
Factor (Iu)
0 18 • Minimum values for the typical operating condition.
multiplier.
C21 SHB-EO I Sheet 1/3 I

I Page 11-27
3-147
FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION • CG21 K· Version
Cell Name
SHB Equivalent Circuit

01 02 08
CK o----f~
CKI
IH o----f-r Do Do Do
XCKI
FFo FFo FFo
::' CKI
XCKI
AI
XAI
BI
XBI
CKI
XCKI
AI
XAI
BI
XBI
~
CKI
XCKI
AI
XAI
BI
XBI
SI
::" XSlo XSOo
00
01
XSlo XSOo
00
02
XSlo
00
08

CKI XBI XCKI
-L -L -L
Do
XCKI AI
IXCKI -L -L I BI I CKI XSOo
00
XAI I CKI I XAI CKI
-L -L
XSlo
I AI
I XBI
C21-SHB-EO Sheet 2/3

Page 11-28
3-148
eeliName
SHB
i) CLOCK MODE
I--- lew - - - . j j 4 - - ICWH - - -
CLOCK
DATA
__________J~__~~--JI~~----+_------------....J
_Ipd_
a,xa If
(OUTPUT)
________________~------J~~_+---------------------
C21 SHB EO I Sheet 3/3 I

I Page 11-29
3-149
Cell Nama Funcllon Number 01 BC
SHe SCAN 1-input 8-bit DFF with Clock-Inhibit & XQ Output 62

Call Symbol Propagation Delay Parameler
!Up Idn
Path
2.211 0.060 2.165 0.062 0.084 4 CK,lHto XQ
,---
OI- l:>--- XOI
02- I:>--- XQ2
03- I:>--- XQ3
04- I:>--- XQ4
05- P-- xas
06- I:>--- X06
07- P-- X07
08- :r-X08
CK-
IH-
51 - Para meIer Symbol Typ (ns)·
A-
Clock Pulse Width lew 4.2
B--<
Clock Pause Time ICWH 3.2
'---

Input loading
Pin Nama
Factor (Iu)
0 1
CK 1
IH 1
51 1
A 1
B 1
Output Driving
Pin Nama
Faclor(lu)
multiplier.
C21-5HC-EO I Sheet 1/3 I

1 Page 11-30
3-150
FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION • CG21K' Version
Cell Name
SHe
Equivalent Circuit
01 02 08
CK o----I~
CKI
IH 0----1-7 Do Do Do
XCKI
FFo FFo FFo
::' CKI
XCKI
AI
XAI
BI
XBI
CKI
XCKI
AI
XAI
BI
XBI
~
CKI
XCKI
AI
XAI
BI
XBI
51
::" X510 XSCb
XOo
X510 XSCb
XOo
X510
XOo
1..----0 XOI 1..----0 X02 1..---0 xaa
)0------<> xOo
Do 0---1
XCKI AI
IXCKI -L -L I
BI
I
CKI
....------0 X5Cb
XAI I I CKI
-L CKI XAI -L
X510 0-----1
I AI
I XBI
C21-SHC-EO Sheet 213

Page 11-31
3-151
FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION I ·CG21K· Version·
Cell Name
SHe
i) CLOCK MODE
j4- Icw-~_- ICWH_
CLOCK
J
DATA If
__...............-JI~.....+-.....,I~~.....~..................................I
_ _ Ipd--lo
a,xa If
(OUTPUT)
__..............................~...........-JI~'.....+-........................................_
C21-8HC-EO I Sheet 313 I

I Page 11-32
3-152
SHJ SCAN 8-bit OFF with Clock-Inhibit &2-to-1 Data Multiplexer 78

tup teln
Path
- to KCL to KCL KCL2 CDR2
Al- -01 2.548 0.060 2.554 0.039 0.056 4 CK,IHtoO
Bl- :>-- XOI 2.178 0.060 2.112 0.050 0.089 4 CK, IHto XO
A2- -02
82- :>-- X02
A3- - 03
83- :>--X03
A4- - 04
84- :>-- X04
A5- - 05
85- :>-- X05
A6- -06
86- :>-- X06
A7- -Q7
87- P - - X07
A8- f - - 08 Parameter Symbol Typ (ns)'
88- P--X08 Clock Pulse Width tew 4.2
AS--<
ss--< Data SetuD Time tso 1.8
CK-
IH-
SI -
A-
8 --<
'----
Input Loading
Pin Name
Factor (Iu)
,
An,8n 1
(n=I-8)
AS,8S 1
CK 1
IH 1
SI 1
A,8 1
Output Driving
Pin Name
Factor (Iu)
a 18
XO 18
multiplier.
C21 SHJ EO I Sheet 1/3 I

I Page 11-33
3-153
Cell Name
SHJ
Equivalent Circuit
A1 B1 A2 B2 AS B8
CK 0---1~
CKI
IH 0---1-r Ao Bo Ao Bo Ao Bo
XCKI FFo !&: FFo
CKI CKI CKI
:~
XCKl XCKI XCKI
AI AI AI
XAI XAI ~ XAI
BI BI BI
XBI XBI XBI
ASo ASo ASo
::~
BSo BSo BSo
XSlo XSOo XSIo XSOo XSIo XSQ,
00 XOo 00 XOo
AS~ASo 01 X01 02 X02 as xas
BS~BSo
SI 0----1 )(>-_ _ _ _ _ _---J
Ao )()------o xOo
AS o
Bo
BS o
...-----0 xSQ,
(V1N)
) 0 - - - 0 00
XAI I I CKI
-L CKI XAI -L
XSlo 0-----1
I AI
I XBI
C21-SHJ-EO Sheet 213

Page 11-34
3-154
CeUName
SHJ
i) CLOCK MODE
- lew -_14-- ICWH_
CLOCK
DATA
,
________-JJI~__~__J~____~-------------J
~Ipd-
a,xa
(OUTPUT)
______________ ~-----JI\~~------------------
C21 SHJ EO I Sheet 3/3 I

I Page 11-35
3-155
SHK SCAN 8-bit DFF with Clock-Inhibit &3-to-1 Data Multiplexer 88

\Up tdn
Path
r--- to KCL to KCL KCl2 CDR2
A1- 2.449 0.060 2.429 0.039 0.045 4 CK,lHto Q
r--01
B1- 2.158 0.060 2.112 0.062 0.084 4 CK,lHto XQ
C1- p - - X01
A2-
r - - 02
B2-
C2- p--XQ2
A3-
83-
I-- Q3
C3- p--XQ3
A4-
r - - 04
84-
C4- p - - X04
A5-
r - - as
B5-
C5- P--X05 Parameter Symbol Typ (ns)'
A6- Clock Pulse Width tew 4.2
86-
r-- as Clock Pause Time tCWH 3.2
C6- P--X06
A7- Data SetupTime tso 2.3
r - - 07
B7- Data Hold Time tHO 1.8
C7- p - - X07
AB-
r - - as
88-
cs- p--xaa
AS--<
BS--<
CS--<
CK-
IH-
SI-
A-
B--<
-
Input Loading
Pin Name
Factor (Iu)
An,Bn,Cn 1
(n=l -s)
AS,BS,CS 1
CK 1
IH 1
SI 1
A,B 1
Output Driving
a 18 The values for the worst case operating condition are given by the maximum delay
XO 18
multiplier.
C21 SHK EO I Sheet 1/3 I

I Page 11-36
3-156
FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
Cell Nama
SHK Equivalent Circuit

Al Bl Cl A2 B2 C2 A8 B8 C8
CK 0--;",,",-
)C>----+CKI
IH o----+-:r Ao Bo Co Ao Bo Co Ao Bo Co
)Q--+ XCKI
FFo FFo FFo
CKI CKI CKI

XCKI XCKI XCKI
AI AI AI
XAI XAI
~ XAI
BI BI BI
XBI XBI XBI
AS o AS o AS o
BS o BS o BS o
CS o CS o CS o
XSlo XSOo XSIo XSOo XSlo XSOo
00 XOo
01 XOI 02 X02 08 XOB
Slo---~ ~>--------~
Ao
AS o )()------o XOo
Bo
BS o
Co
cSo ,-----0 XSOo
(V1N)
) 0 - - - 0 00
XAI I I CKI
-'-
CKI XAI
-'-
XSlo 0-----;
I AI
I XBI
C21-SHK-EO Sheet 2J3

Page 11-37
3-157
Cell Name I
SHK
i) CLOCK MODE
f4-- Icw-~_- ICWH _ _
CLOCK ,
DATA
,
_Ipd_
a.xa
(OUTPUn
,
----------------~------'I~~-+---------------------
C21 SHK-EO I Sheet 313 I

I Page 11-38
3-158
eeliName Function Number of BC
SFDM SCAN 1-input OFF with Clock-Inhibit 10

\up Idn
Path
1.221 0.060 1.254 0.045 0.078 4 CKtoQ
1.551 0.060 1.525 0.039 0.045 4 CKtoXQ
.-----
D-
-0
CK-
IH-
=>-- xo
SI- -so
A-
B --<
'----
Data Setup Time Iso 1.0

Input loading
D 2
CK 1
IH 1
SI 2
A,B 2
Output Driving
0 18
so 18 • Minimum values for the typical operating condition.
multiplier.
C21 SFDM EO I Sheet 1/3 I

I Page 11-39
3-159
Cell Name
SFDM
Equivalent Circuit
ClK XBCK XClK
--L --L --L

00---; XQ
I II ClK
XClK BCK ClK --L
XClK ACK
--L --L
II
ClK XACK
XACK
--L
Slo---; I
XBCK
Q
I
ACK
so
CK
IH
~
[)~[>o------: 0"'
' - - - - - - - - XClK
BOI--<l4--_-_: ::'
C21-SFDM-EO Sheet 2/3

Page 11-40
3-160
Cell Name
SFDM
i) CLOCK MODE
CLOCK ----~
-tcw---+----tCWH--
I
~ ,
~
DATA
, ,
__________JI,'-__-+__-J~____ +_--------------J
~tpd-
a,xa
(OUTPUn ________________ ~------J
C21 SFDM EO I Sheet 3/3 I

I Page 11-41
3-161
SFDO SCAN 1-input OFF with Clear and Clock Inhibit 11

\Up tdn
Path
10 KCL to KCL KC12 COR2
1.413 0.064 1.347 0.050 0.084 4 CKtoQ
1.564 0.060 1.729 0.039 0.045 4 CKtoXQ
1.657 0.060 1.439 0.050 0.084 4 CLtoQ,XQ
0-
-
1--0
CK-
IH-
p-- xo
SI- I-SO
A-
B --C
CL Parameler Symbol Typ (ns)·


Inpul loading Clear Pulse Width ILW 2.5

Pin Name Factor (Iu) Clear Release Time I REM 1.2
0 2 Clear Hold Time IINH 2.9
CK.IH 1
SI 2
A.B 2
CL 2
Output Driving
0 18
SO 18 The values lor the worst case operating condition are given by the maximum delay
multiplier.
C21-8FDO-EO I Sheet 1/3 I

I Page 11-42
3-162
Cell Name
SFDO
Equivalent Circuit
ClK XBCK XClK

-L -L -L
00"----1
XQ
510"----1 T
XBCK
Q
T
ACK
10
~
[)~~-:C~
CK
IH
L....._ _ _ _ _
- XClK
AO---+-----c;-_: :,
BO-.. c;~---~~~~~_:~
. :
C21-8FOo-EO Sheet 213

Page 11-43
3-163
Ce"Name
SFDO
i) CLOCK MODE
CLOCK
I---tcw
~
tcwH-
,
~
-tso.... i--tHO-
DATA
,
J
,
J
-tpd-
a,xa
(OUTPUT)
i i) CLEAR MODE
-tREr--
IDI CK
CLEAR - i---tLW-
~ J
i--tpd-
a,xa
(OUTPUT)
,
J
i--tINH-
CL
021-SFDO-EO I Sheet 3/3 I

I Page 11-44
3-164
SFDP SCAN 1-input OFF with Clear, Preset, and Clock Inhibit 12
tup tdn
Path
1.426 0.064 1.340 0.050 0.084 4 CKtoQ
1.888 0.060 1.729 0.039 0.045 4 CKtoXQ
PR
1.921 0.060 1.419 0.050 0.084 4 CltoQ,XQ
2.403 0.064 0.548 0.039 0.045 4 PRto Q,XQ
0-
1--0
CK-
IH-
p--XO
SI- I-- SO
A-
B-<

CL
Clock Pulse Widlh tew 2.5
Data Setup Time t SD 1.6


Pin Name Factor (Iu) Clear Release Time t REM 1.2
0 2 Clear Hold Time t INH 2.9
CK,IH 1
SI 2 Preset Pulse Width tpw 3.6
A,B 2 0.6
Preset Release Time t REM
CL, PR
Pin Name
2
Output Driving
Factor (Iu)
Preset H old Time t INH 3.6
II]
0 18
SO 18 The values for the worst case operating condition are given by the maximum delay
multiplier.
C21 SFDP EO I Sheet 1/4 I

I Page 11-45
3-165
Cell Name
SFDP
Equivalent Circuit
Clo-------------~~--~--------------------------~
ClK XBCK XCLK

-.L -.L -.L
00----1
xa
II
ClK XACK
PR
XACK
-.L
51
I I
XBCK
ACK a
CK ~
IH [)~~~:cU<
1...-_ _ _ _ _ _ _ _ _
- XClK
A
0- 4--_--::K
BO--<l4~---~~~~~ .:·. ::
C21-SFDP-EO Sheet 214
Page 11--46
3-166
Cell Name
SFDP
i) CLOCK MODE
-lew
, ,
ICWH-
CLOCK 'I
I\.
~ISD-- ~IHD-
DATA
,
JI\. J
i--Ipd-
Q,XQ
(OUTPUn
i i) CLEAR MODE
i--IREM-
CK
-ILW-
CLEAR ~
-tpd-
Q,XQ
(OUTPUn J
-tINH-
'I
CLEAR
C21-SFDP-EO Sheet 3/4

Page 11-47
3-167
Cell Name
SFDP
iii) PRESET MODE
CK f
i--tpw-
P~ESET
---
a,xa
(OUTPUn
P~ESET
J
IDI
C21 SFDP EO I Sheet 4/4 I

I Page 11-48
3-168
SFDR SCAN 4-input DFF with Clear and Clock Inhibit 36

tup tdn
Path
1.967 0.064 1.980 0.050 0.084 4 CKtoQ
- - 2.026 0.050 0.089 4 CLtoQ
-
DA- - OA
DB- - OB
DC - - OC
DD- - 00
CK-
IH-
SI- -SO
A-
B --<
CL Clock Pause Time ICWH 3.2

Data Hold Time IHO 1.5
Inpul Loading Clear Pulse Width ILW 2.5

Pin Name Faclor(lu) Clear Release Time I REM 1.7
0 2 Clear Hold Time IINH 3.4
CK,IH 1
SI 2
A,B 1
CL 1
Output Driving
Pin Name Faclor(lu)
0 18
SO 18 • Minimum values for Ihe typical operating condition.
The values for the worst case operating ~ndiUon are given by the maximum delay
multiplier.
C21 SFDR EO I Sheet 1/4 I

I Page 11-49
3-169
FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION I • CG21K' Version
Cell Name
SFDR Equivalent Circuit

OA DB DC 00
QA aB OC 00
ODD 0
Slo---------I S
:1-'1' ::r ::r a I--
SOl--
CKC>-- CK ClK I---t-\ ClK -CLK r--- ClK . - - - ClK

IH C>-- IH XClK XCLK r - XCLK - XClK r - XClK
ACK ACK - ACK r-- ACK -ACK
AC>--A XACK XACK r-- XACK - XACK r-- XACK (
BCK BCK ,.... BCK r- BCK - BCK SO
BO-<B XBCK XB~K XBCcK XB~K XBCc~
ClC>-- CNTO
Cl.
Equivalent Circuit (CNTO)
~~~-:'~
~ -XClK'
AO_--I~
_ - - - \ )()__- I )()--_ XBCK
Bo-
::
~----BCK
C21-SFDR EO I Sheet 214 I

I Page 11-50
3-170
FUJITSU CMOS GATE ARRAY UNIT CEll SPECIFICATION H CG21K· Version
Cell Name
SFDR Equivalent Circuit (FFO)
ClK XBCK XCLK

-L -L -L
0
ClK
BCK -L
Cl.
XACK
II
ClK XACK
-L
S
I
ACK I
XBCK
a
ClK XBCK XClK

-L -L -L
0
CLK
XClK BCK ClK -L
Cl.
XACK II
ClK XACK
-L
S
I
ACK I
XBCK
a
so
C21-SFDR-EO Sheet 3/4

Page 11-51
3-171
Cell Name
SFDR
i) CLOCK MODE
,
I---Icw ICWH-
CLOCK 'I
- I s o - i--IHO-
DATA
i--Ipd-
a,xa
(OUTPUT)
i i) CLEAR MODE
:e-IRE~
CK
~ILW-
CLEAR ~
-Ipd-
a,xa
(OUTPUT) J
-IINH-
CL
C21-SFDR-EO Sheet 4/4

Page 11-52
3-172
Cell Name Function Number or BC
SFDS SCAN 4-input DFF with Clock Inhibit 31

tup !dn
Path
1.624 0.060 1.597 0.045 0.073 4 CKtoQA-QC
1.736 0.060 1.716 0.045 0.073 4 CKtoQD
DA-
- ~ aA
DB- ~ aB
DC- f-- ac
DD- f-- aD
CK-
IH-
SI- ' - - SO
A-
B --<
- Parameter Symbol Typ (ns)·

Input loading
D 2
CK,IH 1
SI 2
A,B 1
Output Driving
Pin Name Faclor(lu)
a 18
so 18 • Minimum values lor the typical operating condition.
The values ror the worst case operating condiUon are given by the maximum delay
multiplier.
C21 SFDS EO I Sheet 1/4 I

1 Page 11-53
3-173
Cell Name
SFDS Equivalent Circuit
DA OA DB OB DC OC DO 00
Sl~------------~
CK so
IH
A
B
o
S a
00
ClK
XCLK
ACK
XACK
BCK
XBCK
CLK XBCK XClK a
--L --L --L
0 00
IIJI XClK BCK CLK --L

ClK
XACK XClK ACK

--L --L --L BCK
S
T --L
XClK
T T T
ACK ClK XACK
T
XBCK
C
IH K B C l K
XCLK
CNTO ACK
A XACK
:
B BCK ACK
XBCK Equivalent Circuit
(CNTO)
XACK
C21-SF05-EO Sheet 214

B~L----_ : XBCK
BCK
Page 11-54
3-174
FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION "CG2tK" Version
Cell Name
SFDS
o
S Q
ClK
co
FF2
XCLK
ACK
XACK
BCK
XBCK
so
ClK XBCK XCLK
a
--L --L --L
0
ClK
XClK BCK ClK --L
XACK XClK ACK
--L --L --L
s T
XCLK BCK
T T T --L
ACK ClK XACK
T
XBCK
C21-SFDS-EO Sheet 3/4

Page 11-55
3-175
FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION. I . CG21 K • Version
Cell Name
SFDS
i) CLOCK MODE
i---Icw--+--ICWH-
CLOCK
J
'I ,
I\.
-tso-f-tHD-
DATA
a,xa
(OUTPUn
III
C21 SFD5-EO I Sheet 4/4 I

I Page 11-56
3-176
SFJD SCAN J-K FF with Clock Inhibit 14

!Up tdn
Path
1.710 0.064 1.584 0.056 0.089 4 CKtoQ
1.828 0.060 2.000 0.039 0.045 4 CKto XQ
1.479 0.060 1.307 0.039 0.078 4 CLtoQ,XQ
r---
J-
1--0
K-
CK-
p-- xo
IH-
51- I-- SO
A-
B --<

CL 2.5
Clock Pulse Width tew
Data SetuD Time (Jl tso 2.2

Data Hold Time (Jl tHO 0.4
Input Loading Data Setup Time .(K) tso 1.9

Pin Name Factor (Iu) Data Hold Time (Kl tHO 0.1
J, K 1
CK,IH 1 Clear Pulse Width tLW 2.5
51 2 Clear Release Time t REM 1.2
A,B 2 2.6
CL 2 Clear Hold Time tlNH
Output Driving
0 18
multiplier.
C21-SFJD EO I Sheet 1/3 I

I Page 11 57
3-177
Cell Name
SFJD
Equivalent Circuit
)0---0 XQ
Ko-----'
XClK BCK ClK

Clo---------------~--~--------+_--------_+----------_,
XClK ACK ClK
--.L --.L --.L
510-----1
T T
XBCK
ACK
t--------; )0---0 Q
L..-_ _ _ _ -1 )()--o so
CK~
IH [)o
: ClK
XCLK
A 0
L{)O : ACK
XACK
B 0
L{)O : XBCK
BCK
Sheet 213
Page 11-58
3-178
Cell Name
SFJD
i) CLOCK MODE
,
:----Icw ICWH-
CLOCK If
1\
-180- i.-IHO-
DATA ,
J
,
-Ipd-
a,xa
(OUTPUn
i i) CLEAR MODE
I-IRE~
If
CK
i---tLw-
~
CLEAR
I--Ipd-
a,xa
(OUTPUn
-IINH-
CL
C21-SFJD-EO Sheet 3/3

Page 11-59
3-179
CG21 Series Unit CeO Ubrary CMOS ChanneOess Gate A"ays
DI
3-180
CMOS Channelless Gate Arrays CG21 Series Unit Cell LibraI}'
Non Scan Flip-Flop Family
Unit Cell Basic

3-183 FOM Non-Scan 0 FF 6

3-185 FON Non-Scan 0 FF with Set 7
3-187 FOO Non-Scan 0 FF with Reset 7
3-189 FOP Non-Scan 0 FF with Set and Reset 8
3-192 FOO Non-Scan 4-bit 0 FF 21
3-194 FDR Non-Scan 4-bit 0 FF with Clear 26
3-197 FOS Non-Scan 4-bit 0 FF 20
3-199 F02 Non-Scan Power 0 FF 7
3-201 F03 Non-Scan Power 0 FF with Preset 8
3-203 F04 Non-Scan Power 0 FF with Clear and Preset 9
3-205 F05 Non-Scan Power 0 FF with Clear 8
3-207 FJO Non-Scan Positive Edge Clocked
Power J-K FF with Clear 12
III
3-181
CG21 Series Unit Cell Library CMOS Channel/ess Gate Arrays
3-182
FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION t"CG21K"Version
FDM Non-SCAN DFF 6

IUp Idn
Palh
0.924 0.060 0.951 0.039 CKtoQ
1.142 0.060 1.248 0.039 CKto XQ
'=[J=Q
CK
XQ
Para meier Symbol Typ (ns)'

Clock Pause Time leWH 2.5
Data SetuD Time Iso 1.3

Inpul Loading
Pin Name
Faclor(lu)
D 2
CK 1
Pin Name
Output Driving
Faclor(lu)
III
Q 18
XQ 18
The values for Ihe worsl case operating condition are given by the maximum delay
multiplier.
Function Table
Inputs Outputs
D CK Q XQ
H t H L
L t L H
C21-FDM-EO I Sheet 112 I

I Page 12-1
3-183
Cell Name
FDM
Equivalent Circuit
ClK XClK
a
-L -L
0 xa
T
XClK
TClK
XClK CLK
-L -L
TClK TXCLK
CK o-----I>otI)o-- ClK
. L---. XClK
-ICW ICWH ---10
CK
~
f4-- Iso ---10 i4-1HD""
o ~
f4-- Ipd'"
Q,XQ
J
C21-FDM-EO Sheet 2/2

Page 12-2
3-184
FDN Non-SCAN DFF with SET 7

tup teln
Path
0.951 0.060 0.924 0.039 0.056 4 CKtoa
1.300 0.060 1.281 0.039 CKto xa
1.182 0.060 0.568 0.039 Stoa, xa
S
0- 1--0
CK-
P-- xo
'---


Input Loading Set Pulse Width tsw 2.5

Pin Name
Factor (Iu) Set Release Time (S) t REM 0.3
0 2 Set Hold Time tlNH 2.3
S 2
CK 1
,
Output Driving
Pin Name
Factor (Iu)
0 18
xo 18 The values for the worst case operating condition are given by the maximum delay
multiplier.
Function Table
Inputs Outputs
S 0 CK 0 xo
L X X H L
H H i H L
H L i L H
C21 FDN EO I Sheet 1/2 I

I Page 12-3
3-185
Cell Name
FDN Equivalent Circuit

so-_---------.
CKO XCKO ...---+-------4 )0--0 a
-L -L
P---1t-'-I )(>--0 xa
00---1
-.
XCKO
XCKO
-L
-.
CKO
-.
XCKO
CK~CKO
• ~XCKO
D{!fini\.i9f1S 2f Param~~rs
1) tCw, tGWH, t~u, tHO and tI'6 (CK Q,XQ)
CK
,-tc;w
If
tCWH-
J ~
o
~tso
If
~
,
tHO'"
J
.... tpd-ll
Q.XQ
~
2) t8W, tREM, tlNH, and 1pd (8 Q, XQ)

-~--tCWH
CK
~
s
-+-----~
Q
---+-----~ .....
~--+-'
~----+-
.,.._.~.,...._•.,...""'.",...-,'-_+_______ <) • _• __
I--::,."...,..XQ-=="..,.,..,.=".....
C21-FDN-EO Sheet 212
Page 12-4
3-186
FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION I .. CG21K· Version
FDO Non-SCAN OFF with RESET 7

!Up tdn
Path
to KCl to KCl KC12 CDR2
1.023 0.060 0.944 0.045 CKtoQ
1.142 0.060 1.366 0.039 CKtoXQ
1.056 0.060 0.865 0.045 RtoQ, XQ
r---
0- -Q
CK-
>-- XQ
R Parameter Symbol Typ (ns)'

Data SetllpTime tso 1.3

Input loading Reset Pulse Width tRW 2.5

Pin Name
Factor (Iu) Reset Release Time (RI tREM 0.6
0 2 Reset Hold Time tlNH 2.0
R 2
CK 1
Output Driving
Pin Name
Factor (Iu)
Q 18
XQ 18 The values lor the worst case operating condition are givan by the maximum delay
multiplier.
Function Table
Inputs Outputs
R 0 CK Q XQ
l X X L H
H H i H l
H l i l H
C21-FDO-EO I Sheet 1/2 I

I Page 12 5
3-187
FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION " CG21K" Version
Cell Name
FDO Equivalent Circuit

CKO XCKO
~------------~ ~--~ a
..l.... ..l....
00---1 H--------1 X)--......-I ~-o xa
CKO
..l....
ICKO IXCKO
CK~CKO
r ~XCKO R
1) tCW, tCWH, tSD, tHD and tpeI (CK Q, XQ)
-lew ICWH-
CK
If
~
o
- I s o - !+IHO"
,
J
f4-lpd-'
Q,XQ
2) tRW, tREM, tlNH, and tpd (R Q, XQ)

--tofol-- tCWH
CK
~
Ir+-----~
R
~ -""""I-\.
Q
-Il..-.-+-_ _ _ _ ~ •••••
-1,..--+----- ~ - _...
XQ
~-...of-'
C21-FDO-EO Sheet 2/2
Page 12-6
3-188
FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION I "CG21 K" Version
FDP Non-SCAN OFF with Set and Reset 8

!Up tdn
Path
1.036 0.060 0.931 0.045 CKtoQ
1.294 0.060 1.320 0.039 CKtoXQ
1.182 0.060 0.838 0.045 Rto Q, XQ
1.340 0.060 0.535 0.039 Sto Q, XQ
S
D- -0
CK-
:>-- xo
R Parameter Symbol Typ (ns)·


Input loading Set Pulse Width tsw 2.5

Pin Name
Factor (Iu) Set Release Time (S) tREM 0.3
D 2 Set Hold Time tlNH 2.3
S 2
R 2 Reset Pulse Width tRW 2.5
CK 1 0.6
Reset Release Time (Rl tREM
Reset Hold Time tlNH 2.0
Output Driving
Pin Name
Factor (Iu)
0 18
multiplier.
Function Table
Inpuls Outputs
S R D CK 0 XO
H L X X L H
L H X X H L
L L X X Inhibited
H H H r H L
H H L r L H
C21-FDP EO I Sheet 1/3 I

I Page 12-7
3-189
Cell Name
FOP
Equivalent Circuit
SO-~~------------~
CKO
r----+--------~ ~--~ a
-L
00----;
CKO
-L
T
XCKO
CK o-----J>orI>o-- CKO
r ~XCKO
C21-FDP-EO Sheet 2/3

Page 12-8
3-190
Cell Name
FDP Definitions of Parameters

1) tCW, tCWH, t8D, tHD and tpd (CK-+Q, XQ)
CK
,I4-- t cw tcWH-
'--
D
,
J
I-- tso- 4-tHO'"
_tpd_
Q,XQ
2) tRW, tREM, tINH, and tpd (R -+Q, XQ)

-~I+--tCWH
CK
~---+-
Q
---+-----~ -----
XQ
----+-----~ -----
~---+-'
3) t8W, tREM, tINH, and tpd (8 -+ Q, XQ)
~tcw tCWH-
-
CK
'--
-tsw ----=: REM
_tpd_
s
Q
------ ------ ~----
~--+-'
~---+
XQ
------ -----_. ~-----
C21-FDP-EO Sheet 3/3

Page 12-9
3-191
FDQ Non-SCAN 4-bit DFF 21

!Up tdn
Path
1.782 0.060 1.446 0.039 CKtoQ
rDrDrT
r---
OA
CK--<:
r---
OB
- OC
-OD

Clock Pause Time tewL 2.5
Data Setup Time t so 0.7

Input Loading
Pin Name
Factor (Iu)
D 1
CK 1
Output Driving
Pin Name
Factor (Iu)
0 18
multiplier.
Function Table
Input Output
CK D 0
J. H H
J. L L
C21 FDa-EO 1 Sheet 1/2 I

I Page 12-10
3-192
Cell Name
FDQ
Equivalent Circuit
XCKO CKO
-L -L
OA 0 - - - - - - - - - : ; )O---i--o OA
CK~CKO
. L--. . XCKO
IXCKO ICKO
OBO-------~ +-<> OB
----------------------------------------~· ·
DC 0 - - - - - - - ; - +-oac
------------------.---------------------.· I
000-------;- +-000
I
--------------------------------------_ ..
~Icw ICWL-
CK
r-
o
,
J
_ 1 50 - !e-IHo"
a
,
I-- IpeI ....
I
C21-FDQ-EO Sheet 2/2

Page 12-11
3-193
FUJITSU CMOS GATE ARRAY UNIT CEll SPECIFICATION I .. CG21K" Version
Cell Nama Function NumberofBC
FDR Non-SCAN 4-bit OFF with CLEAR 26

!up tdn
Path
1.393 0.060 1.914 0.039 CKtoQ
- - 1.155 0.039 CltoQ
TorlT
f-- aA
f-- aB
CK-
f-- ac
f-- aD
r Parameter
Clock Pulse Width
Clock Pause Time
Symbol
tew
tCWH
Typ (ns)·
2.5
2.5


Pin Nama Factor (Iu) Clear Release Time tRE!! 0.9
0 1 Clear Hold Time tlNH 2.7
CK 1
CL 1
IDI Pin Nama

Output Driving
Factor (Iu)
a 18
multiplier.
Function Table
Inpuls Output
CK 0 CL a
x x L L
i L H L
i H H H
C21 FOR EO I Sheet 113 I

I Page 12-12
3-194
Cell Name
FDR
Equivalent Circuit
,-----------_ .... _-----------------------
CLO
DAo-------------~ )()---...!--o aA
CK~CKO
• LXCKO
CL ~ ~ CLO
I
__________ ~ :~~
___ ______ ~ __________ •
I
DBO +-0 aB
I
t----------------.-----------------------.
I I
DC O-------------l- +-0 ac
I
t----------------------------------------.
I ,
DO O-------------l-' +-0
, aD
.. _------------------------------------_ ..
C21-FDR-EO Sheet 213

Page 12-13
3-195
FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION ", CG21K" Version
Cell Nam.
FDR Definitions of Parameters

1) tCW, tCWH, tSD, tHD and tpd (CK-OA - OD)
lew -_14--
CK
Iso ......f - - -
Ipd
OA-OO
2) tLW, tREM, tlNH, and tpd (CL_ OA - OD)
CK
~
I,....j-----~
CL
~--'-
OA-OO
'---+------~ - - - --
C21-FDR-EO Sheet 3/3

Page 12-14
3-196
FDS Non-SCAN 4-bit DFF 20

\up !dn
Path
to KCL to KCL KCl2 COR2
1.604 0.060 1.294 0.039 CKtoQ
rorrT
I-- aA
I-- as
CK-
I-- ac
I-- aD


Input Loading
Pin Name
Factor (Iu)
0 2
CK 1
Output Driving
Pin Name
Factor (Iu)
a 18
multiplier.
Function Table
Inputs Outputs
CK 0 a
l' L L
l' H H
C21 FDS EO I Sheet 1/2 I

I Page 12-15
3-197
Cell Name
FDS
Equivalent Circuit
ClK XCLK
)O----+-oOA
--L --L
DAo-------~~-~
CK~ClK
• LXCLK
·•• I I
0-------,....···---------------------------------------
ClK XCLK
DB -.....---0 aB
DC 0-------,....- ------------ --------------- ----------- ~ QC
________________________________________ 4
···
DO 0-------,.... .....---0 aD
·
CK
,-ICW
J
ICWH-
j\...-
- I s o - 4-IHO'"
J~
I-Ipct'"
C21-FD5-EO Sheet 2/2

Page 12-16
3-198
FD2 Non-SCAN Power OFF 7

tup Illn
Path
0.871 0.032 0.911 0.023 0.045 7 CKtoQ
1.347 0.032 1.234 0.017 0.034 7 CKtoXQ
DUQ
CK
XQ


Input Loading
Pin Name
Factor (Iu)
D 2
CK 1
Output Driving
Pin Name
Factor (Iu)
Q 36
XQ 36 • Minimum values for the typical operating condition.
multiplier.
Function Table
Inputs Outputs
CK D Q XQ
J. H H L
.j. L L H
C21 FD2-EO 1 Sheet 1/2 I'

I Page 12-17
3-199
Cell Name
FD2 Equivalent Circuit

CKO XCKO
Q
-L -L
0 XQ
T
XCKO
TCKO
XCKO CKO
-L -L
TCKO T
XCKO
CK~XCKO
. L---. CKO
!----tcw tCWL-
CK
r-
J
D
,
J
-tso tHO--
If
+- tpd-"
Q,XQ
C21-FD2-EO Sheet 2/2

Page 12-18
3-200
FD3 Non-SCAN Power DFF with Preset 8

tup teln
Path
0.904 0.023 0.918 0.017 0.045 7 CKtoQ
1.479 0.023 1.320 0.017 0.034 7 CKto XQ
1.261 0.023 0.482 0.017 0.034 7 PRto Q, XQ
PR
D- ~Q
CK~
t:>-- XQ
-

Input Loading Preset Pulse Width tpw 2.5

Pin Name
Factor (Iu) Preset Release Time t REM 0.3
0 2 Preset Hold Time tlNH 2.3
CK 1
PR 2
Output Driving
Pin Name
Factor (Iu)
Q 36
XQ 36 • Minimum values for the typical operating condition.
multiplier.
Function Table
Inpuls Outputs
PR CK 0 Q XQ
L X X H L
H .j. H H L
H .j. L L H
C21 FD3 EO I Sheet 1/2 I

I Page 12-19
3-201
Cell Name
FD3
Equivalent Circuit
PRo-~~------------,
XCKO CKO ,...----+----------1 )0--0 Q

--L --L
D----1>----I )(:>--0 XQ
00---1
TCKO CKO T XCKO

--L XCKO --L
T
XCKO
TCKO
CK~CKO
. L---. XCKO
CK
i
~tcw
, tCWL-
i
V-
I--- t s o - 4-tHO--
D W
J~
Q,XQ
,
. . tpd-+
i~
04- tAEM -+
PR
-tINH -+
PR
Q,XQ
C21-FD3-EO Sheet 212

Page 12-20
3-202
FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION • CG21 K· Version
FD4 Non-SCAN Power OFF with Clear and Preset 9

tup Idn
Path
1.003 0.028 0.911 0.023 0.045 7 CKtoQ
1.485 0.023 1.439 0.017 0.034 7 CKtoXQ
1.307 0.023 0.772 0.023 0.045 7 CLtoQ,XQ
1.314 0.028 0.489 0.017 0.034 7 PRto Q, XQ
PR
D- r--Q
CK ---<
p-- XQ
CL Parameter Symbol Typ (ns) *

Clock Pause Time leWL 2.5

Input Loading Preset Pulse Width tpw 2.5

Pin Name
Faclor(lu) Preset Release Time t REM 0.3
D 2 Preset Hold Time tlNH 2.3
CK 1
CL 2 Clear Pulse Width tLW 2.5
PR 2 0.6
Clear Release Time I REM
Clear Hold Time IINH 2.0
OUlpul Driving
Pin Name
Faclor (Iu)
Q 36
multiplier.
Function Table
Inputs Outputs
PR CL CK D Q XQ
L H X X H L
H L X X L H
H H .!. H H L
H H .!. L L H

I Page 12-21
3-203
Cell Name
FD4
Equivalent Circuit
PRo-~~------------,
XCKO
r----+--------t )0--0 Q
i.
00---1 D--1~-t )(:>---0 XQ
XCKO
i.
T
XCKO
TCKO
CL CK~CKO
Definitions of Parameters • ~XCKO
~ICW ICWL-
CK
I
V-
I4--- l s o - ~IHD'"
o
~ Ipd-l
a,xa
1\
14-- IREM --I
PR
CL ~
I-- IINH - - I
PR
CL
a,xa
C21-FD4-EO Sheet 212

Page 12-22
3-204
FD5 Non-SCAN Power DFF with CLEAR 8

tup tdn
Path
0.997 0.032 0.904 0.023 0.045 7 CKtoO
1.360 0.032 1.360 0.017 0.034 7 CKtoXO
1.248 0.032 0.805 0.023 0.045 7 CL toO. XO
r--
0- -0
CK ---<
:>-- xo
CL Parameter Symbol Typ (ns)·

Clock Pause Time tewl 2.5
Data Setup_Time tso 1.3

input LoadIng Clear Pulse Width tlW 2.5

Pin Name
Factor (iu) Clear Release Time tREM 0.9
D 2 Clear Hold Time t INH 2.7
CK 1
CL 2
output Driving
Pin Name
Factor (Iu)
0 36
multiplier.
Function Table
Inputs Outputs
CL CK D 0 XO
L X X L H
H J. H H L
H J. L L H

I Page 12-23
3-205
Cell Name
FD5
Equivalent Circuit
CKO XCKO
....---------1 )0--0 Q
-L -L
D 0---1 H - - - - i )()--_._-I )()---o XQ
CKO
-L
TCKO T
XCKO
CK~XCKO
. L--. CKO CL
f4--- lew
CK 'f
ICWI. -
,---
J
o
,.. ISD~ f4- IHD~
'I
~ Ipd ....
Q,XQ
f4---IINH-
CL
~
ILW
J
r-
r-Ipd _ _
~
Q,XQ 'I
~
I4-IREM-
CL If
C21-FDS-EO Sheet 2/2

Page 12-24
3-206
FJD Non-SCAN Positive edge clocked Power JKFF with Clear 12

Cell Symbol Propagalion Delay Parameler
!Up Idn
Path
2.323 0.032 1.564 0.023 0.039 7 CKtoQ
2.343 0.032 1.314 0.023 0.039 7 CKtoXQ
1.267 0.032 0.680 0.023 0.039 7 CLloQ,XQ
-
J- !--Q
CK-
K- ::>-- XQ
CL Parameter Symbol Typ (ns)'

Clock Pause Time ICWH 3.3
J K SetuD Time Iso 1.5

J K Hold Time IHO 0.8
Inpul Loading Clear Pulse Width ILW 2.5

Pin Name
Faclor (Iu) Clear Release Time I REM 1.5
CL 2 Clear Hold Time IINH 2.7
J 1
K 1
CK 1
Oulpul Driving
Q 36
XQ 36
multiplier.
Function Table
Inputs Outputs
CL CK J K Q XQ
L H X X L H
H j L L 00 XQO
H j L H L H
H j H L H L
H j H H XOO 00
C21 FJD-EO I Sheet 1/2 I

I Page 12-25
3-207
FUJITSU CMOS GATE ARRAY UNIT CEll SPECIFICATION " CG21K" Version
eel/Name
FJD
Equivalent Circuit
Ko--+..y
CK
P--1~--I )(>----0 xa
CLo--------+---+------~r_--_,
t:>-~""""-I )1:>-----0 a
-lew ICWH-
CK
~
. . ISD~ "IHD~
J, K
i
IDI a,xa
of- Ipd'"
,
i
!+--IINH--
ILW
Cl V-
i
~ rlpd --
a,xa W-
i
!+-IREM-
Cl If
C21-FJD-EO Sheet 212

Page 12-26
3-208
Scan Counter Family
Unit Cell Basic

Up Counter with Parallel Load 62
Down Counter with Parallel Load 66
3-221 SC43 Scan 4-bit Synchronous Binary Up Counter with
Asynchronous Clear 59
3-225 SC47 Scan 4-bit Synchronous Binary Up/down Counter 78
III
3-209
CG21 Series Unit Cell Library CMOS Channe/Isss Gate AlT8)'s
3-210
Cell Name Funcllon Number 01 BC
SCAN 4-bit Synchronous Binary
SC7 Up Counter with Parallel Load 62
\up Idn
Path
1.743 0.032 1.611 0.028 0.067 7 CK,IHto Q
3.056 0.032 2.818 0.028 0.067 7 CK,IHtoXQ
4.119 0.032 2.766 0.017 - - CK,IHto CO
DA-
-OA
1.056 0.032 0.053 0.017 - - Clto CO
DB-
:>--XOA
DC-
-OB
DD-
:>--XOB
CK- -OC
IH- :>--XQC
L--( -00 Parameler Symbol Typ (ns)'
CI- :>--XOD Clock Pulse Width low 4.2
EN- Clock Pause Time IOWH 4.2
-co
SI-
A- Data Setup Time Iso 1.2
B--( Data Hold Time tHO 2.0
Load Setup Time I Sl 3.7

Load Hold Time IHl 2.1
Inpul loading CI Setup Time Isc 4.2

Pin Name
Faclor(lu) CI Hold Time IHC 1.6
D 1
CK 1 EN Setup Time I SE 4.2
IH 1 EN Hold Time tHE 1.6
L 1
CI 2
EN 1
51 1
A,B 1
Outpul Driving
Pin Name
Faclor(lu)
0 36
XO 36 • Minimum values for Ihe typical operating condition.
CO 36 The values for the worsl case operating condition are given by the maximum delay
multiplier.
C21 SC7-EO I Sheet 1/5 I

I Page 13-1
3-211
FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION
Cell Name
sel
Equivalent Circuit
DA QAXQA DB aBxaB DC aexae DO aDXQD
51
EN
CI
CO
~~'
CK ~ A o----i X>--t----- XAI
IH
XCKI )(>--AI
LO~~~_::
B 0----/ )0-......- - - - BI
)O--.XBI
C21-SC7-EO Sheet 2/5

Page 13-2
3-212
FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION • CG21K • Version
Cell Name
SC7
XlDI CKl XBI XCKI

Q
-L -L -L -L
o XQ
1..----...0 co
XCKI
XAI XCKI AI
XlDI -L -L -L
s
I II
'1m
AI CKI XAI
I
XBI
XTG o---li--------+--l X:>-----4
C21-5C7-EO Sheet 3/5

Page 13-3
3-213
Cell Name
sel
Function
LOAD L LJ
DA
DB
DATA
INPUT
DC
DO
CLOCK CK+IH
ENABLE EN
CARRY IN CI
OA ~
DATA OB
OUTPUT
IDII OC
00
CO
n
MODE I I
Inhibit Load Count Inhibit

Page 13-4
3-214
Cell Name
sel
i) CLOCK MODE
----01---1 CWH
CLOCK
DATA
I SL I HL
IHC
Isc
CI
ISE
IHE
'E
EN

Page 13-5
3-215
FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION I " CG21K "Version
SCAN 4-bit Synchronous Binaly
SGB Down Counter with Parallel Load 66
tup tdn
Path
1.782 0.028 1.683 0.028 0.062 7 CK,IHtoQ
2.323 0.023 2.284 0.017 CK,IHto XQ
3.386 0.032 4.422 0.017 CK,IHto BO
DA- 0.786 0.032 1.201 0.017 Blto BO
f--QA
DB-
P--XQA
DC-
f--OB
DD-
P--XOB
CK- f--OC
IH- p--xac
L--( f--OD Parameter Symbol Typ (ns)'
BI--( P--XOD Clock Pulse Width tew 4.0
EN--( Clock Pause Time tcWH 4.0
SI- P--BO
A- Data Setup Time tso 1.2
B--( Data Hold Time tHO 2.0
Load Setup Time t SL 3.7

Input Loading EN Setup Time tSE 4.8

Pin Name
Faclor(lu) EN Hold Time tHE 1.1
D 1
CK 1 BI Setup Time tSB 4.8
IH 1 BI Hold Time tHB 1.1
L 1
BI 2
EN 1
SI 1
A,B 1
Output Driving
Pin Name
Faclor (Iu)
0 36
BO 36
multiplier.
C21-SC8-EO I Sheet 1/5 I

I Page 13-6
3-216
eeliName
SGB
Equivalent Circuit
DA QAXQA DB OBXOB DC OC XOC DO OOXOD
51
EN
BI
BO
~'"
CK ~ A o---~ )(>--_----- XAI
IH
XCKI ) 0 - - . AI
B o---~ )(>--_----- BI
)O--.XBI

Page 13-7
3-217
Cell Name
SGB
XTG o----lI----------4--Dc>---+
C21-SCB-EO Sheet 3/5

Page 13-8
3-218
Cell Name
SGB
Function
LOAD L LJ
DA
DATA DB
INPUT
DC
DD
CLOCK CK+IH
ENABLE EN
CARRY IN BI
OA ~
OB
DATA
OUTPUT
OC
OD
BO LJ
MODE
Inhibit
I I
Load Count down Inhibit

Page 13-9
3-219
Cell Name
SGB
i) CLOCK MODE
CLOCK , I---tcw
1\
tcWH-
1\
If
!--tso- - t H O -
DATA I(
1\
L
, I--tSL
1\
tHL-
tHE
I---tSE
~
EN 1\
BI
, -tsa tHa-

Page 13-10
3-220
FUJITSU CMOS GATE ARRAY UNIT CEll SPECIFICATION I .. CG21K • Version
Cell Name Funclion Number of BC
SCAN 4-bit Synchronous Binary Up Counter
SC43 with Asynchronous Clear
59
Cell Symbol Propagallon Delay Parameler
rup tdn
Path
2.257 0.060 2.172 0.039 0.056 4 CKtoQ
r-- 2.719 0.060 2.904 0.039 0.056 4 CKtoCO
DA-
DB-
-QA
-OB
-
0.964
-
0.060
1.380
0.660
0.039
0.039
0.056
0.056
4
4
CltoQ
CltoCO
DC-
DD-
-QC
-aD
- - 1.888 0.039 0.056 4 CltoCO
CK-
IH-
L--(
CI- I--CO
EN-
Sl- I--SO
A-
B--(
CL Data Setup Time tso 1.2
load Setup Time I SL 1.8
load Hold Time tHL 1.5
Input Loading CI Setup Time Ise 2.4
Pin Name Faclor (Iu) CI Hold Time tHe 1.1
D 2 EN Setup Time tSE 2.4
CK,IH 1 EN Hold Time tHE 1.1
L, CL, SI 1 Clear Pulse Width tLW 3.7
EN 1
A,B,CI 2 Clear Release Time IREM 0.9
Clear Hold Time tlNH 3.4
OUlput Driving
a 18
co 18 • Minimum values for the typical operating condition.
multiplier.
C21-8C43-EO I Sheet 1/4 I

I Page 13-11
3-221
Cell Nam.
8C43
Equivalent Circuit
DA OA DB OB DC OC DO 00
XCKI XCKI
CKI CKI
LDI LDI
XLDI XLDI
XAI XAI
AI AI
BI BI
XBI XBI
CL
81
EN
CI
~c.
CK ~ A ) 0 . - _ 1 ' _ - - - - XAI
IH
XCKI ) 0 . - _... AI
LO B )O.-_1'_----BI
X>---"'XBI
C21-SC43-EO Sheet 214

Page 13-12
3-222
FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION • CG21K " Version
Cell Name
SC43
XLDI CKI XBI XCKI

--L --L --L--L
o )(>--00
L....----<~-oxo
XCKI BI CKI
XLDI XAI XCKI AI

--L --L--L
S
CL.
eo
I II
AI CKI XAI
I
XBI
~Go--r-------------+~

Page 13-13
3-223
Cell Name
SC43
f4-- t cw tCWH-
CK '{
~
~ll---'
tso
tHO-
11
0
i i II
tREM
~tLW
-tINH-
CL' '{
i
11
i - - t S L - :'-tHL-
II
L
CI
i
-tsc
,
tHe....
II
- t S E - -tHE ....
EN '{
i ~
11
C21-8C43 EO I Sheet 4/4 I

I Page13-14
3-224
SC47 SCAN 4-bit Synchronous Binary Up/Down Counter 78

tup tdn
Path
2.376 0.060 2.482 0.084 0.112 4 CKtoQ
DA-
- -QA
3.234
1.241
0.060
0.060
4.594
1.551
0.039
0.039
CKto CO
DUtoCO
DB- -OB
DC- -QC
00- -00
CK-
IH-
L--<
TM-
EN- :>-- co
DU-
SI- r--- SO
A- Parameter Symbol Typ (ns)'
B--< Clock Pulse Width (HI tew 3.0
'-- Clock Pause Time (Ll tCWH 4.3
EN Setup Time tSE 2.4
EN Hold Time tHE 1.1
Input loading DU Input Setup Time tsu 1.1
Pin Name Factor (Iu) DU Input Hold Time tHU 2.4
0 2 Load Pulse Width tlW 3.7
CK.IH. TM. L 1 Clear Release Time t REM 0.9
EN 3 Clear Hold Time tlNH 3.4
DU.A. B 1
SI
Pin Name
2
Output Driving
Factor (Iu)
III
0 18
so 18 • Minimum values for the typical operating condition.
CO 18 The values for the worst case operating condition are given by the maximum delay
multiplier.
C21-SC47 EO I Sheet 1/4 I

I Page 13-15
3-225
Cell Name
SC47
Acr-f>o-~- XAI
Equivalent Circuit ~AI
r---
i""I
l./
ecr-f>o
, ~ ::, co
OU i""I
~ L.I
OA e>-:==:r---
==
aA
~
61 0--:::::: FFu
-
EN == ~1t--
L$
~~~
ae
_ FFu
-
== - ~l
~~-
ac
- FFu
==
== - I -l
.......
000-::::- ao
==
-
"" ~so
./
~ ....... ==
--~
./
TM~
L
LO
CK ~ rr;::cKO
IH XCKI
C21-SC47-EO Sheet 214

Page 13-16
3-226
Cell Nama
SC47
Symbol
0 o
LO
CKO
XCKO
S FFu
XAI
AI
BI
XBI 00
TGO XCo

r----------------------oxao
+----------1 X)---------o 0
H-------t-r ~.__------....o ao
IXCKO I I CKO
BI CKO -L
XAI XCKO AI
-L -L-L DO
LO
S XCKO
XDO BI
LO -L
AI eKO XAI
I XBI
TGO
o 0----..--[>0---: :
Page 13-17
3-227
Cell Name
SC47
tcW-......--tCWH
OK
tHO
tREM
L 11
tSE tHE
11
EN \
IDII DU
tsu tHU
11
C21-SC47-EO Sheel4/4
Page 13-18
3;..228
Non-Scan Counter Family
Unit Cell Basic

3-231 C11 Non-Scan Flip-Flop for Counter 11

3-233 C41 Non-Scan 4-bit Binary Asynchronous Counter 24
3-236 C42 Non-Scan 4-bit Binary Synchronous Counter 32
3-247 C47 Non-Scan 4-bit Binary Synchronous Up/Down Counter 68
3-229
CG21 Series Unit CeH Library CMOS Channa/less Gate AmlYs
3-230
I FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION .. CG21K" Version
C11 Non-SCAN Flip-Flop for Counter 11

tup teln
Path
1.003 0.060 0.924 0.045 CKtoO
.---- 1.340 0.060 1.571 0.045 CKto XO
D- 1.386 0.060 0.918 0.045 CLtoO,XO
L- -0
CK-
TG- >-xo

CL
Clear Pulse Width tlW 2.5

Clear Release Time t REM 0.6
Clear Hold Time tiN" 0.3
Input loading
Pin Name
Factor (Iu) Load Setup Time (CK) tSl 1.4
Load Hold Time (CK) tHl 0.3
L 2
TG 2
CL 2 Data Setup Time (CK) tso 1.5
D,CK 1 Data Hold Time (CKI tHO 0.3
Output Driving TG Setup Time (CK) tST 1.8

Pin Name
Factor (Iu) TG Hold Time (CK) tHT 0.0
0 18
XO 18
The values for the worst case operating condition are given by the maximurtt delay
multiplier.
Function Table
L D TG CL CK 0(00)
X X X L X L
H H X H t H
H L X H t L
L X L H t 0(00)
L X H H t 0(00)
C21 C11 EO I Sheet 1/2 I

I Page 14-1
3-231
Cell Name
e11 Equivalent Circuit

XLO CL
-L
o »------00
XO
CL
TG o--il-+-i
CK~CKO
V ~XCKO
I - - I C.. ICWH-
CK
'---
CL
, -ILW
If
IRE~
f4-IINH
CL
1
I SL IHL-
L If
J
I so IHO-
o W
Jr... ~
1ST IHr
TG If
---1 ~
C21-C11-EO Sheet 2/2

Page 14-2
3-232
C41 Non-SCAN 4-bit Binary Asynchronous Counter 24

tup tdn
Path
1.056 0.051 0.984 0.045 - - CKtoQA
1.941 0.051 1.736 0.045 - - CKtoQB
r--- 2.713 0.051 2.508 0.045 - - CKto QC
-QA 3.485 0.051 3.274 0.045 - - CKto QD
-oB - - 2.211 0.045 - - CLtoQ
-oc
-00
CK-

Cl

Clear Hold Time tlNH 4.0
Input loading
Pin Name
Factor (Iu)
CK 1
Cl 1
Output Driving
Pin Name
Factor (Iu)
a 18
multiplier.
Function Table
Inputs Output
CL CK Q
H t Count up
L X L
C21-C41 EO I Sheet 1/3 I

I Page 14-3
3-233
Cell Name
C41
Equivalent Circuit
OA OB OC 00
CKO
FTO FTO FTO FTO
XCKO
cLoo------4-------------4-------------4------------~
CL o-(>o---t>o- CLO CK~CKO

V L-XCKO
FTO(FIip-Flop for Counter) (not Uint Cell )
~I Function Table
a CLO CKO a
CKO
FTO co L x L
XCKO
XCO H t an-I
CLO
CLO
r------1 ) 0 - - - - - 0 a
1-+-----; X>---_---o co
T XCKO CKO CKO

XCKO
.-L .-L
T T
CKO XCKO
CLO
L-----------------------------------~----_OXCO

Page 14-4
3-234
Cell Name
C41
CK
CL
Sheet 313
Page 14-5
3-235
C42 Non-SCAN 4-bit Binary Synchronous Counter 32

tup teln
Path
1.683 0.051 1.234 0.039 0.056 4 CKtoQ
- - 1.776 0.039 0.056 4 CLtoQ
- I--OA
I--OB
'---oc
1--00
CK-

CL
Clock Pause Time teW!! 2.5
Clock Pulse Width tLW 2.5

Input Loading
Pin Name
Faclor(lu)
CL 1
CK 1
Output Driving
Pin Name
Faclor(lu)
0 18
multiplier.
Function Table
Inputs Outputs
CL CK Q
H i Count up
L X L

I Page 14-6
3-236
Cell Name
C42
Equivalent Circuit
OA OB OC 00
CKO CKO CKO CKO
XCKO
CLOo---------4----;----------~--_+--_f-----4----4_--~----~
'" ~XCKO
CK~ CKO
Inputs Outputs
CKO o
CLO xrG CKO 0(00 )
XCKO
L X X L
XTG co H H i On-l
H L i 0;;:;
CLO

Page 14-7
3-237
Cell Name
C42
CLO
CKO )0------00
--.L
...............--/ )O---~...---o ao
T
KCKO
T T
CKO XCKO
XTG o--I---t--i
CK
tcw--I_- -t
t LW _--t.t_R_EM.-j II '""
--+------ll
CL

Page 14--8
3-238
FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION J • CG21K • Version
C43 Non-SCAN 4-bit Binary Synchronous Up Counter 48

!Up tdn
Path
1.564 0.060 1.267 0.039 CKtoQ
2.957 0.060 1.881 0.039 CKto CO
r-- 0.845 0.060 0.429 0.039 CI to CO
DA- I--QA
- - 2.053 0.039 CLtoQ
DB-
DC-
I--QB
i--QC
- - 1.393 0.039 CLtoCO
00- i--QD
L--<
CK-
EN-
CI- -co

CL Clock Pulse Width lew 2.5
Load Setup Time ISL 2.7
Inpul Loading CI Setup Time Ise 2.6
Pin Name
Faclor (Iu) CI Hold Time IHe 0.6
EN Setup Time ISE 2.6
0 1 EN Hold Time IHE 0.6
L,EN 1
CK,CL 1 Clear Pulse Width ILW 3.3
Ci 2 Clear Release Time I REM 1.2
OUlpul Driving
Pin Name
Factor (Iu)
Q 18
CO 18
multiplier.
Function Table
Inputs Outputs
CL L D EN CI CK Q
L X X X X X L
H L H X X i H
H L L X X i L
H H X H H i Count up
Note: The CO output produces a high level


I Page14-9
3-239
Cell Name
C43
Equivalent Circuit
DA OA DB aB DC ac DO aD
LO
XLO
CKO
XCKO
CI CLO
EN
CL o--i>o-- CLO
L~LO CK~XCKO
. L...[>o---- XLO . L...[>o---- CKO
C21-C43-EO Sheet 214

Page14-10
3-240
Cell Name
C43
0 LO 0 XTGO OLO CK 0(00)

LO 0
X X X H X L
XLO 00
H H X L j H
CKO
H L X L j L
XCKO
L X H L j 0(00)
XTGO
L X L L j --
0(00)
OLO

OLO
XLO
--L
o '\0---00
OKO I
XOKO
XTGO D-----1f-H

Page14-11
3-241
Cell Name
C43
CK
~Icw ICWH_
, '(
~
~11--'
Iso
D
,
J
IHO_
J
11
11
I REM _ _ IINH_
i---ILW
CL ~
J
II
foo-- I SL---- foo-IHL-
'( 11
L ~ J
IHe
j--Isc
CI 'I
J 11
IHE
j--ISE
EN '(
J 11

I Page14-12
3-242
C45 Non-SCAN 4-bit Binary Synchronous Up Counter 48

tup tdn
Path
1.413 0.051 0.990 0.039 0.062 4 CKtoQ
2.680 0.064 1.492 0.039 CKtoCO
- 1.010 0.064 0.720 0.039 CltoCO
DA- i---aA
DB- i---aB
DC- ,..--ac
00- '--aD
L--(
CK-
EN-
CI- -co
Parameter Symbot Typ (ns) *

CL Clock Pulse Width lew 2.5
Clock Pause Time leWH 2.5
Load Setup Time ISl 2.9
Load Hold Time I Hl 1.3
Input Loading CI Setup Time Isc 3.9
Pin Name
Faclor(lu) CI Hold Time tHC 1.2
EN Setup Time I SE 3.9
0 1 EN Hold Time tHE 1.2
L,EN 1
CK,CL 1 Clear Setup Time tSA 2.3
CI 2 Clear Hold Time IHA 1.2
Outpul Driving
Pin Name
Factor (Iu)
a 18
CO 18 • Minimum values for Ihe typical operating condition.
multiplier.
Function Table
Inputs Outputs
CL L D EN CI CK Q
L X X X X l' L
H L H X X l' H
H L L X X l' L
H H X H H l' Count up
Note: The CO output produces a high level


I Page14-13
3-243
Cell Name
C45
Equivalent Circuit
DA OA os as DC ac DO 00
LO
XLO
CKO
XCKO
CI CLO
EN
L~LO CK~XCKO
. L{>o---- XLO . L{>o---- CKO
C21-C45-EO Sheet 214

Page14-14
3-244
Cell Name
C45
0 LO 0 xrGO CLO CK 0(00)

LO 0
L X X H i L
XLO 00
H H X L i H
CKO
H L X L i L
XCKO
L X H L i 0(00)
xrGO
L X L L i -0(00)
-
CLO
CLOo--------,
XLO
.-L
o )0---00
1-1-.......--1 )()----...--o 00
CKO I
XCKO

Page14-15
3-245
Cell Name
C45
,
_ lew lewH _
CK
~
!+-Iso'" _ I H O _
CL
, ~ISR- _ I H R _
_ ISL IHL_
I---Ise
If ,
IHC-
HI
CI
J ~
I---ISE IHE-
EN
If
J 1\
C21-C45-EO I Sheet 4/4 I

I Page14-16
3-246
C47 Non-SCAN 4-bit Binary Synchronous Up/Down Counter 68

tup tdn
Path
2.106 0.060 1.894 0.073 0.112 4 CKtoQ
2.858 0.041 3.234 0.039 CKtoCO
r--- 2.647 0.060 2.924 0.073 0.112 4 LtoQ
DA- f--OA DUto CO
1.307 0.041 1.591 0.039
DB- f--OB
DC- f--OC
00- f--OD
L--<
CK-
EN--<
DU- P--CO
-
Data Setuo Time tso 0.5

Pin Name
Input Loading DU Setuo Time tsu 3.2
Factor (Iu) DU Hold Time tHU 0.5
0 1
L 2 EN Setup Time tSE 2.9
DU 1 EN Hold Time tHE 0.8
CK 1
EN 3
Load Release Time tREM 1.4
I
Output Driving Load Hold Time tlNH 6.5
Pin Name
Factor (Iu)
0 18 • Minimum values for the typical operating condition.
CO 18
multiplier.
Function Table
Inputs Outputs
Q L EN DU CK Q
H L X X X H
L L X X X L
X H H X i No Counting
X H L L i Count Up
X H L H i Count Down
Note: The CO output produces a low level output

pulse when the counter overflows or underflows.

I Page14-17
3-247
Cell Name
C47
Equivalent Circuit
r-- """
l./ ~
- co
DU
"""
~
H> L..I
DAC--
LO-
OA
~
FT7
CKO-
XCKO -C
f.-
EN ,..,
~ 1
~'~
OB
LO-
FT7
CKO-
CK
~'c,o XCKO -C
f--
CKO
1
L o--C:x>-- LO
DCC-- OC
LO-
FT7
CKO-
XCKO -C
-
1
r--
DOC-- 00
LO-
FT7
'.../ CKO-
XCKO -C
-
- -

Page14-18
3-248
Cell Name
C47
Function Table
D8°
LO
CKO
XCKO
TGO
FT7
co
XCO
LO
H
H
L
D
L
X
Inputs
TOO
X
X
L
CKO
X
X
i
CO(O)
H
L
On-1
Outputs
O(CO)
0;;:;
L
H
L X H i a;;:1 On-1

XCO
co
T
XCKO
XCKO
-L
TCKO CKO
-L III
XDO DO
LO LO
CKO XCKO
TGO
D~DO
V L- XDO

Page14-19
3-249
Cell Name
C47
tew tewH
CK
II
tHO
D
II
II
tREM II
tSE tHE
II
EN
tsu tHU
DU
II

Page14-20
3-250
CMOS Channel/ess Gate Arrays CG21 Series Unit Cel/ Library
Adder and ALU Family
Unit Cell Basic

3-253 A1A 1-bit Half Adder 5

3--255 A2N 2-bit Full Adder 16
3-257 A4H 4-bit Binary Full Adder with Fast Carry 48
3-251
CG21 Series Unit Cell Library CMOS Channel/ess Gate AITBYs
3-252
A1A 1-bit Half Adder 5

\Up tdn
Path
0.647 0.032 0.759 0.017 Ato S
0.574 0.032 0.772 0.017 BtoS
0.594 0.032 0.660 0.017 AtoCO
0.673 0.032 0.607 0.017 BtoCO
,=[]=ro
A S
Input Loading
Pin Name
Factor (Iu)
A 2
B 2
Output Driving
Pin Name
Factor (Iu)
CO 36
S 36 • Minimum values for the typical operating condition.
multiplier.
It) F::=~
A B CO S A
B
L L L L
L H L H
H L L H
H H H L
C21 A1A EO I Sheet 1/1 I

I Page 15 1
3-253
A1N 1-bit Full Adder 8

!Up teln
Path
to KOL to KOL KOL2 CDR2
1.393 0.060 1.663 0.039 A,BtoS
0.660 0.060 0.713 0.039 CltoS
1.578 0.060 1.261 0.039 A,BtoCO
0.541 0.060 0.621 0.039 CltoCO
8- I--- 00
A- I--- S
J Parameter Symbol Typ (ns)'
Input Loading
Pin Name
Factor (Iu)
A 3
B 3
01 3
Output Driving
Pin Name
Factor (Iu)
00 18
s 18 • Minimum values for the typical operating condition.
multiplier.
Function Table Equivalent Oircuit
A
r-...
Inputs
01
Outputs
00
B
II...,
Tt7
'"
II S
A B S
L L L L L 01
H L L H L
~~oo
L H L H L
H H L L H
L L H H L I
V
H L H L H
L H H L H
H H H H H
C21 A1N EO I Sheet1/1 I

I Page 15-2
3-254
A2N 2-bit Full Adder 16

tup tdn
Path
1.505 0.106 1.485 0.062 - A1 to CO
1.446 0.106 1.518 0.062 - B1 to CO
0.838 0.106 0.720 0.039 0.056 4 A2to CO
0.779 0.106 0.720 0.039 0.056 4 B2to CO
1.472 0.106 1.366 0.062 - CltoCO
B2- ~CO 1.571 0.083 1.452 0.062 - A1 to S1
A2- 1.571 0.083 1.452 0.062 - B1 to S1
Bl- -52 0.627 0.083 0.627 0.062 - CI to S1
Al- -51 1.492 0.083 1.452 0.062 - A1 to S2
1.644 0.083 1.558 0.062 - A2to S2
1.432 0.083 1.485 0.062 - B1 to S2
-
lr 1.644
1.459
0.083
0.083
1.558
1.333
0.062
0.062 -
B2 to S2
CltoS2
Parameter 5ymbol Typ (ns) *
Input Loading
A,B 2
CI 2
Output Driving
5 14
CO 14 * Minimum values lor the typical operating condition.
multiplier.
Function Table
Outputs
Inputs
CI = L CI =H
Al Bl A2 B2 51 52 CO 51 52 CO
L L L L L L L H L L
H L L L H L L L H L
L H L L H L L L H L
H H L L L H L H H L
L L H L L H L H H L
H L H L H H L L L H
L H H L H H L L L H
H H H L L L H H L H
L L L H L H L H H L
H L L H H H L L L H
L H L H H H L L L H
H H L H L L H H L H
L L H H L L H H L H
H L H H H L H L H H
L H H H H L H L H H
H H H H L H H H H H
C21 A2N EO I Sheet 1/2 I

I Page 15-3
3-255
Cell Name
A2N Equivalent Circuit
~ ________________-+______ -h~-------oCO
A20-_._--I
820--.......-+7
0-----052
Al 0-_._--1
810--.......-+7
0-----051
Cl o-----~--IX>-~-------~r_;
C21-A2N-EO Sheet 212

Page 15--4
3-256
A4H 4-bit Binary Full Adder with Fast Carry 48

\up tdn
Path
to KCL 10 KCL KCl2 CDR2
0.627 0.083 0.865 0.062 Clto S1
1.399 0.106 1.624 0.062 Clto S2
1.604 0.106 1.578 0.062 CI to S3
B4- I - - co 1.657 0.106 1.868 0.062 Clto S4
A4- I - - S4 1.518 0.060 1.696 0.039 CltoCO
B3-
A3- I - - S3 2.013 0.083 1.789 0.062 A1. 81 to S1
B2- 1.677 0.106 1.630 0.062 A1. 81 to S2
A2- I - - S2 1.809 0.106 2.033 0.062 A1. 81 to S3
Bl- 1.980 0.106 2.073 0.062 A1. 81 to S4
AI- l-- SI 1.743 0.060 2.000 0.039 A1. 81 to CO
1
1.630 0.106 1.782 0.062 A2.82toS2
1.934 0.106 1.901 0.062 A2. 82 to S3
1.974 0.106 2.139 0.062 A2. 82 to S4
2.046 0.060 2.026 0.039 A2. 82 to CO
Input Loading 1.485 0.106 1.505 0.062 A3.83toS3

Pin Name Faclor(lu) 2.026 0.106 2.132 0.062 A3. 83 to S4
A 2 2.007 0.060 2.020 0.039 A3. 83 to CO
B 2
CI 2 1.531 0.083 1.591 0.039 0.056 4 A4. 84 to S4
1.934 0.060 1.855 0.039 A4. 84 to CO
Output Driving
Pin Name
Factor (Iu)
18
III
CO
SI, S3, S4 14
S2 18
Function ·Table Nole:
Outputs Inpul conditions al AI, A2, Bl, B2 and

CI are used to delermine outputs SI
Inputs CI =L CI=H
- - - - -C£;C- - - -- -----_C2=H
.. _------ and S2 and Ihe value of the internal
carry C2.
SI S2 C2 The values al C2, A3, 83, A4 and B4
AI Bl A2
- -AS- - -83- - - A4
B2
- - -134-- --saSI ---54-
S2 C2
- - co --- - 53 - - -S4- - -CO- are then used to determine outputs
83, S4 and CO.
L L L L L L L H L L
H L L L H L L L H L
L H L L H L L L H L
H H L L L H L H H L
L L H L L H L H H L
H L H L H H L L L H
L H H L H H L L L H
H H H L L L H H L H
L L L H L H L H H L
H L L H H H L L L H
L H L H H H L L L H
H H L H L L H H L H
L L H H L L H H L H
H L H H H L H L H H
L H H H H L H L H H
H H H H L H H H H H
C21 A4H EO I Sheet 1/2 I

I Page 15-5
3-257
eellName
Equivalent Circuit
A4H
I
D-
""I -""I
-./~
-
CO
-,/
r-.
B4Q--<~
-.--- P---
r-L/
.......
r-..
fp, -U I I
T""D' -f'IP:>--<>S4
A4 L/
-U
J
-- ~~
B3o-~
-r-
r- =)-IFJ-
-L/
.......
fp., --LJ --t-b
r-..
-l""IP:>--<>S3
A3 ....,
-U
~
r- r-
r- r-
B2o-~ r-
A2 ,..
rEP, r--u ~ ....... [}--o52
V~
L/
I....,
Blo-~
~
r-
-lI""I
Al
rFP,
...., r-L' V~51
CI
1ft
C21 A4H EO I Sheet 2/2 1
I Page 15-6
3-258
Data Latch Family
Unit Cell Basic


3-265 LTK Data Latch 4
3-267 LTL 1-bit Data Latch with Clear 5
3-269 LTM 4-bit Data Latch with Clear 16
3-272 LT1 S-R Latch wHh Clear 4
3-274 LT4 4-bit Data Latch 14
3-259
CG21 Series Unit Cell Ubrary CMOS Channe/less Gate Arrays
III
3 .... 260
YL2 1-bit Data Latch with TM 5

\up !dn
Path
1.446 0.032 1.485 0.017 CK,lHto a
0.614 0.032 0.680 0.017 OtoO
'n
CK
IH
TM
Q
Clock Pulse width tew 4.0
Data SetlltLTime tso 1.9

Input Loading
Pin Name
Factor (Iu)
D 2
CK 1
IH 1
TM 1
Output Driving
Pin Name
Factor (Iu)
0 36
The values for the worsl case operating condition are given by the maximum delay
multiplier.
Note :
Function Table
Input Output
Mode
TM IH CK D 0
L X X D D SCAN
H H X X 00
H X H X 00 LATCH
H L L D D
C21 YL2 EO I Sheet 1/2 I

I Page 16-1
3-261
eel/Name
YL2
Equivalent Circuit
~------------------~Q
D o--------------j
T XCKI
XCKI -L
TCKI
XCKI
[)o-----.- :
CKI
CK
,-tcw-
tso tHO
o W '/
J
Q
+- tpd ......
,
C21-YL2-EO Sheet 2/2

Page 16-2
3-262
YL4 4-bit Data Latch with TM 14

!up tdn
Path
1.762 0.032 1.815 0.017 CK,lHlo Q
0.581 0.032 0.680 0.017 Dlo Q
D1- - 01
D2- - 02
D3- - 03
D4- - 04
CK --<
IH-
TM --<
Parameter Symbol Typ (n5)'
Clock Pulse width (CK) tew 4.2
Data Setup Time (D) tSD 1.1

Data Hold Time (D) tHO 2.4
Input Loading
Pin Name
Factor (Iu)
D 2
CK 1
IH 1
TM 1
Output Driving
Pin Name
Factor (Iu)
Q 36
.. Minimum values for the typical operating condition.
multiplier.
Note:
Function Table
Input Output
Mode
TM IH CK Dn On
L X X D D SCAN
H H X X Ono
H X H X Ono LATCH
H L L D D
n = 1- 4
C21 YL4 EO I Sheet 1/2 I

I Page 16-3
3-263
Cell Name
YL4 Equivalent Circuit

~-----.-----------------------
~----~-------------oal
• 01 0--------------:;
T XCKI
XCKI -.L
TCKI
02 0...-------------,,....-----------------------------.-.--------0 Q2
t-----------------------------.~i-------OOO
030...-------r
t--------------- ______________
i
4
04 O . . . - - - - - - - r ~-------O Q4
CK
,I---- lew ---
Iso 'HO
D
1\
f4- lpel --
C21-YL4-EO Sheet 212

Page 16-4
3-264
LTK Data Latch 4

tup tdn
Path
0.548 0.060 0.607 0.039 DtoQ
0.766 0.060 0.865 0.039 Dto XQ
0.924 0.060 0.964 0.039 GtoQ
1.122 0.060 1.234 0.039 GtoXQ
:=[J=a xo

G Inout Pulse Width tGW 2.5
Data Setuo Time tSD 1.0

Input Loading
Pin Name
Factor (Iu)
0 2
G 1
Output Driving
Pin Name
Factor (Iu)
0 18
multiplier.
Function Table
Inputs Outputs
0 G 0 XO
X H 00 XOo
H L H L
L L L H
C21 LTK EO I Sheet 1/2 I

I Page 16-5
3-265
Cell Nama
LTK
Equivalent Circuit
,.---------1 )0----0 a
00--------4 I-..--~ X ) - - - - i X>---t---j )1::>----0 xa
TXCO XCO
--L
Tco
(Case1)
----,.
G
IDIII a,xa
!peI
(Case2) -ISO IHO ....
D
,
I pel
a,XQ
C21-lTK-EO Sheet 212

Page 16-6
3-266
LTL 1-bit Data Latch with Clear 5

!Up tdn
Path
0.733 0.060 0.449 0.039 CLto 0, XO
0.627 0.060 0.647 0.039 DtoO
0.805 0.060 0.904 0.039 Dto XO
1.036 0.060 1.017 0.039 GtoO
1.175 0.060 1.327 0.039 GtoXO
D- -a
G ---<::
p-- xa
r Parameter
G Input Pulse Width
Symbol
tGW
Typ (ns)'
2.5


Input Loading
Pin Name
Factor (Iu)
D 2
G 1
CL 1
Output Driving
Pin Name
Factor (Iu)
a 18
xa 18 • Minimum values for the typical operating condition.
multiplier.
Function Table
Inputs Outputs
CL D G a xa
L x H L H
H X H 00 xOo
H H L H L
H L L L H
C21 LTL EO I Sheet 1/2 I

I Page 16-7
3-267
Cell Name
LTL
Equivalent Circuit
CLo-------------------~
.---------l )0----0 Q
0---......--1 ) 0 - - - -......----1 )(:>------10 XQ

00--------1
XGO
IXGO --L
I GO
(Case1) tGW
----,.
G
tpd
Q,XQ
(Case2)
G
,
-
J
tso tHO--
tpd
Q,XQ
(Case3)
CL
G'
Note'; G input must be high level at the time this latch is cleared.
C21-LTL-EO Sheet 2/2

Page 16-8
3-268
FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION I . CG21 K· Version
LTM 4-bit Data Latch with Clear 16

tup tdn
Path
0.812 0.060 0.515 0.039 CL 10 P, N
0.647 0.060 0.680 0.039 Dlo P
0.845 0.060 0.944 0.039 DloN
1.380 0.060 1.294 0.039 GloP
1.446 0.060 1.663 0.039 GloN
DA- -PA
DB- :>-- NA
DC- -PB
00- :>-- NB
-PC
G --< :>-- NC
-PO
:>-- NO
r Parameter
G InDul Pulse Width
Clear Pulse Width

Symbol
tGW
tLW
Typ (ns)·
2.5
2.5

Input loading
Pin Name
Factor (Iu)
0 2
G 1
CL 4
Output Driving
Pin Name
Factor (Iu)
P 18
N 18
mUltiplier.
Function Table
Inputs Outputs
CL 0 G P N
L X H L H
H X H Po No
H H L H L
H L L L H
C21 LTM EO I Sheel1/3 I

I Page 16-9
3-269
Cell Name
LTM
Equivalent Circuit
CLo-~1+------------~
...-----------1 )1::>--..........- 0 PA
DA 0---1-0-----1 P---4--I )(>---........---1 )(>---'-~D NA
XGO
TXGO --L
TGO
.------------------------------------------------.
• ~PB
DB o----+-;
:---0 NB
.------------------------------------------------~
• ~PC
DC o---H
:---0 NC
~PD
DO 0----: :---0 NO
._----------------------------------------------_.
101
C21-LTM-EO Sheet 2/3

Page 16-10
3-270
Cell Name
LTM
(Case1) tow
---.,.1
G
P,N
(Case2)
G 'f
+-tso- f4- tHo--
D
J
_tpd_
P,N
(Case3) +--tLW-
CL
4- tpd __
P,N
Note' : G input must be high level at the time this latch is cleared.
C21-LTM-EO Sheet 3/3

Page 16-11
3-271
FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION I . CG21 K • Version
LT1 S-R Latch with CLEAR 4

tup tdn
Path
0.931 0.060 0.469 0.039 Slo a, xa
0.825 0.060 0.548 0.039 Rloa, xa
0.759 0.060 0.489 0.039 CLIo a,xa
S--< -0
R--< :>- XO
CL Parameter Symbol Typ (ns)"

Sel Pulse Width tsw 2.5
Resel Pulse Width tRW 2.5
Input loading
Pin Name
Factor (Iu)
S 1
R 1
CL 1
DI Pin Name
Output Driving
Factor (Iu)
0 18
xo 18 " Minimum values for the typical operating condition.
The values for the worst case operating condition ere given by the maximum delay
multiplier.
Function Table
Inputs OutpUts
CL S R 0 XO
L H H L H
H H H 00 XOg
H H L L H
H L H H L
H L L Inhibited
C21 LT1 EO I Sheet 112 I

I Page 16-12
3-272
Cell Name
LT1
Equivalent Circuit
S 0---------1
p--------.-----; )O_------() xa
R 0--------; P-------+---~)O_------()a
CL 0--------;
I--- t sw ----10
s
I\.
I-- tpd -
a,xa W
JI\.
I--- tRW ----10
I-- tpd -
a,xa W
JI\.
~ tLW ----10
CL
.... tpd'"
a,xa If
I\.
C21-LT1-EO Sheet 2/2

Page 16-13
3-273
LT4 4-bit Data Latch 14

!Up kin
Path
1.320 0.060 1.208 0.039 Gto P
1.320 0.060 1.611 0.039 GtoN
0.555 0.060 0.627 0.039 Dto P
0.739 0.060 0.845 0.039 DtoN
DA- r-- PA
DB- p-- NA
DC- ~PB
DD- 0-- NB
~PC
G--<:
p-- NC
r-- PO
b-- ND

G Inout Pulse Width tGW 2.5
Data Setuo Time tso 1.0

Input loading
Pin Name
Factor (Iu)
0 2
G 1
III Pin Name

Output Driving
Factor (Iu)
P 18
N 18 • Minimum values for the typical operating condition.
multiplier.
Function Table
Inputs Outputs
D G P N
H H Po No
L H Po No
H L H l
L l L H
C21 LT4-EO Sheet 1/3 I

I Page 16-14
3-274
FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION " CG21 K " Version
Cell Name
LT4
Equivalent Circuit
PA
DA 0 - - - ' - - - - - - - 1 NA
TXGO XGO
--L
TGO
.-------------------------------------------------4
~PB
DB 0-----+-
~NB
, ~PC
DC 0-----+-
~NC
• _________________________________________________ 4
, ~PD
DO 0-----+-
~ND
C21-LT4-EO Sheet 213

Page 16--15
3-275
Cell Name
LT4
(Case1)
----"\
G
o
~--------t~ --------~
P,N
(Case2)
o
,
J
~tso- - t H O -
_tpd_
P,N
C21-LT4-EO Sheet 3/3

Page 16-16
3-276
CMOS Channel/ess Gate Arrays CG21 Series Unit Cell Ubrary
Shift Register Family
Unit Cell Basic

3-279 FS1 4-bit Serial-in Parallel-out Shift Register 18

3-281 FS2 4-bit Shift Register with Synchronous Load 30
3-283 FS3 4-bit Shift Register with Asynchronous Load 34
3-286 SR1 4-bit Serial-in Parallel-out Shift Register with Scan 36
3-277
3-278
FS1 4-bit Serial-in Parallel-out Shift Register 18

!Up Idn
Path
1.281 0.060 1.657 0.039 0.056 4 CKtoO
ooD~
CK OB
OC
00

SO Setup Time tsso 0.4

SO Hold Time tHSO 0.2
Clock I C ~161u tCwt** 3.4

Input Loading Pause I 16 < C ~321u tCWL** 5.0
Pin Name
Factor (Iu) Time I 32 < C ~481u tCWL** 6.4
SO 1
CK 1
multiplier.
Output Driving "The value of ICWL depends on the load(c)

Pin Name
Factor (Iu) connected to the output terminals, OA, OB, OC and 00.
a 16
Function Table
Inputs Outputs
SO CK OA as OC 00
SO J, -SO OAn OSn OCn
NOTE: • SO = H or L
• OAn, OSn and OCn are levels of

OA, as, and OC respectively,
C21 FS1 EO I Sheet 1/2 I

I Page17-1
3-279
Cel/Name
FS1
-----------------------"j-lll
Equivalent Circuit
XCKO
-.L
CKO
-.L
QA aB ac aD
so I
T T
CKO XCKO
CKO XCKO
-.L -.L
T T
XCKO CKO
t bit
--.------------------------------------------~--
CK~CKO
V ~XCKO
ICW tCWL
CK
j
r-
~tSSD IHS~
SD 'I 'I
J~ ~
-tpd-
Q
'"
J~
C21-FS1-EO Sheet 2/2

Page17-2
3-280
FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION I .. CG21K • Version
CelJName Function Number of BC
FS2 4-bit Shift Register with Synchronous Load 30

CelJSymbol Propagation Delay Parameter
tup teln
Path
1.228 0.060 1.657 0.039 0.056 4 CKtoa
PA- -QA
PB- -OB
PC- -OC
PD- r--OD
SD-
CK--<:
L-
Parameter Symbol T}'p (ns)·

Load Setup Time t SL 2.6

Load Hold Time t HL 0.3
P SetuoTime tsp 2.1

Input Loading P Hold Time tHP 0.9
Pin Name
Factor (Iu)
CK 1 Clock I C ~161u teWLu 3.4
SD 1 Pause 116<C<32Iu tCWL** 5.0
L 1 Time I 32 <C ~481u teWl'" 6.4
P 1
Output Driving The values for the worst case operating condition are given by the maximum delay
Pin Name
Factor (Iu) multiplier.
0 16 •• The value of tcWL depends on the load(c)

connected to the output terminals, OA, OB, OC and CD.
Function Table
Inputs Outputs
SD L P CK aA aB ac aD
SD L X ,J, SD aAn aBn aCn
x H P ,J, PA PB PC PD
NOTE: • SD = H or L
• aAn, aBn and aCn are levels of

aA, aB, and ac respectively,
• P represents PA, PB, PC and PD.

I Page17-3
3-281
Cell Name
FS2
PA QA PB PC PO
Equivalent Circuit
so o--l----I 1-1--; )O--+-!-

-'l-r-r-r-r-ri •
.
I
I
CKO
CKO
--L
T T
XCKO CKO
1 bit
--.---------------------------------------------~----
CK~CKO L o----{>o------- XLO
V ~XCKO
tcw
,
tCWl
CK r-
tSSD tH~
so V 'V
1\ JI\
j4-lsp IHP-
p
1\ )
,
tHl
tSl
L
V
J 1\
-tpd-
C21-FS2-EO Sheet 2/2

Page 17-4
3-282
FS3 4-bit Shift Register with Asynchronous Load 34

tup tdn
Path
to KCL 10 KCL KCL2 COR2
1.208 0.064 1.122 0.050 CKtoQ
2.449 0.064 1.848 0.050 L to~
1.076 0.064 1.597 0.050 Pto Q
PA- -OA
PB- -OB
PC- -OC
Po- -00
so-
CK-
L---C

Clock Pulse Widlh tcw 2.5
SO Setup Time tSSD 0.6

Input Loading SO Hold Time tHSD 1.1
Pin Name
Factor (Iu)
P Setup Time tsp 0.3
CK 2
SO 2 P Hold Time tHP 1.4
L 1
p 2
Pin Name
0
Output Driving
Faclor (Iu)
18
III
multiplier.
Function Table
Inputs Outputs
L P SD CK Q
L L X X L
L H X X H
H X L i L
H X H i H

I Page17-5
3-283
eel/Name
FS3
Equivalent Circuit
500------1 FFO FFO FFO FFO
T
CKO XCKO
C21-FS3-EO Sheet 213

Page17-6
3-284
Cell Name
FS3
.......- - Icw - - - o i - - - - I C W H - - - - I
CK
so If
--------' ~'---I----'I"------
I I--Isso-~ HSO-
_ _ _ _ _ _ _""'\ ....-----ILW-----001,..._ _ _ _ __
l
J
p
_ _ _ _ _ _ _ _ _J '--_ _ _ _-+-_-'1"---
- I s p - - " ' * '.... IHP ...

I Page17 7
3-285
FUJITSU CMOS GATE ARRAY UNIT.CELL SPECIFICATION I • CG21K • Version
Cell Nama Function Number of BC
SRt 4-bit Serial-in Parallel-out Shift Register with SCAN 36

!Up tdn
Path
1.729 0.032 1.782 0.034 0.050 7 CKtoQ
r---
D- -OA
CK-
-os
-OC
IH-
-OD
51-
A-
S-<:
'---

Input Loading
Pin Name
Factor (Iu)
D 1
CK 1
IH 1
51 1
A,S 1
Output Driving
Pin Name
Factor (Iu)
Q 36
multiplier.
C21 SR1 EO I Sheet 1/3 I

I Page17--8
3-286
Cell Name
SR1
OA OB OC 00
0 DO 00
SoO SOO
ClK ClK ClK
SI
XClK XClK XClK
ACK ACK ACK ACK
XACK XACK XACK XACK
BCK BCK BCK BCK
XBCK XBCK XBCK XBCK
FFO FFO FFO FFO
ClK XBCK XClK ~----~ ~~-------oOO
---L ---L ---L

DO ~~----~ ~~~-----oSQO
I
XClK BCK ClK
XACK XClK ACK ClK

---L ---L ---L ---L
SOO
I II I BCK
ACK ClK XACK XClK
---L
ClK
CK
IH
XClK IXBCK
A~XACK B~BCK
. L{)o-ACK . L { ) o - XBCK
C21-SR1-EO Sheet 2/3

Page17-9
3-287
eellName
SR1
CK
,1 - - - I c w - - _ I - - - ICWHI--..,f
IJ
J
o ______________J~____~____ _JJI'-------------
or
C21-SR1 EO 1 Sheet 3/31

I Page17-10
3-288
Parity Generator/Selector/Decoder Family
Unit Cell Basic

Parity Generators/Checkers
3-291 PES 5-bit Even Parity Generator/Checker 12
3-292 pas 5-bit Odd Parity Generator/Checker 12
Data Selector
3-297 P24 4-wide 2:1 Data Selector 12
Decoders
3-298 DE2 2:4 Decoder 5
3-299 DE3 3:8 Decoder 15
Selectors
3-304 T26 2:1 Selector 2
3-305 T2C Dual 2:1 Selector 4
3-307 T2D 2:1 Selector 2
3-308 T2E Dual 2:1 Selector 5
3-309 T2F 2:1 Selector 8
3-311 T5A 4:1 Selector 5
3-313 V3A 1:2 Selector 2
3-314 V36 Dual 1:2 Selector 4
Magnitude Comparator
3-315 MC4 4-bit Magnitude Comparator 42
3-289
CG21 Series Unit Cell Library CMOS Channe//ess Gate AtTays
3-290
PES 5-bit Even Parity Generator/Checker 12

!Up IeIn
Palh
1.386 0.032 1.802 0.017 AtoX
1.386 0.032 1.729 0.017 BtoX
2.185 0.032 2.554 0.017 Cto X
AD
Bl
B2
Cl
C2
X
Para meier Svmbol Typ (ns)'
Input loading
A 2
B 2
C 2
Outpul Driving
Pin Name Faclor(lu)
X 36
• Minimum values for lhe Iypical operating condition.
multiplier.
Bl
.......
II
l:input X B2 ...,
Odd L
X
Even H
Cl
....... , ......
C2
II
...,
A
C21 PE5 EO I Sheet 111 I

I Page 20-1
3-291
POS 5-bit Odd Parity Generator/Checker 12

\up Idn
Path
1.393 0.032 1.624 0.017 Ato X
1.512 0.032 1.604 0.017 Bto X
2.211 0.032 2.409 0.017 CtoX
AD
81
82
Cl
C2
X
Input Loading
A 2
8 2
c 2
Output Driving
X 36
multiplier.
:Einput X tr--.
81
Odd H 82
II
tV
Even L
X
tr--.
Cl r-.....
II
C2 1/
C21 POS-EO I Sheet 1/1 I

I Page 20-2
3-292
FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION I • CG21K .. Version
PEB 5-bit Even Parity Generator/Checker 18

tup IeIn
Path
2.033 0.060 2.290 0.039 Ato X
2.079 0.060 2.337 0.039 8to X
2.079 0.060 2.323 0.039 CtoX
2.125 0.060 2.370 0.039 DtoX
Al-
A2-
Bl-
B2-
Cl-
b--x
C2-
01-
02-
Input Loading
A 2
B 2
C 2
0 2
Output Driving
X 18
* Minimum values for the typical operating condidon.
multiplier.
Al II"-
A2
II
Einput X 11/
Odd L Bl II"-
B2
II
Even H 11/
X
Cl
r-..
II
C2 1./
l"-
01
II
02 ,1./
C21 PE8 EO I Sheet 1/1 I

I Page20-3
3-293
Cell Name Function NumbsrolBC
P08 8-bit Odd Parity Generater/Checker 18

tup tdn
Path
1.993 0.060 2.264 0.039 AtoX
2.040 0.060 2.310 0.039 Bto X
2.046 0.060 2.224 0.039 CtoX
2.092 0.060 2.251 0.039 DtoX
A1-
A2-
B1-
B2-
C1-
-x
C2-
01-
02-
Input Loading
A 2
B 2
C 2
0 2
Output Driving
X 18
multiplier.
tr-...
l:input X A1
A2
II
L
......
Odd
B1 Ir-...
Even H
B2
"
IV
r-...
X
C1
II
C2 IV
r-...
01
II
02 I .......
C21 POS-EO I Sheet 1/1 I

I Page 20-4
3-294
PE9 9-bit Even Parity Generator/Checker 22

CellSymbof Propagation Delay Parameter
tup tdn
Path
2.792 0.060 3.016 0.039 AtoX
Al-
A2-
A3-
A4-
AS- p--X
AG-
A7-
AS-
A9-
Input Loading
A 2
Output Driving
X 18
multiplier.
A3
Einput X AS II""'-..
A9
I ..,
Odd L 11./
Even H Al II"-..
A2
II
.., 11./
X
A4 II""'-..
AS
II
..,
AS r-..
II
A7 11./
C21 PE9 EO I Sheet 1/1 I

I Page20-5
3-295
P09 9-bit Odd Parity Generator/Checker 22

tup tdn
Path
2.746 0.060 3.016 0.039 Ato X
Al-
A2-
A3-
M-
AS- -X
A6-
Al-
AS-
A9-
Input Loading
A 2
Output Driving
X 18
multiplier.
A3
:Einput X AS I'""'
A9
II .......
Odd H IV
Even L AI I'""'
A2
II IV
I .......
X
M
r--..
AS
II
I .......
AS
r--..
Al
II
I .......
C21 P09 EO I Sheet 1/1 I

I Page 20-6
3-296
P24 4-wide 2 : 1 Data Selector 12

!Up tdn
Path
0.502 0.032 0.442 0.017 Ato X
0.614 0.032 0.515 0.017 Bto X
0.429 0.032 0.502 0.017 SAtoX
0.528 0.032 0.574 0.017 SBto X
Al-
r--Xl
Bl-
A2-
r - - X2
B2-
A3-
r--X3
B3-
A4-
f--X4
B4-
SA- Parameter Symbol Typ (ns)·
SB-
Input Loading
A 1
B 1
S 4
Output Driving
X 36
multiplier.
SA SB Xn
Al
L L L c--
Xl
H L An Bl
L H Bn -
A2
H H An+Bn 0---
X2
B2
0--
A3
0---
X3
B3
.....
A4
0---
X4
B4
SA- o--
SB-
C21-P24-EO I Sheet 1/1 I

I Page 20-7
3-297
FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION .. CG21K .. Version
CeUName Function Number of BC
DE2 2: 4 Decoder 5
tup teln
Path
0.416 0.060 0.574 0.062 AtoXO
0.469 0.060 0.515 0.062 Ato X1
0.198 0.060 0.238 0.062 Ato X2,X3
0.469 0.060 0.515 0.062 BtoXO
0.152 0.060 0.297 0.062 BtoX1,X3
0.416 0.060 0.574 0.062 BtoX2
'D~
B
XI
X2
X3
Input Loading
A 3
B 3
Output Driving
X 18
multiplier.
Inputs Outputs
A XO
~
~
A B X3 X2 X1 XO
L L H H H L
XI
L H H H L H
H L H L H H
H H L H H H X2
B
-~ X3
C21 DE2 EO I Sheet 1/1 1

I Page 20-8
3-298
DE3 3: 8 Decoder 15
tup tdn
Path
0.759 0.060 0.885 0.084 A to XO-X3
1.287 0.060 1.287 0.084 A to X4-X7
0.706 0.060 0.911 0.084 Bto XO-X3
I--XO 1.234 0.060 1.314 0.084 B to X4-X7
A- I--Xl 0.654 0.060 0.944 0.084 Cto XO-X3
I--X2 1.182 0.060 1.743 0.084 C to X4-X7
I--X3
B-
I--X4
I--X5
c- I--X6
I--X7
Input Loading
A 1
B 1
C 1
Output Driving
X 14
multiplier.
Function Table
Inputs Outputs
A B C XO X1 X2 X3 X4 X5 X6 X7
L L L L H H H H H H H
L L H H L H H H H H H
L H L H H L H H H H H
L H H H H H L H H H H
H L L H H H H L H H H
H L H H H H H H L H H
H H L H H H H H H L H
H H H H H H H H H H L
C21 DE3 EO I Sheet 1/2 I

I Page 20-9
3-299
Cell Name
DE3
Equivalent Circuit
A o-----i X>-~P---------- .......---i

0 - - - 0 XO
0 - - - 0 Xl
Bo--~ X>~P------+-r--i
0 - - - 0 X2
0 - - - 0 X3
0 - - - 0 X4
c o--~ X>~p------+-HH-+-~
0---0 XS
b---o X6
0 - - - 0 X7
C21-DE3-EO Sheet 2/2

Page 20-10
3-300
DE4 2 : 4 Decoder with Enable 8

tup tdn
Path
0.627 0.060 0.772 0.084 GtoX
0.456 0.060 0.588 0.084 AtoX
0.568 0.060 0.601 0.084 BtoX
AD~
B X1
X2
G X3
Input Loading
A 3
B 3
G 1
Output Driving
X 14
multiplier.
G A B X3 X2 X1 XO
A Hl
I
XO
H X X H H H H
L L L H H H L
L
L
L
H
H
L
H
H
H
L
L
H
H
H
'-- R) X1
L H H L H H H
B-~
f--- R) X2
--=n X3
C21 DE4-EO I Sheet 1/1 I

I Page 20-11
3-301
DE6 3 : 8 Decoder with Enable 30

tup tdn
Path
1.611 0.060 3.142 0.039 GtoX
1.525 0.060 1.736 0.039 StoX
Gl- f--XO
G2- f--Xl
G3- f--X2
I--X3
SI-
f--X4
S2-
f--xs
S3-
f--X6
f--X7
Input Loading
G 1
S 1
Output Driving
X 18
multiplier.
Function Table
G1 G2+G3 S3 S2 S1 X7 X6 X5 X4 X3 X2 X1 XO
X H X X X H H H H H H H H
L X X X X H H H H H H H H
H L L L L H H H H H H H L
H L L L H H H H H H H L H
H L L H L H H H H H L H H
H L L H H H H H H L H H H
H L H L L H H H L H H H H
H L H L H H H L H H H H H
H L H H L H L H H H H H H
H L H H H L H H H H H H H
C21 DE6-EO I Sheet 1/2 I

1 Page 20-12
3-302
FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION .. CG21K n Version
Cell Name
DE6
Equivalent Circuit
Gl
> - - - 0 XO
G20-------~~>-~_+----------4_~_4
G30-----+-I
>-----0 Xl
>----0 X2
>---OX3
>---OX4
Sl 0------1 )O.--H-+-I )(>--+--HH-~

>---OX5
S2 0------1 )0------<1-+-1 X>---1-~I--I----1

">-----0 X6
>---OX7
53 0 - - - - - 1 )0.-----+-1 )(>-----''----l
Sheet 2/2
Page 20-13
3-303
T2B 2 : 1 Selector 2
tup tdn
Path
0.277 0.060 0.416 0.039 A.B to X
0.324 0.060 0.522 0.039 StoX
,;0,
82
Parameter 8ymbol Typ (ns)'
Input Loading
A,B 2
8 1
IDII Pin Name
X
Output Driving
Factor (Iu)
18
multiplier.
Inputs Outputs
A B S1 S2 X
A
L H L H H
H H L H L
X
X
L
H
H
H
L
L
H
L E- ~X
L H L L Inhibit
L H H H Inhibit B~
H L L L Inhibit
H L H H Inhibit
81 ~
---y--
82
C21 T2B-EO I Sheet 1/1 I

I Page 20-14
3-304
T2C Dual 2 : 1 Selector 4

tup tdn
Path
0.271 0.060 0.409 0.039 A,8toX
0.357 0.060 0.548 0.039 Sto X
lSI
A1- P---- XO
A2-
B1-
B2- p---- X1
Input Loading
A.B 2
S 2
Output Driving
X 18
multiplier.
Function Table
Inputs Outputs
A1 ,81 A2,82 S1 S2 XO X1
L X L H H H
H X L H L L
X L H L H H
X H H L L L
L H L L Inhibit Inhibit
H L L L Inhibit Inhibit
L H H H Inhibit Inhibit
H L H H Inhibit Inhibit
C21 T2C EO Sheet 1/2 I

I Page 20-15
3-305
Cell Name
T2C
Equivalent Circuit
AI 0---+---1
x>--oxo
A2 0--+_---1
91 0---+---1
X>--OXI
92 0--+----1
51 0---<1------'
52o------~
C21-T2C-EO Sheet 212

Page 20-16
3-306
T2D 2 : 1 Selector 2
tup tdn
Path
0.330 0.069 0.370 0.056 A,B to X
0.357 0.069 0.271 0.056 Sto X
:D-'
81
82
Input Loading
A,B 1
8 1
Output Driving
X 14
multiplier.
Inputs Outputs -=:L

A B S1 S2 X
A
L X L H H
H
X
X
L
X
L
H
H
L
H
H
L
H
L
L
L
L
L
H
Inhibit
r-- r-----o X
B ~
L H H H Inhibit
H L L L Inhibit
H L H H Inhibit 51 -r-
52
C21 T2D EO I Sheet 1/1 I

Page 20-17
3-307
FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION I • CG21K " Version
T2E Dual 2 : 1 Selector 5

tup tdn
Path
0.284 0.060 0.284 0.045 0.062 4 A,BtoX
0.865 0.060 0.858 0.045 0.062 4 Sto X
Al-
p--XO
A2-
Bl-
p.-Xl
B2-
s-
Input Loading
A,B 2
S 1
Output Driving
X 18 • Minimum values for the typical operating condition.

multiplier.
Equivalent Circuit
-----::::L
AI
A2
::::E- k> XO
-----3:
Bl
::::E- -t> XI
B2
S
--r
C21 T2E-EO I Sheet 1/1 ,Y>
I Page 20-18
3-308
Cel/Name Function NumberolBC
T2F 2 : 1 Selector 8
\up tdn
Path
0.284 0.060 0.284 0.045 0.062 4 A,B,C,Dlo X
0.865 0.060 0.858 0.045 0.062 4 Sio X
Al-
p...-XO
A2-
Bl-
p...-Xl
B2-
Cl-
p...-X2
C2-
01-
p...-X3
02-
S-
Input Loading
A,B,C,D 2
S 1
I
Output Driving
X 18
multiplier.
C21 T2F EO I Sheet 1/2 I

I Page 20-19
3-309
Cell Name
T2F
Equivalent Circuit
X>--Oxo
) 0 - - 0 Xl
X>--OX2
X>--OX3
C21-T2F-EO Sheet 2/2

Page 20-20
3-310
T5A 4 : 1 Selector 5
!Up tdn
Path
0.528 0.087 0.528 0.073 A.Blo X
0.528 0.087 0.442 0.073 S1-4 to X
0.297 0.087 0.284 0.073 S5-6to X
Al-
11 1,
2
A2-
Bl-
p--x
B2-
r1 Parameter Symbot Typ (ns) "
Input Loading
A.B 1
S 1
Output Driving
X 9
" Minimum values for the typical operating condition.
multiplier.
Function Table
Inputs Output
A1 A2 B1 B2 S1 S2 S3 S4 S5 S6 X
L L H L H H
H L H L H L
L H L L H H
H H L L H L
L L H H L H
H L H H L L
L H L H L H
H H L H L L
A 1.'A2 to S1 =S2 or 85=86 Inhibit

B1.,B2 to 83=84 or 85=86 Inhibit
A1.A2;tB1.B2 or 85=86 Inhibit
C21 T5A EO I 8heet 1/2 I

1 Page 20-21
3-311
eel/Name
T5A
Equivalent Circuit
Alo---~ ~--4-~
A2o---~ ~--4-~
SI 0-----------'
S20-----------------~
t-----ox
S40------------------..
S3 0-----------,
Bl o---~ )0----1--;
B2o---~ xr--~_4
S5O---------------------------~
~o-------------------------------------~
C21-T5A-EO Sheet 212

Page 20-22
3-312
V3A 1 : 2 Selector 2
\Up teln
Path
0.330 0.069 0.370 0.056 Ato X
0.291 0.069 0.238 0.056 StoX
AD~
51
S2 XI

Input Loading
A 1
5 1
Output Loading
X 1
Output Driving
Pin Name Factor (Iu) • Minimum values lor the typical operating condition.
X 14 The values for the worst case operating condition are given by the maximum delay
multiplier.
Inputs Outputs
A S1 S2 XO X1
--=:L
L L L Inhibit XO
L
H
L H
L X
H
H
X
A o----{)c>-- r
L H H XI
Inhibit
H L L
51
-r
H H L X L
52 ....
H L H L X
H H H Inhibit
C21-V3A EO I Sheet 1/1 I

1 Page 20-23
3-313
Cell Name Function . Number of BC
V38 Dual 1 : 2 Selector 4

IUp Idn
Path
0.337 0.069 0.403 0.056 A,Bto X
0.304 0.069 0.258 0.056 StoX
'D~
B
SI
S2
XI
X2
X3

Input Loading
A 1
B 1
S 2
Output Loading
X 1
Output Driving
Pin Name Factor (Iu) • Minimum values for the typical operating condition.
X 14 The values for !he worst case operating condition are given by !he maximum delay
multiplier.

I-l
,~+~
Inputs Outputs
XO
A,B 81 82 XO, X2 X1, X3
+Br-=r:
L L L Inhibit
L H L X H
XI
L L H H X
,~+~
L H H
Inhibit
X2
H L L
+B
H H L X L
H L H L X
X3
H H H Inhibit
SI ~
-r
S2
C21-V3B EO I Sheet 1/1 I

I Page 20-24
3-314
MC4 4-bit Magnitude Comparator 42

!Up tdn
Path
2.792 0.106 3.340 0.039 0.050 4 AtoOS
2.845 0.106 3.280 0.039 0.050 4 BtoOS
1.248 0.106 1.472 0.039 0.050 4 IEtoOS
B3- 1.023 0.106 1.274 0.039 0.050 4 IGtoOS
A3 B2 = = 2.739 0.106 3.452 0.039 0.050 4 AtoOG
A2Bl== 2.785 0.106 3.393 0.039 0.050 4 BtoOG
AI 00== 1.188 0.106 1.578 0.039 0.050 4 IEtoOG
AO - - 1.129 0.106 1.221 0.039 0.050 4 IStoOG
3.003 0.060 2.304 0.039 0.056 4 AtoOE
IG- -OG 2.950 0.060 2.350 0.039 0.056 4 BtoOE
IE- I---OE 1.129 0.060 0.759 0.039 0.056 4 IEtoOE
15- 1---05
Input Loading
A 3
B 3
IE 1
IG 1
15 1
Output Driving
OE 18
OG 10 • Minimum values lor the typical operating condition.
05 10 The values lor the worst case operating condition are given by the maximum delay
multiplier.
Function Table
Comparing Inputs Cascading Inputs Outputs

IG IS IE OG OS OE
A3,B3 A2,B2 A1, B1 AO,BO (A>B) (A<B) (A=B) (A>B) (A<B) (A=B)
A3>B3 X X X X X X H L L
A3<B3 X X X X X X L H L
A3=B3 A2>B2 X X X X X H L L
A3=B3 A2<B2 X X X X X L H L
A3=B3 A2=B2 A1>B1 X X X X H L L
A3=B3 A2=B2 A1<B1 X X X X L H L
A3=B3 A2=B2 A1=B1 AO>BO X X X H L L
A3=B3 A2=B2 A1=B1 AO<BO X X X L H L
A3=B3 A2=B2 A1=B1 AO=BO X X H L L H
A3=B3 A2=B2 A1=B1 AO=BO H L L H L L
A3=B3 A2=B2 A1=B1 AO=BO L H L L H L
A3=B3 A2=B2 A1=B1 AO=BO H H L L L L
A3=B3 A2=B2 A1=B1 AO=BO L L L H H L
C21 MC4-EO I Sheet 1/2 I

Page 20-25
3-315
FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION 1 .. CG21K" Version
Cell Name
MC4 if-
A3
B3~
r-- w
if-
1>- -I
1
Equivalent
Circuit
r-
l..-' OG
1""'\
~~~
:~
~
A2~
B2 if- f-<
~
f--- P-
c--
IS l/
1""'\
IE - OE
~f--
1--1,...1
IG~
1""'\
I--
:~
P-
A1
B1 ~
I l/
--,
1,...1 OS
1""'\
v~
~
AO~
BO~
C21 MC4 EO I
1
Sheet 2/4 I
9 1
I Page 20-26
3-316
Bus Driver Family
Unit Cell Basic


3-317
CG21 Series Unit Cell Ubrary CMOS Channel/ess Gate Arrays
3-318
811 1-bit Bus Driver 5

tup tdn
Path
0.759 0.028 0.759 0.023 AtoX
0.858 0.028 0.858 0.023 CtoX
~=o-~
Input Loading
Pin Name
Faclor(lu)
A 1
C 1
Output Loading
Pin Name
Factor (Iu)
X 1
Output Driving
Pin Name
Factor (Ju)
multiplier.
Equivalent Circuit
Co
---L
AO XO
T
Co
C h-{»-- Co
CO
C21 811 EO I Sheet 1/1 I

I Page 18-1
3-319
FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION I· CG21K" Version

\Up !dn
Path
0.759 0.028 0.759 0.023 AtoX
1.419 0.028 1.254 0.023 CtoX
'"=[J=~
Al
C
Xl
Input Loading
Pin Name
Factor (Iu)
A 1
C 1
Output Loading
Pin Name
Factor (Iu)
X 1
Output Driving
Pin Name
Factor (Iu)
multiplier.
Equivalent Circuit
Co
; •..........•. :.:I:..: . :
I I
I I
I I
AO I I
XO
I I
I I
:............. T-.!
Co
.------------------~
Al---: :---Xl
._---------------_ ..
C f>L{)o--- Co
CO

I Page 18-2
3-320
FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION I • CG21 K" Version

!Up Idn
Path
0.759 0.028 0.759 0.023 Alo X
2.310 0.028 1.914 0.023 CloX
AO- -XO
Al- - Xl
A2- -X2
A3- -X3
C --<
Input Loading
Pin Name
Factor (Iu)
A 1
C 1
Output Loading
Pin Name
Factor (Iu)
X 1
Output Driving
Pin Name
Factor (Iu)
X 36
multiplier.
Equivalent Circuit
Co
;, -------------:..:I:.: -:,
, ,
AO ,,
0 0
,,
0 Xo
,
:-------------T-!
CO
.------------------.
Al---: :---Xl
,------------------ .
. ------------------.
A2---: : - - - X2
------------------..
.,-----------------_
A3---: ' - , - - - X3
,-----------------_.
C
~co
CO
C21 841 EO I Sheet 111 I

I Page 18-3
3-321
B81 8-bit Bus Driver 33

tup tdn
Path
0.759 0.028 0.759 0.023 Ato X
4.422 0.028 3.630 0.023 Cto X
AO- -XO
Al- : - - Xl
A2- : - - X2
A3- f---- X3
A4- f---- X4
A5- f---- X5
A6- f---- X6
A7- ' - - X7
C --<:
Input Loading
Pin Name
Factor (Iu)
A 1
C 1
Output Loading
Pin Name
Factor (Iu)
X 1
Output Driving
Pin Name
Factor (Iu)
X 36
multiplier.
Equivalent Circuit
Co
;, -------------:.±.: -:,
,, ,,
AO ,
,
,
,,, XO
:-------------T-:
CO
Al - - - - : ======= ===== === ===:--- Xl

A2 - - - - : ==================:--- X2
A3 ----:=========::::::::::--- X3
A4 ----:==================:--- X4
A5 ----:==================:--- X5
A6 ----:==================:--- X6
A7 - - - - : ==================:--- X7
C
~~ CO
C21 881 EO Sheet 1/1 I

I Page 18--4
3-322
812 1-bit Block Bus Driver 7

!Up tdn
Path
0.759 0.019 1.287 0.011 Ato X
0.957 0.019 1.617 0.011 Cto X
:=O-~
Input loading
Pin Name
Factor (Iu)
A 2
C 1
Output loading
Pin Name
Factor (Iu)
X 2
Output Driving
Pin Name
Factor (Iu)
X 72
The values for the worst case operating conditlon are given by the maximum delay
multiplier.
Equivalent Circuit Note:

This cell is for inter-block bus under chip level.
AO
Co
I I ,~
l xo
·1
A
Co
I
V
C
~co
CO

1 Page 18-5
3-323
Cell Name FunctIon Number 01 SC

!Up teln
Path
to KCL • to KCL KCL2 CDR2
0.759 0.019 1.287 0.011 Ato X
1.056 0.019 1.848 0.Q11 CtoX
M=O=~
A1
C
XI
Input loading
Pin Name
Factor (Iu)
A 2
C 1
Output Loading
Pin Name
Factor (Iu)
X 2
Output Driving
Pin Name
Factor (Iu)
X 72
multiplier.
Equivalent Circuit Note:

This cell is lor inter-block bus under chip level.
AO
Co
I I ,~
4 xo
Co ......
'1
Al-1 r- X1
C
~co
CO
C21-B22 EO I Sheet 111 I

I Page 18-6
3-324
Cell Nama Function Number of BC

\up !dn
Path
0.759 0.019 1.287 0.011 Ato X
1.320 0.019 2.046 0.011 Cto X
AO- r-- XO
Al- I--- Xl
A2- I--- X2
A3- I--- X3
C --<
Input Loading
Pin Name
Faclor (Iu)
A 2
C 1
Output Loading
Pin Name
Factor (Iu)
X 2
Output Driving
Pin Name
Factor (Iu)
X 72
multiplier.
Equivalent Circuit Note :

This cell is for inter-block bus under chip level.
AO
Co
I I
:~
Co
Lf v
:~
XO
Al ---1 ~Xl
A2 ---1 ~X2
A3 ---1 ~X3
C ~co
CO
C21 B42-EO I Sheet 1/1 I

T Page 18-7
3-325
CG21 Series Unit Cell Ubrary CMOS Channe//ess Gate Atrays
3-326
Clip Cell Family
Unit Cell Basic

3-329 zoo 0 Clip o

3-330 Z01 1 Clip o
3-327
CG21 Series Unit Cell Library CMOS Channe/less Gate Arrays
IIDI
3-328
ZOO o Clip 0
!Up teln
Path
~
Input Loading
Pin Name
Factor (Iu)
Output Driving
Pin Name
Factor (Iu)
X 200
multiplier.
C21 ZOO EO I Sheet 1/1 I

I Page 19-1
3-329
Z01 1 Clip 0
!up tdn
Path
'Y X
Input Loading
Pin Name
Factor (Iu)
Output Driving
Pin Name
Factor (Iu)
X 200
multiplier.
C21-Z01-EO I Sheet 1/1 I

I Page 19-2
3-330
1/0 Buffer Family
Unit Cell Basic

3-335 11B Input Buffer (Inverter) 5
3-336 11BU 11 B with Pull-up Resistance 5
3-337 11BD 11B with Pull-down Resistance 5
3-338 12B Input Buffer (True) 4
3-339 12BU 12B with Pull-up Resistance 4
3-340 12BD 12B with Pull-down Resistance 4
3-341 IKB Clock Input Buffer (Inverter) 4
3-342 IKBU IKB with Pull-up Resistance 4
3-343 IKBD IKB with Pull-down Resistance 4
3-444 IKC CMOS Interface Clock Input Buffer (Inverter) 4
3-445 IKCU IKC with Pull-up Resistance 4
3-446 IKCD IKC with Pull-down Resistance 4
3-347 ILB Clock Input Buffer (True) 8
3-348 ILBU ILB with Pull-up Resistance 8
3-349 ILBD ILB with Pull-down Resistance 8
3-350 ILC CMOS Interface Clock Input Buffer (True) 6
3-351 ILCU ILC with Pull-up Resistance 6
3-352 ILCD ILC with Pull-down Resistance 6
3-353 11C CMOS Interface Input Buffer (Inverter) 5
3-355 11CD 11C with Pull-down Resistance 5
3-356 12C CMOS Interface Input Buffer (True) 4
3-358 12CD 12C with Pull-down Resistance 4
3-359 11S Schmitt Trigger Input Buffer (CMOS Type, Inverter) 8
3-361 11SD 11S with Pull-down Resistance 8
3-362 12S Schmitt Trigger Input Buffer (CMOS Type, True) 8
3-364 12SD 12S with Pull-down Resistance 8
3-365 11R Schmitt Trigger Input Buffer (TTL Type, Inverter) 8
3-366 11RU 11 R with Pull-up Resistance 8
3-367 11RD 11 R with Pull-down Resistance 8
3-368 12R Schmitt Trigger Input Buffer (TTL Type, True) 8
3-369 12RU 12R with Pull-up Resistance 8
3-370 12RD 12R with Pull-down Resistance 8
3-371 01Bl Output Buffer (Inverter) 3
3-372 01BF2 Outpu1 Buffer (Inverter) 3
3-373 01L3 Power Output Buffer (Inverter) 3
3-374 01Rl Output Buffer (Inverter) with Noise Limit Resistance 5
3-375 01RF2 Output Buffer (Inverter) with Noise Limit Resistance 5
3-376 01S3 Power Output Buffer (Inv~rter) with Noise Limit
Resistance 5
3-377 02Bl Output Buffer (True) 3
3-378 02BF2 Output Buffer 3
3-379 02L3 Power Output Buffer (True) 3
3-380 02Rl Output Buffer (True) with Noise Limit Resistance 4
3-381 02RF2 Output Buffer with Noise Limit Resistance 4
1. IOL=3.2 mA
2. IOL=8 mA
3. IOL= 12 mA
3-331
CG21 Series Unit CeD Library CMOS Channe/Jess Gate Arrays
UnH Cell Basic

3-382 02S3 Power Output Buffer (True) with Noise Limit Resistance 4
3-383 04T1 3-state Output Buffer (True) 6
3-384 O4TF2 3-state Output Buffer (True) 6
3-385 O4W3 Power 3-state Output Buffer (True) 6
3-386 O4R1 3-state Output Buffer (True) with Noise Limit
Resistance 5
3-387 O4RF2 3-state Output Buffer (True) with Noise Limit
Resistance 5
3-388 O4S3 Power 3-state Output Buffer (True) with Noise Limit
Resistance 5
3-389 H6T1 3-state Output and Input Buffer (True) 8
3-390 H6TU H6T with Pull-up Resistance 8
3-392 H6TF2 3-state Output and Input Buffer (True) 8
3-394 H6TF02 H6TF with Pull-down Resistance 8
3-395 H6W3 Power 3-state Output and Input Buffer (True) 8
3-398 H6C1 3-state Output and CMOS Interface Input Buffer
(True) 8
3-399 H6CU1 H6C with Pull-up Resistance 8
3-400 H6C01 H6C with Pull-down Resistance 8
3-401 H6CF2 3-state Output and CMOS Interface Input Buffer 8
3-404 H6E3 Power 3-state Output and CMOS Interface Input
Buffer (True) 8
3-407 H6S 1 3-state Output and Schmitt Trigger Input Buffer
(CMOS Type, True) 12
3-408 H6SU1 H6S with Pull-up Resistance 12
3-409 H6S0 1 H6S with Pull-down Resistance 12
3-410 H6R1 3-state Output and Schmitt Trigger Input Buffer
(TTL Type, True) 12
3-411 H6RU1 H6R with Pull-up Resistance 12
3-412 H6R01 H6R with Pull-down Resistance 12
3-413 H8T1 3-state Output with Noise Limit Resistance and
3-414 H8TU1 H8T with Pull-up Resistance 9
3-416 H8TF2 3-state Output with Noise Limit Resistance
and Input Buffer True) 9
3-418 H8TF02 H8TF with Pull-down Resistance 9
3-419 H8WS Power 3-state Output with Noise Limit Resistance and
1. IOL=3.2 rnA
2. IOL=8 rnA
3. IOL= 12 rnA
3-332
1/0 Buffer Family (Continued)
Unit Cell BaSic

3-421 H8WOS H8W with Pull-down Resistance 9
3-422 H8C1 3-state Output Buffer with Noise Limit Resistance
3-423 H8CU 1 H8C with Pull-up Resistance 9
3-424 H8C01 H8C with Pull-down Resistance 9
3-425 H8CF2 3-state Output Buffer with Noise Limit Resistance
3-428 H8E3 Power 3-state Output Buffer with Noise Limit
Resistance and CMOS Interface Input Buffer (True) 9
3-431 H8S 1 3-state Output and Schmitt Trigger Input Buffer
(CMOS Type, True) with Noise Limit Resistance 13
3-432 H8SU1 H8S with Pull-up Resistance 13
3-433 H8S0 1 H8S with Pull-down Resistance 13
3-434 H8R1 3-state Output and Schmitt Trigger Input Buffer
(TTL Type, True) with Noise Limit Resistance 13
3-435 H8RU1 H8R with Pull-up Resistance 13
3-436 H8R01 H8R with PUll-down Resistance 13
1. IOl=3.2 rnA
2. IOl=8mA
3. IOl= 12 rnA
3-333
CG21 Series Unit Cell Library CMOS Channelless Gate AITaYs
3-334
Cell Nama Function Numbarof BC
118 Input Buffer (Inverter) 5

tup tdn
Path
0.845 0.014 0.812 0.017 XtolN
X-{:>o-IN
Input Loading
Output Driving
IN 36
multiplier.
C21 11B-EO Sheet 1/1 J

I Page 21 1
3-335
11BU with Pull-up Resistance
5
!Up !dn
Path
0.845 0.014 0.812 0.017 XtolN
X-{:>o--IN
Input Loading
IDI Pin Name

Output Driving
Factor (Iu)
IN 36
multiplier.
C21 11BU EO I Sheet 1/1 I

I Page 21 2
3-336
1180 with Pull-down Resistance
5
!Up IeIn
Path
0.845 0.014- 0.812 0.017 XtotN
X~IN
Input Loading
Output Driving
IN 36
multiplier.
C21 11 BD-EO I Sheet 1/1 I

I Page 21-3
3-337
Cell Name Function Number of Be
128 Input Buffer (True) 4

!Up Idn
Path
0.561 0.014 0.970 0.017 XtolN
X-C>--IN
Input Loading
,
Output Driving
IN 36
multiplier.
C21 12B-EO I Sheet 1/1 I

I Page 21-4
3-338
Cell Nama Function NumberolBC
12BU with Pull-pu Resistance
\up tdn
Path
0.561 0.014 0.970 0.017 Xto IN
X-{>-IN
Input Loading
Output Driving
Pin Nama Factor (Iu)
IN 36
multiplier.
C21 12BU EO I Sheet 1/1 I

I Page 21-5
3-339
1280 with Pull-down Resistance
tup !dn
Path
0.561 0.014 0.970 0.017 Xto IN
X-[:>--IN
Input Loading
Output Driving
IN 36
The values lor the worst case operating condilion are given by the maximum delay
multiplier.
C21 12BD-EO I Sheet 1/1 I

I Page21-6
3-340
IKB Clock Input Buffer (Inverter) 4

Cell Symbol Propaaation Delay Parameter
\Up \dn
Path
1.540 0.004 1.020 0.004 XtoCI
X -{::>o-- CI
Parameter Symbol Typ (nsl'
Input loading
Pin Name Factor (luI
Output Driving
CI 200
multiplier.
C21 IKB EO I Sheet 1/1 I

I Page 21-7
3-341
IKBU with Pull-up Resistance 4
tup teln
Path
1.540 0.004 1.020 0.004 Xto CI
x-{::>o- CI
Input Loading
Output Driving
CI 200
multiplier.
C21 IKBU EO I Sheet 1/1 I

I Page 21-8
3-342
FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION I . CG21K .. Version
Clock Input Buffer (Inverter) 4
IKBD with Pull-down Resistance
tup tdn
Path
1.540 0.004 1.020 0.004 XtoCI
x-{::>o- CI
Input Loading
Output Driving
CI 200
• Minimum values for the typical operating ccndition.
multiplier.
C21 IKBD EO I Sheet 1/1 I

I Page 21-9
3-343
IKG CMOS Interface Clock Input Buffer (Inverter) 4

!Up tdn
Path
1.310 0.004 0.980 0.004 XtoCI
x-[:>o-- CI
Input Loading
Output Driving
CI 200
The values for the worst case operating cond~ion are given by the maximum delay
multiplier.
C21 IKC EO I Sheet 1/1 I

I Page 21-10
3-344
FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION 1 • CG21K • Version
Cel/Nama Function Number 01 BC
CMOS Interface Clock Input Buffer (Inverter) 4
IKCU with Pull-up Resistance
!Up tdn
Path
1.310 0.004 0.980 0.004 XtoCI
X-{:>o-CI
Input Loading
,
Output Driving
Pin Nama Faclor(lu)
CI 200
multiplier.
C21-1KCU EO I Sheet 1/1 I

I Page 21-11
3-345
CMOS Interface Clock Input Buffer (Inverter)
IKeD 4
\up tdn
Path
1.310 0.004 0.980 0.004 Xto CI
x-{)x>-- CI
Input Loading
Output Driving
CI 200
multiplier.
C21 IKCD-EO I Sheet 1/1 I

I Page 21-12
3-346
FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION I • OG21K • Version
ILB Clock Input Buffer (True) 8

!Up tdn
Path
0.560 0.004 1.330 0.004 XtoCI
X--t>--CI
Input Loading
Output Driving
CI 200
multiplier.
C21 ILB-EO I Sheet 1/1 I

I Page 21-13
3-347
Cell Name Function .Number of BC
Clock Input Buffer (True) 8
ILBU with Pull-up Resistance
\Up teln
Path
0.560 0.004 1.330 0.004 XloCI
X-[::>-CI
Input Leading
Output Driving
Pin Name Fac\or(lu)
CI 200
• Minimum values for the typical operating condidon.
multiplier.
C21-ILBU EO I Sheel1/1 I
I Page 21-14
3-348
fLBD with Pull-down Resistance 8
tup tdn
Path
0.560 0.004 1.330 0.004 XtoCI
X-[:>-CI
Input Loading
Output Driving
CI 200
multiplier.
C21 ILBD-EO I Sheet 1/1 I

I Page 21-15
3-349
fLC CMOS Interface Clock Input Buffer (True) 6

\Up teln
Path
0.880 0.004 1.550 0.004 XtoCI
X-[:::>-CI
Input Loading
Output Driving
CI 200
multiplier.
C21 ILC EO I Sheet 111 I

I Page 21-16
3-350
CMOS Interface Clock Input Buffer (True)
ILeU 6
\Up teln
Path
0.880 0.004 1.550 0.004 XtoCI
X-[:>--CI
Input loading
Output Driving
CI 200
• Minimum values for the typicaf operating condition.
multiplier.
C21 ILCU EO I Sheet 1/1 I

I Page 21-17
3-351
CMOS Interface Clock Input Buffer (True)
fLCD with Pull-down Resistance
6
\Up !dn
Path
0.880 0.004 1.550 0.004 XtoCI
X-[:>-CI
Input loading
Pin Name Fac\or(lu)
Output Driving
Pin Name Fac\or(lu)
CI 200
The values for the worst case operating conditiOn are given by the maximum delay
multiplier.
C21 ILCD-EO I Sheet 1/1 I

I Page 21-18
3-352
ftC CMOS Interface Input Buffer (Inverter) 5

tup tdn
Path
0.387 0.014 0.210 0.017 XtolN
X -(::>0-- IN
Input Loading
Pin Name
Output Driving
Factor (Iu)
III
IN 36
multiplier.
C21 11C EO I Sheet 1/1 I

I Page 21-19
3-353
CMOS Interface Input Buffer (Inverter) 5
11eU with Pull-up Resistance
!Up tdn
Path
0.387 0.014 0.210 0.017 Xto IN
X ---{:><>- CI
Parameter Symbol Typ Ins)·
Input Loading
Pin Name Factorllu)
Output Driving
Pin Name Factorllu)
IN 36
multiplier.
C21 11CU-EO I Sheet 1/1 I

I Page21-20
3-354
CMOS Interface Input Buffer (Inverter) 5
/1eD with Pull-down Resistance
\up teln
Path
0.387 0.014 0.210 0.017 XtolN
X -(::>0-- IN
Input loading
Output Driving
Pin Name Fac\or(lu)
IN 36
Tha values for the worst case operating condition are given by the maximum delay
multiplier.
C21 11CD-EO I Sheet 1/1 I

1 Page 21-21
3-355
Cell Name FunctIon Number 01 BC
12C CMOS Interface Input Buffer (True) 4

!Up Idn
Path
0.489 0.014 0.706 0.017 XtolN
X-[:>--IN
Input loadIng
Output DrIving
PIn Name Factor (Iu)
IN 36
multiplier.
C21-12C EO I Sheet 1/1 I

I Page 21-22
3-356
FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION I • Cl;;21K • Version
12CU with Pull-up Resistance (True) 4
tup tdn
Path
0.489 0.014 0.706 0.017 Xto IN
X~IN
Input loading
Output Driving
IN 36
The values for the worst case operating condition ere given by the maximum delay
multiplier.
C21 12CU EO I Sheet 111 I

I Page 21-23
3-357

12CD with Pull-down Resistance ('Jrue)
4
tup teln
Path
0.489 0.014 0.706 0.017 XtolN
X--{>-IN
Input Loading
Pin Name Fac\or(lu)
DI Pin Name
Output Driving
Factor (Iu)
IN 36
multiplier.
C21 12CD-EO I Sheet 1/1 I

I Page 21-24
3-358
FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION .. CG21K .. Version
11S (CMOS Type, Inverter) 8
!Up tdn
Path
2.059 0.060 1.419 0.039 Xlo IN
X~IN
Input Loading
Output Driving
IN 18
The values for the worst case operating condiflon are given by the maximum delay
multiplier.
C21 118-EO I Sheet 1/1 I

I Page 21-25
3-359
11SU (CMOS Type, Inverter) with Pull-up Resistance 8
!Up !dn
Path
2.059 0.060 1.419 0.039 Xto IN
X~IN
Input Loading
Output Driving
IN 18
multiplier.
C21 11SU EO I Sheet 1/1 I

I Page 21-26
3-360
I1SD (CMOS Type, Inverter) with Pull-down Resistance 8
!Up tdn
Path
2.059 0.060 1.419 0.039 XtolN
X~IN
Input Loading
Output Driving
IN 18
multiplier.
C21-11SD-EO I Sheet 1/1 I

r Page 21-27
3-361
12S (CMOS Type, True) 8
\up tdn
Path
1.314 0.060 1.630 0.045 XlolN
X~IN
Input Loading
III Pin Name

Output Driving
Factor (Iu)
IN 18
multiplier.
C21 128-EO Sheet 1/1 I

I Page 21 28
3-362
FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION I • CG21K .. Version
12SU (CMOS Type, True) with Pull-up Resistance 8
tup tdn
Path
1.314 0.060 1.630 0.045 XtolN
X~IN
Input Loading
Output Driving
IN 18
The values for the worst case operating conditiOn are given by the maximum delay
multiplier.
C21 12SU-EO I Sheet 1/1 I

I Page 21-29
3-363
12SD (CMOS Type, True) with Pull-down Resistance 8
tup tdn
Path
1.314 0.060 1.630 0.045 XtolN
X~IN
Input loading
Output Ddvlng
IN 18
multiplier.
C21 12SD-EO J Sheet 1/1 I

I Page 21-30
3-364
11R (TTL Type, Inverter) 8
tup tdn
Path
2.370 0.060 1.248 0.039 Xlo IN
X~IN
Parameter Symbol Typ (n.)·
Input loading
Output Driving
IN 18
• Minimum value. lor the typical operating condition.
multiplier.
C21 11R EO I Sheel1/1 I

I Page 21-31
3-365
11RU (TTL Type, Inverter) with Pull-up Resistance 8
!Up teln
Path
2.370 0.060 1.248 0.039 Xto IN
X~IN
Input Loading
Output Driving
IN 18
multiplier.
C21 11RU EO I Sheet 111 I

I Page 21-32
3-366
11RD (TIL Type, Inverter) with Pull-down Resistance 8
IUp tdn
Path
2.370 0.060 1.248 0.039 XtolN
X~IN
Input Loading
Output Driving
IN 18
The values for the worst case operating condir.on are given by the maximum delay
multiplier.
C21 11RD EO Sheet 1/1 I

I Page 21-33
3-367
Call Name Function Number 01 BC
12R (TTL Type, True) 8
CenSymbol Propagation Delay Parameter
IUp Idn
Palll
1.182 0.060 1.967 0.062 Xto IN
X~IN
Input Loading
Output Driving
IN 18
• Minimum values lor the typical operating conation.
The values for lIIe worst case operating oondition are given by !he maximum delay
multiplier.
C21 12R-EO I Sheet 1/1 I

I Page 21-34
3-368
12RU (TIL Type, True) with Pull-up Resistance 8
tup tdn
Path
1.182 0.060 1.967 0.062 XtolN
X~IN
Input Loading
Output Driving
IN 18
multiplier.
C21 12RU EO I Sheet 1/1 I

1 Page 21-35
3-369
12RD (TTL Type, True) with Pull-down Resistance 8
!Up teln
Path
1.182 0.060 1.967 0.062 XtolN
X~IN
Input Loading
Output Driving
IN 18
multiplier.
C21-12RD-EO I Sheet 1/1 I

I Page 21-36
3-370
018 Output Buffer (Inverter) 3

tup tdn
Path
0.790 0.028 1.060 0.053 OTto X
(2.47) (4.24)
OT--(>-X
Input Loading
OT 2
Output Driving

multiplier.

C21 01B-EO I Sheet 1/1 I

1 Page 21-37
3-371
01BF Output Buffer (IOL=8mA. Inverter) 4

IUp Idn
Path
0.830 0.028 1.070 0.040 OTto X
(2.51) (3.47)
OT-l>-X
Input loading
OT 2
Output Driving

multiplier.

C21-01BF EO I Sheet 111 I

I Page 21-38
3-372
FWITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION I • CG21K • Version
01L Power Output Buffer (Inverter) 3

CellSymbcl Propallatlon Delay Parameter
tup tdn
Path
0.900 0.020 1.240 0.026 OTto X
(2.10) (2.80)
OT-(>--X
Parameter Symbol Typ (nsl"
Input loading
OT 2
Output Driving
• Minimum values for the typicaf operating condition.

multiplier.

C21-01L EO I Sheet 1/1 I

I Page 21-39
3-373
Cell Name Funcdon Number of BC
Output Buffer (Inverter)
01R with Noise Limit Resistance 5
\Up teln
Path
1.730 0.036 4.540 0.081 OTto X
(3.89) (9.40)
OT-{>-X
Input Loading
OT 1
HI Pin Name
Output Driving
Factor (Iu)

multiplier.
Note: 1. The unit of KCL is nslpF.

C21-01R EO I Sheet 1/1 I

TPage 21-40
3-374
Output Buffer (I0L=8mA. Inverter)

01RF with Noise Limit Resistance
5
!Up tdn
Path
1.780 0.036 5.690 0.048 OTtoX
(3.94) (8.57)
OT--[>-X
Input Loading
OT 1
Output Driving

The values for the worst case operating condifion are given by the maximum delay
multiplier.

C21 01RF EO Sheet 1/1 I

1 Page 21-41
3-375
018 with Noise Limit Resistance 5
\up IeIn
Path
2.040 0.024 6.720 0.040 OTto X
(3.48) (9.12)
OT-[>-X
Parameler Symbol Typ(ns)'
Inpul loading
Pin Name Faclor(lu)
OT 1
OUlpul Driving
Pin Name Faclor(lu)

The values for the worSI case operaling condilion are given by the maximum delay
multiplier.
Note: 1. The unit of KCLis nS/pF.

C21 01S EO I Sheet 1/1 I

I Page 21-42
3-376
FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION .. CG21K • Version
028 Output Buffer (True) 3

!Up tdn
Path
0.500 0.028 0.820 0.053 OTto X
(2.18) (4.00)
OT--[>-X
Input Loading
OT 6
Output Driving

The values for the worst case operating condition ara given by the maximum delay
multiplier.

C21-02B-EO I Sheet 1/1 I

I Page 21-43
3-377
02BF Output Buffer (IOL=8mA, True) 3

!Up tdn
Path
0.560 0.048 0.850 0.040 OTto X
(2.24) (3.25)
OT-f>-X
Input Loading
OT 6
Output Driving
Pin Name Faclor(lu)

multiplier.

C21-02BF EO I Sheet 1/1 I

I Page 21-44
3-378
Cel/Name I Function Number-olBC
02L I Power Output Buffer (True) 3

I
!Up !dn
Path
0.&40 0.020 1.020 0.026 OTto X
(1.84) (2.58)
OT-{>-X
Input Loading
OT 6
Output Driving

The values for the worst case operating conditibn are given by the maximum delay
multiplier.

C21-02L EO I Sheet 1/1 I

I Page 21-45
3-379
02R with Noise Limit Resistance
4
CeJlSymbol Propagation Delay Parameter
!Up tdn
Pam
1.510 0.036 4.400 0.081 OTto X
(3.67) (9.26)
OT--t>-X
Input Loading
OT 2
Output Driving

multiplier.

2. Output load capacitance of 60 pF is used for Fujitsu'S logic simulation.
C21-02R EO I Sheet 1/1 I

I Page 21-46
3-380
Output Buffer (IOL=8mA. True)
02RF with Noise Limit Resistance 4
tup tdn
Path
1.570 0.036 5.600 0.048 OTtoX
(3.73) (8.48)
OT-{>-X
Input Loading
OT 2
Output Driving

multiplier.

C21 02RF EO I Sheet 1/1 I

I Page 21-47
3-381
028 with Noise Limit Resistance
4
\up tdn
Path
1.820 0.024 6.560 0.040 OTto X
(3.26) (8.96)
OT---{>-X
Input loading
OT 2
Output Driving

multiplier.

C21 02S-EO I Sheet 1/1 I

I Page 21-48
3-382
FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION " CG21K • Version
04T Tri-state Output Buffer (True) 6

\up tdn
Path
0.710 0.028 1.460 0.053 OTto X
(2.53) (4.91)
OT-{f'
C
LtoZ ZtoL
to KCL 10 KCL CtoX
2.000
(15.00) . 1.550
(5.13)
0.055
Input loading
Pin Name Faclor(lu)
or 6
C 2 HloZ ZloH
to KCL 10 KCL
Pin Name
Output Driving
Factor (Iu)
2.600
(15.00) . 0.740
(5.13)
0.028

DI"",kO
LSI
,IC
LSI
lc ~
~
R=2kn
,I nm
(a) Measurement of tpd at LZ and Zl. (b) Measurement of tpd at HZ and ZH.
Note: 1. The unit of KCL is nslpF.

2. Output load capacitance of 65 pF.is used for Fujitsu's logic simulation.
C21-04T EO I Sheet 1/1 I

I Page 21-49
3-383
FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION I • CG2tK· Version
04TF Tn-state Output Buffer (IOL=8mA, True) 6

\Up Idn
Path
0.750 0.028 1.480 0.040 OTto X
(2.57) (4.08)
or-tr' C
to
LtoZ
KCL to
ZtoL
KCL CtoX
2.200
(15.80) . 1.650
(4.32)
0.041
Input loading
OT 6
C 2 HtoZ ZtoH
to KCL 10 KCL
Pin Name
Output Driving
Factor (Iu)
2.600
(15.80) . 0.750
(4.32)
0.028

at LZ, Zl, HZ and ZH are as follows:
DI LSI
R-"O
LSI -1
~
R=2kn
,Ic ,Ic •
m'77
Note: 1. The unit of KCL is nsJpF.

C21-04TF-EO I Sheet 1/1 I

I Page 21-50
3-384
Cell Name Function NumberolaC
04W Power Tri-state Output Buffer (True) 6

\up tdn
Path
0.860 0.020 1.580 0.029 OTtoX
(2.16) (3.47)
cry C
x
LtoZ ZtoL
to KCL to KCL CtoX
2.800
(16.70) . 1.550
(3.50)
0.030
Input Loading
Pin Name Fac\or(lu)
OT 6
C 2 HtoZ ZtoH
to KCL to KCL
Pin Name
Output Driving
Factor (Iu)
3.300
(16.70) . 0.800
(3.50)
0.020

Dl
R.,.O
~
LSI
,IC
LSI
lc ;.
..;
R=2kn
,I nfn

C21 04W EO I Sheet 1/1 I

TPage 21-51
3-385
FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION , • CG21K· Version
Tri-state Output Buffer (True) 5
04R with Noise Limit Resistance
lop tdn
Path
1.570 0.036 4.720 0.081 OTto X
(3.91) (9.99)
o,--t?- C
X
LtoZ Zto L
to KCL to KCL Cto X
2.100
(14.20) . 4.600
(9.87)
0.081
Input Loading
OT 2
C 2 H to Z Zto H
to KCL to KCL
Pin Name
Output Driving
Factor (Iu)
1.900
(14.20) . 1.600
(9.87)
0.036
01
CJI .LSI
,.n
LSI
~
lc 1
R=2kO
,Ic
,I nTn

C21 04R EO I Sheet 1/1 I

I Page 21-52
3-386
FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION I • CG21K »Version
Tri-state Output Buffer (IOL=8mA, True)
04RF with Noise Limit Resistance
5
\up tdn
Path
1.730 0.036 5.950 0.048 OTtoX
(4.07) (9.07)
mT C
X
LtoZ ZtoL
to KCL to KCL Cto X
2.100
(16.10) . 5.650
(8.97)
0.051
Input loading
OT 2
C 2 HtoZ ZtoH
to KCL to KCL
Pin Name
Output Driving
Factor (Iu)
2.650
(16.10) . 1.600
(8.97)
0.036

c:tILSI
..,.0
LSI
lc :~ R=2kO
,IC
,I nm

C21-04RF EO I Sheet 111 I

I Page 21-53
3-387
FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION I • CG21K " Version
04S with Noise Limit Resistance
5
IUP tdn
Path
2.170 0.024 6.900 0.040 OTto X
(3.73) (9.50)
OTy C
X
LtoZ ZtoL
to KCL to KCL CtoX
2.500 6.750 0.041
(16.80) * (9.42)
Input Loading
Pin Name Faclor(lu)
OT 2
c 2 HtoZ ZtoH
to KCL to KCL
3.500 1.800 0.025
Pin Name Faclor(lu)

DI"""n
LSI
,Ic
LSI
1c
,I
:
~
rrlrr
R=2kn
(a) Measurement of tpd at LZ and Zl. (b) Measurement of tpel at HZ and ZH.

C21 04S EO I Sheet 1/1 I

I Page 21-54
3-388
H6T Tri-state Output & Input Buffer (True) 10

tup tdn
Path
0.561 0.014 0.970 0.017 XtolN
0.710 0.028 1.460 0.053 OTto X
(3.09) (5.97)
'"~
OT X
C LloZ Zto L
10 KCL 10 KCL CtoX
2.000
(19.20)
. 1.550
(6.23)
0.055
Input loading
OT 6
C 2 HtoZ ZtoH
10 KCL 10 KCL
Oulput Driving
2.600
(19.20)
. 0.740
(6.23)
0.028
IN 36

DI LSI
R.,.e
LSI
lc : R-2kO
~C
~ "'77

C21 H6T-EO I Sheet 1/1 I

I Page 21-55
3-389
H6TU 10
!Up tdn
Path
0.561 0.014 0.970 0.017 XtolN
0.710 0.028 1.460 0.053 OTto X
(3.09) (5.97)
"=cr-
OT
C
X
LtoZ ZtoL
.
to KCL to KCL CtoX
2.000 1.550 0.055
(19.20) (6.23)
Input Loading
OT 6
C 2 HtoZ ZtoH
.
to KCL to KCL
2.600 0.740 0.028
IN 36

DI LSI
R."n
LSI
1c
.:-
R=2kO
,IC
,I m'77

C21-H6TU EO I Sheet 111 I

I Page 21-56
3-390
H6TD with Pull-down Resistance
10
tup tdn
Path
0.561 0.014 0.970 0.017 XtolN
0.710 0.028 1.460 0.053 OTto X
(3.09) (5.97)
'"=tr-
OT
C
X
to
LtoZ
KCL to
Zto L
KCL Cto X
2.000
(19.20)
. 1.550
(6.23)
0.055
Input Loading
OT 6
C 2 HtoZ ZtoH
to KCL to KCL
Output Driving
2.600
(19.20)
. 0.740
(6.23)
0.028
IN 36

DI LSI
R."n
LSI
Ic
c
~
R=2kQ
,IC
,I 1Tl77
(a) Measurement of tpd at LZ and.Zl. (b) Measurement of tpd at HZ and ZH.

C21 H6TD EO I Sheet 1/1 I

1 Page 21-57
3-391
Cell Name Funcllon Number of BC
H6TF Tri-state Output & Input Buffer (IOL=8mA. True) 10

\up \dn
Palll
0.561 0.014 0.970 0.017 Xto IN
0.750 0.028 1.480 0.040 OTto X
(3.13) (4.88)
'"~
OT X
C
LtoZ ZloL
10 KCL 10 KCL Cto X
2.200
(20.10) . 1.650
(5.14)
0.041
Inpul Loading
Pin Name Faclor(lu)
OT 6
C 2 HtoZ ZtoH
10 KCL to KCL
Pin Name
Oulpul Driving
Faclor(lu)
2.600
(20.10) . 0.750
(5.14)
0.028
IN 36
IDI
at LZ. ZL, HZ and ZH are as follows:
DI LSI
,_"n
LSI
Ic ;.
<-
R=2kn
~C
~ rrl77

C21 H6TF EO I Sheet 1/1 I

I Page 21-58
3-392
Tri-state Output & Input Buffer (IOL=8mA. True)
H6TFU with Pull-up Resistance
10
tup tdn
Path
0.561 0.014 0.970 0.017 XtolN
0.750 0.028 1.480 0.040 OTto X
(3.13) (4.88)
"=tr-
OT
C
X
to
LtoZ
KCL to
Zto L
KCL Cto X
2.200
(20.10) . 1.650
(5.14)
0.041
Input Loading
OT 6
C 2 HtoZ ZtoH
to KCL to KCL
Pin Name
Output Driving
Factor(lu)
2.600
(20.10) . 0.750
(5.14)
0.028
IN 36
lID
at LZ. ZL, HZ and ZH are as follows:
Di··"n
LSI
,IC
LSI
-
VI
,IC
.(
~
<-
rrl77
R=2kn
Note: 1. The unit of KCL for paths OTt C to X is ns/pF.

C21-H6TFU EOI Sheet 1/1 I

TPage 21-59
3-393
H6TFD 10
tup tdn
Path
0.561 0.014 0.970 0.017 XtolN
0.750 0.028 1.480 0.040 OTto X
(3.13) (4.88)
IN~
OT X
C
LtoZ ZtoL
to KCL to KCL CtoX
2.200
(20.10) . 1.650
(5.14)
0.041
Input loading
OT 6
C 2 HtoZ Zto H
to KCL to KCL
Pin Name
Output Driving
Factor (Iu)
2.600
(20.10) . 0.750
(5.14)
0.028
IN 36

CJI LSI
R."e
LSI -1 ;.
~
R=2kn
I C
I C
rrl77

C21 H6TFD-EOI Sheet 1/1 I

I Page 21-60
3-394
Cell Name Function Number olSC
I-
H6W Power Tri-state Output & Input Buffer (True) 10
!Up teln
Path
0.561 0.014 0.970 0.017 XtolN
0.860 0.020 1.580 0.029 OTto X
(2.56) (4.05)
"=rr-
OT
C
X
L 10Z ZtoL
. CtoX
10 KCL 10 KCL
2.800 1.550 0.030
(21.00) (4.10)
Input Loading
Pin Name Faclor(lu)
OT 6
C 2 HloZ ZtoH
.
10 KCL 10 KCL
3.300 0.800 0.020
Oulpul Driving (21.00) (4.10)
IN 36

~R_"n
-1
~
LSI LSI ;. R=2kn

'\
I C
I C
rrlTT
(a) Measurement of tpd at LZ and. ZL. (b) Measurement of tpd at HZ and ZI:f.

C21 H6W EO I Sheet 1/1 I

I Page 21-61
3-395
Celt Name Function Number or BC
Power Tri-state Output & Input Buffer (True) 10
H6WU with Pull-up Resistance
\up teln
Pa1h
0.561 0.014 0.970 0.017 XlolN
0.860 0.020 1.580 0.029 OTto X
(2.56) (4.05)
IN~
OT X
C LtoZ ZtoL
2.800
to
(21.00)
.
KCL. to
1.550
(4.10)
0.030
KCL CtoX
Input loading
OT 6
C 2 HtoZ ZtoH
to KCL to KCL
Output Driving
3.300
(21.00)
. 0.800
(4.10)
0.020
IN 36

DIR.,.c
LSI LSI f" R=2k.(l
1c '\
,IC
,I nTr7

C21-H6WU EO I Sheet 1/1 I

I Page 21-62
3-396
Power Tri-state Output & Input Buffer (True) 10
H6WD with Pull-down Resistance
tup !dn
Path
0.561 0.014 0.970 0.017 XtolN
0.860 0.020 1.580 0.029 OTto X
(2.56) (4.05)
'"=cr-
OT
C
X
to
LtoZ
KCL to
ZtoL
KCL Cto X
2.800
(21.00)
. 1.550
(4.10)
0.030
Input loading
OT 6
C 2 HtoZ ZtoH
to KCL to KCL
Output Driving
3.300
(21.00)
. 0.800
(4.10)
0.020
IN 36

DIR."n
LSI LSI
Ic
R=2kQ
,r,c
,r, ",7T

C21 H6WD EO I Sheet 1/1 I

I Page 21-63
3-397
H6C Tri-state Output & CMOS Interface Input Buffer (True) 10

tup tdn
Palh
0.489 0,014 0.706 0.017 XtolN
0.710 0.028 1.460 0.053 OTto X
(3.09) (5.97)
OT
"=tr- C
X
to
LtoZ
KCL to
ZtoL
KCL Cto X
2.000
(19.20)
. 1.550
(6.23)
0.055
Input Loading
Pin Name Factor (luJ
OT 6
C 2 HtoZ Zto H
KCL to KCL
.
to
2.600 0.740 0.028
Pin Name Factor (luJ
IN 36

~,",kn
LSI LSI
• R=2kO
lc
,IC
,I nl77

C21 H6C EO I Sheet 1/1 I

I Page 21-64
3-398
Tri-state Output & CMOS Interface Input Buffer (True) 10
H6CU with Pull-up Resistance
!Up teln
Path
0.489 0.014 0.706 0.017 XtolN
0.710 0.028 1.460 0.053 OTtoX
(3.09) (5.97)
"=tr-
OT
C
X
LtoZ ZtoL
2.000
to
(19.20)
.
KCL to
1.550
(6.23)
KCL
0.055
Cto X
Input Loading
OT 6
C 2 HtoZ ZtoH
KCL to KCL
.
to
2.600 0.740 0.028
IN 36

DI""c
LSI
I C
LSI
I
lc :
m77
R=2kQ

C21 H6CU EO I Sheet 1/1 I

I Page 21-65
3-399
Tri-state Output & CMOS Interface Input Buffer (True) 10
H6CD with Pull-down Resistance .
\up teln
Path
0.489 0.014 0.706 0.017 XtolN
0.710 0.028 1.460 0.053 OTto X
(3.09) (5.97)
w=cr-
or x
C LtoZ Zio L
10 KCL 10 KCL Cto X
2.000
(19.20)
. 1.550
(6.23)
0.055
Input loading
Pin Name FaC\or(lu)
or 6
C 2 HloZ ZtoH
KCL to KCL
.
10
2.600 0.740 0.028
output Driving (19.20) (6.23)
IN 36
III
CJI LSI
R."e
LSI
lc
> R~2kn
,Ic
,I mw

C21-H6CD-EO I Sheet 1/1 I

I Page 21-66
3-400
FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION I " CG21 K" Version
H6CF (IOL=8mA, True)
8
CeUSymbol Propagallon Delay Parameter
!Up tdn
Path
0.489 0.014 0.706 0.017 XtolN
0.750 0.028 1.480 0.040 OTto X
(3.13) (4.88)
"~
OT X
C
LtoZ ZtoL
to KCL. to KCL CtoX
2.200
(20.10)
. 1.650
(5.14)
0.041
Input Loading
OT 4
C 2 HtoZ ZtoH
to KCL to KCL
Pin Name
Output Driving
Factor (Iu)
2.600
(20.10) . 0.750
(5.14)
0.028
IN 36

CJI LSI
"."e
LSI
1c
.
=
R=2kn
I C
I mn
(a) Measurement of tpd at LZ and ZL. (b) Measurement of tpd at HZ and ?H.

C21 H6CF EO I Sheet 1/1 I

I Page 21-67
3-401
H6CFU with Pull-up Resistance (IOL=8mA, True)
8
tup tdn
Palh
0.489 0.014 0.706 0.017 Xto IN
0.750 0.028 1.480 0.040 OTto X
(3.13) (4.88)
'"=er-
OT
C
X
LtoZ ZtoL
to KCL to KCL Cto X
2.200
(20.10) . 1.650
(5.14)
0.041
Input Loading
OT 4
C 2 HtoZ ZtoH
to KCL to KCL
Pin Name
Output Driving
Factor (Iu)
2.600
(20.10) . 0.750
(5.14)
0.028
IN 36

DI LSI
A."n
LSI -1 ~ R=2kn
,Ic ,Ic <'

rrfn
(a) Measurement of tpd at LZ and ZL. (b) Measurement of tpel at HZ and ZH.
Note: 1. The unit of KCL for paths OT, C to X is nsipF.

2. Output load capacitance of 85 pF is used for Fujitsu's logiC simulation.
C21 H6FU EO I Sheet 1/1 I

I Page 21-68
3-402
H6CFD with Pull-down Resistance (IOL=8mA, True)
8
tup teln
Path
0.489 0.014 0.706 0.017 XtolN
0.750 0.028 1.480 0.040 OTtoX
(3.13) (4.88)
"=tr-
OT
C
X
to
LtoZ
KCL. to
ZtoL
KCl Cto X
2.200
(20.10) . 1.650
(5.14)
0.041
Input loading
OT 4
C 2 HtoZ ZtoH
to KCL to KCL
Pin Name
Output Driving
Factor (Iu)
2.600
(20.10) . 0.750
(5.14)
0.028
IN 36

.C:rI
,.,,0
LSI lSI
- ~ R=2kn
Ic ~
I C
I nm

C21 H6CFD-EOI Sheet 1/1 I

I Page 21-69
3-403
Power Tri-state Output & CMOS Interface 10
H6E Input Buffer (True)
tup tdn
Palll
0.489 0.014 0.706 0.017 XtolN
0.860 0.020 1.580 0.029 OTto X
(2.56) (4.05)
w~
OT X
C LtoZ ZtoL
to KCL. to KCL Cto X
2.800
(21.00)
. 1.550
(4.10)
0.030
Input loading
OT 6
C 2 HtoZ ZloH
10 KCL to KCL
Oulput Driving
3.300
(21.00)
. 0.800
(4.10)
0.020
Pin Name Faclor(lu)
IN 36

DI LSI
..,,0
LSI
lc ~ R=2kn
,Ic ,I
>
nm

C21-H6E EO I Sheet 111 I

I Page 21-70
3-404
Power Tri-state Output & CMOS Interface 10
H6EU Input Buffer (True) with Pull-up Resistance
!up tdn
Palh
0.489 0.014 0.706 0.017 XtolN
0.860 0.020 1.580 0.029 OTtoX
(2.56) (4.05)
OT
'"=tr- C
X
LtoZ ZtoL
2.800
to
(21.00)
.
KCL to
1.550
(4.10)
0.030
KCl CtoX
Input loading
OT 6
C 2 HtoZ ZtoH
to KGL to KCl
Output Driving
3.300
(21.00)
. 0.800
(4.10)
0.020
IN 36
III
DI LSI
"_"n
LSI
1c
..; R=2kO
,IC
,I nfn

C21 H6EU-EO I Sheet 1/1 I

I Page 21-71
3-405
H6ED Input Buffer (True) with Pull-down Resistance
10
!Up Idn
Path
0.489 0.014 0.706 0.017 XtolN
0.860 0.020 1.580 0.029 OTto X
(2.56) (4.05)
m=cr-
OT X
C L 10 Z Zio L
10 KCL 10 KCL CtoX
2.800
(21.00)
. 1.550
(4.10)
0.030
Input Loading
OT 6
C 2 HloZ ZloH
10 KCL 10 KCL
Oulput Driving
3.300
(21.00)
. 0.800
(4.10)
0.020
IN 36
HI
~R."n
LSI
,IC
LSI
Ic ./'
-i
R=2kO
,I nm
Note: 1. The unit of KCL for paths OT, C to X is nsJpF.

3. The parameters in. parentheses are the values applied to the simulation.
C21 H6ED-EO I Sheet 111 I

1Page 21-72
3 ....406
Cel/Name Function Number of BC
Tri-state Output & Schmitt Trigger Input Buffer 14
H6S (CMOS Type, True)
tup tdn
Path
1.314 0.060 1.630 0.045 XtolN
0.710 0.028 1.460 0.053 OTto X
(3.09) (5.97)
'"=tr-
OT
c
X
LtoZ
KCL to
Zto L
KCL Cto X
.
to
2.000 1.550 0.055
(19.20) (6.23)
Input Loading
Pin Name FactorClu)
OT 6
C 2 HtoZ Z to H
to KCL to KCL
Output Driving
2.600
(19.20)
. 0.740
(6.23)
0.028
Pin Name FactorClu)
iN 18 (

DI LSI
R."n
LSI
lc
;.
..;
R=2kn
I C
I nm
(a) Measurement of tpd at LZ and.zl. (b) Measurement of tpd at HZ and ZH.

C21 H6S-EO I Sheet 1/1 1

I Page 21-73
3-407
H6SU (CMOS Type, True) with Pull-up Resistance
iuD !dn
Path
1.314 0.060 1.630 0.045 XtolN
0.710 0.028 1.460 0.053 OTto X
(3.09) (5.97)
'"=tr-
OT
C
X
to
LtoZ
KCL. 10
ZtoL
KCL Cto X
2.000
(19.20)
. 1.550
(6.23)
0.055
Input loading
OT 6
C 2 HtoZ ZtoH
to KCL to KCL
Output Driving
2.600
(19.20)
. 0.740
(6.23)
0.028
IN 18

CJI
R.,"e
LSI LSI ~ R=2kO

lc ;-
I C
I nm
(a) Measurement of tpd at LZ and ZL. (b) Measurement of tpel at HZ and ZH.

C21 H6SU EO I Sheet 1/1 I

I Page 21-74
3-408
Call Name Function Number 01 BC
H6SD (CMOS Type, True) with Pull-down Resistance
\up teln
Palh
1.314 0.060 1.630 0.045 XtolN
0.710 0.028 1.460 0.053 OTto X
(3.09) (5.97)
'"=tr-
OT
C
X
to
LtoZ
KCL to
ZtoL
KCL Cto X
2.000
(19.20)
. 1.550
(6.23)
0.055
Input loading
OT 6
C 2 HtoZ ZtoH
to KCL 10 KCL
Output Driving
2.600
(19.20)
. 0.740
(6.23)
0.028
IN 18

atLZ, ZL, HZ and ZH are as follows:
DI"""o
LSI
,IC
LSI
Ic
,I
>
~
rri"TT
R=2kO

C21-H6SD-EO I Sheet 1/1 I

I Page 21-75
3-409
H6R (TTL Type, True)
14
lOp tdn
Path
1.182 0.060 1.967 0.062 XtolN
0.710 0.028 1.460 0.053 OTto X
(3.09) (5.97)
~~
OT X
C
LloZ ZtoL
to KCL to KCL CtoX
2.000
(19.20)
. 1.550
(6.23)
0.055
Input loading
OT 6
C 2 HtoZ ZtoH
to KCL to KCL
Output Driving
2.600
(19.20)
. 0.740
(6.23)
0.028
IN 18

DI LSI
R."e
LSI
....
Ic .> R=2kO
,IC
,I m'77

C21-H6R EO I Sheet 111 I

I Page 21-76
3-410
FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION I n CG21K" Version
H6RU (TTL Type, True) with Pull-up Resistance
\up Idn
Path
1.182 0.060 1.967 0.062 Xto IN
0.710 0.028 1.460 0.053 OTto X
(3.09) (5.97)
"~
OT X
C
LtoZ Zio L
10 KCL 10 KCL CtoX
2.000
(19.20)
. 1.550
(6.23)
0.055
Input Loading
OT 6
C 2 HtoZ Zto H
10 KCL to KCL
Output Driving
2.600
(19.20)
. 0.740
(6.23)
0.028
IN 18

crI LSI
..,.0
LSI
lc . R=2kO
,IC
,I m77

C21 H6RU EO I Sheet 111 I

I Page 21-77
3-411
H6RD (TTL Type, True) with Pull-down Resistance
tup tdn
Path
1.182 0.060 1.967 0.062 Xto IN
0.710 0.028 1.460 0.053 OTto X
(3.09) (5.97)
"=tr-
OT
C
X
to
LtoZ
KCL to
ZtoL
KCL CtoX
2.000
(19.20)
. 1.550
(6.23)
0.055
Input Loading
OT 6
C 2 HtoZ ZtoH
to KCL to KCL
Output Driving
2.600
(19.20)
. 0.740
(6.23)
0.028
IN 18

CJ! LSI
R."a
LSI
lc
~
~
R=2kQ
,IC
,I rrl77

C21 H6RD EO I Sheet 1/1 I

I Page 21-78
3-412
HBT & Input Buffer (True)
9
!Up tdn
Path
0.561 0.014 0.970 0.017 XtolN
1.570 0.036 4.720 0.081 OTtoX
(4.63) (11.61)
'"~
OT X
C
LtoZ Zto L
. CtoX
to KCL to KCL
2.100 4.600 0.081
(18.10) (11.49)
Input loading
OT 2
C 2 HtoZ ZtoH
to KCL to KCL
Output Driving
1.900
(18.10)
. 1.600
(11.49)
0.036
IN 36

DI LSI
R."n
LSI
lc ;.
•
R=2kn
,IC
,1 rrl77

C21 H8T EO I Sheet 1/1 I

I Page 21-79
3-413
HBTU & Input Buffer (True) with Pull-up Resistance
9
!Up tdn
Path
0.561 0.014 0.970 0.017 XtolN
1.570 0.036 4.720 0.081 OTto X
(4.63) (11.61)
'"~
OT X
C
LtoZ ZloL
10 KCL 10 KCL CtoX
2.100
(18.10)
. 4.600
(11.49)
0.081
Input Loading
OT 2
C 2 HloZ ZloH
KCL 10 KCL
.
10
1.900 1.600 0.036
IN 36

CJI
"_,,0
LSI LSI $. R=2kn
lc •
,Ic
,I rrl77

C21 HBTU EO I Sheet 1/1 I

I Page 21-80
3-414
HBTD & Input Buffer (True) with Pull-down Resistance
9
!Up Idn
Path
0.561 0.014 0.970 0.017 XtolN
1.570 0.036 4.720 0.081 OTto X
(4.63) (11.61)
'"=tr-
OT
C
X
to
LtoZ
KCL 10
Zio L
KCL CtoX
2.100
(18.10)
. 4.600
(11.49)
0.081
Input Loading
OT 2
C 2 HtoZ ZloH
10 KCL to KCL
Output Driving
1.900
(18.10)
. 1.600
(11.49)
0.036
IN 36

C}f LSI
".,,0
LSI
.
= R=2kn
lc ~
,IC
,I nfn

C21 H8TD EO I Sheet 1/1 I

1 Page 21-81
3-415
HBTF & Input Buffer (IOL=8mA. True)
9
!Up tdn
to KCL to KCL KCL2 Path
CDR2
0.561 0.014 0.970 0.017 XtolN
1.730 0.036 5.950 0.048 OTto X
(4.79) (10.03)
'N~
OT X
C
LIOZ ZtoL
to KCL to KCL Cto X
2.100
(20.90) . 5.650
(9.99)
0.051
Input loading
OT 2
C 2 HIOZ ZtoH
to KCL to KCL
Pin Name
Output Driving
Factor (Iu)
2.650
(20.90) . 1.600
(9.99)
0.036
III' IN 36

CJ! LSI
"",kO
LSI
lc
:
>
R=2kn
,IC
,I

'""

C21 H8TF EOl Sheet 1/1 I

I Page2Hl2
3-416
HBTFU 9
& Input Buffer (IOL=8mA, True) with Pull-up Resistance
!Up tdn
Path
0.561 0.014 0.970 0.017 XtolN
1.730 0.036 5.950 0.048 OTtoX
(4.79) (10.03)
"~
OT X
C
Lto Z Z to L
to KCL to KCL CtoX
2.100
(20.90)
. 5.650
(9.99)
0.051
Input Loading
OT 2
C 2 H to Z Z toH
to KCL to KCL
Pin Name
Output Driving
Factor (Iu)
2.650
(20.90) . 1.600
(9.99)
0.036
IN 36

C}f ,-,,0
1
LSI
J,c
LSi
lc "i
R=2kn
J, rriTT

C21 H8TFU EOI Sheet 1/1 1

I Page 21-83
3-417
HBTFD & Input Buffer (IOL=8mA, True) with Pull-down Resistance
9
lup Idn
Path
0.561 0.014 0.970 0.017 Xto IN
1.730 0.036 5.950 0.048 OTto X
(4.79) (10.03)
'"=rr-
OT
C
X
10
LtoZ
KCL 10
Zlo L
KCL CtoX
2.100
(20.90) . 5.650
(9.99)
0.051
Inpul Loading
OT 2
C 2 HloZ ZloH
10 KCL 10 KCL
Pin Name
Oulpul Driving
Faclor (Iu)
2.650
(20.90) . 1.600
(9.99)
0.036
IN 36

CJI
R.,.o
LSI LSI : R=2kn

lc ~
,rc
,I nTn

C21 H8TFD Eol Sheet 111 I

I Page 21-84
3-418
Power Tri-state Output with Noise Limit Resistance
HBW & Input Buffer (True)
9
\up tdn
Path
0.561 0.014 0.970 0.017 XtolN
2.170 0.024 6.900 0.040 OTto X
(4.21) (10.30)
"=tr-
OT
C
X
10
LtoZ
KCL 10
ZloL
KCL Cto X
2.500
(20.90)
. 6.750
(10.24)
0.041
Input Loading
Pin Name Faclor(lu)
OT 2
C 2 HloZ ZloH
10 KCL 10 KCL
Output Driving
3.500
(20.90)
. 1.800
(10.24)
0.025
IN 36

CJI LSI
R."e
LSI
Ic R=2kO
,Ic ,I m'77
(a) Measurement of tpd at LZ and.ZL. (b) Measurement of tpd at HZ and ZH.

C21 H8W-EO I Sheet 1/1 I

I Page 21-85
3-419
Power Tri-state Output with Noise Limit Resistance 9
HBWU & Input Buffer (True) with Pull-up Resistance
IUp !dn
Path
to KCl 10 KCl KCl2 CDR2
0.561 0.014 0.970 0.017 XtolN
2.170 0.024 6.900 0.040 OTto X
(4.21) (10.30)
'"=tr-
OT
C
X
to
ltoZ
KCl to
Ztol
KCl CtoX
2.500
(20.90)
. 6.750
(10.24)
0.041
Input loading
OT 2
C 2 HtoZ ZtoH
KCl to KCl
.
10
3.500 1.800 0.025
IN 36

c=rI
R_'~
lSI lSI
Ic :1 R=2K.O
,IC
,I nm
Note: 1. The unit of KCl for paths OT, C to X is ns/pF.

C21-H8WU-EO I Sheet 1/1 I

I Page 21-86
3-420
FUJITSU CMOS GATE ARRAY UNIT CEll SPECIFICATION r" CG21K" Version
Power Tri-state Output with Noise Limit Resistance 9
HBWD & Input Buffer (True) with Pull-down Resistance
hJp !dn
Path
0.561 0.014 0.970 0.Q17 XtolN
2.170 0.024 6.900 0.040 OTto X
(4.21) (10.30)
'"=cr-
OT
C
X
LtoZ ZtoL
. CtoX
to KCL to KCL
2.500 6.750 0.041
(20.90) (10.24)
Input Loading
OT 2
C 2 HloZ ZtoH
Output Driving
3.500
to
(20.90)
.
KCL to
1.800
(10.24)
KCL
0.025
IN 36

at LZ, Zl, HZ and ZH are as follows:
DI LSI
"",,0
LSI
lc
R=2kn
,Ic
,I ",77
(a) Measurement of tpd at lZ and Zl. (b) Measurement of tpd at HZ and ZH.

C21 H8WD EO I Sheet 1/1 I

I Page 21-87
3-421
Tri-state Output Buffer with Noise limit Resistance
HBC & CMOS Interface Input Buffer (True)
9
Cell Symbol Propagat/on Delay Parameler
!Up teln
Path
0.489 0.014 0.706 0.017 XtolN
1.570 0.036 4.720 0.081 OTto X
(4.63) (11.61)
."=tr-
aT
C
x
LtoZ ZloL
.
10 KCL to KCL CtoX
2.100 4.600 0.081
(18.10) (11.49)
Input Loading
Pin Name Faclor(lu)
aT 2
C 2 HloZ ZloH
.
10 KCL 10 KCL
1.900 1.600 0.036
IN 36

DI"""
LSI
,Ic
LSI -1
~
,Ic >
~
rrlrr
R=2kn

C21-H8C-EO I Sheet 1/1 I

I Page 21-88
3-422
Tri-state Output Buffer wI Noise Limit Resistance &
HBCU CMOS Interface Input Buffer (True) wI Pull-up Resistance
9
lup Idn
Path
0.489 0.014 0.706 0.017 XtolN
1.570 0.036 4.720 0.081 OTtoX
(4.63) (11.61)
"=tr-
OT
C
X
10
LloZ
KCL 10
ZloL
KCL CtoX
2.100
(18.10)
. 4.600
(11.49)
0.081
Input loading
Pin Name Faclor(lu)
OT 2
C 2 HloZ ZIO H
KCL 10 KCL
.
10
1.900 1.600 0.036
Oulpul Driving (18.10) (11.49)
Pin Name Faclor(lu)
IN 36

~R_"D -
LSI LSI
lc <: R=2kQ
~
,IC
,I rrl-n

C21 H8CU-EO I Sheet 1/1 I

I Page 21--89
3-423
FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION .. CG21 K" Version
Tri-state Output Buffer wi Noise Limit Resistance & CMOS 9
HBCD Interface Input Buffer (True) wi Pull-down Resistance
!Up tdn
Path
0.489 0.014 0.706 0.017 Xto IN
1.570 0.036 4.720 0.081 OTto X
(4.63) (11.61 )
'"=cr-
OT
C
X
L toZ Zte L
to KCL to KCL CtoX
2.100
(18.10)
. 4.600
(11.49)
0.081
Input Loading
Pin Name Faclor(lu)
OT 2
C 2 H to Z ZteH
to KCL to KCL
Output Driving
1.900
(18.10)
. 1.600
(11.49)
0.036
IN 36

DI
,.,,0
LSI LSI
lc ;.
•
R=2kn
,rC
,l rrTn
Note: 1. The unit of KCL for paths OT. C to X is ns/pF.

C21 H8CD EO Sheet 1/1 I

I Page 21-90
3-424
Tri-state Output Buffer with Noise Limit Resistance
HBCF & CMOS Interface Input Buffer (IOL=8mA, True)
9
\up Idn
Path
0.489 0.014 0.706 0.017 XtolN
1.730 0.036 5.950 0.048 OTto X
(4.79) (10.03)
"=tr-
OT
C
X
10
L loZ
KCL 10
ZloL
KCL Cto X
2.100
(20.30) . 5.650
(9.99)
0.051
Inpul Loading
Pin Name Faclor(lu)
OT 2
C 2 HtoZ Zlo H
10 KCL 10 KCL
Pin Name
Oulpul Driving
Faclor(lu)
2.650
(20.30) . 1.600
(9.99)
0.036
IN 36

c:rILSI
,",,0
LSI : R=2kn
,Ie 1c
,I
~
nfrT

C21-H8CF-EO I Sheet 1/1 I

I Page 21-9t
3-425
FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION '"CG21K"Version
Tri-state Output Buffer wI Noise Limit Resistance & CMOS
H8CFU Interface Input Buffer (IOL=8mA, True) wI Pull-up Resistance
9
Cell Symbol PropagaUon Delay Parameler
lup Idn
Path
0.489 0.014 0.706 0.017 XtolN
1.730 0.036 5.950 0.048 OTto X
(4.79) (10.03)
'"=tr-
OT
C
X
10
LIc Z
KCL 10
ZIO L
KCL CtoX
2.100
(20.30) . 5.650
(9.99)
0.051
Inpul Loading
Pin Name Faclor(lu)
OT 2
C 2 HIoZ ZIoH
10 KCL 10 KCL
Pin Name
Oulpul Driving
Faclor(lu)
2.650
(20.30) . 1.600
(9.99)
0.036
IN 36

DI LSI
"",,0
LSI
~
Ic ~
'\
R=2kn
I C
I rrl77

C21 H8CFU EO Sheet 1/1 I

-[ Page 21-92
3-426
Tri-state Output Buffer wI Noise Limit Resistance & CMOS
HBCFD 9
Interface Input Buffer (IOL=8mA, True) wI Pull-down Resistance
\Up tdn
Path
0.489 0.014 0.706 0.017 XtolN
1.730 0.036 5.950 0.048 OTto X
(4.79) (10.03)
'"=tr-
OT
C
X
10
LtoZ
KCL 10
ZloL
KCL Cto X
2.100
(20.30) . 5.650
(9.99)
0.051
Input Loading
Pin Name Faclor(lu)
OT 2
C 2 HloZ Zto H
10 KCL 10 KCL
Pin Name
Output Driving
Factor (Iu)
2.650
(20.30) . 1.600
(9.99)
0.036
IN 36

C}f LSI
,",,0
LSI ~ R=2kO
Ic <>
,IC
,I rrlTT

C21 H8CFD EOI Sheet 1/1 I

I Page 21-93
3-427
Cell Name Funcdon Numb.ror BC
Power Tri-state Output Buffer wI Noise Limit Resistance
HBE & CMOS Interface Input Buffer (True)
9
!Up teln
Path
0.489 0.014 0.706 0.017 XtolN
2.170 0.024 6.900 0.040 OTto X
(4.21) (10.30)
'"~
OT X
C
LtoZ ZtoL
. CtoX
to KCL to KCL
2.500 6.750 0.041
(20.90) (10.24)
Input Loading
OT 2
C 2 HtoZ ZtoH
to KCL to KCL
Output Driving
3.500
(20.90)
. 1.800
(10.24)
0.025
IN 36
IDI
CJI LSI
R.,.e
LSI -1 ;.
'\
R=2kO
I C
I C
rrlrt

C21 H8E-EO I Sheet 1/1 I

I Page 21-94
3-428
Power Tri-state Output Buffer wI Noise Limit Resistance &
HBEU CMOS Interface Input Buffer (True) wI Pull-up Resistance
9
\Up teln
Path
0.489 0.014 0.706 0.017 XtolN
2.170 0.024 6.900 0.040 OTto X
(4.21) (10.30)
"=tr-
OT
C
X
10
LtoZ
KCL 10
ZtoL
KCL CtoX
2.500
(20.90)
. 6.750
(10.24)
0.041
Input loading
aT 2
C 2 HtoZ ZtoH
10 KCL 10 KCL
Output Driving
3.500
(20.90)
. 1.800
(10.24)
0.025
IN 36

DI"""c
LSI
,IC
LSi
Ic
,I
'$
'I
nm
R=2kQ

C21-H8EU EO I Sheet 1/1 I

I Page 21-95
3-429
Power Tri-state Output Buffer wI Noise Limit Resistance &
HBED CMOS Interface Input Buffer (True) wI Pull-down Resistance
9
\up tdn
Path
0.489 0.014 0.706 0.017 XtolN
2.170 0.024 6.900 0.040 OTto X
(4.21) (10.30)
"=tr-
OT
C
X
to
LtoZ
KCL to
ZtoL
KCL Cto X
2.500
(20.90)
. 6.750
(10.24)
0.041
Input Loading
OT 2
C 2 HtoZ ZtoH
to KCL to KCL
Output Driving
3.500
(20.90)
. 1.800
(10.24)
0.025
IN 36

~"_"n
LSI
,IC
LSI
1c ~ R=2kO
;.
,I ntrr

C21 H8ED-EO I Sheet 1/1 I

I Page 21-96
3-430
HBS (CMOS Type, True) with Noise Limit Resistance
13
\up tdn
Path
1.314 0.060 1.630 0.045 XtolN
1.570 0.036 4.720 0.081 OTto X
(4.63) (11.61)
'"~
OT X
C
LtoZ ZtoL
to KCL to KCL Cto X
2.100
(18.10) . 4.600
(11.49)
0.081
Input loading
OT 2
C 2 HtoZ ZtoH
to KCL to KCL
Pin Name
Output Driving
Factor (luJ
1.900
(18.10) . 1.600
(11.49)
0.036
IN 18

~R_"O
LSI
~c
LSI
Ie t R=2kn
~ nm

C21 H8S-EO I Sheet 1/1 I

I Page 21-97
3-431
Tri-S!rte Output & Schmitt Trigger Input Buffer (CMOS Type 13
HBSU • True wI Noise Limit Resistance wI Pull-up Resistance
III tdn
Palh
1.314 0.060 1.630 0.045 XtolN
1.570 0.036 4.720 0.081 OTto X
(4.63) (11.61)
OT w~ X
C
LtoZ ZtoL
. Cto X
to KCL to KCL
2.100 4.600 0.081
(18.10) (11.49)
Input loading
Pin Name Faclor(lu)
OT 2
C 2 HtoZ ZtoH
to KCL to KCL
Pin Name
Output Driving
Faclor(lu)
1.900
(18.10) . 1.600
(11.49)
0.036
IN 18

crI LSI
R-"n
LSI
lc ~
-?'
R.2kil
,IC
,I rrm

C21 H8SU-EO I Sheet 1/1 I

I Page 21-98
3-432
Tri-state Output & Schmitt Trigger Input Buffer (CMOS Type
HBSD , True) wi Noise Limit Resistance wi Pull-down Resistance
13
Ce/lSymbol Propagation Delay Parameter
tup teln
Path
1.314 0.060 1.630 0.045 XtolN
1.570 0.036 4.720 0.081 OTto X
(4.63) (11.61)
OT
'"=rr- C
X
LtoZ ZtoL
to KCL to KCL CtoX
2.100
(18.10)
. 4.600
(11.49)
0.081
Input Loading
OT 2
C 2 HtoZ ZtoH
to KCL to KCL
Pin Name
Output Driving
Factor (Iu)
1.900
(18.10) . 1.600
(11.49)
0.036
IN 18

c:rI
,.,,0
LSI
,Ic
LSI
lc ;. R=2kO
~
,I nTn

C21 H8SD EO I Sheet 1/1 I

I Page 21-99
3-433
HBR (TTL Type, True) with Noise Limit Resistance
13
\up teln
Palh
1.182 0.060 1.967 0.062 Xto IN
1.570 0.036 4.720 0.081 OTto X
(4.63) (11.61)
'"=tr-
OT
C
X
LtoZ ZloL
. CtoX
10 KCL 10 KCL
2.100 4.600 0.081
(18.10) (11.49)
Input loading
Pin Name Faclor(lu)
OT 2
C 2 HloZ ZtoH
10 KCL 10 KCL
Pin Name
Output Driving
Faclor(lu)
1.900
(18.10) . 1.600
(11.49)
0.036
IN 18

CJI LSi
..,.0
LSi
Ic >-
R=2kO
,IC
,I rr.fT7

C21 H8R EO I Sheet 1/1 I

I Page 21-100
3-434
FUJITSU CMOS GATE ARRAY UNIT CELL SPECIFICATION ,"CG21K"Version
Tri-state Output & Schmitt Trigger Input Buffer (TTL Type, 13
HBRU True) wI Noise Limit Resistance wI Pull-up Resistance
tup tdn
Path
1.182 0.060 1.967 0.062 XtolN
1.570 0.036 4.720 0.081 OTto X
(4.63) (11.61)
w=rr-
OT X
C
LtoZ ZtoL
. CtoX
to KCL. to KCL
2.100 4.600 0.081
(18.10) (11.49)
Input loading
OT 2
C 2 HtoZ ZtoH
to KCL to KCL
Pin Name
Output Driving
Factor (Iu)
1.900
(18.10) . 1.600
(11.49)
0.036
IN 18
IIJ
~R'''C
LSI
,Ic
LSI
1c ~ R~2kn
,I rrl77

C21 H8RU EO I Sheet 1/1 ,

I Page 21-101
3-435
Tri-state Output & Schmitt Trigger Input Buffer (TIL Type,
HBRD True) wi Noise Limit Resistance wi Pull-down Resistance
13
\up tdn
Path
1.182 0.060 1.967 0.062 XtolN
1.570 0.036 4.720 0.081 OTto X
(4.63) (11.61)
'"=tr-
OT
C
X
LtoZ Zto L
. Cto X
to KCL to KCL
2.100 4.600 0.081
(18.10) (11.49)
Input Loading
OT 2
C 2 HIOZ ZtoH
to KCL to KCL
Pin Name
Output Driving
Factor (Iu)
1.900
(18.10) . 1.600
(11.49)
0.036
iN 18

CJl LSI
A."O
LSI
lc :~ R-2kO
,IC
,I rrlrr

C21-H8RD-EO I Sheet 1/1 I

I Page 21-102
3-436
CMOS Channel/ess Gate Arrays CG21 Series Unit Cel/ Library
Appendix A: General AC Specifications
Simulation Delay Specifications

(Recommended Operating Conditions, Ta = 0 to 70°C, VDD = 5 V±5%
Delay Multipliers Min. Max.

Pre·layout Simulation 0.35 tmaxB
Post-layout Simulation 0.40 tmaxA
Junction Temperature (Til tmaxB tmaxA

Tj .$ 60°C 1.65 1.55
60°C<Tj .$ 70°C 1.70 1.60

70°Cdj .$ 80°C 1.75 1.65
80°Cdj .$ 90°C 1.80 1.70
90°Cdj .$ 105°C 1.85 1.75
105°Cdj .$ 120°C 1.90 1.80
120°Cdj .$ 130°C' 1.95 1.85
130°Cdj .$ 140°C2 2.00 1.90
140°Cdj .$ 150°C2 2.05 1.95
NOTES: 1. This condition cannot be applied to devices in some plastic packages. If this condition is
required for devices in plastic, please consult Fujitsu.
2. This condition cannot be applied to devices in plastic packages. If this condition is required
even for ceramic packages, please consult Fujitsu.
Tj is determined by the following formula:
Tj = TaMAX + 9ja x Pd tC)
where
TaMAX: Maximum Ambient Termperature (0G)

9ja: Thermal Resistance (OC/W). This value is determined for each package.
Pd: Power dissipation (W). Please refer to Chapter 5 of Section 1 of this Data Book or the CG21
Design Manual for details.
3-437
CG21 Series Unit CeU LibraI}' CMOS Channe//ess Gate Arrays
3-438
Appendix B: Hierarchical Structure
LEVEL
2
3-439
CG21 Series Unit CeR Library CMOS Channel/ess Gate Arrays
3-440
CMOS Channe//ess Gate Arrays CG21 Series Unit Cell Library
Appendix C: Estimation Tables for Metal Loading

CG21303 (30K-gate-devlce) (Main Block)
Cdlu)
1 12.3 9.7 6.8 4.3 2.1
2 18.5 14.4 10.3 6.6 3.2
3 24.8 19.3 13.8 8.8 4.3
4 29.0 22.7 16.1 10.3 5.1
5 32.1 25.2 17.8 11.4 5.7
6 34.6 27.1 19.2 12.3 6.1
7 37.9 29.6 21.1 13.5 6.7
8 39.4 30.9 21.8 14.0 6.9
9 40.4 31.6 22.4 14.4 7.1
10 41.4 32.5 23.0 14.7 7.3
11 41.4 32.5 23.0 14.7 7.3
12 42.0 32.8 23.3 14.9 7.4
13 42.6 33.3 23.7 15.1 7.6
14 43.6 34.2 24.3 15.5 7.7
15 43.6 34.2 24.3 15.5 7.7
16-30 47.2 37.0 26.3 16.7 8.3
31-50 54.0 42.4 30.0 19.2 9.5
51-75 55.6 43.5 30.9 19.7 9.8
76-100 61.1 47.8 33.8 21.7 10.8
CG21303 (30K-gate-devlce) (Sub Block)
Cdlu)
1 5.8 4.1 2.7 1.2
2 10.7 7.6 4.8 2.4
3 15.6 11.0 7.1 3.5
4 18.8 13.4 8.7 4.2
5 21.3 15.1 9.7 4.7
6 23.8 16.5 10.7 5.2
7 25.2 18.3 11.8 5.8
8 27.0 19.2 12.3 6.1
9 27.9 19.7 12.6 6.2
10 28.6 20.3 13.0 6.4
11 28.6 20.3 13.0 6.4
12 29.0 20.6 13.3 6.4
13 29.6 20.9 13.5 6.6
14 30.4 21.6 13.9 6.8
15 30.4 21.6 13.9 6.8
16-30 33.2 23.5 15.1 7.4
31-50 38.5 27.4 17.5 8.7
51-75 39.8 28.1 18.1 8.9
76-100 44.00 31.2 19.9 9.9
3-441
CG21403 (40K-gate-device) (Main Block)
CL(lu)
1 14.0 9.7 6.8 4.3 2.1
2 21.1 14.4 10.3 6.6 3.2
3 28,2 19.3 13.8 8.8 4.3
4 33.1 22.7 16.1 10.3 5.1
5 36.7 25.2 17.8 11.4 5.7
6 39.5 27.1 19.2 12.3 6.1
7 43.2 29.6 21.1 13.5 6.7
8 45.0 30.9 21.8 14.0 6.9
9 46.2 31.6 22.4 14.4 7.1
10 47.3 32.5 23.0 14.7 7.3
11 47.3 32.5 23.0 14.7 7.3
12 47.9 32.8 23.3 14.9 7.4
13 48.7 33.3 23.7 15.1 7.6
14 49.9 34.2 24.3 15.5 7.7
15 49.9 34.2 24.3 15.5 7.7
16 -30 54.0 37.0 26.3 16.7 8.3
31 -50 61.8 42.4 30.0 19.2 9.5
51 -75 63.6 43.5 30.9 19.7 9.8
76 -100 69.8 47.8 33.8 21.7 10.8
CG21403 (40K-gate-device) (Sub Block)
CL(lu)
1 5.8 4.1 2.7 1.2
2 10.7 7.6 4.8 2.4
3 15.6 11.0 7.1 3.5
4 18.8 13.4 8.7 4.2
5 21.3 15.1 9.7 4.7
6 23.3 16.5 10.7 5.2
7 25.5 18.3 11.8 5.8
8 27.0 19.2 12.3 6.1
9 27.9 19.7 12.6 6.2
10 28.6 20.3 13.0 6.4
11 28.6 20.3 13.0 6.4
12 29.0 20.6 13.3 6.4
13 29.6 20.9 13.5 6.6
14 30.4 21.6 13.9 6.8
15 30.4 21.6 13.9 6.8
16-30 33.2 23.5 15.1 7.4
31 -50 38.5 27.4 17.5 8.7
51 -75 39.8 28.1 18.1 8.9
76 -100 44.0 31.2 19.9 9.9
3-442
CG21S03 (SOK-gate-devlce) (Main Block)
Cdlu)
1 15.7 9.7 6.8 4.3 2.1
2 23.7 14.4 10.3 6.6 3.2
3 31.8 19.3 13.8 8.8 4.3
4 37.3 22.7 16.1 10.3 5.1
5 41.3 25.2 17.8 11.4 5.7
6 44.5 27.1 19.2 12.3 6.1
7 48.7 29.6 21.1 13.5 6.7
8 50.7 30.9 21.8 14.0 6.9
9 51.9 31.6 22.4 14.4 7.1
10 53.3 32.5 23.0 14.7 7.3
11 53.3 32.5 23.0 14.7 7.3
12 53.9 32.8 23.3 14.9 7.4
13 54.8 33.3 23.7 15.1 7.6
14 56.1 34.2 24.3 15.5 7.7
15 56.1 34.2 24.3 15.5 7.7
16-30 60.7 37.0 26.3 16.7 8.3
31-50 69.5 42.4 30.0 19.2 9.5
51-75 71.5 43.5 30.9 19.7 9.8
76-100 78.4 47.8 33.8 21.7 10.8
CG21S03 (SDK-gate-device) (Sub Block)
CL(lU)
1 5.8 4.1 2.7 1.2
2 10.7 7.6 4.8 2.4
3 15.6 11.0 7.1 3.5
4 18.8 13.4 8.7 4.2
5 21.3 15.1 9.7 4.7
6 23.3 16.5 10.7 5.2
7 25.5 18.3 11.8 5.8
8 27.0 19.2 12.3 6.1
9 27.9 19.7 12.6 6.2
10 28.6 20.3 13.0 6.4
11 28.6 20.3 13.0 6.4
12 29.0 20.6 13.3 6.4
13 29.6 20.9 13.5 6.6
14 30.4 21.6 13.9 6.8
15 30.4 21.6 13.9 6.8
16-30 33.2 23.5 15.1 7.4
31-50 38.5 27.4 17.5 8.7
51-75 39.8 28.1 18.1 8.9
76-100 44.0 31.2 19.9 9.9
3-443
CG21 Series Unit Cell Library CMOS Channel/ess Gate Arrays
CG21753 (75-gate-device) (Main Block)
Cdlu)
1 18.8 9.7 6.8 4.3 2.1
2 28.2 14.4 10.3 6.6 3.2
3 37.9 19.3 13.8 8.8 4.3
4 44.5 22.7 16.1 10.3 5.1
5 49.2 25.2 17.8 11.4 5.7
6 53.2 27.1 19.2 12.3 6.1
7 58.1 29.6 21.1 13.5 6.7
8 60.5 30.9 21.8 14.0 6.9
9 62.1 31.6 22.4 14.4 7.1
10 63.7 32.5 23.0 14.7 7.3
11 63.7 32.5 23.0 14.7 7.3
12 64.4 32.8 23.3 14.9 7.4
13 65.4 33.3 23.7 15.1 7.6
14 67.0 34.2 24.3 15.5 7.7
15 67.0 34.2 24.3 15.5 7.7
16-30 72.6 37.0 26.3 16.7 8.3
31 -50 83.0 42.4 30.0 19.2 9.5
51-75 85.4 43.5 30.9 19.7 9.8
76-100 93.8 47.8 33.8 21.7 10.8
CG21753 (75-gate-device) (Sub Block)
CL(lu)
1 5.8 4.1 2.7 1.2
2 10.7 7.6 4.8 2.4
3 15.6 11.0 7.1 3.5
4 18.8 13.4 8.7 4.2
5 21.3 15.1 9.7 4.7
6 23.3 16.5 10.7 5.2
7 25.5 18.3 11.8 5.8
8 27.0 19.2 12.3 6.1
9 27.9 19.7 12.6 6.2
10 28.6 20.3 13.0 6.4
11 28.6 20.3 13.0 6.4
12 29.0 20.6 13.3 6.4
13 29.6 20.9 13.5 6.6
14 30.4 21.6 13.9 6.8
15 30.4 21.6 13.9 6.8
16-30 33.2 23.5 15.1 7.4
31 -50 38.5 27.4 17.5 8.7
51 -75 39.8 28.1 18.1 8.9
76 -100 44.0 31.2 19.9 9.9
3-444
CMOS Channe//ess Gate Arrays CG21 Series Unit Cell Ubrary
CG2ll04 (lOOK- gate-device) (Main Block)
Cdlu)
1 21.9 9.7 6.8 4.3 2.1
2 32.8 14.4 10.3 6.6 3.2
3 44.1 19.3 13.8 8.8 4.3
4 51.8 22.7 16.1 10.3 5.1
5 57.2 25.2 17.8 11.4 5.7
6 61.8 27.1 19.1 12.3 6.1
7 67.6 29.6 21.1 13.5 6.7
8 70.4 30.9 21.8 14.0 6.9
9 72.1 31.6 22.4 14.4 7.1
10 74.0 32.5 23.0 14.7 7.3
11 74.0 32.5 23.0 14.7 7.3
12 75.0 32.8 23.3 14.9 7.4
13 76.1 33.3 23.7 15.1 7.6
14 77.9 34.2 24.3 15.5 7.7
15 77.9 34.2 24.3 15.5 7.7
16-30 84.4 37.0 26.3 16.7 8.3
31-50 96.5 42.4 30.0 19.2 9.5
51-75 99.2 43.5 30.9 19.7 9.8
76 -100 109.0 47.8 33.8 21.7 10.8
CG2l104 (lOOK- gate-device) (Sub Block)
Cdlu)
1 5.8 4.1 2.7 1.2
2 10.7 7.6 4.8 2.4
3 15.6 11.0 7.1 3.5
4 18.8 13.4 8.7 4.2
5 21.3 15.1 9.7 4.7
6 23.3 16.5 10.7 5.2
7 25.5 18.3 11.8 5.8
8 27.0 19.2 12.3 6.1
9 27.9 19.7 12.6 6.2
10 28.6 20.3 13.0 6.4
11 28.6 20.3 13.0 6.4
12 29.0 20.6 13.3 6.4
13 29.6 20.9 13.5 6.6
14 30.4 21.6 13.9 6.8
15 30.4 21.6 13.9 6.8
16-30 33.2 23.5 15.1 7.4
31-50 38.5 27.4 17.5 8.7
51-75 39.8 28.1 18.1 8.9
76-100 44.00 31.2 19.9 9.9
3-445
CG21 Series Unit Cell Ubrary CMOS Channelless Gate Arrays
III
3-446
Appendix D: Available Package Types
Pad. for
Decoupllng 9JA(TYP)
(C°1W)
Package Material Cavity Pin Arrangement Capacllor Device alOmia at3 mI.
CG21103' 80 50
SDIP-64 Plastic None 70 mil Lead Pitch None CG21153' 80 55
CG21203' 85 60
CG211 03' 50 35
PLCC--08 Plastic None 70 mil Lead Pilch None CG21153' 55 40
Gull-wing CG21203' SO 40
CG21103' 50 35
PLCC-64 Plastic None 30 mil Lead Pilch None CG21153' 50 35
CG21103' 80 55
OFP-64 Plastic None 100 mil Lead Pilch None CG21153' 85 SO
Gull-wing CG21203' 90 S5
CG21103' 80 55
OFP-60 Plastic None 0.8 mm Lead Pilch None CG21153' 85 60
CG21103' 80 55
OFP-l00 Plastic None 0.65 mm Lead Pitch None CG21153' 85 60
OFP-120 Plastic None 0.8 mm Lead Pilch None CG21303

Gull-wing CG21403 65 40
CG21503
CG21103'
CG21153' 70 50
CG21203'
OFP-l60 Plastic None 0.65 mm Lead Pitch None CG21303 59 39

Gull-wing CG21403
CG21503
CG21153 70 50
CG21253
OFP-l96" Plastic None TBD None CG21503 TBD TBD

Gull-wing CG21753
CG21104

Gull-wing CG21104
OFP-17S" Plastic None TBD None CG21403 TBD TBD

Gull-wing CG21503
CG21753

Gull-wing CG21503
CG21753
CG21104

Gul~ing
Continued on next page

• planned device
"package under development
3-447
CG21 Series Unit CeN library CMOS Channe//ess Gate Arrays
Appendix D: Available Package Types (Continued)
Pad. lor
Decoupllng 9JA(TYP) (C°1W)
Package Material Cavltv Pin Arrangement Capacitor Device atOm/s 8t3m/s
CG21103'
PGA-64 Ceramic Up 100 m" Pin Pitch Ves CG21153' 40 20
CG21103'
PGA-68 Ceramic Up 100 mil Pin Pitch Ves CG21153' 40 20
CG21303
AIICG21
PGA-I35 Ceramic Up 100 mil Pin Pitch Ves 30 15
Through hole
CG21203' 30 15
CG21303 25 13
PGA-I79 Caramic Up 100 in"Pin Pitch Ves CG21403
CG21753
CG21104
PGA-208 Ceramic Up 100 mil Pin Pitch Ves CG21303

CG21503
CG21753
CG21104
PGA-256 Ceramic Up 100 mil Pin Pitch Ves CG21403

CG21753
CG21104
PGA-299 Ceramic Down 100 m" Pin Pitch Ves CG21503

CG21104
PGA-321 Ceramic Down 70 mil Stagger Ves CG21753 22-24 11-13



Through hole
3-448
Appendix E: TTL 7400 Function Conversion Table
TTL 7400 Number

7400 Quad 2-input NAND 4xN2N 4

7401 Quad 2-input NAND, Open Collector OUtputs T24 multiplexer 6
7402 Quad 2-input NOR 4 xR2N 4
7403 Quad 2-input NAND, Open Collector OUtputs T24 multiplexer 6
7404 Hex Inverter 6xVIN 6
7405 Hex Inverter, Open Collector Outputs R6B 5
7406 Hex Inverter/Buffer, Open Collector Outputs ASB 5
7407 Hex Buffer, Open Collector Outputs 2 x N3N into R2N 5
740B Quad 2-input AND 4xN2P B
7409 Quad 2-input AND, Open Collector Outputs NBP 6
7410 Triple 3-input NAND 3x N3N 6
7411 Triple 3-input AND 3x N3P 9
7412 Triple 3-NAND, Open Collector Outputs T33 7
7413 Dual4-input NAND, Schmitt Trigger 2 x (4 x 12R to N4N) 6B
7414 Hex Schmitt Trigger Inverter 6xl1R 4B
7415 Triple 3-input AND, Open Collector Outputs NBP to N2P B
741B Dual4-input NAND, Schmitt Trigger 2 x (4 x 12R to N4N) 6B
7419 Hex Schmitt Trigger Inverter 6 xl1R 4B
7420 Dual 4-input NAND 2 xN4N 4
7421 Dual 4-input AND 2 xN4P 6
7422 Dual4-input NAND, Open Collector Outputs 2 x N4N + N2P 6
7423 Expanded Dual 4-input NOR with Strobe R4P to 023 + R4P to R2N 9
7424 Quad Schmitt Trigger 2-input NAND 8 x 12R + 4 x N2N 6B
7425 Dual 4-input NOR with Strobe 2 x (R4P + R2N) B
7426 Quad 2-input NAND, High Voltage Output 4 xN2N 4
7427 Triple 3-input NOR 3 xR3N 6
742B Quad 2-input NOR Buffer 4 xR2N 4
7430 B-input NAND NBB 6
7432 Quad 2-input OR 4 xR2P B
7433 Quad 2-input NOR Buffer, Open Collector
Outputs 4 x R2N + N4P 7
7434 Hex Noninverter 6 xB1N 6
7435 Hex Noninverter with Open Collector Outputs 2 x N3N into R2N 5
7437 Quad 2-input NAND Buffer 4 xN2B 12
743819 Quad 2-input NAND Buffer, Open Collector
Outputs 4 x N2N + N4P 7
7440 Dual 4-input NAN 0 Buffer 2 x N4B (N4N if not power) B(4)
7442 BCD to Decimal Decoder 4xV2B+10xN4N 24
7443 EX3 to Decimal Decoder 4xV2B+10xN4N 24
7444 4 to 10 Une Decoder 4xV2B+10xN4N 24
7445 BCD to Decimal Decoder/driver (30V) 4xV2B+10xN4N 24
7446 BCD to 7-segment Decoder/Driver (30V) 4 x V1N + 11 x N2N + 10 x N3N + 4 x N3P + 3 x N2P 53
7447 BCD to 7-segment Decoder/Driver (15V) 4 x V1N + 11 x N2N + 10 x N3N + 4 x N3P + 3 x N2P 53
744B BCD to 7-segment Decoder/Driver 4 x V1N + 11 x N2N + 10 x N3N + 4 x N3P + 3 x N2P 53
7449 BCD to 7-segment, Open Collector Outputs 4 x V1N + 11 x N2N + 10 x N3N + 4 x N3P + 3 x N2P 53
7450 Dual 2-input, 2-wide AOI (One Expandable) 036 + 024 5
7451 AOI 2x 024 4
7452 Expandable 4-wide AN~R N3N + 036 + V1 N into N3N B
7453 Expandable 4-wide AOI 036 + 023 into N2P 7
7454 4-wideAOI 2 x N3N + 2 x N2N + N4N + V1 N 9
7455 2--wide 4--input AOI T42 6
7460 Dual 4--input Expander 2x N4P 6
7461 Triple :Hnput Expander 3x N3P 6
7462 4--wide AND-OR Expander 2 x N3N + 2 x N2N + N4N 8
7464 4-2--3--2 AOI T54 10
7465 4-2--3--2 AOI (Open Collector) T54 10
3-449
CG21 Series Unit CeO Ubrary CMOS Channel/ess Gate Arrays
TTL 7400 Number

Serlea Fujitsu of Unit
Name Function Basic Cella Cella
7470 AND-gated positive-edge JK FF with Preset
and Clear 3 • V1 N + 2 • N3N + N2N + R2N + FJD 21
or: FD4 + 2. N2N + R2N + V1N + R2P + 024 17
7471 AND-gated RS MIS FF with Preset
and Clear FD4 + 2. N3N + 2.023 + 2. V1N 19
or: LT1+ 2. N4N + N2P 10
7472 AND-gated JK MIS FF with Preset
and Clear V1N +2. N3N +N2N + R2N +FJD 19
or: FD4 + N3P + N3N + V1N + 024 17
7473 Dual JK FF with Clear 2. FJD 24
7474 Dual positive-edge D-FF with Preset and
Clear 2. FOP 16
7476 Dual JK FF with Preset and Clear 2. (FJD + N2N + R2N + V1N) 30
7478 Dual JK FF with Preset and Common 2. (FJD + N2N + R2N + V1N) 30
Clear and Clock
7480 Gated Full Adder A1N 8
7482 2-bit Binary Full Adder A2N 16
7483 4-bit Binary Full Adder with Fast Carry A4H 48
7484 4-bit Magnitude Comparator MC4 42
7486 Quad 2-input XOR 4.X2N 12
7487 4-bit True/Complement ZerolOne Element 4. N2N + V1N +4. N2N 17
7489 64-bit (16.4) Memory 2. DE6 + V1 N + 16. LT4 298
0" 7490
7491
Decade Counter
(Different Implementation)
B-bit Shift Register
+ 5. (V2B + TSA) + 10. V2B
2 .(FDP + FDO + N2P + N2N + R2N) + V1N
4.N2P+2.R2P+N2N+C41 +LT1
2.FDS+V1N
39
41
41
7492 Divide-by-12 Counter 4 .FDO+2. V1N +2.R2N + N2N 33
7493 4-bit Binary Counter C41 + N2N (for the resets) 25
7494 4-bit Shift Register, 2 asynchronous Presets FS3 34
4-bit Shift Register, 2 asynchronous
Presets, Full Implementation 4. FOP + 4.024 + 2. V1N 42
7495 4-bit Parallel-access Shift Register FS2 + 024 + 2. V1N 34
7496 5-b~ Shift Register 5 • FOP + 5 • N2N + V1 N(clock) 46
7497 Synch 6-bit Binary Rate Multiplier FOR + 2. FDO +3. V1N + 2. N2N 122
+ 2. N3N + 2. N4N +5. N6B+3. N8B
+ R2B +X2N + 5. X1B.
7498 4-bit Data SelectoriStorage Register FDQ + T2F +4 .V1N 33
7499 4-bit Universal Shift Register FS2 + LTK + 2.024 + 4. V1N 42
74100 B-bit Bistable Latch 2.YL4 + 2.V1N 30
74101 AO-gated JK Negative-Edge FF,
with Preset FD3 + V1N + 3.024 15
74102 AND-gated JK Negative-Edge FF with
Preset and Clear FD4 + 024 + N3P + N3N 16
74103 Dual JK FF with Clear 2. FJD + 2. V1 N (for clock) 26
or: 2. (FD5 + 024 + V1N) 22
and Clear 2. (FD4 + 024 + V1N) 24
74107 Dual JK FF with Clear 2. (FJD + 2. V1N) 22
and Common Clear and Clock 2. (FD4 + 024 + V1N) 24
74109 Dual JK Positive-Edge FF with Preset and
Clear 2. (FOP + V1N + 024) 22
74110 AND-gated JK MIS FF with Data
Lockout FOP + 024 + N3P + N3N 15
74111 Dual JK MIS FF with Data Lockout 2. (FOP + 024 + V1N) 22
and Clear 2. (FD4 + 024 + V1N) 24
3-450
CMOS Channel/ess Gate A""ys CG21 Series Unit Cen Ubtary
Appendix E: TIL 7400 Function Conversion Table (Continued)
TTL 7400 Number

Name FunctIon BasleCells Cells
74113 Dual JK Negative-Edge FF with Preset 2 x (FD3 + D24 + V1N) 22

74114 Dual JK Negative-Edge FF with Preset and
Common Clear and Clock 2 x (FD4 + D24 + V1N) 24
74116 Dual 4-bit Latch with Clear 2xLTM 32
74120 Dual Pulse Synchronizer/Driver 2 x (N2P + LT1 + 4 x N3N + 2 x N2N + 2 x VI N) 36
74125 Quad Bus Buffer with ~tate Output 841 9
74126 Quad Bus Buffer with ~tate Output 841 + 4x V1N 13
74132 Quad 2--input NAND Schmitt Trigger 4 x (2 x 12R + N2N) 68
74133 13--inputNAND 2 x N4N + N3N + N2N into R4P 10
74134 12--input NAND with 3-state Outputs NCB+04R 15
74135 Quad 3--input EXORlEXNOR 4xX4N 20
74136 Quad 2--input EXOR with Open-Collector
Outputs 4xX2N+R4N 14
74137 3-line to 8-line Decoder with Address
Latch 3 x LTK into DE6 42
74138 3-line to 8-line Decoder with Enable DE6 30
74139 Dual 2-line to 4-line Decoder 2x DE4 16
74141 BCD-to-Decimal Decoder 4xV2B+l0xN4N 24
74145 BCD-to-decimal Decoder 4 x V1N + 10 x N4N 24
74147 1<Hine to 4-line BCD Priority Encoder 3 x N4N + 3 x N3N + 2 x N2N + 2 x N2P 36
+ 3 x R2N + R4N + 13 x Vl N
74148 8-line to 3-line Octal Priority Encoder N9B + 2 x N2N + R2P + R4N + 4 x N3N 40
+ 2x N4N + G44 + 12 x V1N
74150 1-10-16 Multiplexer DE3 + 2 x U28 + D24 + 2 x Vl N 41
III
74151 1-4cH1 Multiplexer with Strobe DE3 + U28 + N2N + V1N 28
74152 1-4cH1 Multiplexers DE3 + U28 26
74153 Dual4-lioo to l-line Selector/Multiplexer DE2 +2x U24 + 2xR2N 19
74154 4-lioo to 18-line Decoder/Demultiplexer 2 x DE6 + V1N 61
or: 2 x DE4 + N2P + 16 x R2P 50
74155 Dual 2-line to 4-lioo Decoder/Demultiplexer
(Totem Pole) 8 x N3N + 2 x R2N + 5 x Vl N 23
(Open Collector) 8 x N3N + 2 x R2N + 5 x Vl N 23
74157 Quad 2-line to l-line multiplexer T2F + 4 x R2N + BIN 13
74158 Quad 2-line to l-line multiplexer
(Inverter Data Outputs) 4 x D24 + V1N + 2 x R2N 11
74159 4-line to 18-line Demultiplexer 2 x DE6 + V1N (without open collector) 50
74160 Synchronous 4-bit Counter 4xCll + K1B+ 2 xV2B +V1N + B1N+ 62
(Decimal with Direct Clear) N2K + 2 x R3N + R4N + 3 x R2N + N2N
with Direct Clear) C43 48
74162 Synchronous 4-bit Counter
(Decimal with Synchronous Clear) C45 + D36 + N3P + 2 x R2N + BIN 57
with Synchronous Clear) C45 48
74164 8-bit Parallel Output Serial Shift
Register, Asynchronous Clear 2 x FDR + N2P 54
74165 B-bit Shift Register 2 x FDS + 8 x D24 + 11 x V1N + K4B + R2P 71
74166 8-bit Shift Register 2 x FDR + 8 x D24 + lOx Vl N + K4B 80
(Decade) 4 x Cll + 4 x T32 + 7 x N2N + 2 x N3N + R2N 85
+7xV2B+K1B
(Binary) C47 68
74170 4-by-4 Register File 4 x (YL4 + BIN + V1N + U24) + 2 x DE4 104
74171 Quad D-FF with Clear FDR+4xV1N 30
74172 16-bit (8 x 2) Register File 3 x DE6 + 4 x FDS + 16 x (N2N + G34 + 348
+ VI N + 2 x R2P + 4 x U28) + 2 x VI N + 2 x R2P
3-451
CG21 Series Unit Cel/ Ubrary CMOS Channel/ess Gate AITBYs
TTL 7400 Number

74173 ~it D-type Register

(3-stale Output) FOR + 2 x R2N + 841 + 6 x VI N + Kl B + 4 x 024 53
74174 Hex D-FF (Single Output) FDR+2xFDO 40
74175 Quad D-FF (with Clear) FDR+4xV1N 30
74176 Presettable Decade/Binary Counter 4 x FOP + 2 x R2N + 5 x N2N + 4 x N3N + Kl B 49
74177 Presettable Binary Counler 4 x FOP + 5 x N2N + 4 x N3N + KIB 47
74178 4-bit Universal Shift Regisler FS2 30
74179 ~it Universal Shift Register
(Direct Clear) FS2 + 9 x N2N + Bl N 40
74180 9-bit OddIEven Parity Checker P08 +2 x 024+ VIN 23
74181 ALUIFunction Generator 5 x VIN + 5 x T32 + 4 x 036 + 8 x X2N + 3 x T54 +
N6B + N4B + 2 x N2N + 2 x N4P 113
74182 Look-ahead Carry Generator R4P + 2 x VIN + 2 x T44 + T33 + 024 36
74183 Dual Carry-save Full Adder 2xA1N 16
74184 BCD-to-binary Code Converler These devices are ROM based
74185 Binary-to-BCD Code Converler These devices are ROM based
74190 Synch Up/Down Counler (BCD) 4 x FOP + 4 x X2N + KIB + 3 x VIN + 3 x N3N
+ 9 x N2N + 2 x T32 + T43
74191 Synch Up/Down Counter (Binary) C47 68
74192 Up/Down Dual Clock Counler (BCD) 4 xCII + 4 x V2B + N6B + 2 x N3N + R2N 79
+T32+T42+T43
DI
74193 Up/Down Dual Clock Counter (Binary) 4 xCII + 2 x N6B + 4 x V2B + R2N + 024 + T32 72
+ T42
74194 4-bit Bidirectional Universal Shift Register FOR + 6 x VIN + R2N + 4 x 036 + 023 + BIN 48
74195 4-bit Parallel Access Shilt Regisler FS2 + 024 + 2 x VIN 34
74196 Preset Decade/Binary Counter/Latch 4 x FOP + 2 x R2N + 5 x N2N + 4 x N3N + Kl B 49
74197 Preset Binary Counler/Latch 4 x FOP + 5 x N2N + 4 x N3N + KIB 47
74198 &-bit Bidirectional Universal Shift Register 2 x FOR + 024 + 10 x VI N + R2N + 8 x 036 89
74199 &-bit Bidirectional Universal Shift
Register (JK Serial Input) 2 x FS2 + 024 + 3 x VI N + BIN + R2N + 8 x N2P 83
or: 2 x FOR + 7 x 024 + T33 + 11 x VI N + R2N 85
74246 BCD-to-7-·Segment Decoder/Driver
(30V, Active Low Open Collector) 4 x VI N + 11 x N2N + 10 x N3N + 4 x N3P + 3 x N2P 53
(15V, Active Low Open Collector) 4 x VIN + 11 • N2N + 10 x N3N + 4 x N3P + 3. N2P 53
(Internal Pull-up) 4xV1N + 11. N2N + lOx N3N + 4. N3P + 3x N2P 53
(Open Collector) 4 x VI N + 11 x N2N + 10 x N3N + 4. N3P + 3 x N2P 53
74280 Dual 5-input NOR 2xR6B 10
74265 Quad Complementary Output Element BIN + VIN
74266 Quad 2-EXNOR, Open Collector 4 xX1N 12
74273 Octal D-type FF with Clear 2xFDR 52
74276 Quad J-K FF 4 x (FOP + VI N + 024) + 2 x Bl N 46
74347 BCD-to-7-Segment Decoder/Driver 4 x VI N + 11 • N2N + 10 • N3N + 4 x N3P + 3 x N2P 53
3-452
CMOS Channe//ess Gate Arrays CG21 Series Unit CeY Ubrary
Appendix F: Alphanumeric Index of Unit Cells
A1A 1-bit HaH Adder 3-253

A4H 4-bit Binary Full Adder with Fast Carry 3-257
BD3 Delay Cell 3-10
BD4 Delay Cell 3-11
BD5 Delay Cell 3-12
BD6 Delay Cell 3-13
B1N True Buffer 3-9
C11 Non-Scan Flip-flop for Counter 3-231
C41
C42
C43
Non-Scan 4-bit Binary Asynchronous Counter
Non-Scan 4-bit Binary Synchronous Counter
Non-Scan 4-bit Binary Synchronous Up Counter
3-233
3-236
3-239
1m
C47 Non-Scan 4-bit Binary Synchronous Up/Down Counter 3-247
D14 2-wide 3-AND 4-lnput ADI 3-68
D44 3-wide 2-DR 2-AND 4-lnput ADI 3-72
FDM Non-Scan D Flip-flop 3-183
FDN Non-Scan D Flip-flop with Set 3-185
FDD Non-Scan D Flip-flop with Reset 3-187
FDP Non-Scan D Flip-flop with Set and Reset 3-189
FDO Non-Scan 4-bit D Flip-flop 3-192
FDR Non-Scan 4-bit D Flip-flop with Clear 3-194
FDS Non-Scan 4-bit D Flip-flop 3-197
FD2 Non-Scan Power D Flip-flop 3-199
FD3 Non-Scan Power D Flip-flop with Preset 3-201
3-453
CG21 Series Unit Cel/ Library CMOS Channel/ess Gate Arrays
FD4 Non-Scan Power D Flip-flop with Clear and Preset 3-203

FD5 Non-Scan Power D Flip-flop with Clear 3-205
FJD Non-Scan Positive Edge Clocked Power J-K FK with Clear 3-207
FS1 4-bit Serial-in Parallel-<lut Shift Register 3-279
FS2 4-bit Shift Register with Synchronous Load 3-281
FS3 4-bit Shift Register with Asynchronous Load 3-283
G44 2-wide 2-AND 2-0R 4-lnput OAI 3-79
H6C 3-state Output (IOL = 3.2 rnA) and CMOS Interface Input Buffer (True) 3-398
H6CF 3-state Output and CMOS Interface Input Buffer (IOL = 8 mA,True) 3-401
H6CFD H6CF with Pull-down Resitance 3-403
III H6E
H6ED
HSEU
Power 3-state Output (IOL = 12 rnA) and CMOS Interface Input Buffer (True)
H6E with Pull-down Resistance
H6E with Pull-up Resistance
3-404
3-406
3-405
HSR 3-state Output (IOL = 3.2 rnA) and Schmitt Trigger Input Buffer (TTL type, True) 3-410
HSRD H6R with Pull-down Resistance 3-412
HSRU H6R with Pull-up Resistance 3-411
HSS 3-state Output (IOL = 3.2 rnA) and Schmitt Trigger Input Buffer (CMOS type, True) 3-407
HSSD H6S with Pull-down Resistance 3-409
HSSU H6S with Pull-up Resistance 3-408
HST 3-state Output (IOL = 3.2 rnA) and Input Buffer (True) 3-389
HSTD H6T with Pull-down Resistance 3-391
HSTF 3-state Output and Input Buffer (IOL = 8 rnA, True) 3-392
HSTFD H6TF with Pull-down Resistance 3-394
HSTFU HSTF with Pull-up Resistance 3-393
HSTU H6T with Pull-up Resistance 3-390
HSW Power 3-state Output (IOL = 12 rnA) and Input Buffer (True) 3-395
HSWD H6W with Pull-down Resistance 3-397
HSWU H6W with Pull-up Resistance 3-396
H8C 3-state Output Buffer (IOL =3.2 rnA) with Noise Limit Resistance and CMOS
Interface Input Buffer (True) 3-422
H8CF 3-state Output Buffer with Noise Limit Resistance and CMOS
Interface Input Buffer (IOL = 8 rnA, True) 3-425
H8CFD H8CF with Pull-down Resistance 3-427
3-454

H8E Power 3-state Output Buffer (IOl = 12 rnA) wHh Noise Limit Resistance and
CMOS Interface Input Buffer (True) 3-428
H8ED H8E with Pull-down Resistance 3-430
H8EU H8E with Pull·up Resistance 3-429
H8R 3·state Output and Schmitt Trigger Input Buffer (TTL type, True)
H8RD H8R with Pull·down Resistance 3-436
H8RU H8R with Pull-up Resistance 3-435
H8S 3-state Output and Schmitt Trigger Input Buffer (CMOS type, True)
H8SD H8S with Pull-down Resistance 3-433
H8T 3-state Output with Noise Limit Resistance and Input Buffer (True) 3-413
H8TF 3-state Output with Noise LimH Resistance and Input Buffer (IOl = 8 mA, True) 3-416
H8TFU H8TF with Pull-up Resistance 3-417
H8TU
H8W
H8T with Pull-up Resistance
Power 3-state Output with Noise Limit Resistance and Input Buffer (True)
3-414
3-419
III
H8WU H8W wHh Pull-up Resistance 3-420
IKB Clock Input Buffer (Inverter) 3-341
IKBD IKB with Pull-down Resistance 3-343
IKBU IKB with Pull-up Resistance 3-342
IKC CMOS Interface Clock Input Buffer (Inverter) 3-344
IKCD IKC with Pull-down Resistance 3-346
IKCU IKC with Pull-up Resistance 3-345
ILB Clock Input Buffer (True) 3-347
ILBD ILB with Pull-down Resistance 3-349
ILBU ILB with Pull-up Resistance 3-348
ILC CMOS Interface Clock Input Buffer (True) 3-350
ILCD ILC with Pull-<lown Resistance 3-352
ILCU ILC with Pull-up Resistance 3-351
11B Input Buffer Inverter 3-335
11BD 11 B with Pull-down Resistance 3-337
11BU 11 B with Pull-up Resistance 3-336
11C CMOS Interface Input Buffer (Inverter) 3-353
11CD 11C with Pull-<lown Resistance 3-355
11CU 11C with Pull-up Resistance 3-354
11R Schmitt Trigger Input Buffer (TTL Type, Inverter) 3-365
11RD 11 R with Pull-down Resistance 3-367
3-455
CG21 Series Unit Cell Library CMOS Channe/less Gate Arrays
11RU 11 R with Pull·up Resistance :M166

11S Schmitt Trigger Input Buffer (CMOS Type, Inverter) 3-359
11SD 11S with Pull·down Resistance :M160
11SU 11S with Pull-up Resistance :M161
12B Input Buffer (True) 3-338
12BD 12B with Pull-down Resistance :M140
12BU 12B with Pull-up Resistance :M139
12C CMOS Interface Input Buffer (True) :M156
12CD 12C with Pull-down Resistance :M158
12CU 12C with Pull-up Resistance :M157
12R Schmitt Trigger Input Buffer (TTL Type, True) :M168
12RD 12R with Pull-down Resistance :M170
12RU 12R with Pull-up Resistance :M169
12S Schmitt Trigger Input Buffer (CMOS Type, True) :M162
12SD 12S with Pull-down Resistance :M164
12SU 12S with Pull-up Resistance 3-363
KAB Block Clock (OR) Buffer 3-110
0 KBB
KDB
KEB
Block Clock Buffer(OR x 10)
Block Clock Buffer(OR x 10)
Block Clock Buffer
3-111
3-113
3-115
K1B True Clock Buffer 3-105
K2B Power Clock Buffer 3-106
K3B Gated Clock (AND) Buffer 3-107
K4B Gated Clock (OR) Buffer 3-108
K5B Gated Clock (NAND) Buffer 3-109
LTK Data Latch 3-265
LTL 1-bit Data Latch with Clear 3-267
LTM 4-bit Data Latch with Clear 3-269
LT1 S-R Latch with Clear 3-272
LT4 4-bit Data Latch 3-274
MC4 4-bit Magnitude Comparator 3-315
NCB Power 12-lnput NAND 3-27
NGB Power 16-lnput NAND 3-28
N2K Power 2-lnput NAND 3-19
3-456
CMOS Channe/less Gate Arrays CG21 Series Unit Cell Ubrary

01B Output Buffer (IOl = 3.2 rnA, Inverter) 3-371
01BF Output Buffer (IOl = 8 rnA, Inverter) 3-372
01L Power Output Buffer (IOl = 12 mA, Inverter) 3-373
01R Output Buffer (IOl = 3.2 rnA, Inverter) with Noise Limit Resistance 3-374
01RF Output Buffer (IOl = 8 rnA, Inverter) with Noise Limit Resistance 3-375
01S Power Output Buffer (IOl = 12 mA, Inverter) with Noise Limit Resistance 3-376
02B Output Buffer (IOl = 3.2 rnA, True) 3-377
02BF Output Buffer (IOl = 8 rnA, True) 3-378
02L Power Output Buffer (IOl = 12 rnA, True) 3-379
02R Output Buffer (IOl = 3.2 rnA, True) with Noise Limit Resistance 3-380
02RF Output Buffer (IOl = 8 rnA, True)with Noise Limit Resistance 3-381
02S
04R
04RF
Power Output Buffer (IOl = 12 rnA, True) with Noise Limit Resistance
3-state Output Buffer (IOl = 3.2 rnA, True) with Noise Limit Resistance
3-state Output Buffer (IOl = 8 rnA, True) with Noise Limit Resistance
3-382
3-386
3-387
IE
04S Power 3-state Output Buffer (IOl = 12 rnA, True) with Noise Limit Resistance 3-388
04T 3-state Output Buffer (IOl = 3.2 rnA, True) 3-383
04TF 3-state Output Buffer (IOl = 8 rnA, True) 3-384
04W Power 3-state Output Buffer (IOl = 12 rnA, True) 3-385
P24 4-wide 2:1 Data Selector 3-297
RCB Power 12-lnput NOR 3-41
RGB Power 16-lnput NOR 3-42
R2K Power 2-lnput NOR 3-33
3-457
CG21 Series Unit Cen Librarv CMOS Channel/ess Gate Arrays

SC7 Scan 4-bit Synchronous Binary Up Counter with Parallel Load 3-211
SC8 Scan 4-bit Synchronous Binary Down Counter with Parallel Load 3-216
SC43 Scan 4-bit Synchronous Binary Up Counter with Asynchronous Clear 3-221
SC47 Scan 4-bit Synchronous Binary Up/Down Counter 3-225
SOA Scan 1-lnput 0 Flip-flop with Clock Inhibit 3-137
SOB Scan 1-lnput 4-bit 0 Flip-flop with Clock Inhibit 3-140
SOD Scan 2-lnput 0 Flip-flop with Clear, Preset, and Clock Inhibit 3-133
SOH Scan 2-lnput 0 Flip-flop with Clear and Clock Inhibit 3-121
SOJ Scan 4-lnput 0 Flip-flop with Clear and Clock Inhibit 3-124
SDK Scan 6-lnput 0 Flip-flop with Clear and Clock Inhibit 3-127
SFDM Scan 1-lnput 0 Flip-flop with Clock Inhibit 3-159
OIl SFDO
SFDP
SFOR
Scan 1-lnput 0 Flip-flop with Clear and Clock Inhibit
Scan 1-lnput 0 Flip-flop with Clear, Preset, and Clock Inhibit
Scan 4-lnput 0 Flip-flop with Clear and Clock Inhibit
3-162
3-165
3-169
SFOS Scan 4-lnput 0 Flip-flop with Clock Inhibit 3-173
SFJO Scan J-K Flip-flop with Clock Inhibit 3-177
SHA Scan 1-lnput 8-bit 0 Flip-flop with Clock Inhibit 3-144
SHB Scan 1-lnput 8-bit 0 Flip-flop with Clock Inhibit and Q Output 3-147
SHC Scan 1-lnput 8-bit D Flip-flop with Clock Inhibit and XQ Output 3-150
SHJ Scan 8-bit 0 Flip-flop with Clock Inhibit and 2-to-1 Data Multiplexer 3-153
SHK Scan 8-bit D Flip-flop with Clock Inhibit and 3-10-1 Data Multiplexer 3-156
SJH Scan J-K Flip-flop with Clear and Clock Inhibit 3-130
SR1 Scan 4-bit Serial-in Parallel-out Shift Register with Scan 3-286
T2B 2:1 Selector 3-304
T2C Dual 2:1 Selector 3-305
T2D 2:1 Selector 3-307
T2E Dual 2:1 Selector 3-308
T2F 2:1 Selector 3-309
T24 Power 2-ANO 4-wide Multiplexer 3-83
3-458

T54 Power 4-2-3-2 AND 4-wide Multiplexer 3-93
T5A 4:1 Selector 3-311
V1L Inverting Clock Buffer 3-117
V1N Inverter 3-7
V2B Power Inverter 3-8
V3A 1 :2 Selector 3-313
V3B
X1B
X1N
Dual 1 :2 Selector
Power Exclusive NOR
Exclusive NOR
3-314
3-58
3-57
III
X2B Power Exclusive OR 3-60
X2N Exclusive OR 3-59
X3B Power 3-lnput Exclusive NOR 3-62
X3N 3-lnput Exclusive NOR 3-61
X4B Power 3-lnput Exclusive OR 3-64
X4N 3-lnput Exclusive OR 3-63
ZOO oClip 3-329
Z01 1 Clip 3-330
3-459
CG21 Series Unit CaU Libmry CMOS Channa/less Gate Arrays
3-460
Section 4
Sales Information
I Page Contents
4-3 Introduction to Fujitsu
4-7 Integrated Circuits Corporate Headquarters - Worldwide
4-a FMI Sales Offices for North and South America
4-9 FMI Representatives - USA
4-11 FMI Representatives - Canada
4-11 FMI Representatives - Mexico
4-11 FMI Representatives - Puerto Rico
4-12 FMI Distributors - USA
4-16 FMI Distributors - Canada
4-17 FMG Sales Offices for Europe
4-18 FMG Distributors - Europe
4-20 FMA Sales Offices for Asia and Australia
4-21 FMA Representatives - Asia and Australia
4-22 FMA Distnbutors - Asia and Australia
III
Sales Information CMOS Channel/ess Gate Arrays
4-2
CMOS Channelless Gate Arrays Sales Information
Introduction to Fujitsu
Fujitsu Limited
Fujitsu Limited, headquartered near Tokyo, Japan, is the largest

supplier of computers in Japan and is among the top ten
companies operating in Japan. Fujitsu is also one of the world's
largest suppliers of telecommunications equipment and
semiconductor devices.
Established in 1935 as the Communications Division spinoff of

Fuji Electric Company Limited, Fujitsu Limited, in 1985,
celebrated 50 years of service to the world through the develop-
ment and manufacture of state-of-the-art products in data
processing, telecommunications and semiconductors.
Fujitsu has five plants in key industrial regions in Japan covering

all steps of semiconductor production. Five wholly-owned
Japanese subsidiaries provide additional capacity for production
of advanced semiconductor devices. Two additional facilities
operate in the U.S. and one in Europe to help meet the growing
worldwide demand for Fujitsu semiconductor products.
4-3
Sales ·Information CMOS Channe/less Gale Arrays
Introduction to Fujitsu (Continued)

Fujitsu Microelectronics, Inc. (FMI), with headquarters in San
Jose, California, was established in 1979 as a wholly-owned
Fujitsu Limited subsidiary for the marketing, sales, and distribu-
tion of Fujitsu integrated circuit and component products. Since
1979, FMI has grown to three marketing divisions, two manufac-
turing divisions and a subsidiary. FMI offers a complete array of
semiconductor products for its customers.
The Advanced Products Division (APD) is responsible for the

complete product development cycle, from design through
operations support and worldwide marketing and sales. Products
are the result of both internal development and external
relationships, such as joint development agreements, technology
licenses, and joint ventures. The SPARCTM RISC processor was
developed by both APD and Sun Microsystems, Inc.
In addition to designing and selling a full line of SPARC

processors and peripheral chips, APD also designed and is
selling the EtherStar™ LAN controller - the first VLSI device to
integrate both StarLAN'M and Ethernet® protocols into one
device. The core of APD's EtherStar chip was the result of APD's
cooperative venture with Ungermann-Bass.
The Microwave and Optoelectronics Division (MOD) markets

GaAs, FETs, and FET power amplifiers, lightwave and micro-
wave devices, optical devices, emitters, and SI transistors.
The largest FMI marketing division is the Integrated Circuits

Division (ICD).
Memory and programmable devices marketed by ICD include the

following:
DRAMs and DRAM Modules

EPROMs
EEPROMs
NOVRAMs
CMOS masked ROMs
CMOS SRAMs and CMOS SRAM Modules
BiCMOS SRAMs
Bipolar PROMs
ECLRAMs
STRAMs (seH-timed RAM)
Hi-Rei PROMs and SRAMs
Ultra High-speed ECUECL-TIL Translator Circuits
Linear ICs and Transistors
4-4
CMOS Channelless Gate Arrnys Sales Information
ASIC products offered by ICD include the following:
CMOS, ECl, and BiCMOS gate arrays

CMOS standard cells
Design Software Support
Customer support and customer training for ASIC products are

available through the following FMI design centers:
San Jose Gresham

Dallas Chicago
Atlanta Boston
Microcomputer and communications products offered by ICD

include the following:
4-bit MCUs
8- and 16-bit MPUs
SCSI and controllers
DSPs
Prescalers
PLLs
Memory Cards
FMI's manufacturing divisions are in San Diego, California and

Gresham, Oregon. The San Diego Manufacturing Division
assembles and tests memory devices. In 1988, the Gresham
Manufacturing Division began manufacturing ASIC products and
DRAM memories. This facility, when completed, will have one
million square feet of manufacturing-the largest Fujitsu
manufacturing plant outside Japan.
FMl's subsidiary, FujHsu Components of America, markets

connectors, keyboards, plasma displays, relays, and hybrid ICs.
Fujitsu Mlkroelektronlk GmbH (European Sales Operation)
Fujitsu Mikroelektronik GmbH (FMG) was established in June,

1980, in Frankfurt, West Germany, and is a wholly-owned
subsidiary of Fujitsu Limited, Tokyo. FMG is the sole representa-
tive of the Fujitsu Electronic Device Group in Europe. The wide
range of ICs, lSI memories, microprocessors, and ASIC
products are noted throughout Europe for design excellence and
unmatched reliability. Branch offices are located in Munich,
London, Paris, Stockholm, and Milan.
4-5
Sales Information CMOS Cflanne/less Gate A"ays

Fujitsu Microelectronics Ireland, Ltd. (European Production Operation)
Fujitsu Microelectronics Ireland, Ltd. (FME) was established in
1980, in the suburbs of Dublin, as Fujitsu's European Production
Center for integrated circuits. FME assembles DRAMs,
EPROMs, and other LSI memory products.
Fujitsu Microelectronics, Ltd. (European ASIC Design Operation)

Fujitsu Microelectronics, Ltd., Fujitsu's European VLSI Design
Center, opened in October of 1983 in Manchester, England. The
Design Center is equipped with highly sophisticated CAD
systems to ensure fast and reliable processing of input data. An
experienced staff of engineers is available to assist in all phases
of the design process.
Fujitsu Microelectronics Asia PTE Ltd. (Asian/Oceanian Sales Operation)

Fujitsu Microelectronics Asia PTE Ltd. (FMA) opened in August
1986 in Hong Kong as a wholly-owned Fujitsu subsidiary for
sales of electronic devices to Asian and Southwest Pacific
markets.
SPARe· 18 a trademark 01 Sun Mlaosyaten. Inc.

EIh........ '''111_ trademark 01 Xerox ~"Ion.
EtherStar1lll1a a trademark of Fujitsu MlcroaIed:ronlca. Inc.
StarlANlM II a trademark of AT&T.
4-6
CMOS Channs/less Gate Arrays Sales Information
Integrated Circuits Corporate Headquarters - Worldwide
International Corporate Headquarters

FUJITSU LIMITED
Marunouchi Headquarters
6-1, Marunouchi l-d1ome
Chiyoda-ku, Tokyo 100
Japan
Tel: (03) 216-3211
Telex: 781-22833
FAX: (03) 213-7174
For Integrated circuits marketing information please contact the following:
Headquarters for Japan

FUJITSU LIMITED
Integrated Circuits and Semiconductor Marketing
Furukawa Sogo Bldg.
6-1, Marunouchi 2-dlome
Chiyoda-ku, Tokyo 100
Japan
Tel: (03) 216-3211
Telex: 781-2224361
FAX: (03) 211-3987
Headquarters for North and South America

FUJITSU MICROELECTRONICS, INC.
Integrated Circuits Division
3545 North First Street
San Jose, CA 95134-1804
USA
Tel: (408) 922-9000
Telex: 910--338-0190
FAX: (408) 432-9044
Headquarters for Europe

FUJITSU MIKROELEKTRONIK GmbH
Lyoner Strasse 44-48
Arabella Centre 9. OG
~ Frankfurt 71
Federal Republic of Germany
Tel: (069) 66320
Telex: 441963
FAX: (069) 6632122
Headquarters for Asia and Australia

FUJITSU MICROELECTRONICS ASIA PTE LIMITED
06-04106-07 Plaza by the Park
No. 52 Bras Basah Road
Singapore 0718
Tel: (65) 336-1600
Telex: 55573
FAX: (65) 336-1609
4-7
Fujitsu Microelectronics, Inc. (FMI) Sales Offices for

North and South America
NORTHERN CALIFORNIA ILLINOIS (Chicago) NEW YORK (Hauppauge)

Fujitsu Microelectronics, Inc. Fujitsu Mcroeiectronics, Inc. Fujitsu Microelectronics, Inc.
10600 N. De Anza Blvd. One Pierce Plaoe 601 Velerans Memorial Highway
Suite 225 Suile 910 Suite P
Cupertino, CA 95014 Itasca, IL 60143-2681 Hauppauge, NY 11788-1054
Tel: (408) 996-1600 Tel: (708) 250-8580 Tel: (516) 361--6565
FAX: (408) 72lH1746 FAX: (708) 250-8591 FAX: (516) 361--6480
SOUTHERN CALIFORNIA MASSACHUSETTS (Boston) OREGON (Portland)

Fujitsu Microelectronics, Inc. Fujitsu Microeiectronics, Inc. Fujitsu Microelectronics, Inc.
Century Centre 75 Wells Avenue 5285 SW Meadows Road
2603 Main Street Suile5 Suile222
Suite 510 Newton Center, MA 02159--3251 Lake Oswego, OR 97035-9998
Irvine, CA 92714 Tel: (617) 964-7080 Tel: (503) 684-4545
Tel: (714) 724-8777 FAX: (617) 964-3301 FAX: (503) 684-4547
FAX: (714) 724-8778
MINNESOTA (Minneapolis) TEXAS (Dallas)
COLORADO (Denver) Fujitsu Microelectronics, Inc. Fujitsu Microelectronics, Inc.
Fujitsu Microelectronics, Inc. 3460 Washington Drive 14785 Preston Road
5445 DTC Parkway Suile 209 Suile 670
Suite 300 Eagan, MN 55122-1303 Dallas, TX 75240
Englewood, CO 80111 Tel: (612) 454-0323 Tel: (214) 233-9394
Tel: (303) 74D-8880 FAX: (612) 454-{)601 FAX: (214) 386-7917
FAX: (303) 740-8988
NEW JERSEY (MI. Laurel)
GEORGIA (Atlanta) Fujitsu Microelectronics, Inc.
Fujitsu Microelectronics, Inc. Horizon Corporate Cenler
3500 Parkway Lane 3000 Atrium Way
g Suite 210
Norcross, GA 30092
Tel: (404) 449-8539
FAX: (404) 441-2016
Suile 100
MI. Laurel, NJ 08054
Tel: (609) 727-9700
FAX: (609) 727-9797
4-8
CMOS Channe//ess Gate A"eys Se/es Information
FMI Representatives - USA

For product information, contact your nearest Representative.
Alabama Connecticut Indiana

The Nows Group, Inc. Conntech Sales, Inc. Fred Dorsey & Associates
2905 Westcorp Blvd. 182 Grand Street 3518 Eden Place
Suite 120 Suite 318 Carmel, IN 46032
Huntsville, AL 35805 Waterbury, CT 06702 Tel: (317) 8~842
Tel: (205) 534-0044 Tel: (203) 754-2823 FAX: (317)~843
FAX: (205) 534-{)186 FAX: (203) 57:Hl538
Iowa
Arizona Florida Electromec Sales
Aztech Component Sales Inc. Semtronic Associates, Inc. 1500 2nd Avenue
15230 N 75th Street 657 Mailland Avenue Suite 205
Suite 1031 Altamonte Springs, FL 32701 Cedar Rapids, IA 52403
Scottsdale, AZ 85260 Tel: (407) 831~233 Tel: (319) 362-0413
Tel: (602) 991-6300 FAX: (407) 831-2844 FAX: (319) 362-0535
FAX: (602) 991-0563
Semtronic Associates, Inc.
1467 S. Missouri Avenue Kansas
California Clearwater, FL 33516 Rothkopf & Associates, Inc.
Harvey King, Inc. Tel: (813) 461-<1675 1948 E. Santa Fe
6393 Nancy Ridge Drive FAX: (813) 442-2234 SuiteH
San Diego, CA 92121 Olathe, KS 66062
Semtronic Associates, Inc.
Tel: (619) 587--9300 Tel: (913) 8~897
3471 NW 55th Street
FAX: (619) 587-0507 FAX: (913) 829-1664
Ft. Lauderdale, FL 33309
Infinity Sales, Inc. Tel: (305) 731-2484
4500 Campus Drive FAX: (305) 731-1019 Maryland
Suite 300 Arbotek Associates
Newport Beach, CA 92660 Georgia 102 W. Joppa Road
Tel: (714) 833-0000 Towson, MD 21204
The Novus Group, Inc.
FAX: (714) 833-0003 Tel: (301) 825-0775
611S-A Oakbrook Pkwy
FAX: (301) 337-2781
Norccmp Norcross, GA 30093
3350 Scott Blvd., Tel: (404) 263-0020
Suite 24 FAX: (404) 26~46 Massachusetts
Santa Clara, CA 95054 Mill-Bem Associates
Tel: (408) 727-7707 Idaho 2 Mack Road
FAX: (408)986-1947 Wobum, MA 01801
Cascade Components
Norcomp Tel: (617)932...,'3311
2710 Sunrise Rim Road
2140 Professional Drive FAX: (617)932-0511
Suite 130
Suite 200 Boise, 10 83705
Roseville, CA 95661 Tel: (208) 343--9886 Michigan
Tel: (916) 782~70 FAX: (208) 343-9887 Greiner Associates, Inc.
FAX: (916) 782~73 15324 E. Jefferson Avenue
Sonika Electronica of America illinois Suite 12
925 Hale Place Grosse Point Park, MI 48230
Beta Technology
SuiteA~ Tel: (313)499-0188
1009 Hawthom Drive
Chula Vista, CA 92013 FAX: (313) 499-0665
Itasca,IL60143
Tel: (619) 482~700 Tel: (708) 256--9586
FAX: (619) 482-7598 FAX: (708) 256-9592
Colorado
Front Range Marketing
3100 Arapahoe Road
Suite 404
Boulder, CO 80303
Tel: (303) 443-4780
FAX: (303) 447-0371
4-9
Sales Information CMOS Channe//ess Gate Arrays
FMI Representatives - USA (Continued)
Minnesota Quality Components Texaa

116 Fay_Street
Electromec Sales Technical Marketing, Inc.
Manlius, NY 13104
1601 E Highway 13 3320 Wiley Post Road
Tel: (315) 682--8885
Suite 200 Carrollton, TX 75006
FAX: (315) 682-2277
Bumsville, MN 55337 Tel: (214) 387-3601
Tel: (612) 89<H!200 Quality Components FAX: (214) 387-3605
FAX: (612) 894-9352 2318litus Ave.
Technical Marketing, Inc.
Rochester, NY 14622
2901 Wilcrest Drive
Missouri Tel: (716) 342-7229
Suite 139
FAX: (716) 342-7227
Rothkopf & Associates, Inc. Houston, TX 77042
8721 Manchester Road Tel: (713) 783-4497
SI. Louis, M063144 North carolina FAX: (713) 783-5307
Tel: (314) 961--4485 The Novus Group, Inc. Technical Marketing, Inc.
FAX: (314) 961-4736 1026 Commonwealth Court 1315 Sam Bass Circle
Cary, NC 27511 Suite B-3
New Jersey Tel: (919) 460-7771 Round Rock, TX 78681
FAX: (919)460-5703 Tel: (512) 244-2291
BGR Associates
Evesham Commons FAX: (512)338-1596
525 Route 73 Ohio
Suite 100 Spectrum ESD Washington
Marlton, NJ 08053 3947 Ray Court Road L-Squared Limited
Tel: (609) 983-1020 Morrow, OH 45152 105 Central Way
FAX: (609) 983-1879 Tel: (513) 899-3260 Suite 203
FAX: (513) 899-3260 Kirkland, WA 98033
Technical Applications & Marketing
91 Clinton Road Spectrum ESD Tel: (206) 827-5555
Suite 10 8925 Galloway Trail FAX: (206) 828-5102
Fairfield, NJ 07006 Novelty, OH 44072
Tel: (201) 575-4130 Tel: (216) 338-5226 Wisconsin
FAX: (201) 575-4563 FAX: (216) 338-3214
Bela Technology
01
9401 W Beloit Street
New York Oregon Suite304C
Quality Components L-Squared Umited Milwaukee, WI 53227
3343 Harlem Road 15234 NW Greenbrier Pkwy Tel: (414)543-6609
Buffalo, NY 14225 Beaverton, OR 97006 FAX: (414) 543-9288
Tel: (716) 837-5430 Tel: (503) 629-8555
FAX: (716) 837-0662 FAX: (503) 645-6196
4-10
CMOS Channslless Gate Arrays Sales Information
FMI Representatives - Canada, Mexico and Puerto Rico
canada Mexico Puerto Rico
Pipe-Thompson Limited Solano Electronica Semtronic Associates

5468 Dundas Street W. Ennita 1039-10 Mercantil Plaza Building
Suite 206 Colonia Chapalita Suite 816
Islington, Ontario M9B 6E3 Guadalajara, JAL. 45042 Hato Rey, Puerto Rico 00918
Tel: (416) 236-2355 Tel: (36) 47--<1250 Tel: (809) 7~700
FAX: (416) 236-3387 FAX: (36) 473433
Pipe-Thompson Limited Solano Electronicas
RR2 North Gower Thiers 100
Ottawa, Ontario KOZ 2TO Colonia Anzures
Tel: (613) 258-4067 Mexico City, D.F. 11590
FAX: (613) 258-7649 Tel: (55) 31-5915
FAX: (55) 31-5915
4-11
Sales Information CMOS Channe/less Gate Arrays
FMI Distributors - USA
Alabama Marshalllndus1ries Colorado

Marshall Industries One Morgan Marshall Industries
3313 S. Memorial Highway Irvine, CA 92718 12351 N. Grant Road
SUite 121 (714) 458-5308 SUite A
Huntsville, AL 35801 Marshall Industries Thomton, CO 80241
(205) 881-9235 336 Los Cachas Street (303)451-9383
Repton Electronics Milpitas, CA 95035 Sterling Electronics
4950 Corporate Drive (408) 942-4600
8200 South Akron Street
Suite l05C Marshall Industries Suite 111
Huntsville, AL 35805 3039 Kilgore Ave. Englewood, CO 80112
(205) 722-9565 Rancho Cordova, CA 95670 (303) 792-3939
(916) 635-9700
Arizona Marshall Industries Connecticut
Insight Electronics 10105 Carroll Canyon Road Marshall Industries
1515 W. University Drive San Diego, CA 92131 20 Sterling Drive
Suite 103 (619) 578-9600 Wallingford, CT 06492
Tempe, AZ. 85281 (203) 265-3822
(602) 829-1800 Merit Electronics
2070 Ringwood Avenue Milgray Electronics
Sterling Electronics San Jose, CA 95131 326 W. Main Street
3501 E. Broadway Road (408)4~ Milford, CT 06460
Phoeniz, AZ. 85040 (203) 795-0711
(602) 269-2121 Sterling Electronics
55310 Deny Westem Microtechnology, Inc.
Marshall Industries Unit X 731 Main Street
9830S.51stSln!Bt Agoura, CA 91301 SuiteB2
SuiteB121 (818) 707-0911 Lantem Ridge Monroe, CT 06468
Phoenix, AZ. 85044 (203) 452.{)533
(602) 491Hl290 Sterling Electronics
9410 Topanga Canyon Rd.
•
Chatsworth, CA 91311 Florida
california (818) 407-9850 Marshallindustnes
Insight Electronics 380 S. Northlake Blvd
Sterling Electronics
28035 Dorothy Drive SUite 1024
1342 Bell Avenue
Suite 220 Altamonte Springs, FL 32701
Tustin, CA 92680
Agoura, CA 91301 (407) 767-8585
(714) 259-0900
(818) 707-2100
Marshall Industries
Westem Microtechnology
Insight Electronics 2700 W. Cypress Creek Rd.
28720 Roadside Dr.
15635 Alton Parkway SUiteC 106
SUite 175
SUite 120 Ft. Lauderdale, FL 33309
Agoura Hills, CA 91301
Irvine, CA 92718 (305) 977-4880
(818) 356-0180
(714) 727-2111
Marshall Industries
Insight Electronics 2840 Sherer Drive
1637 North Brian
6885 Flanders Drive SI. Petersburg, FL 33716
Orange, CA 92667
Suite G (813) 573-1399
(714) 637-0200
San Diego, CA 92126
(619) 587-9757 Milgray Electronics
1850 Lee Road
6837 Nancy Ridge Drive
Marshall Industries SUite 104
San Diego, CA 92121
9710 Desoto Ave. Winter Park, FL 32789
(619)453-8430
Chatsworth, CA 91311 (407)647-6747
(818) 407-4100 Westem Microtechnology
12900 Saratoga Ave.
Marshall Industries
Saratoga, CA 95070
9674 Telster Ave.
(408) 725-1660
EI Monte, CA 91731
(818) 459-5500
4-12
OMOS Ohsnne/less Gate Arrays Sales Information
FMI Distributors - USA (Continued)
Florida (Continued) Kansas Michigan

Reptron Electronics Marshallinduslries Replron Electronics
33320 N.w. 53rd Street 10413 W. 84th Terrace 34403 Glendale
Suite 206 Lenexa, KS 66214 Livonia, MI 48150
Ft. Lauderdale, FL 33309 (913) 492-3121 (313) 525--2700
(305) 735-1112
Milgray Electronics
Reptron Electronics 6901 W. 63rd Street Minnesota
14501 McCormick Drive Overland Park, KS 66202 Marshall Industries
Tampa, FL 33626 (913) 236-8800 3955 Annapolis Lane
(813) 855--2351 Plymouth, MN 55447
Maryland (612) 559--2211
Georgia Marshall Industries Reptron Electronics
Marshallinduslries 2221 Broadbirch 5929 Baker Road
5300 Oakbrook Pkwy Suite G Minnetonka, MN 55345
Suite 146 Silver Springs, MD 20910 (612) 938-0000
Norcross, GA 30093 (301) 622-1118
(404) 923--5750 Missouri
Milgray Electronics
9801 Broken Land Parkway Marshall Industries
Georgia Columbia, MD 21045 33n Hollenberg Drive
Milgray Electronics (301) 995--6169 Bridgeton, Me 63044
3000 Northwoods Parkway (314) 291-4650
Vantage Components, Inc.
Suite 270
6925-R Oakland Mills Road
Norcross, GA 30071 New Jersey
Columbia, MD 21045
(404) 446-97n
(301) 720-5100 Marshall Industries
Reptron Electronics 101 Fairfield Road
3040 H Business Park -Drive Massachusatts Fairfield, NJ 07006
Norcross, GA 30071 (201) 882--{)320
Interface Electronic Corp.
(404) 446-1300
228 South Street Marshall Industries
Hopkinton, MA 01748 158 Gaither Drive
illinois
Classic Components
3336 Commercial Ave.
Northbrook, IL 60062
(617) 435-6858
Marshallinduslries
33 Upton Drive
Wilmington, MA 01887
Mt Laurel, NJ 08054
(609) 234-9100
Milgray Electronics
3002 Greentree Exec. Campus
III
(312) 272-9650
(508) 658-0810 Suite B
Marshallinduslries Marlton, NJ 08053
Milgray Electronics
50 E. Commerce Dr. (609) 983--5010
187 Ballardvale Street
Suite I
Wilmington, MA 01887 Vantage Components, Inc.
Schaumburg, IL 60173
(508)657~900 23 Sebago Street
(312)49~155
P.O. Box 2939
Milgray Electronics Clifton, NJ 07013
200 Bulfinch Drive
3223 N. Wilkey Road (201) n7-4100
Andover, MA 01810
Arlington Heights, IL 60004
(508) 687-3900 Western Microtechnology, Inc.
(312) 253--1573
387 Passaic Avenue
Western Microtechnology
Reptron Electronics Fairfield, NJ 07006
20 Blanchard Road
1000 E. State Hwy (201) 882-4999
9 Corporate Place
Suite K
Burlington, MA 01803
Schaumburg, IL 60173 New Mexico
(617) 273--2800
(312) 882-1700
Sterling Electronics
Michigan 345O-D Pan American Freeway
Indiana Albuquerque, NM 871 07
Marshal Industries
Marshallinduslries (505) 884-1900
31067 Schoolcraft Rd.
6990 Corporate Drive
Uvonia. M148150
Indianapolis, IN 46278
(313)5~
(317) 297~83
4-13
Sales Information CMOS Channelless Gate Arrays
New York Ohio Texas

Marshall Industries MarshaU Industries Insight Electronics, Inc.
275 Oser Avenue 3520 Park Center Drive 1778 Plano Road
Hauppauge, NY 11788 Dayton, OH 45414 Suite 320
(516) 273-2424 (513) 898-4480 Richardson, TX 75081
(214) 783-0800
Marshall Industries Marshall Industries
129 Brown Street 30700 Bain Bridge Road Marshall Industries
Johnson City, NY 13790 Unit A 8504 Cross Park Drive
(607) 798-1611 Solon, OH 44139 Austin, TX 78754
(216) 248-1788 (512)837-1991
New York Milgray Electronics Marshall Industries
Marshall Industries 6155 Rockside Road 2045 Chenault
1280 Scottsville Road Cleveland,OH 44131 Carrollton, TX 75006
Rochester, NY 14624 (216)447-1520 (214) 233-5200
(716) 235-7620
Reptron Electronics Marshall Industries
Mast Distributors 404 E. Wilson Bridge Road 2635 South Highway 77
95 Oser Avenue Suite A Harlingen, TX 78550
P.O. Box 12248 Worthington, OH 43085 (512) 421-4621
Hauppauge, NY 11788 (614) 43EH;675
Marshall Industries
(516) 273-4422
7250 Langtry
Micro Genesis Oklahoma Houston, TX 77040
90-10 Colin Drive Radio Inc. (713) 895-9200
Holbrook, NY 11741 1000 South Main
Milgray Electronics
(516) 472-0000 Tulsa, OK 74119
16610 N. Dallas Pkwy
(918)587-9123
Milgray Electronics Suite 1300
77 Schmitt Blvd. Dallas, TX 75248
Farmingdale, NY 11735 Oregon (214) 248-1603
•
(516) 420-9800 Marshall Industries Reptron Electronics
9705 S.w. Gemin Drive 3410 Midcourt
Milgray Electronics
Beaverton, OR 97005 Carrollton, TX 75006
1200 A Scottsville Rd.
(503) 644-5050 (214) 702-9373
Rochester, NY 14624
(716) 235-0830 Western Microtechnology Western Microtechnology, Inc.
1800 N.W. 169th Place 18333 Preston Road
Suite B300 Suite 460
1041-G West Jericho Turnpike
Beaverton, OR 97006 Dallas, TX 75252
Smithtown, NY 11787
(503) 629-2082 (214) 248-3775
(516) 543-2000
Pennsylvania Western Microtechnology, Inc.

North carolina 2500 Wilcrest, 3rd Floor
Interlace Electronic Corp. Houston, TX 77042
Marshall Industries
7 Great Valley Parkway (713) 954-4850
5224 Greens Dairy Road
Malvern, PA 19355
Raleigh, NC 27604
(215) 889-2060
(919) 878-9882
Marshall Industries
Reptron Electronics
701 Alpha Drive
5954-A Six Fork Road
Pittsburg, PA 15237
Raleigh, NC 27609
(412) 7811-4141
(214)7~8oo
4-14
CMOS Channe//ess Gate Arrays Sales Information
Utah Marshallinduslries Marsh Electronics

Marshall Industries 11715 N. Creek Parkway 1563S.101stSb"eet
Suite 112 Milwaukee, WI 53214
466 Lawndale Drive
Bothell, WA 98011 (414)47~000
Suite C
(206)4~747
Salt Lake City, UT 84115 Marshall Industries
(801)485-1551 Western Microtechnology 20900 Swenson Drive
14636 N.E. 95th Street Suite 150
Milgray Electronics
Redmond, WA 98052 Waukesha, WI 53186
4190 S. Highland Drive
(206)881~737 (414) 797--8400
Suite 102
Salt Lake City, UT 84124
(801 ) 272-4999 Wisconsin
Classic Components
Washington 2925 S. 160th Street
New Benin, WI 53151
Insight Electronics, Inc.
(414)7~300
12002115thAvenue, NE
Kirkland, WA 98034
(206) 820-8100
lEI
4-15
Sales Information CMOS Channe/less Gate Arrays
FMI Distributors - Canada

BrHish Columbia MarshaU Industries Quebec
ITT Industries 4 Paget Road Marshall Industries
3455 Gardner Court Unit 10 & 11 3869 Sources Blvd
Burnaby, B.C. V5G 4J7 Framton, ON 16T 5G3 Suite 207
(604) 291-1227 (416) 453-a046 0.0.0., QUE H9B 2A2
Milgray Electronics (514) 663-9440
Space Electronics
1695 Bcunclry Road 150 Consumers Road Space Electronics
Vancouver, B.C. V5K 4X7 Suite 502 5651 Rue Ferrier Street
Willowdale, ON M2J 4R4 Montreal, QUE H4P 2K5
(604) 294-1166
(416) 756-4481 (514) 697-a676
Ontario
ITT Industries
300 North Rivermede Road
Concord, ON L4K 2Z4
(416) 736-1114
4-16
CMOS Channe/less Gate AtTars Sales Information
Fujitsu Mikroelektronik GmbH (FMG) Sales Offices for

Europe
France Fujitsu Mikroelektronik GmbH Sweden

Fujitsu CarI-Zeiss-Ring 11 Fujitsu Microelectronics Ltd.
Immeuble Ie Trident D-8045lsmaning Torggatan8
3-6, Vole Felix Ebooe bei Munchen 17154501na
F-S4024 Creteil Codex Tel: (89)960--9440 Tel: (8)764-6365
Tel: (1)4-207~200 Telex: 8974464 Telex: 13411
FAX: (89)9Ei(l-S442
Telex: 262861 FAX: (8)2/Hl345
FAX:(1)~7-7933
"aly United Kingdom
F.R. Germany FujRsu Microelectronics
Fujitsu Microelectronics Ltd.
Fujitsu Mikroelektronik GmbH ltalia S.R.L Hargrave House
Lyoner Snsse 44-48 Centro Direzionale Milanofiori Belmont Road
Arabana Center 9. OG Strada 4 - Palazzo Al2 Maidenhead
0-«)00 Frankfurt am Main 71 1-20094 Milano Berkshire S16 6NE
Tel: (69)66320 Tel: (39)(2)824-61701176 Tel: (0628)76100
Telex: 411963 Telex: 318546 Telex: 848955
FAX: (69)66321 FAX: (39)(2)824-6189 FAX: (0628)781484
Fujitsu Mikroeleklronik GmbH
Am Joachimsberg 10--12 Netherland.
0-7033 Henenberg
Tel: (07032) 4085 Fujitsu Benelux
FAX: (07032) 4088 Europalaan 6JB
5623 W Eindhoven
Tel: (31 )44-7440
Telex: 59265
FAX: (31)44-4158
lEI
4-17
FMG Distributors - Europe
Austria AspecsOY Unidis Group Torino

Eljapex Handelsges. MBH Myyrmaentie 2 A PCMSnC
Eitnergasse 6 01600 Vantaa Via Piave 541B
Helsinki 10099 Rivoli
1232Wien
Tel: (222)861531 Tel: (90)5668686 Tel: (011)9532256
FAX: (011 )9534238
Telex: 112344
FAX: (222)863211200 France
DPA Netherlands
MHVlEBV Elektronik
Diefenbachgasse 35/6 12, Avenue des Pres MHV/EBV Elektronik
1150 Wien 78180 Montigny Ie Bretonneux Planetenbaan 2
Tel: (222)838519 Tel: (1 )30575040 3606 AK-Maarssenbroek
Telex: 134946 Telex: 689423 Tel: (3465)62353
FAX: (222) 838530 FAX: (1)30571863 Telex: 76089
FAX: (3465)64277
Microram
Belgium 6, Rue Ie Corbusier P & T Electronics B.V.
EriatSA Silic424 Esse Baan 77
83, Rue des Fraisiers 94583 Rungis Cedex P.O. Box 329
4410 Herstal Vottem Tel: (1)46868170 2908 LJ Capelle AID Ijssel
Tel: (41)271993 Telex: 2265909 Tel: 104501444
Telex: 41782 FAX: (1)45605549 Telex: 26096
FAX: (41 )278085 FAX: 104507092
Germany
MHVlEBV Elektronik Norway
Excelsiorlaan 35 Eljapex GmbH
Avenue Excelsion 35 Felsenauerstr. 18 Odin Electronics AS
1930 Zaventem 7890 Waldshut-Tiengen Postboks 72
Tel: (2)7209938 Tel: (07751)2035 Edv. Griegsvei 2
Telex: 62590 Telex: (07751)6603 1472 Fjellhamar
FAX: (2)7208152 Tel: (02)703730
Micro Halbleiter GmbH
Telex: 19732
Jagerweg 10
FAX: (02)700310
Denmark 8012 Ottobrunn
III Nordisk Elektronik AS

Transformervej 17
2730 Herlev
Tel: (2)842000
Tel: (089)6096068
Telex: 5213807
FAX: (089)6093758
Republic of Ireland
Allied Semiconductors International Ltd.
Unit 1
Telex: 35200 Italy Distribution Park
FAX: (2)921552 Shannon Industrial Estate
Unidis Group Bologna
Shannon
Malpassi SRL
Co. Clare
Finland Via Baravelli, 1 Tel: (61)61777
40012 Caiderara di Reno
GadeliusOY Telex: 70358
Tel: (051)727252
Kaupintie 18 FAX: (61)363141
00440 Helsinki Telex: 583118
FAX: (051)727515
Tel: (90)5626644
Telex: 121274
FAX: (90)5826196
4-18
CMOS Channe//ess Gars Arrays Sales Information
FMG Distributors - Europe (Continued)
Spain SWeden United Kingdom

Comella SA Martinsson Eleklronik AB Hawke Components
Pedro IV-M, 5 PI Box 9060 Amotex House
08005 Barcelona Insb'Umentvagen 16 45 Hanworth Road
Tel: (93)3007712 12609 Hagersten Sunbury on Thames
Telex: 51934 Tel: (8)7440300 Middlesex
FAX: (93)3005156 Telex: 13077 TW165DA
FAX: (8)744340S Tel: (0197)97799
Comella SA
Telex: 923592
Emilio Munoz 41
SWHmrland FAX: (9327)87333
Nave 1-1-2
28037 Madrid EljapexAG Pronlo Electronic Systems Ltd.
Tel: (1 )7543001 Hardslrasse 72 City Gate House
Telex: 42007 5430 Wettingen 399/425 Eastem Avenue
FAX: (1)7542151 Tel: (56)275m Gants Hills
Telex: 826300 lllord
FAX: (56)261486 Essex IG2 6LR
Tel: (15)546222
Telex: 8954213
FAX: (15)183222
4-19
Sales Informa6on CMOS Channelless Gats Arrays
Fujitsu Microelectronics Asia PTE Limited (FMA) Sales Offices for

Asia and Australia
Taiwan Singapore Hong Kong
Fujitsu Mlcroelec1ronics Pacific Asia Fujitsu Electronics PTE lid. Fujitsu Microelectronics Pacific Asia Lid.
TW Branch Ltd. ~7P~abyt.Pam 616-617, Tower B
1906 No. 333 Keelung Road 52 Bras Basah Road New Mandarin P~
Sec. 1 Taipei 10548 05-,'30112, The Plaza 14 Science Museum Road
Taiwan, Republic of China Singapore 0718 TST East, Kowloon
Tel: (02) 757~ Tel: (65) 336-1600 Hong Kong
Telex: 17312 FMPTPI Telex: 55573 FESPL Tel: 723-0093
FAX: (02) 757-6571 FAX: 336-1609 FAX: 721-6555
4-20
CMOS Channel/ess Gate Arrays Sales Information
FMA Representatives - Asia and Australia
Australia Korea
Pacific Microelectronics PTY Ltd. KML Corporation
Unit A20, Central Park 3/F Bangbae Station Bldg.
4 Central Avenue 981-15 Bangbae ~Dong
P.O. Box 189 ShuchD-ilu,
Thornleigh NSW 2120 Seoul, Korea
Australia Tel: (2)588-2011
Tel: (2)481-0065 Telex: K25981 KMLCORP
Telex: 24844460 FAX: (2)588-2017
FAX: (2) 484--4460
4-21
Sales Information CMOS Channs/l9ss Gate Anays
FMA Distributors - Asia
Hong Kong Singapore Taiwan

Famint (HK) Lid. Cony Electronics (S) PTE lid. Eplus Corporation, lid.
Room 1502,l51F 10 Jalan Besar llF-8, No. 20
No. 111 Leighton Road 03-,25 Sim Lim Tower Min Chuin West Road
Causeway Bay, Singapore 0820 Taipei, Taiwan
Hong Kong Tel:~lll Tel: (2) 536-,3250
Tel: 5-760130 15-760146 Telex: CONY RS34808 FAX: (2) 581~309
FAX: 5-765619 FAX: 296-0339
Famint (Taiwan) Co., Lid.
Famint Electronics PTE Lid. Room 113, 101F
01-302, The Plaza Chang An East Road
7500 A Beach Road Taipei, Taiwan
Singapore 0719 Republic of China
Tel: 298-4566 Tel: (02) 5051963
Telex: RS37295 FAMINT FAX: (02) 5080385
FAX: 297-2597
4-22
Design Information
g AU Series CMOS Gate Array Macrocell Library
o CG21 Series CMOS Gate Array Macrocell Library
o Sales Information
FUJITSU LIMITED
Marunouchi Headquarters
6-1 , Marunouchi 1-chome
Chiyoda-ku , Tokyo 100, Japan
Tel: (03) 216-3211
Telex: 781-22833
FAX: (03) 213-7174
For further information , please contact:

Japan
FUJITSU LIMITED
Integrated Circuits and Semiconductor Marketing
Furukawa Sogo Bldg.
6-1, Marunouchi 2-chome
Chiyoda-ku , Tokyo 100, Japan
Tel : (03) 216-3211
Telex: 781-2224361
FAX: (03) 211-3987
Europe
FUJITSU MIKROELEKTRONIK GmbH
Lyoner Strasse 44-48
Arabella Centre 9. OG
0-6000 Frankfurt 71
Federal Republic of Germany
Tel: (49) (069) 66320
Telex: 441-963
FAX: (069) 663-2122
Asia
FUJITSU MICROELECTRONICS ASIA PTE. LTD.
06-04/06-07 Plaza By the Park
No. 52 Bras Basah Road
Singapore 0718
Tel: (65) 336-1600
Telex: 55573
FAX: (65) 336-1609
North and South America

FUJITSU MICROELECTRONICS, INC.
Integrated Circuits Division
3545 North First Street
San Jose, CA 95134-1804 USA
Tel: (408) 922-9000
Telex: 910-338-0190
FAX: (408) 432-9044
© 1990 FUJITSU LIMITED and Fujitsu Microelectronics, Inc. Printed in USA

1990 Fujitsu Channelless Gate Arrays

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CG21 Series CMOS Gate Array Macrocell Library IIIJ

CMOS Channelless Gate Arrays

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Ethamet™ is a registered trademark of Xerox Corporation.

Section 1 - Design Information

Section 2 - AU Series CMOS Gate Array Unit Cell Library

Section 3 - CG21 Series CMOS Gate Array Unit Cell Library

Section 4 - Sales Information

1-1 .. The Basic Cell .............................................................. 1-4

Figures from Chapter 7, Application Notes

CMOS ASIC Test Patterns

ASIC Packaging Considerations

Tables from Chapter 7, Application Notes

ASIC Packaging COnsiderations

CMOS Channeled Gate Arrays Data Book

Description Name Device Part Number

336 Gates, 58 1/0 C330UHB MB625xxx

3,256 Gates, 108 110 CG10272 MBCG10272xxx

CMOS Channelless Gate Arrays Data Book

10,224 Gates, 108 1/0 Cl0KAU MOO37xxx

10,224 Gates, 1081/0 CG21103 MBCG21103xxx

BiCMOS Gate Arrays Data Book

Description Name Device Pari Number

645 Gales, 52 1/0 BC400 MB211xxx

BC-H Series BICMOS Gate Arrays - 1.01110.511. 0.45 ns typical delay

4,312 Gates, 96110 BC4000H MB221xxx

ECl Gate Arrays Data Book

1,056 Gates, 64 1/0 ET750 MB121Kxxx

H Series ECl Gate Arrays - 0,511.100 ps typical delay

9,856 Gales, 200 I/O ET10000H MB147/157xxx

Ultra High Performance ECl Gate Arrays 0.511. 75 ps typical delay

128 Gales, 23/1/0 E128H MB1800

VH Series ECl Gate Arrays 0.411. 80 ps typical delay

38,948 Gates, 300 1/0 E30000VH MB1621172xxx

CMOS Standard Cell Data Book

AS Series Standard Cells - 0.811. 370 ps typical delay

Chapter 1 - Fujitsu CMOS Products

Contents of This Chapter

1.2 CMOS Technology for ASICs

1.3 CMOS Gate Array Structure

1.3.1 The Basic Cell

Figure 1-1. The Basic Cell

1.3.2 Basic Cell Construction

Figure 1-3. Physical Construction of the Unit Cell NAND Gate

1.3.3 BasiC Cell Arrangement

1.3.4 Unit Cells

1.3.5 User Macros

1.3.6 Compiled Cells and SuperMacros

Table 1-1. SuperMacro Implementations for CMOS ASIC

1.3.71/0 (Input/Output) Buffer Cells

1.3.8 Structure of the Chip

I Basic Cell (Double Column)

DO 0 4------------------. DOD mlr=t ........................................ ElImImI

Figure 1-4. Channeled Gate Array Chip Structure

Basic Cell (Pair)

Figure 1-5 Channelless Gate Array Chip Structure

1.4 Fujitsu'S CMOS Gate Arrays

1975 1980 1985 1990 1992

Figure 1--6. Equivalent Gate Count vs. Processing Speed,