LT8390A

60V 2MHz Synchronous

4-Switch Buck-Boost Controller
with Spread Spectrum
FEATURES DESCRIPTION
nn 4-Switch Single Inductor Architecture Allows VIN The LT®8390A is a synchronous 4-switch buck-boost DC/DC
Above, Below or Equal to VOUT controller that regulates output voltage, input or output
nn Up to 95% Efficiency at 2MHz current from an input voltage above, below, or equal to
nn Proprietary Peak-Buck Peak-Boost Current Mode the output voltage. The proprietary peak-buck peak-boost
nn Wide V Range: 4V to 60V current mode control scheme allows adjustable and syn-
IN
nn ±1.5% Output Voltage Accuracy: 1V ≤ V
OUT ≤ 60V chronizable 600kHz to 2MHz fixed frequency operation, or
nn ±3% Input or Output Current Accuracy with Monitor internal 25% triangle spread spectrum frequency modula-
nn Spread Spectrum Frequency Modulation for Low EMI tion for low EMI. With a 4V to 60V input voltage range, 0V
nn High Side PMOS Load Switch Driver to 60V output voltage capability, and seamless low noise
nn No Top MOSFET Refresh Noise in Buck or Boost transitions between operation regions, the LT8390A is ideal
nn Adjustable and Synchronizable: 600kHz to 2MHz for voltage regulator, battery and supercapacitor charger
nn V
OUT Disconnected from VIN During Shutdown applications in automotive, industrial, telecom, and even
nn Available in 28-Lead TSSOP with Exposed Pad and battery-powered systems.
28-Lead QFN (4mm × 5mm)
The LT8390A provides input or output current monitor
and power good flag. Fault protection is also provided to
APPLICATIONS detect output short-circuit condition, during which the
nn Automotive, Industrial, Telecom Systems LT8390A retries, latches off, or keeps running.
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Analog
nn High Frequency Battery-Powered System Devices, Inc. All other trademarks are the property of their respective owners.

TYPICAL APPLICATION
95% Efficient 48W (12V 4A) 2MHz Buck-Boost Voltage Regulator
5mΩ 1µH 10mΩ
VIN VOUT
6V TO 28V 12V
CONTINUOUS 22µF 0.1µF 0.1µF 22µF 4A
63V 0.1µF SW1 LSP LSN SW2 0.1µF 16V
4V TO 56V
TRANSIENT 100V BST1 BST2 16V ×2 22µF

4.7µF
×2 ×2 16V Efficiency vs VIN
100V INTVCC INTVCC 100
×2 BG1 BG2
GND
TG1 TG2 90
LT8390A
VIN VOUT
EFFICIENCY (%)

1µF 1µF 80
383k
10Ω
EN/UVLO ISP
1µF 10Ω
169k 110k 70
LOADTG ISN IOUT = 4A
TEST FB IOUT = 2A
SSFM OFF
10k 60 CONTINUOUS OPERATION WITH
ISMON ISMON SYNC/SPRD
INTVCC HIGHEST COMPONENT TEMPERATURE
CTRL INTVCC SSFM ON BELOW 90°C (TA = 25°C)
50
4.7µF 0 5 10 15 20 25 30 35 40
100k 133k LOADEN 100k
INPUT VOLTAGE (V)
VREF PGOOD PGOOD 8390a TA01b

0.47µF SS VC RT

22nF 10k 59.0k

2MHz
2.2nF
8390a TA01a

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LT8390A
ABSOLUTE MAXIMUM RATINGS (Note 1)

VIN, EN/UVLO, VOUT, ISP, ISN.....................................60V FB, LOADEN, SYNC/SPRD, CTRL, PGOOD....................6V
(ISP-ISN)...........................................................–1V to 1V Operating Junction Temperature Range (Notes 2, 3)
BST1, BST2.................................................................66V LT8390AE............................................ –40°C to 125°C
SW1, SW2, LSP, LSN...................................... –6V to 60V LT8390AI............................................. –40°C to 125°C
INTVCC, (BST1-SW1), (BST2-SW2)...............................6V LT8390AH............................................ –40°C to 150°C
(BST1-LSP), (BST1-LSN)..............................................6V Storage Temperature Range.................... –65°C to 150°C

PIN CONFIGURATION
TOP VIEW
TOP VIEW
BG1 1 28 BG2

BST1

BST2
SW1

SW2
BST1 2 27 BST2

BG1
BG2
SW1 3 26 SW2 28 27 26 25 24 23
TG1 4 25 TG2 TG1 1 22 TG2
LSP 5 24 VOUT LSP 2 21 VOUT
LSN 6 23 LOADTG LSN 3 20 LOADTG
VIN 7 29 22 SYNC/SPRD VIN 4 19 SYNC/SPRD
29
GND
INTVCC 5 GND 18 RT
INTVCC 8 21 RT
EN/UVLO 9 20 VC EN/UVLO 6 17 VC
TEST 7 16 FB
TEST 10 19 FB
LOADEN 8 15 SS
LOADEN 11 18 SS
9 10 11 12 13 14
VREF 12 17 PGOOD
VREF
CTRL
ISP
ISN
ISMON
PGOOD
CTRL 13 16 ISMON
ISP 14 15 ISN
UFD PACKAGE
FE PACKAGE 28-LEAD (4mm × 5mm) PLASTIC QFN
28-LEAD PLASTIC TSSOP θJA = 43°C/W, θJC = 3.4°C/W
θJA = 30°C/W, θJC = 5°C/W EXPOSED PAD (PIN 29) IS GND, MUST BE SOLDERED TO PCB
EXPOSED PAD (PIN 29) IS GND, MUST BE SOLDERED TO PCB

ORDER INFORMATION http://www.linear.com/product/LT8390A#orderinfo

LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE
LT8390AEFE#PBF LT8390AEFE#TRPBF LT8390AFE 28-Lead Plastic TSSOP –40°C to 125°C
LT8390AIFE#PBF LT8390AIFE#TRPBF LT8390AFE 28-Lead Plastic TSSOP –40°C to 125°C
LT8390AHFE#PBF LT8390AHFE#TRPBF LT8390AFE 28-Lead Plastic TSSOP –40°C to 150°C
LT8390AEUFD#PBF LT8390AEUFD#TRPBF 8390A 28-Lead (4mm × 5mm) Plastic QFN –40°C to 125°C
LT8390AIUFD#PBF LT8390AIUFD#TRPBF 8390A 28-Lead (4mm × 5mm) Plastic QFN –40°C to 125°C
LT8390AHUFD#PBF LT8390AHUFD#TRPBF 8390A 28-Lead (4mm × 5mm) Plastic QFN –40°C to 150°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/. Some packages are available in 500 unit reels through
designated sales channels with #TRMPBF suffix.

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 LT8390A
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C (Note 2). VIN = 12V, VEN/UVLO = 1.5V unless otherwise noted.
PARAMETER CONDITIONS MIN TYP MAX UNITS
Supply
VIN Operating Voltage Range l 4 60 V
VIN Quiescent Current VEN/UVLO = 0.3V 1 2 µA
VEN/UVLO = 1.1V 270 µA
Not Switching 2.1 2.8 mA
VOUT Voltage Range l 0 60 V
VOUT Quiescent Current VEN/UVLO = 0.3V, VOUT = 12V 0.1 0.5 µA
VEN/UVLO = 1.1V, VOUT = 12V 0.1 0.5 µA
Not Switching, VOUT = 12V 20 40 60 µA
Linear Regulators
INTVCC Regulation Voltage IINTVCC = 20mA 4.85 5.0 5.15 V
INTVCC Load Regulation IINTVCC = 0mA to 80mA 1 4 %
INTVCC Line Regulation IINTVCC = 20mA, VIN = 6V to 60V 1 4 %
INTVCC Current Limit VINTVCC = 4.5V 110 145 190 mA
INTVCC Dropout Voltage (VIN – INTVCC) IINTVCC = 20mA, VIN = 4V 160 mV
INTVCC Undervoltage Lockout Threshold Falling 3.44 3.54 3.64 V
INTVCC Undervoltage Lockout Hysteresis 0.24 V
VREF Regulation Voltage IVREF = 100µA l 1.97 2.00 2.03 V
VREF Load Regulation IVREF = 0mA to 1mA 0.4 1 %
VREF Line Regulation IVREF = 100µA, VIN = 4V to 60V 0.1 0.2 %
VREF Current Limit VREF = 1.8V 2 2.5 3.2 mA
VREF Undervoltage Lockout Threshold Falling 1.78 1.84 1.90 V
VREF Undervoltage Lockout Hysteresis 50 mV
Control Inputs/Outputs
EN/UVLO Shutdown Threshold l 0.3 0.6 1.0 V
EN/UVLO Enable Threshold Falling l 1.196 1.220 1.244 V
EN/UVLO Enable Hysteresis 13 mV
EN/UVLO Hysteresis Current VEN/UVLO = 0.3V –0.1 0 0.1 µA
VEN/UVLO = 1.1V 2.1 2.5 2.9 µA
VEN/UVLO = 1.3V –0.1 0 0.1 µA
CTRL Input Bias Current VCTRL = 0.75V, Current Out of Pin 0 20 50 nA
CTRL Latch-Off Threshold Falling l 285 300 315 mV
CTRL Latch-Off Hysteresis 25 mV
Load Switch Driver
LOADEN Threshold Rising l 1.3 1.4 1.5 V
LOADEN Hysteresis 220 mV
Minimum VOUT for LOADTG to be On VLOADEN = 5V 2.4 3 V
LOADTG On Voltage V(VOUT-LOADTG) VOUT = 12V 4.5 5 5.5 V
LOADTG Off Voltage V(VOUT-LOADTG) VOUT = 12V –0.1 0 0.1 V
LOADEN to LOADTG Turn On Propagation Delay CLOADTG = 3.3nF to VOUT, 50% to 50% 90 ns
LOADEN to LOADTG Turn Off Propagation Delay CLOADTG = 3.3nF to VOUT, 50% to 50% 40 ns
LOADTG Turn On Fall Time CLOADTG = 3.3nF to VOUT, 10% to 90% 300 ns
LOADTG Turn Off Rise Time CLOADTG = 3.3nF to VOUT, 90% to 10% 10 ns

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LT8390A
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C (Note 2). VIN = 12V, VEN/UVLO = 1.5V unless otherwise noted.
PARAMETER CONDITIONS MIN TYP MAX UNITS
Error Amplifier
Full Scale Current Regulation V(ISP-ISN) VCTRL = 2V, VISP = 12V l 97 100 103 mV
VCTRL = 2V, VISP = 0V l 97 100 103 mV
1/10th Current Regulation V(ISP-ISN) VCTRL = 0.35V, VISP = 12V l 8 10 12 mV
VCTRL = 0.35V, VISP = 0V l 8 10 12 mV
ISMON Monitor Output VISMON V(ISP-ISN) = 100mV, VISP = 12V/0V l 1.20 1.25 1.30 V
V(ISP-ISN) = 10mV, VISP = 12V/0V l 0.30 0.35 0.40 V
V(ISP-ISN) = 0mV, VISP = 12V/0V l 0.20 0.25 0.30 V
ISP/ISN Input Common Mode Range l 0 60 V
ISP/ISN Low Side to High Side Switchover Voltage VISP = VISN 1.8 V
ISP/ISN High Side to Low Side Switchover Voltage VISP = VISN 1.7 V
ISP Input Bias Current VLOADEN = 5V, VISP = VISN = 12V 23 µA
VLOADEN = 5V, VISP = VISN = 0V –10 µA
VEN/UVLO = 0V, VISP = VISN = 12V or 0V 0 µA
ISN Input Bias Current VLOADEN = 5V, VISP = VISN = 12V 23 µA
VLOADEN = 5V, VISP = VISN = 0V –10 µA
VEN/UVLO = 0V, VISP = VISN = 12V or 0V 0 µA
ISP/ISN Current Regulation Amplifier gm 2000 µs
FB Regulation Voltage VC = 1.2V l 0.985 1.00 1.015 V
FB Line Regulation VIN = 4V to 60V 0.2 0.5 %
FB Load Regulation 0.2 0.8 %
FB Voltage Regulation Amplifier gm 660 µS
FB Input Bias Current FB in Regulation, Current Out of Pin 10 40 nA
VC Output Impedance 10 MΩ
VC Standby Leakage Current VC = 1.2V, VLOADEN = 0V –10 0 10 nA
Current Comparator
Maximum Current Sense Threshold V(LSP-LSN) Buck, VFB = 0.8V l 35 50 65 mV
Boost, VFB = 0.8V l 40 50 60 mV
LSP Pin Bias Current VLSP = VLSN = 12V 60 µA
LSN Pin Bias Current VLSP = VLSN = 12V 60 µA
Fault
FB Overvoltage Threshold (VFB) Rising l 1.08 1.1 1.12 V
FB Overvoltage Hysteresis l 35 50 65 mV
FB Short Threshold (VFB) Falling l 0.24 0.25 0.26 V
FB Short Hysteresis Hysteresis l 35 50 65 mV
ISP/ISN Over Current Threshold V(ISP-ISN) VISP = 12V 750 mV
PGOOD Upper Threshold Offset from VFB Rising l 8 10 12 %
PGOOD Lower Threshold Offset from VFB Falling l –12 –10 –8 %
PGOOD Pull-Down Resistance 100 200 Ω
SS Hard Pull-Down Resistance VEN/UVLO = 1.1V 100 200 Ω
SS Pull-Up Current VFB = 0.4V, VSS = 0V 10 12.5 15 µA
SS Pull-Down Current VFB = 0.1V, VSS = 2V 1 1.25 1.5 µA
SS Fault Latch-Off Threshold 1.7 V
SS Fault Reset Threshold 0.2 V

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 LT8390A
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C (Note 2). VIN = 12V, VEN/UVLO = 1.5V unless otherwise noted.
PARAMETER CONDITIONS MIN TYP MAX UNITS
Oscillator
RT Pin Voltage RT = 100kΩ 1.00 V
Switching Frequency VSYNC/SPRD = 0V, RT = 226kΩ 645 685 725 kHz
VSYNC/SPRD = 0V, RT = 100kΩ 1290 1360 1430 kHz
VSYNC/SPRD = 0V, RT = 59.0kΩ l 1900 2000 2100 kHz
SYNC Frequency 600 2100 kHz
SYNC/SPRD Input Bias Current VSYNC/SPRD = 5V –0.1 0 0.1 µA
SYNC/SPRD Threshold Voltage 0.4 1.5 V
Highest Spread Spectrum Above Oscillator Frequency VSYNC/SPRD = 5V 21 23 25 %
Region Transition
Buck-Boost to Boost (VIN /VOUT) 0.73 0.75 0.77
Boost to Buck-Boost (VIN /VOUT) 0.83 0.85 0.87
Buck to Buck-Boost (VIN /VOUT) 1.23 1.25 1.27
Buck-Boost to Buck (VIN /VOUT) 1.31 1.33 1.35
Peak-Buck to Peak-Boost (VIN /VOUT) 0.96 0.98 1.00
Peak-Boost to Peak-Buck (VIN /VOUT) 1.00 1.02 1.04
NMOS Drivers
TG1, TG2 Gate Driver On-Resistance V(BST-SW) = 5V
Gate Pull-Up 2.6 Ω
Gate Pull-Down 1.4 Ω
BG1, BG2 Gate Driver On-Resistance VINTVCC = 5V
Gate Pull-Up 3.2 Ω
Gate Pull-Down 1.2 Ω
TG1, TG2 Rise Time CL = 3.3nF, 10% to 90% 25 ns
TG1, TG2 Fall Time CL = 3.3nF, 90% to 10% 20 ns
BG1, BG2 Rise Time CL = 3.3nF, 10% to 90% 25 ns
BG1, BG2 Fall Time CL = 3.3nF, 90% to 10% 20 ns
TG Off to BG On Delay CL = 3.3nF 25 ns
BG Off to TG On Delay CL = 3.3nF 25 ns
TG1 Minimum Duty Cycle in Buck Region Peak-Buck Current Mode 10 %
TG1 Maximum Duty Cycle in Buck Region Peak-Buck Current Mode 90 %
TG1 Fixed Duty Cycle in Buck-Boost Region Peak-Boost Current Mode 80 %
BG2 Fixed Duty Cycle in Buck-Boost Region Peak-Buck Current Mode 20 %
BG2 Minimum Duty Cycle in Boost Region Peak-Boost Current Mode 10 %
BG2 Maximum Duty Cycle in Boost Region Peak-Boost Current Mode 90 %
Note 1: Stresses beyond those listed under Absolute Maximum Ratings temperature range. The LT8390AH is guaranteed over the –40°C to 150°C
may cause permanent damage to the device. Exposure to any Absolute operating junction temperature range. High junction temperatures degrade
Maximum Rating condition for extended periods may affect device operating lifetimes. Operating lifetime is derated at junction temperatures
reliability and lifetime. greater than 125°C.
Note 2: The LT8390AE is guaranteed to meet performance specifications Note 3: The LT8390A includes overtemperature protection that is intended
from 0°C to 125°C operating junction temperature. Specifications over to protect the device during momentary overload conditions. Junction
the –40°C to 125°C operating junction temperature range are assured by temperature will exceed 150°C when overtemperature protection is active.
design, characterization and correlation with statistical process controls. Continuous operation above the specified absolute maximum operating
The LT8390AI is guaranteed over the –40°C to 125°C operating junction junction temperature may impair device reliability.

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 LT8390A
TYPICAL PERFORMANCE CHARACTERISTICS TA = 25°C, unless otherwise noted.

Efficiency vs Load Current Efficiency vs Load Current Efficiency vs Load Current

(Buck Region) (Buck-Boost Region) (Boost Region)
100 100 100

90 90 90

80 80 80
EFFICIENCY (%)

EFFICIENCY (%)
EFFICIENCY (%)
70 70 70

60 60 60

50 50 50
FRONT PAGE APPLICATION FRONT PAGE APPLICATION FRONT PAGE APPLICATION
VIN = 24V, VOUT = 12V, fSW = 2MHz VIN = 12V, VOUT = 12V, fSW = 2MHz VIN = 8V, VOUT = 12V, fSW = 2MHz
40 40 40
0 0.5 1 1.5 2 2.5 3 3.5 4 0 0.5 1 1.5 2 2.5 3 3.5 4 0 0.5 1 1.5 2 2.5 3 3.5 4
LOAD CURRENT (A) LOAD CURRENT (A) LOAD CURRENT (A)
8390a G01 8390a G02 8390a G03

Switching Waveforms Switching Waveforms Switching Waveforms

(Buck Region) (Buck-Boost Region) (Boost Region)

VSW1 VSW1
20V/DIV VSW1
20V/DIV
20V/DIV
VSW2
VSW2 20V/DIV
VSW2
20V/DIV
20V/DIV IL
IL IL 2A/DIV
2A/DIV 2A/DIV

VOUT VOUT VOUT

500mV/DIV 500mV/DIV 500mV/DIV
8390 G06
200ns/DIV
8390 G04
200ns/DIV
8390 G05
200ns/DIV
FRONT PAGE APPLICATION FRONT PAGE APPLICATION FRONT PAGE APPLICATION
VIN = 24V, IOUT = 2A VIN = 12V, IOUT = 2A VIN = 8V, IOUT = 2A

VOUT vs IOUT (CV/CC) VIN Shutdown Current VIN Quiescent Current

14 3.0 2.8

12 2.5
2.6
OUTPUT VOLTAGE (V)

10 2.0 VIN = 60V

VIN = 60V 2.4
IQ (mA)
IQ (µA)

8 1.5 VIN = 12V

VIN = 12V 2.2

6 1.0 VIN = 4V

VIN = 4V 2.0
4 0.5

2 0.0 1.8
0 1 2 3 4 5 6 7 –50 –25 0 25 50 75 100 125 150 –50 –25 0 25 50 75 100 125 150
LOAD CURRENT (A) TEMPERATURE (°C) TEMPERATURE (°C)
8390a G07
8390a G08 8390a G09

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 LT8390A
TYPICAL PERFORMANCE CHARACTERISTICS TA = 25°C, unless otherwise noted.

INTVCC Voltage vs Temperature INTVCC Voltage vs VIN INTVCC UVLO Threshold

5.15 5.15 4.0

3.9
5.10 5.10
3.8 RISING
5.05 5.05
IINTVCC = 20mA 3.7
VINTVCC (V )

VINTVCC (V)
VINTVCC (V)
IINTVCC = 0mA
5.00 5.00 3.6
FALLING
IINTVCC = 80mA
3.5
4.95 4.95
3.4
4.90 4.90
3.3

4.85 4.85 3.2

–50 –25 0 25 50 75 100 125 150 0 10 20 30 40 50 60 –50 –25 0 25 50 75 100 125 150
TEMPERATURE (°C) VIN (V) TEMPERATURE (°C)
8390a G10 8390a G11 8390a G12

VREF Voltage vs Temperature VREF Voltage vs VIN VREF UVLO Threshold

2.04 2.04 2.00

2.03 2.03
1.95
2.02 2.02
1.90 RISING
2.01 2.01
IVREF = 0mA IVREF = 100µA
VREF (V)
VREF (V)

VREF (V)
2.00 2.00 1.85 FALLING

1.99 1.99
IVREF = 1mA 1.80
1.98 1.98
1.75
1.97 1.97

1.96 1.96 1.70

–50 –25 0 25 50 75 100 125 150 0 10 20 30 40 50 60 –50 –25 0 25 50 75 100 125 150
TEMPERATURE (°C) VIN (V) TEMPERATURE (°C)
8390a G13 8390a G14 8390a G15

EN/UVLO Enable Threshold EN/UVLO Hysteresis Current CTRL Latch-Off Threshold

1.240 3.0 0.40

1.235
2.8
1.230 0.35
RISING RISING
1.225
VEN/UVLO (V)

2.6
VCTRL (V)
IHYS (µA)

1.220 0.30
FALLING
FALLING 2.4
1.215

1.210 0.25
2.2
1.205

1.200 2.0 0.20

–50 –25 0 25 50 75 100 125 150 –50 –25 0 25 50 75 100 125 150 –50 –25 0 25 50 75 100 125 150
TEMPERATURE (°C) TEMPERATURE (°C) TEMPERATURE (°C)
8390a G18
8390a G16 8390a G17

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LT8390A
TYPICAL PERFORMANCE CHARACTERISTICS TA = 25°C, unless otherwise noted.

V(ISP-ISN) Regulation
V(ISP-ISN) Regulation vs VCTRL V(ISP-ISN) Regulation vs VISP vs Temperature
125 106 106

104 104
100

102 102

V(ISP-ISN) (mV)

V(ISP-ISN) (mV)
V(ISP-ISN) (mV)

75
100 100
50
98 98

25 96 ISP = 0V
96
ISP = 12V
ISP = 60V
0 94 94
0 0.25 0.50 0.75 1 1.25 1.50 1.75 2 0 10 20 30 40 50 60 –50 –25 0 25 50 75 100 125 150
VCTRL (V) VISP (V) TEMPERATURE (°C)
8390a G19
8390a G20 8390a G21

Maximum Current Sense

V(ISP-ISN) Regulation vs VFB FB Regulation vs Temperature vs Temperature
120 1.03 70

65
100 1.02
60

CURRENT LIMIT (mV)

80 1.01
V(ISP-ISN) (mV)

55
VFB (V)

60 1.00 50

45
40 0.99
40
20 0.98 VIN = 4V
VIN = 12V 35 BUCK
VIN = 60V BOOST
0 0.97 30
0.96 0.97 0.98 0.99 1.00 1.01 1.02 1.03 1.04 –50 –25 0 25 50 75 100 125 150 –50 –25 0 25 50 75 100 125 150
VFB (V) TEMPERATURE (°C) TEMPERATURE (°C)
8390a G22 8390a G23 8390a G24

FB Overvoltage Threshold FB Short Threshold PGOOD Thresholds

1.20 0.40 20

15
1.15 0.35 UPPER RISING
10
THRESHOLD OFFSET (%)

RISING RISING
1.10 0.30 UPPER FALLING
5
FALLING
VFB (V)
VFB (V)

1.05 0.25 0
FALLING
–5
1.00 0.20 LOWER RISING
–10
0.95 0.15 LOWER FALLING
–15

0.90 0.10 –20

–50 –25 0 25 50 75 100 125 150 –50 –25 0 25 50 75 100 125 150 –50 –25 0 25 50 75 100 125 150
TEMPERATURE (°C) TEMPERATURE (°C) TEMPERATURE (°C)
8390a G25 8390a G27
8390a G26

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 LT8390A
TYPICAL PERFORMANCE CHARACTERISTICS TA = 25°C, unless otherwise noted.

Oscillator Frequency
ISMON Voltage vs V(ISP-ISN) SS Current vs Temperature vs Temperature
1.50 15.0 2.5

RT = 59.0k
1.25 12.5

SWITCHING FREQUENCY (MHz)

PULL-UP 2.0

1.00 10.0
1.5 RT = 100k
VISMON (V)

ISS (µA)
0.75 7.5
1.0
0.50 5.0 RT = 226k

0.5
0.25 2.5 PULL-DOWN

0 0.0 0
0 20 40 60 80 100 –50 –25 0 25 50 75 100 125 150 –50 –25 0 25 50 75 100 125 150
V(ISP-ISN) (mV) TEMPERATURE (°C) TEMPERATURE (°C)
8390a G28 8390a G30
8390a G29

PIN FUNCTIONS
BG1: Buck Side Bottom Gate Drive. Drives the gate of buck INTVCC: Internal 5V Linear Regulator Output. The INTVCC
side bottom N-channel MOSFET with a voltage swing from linear regulator is supplied from the VIN pin, and powers the
ground to INTVCC. internal control circuitry and gate drivers. Locally bypass
this pin to ground with a minimum 4.7µF ceramic capacitor.
BST1: Buck Side Bootstrap Floating Driver Supply. The
BST1 pin has an integrated bootstrap Schottky diode from EN/UVLO: Enable and Undervoltage Lockout. Force the
the INTVCC pin and requires an external bootstrap capacitor pin below 0.3V to shut down the part and reduce VIN qui-
to the SW1 pin. The BST1 pin swings from a diode voltage escent current below 2µA. Force the pin above 1.233V for
drop below INTVCC to (VIN + INTVCC). normal operation. The accurate 1.220V falling threshold
can be used to program an undervoltage lockout (UVLO)
SW1: Buck Side Switch Node. The SW1 pin swings from
threshold with a resistor divider from VIN to ground. An
a Schottky diode voltage drop below ground up to VIN.
accurate 2.5µA pull-down current allows the programming
TG1: Buck Side Top Gate Drive. Drives the gate of buck of VIN UVLO hysteresis. If neither function is used, tie this
side top N-channel MOSFET with a voltage swing from pin directly to VIN.
SW1 to BST1.
TEST: Factory Test. This pin is used for testing purpose
LSP: Positive Terminal of the Buck Side Inductor Current only and must be directly connected to ground for the
Sense Resistor (RSENSE). Ensure accurate current sense part to operate properly.
with Kelvin connection.
LOADEN: Load Switch Enable Input. The LOADEN pin is
LSN: Negative Terminal of the Buck Side Inductor Current used to control the ON/OFF of the high side PMOS load
Sense Resistor (RSENSE). Ensure accurate current sense switch. If the load switch control is not used, tie this pin
with Kelvin connection. to VREF or INTVCC. Forcing the pin low turns off TG1 and
VIN: Input Supply. The VIN pin must be tied to the power TG2, turns on BG1 and BG2, disconnects the VC pin from
input to determine the buck, buck-boost, or boost operation all internal loads, and turns off LOADTG.
regions. Locally bypass this pin to ground with a minimum VREF: Voltage Reference Output. The VREF pin provides
1µF ceramic capacitor. an accurate 2V reference capable of supplying 1mA
current. Locally bypass this pin to ground with a 0.47µF
ceramic capacitor.
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LT8390A
PIN FUNCTIONS
CTRL: Control Input for ISP/ISN Current Sense Threshold. short-circuit (VFB < 0.25V) condition, the part gets into one
The CTRL pin is used to program the ISP/ISN current limit: fault mode per customer setting. During an overvoltage
(VFB > 1.1V) condition, the part turns off all TG1, BG1,
Min ( VCTRL − 0.25V,1V ) TG2, BG2, and LOADTG.
IIS(MAX) =
10 • RIS
VC: Error Amplifier Output to Set Inductor Current Com-
The VCTRL can be set by an external voltage reference or parator Threshold. The VC pin is used to compensate the
a resistor divider from VREF to ground. For 0.3V ≤ VCTRL control loop with an external RC network. During LOADEN
≤ 1.15V, the current sense threshold linearly goes up low state, the VC pin is disconnected from all internal loads
from 5mV to 90mV. For VCTRL ≥ 1.35V, the current sense to store its voltage information.
threshold is constant at 100mV full scale value. For 1.15V RT: Switching Frequency Setting. Connect a resistor from
≤ VCTRL ≤ 1.35V, the current sense threshold smoothly this pin to ground to set the internal oscillator frequency
transitions from the linear function of VCTRL to the 100mV from 600kHz to 2MHz.
constant value. Tie CTRL to VREF for the 100mV full scale
threshold. Force the pin below 0.3V to stop switching. SYNC/SPRD: Switching Frequency Synchronization or
Spread Spectrum. Ground this pin for switching at inter-
ISP: Positive Terminal of the ISP/ISN Current Sense Re- nal oscillator frequency. Apply a clock signal for external
sistor (RIS). Ensure accurate current sense with Kelvin frequency synchronization. Tie to INTVCC for 25% triangle
connection. spread spectrum above internal oscillator frequency.
ISN: Negative Terminal of the ISP/ISN Current Sense LOADTG: High Side PMOS Load Switch Top Gate Drive. A
Resistor (RIS). Ensure accurate current sense with Kelvin buffered and inverted version of the LOADEN input signal, the
connection. LOADTG pin drives an external high side PMOS load switch
ISMON: ISP/ISN Current Sense Monitor Output. The ISMON with a voltage swing from the higher voltage of (VOUT-5V)
pin generates a voltage that is equal to ten times V(ISP-ISN) and 1.2V to VOUT. Leave this pin unconnected if not used.
plus 0.25V offset voltage. For parallel applications, tie the VOUT: Output Supply. The VOUT pin must be tied to the
master LT8390A ISMON pin to the slave LT8390A CTRL pin. power output to determine the buck, buck-boost, or boost
PGOOD: Power Good Open Drain Output. The PGOOD operation regions. The VOUT pin also serves as positive rail
pin is pulled low when the FB pin is within ±10% of the for the LOADTG drive. Locally bypass this pin to ground
final regulation voltage. To function, the pin requires an with a minimum 1µF ceramic capacitor.
external pull-up resistor. TG2: Boost Side Top Gate Drive. Drives the gate of boost
SS: Soft-Start Timer Setting. The SS pin is used to set side top N-Channel MOSFET with a voltage swing from
soft-start timer by connecting a capacitor to ground. An SW2 to BST2.
internal 12.5µA pull-up current charging the external SS SW2: Boost Side Switch Node. The SW2 pin swings from
capacitor gradually ramps up FB regulation voltage. A a Schottky diode voltage drop below ground to VOUT.
22nF capacitor is recommended on this pin. Any UVLO or
thermal shutdown immediately pulls SS pin to ground and BST2: Boost Side Bootstrap Floating Driver Supply. The
stops switching. Using a single resistor from SS to VREF, BST2 pin has an integrated bootstrap Schottky diode from
the LT8390A can be set in three different fault protection the INTVCC pin and requires an external bootstrap capacitor
modes during output short-circuit condition: hiccup (no to the SW2 pin. The BST2 pin swings from a diode voltage
resistor), latch-off (499kΩ), and keep-running (100kΩ). drop below INTVCC to (VOUT + INTVCC).
See more details in the Application Information section. BG2: Boost Side Bottom Gate Drive. Drives the gate of
FB: Voltage Loop Feedback Input. The FB pin is used for boost side bottom N-channel MOSFET with a voltage
constant-voltage regulation and output fault protection. swing from ground to INTVCC.
The internal error amplifier with its output VC regulates GND (Exposed Pad): Ground. Solder the exposed pad
VFB to 1.00V through the DC/DC converter. During output directly to the ground plane.
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 LT8390A
BLOCK DIAGRAM
VIN LSN LSP
INTVCC

INTVCC +
5V LDO
A1 + BST1

– A3
TG1
VREF –
2V REF
SW1
PEAK_BUCK BUCK
LOGIC
INTVCC
LOADON
RT
BG1
OSC VOS
SYNC/SPRD

0.3V +
CTRL
– VOUT/BST2 CHARGE
VIN/BST1 CONTROL
+ FB
ISMON FBOV
1X VIS – 1.1V
INHIBIT BG2
SWITCH
EN/UVLO
–
+ VISP-ISN LOADON
BOOST
1.220V + ISOC LOGIC
INTVCC
– 0.75V
PEAK_BOOST
SW2
2.5µA
TG2
+
A4
BST2
LOADEN –

TEST
VREF
0.25V + 12.5µA INTVCC
LOADON SHORT +
VOUT
FB – EA1 + 1V
FB
LOADTG
10µA
–
FAULT
LOGIC
VOUT –5V + 1.1V + CTRL
PGOOD – FB + 1.25V
1.25µA EA2
ISP
+
+ FB LOADON – + A2=10
ISN
– 0.9V –
VIS
SS VC GND 0.25V
8390a BD

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LT8390A
OPERATION
The LT8390A is a current mode DC/DC controller that VIN VOUT

can regulate output voltage, input or output current from TG1 A D TG2
input voltage above, below, or equal to the output voltage. SW1
RSENSE L
SW2
The LTC proprietary peak-buck peak-boost current mode
control scheme uses a single inductor current sense resis- BG1 B C BG2

tor and provides smooth transition between buck region, 8390a F01

buck-boost region, and boost region. Its operation is best

Figure 1. Simplified Diagram of the Power Switches
understood by referring to the Block Diagram.

Power Switch Control

Figure 1 shows a simplified diagram of how the four power PEAK-BUCK
switches A, B, C, and D are connected to the inductor L,
the current sense resistor RSENSE, power input VIN, power
output VOUT, and ground. The current sense resistor RSENSE
connected to the LSP and LSN pins provides inductor
current information for both peak current mode control
and reverse current detection in buck region, buck-boost PEAK-BOOST
region, and boost region. Figure 2 shows the current mode
control as a function of VIN/VOUT ratio and Figure 3 shows 0.98 1.00 1.02 8390a F02

the operation region as a function of VIN/VOUT ratio. The VIN/VOUT

power switches are properly controlled to smoothly transi- Figure 2. Current Mode vs VIN/VOUT Ratio
tion between modes and regions. Hysteresis is added to
prevent chattering between modes and regions.
There are total four states: (1) peak-buck current mode (1)

control in buck region, (2) peak-buck current mode con- BUCK

trol in buck-boost region, (3) peak-boost current mode

control in buck-boost region, and (4) peak-boost current (3)
(2)

mode control in boost region. The following sections give BUCK-BOOST

detailed description for each state with waveforms, in (2)

which the shoot-through protection dead time between
switches A and B, between switches C and D are ignored BOOST

for simplification. (4)

0.75 0.85 1.00 1.25 1.33
VIN/VOUT 8390a F03

Figure 3. Operation Region vs VIN/VOUT Ratio

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 LT8390A
OPERATION
(1) Peak-Buck in Buck Region (VIN >> VOUT) (2) Peak-Buck in Buck-Boost Region (VIN ~> VOUT)
When VIN is much higher than VOUT, the LT8390A uses When VIN is slightly higher than VOUT, the LT8390A uses
peak-buck current mode control in buck region (Figure peak-buck current mode control in buck-boost region
4). Switch C is always off and switch D is always on. At (Figure 5). Switch C is always turned on for the beginning
the beginning of every cycle, switch A is turned on and 20% cycle and switch D is always turned on for the remain-
the inductor current ramps up. When the inductor cur- ing 80% cycle. At the beginning of every cycle, switches
rent hits the peak buck current threshold commanded by A and C are turned on and the inductor current ramps
VC voltage at buck current comparator A3 during (A+D) up. After 20% cycle, switch C is turned off and switch D
phase, switch A is turned off and switch B is turned on is turned on, and the inductor keeps ramping up. When
for the rest of the cycle. Switches A and B will alternate, the inductor current hits the peak buck current threshold
behaving like a typical synchronous buck regulator. commanded by VC voltage at buck current comparator A3
during (A+D) phase, switch A is turned off and switch B
is turned on for the rest of the cycle.

A A

B B

C 100% OFF C 20% 20%

D 100% ON D 80% 80%

IL IL
A+D A+D
B+D B+D A+C B+D A+C B+D
A+D A+D
8390a F05
8390a F04

Figure 4. Peak-Buck in Buck Region (VIN >> VOUT) Figure 5. Peak-Buck in Buck-Boost Region (VIN ~> VOUT)

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LT8390A
OPERATION
(3) Peak-Boost in Buck-Boost Region (VIN <~ VOUT) (4) Peak-Boost in Boost Region (VIN << VOUT)
When VIN is slightly lower than VOUT, the LT8390A uses When VIN is much lower than VOUT, the LT8390A uses
peak-boost current mode control in buck-boost region peak-boost current mode control in boost region (Figure 7).
(Figure 6). Switch A is always turned on for the begin- Switch A is always on and switch B is always off. At the
ning 80% cycle and switch B is always turned on for the beginning of every cycle, switch C is turned on and the
remaining 20% cycle. At the beginning of every cycle, inductor current ramps up. When the inductor current hits
switches A and C are turned on and the inductor current the peak boost current threshold commanded by VC volt-
ramps up. When the inductor current hits the peak boost age at boost current comparator A4 during (A+C) phase,
current threshold commanded by VC voltage at boost switch C is turned off and switch D is turned on for the
current comparator A4 during (A+C) phase, switch C is rest of the cycle. Switches C and D will alternate, behaving
turned off and switch D is turned on for the rest of the like a typical synchronous boost regulator.
cycle. After 80% cycle, switch A is turned off and switch
B is turned on for the rest of the cycle.

A 80% 80% A 100% ON

B 20% 20% B 100% OFF

C C

D D

IL A+D A+D IL
A+C A+C
A+C A+D A+C A+D
B+D B+D
8390a F06 8390a F07

Figure 6. Peak-Boost in Buck-Boost Region (VIN <~ VOUT) Figure 7. Peak-Boost in Boost Region (VIN << VOUT)

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 LT8390A
OPERATION
Main Control Loop Internal Charge Path
The LT8390A is a fixed frequency current mode control- Each of the two top MOSFET drivers is biased from its
ler. The inductor current is sensed through the inductor floating bootstrap capacitor, which is normally re-charged
sense resistor between the LSP and LSN pins. The current by INTVCC through both the external and internal boot-
sense voltage is gained up by amplifier A1 and added to strap diodes when the top MOSFET is turned off. When
a slope compensation ramp signal from the internal os- the LT8390A operates exclusively in the buck or boost
cillator. The summing signal is then fed into the positive regions, one of the top MOSFETs is constantly on. An
terminals of the buck current comparator A3 and boost internal charge path, from VOUT and BST2 to BST1 or from
current comparator A4. The negative terminals of A3 and VIN and BST1 to BST2, charges the bootstrap capacitor to
A4 are controlled by the voltage on the VC pin, which is 4.6V so that the top MOSFET can be kept on.
the diode-OR of error amplifiers EA1 and EA2.
Shutdown and Power-On-Reset
Depending on the state of the peak-buck peak-boost cur-
rent mode control, either the buck logic or the boost logic The LT8390A enters shutdown mode and drains less than
is controlling the four power switches so that either the 2µA quiescent current when the EN/UVLO pin is below its
FB voltage is regulated to 1V or the current sense voltage shutdown threshold (0.3V minimum). Once the EN/UVLO
between the ISP and ISN pins is regulated by the CTRL pin is above its shutdown threshold (1V maximum), the
pin during normal operation. The gains of EA1 and EA2 LT8390A wakes up startup circuitry, generates bandgap
have been balanced to ensure smooth transition between reference, and powers up the internal INTVCC LDO. The
constant-voltage and constant-current operation with the INTVCC LDO supplies the internal control circuitry and gate
same compensation network. drivers. Now the LT8390A enters undervoltage lockout
(UVLO) mode with a hysteresis current (2.5µA typical)
Light Load Current Operation pulled into the EN/UVLO pin. When the INTVCC pin is
charged above its rising UVLO threshold (3.78V typi-
At light load, the LT8390A runs either at full switching fre-
quency discontinuous conduction mode or pulse-skipping cal), the EN/UVLO pin passes its rising enable threshold
mode, where the switches are held off for multiple cycles (1.233V typical), and the junction temperature is less than
its thermal shutdown (165°C typical), the LT8390A enters
(i.e., skipping pulses) to maintain the regulation and
enable mode, in which the EN/UVLO hysteresis current is
improve the efficiency. Both the buck and boost reverse
turned off and the voltage reference VREF is being charged
current sense thresholds are set to 1mV (typical) so that
up from ground. From the time of entering enable mode to
no reverse inductor current is allowed. Such no reverse
the time of VREF passing its rising UVLO threshold (1.89V
inductor current from the output to the input is highly
typical), the LT8390A is going through a power-on-reset
desired in certain applications.
(POR), waking up the entire internal control circuitry and
In the buck region, switch B is turned off whenever the settling to the right initial conditions. After the POR, the
buck reverse current threshold is triggered during (B+D) LT8390A is ready and waiting for the signals on the CTRL
phase. In the boost region, switch D is turned off whenever and LOADEN pins to start switching.
the boost reverse current threshold is triggered during
(A+D) phase. In the buck-boost region, switch D is turned
off whenever the boost reverse current threshold is trig-
gered during (A+D) phase, and both switches B and D are
turned off whenever the buck reverse current threshold is
triggered during (B+D) phase.

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LT8390A
OPERATION
Start-Up and Fault Protection above 0.25V, the LT8390A enters the UP/TRY state, where
the LOADTG is turned on first while the switching is still
Figure 8 shows the start-up and fault sequence for the
disabled. If an excessive current flowing through the
LT8390A. During the POR state, the SS pin is hard pulled
current sense resistor triggers the ISP/ISN over current
down with a 100Ω to ground. In a pre-biased condition,
(ISOC) signal, it will reset the LT8390A back into the POR
the SS pin has to be pulled below 0.2V to enter the INIT
state. After 10µs in the UP/TRY state without triggering
state, where the LT8390A wait 10µs so that the SS pin can
the ISOC signal, the LT8390A enters the UP/RUN state.
be fully discharged to ground. After the 10µs, the LT8390A
enters the UP/PRE state when the LOADON signal goes During the UP/RUN state, the switching is enabled and
high. The LOADON high signal happens when CTRL pin is the start-up of the output voltage VOUT is controlled by
above its rising latch-off thresholds (0.325V typical) and the voltage on the SS pin. When the SS pin voltage is less
the LOADEN is high. than 1V, the LT8390A regulates the FB pin voltage to the
SS pin voltage instead of the 1V reference. This allows the
During the UP/PRE state, the SS pin is charged up by a
SS pin to be used to program soft-start by connecting an
12.5µA pull-up current while the switching is disabled
external capacitor from the SS pin to GND. The internal
and the LOADTG is turned off. Once the SS pin is charged
12.5µA pull-up current charges up the capacitor, creating
POR = HI or a voltage ramp on the SS pin. As the SS pin voltage rises
ISOC = HI
linearly from 0.25V to 1V (and beyond), the output voltage
POR INIT VOUT rises smoothly to its final regulation voltage.
• SS hard pull down • SS hard pull down
• Switching disabled SS < 0.2V • Switching disabled Once the SS pin is charged above 1.75V, the LT8390A
• LOADTG turned off • LOADTG turned off
• No short detection • No short detection enters the OK/RUN state, where the output short detec-
Wait 10µs and
tion is activated. The output short means VFB < 0.25V.
LOADON = HI When the output short happens, the LT8390A enters
UP/TRY UP/PRE the FAULT/RUN state, where a 1.25µA pull-down current
• SS 12.5µA pull up
SS > 0.25V
• SS 12.5µA pull up slowly discharges the SS pin with the other conditions the
• Switching disabled • Switching disabled
• LOADTG turned on • LOADTG turned off same as the OK/RUN state. Once the SS pin is discharged
• No short detection • No short detection
below 1.7V, the LT8390A enters the DOWN/STOP state,
Wait 10µs where the switching is disabled and the short detection is
deactivated with the previous fault latched. Once the SS
UP/RUN OK/RUN
• SS 12.5µA pull up • SS 12.5µA pull up
pin is discharged below 0.2V and the LOADON signal is
• Switching enabled SS > 1.75V • Switching enabled still high, the LT8390A goes back to the UP/RUN state.
• LOADTG turned on • LOADTG turned on
• No short detection • Short detection
In an output short condition, the LT8390A can be set to
SS < 0.2V and SHORT hiccup, latch-off, or keep-running fault protection mode
LOADON = HI
with a resistor between the SS and VREF pins. Without
DOWN/STOP FAULT/RUN
any resistor, the LT8390A will hiccup between 0.2V and
• SS 1.25µA pull down • SS 1.25µA pull down
• Switching disabled SS < 1.7V • Switching enabled 1.75V and go around the UP/RUN, OK/RUN, FAULT/RUN,
• LOADTG turned on
• No short detection
• LOADTG turned on
• Short detection and DOWN/STOP states until the fault condition is cleared.
8390a F08
With a 499kΩ resistor, the LT8390A will latch off until the
EN/UVLO is toggled. With a 100kΩ resistor, the LT8390A
Figure 8. Start-Up and Fault Sequence
will keep running regardless of the fault.

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 LT8390A
APPLICATIONS INFORMATION
The front page shows a typical LT8390A application circuit. implements a triangle spread spectrum frequency modu-
This Applications Information section serves as a guideline lation scheme. With the SYNC/SPRD pin tied to INTVCC,
of selecting external components for typical applications. the LT8390A starts to spread its switching frequency 25%
The examples and equations in this section assume con- above the internal oscillator frequency. Figure 9 and Figure
tinuous conduction mode unless otherwise specified. 10 show the noise spectrum of the front page application
when spread spectrum enabled.
Switching Frequency Selection
90
The LT8390A uses a constant frequency control scheme 80
SSFM ON WITH EMI FILTER
NOISE FLOOR
between 600kHz and 2MHz. Selection of the switching 70 CISPER 25 CLASS 5 PEAK LIMITS
frequency is a tradeoff between efficiency and component 60
LW

EMI (dBµV)
50
size. Low frequency operation improves efficiency by 40 MW SW
reducing MOSFET switching losses, but requires larger 30 CB
inductor and capacitor values. For high power applica- 20

tions, consider operating at lower frequencies to minimize 10

0
MOSFET heating from switching losses. For low power –10
applications, consider operating at higher frequencies to 0.1 1
FREQUENCY (MHz)
10

minimize the total solution size. 8390a F09

Figure 9. Average Conducted EMI

In addition, the specific application also plays an important
role in switching frequency selection. In a noise-sensitive
system, the switching frequency is usually selected to keep 90
80
SSFM ON WITH EMI FILTER
the switching noise out of a sensitive frequency band. 70
LW NOISE FLOOR
CISPER 25 CLASS 5 PEAK LIMITS
60 MW SW
Switching Frequency Setting
EMI (dBµV)

50 CB
40
The switching frequency of the LT8390A can be set by 30
the internal oscillator. With the SYNC/SPRD pin pulled to 20
10
ground, the switching frequency is set by a resistor from 0
the RT pin to ground. Table 1 shows RT resistor values –10
0.1 1 10
for common switching frequencies. FREQUENCY (MHz)
8390a F10

Table 1. Switching Frequency vs RT Value (1% Resistor) Figure 10. Peak Conducted EMI
fOSC (MHz) RT (k)
0.6 267 Frequency Synchronization
0.8 191 The LT8390A switching frequency can be synchronized to
1.0 147 an external clock using the SYNC/SPRD pin. Driving the
1.2 118 SYNC/SPRD with a 50% duty cycle waveform is always a
1.4 97.6 good choice, otherwise maintain the duty cycle between
1.6 82.5 10% and 90%. Due to the use of a phase-locked loop (PLL)
1.8 66.5 inside, there is no restriction between the synchronization
2.0 59.0 frequency and the internal oscillator frequency. The rising
Spread Spectrum Frequency Modulation edge of the synchronization clock represents the begin-
ning of a switching cycle, turning on switches A and C,
Switching regulators can be particularly troublesome for or switches A and D.
applications where electromagnetic interference (EMI) is
a concern. To improve the EMI performance, the LT8390A
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LT8390A
APPLICATIONS INFORMATION
Inductor Selection RSENSE Selection and Maximum Output Current
The switching frequency and inductor selection are inter- RSENSE is chosen based on the required output current.
related in that higher switching frequencies allow the use of The duty cycle independent maximum current sense
smaller inductor and capacitor values. The inductor value thresholds (50mV in peak-buck and 50mV in peak-boost)
has a direct effect on ripple current. The highest current set the maximum inductor peak current in buck region,
ripple ∆IL% happens in the buck region at VIN(MAX), and the buck-boost region, and boost region.
lowest current ripple ∆IL% happens in the boost region at
In boost region, the lowest maximum average load current
VIN(MIN). For any given ripple allowance set by customers,
happens at VIN(MIN) and can be calculated as:
the minimum inductance can be calculated as:
 50mV ∆IL(BOOST)  VIN(MIN)
VOUT • ( VIN(MAX) − VOUT ) IOUT(MAX _ BOOST) =  − •
LBUCK >  RSENSE 2  VOUT
f •IOUT(MAX) • ∆IL % • VIN(MAX)
where ∆IL(BOOST) is peak-to-peak inductor ripple current
VIN(MIN)2 • ( VOUT − VIN(MIN) )
LBOOST > in boost region and can be calculated as:
f •IOUT(MAX) • ∆IL % • VOUT2
VIN(MIN) • ( VOUT − VIN(MIN) )
∆IL(BOOST) =
where: f • L • VOUT
∆IL In buck region, the lowest maximum average load current
∆IL % =
IL(AVG) happens at VIN(MAX) and can be calculated as:

 50mV ∆IL(BUCK) 
f is switching frequency IOUT(MAX _ BUCK) =  − 
 RSENSE 2 
VIN(MIN) is minimum input voltage
VIN(MAX) is maximum input voltage where ∆IL(BUCK) is peak-to-peak inductor ripple current in
buck region and can be calculated as:
VOUT is output voltage
IOUT(MAX) is maximum output current VOUT • ( VIN(MAX) − VOUT )
∆IL(BUCK) =
Slope compensation provides stability in constant fre- f • L • VIN(MAX)

quency current mode control by preventing subharmonic
The maximum current sense RSENSE in boost region is:
oscillations at certain duty cycles. The minimum inductance
required for stability when duty cycles are larger than 50%
can be calculated as: 2 • 50mV • VIN(MIN)
RSENSE(BOOST) =
10 • VOUT • RSENSE 2 •IOUT(MAX) • VOUT + ∆IL(BOOST) • VIN(MIN)
L>
f
The maximum current sense RSENSE in buck region is
For high efficiency, choose an inductor with low core loss, 2 • 50mV
such as ferrite. Also, the inductor should have low DC RSENSE(BUCK) =
2 •IOUT(MAX) + ∆IL(BUCK)
resistance to reduce the I2R losses, and must be able to
handle the peak inductor current without saturating. To
The final RSENSE value should be lower than the calculated
minimize radiated noise, use a shielded inductor.
RSENSE in both buck and boost regions. A 20% to 30%
margin is usually recommended. Always choose a low
ESL current sense resistor.
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 LT8390A
APPLICATIONS INFORMATION
Power MOSFET Selection RL is the maximum DCR resistor of inductor at 25°C
The LT8390A requires four external N-channel power MOS- The RDS(ON) and DCR increase at higher junction
FETs, two for the top switches (switches A and D shown temperatures and the process variation have been included
in Figure 1) and two for the bottom switches (switches B in the calculation above.
and C shown in Figure 1). Important parameters for the
In order to select the power MOSFETs, the power dis-
power MOSFETs are the breakdown voltage VBR(DSS),
sipated by the device must be known. For switch A, the
threshold voltage VGS(TH), on-resistance RDS(ON), reverse
maximum power dissipation happens in boost region, when
transfer capacitance CRSS and maximum current IDS(MAX).
it remains on all the time. Its maximum power dissipation
To achieve 2MHz operation, the power MOSFET selection at maximum output current is given by:
is critical. With typical 25ns shoot-through protection
deadtime, high performance power MOSFETs with low  IOUT(MAX) • VOUT  2
PA(BOOST) =   • ρT • RDS(ON)
Qg and low RDS(ON) must be used.  VIN 

Since the gate drive voltage is set by the 5V INTVCC supply,
logic-level threshold MOSFETs must be used in LT8390A where ρT is a normalization factor (unity at 25°C) ac-
applications. Switching four MOSFETs at higher frequency counting for the significant variation in on-resistance with
like 2MHz, the substantial gate charge current from INTVCC temperature, typically 0.4%/°C as shown in Figure 11. For
can be estimated as: a maximum junction temperature of 125°C, using a value
of ρT = 1.5 is reasonable.
IINTVCC = f • (QgA +QgB +QgC +QgD) Switch B operates in buck region as the synchronous

rectifier. Its power dissipation at maximum output cur-
where: rent is given by:
f is the switching frequency VIN − VOUT
PB(BUCK) = •IOUT(MAX)2 • ρT • RDS(ON)
QgA, QgB, QgC, QgD are the total gate charges of MOSFETs VIN
A, B, C, D

Make sure the total required INTVCC current not exceed- Switch C operates in boost region as the control switch.
ing the INTVCC current limit in the datasheet. Typically, Its power dissipation at maximum current is given by:
MOSFETs with less than 10nC Qg are recommended.
PC(BOOST) =
( VOUT − VIN ) • VOUT •I 2
• ρT
2 OUT(MAX)
The LT8390A uses the VIN/VOUT ratio to transition between VIN
modes and regions. Bigger IR drop in the power path caused
IOUT(MAX)
by improper MOSFET and inductor selection may prevent • RDS(ON) + k • VOUT3 • • CRSS • f
the LT8390A from smooth transition. To ensure smooth VIN
transitions between buck, buck-boost, and boost modes 2.0
of operation, choose low RDS(ON) MOSFETs and low DCR
ρT NORMALIZED ON-RESISTANCE (Ω)

inductor to satisfy: 1.5

0.025• VOUT
IOUT(MAX) ≤
RA,B +RC,D +RSENSE +RL 1.0

where: 0.5

RA,B is the maximum RDS(ON) of MOSFETs A or B at 25°C 0

–50 0 50 100 150
RC,D is the maximum RDS(ON) of MOSFETs C or D at JUNCTION TEMPERATURE (°C)
8390a F11

25°C
Figure 11. Normalized RDS(ON) vs Temperature
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LT8390A
APPLICATIONS INFORMATION
where CRSS is usually specified by the MOSFET manufac- CIN and COUT Selection
turers. The constant k, which accounts for the loss caused Input and output capacitance is necessary to suppress
by reverse recovery current, is inversely proportional to voltage ripple caused by discontinuous current moving
the gate drive current and has an empirical value of 1.7. in and out the regulator. A parallel combination of capaci-
For switch D, the maximum power dissipation happens in tors is typically used to achieve high capacitance and low
boost region, when its duty cycle is higher than 50%. Its equivalent series resistance (ESR). Dry tantalum, special
maximum power dissipation at maximum output current polymer, aluminum electrolytic and ceramic capacitors are
is given by: all available in surface mount packages. Capacitors with
VOUT low ESR and high ripple current ratings, such as OS-CON
PD(BOOST) = •IOUT(MAX)2 • ρT • RDS(ON) and POSCAP are also available.
VIN
Ceramic capacitors should be placed near the regula-tor
For the same output voltage and current, switch A has the input and output to suppress high frequency switching
highest power dissipation and switch B has the lowest spikes. Ceramic capacitors, of at least 1µF, should also
power dissipation unless a short occurs at the output. be placed from VIN to GND and VOUT to GND as close to
the LT8390A pins as possible. Due to their excellent low
From a known power dissipated in the power MOSFET, its
ESR characteristics, ceramic capacitors can significantly
junction temperature can be obtained using the following
reduce input ripple voltage and help reduce power loss in
formula:
the higher ESR bulk capacitors. X5R or X7R dielectrics are
TJ = TA + P • RTH(JA) preferred, as these materials retain their capacitance over
The junction-to-ambient thermal resistance RTH(JA) in- wide voltage and temperature ranges. Many ceramic ca-
cludes the junction-to-case thermal resistance RTH(JC) pacitors, particularly 0805 or 0603 case sizes, have greatly
and the case-to-ambient thermal resistance RTH(CA). This reduced capacitance at the desired operating voltage.
value of TJ can then be compared to the original, assumed Input Capacitance CIN: Discontinuous input current is
value used in the iterative calculation process. highest in the buck region due to the switch A toggling
on and off. Make sure that the CIN capacitor network has
Optional Schottky Diode (DB, DD) Selection low enough ESR and is sized to handle the maximum RMS
The optional Schottky diodes DB (in parallel with switch current. In buck region, the input RMS current is given by:
B) and DD (in parallel with switch D) conduct during the VOUT VIN
dead time between the conduction of the power MOSFET IRMS ≈ IOUT(MAX) • • −1
switches. They are intended to prevent the body diode of VIN VOUT

synchronous switches B and D from turning on and storing
The formula has a maximum at VIN = 2VOUT, where IRMS
charge during the dead time. In particular, DB significantly
= IOUT(MAX) /2. This simple worst-case condition is com-
reduces reverse recovery current between switch B turn-
monly used for design because even significant deviations
off and switch A turn-on, and DD significantly reduces
do not offer much relief.
reverse recovery current between switch D turn-off and
switch C turn-on. They improve converter efficiency and Output Capacitance COUT: Discontinuous current shifts
reduce switch voltage stress. In order for the diode to be from the input to the output in the boost region. Make sure
effective, the inductance between it and the synchronous that the COUT capacitor network is capable of reducing
switch must be as small as possible, mandating that these the output voltage ripple. The effects of ESR and the bulk
components be placed adjacently. capacitance must be considered when choosing the right
capacitor for a given output ripple voltage. The maximum
steady state ripple due to charging and discharging the
bulk capacitance is given by:
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20 For more information www.linear.com/LT8390A

 LT8390A
APPLICATIONS INFORMATION
IOUT(MAX) • ( VOUT − VIN(MIN) ) Top Gate MOSFET Driver Supply (CBST1, CBST2)
∆VCAP(BOOST) = The top MOSFET drivers, TG1 and TG2, are driven between
COUT • VOUT • f
their respective SW and BST pin voltages. The boost volt-
 V  ages are biased from floating bootstrap capacitors CBST1
VOUT • 1− OUT 
 VIN(MAX)  and CBST2, which are normally recharged through both the
∆VCAP(BUCK) = external and internal bootstrap diodes when the respective
8 • L • f2 • COUT top MOSFET is turned off. External bootstrap diodes are
recommended because the internal bootstrap diodes are
The maximum steady ripple due to the voltage drop across
not always strong enough to refresh top MOSFETs at 2MHz.
the ESR is given by:
Both capacitors are charged to the same voltage as the
VOUT •IOUT(MAX) INTVCC voltage. The bootstrap capacitors CBST1 and CBST2,
∆VESR(BOOST) = • ESR need to store about 100 times the gate charge required by
VIN(MIN)
the top switches A and D. In most applications, a 0.1µF
 V  to 0.47µF, X5R or X7R dielectric capacitor is adequate.
VOUT • 1− OUT 
 VIN(MAX)  Programming VIN UVLO
∆VESR(BUCK) = • ESR
L•f
A resistor divider from VIN to the EN/UVLO pin implements
INTVCC Regulator VIN undervoltage lockout (UVLO). The EN/UVLO enable
falling threshold is set at 1.220V with 13mV hysteresis. In
An internal P-channel low dropout regulator produces addition, the EN/UVLO pin sinks 2.5µA when the voltage
5V at the INTVCC pin from the VIN supply pin. The INTVCC on the pin is below 1.220V. This current provides user
powers internal circuitry and gate drivers in the LT8390A. programmable hysteresis based on the value of R1. The
The INTVCC regulator can supply a peak current of 145mA programmable UVLO thresholds are:
and must be bypassed to ground with a minimum of
4.7µF ceramic capacitor. Good local bypass is necessary R1+R2
VIN(UVLO+) = 1.233V • + 2.5µA • R1
to supply the high transient current required by MOSFET R2
gate drivers. R1+R2
VIN(UVLO−) = 1.220V •
Higher input voltage applications with large MOSFETs be- R2
ing driven at higher switching frequencies may cause the Figure 12 shows the implementation of external shut-down
maximum junction temperature rating for the LT8390A control while still using the UVLO function. The NMOS
to be exceeded. The system supply current is normally grounds the EN/UVLO pin when turned on, and puts the
dominated by the gate charge current. Additional external LT8390A in shutdown with quiescent current less than 2µA.
loading of the INTVCC also needs to be taken into account
for the power dissipation calculation. The total LT8390A VIN
power dissipation in this case is VIN • IINTVCC, and overall
R1
efficiency is lowered. The junction temperature can be
estimated by using the equation: EN/UVLO
RUN/STOP
TJ = TA + PD • θJA
LT8390A R2 CONTROL
(OPTIONAL)

where θJA (in °C/W) is the package thermal resistance. GND

To prevent maximum junction temperature from being

8390a F12

exceeded, the input supply current must be checked op- Figure 12. VIN Undervoltage Lockout (UVLO)
erating in continuous mode at maximum VIN.
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For more information www.linear.com/LT8390A 21

LT8390A
APPLICATIONS INFORMATION
Programming Input or Output Current Limit frequency is expected. If the current sense resistor RIS
is placed between power input and input bulk capacitor
The input or output current limit can be programmed by
(Figure 13a), or between output bulk capacitor and system
placing an appropriate value current sense resistor, RIS, in
the input or output power path. The voltage drop across output (Figure 14a), a filter is typically not necessary. If
RIS is (Kelvin) sensed by the ISP and ISN pins. The CTRL the RIS is placed between input bulk capacitor and input
decoupling capacitor (Figure 13b), or between output
pin should be tied to a voltage higher than 1.35V to get
decoupling capacitor and output bulk capacitor (Figure
the full-scale 100mV (typical) threshold across the sense
14b), a low pass filter formed by RF and CF is recom-
resistor. The CTRL pin can be used to reduce the current
mended to reduce the current ripple and stabilize the
threshold to zero, although relative accuracy decreases
current loop. Since the bias currents of the ISP and ISN
with the decreasing sense threshold. When the CTRL pin
pins are matched, no offset is introduced by RF. If input
voltage is between 0.3V and 1.15V, the current limit is:
or output current limit is not used, the ISP and ISN pins
VCTRL − 0.25V should be shorted to VIN, VOUT, or ground.
IIS(MAX) =
10 • RIS
ISMON Current Monitor
When VCTRL is between 1.15V and 1.35V the current limit The ISMON pin provides a buffered monitor output of the
varies with VCTRL, but departs from the equation above current flowing through the ISP/ISN current sense resistor,
by an increasing amount as VCTRL increases. Ultimately, RIS. The VISMON voltage is calculated as V(ISP-ISN) • 10 +
when VCTRL is larger than 1.35V, the current limit no 0.25V. Since the ISMON pin has the same 0.25V offset
longer varies. The typical V(ISP-ISN) threshold vs VCTRL is as the CTRL pin, the master LT8390A ISMON pin can
listed in Table 2. be directly tied to the slave LT8390A CTRL pin for equal
Table 2. V(ISP-ISN) Threshold vs VCTRL current sharing in parallel applications.
VCTRL (V) V(ISP-ISN) (mV)
RIS
1.15 90 FROM POWER TO DRAIN OF
INPUT + SWITCH A
1.20 94.5
1.25 98
1.30 99.5 ISP ISN
1.35 100 LT8390A

8390a F13a

When VCTRL is larger than 1.35V, the current threshold (13a)

is regulated to:
RIS
100mV FROM POWER TO DRAIN OF
IIS(MAX) = INPUT + SWITCH A

RIS RF RF
CF

The CTRL pin should not be left open (tie to VREF if not
used). The CTRL pin can also be used in conjunction with ISP ISN
a thermistor to provide overtemperature protection for LT8390A
the output load, or with a resistor divider to VIN to reduce
output power and switching current when VIN is low. 8390a F13b

The presence of a time varying differential voltage ripple (13b)

signal across the ISP and ISN pins at the switching Figure 13. Programming Input Current Limit

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22 For more information www.linear.com/LT8390A

 LT8390A
APPLICATIONS INFORMATION
FROM DRAIN OF
RIS
TO SYSTEM Programming Output Voltage and Thresholds
SWITCH D + OUTPUT
The LT8390A has a voltage feedback pin FB that can be
used to program a constant-voltage output. The output
ISP ISN voltage can be set by selecting the values of R3 and R4
LT8390A
(Figure 15) according to the following equation:
R3+R4
8390a F14a VOUT = 1V •
(14a) R4
In addition, the FB pin also sets output overvoltage
RIS
FROM DRAIN OF
SWITCH D
TO SYSTEM
OUTPUT
threshold, output power good thresholds, and output
+
RF RF
short threshold. For an application with small output
CF capacitors, the output voltage may overshoot a lot during
VOUT
ISP ISN

LT8390A LT8390A R3

FB
8390a F14b
R4
(14b) 8390a F15

Figure 14. Programming Output Current Limit

Figure 15. Feedback Resistor Connection

Load Switch Control load transient event. Once the FB pin hits its overvoltage
The LOADEN and LOADTG pins provide high side PMOS threshold 1.1V, the LT8390A stops switching by turning
load switch control. The LOADEN pin accepts a logic level off TG1, BG1, TG2, and BG2, and also turns off LOADTG
ON/OFF signal and then drives the LOADTG pin to turn on to disconnect the output load for protection. The output
or off the high side PMOS load switch, thereby connect- overvoltage threshold can be set as:
ing or disconnecting the LT8390A power output from the R3+R4
system output. When the LOADEN pin is forced low, the VOUT(OVP) = 1.1V •
R4
LT8390A turns off TG1 and TG2, turns on BG1 and BG2,
disconnects the VC pin from all internal loads, and turns To provide the output short-circuit detection and protection,
off LOADTG. The LOADEN pin should not be left open (tie the output short falling threshold can be set as:
to INTVCC or VREF if not used).
R3+R4
VOUT(SHORT) = 0.25V •
High Side PMOS Load Switch Selection R4
A high side PMOS load switch is recommended in some
Power GOOD (PGOOD) Pin
LT8390A applications requiring load switch control. The
high side PMOS load switch is typically selected for drain- The LT8390A provides an open-drain status pin, PGOOD,
source voltage VDS, gate-source threshold voltage VGS(TH), which is pulled low when VFB is within ±10% of the 1.00V
and continuous drain current ID. For proper operations, regulation voltage. The PGOOD pin is allowed to be pulled
VDS rating should exceed the output regulation voltage up by an external resistor to INTVCC or an external voltage
set by the FB pin, the absolute value of VGS(TH) should source of up to 6V.
be less than 3V, and ID rating should be above IOUT(MAX).

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LT8390A
APPLICATIONS INFORMATION
Soft-Start and Short-Circuit Protection trol loop. The external inductor, output capacitor, and the
As shown in Figure 8 and explained in the Operation sec- compensation resistor and capacitor determine the loop
tion, the SS pin can be used to program the output voltage stability.
soft-start by connecting an external capacitor from the SS The inductor and output capacitor are chosen based on
pin to ground. The internal 12.5µA pull-up current charges performance, size and cost. The compensation resistor
up the capacitor, creating a voltage ramp on the SS pin. and capacitor on the VC pin are set to optimize control
As the SS pin voltage rises linearly from 0.25V to 1V (and loop response and stability. For a typical voltage regulator
beyond), the output voltage rises smoothly into its final application, a 2.2nF compensation capacitor on the VC pin
voltage regulation. The soft-start time can be calculated as: is adequate, and a series resistor should always be used
CSS to increase the slew rate on the VC pin to maintain tighter
tSS = 1V • output voltage regulation during fast transients on the
12.5µA input supply of the converter.
Make sure the CSS is at least five to ten times larger than the
Efficiency Considerations
compensation capacitor on the VC pin for a well-controlled
output voltage soft-start. A 22nF ceramic capacitor is a The power efficiency of a switching regulator is equal to
good starting point. the output power divided by the input power times 100%.
It is often useful to analyze individual losses to determine
The SS pin is also used as a fault timer. Once an output
what is limiting the efficiency and which change would
short-circuit fault is detected, a 1.25µA pull-down current
produce the most improvement. Although all dissipative
source is activated. Using a single resistor from the SS pin
elements in circuits produce losses, four main sources
to the VREF pin, the LT8390A can be set to three different
account for most of the losses in LT8390A circuits:
fault protection modes: hiccup (no resistor), latch-off
(499k), and keep-running (100k). 1. DC I2R losses. These arise from the resistances of the
MOSFETs, sensing resistor, inductor and PC board
With a 100k resistor in keep-running mode, the LT8390A
traces and cause the efficiency to drop at high output
continues switching normally and regulates the current
currents.
into ground. With a 499k resistor in latch-off mode, the
LT8390A stops switching until the EN/UVLO pin is pulled 2. Transition loss. This loss arises from the brief amount
low and high to restart. With no resistor in hiccup mode, of time switch A or switch C spends in the saturated
the LT8390A enters low duty cycle auto-retry operation. region during switch node transitions. It depends upon
The 1.25µA pull-down current discharges the SS pin to the input voltage, load current, driver strength and
0.2V and then 12.5µA pull-up current charges the SS MOSFET capacitance, among other factors.
pin up. If the output short-circuit condition has not been 3. INTVCC current. This is the sum of the MOSFET driver
removed when the SS pin reaches 1.75V, the 1.25µA and control currents.
pull-down current turns on again, initiating a new hiccup
cycle. This will continue until the fault is removed. Once 4. CIN and COUT loss. The input capacitor has the dif-
the output short-circuit condition is removed, the output ficult job of filtering the large RMS input current to the
will have a smooth short-circuit recovery due to soft-start. regulator in buck region. The output capacitor has the
difficult job of filtering the large RMS output current in
Loop Compensation boost region. Both CIN and COUT are required to have
low ESR to minimize the AC I2R loss and sufficient
The LT8390A uses an internal transconductance error
capacitance to prevent the RMS current from causing
amplifier, the output of which, VC, compensates the con-
additional upstream losses in fuses or batteries.

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24 For more information www.linear.com/LT8390A

 LT8390A
APPLICATIONS INFORMATION
5. Other losses. Schottky diode DB and DD are responsible n Place switch A and switch C as close to the controller as
for conduction losses during dead time and light load possible, keeping the PGND, BG and SW traces short.
conduction periods. Inductor core loss occurs predomi- n Keep the high dV/dT SW1, SW2, BST1, BST2, TG1 and
nately at light loads. Switch A causes reverse recovery
TG2 nodes away from sensitive small-signal nodes.
current loss in buck region, and switch C causes reverse
recovery current loss in boost region. n The path formed by switch A, switch B, DB and the
CIN capacitor should have short leads and PCB trace
When making adjustments to improve efficiency, the lengths. The path formed by switch C, switch D, DD and
input current is the best indicator of changes in ef- the COUT capacitor also should have short leads and
ficiency. If you make a change and the input current PCB trace lengths.
decreases, then the efficiency has increased. If there is
no change in the input current, then there is no change n The output capacitor (–) terminals should be connected
in efficiency. as close as possible to the (–) terminals of the input
capacitor.
PC Board Layout Checklist n Connect the top driver bootstrap capacitor CBST1 closely
The basic PC board layout requires a dedicated ground to the BST1 and SW1 pins. Connect the top driver
plane layer. Also, for high current, a multilayer board bootstrap capacitor CBST2 closely to the BST2 and SW2
provides heat sinking for power components. pins.
n The ground plane layer should not have any traces and n Connect the input capacitors CIN and output capacitors
it should be as close as possible to the layer with power COUT closely to the power MOSFETs. These capacitors
MOSFETs. carry the MOSFET AC current.
n Place CIN, switch A, switch B and DB in one compact n Route LSP and LSN traces together with minimum
area. Place COUT, switch C, switch D and DD in one PCB trace spacing. Avoid sense lines pass through
compact area. noisy areas, such as switch nodes. The filter capacitor
n Use immediate vias to connect the components to the between LSP and LSN should be as close as possible
ground plane. Use several large vias for each power to the IC. Ensure accurate current sensing with Kelvin
component. connections at the RSENSE resistor. Low ESL sense
resistor is recommended.
n Use planes for VIN and VOUT to maintain good voltage n Connect the VC pin compensation network close to the
filtering and to keep power losses low.
IC, between VC and the signal ground. The capacitor
n Flood all unused areas on all layers with copper. Flooding helps to filter the effects of PCB noise and output volt-
with copper will reduce the temperature rise of power age ripple voltage from the compensation loop.
components. Connect the copper areas to any DC net n Connect the INTVCC bypass capacitor, CINTVCC, close to
(VIN or GND).
the IC, between the INTVCC and the power ground. This
n Separate the signal and power grounds. All small-signal capacitor carries the MOSFET drivers’ current peaks.
components should return to the exposed GND pad
from the bottom, which is then tied to the power GND
close to the sources of switch B and switch C.

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For more information www.linear.com/LT8390A 25

LT8390A
TYPICAL APPLICATIONS
95% Efficient 48W (12V 4A) 2MHz Buck-Boost Voltage Regulator

R1 L1 R2
M1 5mΩ 1µH M4 10mΩ
VIN VOUT
6V TO 28V 12V
CONTINUOUS 22µF 22µF 22µF 4A
0.1µF SW1 LSP LSN SW2 0.1µF
4V TO 56V 63V 0.1µF 16V 16V
0.1µF
TRANSIENT 100V BST1 BST2 ×2
16V
4.7µF ×2 ×2
100V D1 D2
×2 INTVCC INTVCC
M2 BG1 BG2 M3
GND
TG1 TG2
VIN LT8390A VOUT

383k 1µF 1µF

10
EN/UVLO ISP
1µF 10
LOADTG ISN 110k
169k
TEST FB
SSFM OFF
ISMON ISMON SYNC/SPRD 10k
INTVCC
CTRL INTVCC SSFM ON

100k 133k LOADEN 4.7µF 100k

L1: WURTH 74437336010 1µH
VREF PGOOD PGOOD M1, M2: INFINEON BSZ065NO6LS5
0.47µF SS VC RT M3, M4: INFINEON BSZ033NE2LS5
D1, D2: NXP BAT46WJ
22nF 59.0k R1: Susumu KRL3216D-M-R005-F-T5
10k
2MHz
2.2nF
8390a TA02a

8390afa

26 For more information www.linear.com/LT8390A

 LT8390A
PACKAGE DESCRIPTION
Please refer to http://www.linear.com/product/LT8390A#packaging for the most recent package drawings.

FE Package
28-Lead Plastic TSSOP (4.4mm)
(Reference LTC DWG # 05-08-1663 Rev L)
Exposed Pad Variation EB

4.75 9.60 – 9.80*

(.187) (.378 – .386)
4.75
(.187)
28 27 26 2524 23 22 21 20 1918 17 16 15

2.74 EXPOSED
6.60 ±0.10
(.108) PAD HEAT SINK
4.50 ±0.10 SEE NOTE 4 ON BOTTOM OF 6.40
PACKAGE 2.74
0.45 ±0.05 (.252)
(.108)
BSC
1.05 ±0.10

0.65 BSC
RECOMMENDED SOLDER PAD LAYOUT
1 2 3 4 5 6 7 8 9 10 11 12 13 14
1.20
4.30 – 4.50* (.047)
(.169 – .177) 0.25 MAX
REF
0° – 8°

0.65
0.09 – 0.20 0.50 – 0.75 (.0256) 0.05 – 0.15
(.0035 – .0079) (.020 – .030) BSC (.002 – .006)
0.195 – 0.30
FE28 (EB) TSSOP REV L 0117
(.0077 – .0118)
TYP
NOTE:
1. CONTROLLING DIMENSION: MILLIMETERS 4. RECOMMENDED MINIMUM PCB METAL SIZE
2. DIMENSIONS ARE IN MILLIMETERS FOR EXPOSED PAD ATTACHMENT
(INCHES) *DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH
3. DRAWING NOT TO SCALE SHALL NOT EXCEED 0.150mm (.006") PER SIDE

8390afa

For more information www.linear.com/LT8390A 27

LT8390A
PACKAGE DESCRIPTION
Please refer to http://www.linear.com/product/LT8390A#packaging for the most recent package drawings.

UFD Package
28-Lead Plastic QFN (4mm × 5mm)
(Reference LTC DWG # 05-08-1712 Rev C)

0.70 ±0.05

4.50 ±0.05
3.10 ±0.05

2.50 REF
2.65 ±0.05
3.65 ±0.05

PACKAGE OUTLINE

0.25 ±0.05
0.50 BSC
3.50 REF
4.10 ±0.05
5.50 ±0.05

RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS

APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED PIN 1 NOTCH
2.50 REF R = 0.20 OR 0.35
R = 0.05 R = 0.115 × 45° CHAMFER
4.00 ±0.10 0.75 ±0.05
TYP TYP
(2 SIDES) 27 28

0.40 ±0.10
PIN 1
TOP MARK
(NOTE 6) 1

5.00 ±0.10
3.50 REF
(2 SIDES)

3.65 ±0.10
2.65 ±0.10

(UFD28) QFN 0816 REV C

0.200 REF 0.25 ±0.05

0.00 – 0.05 0.50 BSC
BOTTOM VIEW—EXPOSED PAD

NOTE:
1. DRAWING PROPOSED TO BE MADE A JEDEC PACKAGE OUTLINE MO-220 VARIATION (WGHD-3).
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE

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28 For more information www.linear.com/LT8390A

 LT8390A
REVISION HISTORY
REV DATE DESCRIPTION PAGE NUMBER
A 09/17 Added H-Grade Temperature Option 2, 5
Clarified Block Diagram 11
Clarified Sense Resistors descriptiion in Route LSP and LSN traces bullet 25

8390afa

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.

However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
For more
tion that the interconnection information
of its circuits www.linear.com/LT8390A
as described herein will not infringe on existing patent rights. 29
LT8390A
TYPICAL APPLICATION
25W (5V 5A) 2MHz Buck-Boost Voltage Regulator
R1 L1 R2
VIN M1 5mΩ 0.33µH M4 10mΩ VOUT
4.5V TO 20V 5V
CONTINUOUS 47µF 5A
4V TO 56V 22µF 0.1µF SW1 LSP LSN SW2 0.1µF 0.1µF
0.1µF 10V 47µF
TRANSIENT 63V 100V BST1 BST2 10V ×2 10V
×2 ×2
D1 D2
4.7µF
100V INTVCC INTVCC
×2 M2 BG1 BG2 M3
GND
TG1 TG2
VIN LT8390A VOUT

383k 1µF 1µF

10Ω
EN/UVLO ISP
1µF 10Ω
LOADTG ISN 40.2k
169k
TEST FB
SSFM OFF
ISMON ISMON SYNC/SPRD 10k
INTVCC
CTRL INTVCC SSFM ON

105k 95.3k LOADEN 4.7µF 100k

L1: COILCRAFT XEL4020-331ME 0.33µH
VREF PGOOD PGOOD M1, M2: INFINEON BSZ034N04LS
SS VC RT M3, M4: INFINEON BSZ033NE2LS5
0.47µF
D1, D2: NXP BAT46WJ
59k R1: SUSUMU KRL3216D-M-R005-F-T5
22nF 11k
2MHz
2.2nF

RELATED PARTS
PART NUMBER DESCRIPTION COMMENTS
LT8390 60V Synchronous 4-Switch Buck-Boost Controller VIN: 4V to 60V, VOUT: 0V to 60V, ±1.5% Voltage Accuracy, ±3% Current
with Spread Spectrum Accuracy, TSSOP-28 and 4mm × 5mm QFN-28
LT8391 60V Synchronous 4-Switch Buck-Boost LED VIN: 4V to 60V, VOUT: 0V to 60V, ±1.5% Voltage Accuracy, ±3% Current
Controller with Spread Spectrum Accuracy, TSSOP-28 and 4mm × 5mm QFN-28
LT8391A 60V Synchronous 2MHz 4-Switch Buck-Boost LED VIN: 4V to 60V, VOUT: 0V to 60V, ±1.5% Voltage Accuracy, ±3% Current
Controller with Spread Spectrum Accuracy, TSSOP-28 and 4mm × 5mm QFN-28
LT3790 60V Synchronous 4-Switch Buck-Boost Controller VIN: 4.7V to 60V, VOUT: 1.2V to 60V, Regulates VOUT, IOUT, IIN, TSSOP-38
LT8705 80V VIN and VOUT Synchronous 4-Switch Buck-Boost VIN: 2.8V to 80V, VOUT: 1.3V to 80V, Regulates VOUT, IOUT, VIN, IIN,
DC/DC Controller 5mm × 7mm QFN-38 and Modified TSSOP-38 for High Voltage
LTC®3789 High Efficiency Synchronous 4-Switch Buck-Boost VIN: 4V to 38V, VOUT: 0.8V to 38V, Regulates VOUT, IOUT or IIN, 5mm × 5mm
Controller QFN-32 and SSOP-24
LTC3780 High Efficiency Synchronous 4-Switch Buck-Boost VIN: 4V to 36V, VOUT: 0.8V to 30V, Regulates VOUT, 4mm × 5mm QFN-28 and
Controller SSOP-28
LT3763 60V High Current Step-Down LED Driver Controller VIN: 6V to 60V, 4mm × 4mm QFN-20 and TSSOP-20
LT3757/LT3757A Boost, Flyback, SEPIC and Inverting Controller VIN: 2.9V to 40V, Positive or Negative VOUT, 3mm × 3mm DFN-10, MSOP-10
LT3758 High Input Voltage, Boost, Flyback, SEPIC and VIN: 5.5V to 100V, Positive or Negative VOUT, 3mm × 3mm DFN-10, MSOP-10
Inverting Controller
LT8710 Synchronous SEPIC/Inverting/Boost Controller with VIN: 4.5V to 80V, Rail-to-Rail Output Current Monitor and Control, TSSOP-28
Output Current Control

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LT 0917 REV A • PRINTED IN USA
www.linear.com/LT8390A
For more information www.linear.com/LT8390A  LINEAR TECHNOLOGY CORPORATION 2017