B.V.

Raju Institute of Technology

(Autonomous)
Vishnupur, Narsapur, Medak (District) – 502313
Department of Electronics and Communication Engineering
Lesson Plan
L T P C
Course Code: A33D1 Digital Logic Design 4 1 - 4
Pre-requisites: Mathematical Foundation
Name of the Faculty U.Gnaneshwara chary
Designation Assistant Professor
Department ECE
Academic year 2019-20 Class: II B.Tech I Sem Section: C

The purpose of learning this course is to

Learning 1. Classify number systems based on radix.
Rationale 2. Design of digital circuits and fundamental concepts used in the design of digital systems
3. Design of sequential circuits using flip-flops.
4. Analyze sequential systems in terms of state machines.
Learning
Outcomes At the end of this course, learners will be able to:

Po1 Po2 Po3 Po4 Po5 Po6 Po7 Po8 Po9 Po10 Po11 Po12 Pso1 Pso2
Understand different number systems, 3 2 1
codes and conversions
Understand and optimize Boolean 2 3
functions using K-Maps
Design combinational logic circuits 2 3 1 2
Understand basic building blocks of 2 3 1 1
Sequential Logic circuits
Design & Analyze Sequential Logic 1 3 1
circuits
Design Digital Systems using 1 3 2
Programmable logic Devices and
understand Logic Families
1.4 2
Attainment Target 1.8 3 1

Learning Content & Plan

No. of Teaching Text

Unit Title Name of the Topic Date
Periods aids book
Unit- I
Introduction to Number systems
2 17-06-19 LCD/BB T1
Number Systems Base Conversion Methods Complements 2
18-06-19 LCD/BB T1
of numbers

1 21-06-19 LCD/BB T1
Complements of Numbers
Learning Content & Plan

No. of Teaching Text

Unit Title Name of the Topic Date
Periods aids book
Signed Numbers-Signed 2 LCD/BB T1
24-06-19
Magnitude
1‟s Complement and 2‟s complement 2 LCD/BB T1
25-06-19
representation
Signed and unsigned addition 1 26-06-19 LCD/BB T1
/subtraction, Binary Codes-Binary Coded
Decimal
1 27-06-19 LCD/BB T1
Exess-3 code, Gray code and Error
Detection Codes- Parity code

Hamming code and problems 2 01-07-19 LCD/BB T1

Signed Numbers-Signed 2 LCD/BB T1
02-07-19
Magnitude
1 Test/ Interactive
Unit Assessment 05-07-19 Session

Unit- II
Basic Theorems and Postulates, 2 08-07-19 LCD/BB T1
Digital Logic Gates, Universal Gates, 2 09-07-19 LCD/BB T1
Algebraic Simplification of Digital Logic 1 LCD/BB T1
Gates using Theorems and Postulates, 10-07-19

Multilevel NAND/NOR realizations 1 LCD/BB T1

12-07-19
Canonical and Standard Forms. 2 15-07-19 LCD/BB T1
The Karnaugh Map Method, Five Variable 1 17-07-19 LCD/BB T1
Boolean Maps
Algebra Prime and Essential Implications 2 LCD/BB T1
22-07-19

Don‟t Care Map Entries, Partially 2 LCD/BB T1

23-07-19
Specified Expressions
1 Test/ Interactive
Unit Assessment 26-07-19
Session

Unit- III
Arithmetic Circuits-Half adder, Full adder, 2 30-07-19 LCD/BB T1
Half subtractor, Full Subtractor 1 31-07-19 LCD/BB T1
4-bit parallel adder/subtractor, 1 LCD/BB T1
01-08-19

BCD Adder, 1 LCD/BB T1

02-08-19
2-bit comparator, 4:1 Multiplexers, 2 05-08-19 LCD/BB T1
Implement Boolean functions using
Multiplexers,
Decoders, Implement Boolean functions 2 06-08-19 LCD/BB T1
Combinational using Decoder,
Design BCD to Seven Segment Decoder, Encoder- 1 LCD/BB T1
2 to 4 Encoder, Priority Encoder, 07-08-19

Code Converters-Binary to Gray, Gray to 1 LCD/BB T1

08-08-19
Binary, Binary to BCD , BCD to Binary,
Barrel shifter and ALU 1 LCD/BB T1
09-08-19
 1 Test/ Interactive
Unit Assessment 09-08-19
Session

Unit- IV
Basic Architectural Distinctions between 1 22-08-19 LCD/BB T1
Combinational and Sequential circuits,
The basic Latch-NAND latch & NOR latch, Clocked
1 Latches-SR, D, JK and LCD/BB
23-08-19 Flip Flops-Master-Slave
T1

Clocked Latches-SR, D, JK and Flip Flops- 1 LCD/BB T1

Master-Slave F/F 26-08-19

Sequential Edge triggered F/Fs,Flip-Flop- Excitation 1 LCD/BB T1

29-08-19
Circuits Tables

Conversion from one type of Flip-Flop to 1 30-08-19 LCD/BB T1

another
2 Test/ Interactive
Unit Assessment 03-09-19
Session
Unit- V
Overview of Synchronous and 1 04-09-19 LCD/BB T1
Asynchronous Sequential Circuits
Finite State Machines –Mealy Machine 1 05-09-19 LCD/BB T1
and Moore Machine
State Diagram, State Minimization and 1 LCD/BB T1
Assignments 06-09-19

Design and Design Procedure and Realization using 1 LCD/BB T1

09-09-19
Analysis of Flip-Flops
Sequential Circuit

Analysis of Synchronous Finite State 1 11-09-19 LCD/BB T1

Machines
Design of Asynchronous Counter-Ripple 1 12-09-19 LCD/BB T1
Up/Down Counter and Mod-N Counters
Design of Synchronous counters 1 LCD/BB T1
13-09-19

Binary and BCD Up/Down counters 1 LCD/BB T1

14-09-19
and Mod-N Counters
Shift Registers-SISO, SIPO, PISO, PIPO 2 LCD/BB T1
17-09-19

Bidirectional and Universal Shift Register 1 18-09-19 LCD/BB T1

Shift Register based Counters-Ring and 1 LCD/BB T1
Johnson (Twisted Ring) Counter 19-09-19

1 Test/ Interactive
Unit Assessment 20-09-19
Session
Unit- VI
Algorithmic State Machines-Components 2 24-09-19 LCD/BB T1
of ASM Charts,
Salient features of the ASM chart

Design Examples using ASM Charts- 1 30-09-19 LCD/BB T1

Sequence Detector, Serial Adder
Algorithmic State Logic Families-RTL, DTL, TTL, ECL & 2 LCD/BB T1
Machines (ASM), CMOS logic Families and their 01-10-19
Logic Families specifications
&Programmable
Logic Devices
 (PLD)

Programmable Array Logic (PAL), 1 LCD/BB T1

04-10-19
Programmable Logic Array (PLA)

Combinational Circuit Implementation 1 14-10-19 LCD/BB T1

Using PAL and PLA.
1 Test/ Interactive
Unit Assessment 16-10-19
Session

Learning Resources

Unit 1 Unit 2 Unit 3 Unit 4 Unit 5

1 Switching Theory and Logic Design- A. Anand Kumar, PHI, 5th ✓ ✓ ✓ ✓ ✓

Edition.

2 Digital Design- Morris Mano, PHI, 3rd Edition. ✓ ✓ ✓ ✓ ✓

Learning Assessment Method

Unit 1 Unit 2 Unit 3 Unit 4 Unit 5 Continuous External Total

Assessment Evaluation

Theory 5% 5% 5% 5% 5% 25% 25% 100%

Practice 5% 5% 5% 5% 5% 25% 25%

Head of Department Signature of Faculty