Chapter 4

Operational Transconductor Amplifier (OT A)-based

Field Programmable Analog Array (FPAA)

4.1 Introduction

Analog circuit dc:>ign has a number of usual chullenges such as linearity, noise

performance and bundwidth specifications. Apart from these inherent challenges, the

FPAAs huvc two additional obstacles, which arc the configurable interconnection and the

versatility of analog function blocks at diITcrent granularity levels. The interconnection

:ihould be dcsigncu wi ll1uut affecting the accuracy of the instantiated circuit, while the

analog function blocks should provide a good vark:ty of useful programmable functions.

4.2 Operational Transconductance Amplifiers (OTA)

OTA is basically an Op-Amp without an output butler, which can only drive

capacitive loads [3 1]. An OTA can be define<l as an amplifier where all nodes are low

impedance except the input and output nodes. OT A is the voltage controlled current

source device whereas the Op-Amp is the voltage controlled voltage source device. Like

Op-Amp, OTA is used as a building block for many analog applications including

continuous high frequency filters and analog multipliers.

33
 4.2.l Principle of OTA Operation

An OTA is a voltage controlle<l current source; more specifi cally the term
'·opcmtional" com es from the fact that it takes the difference of two voltages as the inpul
for the current conversion f37l.

n u.: ideal transfer characteristic is therefore .

(4. 1)

Or, by taking the pre-computed difference as the input.

l out= gm vid (4.2)

In relation (4.2) constant transconductance ·gm' is the proportional factor

between the ' Vi<!' and '1 0 u 1'. In reality the trnn~condui-rHDce is also B function ufthc input

<liffi.'rential voltage. The symbvl lilr a single-ended OTA is shown in Fig. 4.1

+ +

Figure 4.1.Symbol of OTA and its low-frequency linear model

An ideal OTA has two voltage input.<; ~ ith infinite impedance {i.e. there is no

input cum :nt). The common mode input range rs also infinite. while the differential signul

between these two inputs is used to control an ideal voltage-controlled current source (i.e.

the output current does not depend on the output vollage) that functions as an output. The

proportionality factor between output current and input differential voltage is called

tranc:conductance. Any ruul OTA will have circuitry to process the input voltages with
low input current over a wide common mode input range and provide a current to the

output that is a representation of the input differential voltage and relatively independent

of th1.: output voltage. Since an OTA can be used without feedback, the maximum output

current and with it the transconductance can often be adjusted [23]. OTAs in generally

operate at higher frequencies than Op-Amps because they have low impedance internal

nodes and operate in open loop (37).

4.2.2 Comparison between Op-Amp and OTA

OTA essentially comprises of differential pair an<l current mirrors. The

comparison between OT A and Op-Amp is summarized in Tublc 4.1

T a h l c 4 . t C ornpn rlso n o f O T A & Op-Atnp

OTA Op-Amp

Current source output Voltage source output

(high output impedance) (low output impedance)

lout= Gm* V;d Vout "" A* V,d

Cannot drive resistive loads Essential to drive resistive loads

Can be used in open-loop Should be used in closed-loop

configuration t.:onfiguration
Buffer increases power dissipation,
--- noise.
Changing bias current/voltage
Changing feedback 'R' and ' C' can
externally can achieve tuning in
achieve tuning in filter applications.
fi lter applications.

35
4.2.3 Performance Parameters of OTAs

OTA structures reported in the literature have been proposed to fit specific

applications. Important criteria for evaluation of OTAs include [38].

i) Bandwidth

ii) Linearity

iii) Noise

iv) Power dissipation

v) Tuning range

I) OaodwldCb ( DW)

One of the most important aspects of OTA-C active tilter design is the bandwidth
of the OTA, defined as the frequency range hetwccn DC ond the -JdH point of the OTA

frequency rc~ponse. For filter operation in the video-frequency range up to IOMHz, this

means that OTA must provide bandwidth of al least >I OOMHz.

ii) Linearity

In general. the output signul y(t) of a time-invuriant electrical network can be

expressed in tenns of its input x(t) by a Taylor series expansion

y(t) .. n 1x(t) 1- a 1 x 2 (t) ·t- a , " ' (t) + .................... .. . (4.3)

where the coefficient a1 represents the desired linear gain of the network and coefficients

a2. a, ..... represent the distortion. In practice, the output signal y(t) of a transistor-l~vel

OTA will be distorted and its maximum signal level will be dictated by the non-linear

effect of practical amplifier saturation characteristics. There are dillenmt measures of

nonlineority. For example if a sine wave is applied to the input of rm OTA, then the root-

36
mean-square (rms) value of the ratio of all harmonics 'a;' (1 <i) to the I si harmonic •a 1•

will be a measure of nolinearity known as 'Total Hannonic Distortion (THO). w h ich is

usually expressed in dB '. While at low frequencies the coefficients 'a,· can be assumed

constant, at video freq uencies the reactive components in the circuit introduce frcquency-

depcndence into the coefficients 'a1' of equation (4.3). Hence. the calculation of hannonic

distortion involves solving a set of non-linear equations separately for every harmonic

'a;'. Of course in software simulation, it is not possible to include all hurmonics into this

solution. For the implementation of high-performance filters, it is necessary that the

active devices exhibit low THD, typically <-50dB.

iii) Noise
The noise in electronic circuits may be either nn unwanted signnl, tending to

interfere with a required signal (interforence) or a random fluctuation in voltage or

current originating from random motion of charge carriers (intrinsic noise). In the first

case, the noise source is external to the circuit under consideration, while in the second

case; the noise is generated within the circuit elements. In IC design, external interference

can be sufficiently suppressed by shielding either on the circuil board or on the die

packaging level. Intrinsic noise is a sib'llal with random amplitude versus time and is

generated by all active and passive circuit devices. Its average value over a certain period

of time is zero and lherefore the noise vollage VN squared to v 2n and averaged over that

time period measurt!s its power. In the frequency domain, it is commonly accepted to take

an elementary small frequency band df and denote the noise power in this band by dv 2 N

wruch allows more accurntc calc ula tion of noise figures [39).

37
iv) Power Dissiplltion (PD)

One of the motivarions for integrating analogue filters is their prospective use in

portable system applications where low power dissipation is a major design

consideration. PD is defined as the product of supply voltage difference (VDD • VSS )

and total current flowing through the supply terminals.

v) Tuning Range (TR)

In almost every OTA reported in the literature, tht: transconductance gain •Gm• is

proponional to an external DC bias voltage or current. The ability to tune the 'Gm' of the

OTA is one of the main advantages of 0 rA-C filter design, since it enables external

control of filter parameter<; including (l)o nnd Q. A wide tuning range is advantageous in

uctive integrated filter design, especially for tuning the cut-off frequency of the OTA-C

filter. The tuning range wi ll be expressed in tenns of the minimum mid maximum ·om·

value, which can be achieved within the possible bias voltage or current range. 111e

typical range of 'Gm' values for filters operating ttt vidco-frtlqucncies is I O_S to I mS.

4.3 OTA as a Configurable Analog Block (CAB)

Design of Lhe CAB, the basic cell used in FPAAs, is usually influenced by a

number of factors, including the functionality and performance features of circuits to be

prototyped, the area-efficiency of routing resources dictated by the CAB design itself and

the supporting semiconductor process technology.

Since high bandwidth is always desirable in analog signal proct:ssing circuit,

programmable analog circuits are no exceptions. To date, many of the published FPAA

38
designs have limited their operating bandwidth under IMHz. However. lhis bandwidlh is

insufficient for video applications, which normally require up to 1OMHz or mon:. In

order to increase bandwidths of PPAA, new architectures need LO be developed to avoid

the bandwidth limitation by the frequency response of conventional Op-Amp based

design. Also inherent programming and tuning capability of OTAs make them a proper

choice for programmable analog design. From recent researches, OTA is proposed to

replace the use of Op-Amp in configurable analog building blocks [23).

A key issue in FPAA design is the level of granularity. l"'inc grain FPAA

ai·c11iLc(;LL1res (con!Igurable al Lhe transistor level) will require more routing resources and

switches in the signal path than a coarser grain FPAA architecture (configurable at a

macro-block level, e.g. integrators and S/H). However. the coarser architecture will he

less versatile, i.e. it will be able to implement a nnrrower range of circuits than the fine

architecture. Another issue is whether to make the CABs distinct for different circuit

functions, or identical, but programmable to implement different functions. This choice

will influence the area of the CABs and routing of circuits within the FPAA. CAB design

can thus he seen to strongly influence the fPAA ureu, the routing rt:4uirements, and the

variety of circuits that can be prototyped and the performance of circuits implemented on

the PPM. These issues were explored in A detailed study of CAB do:iign, bMcd on Cl set
ol' upplicn1iv11 circuilS !or analog i:igrrnl processing. ln chapter 1, Tuble 1. I :shows the

summary ofFPAA grllllularity: 1he granularity ofthc computational logic used in FPAA

impacts the size, performance, flexibility, and functionality of the device ( 15].

The analog functions will be grouped into CAO's and the interconnection network

will cv1mt:1.:l chem wgether. Une important observation is that different functions can be

39
conveniently obtained by configurins the circuit primitives with !l few trnnsi:ito1:1 lhdt dl:I

as nnalog switchc:;. Though various l>pecialized types of CABs could be defined,

controlling the level of granularity of the CAB is critical to minimizing the number of 1/0

lines that ultimately must be accommodated by the interconnection network.

The CAB:i on 11.n FPAA may be homogeneous oi- hetcrogc::neous. For example, an

FPAA could contain specialized CABs which realize only a few different functions, or

the FPAA could contain CABs which are homogeneous but cun be configured as many

different functions. Also, CABs may be reali2et1 s:11 diffoNnt fun1,,tiumillcY 1evPIC!,

including transi):tor, sub-circuit, builuing blocf.... macro block and sub-system levels.
In the presented research it was aimed to huvc a versntile CAR with ns:1ocialcd

switches us a building block of FPAA. Accordingly we chose the CAO design und its

intcrco1utcctions, shown in fig. 4.2 as a starting architecture f 14). A loc:il shift register

determines the configurntion of the CAB. Each bit of the shift register controls vorious

switches within the CAB itself.

The starting architecture of CAB consists one programmable fully difl'crcmial

OT A, one programmable capacitor and a set of switches. The switches are placed in such

a way that OTA can be connected with or without the capacitor. It is also pos:;ible !O pass

lhc signals of other CABs through the switches situntc<l at the top and the bollom of the

('AB. Switches are able to connect the input to the OTA directly or connect tJ1e OT A

output to the next CAD.

40
 ;
. ~
- · ...
-·-- -::-
s.. . . ,,. l .' : 0

I;
I
.,
,·..:..s,

OT·I

c·---
. -- .
.., --·
Figure 4.2 S tructure of CAB

4.4 Project Obj~ctlv~s

The proposed design of the whole FPAA has been done in 0.35um CMOS process

in this thesis. Reference works have used 2um CMOS process but one of our goals in this

research has been to first scale that design (not as per digital scaling rules) und second

optimize it for low power consumption and high linearity.

The aim of presented work in this thesis is to design and op1imi1e an OT A-based

FPAA for implementing a set of commonly uc:ed analog signul processing fu nctions

including adjustable transconductors, programmable continuous time filtering and analog

multiplication. While des igning an FPAA using OTA design specifications including

tuning range, progrumming versatility and efficiency in the sense or power, area and a set

uf pruc.:cical specltications are consideroo. The most importnnt !O:pccifications include

transconductance and operating frequency ranse. power dissipation. input voltage

dynamic rnngc, linearity, area and common-mode voltage range.

41
4.5 Basic Principle a11d Architecture of the OTA as a CAB

4.5.1 OTA Architect11re Selection

From the survey it was found that widely tunable OTA with cross-coupled

architecture offers more l· nearity than other architectures. On the other hand since wide

tuning range was a coricem for us the cross-coupled architecture was chosen.

Transconductance is moslly affected by linearity at the input stage and hence a linear

input stage is desired. In <:ddition to tuning the input stage the transconductance can be

programmed using prograr unable output current mirrors to achieve a wide tuning range.

The simplified scl1ematic diagram of the OTA based on two cross-coupled

differential MOS pairs and programmable current mirrors is shown in Fig. 4.3 [1 4).

~----------~--<>VDD

l Iw~ Ii,;~

l :A ! :A
Current Current.
MinorOl MinorG2

Figure 4.3 Schentatic diagram of the CMOS programmable OTA

4.5.2 Cross-Coupled A .·chitecture

Schematic of the 0 r A based on two cross-coupled differential MOS pairs is

shown in Fig.4.4. Two crms-coupled differential pairs with MOS devices Ml- M4 are

operating in saturation. A DC current Iss in combination with an adjustable floating

42
rnlrage source Vb, with low output resistance, b1a.<:es both pairs. Vb is connected between
the common-source nodes C and 0. Thus. thi~ topology of the transconductors circuit

c.loes not introduce additional internal nodes, rc~ulting in improved high-frequency

performance.
Relations (4.4) and (4.5) c xprei;s c urrent lout11 and Iout12 using the Standard
:;quare-law model for MOS devices.
2 2
l 1n1 - K (Vp - Y Tp) + K(Vo - V b - V rp) (4.4)

linJ = K (V Q - VTv )2 + K(V" - Vb- Vrp)J (4.5)

In relations (4.4) and (4.5) 'K= 0.5µ C0 xWIL' is the tramconductance parrunctcr

of transistors Ml M4, having the same W/L ratios. V-rP is the thrc<;hold voltage of PMO:S

transistors, Vb is the voltcgc of Lhe noaring UC source, and Vrand v 0 iu-e the gate-source

volta~cs of transistors M I and M2, respectively.

The overall transconductance gm of the OTA circuit is obtained and is given by

relation (4.6). To increase programmability of the OTA current mirror s ta5c5 can be

added to the outp ut of ll1c OTA as shOwn in .Fig. d.1 Thercforo u ver.sutilc control range

can be obtained by adjusting using two methods: one method is co nme the flo:iting bins

voltage by an analog voltage and the other is to make the gain of the output current

mirrors prosrrunmuble in a digital way. The l:ittcr m ethod lends to relation (4.0) for Ille

tran~conduclance of the adjustable and progrwnm<1ble u·1A.

!/.., = ~v:: = J( \1(iA.

(4.6)

43
 Vln1 ~
C VOD•3.3 t
------.--4-~~ M3 M4 g,_I-..,..__,__v_in2 •
_/ M2

Figure 4.4 Cross-coupled architecture of OT A

4.5.3 Prelimin~ry Design and Slmulntion of Cross-Coupled OTA in

0.35µrn CMOS Process

4.5.3.1 Preliminary Design of Core Architecture

A preliminary dosign wu:s done tor the simple Cross-Coupled architecture in Fig.

4.4 using 0.35µm CMOS technology available from TSMC. The design considered from

reference paper is of 2µM technology. The design was convened into 0.35µM technology

using following equation::> (4.7). For i;:c11Jing the tc1,;hnulugy from 2µM to 0.35µM, the

factors such as transconductance, mobility, W/ L ratio, Vb should be con::;idcrcLI.

Gm (µp cox w)
L OJSµm •v. 0 0 lll""
0351un _ _
(4.7)
(1-iocn• Lw ) 2,..m
·~v.52..,.

44
4.S.3.2 Simula tion R~ ul ts of the Preliminary Core Architecture

The simple Cross-Coupled architecture in Fig 4.4 was simulated using Cadence's

Custom IC Design Tools in 0.35um CMOS technology with VTn=0.45V: VTp=-0.6SV;

1-lnCox - I S8uNV
2
and µ pCox = 66.89uA/V2 . The power supply is Yoo = 3.3V, Vss = OV.
The Vb varies from 29mV to 460mV with lss = 19uA.

~ llt•5pvn~~
I!
• V8•"«9m"j
11 11
• : VB•.. ttli.lm": ~ : VB•"364.~m0: "' ' V9•"J18.Jm", +: V8•"?tU' 4m" :
e.eu • : V9• 221J.6rn ; ... : V9-" 172 7m"; a. ; VO•" l2' .8tn"; - · V8 - '?6.60m''; • : V8• .. 29m";

< 1.eu
"
J.eu

2.Gu

.·-
0.11
10Q ~-::;~--~~
1K =-~..._...""'\'111
...... 0W7'0K ~ ...-~~_....,1
0-M
IC
treq ( H1 )

Figure 4.5 T ra nsconductnncc Vs. frequency

AC Respon.. I!
., V8•" 17Jm": . , V8•"125m" , • : V8• "77m" ; 1: V8•"29m": - : \18•"4 8 1m",
~.0u ...: V8="413m": "": VB•"365m..: "': \18•"J 17m'"; • V8• "289m"; • • VB• .. 2llm";

o.eu

7.Gu

O.llu

6 llu
<
4 llu

J .o_,

2.~. r----------------------------~
1\lv

Figure 4.6 Tram1concJuccance Vs. Vid (half)

45
 Table 4.2 shows model paramerers for T8MC 0.35 MIXED-MODE CMOS

process and Fig. 4.5 shows the transconductance of the simulated cross-coupled

nrchirecturc for variation of the frequency from I OOHz to I GHz and Vb is taken as a

parameter. The si mulation result shows that this cross-coupled architecture hus the

bandwidth of 20MJ Iz. The transconducrancc:: varies from 0.45uS co 7. 7uS for change of

Vb from 29mV to 460rnV. Fig. 4.6 s hows thut rhc cross-coupled architecture works
linearly for the range ofV,d from -0.2V to +0.2V.

Table 4.2 Typical modeJ parameters ofTSMC 0.35 MIXED-MODE CMOS process
Parameter raramcter Typical Parameter Vnluc
Symbol Descri£tlon n-channel p - cbn nn c l Units
VTO Threshold 0.4547523 0.6701014 v
uo Mobility 348 3086407 147.3371727 cm·N•.,.
DELTA Narrow- width threshold 0.0 1 0.0 1 -
adjustment factor
TOX Oxide thickness 7.6F.-9 7.6E-9 A
XJ Metallundcal junction depth I r~-7 1r:-1
,..-.~
-
CG SO Overlap capacitance for the 2.7913-10 2.43E-10 F/m
gate-source
CCDO Overlap capacitance for the 2.791-,-10 2.43E- 10 F/m
gate-drain
CGBO Overlap capacitance for the IE-12 IE-12 F/m
-
go.Le-bulk
CJ Zero-bias j unction capacilallCC 9.06398713-4 1.419861 E-3 Pim'
CJSW Zero-bins, bulk-source/drain 3.41 8862E- IO 2.839933E-10 Flrn'
sidewall caQacitance
MJ Bulk-junction gradient 0.350588 0.559054 1 .
cocflicient
MJSW Bulk-source/drain sidewall 0.123 7491 0.40 14951 -
Qrndient co~ffi c i ent
~
Vno Voltage Suooly (+) 3.3 3.3 v
Vss Voltage Suooly (-) 0 0 v
V..In Threshold Voltage 0.45 - v
VTD Threshold Voltage - 0.65 v
J!nCox 158 - uNV·
UD C OX - 66.89 uAN'

46
4.5 .4 C ross-Coupled OTA With Source Degeneration

This i~ ;111111hPr method ado pted for fu1tltc1 imµ1uvlng tl1e llneanty. Here the

linearit.Ution cw1 be increased by using c:ource degeneration concept with the cross-

coupled OTA [40-41). T o explore the effcctivcne:.:; o f the method the OTA with source

degeneration was implemented as shown in Fig. 4.7. Transistor M l-M4 comprises the

cross-coupled differential input pair, biased by the current coming from tl u.: current

source and fl owing through the floating voltage V 11•

The voltage drop across the resistor. added at the source of each transistor, is to be

added to the voltage source Vb to hav~ the accurate result. Large degeneration factors

could result in a significant transconductance loss and excessive power consumption of

transistors Ml-M4. The values of resistance are varied and their effects on THD (Total

Hormonic Distorsion) are observed as given in Fig. 4.8.

M5 M6
10u
~ ~

lfigure 4. 7 Cro:s:s-couple<I with source d egeneration

47
 A~ Fig. 4.R shows that the source degeneration method improved the linearity of

this cross-coupled architecture maximum by 2dB only. llcnce the cross-coupled

architecture without source degeneration is considered in this thesis.

- - -22mV
70 2 , - - •]lJmV
/ :109mV
7U ••./ • -l!OOmV
.:'

:'
. . . .. . . . •1
... ..... _.,/
r _ _ ___ ..,,..,,. ,-,,.. ,/
/
/
'
,/ /

lill 40 ~06_ _ .,,.0._1--..,0 ~-5--Oi....2- -11..._J&_ _O_.,J,....-- .,,.O~~.---:".'114--0 4~

Otg1u11,.uan ,. tc101

Figure 4.8 E ffect of sou rce clcgencrntlon on T l I 0

4.6 Rou ting Eleme nts

4.6.1 A nulog R o uting

Digi tal circuits arc chorocteri)'cd by 0 11 intrinsic robustness lo p11rnsl1ic e ffects.

With unaloa ci rcui ts. effocl:l of :1lrny rcsistarn.:cs 011<.l cupoci1m1ccs cannot be cumul nted us

in digital systems. bu1 needs lo be.: cons idered on u nc:t-by-net basis. Analog routing

thc:rclbrc is far more formidublc thun digitnl routing.

Th1: early nnnlos ruuters weai.: bused on a net clussilicmion scheme. Weight-driven

routers minimize tt cost function given by a weighted sum of items proportional to

48
parusitics, wire length, and number of bends and vi as. l n constraint-driven routers,

parasitics nrc eliminated from the cost function. lnstcud. parusitics in the candidate path

are then checked ugainst their bounds. and if the bound is violotcd. furtht:r expunsion

along thol pnlh is terminated. r42)

Routing is responsible for the introduction of purasitics in the.: interconnections.

which can have ll significant impuct on the electrical behavior of the circuit. For u given
nt:t. i111crconncc1 pBrHsitics l11clude struy resistances, strny capacitnnccq o f wires lo the
substrate, and the cross-coupling cnpocitanccs hetw.,en nets (p1trallcl nets nnd crossing
nc::ts). In addition. switcht!s in the progrnmmuble urchitccrurc imroduc.:c significunt sc::rics
n:sist11ncc und pacasillc cupacitancc. T hese factors constrain the routing to reduce wire
lengths, the number of parallel und crossing wires between different 11e:ts, und also tJ)e

number or switche:i used. It is thw, evident tht11 a good F l'AA router must keep the
perfornmnce dcgnodotion mininwl (4Jl

4.6.2 Switches in Inte rconnectio n Netwo rk

When u connection between the output of block t\. and the input of block B is

made via the interconnection network, the corresponding wire segments and routing

switches are activated by loading the configuration bits from the on-chip shift register.

'ntese routing switches are usually made use of NMOS pass transistors or CMOS

transmission gates, and they will have parasitic non-linear resistance and cupacitance,

which will consequently affect the linearity and the frequency response or the desired

analog circuit implemented. r13).

49
 As a counterpart of the SC discrete-time approach, the transconductor approach i:,

a continuous-time approach thal can be used as a programmable linear resistor, o signul

controlled resistor, signal multiplier or a Polarity change swit..:h. uecnusc of the

continuous-time nature, a higher bandwidth is achievable by this technique. Fig. 4.9

shows a MOS transconductor. This transconductor is classified as a triode transconductor

because the transistors are operated in triode mode. Th1; transconductance in the ON

stat1:, Gon, is as the following,

Gon = (i I - i2) I (vi - v2) == ~t Cox (W/L)(Vgl - Vg2) (4.8)

Where the V gl & V g2 are the control voltages and v 1, v2 ~ min (V g I - VT, v g2 - VTJ

From above equation, the Gon is direct ly proportional to (Vg l - Vg2), and the polarity of

the differential current (ii - i2) is detennined by the sign of (Vgl - Vg2). Also, the

transconductor acts as a linear multiplier as the Gon varies linearly with the control
voltage difference (Vg l - Vg2). With all the properties depicted from above equation, the

transconductor not only acts as a switch for routing the interconnection network, but also

>tC I ns a polarity chang1; Switch, a linear Variable TCSiStOf and a n1Ulliplier.

Vg1
-I:::-- 11
V1 c--.

"-i ~------!
~
.
V2 ,---1'
12 -
Vg'l

Figure 4.9 MOS transconductor

50
 This allows the transconductor to be used as an element in the programmed

analog circuit instead of merely hcing a routing interconnection switch. fig. 4. 1O

illustrates how lhe MOS transconductor connects as a routing swilch L44].

Vgl Vg2

V1 V2 I
I 1

-12

11

Figure 4. lO C onnection of trunscooducto r for r o uting

The transconductor switch can be used as a circuit component in the f'PAA. Wilh

this technique, sub-circuit level CABs may~ used because linear resistances are always

necessary for implementing analog circuits. Sub-circuit level CABs include simple

transistor level circuits that perform only one specific function such us current mirror,

output stage, and differential stage. The disadvantage of th1.: transconductor technique is

the allowable voltage range being limited b) the transconductor linearity, since the

linearity is sensitive to the process and temperature variations.

Since high bandwidth is always desirable in analog signal processing circuit,

progrdl11mable analog circuits are no exceptions. To date, many of the published FPAA

designs have limited their operotmg bandwidth under l MHz. Ho\\>ever, this bandwidth is
insuflicient for video applications. which normally require up to IOMHz or more. In

51
order to increas~ bandwidths of FPAA. new architectures need to be developed lo avoid

the bandwidth limitation by the frequency response of conventional Op-Amp bused

dec:ign. From reco.!nt 1escarchcs, operational transconductance amplifier is proposed to

replace the use of Op-Amp in configurable analog building blocks.

4.6.3 Four-Transistor Transcooductor as a Switch

As the design of the target FPAA deals with di fferential configuration. four-

transistor MOS transconductor is most suitable. The transconductor element comprises

four identical MOS transistors operating in the linear (triode) region. MOS nonlinearities

are cancelled when one subtracts the two-transconductor output currents. The re:>ulting

lrnnsconductunec is independent of the thrc:>hold voltage and can he \'aried over a wide

range without affecting the input signal handling capability. It also minimizes the cffcctS

of threshold voltage mismatch nnd substJat1: noise.

4.6.3.l Preliminary Design and Simulation Results of Four-Transistor

Transcond uctor

The four-transistor transconductor architecture in Fig. 4 .1 1 was designed and

simulated using Cadence's Custom IC Design rools in 0.35um CMOS technology. The

gate widths are WI -- W2 - W3 "" W4 = IOOum and the gate lengths are Ll "" L2 =L3 =

L4 =0.4um. The designed switch offers a resistance of 8. 7 ohms to 65.8 olu11s for Vgs I
& vgs2 = o to 2v respectively. The Typical Resistance is 18.94 ohms at Vgsl = Vgs2 =

l .65 V. The TI ID of this switch is - 51 .5 dB.

52
 Vgs1 Vgs 2

ot o2

Figure. 4.11 Schematic of four-transistor transconductor

4.6.4 Programmable Components

Various methods have been used to implement programmable resistors (Fig.4 .12).

These include the use of poly-silicon resistors switched into circuits with pass transistors,

complementary MOS transistor pairs with controlled gate voltages and more complex

transistor implementations of programmable resistive elements such as MOS

transconductors.

Programmable capacitor arrays (PCA) (Fig. 4.13) havc been widely used,

especially in switched-capacitor circuits, in which tht:y can be made to emulate

programmable resistors. The literature contains several publications and products in the

areas of programmable amplifiers and filters. On-chip tuning circuits may he required to

produce bias voltages or current:; that seL the value of programmable components. These

circuits often involve the use of digital registers to store component values, and digital to

analog conversion to produce the bias voltage or current. A major constraint of analog

53
VLSI design in a digital process is the requirement for linear capacitors. Field-

programmability adds the constraint that fabricated capacitors must have a large

capacitance per unit area, so that a sufficient number of programmable capacitor arrays

(PCAs) will fit on a single chip of area comparable to standard FPGAs. Capacitors add in

parallel, so a PCA, each of which must have a capacitance significantly larger than the

parasitic capacitances associated with the substrate and interconnect. This accounts for

the fact that PCAs occupy the largest amo unt of area on an FPAA [ 45].

2><

Figure 4.12 Progrnmmablc resistor array

Figure 4.13 Programmable capacitor array

54
 In

M2

l-400.0n----1 l-4011!.0n
w=25u w=25u

Cl!I c10-c 11 - r.w -·~22- C31!1-CJJ- C40-C44-

r-~ l <-•~N•
c - 45,t;l. 001 c-4!5c»'.0'1f r. - <t50.'90f

I I l
tt
Figure 4.14 Programmable capacitor array (CMOS)

Programmable Capacitor Array, shown in Pig.4.14, was simulated and the results

are shown in Table 4.3.

Table 4.3 Parameters of programmable capacitor array

Parameter Value
No. of bits 5

Minimum Capacitance 0.45p F

Maximum Capacitance 6.75p F
Resolutio n 0.45p F

Occupied Area 46.7u M x 75u M

4.6.5 Configuration Memory

Nonnally two types of configuration memory are used in a programmable analog

integrated circuit. Shift registers are widely used to store the states of connection switches

as well as the values of components such as programmable capacitor arrays [26). The

Analog memory is used to store circuit parameters such as multiplication coetlicients or

the gate voltages of a MOS transistor in a circuit implementing a programma ble resistor.

55
Storing a voltage on a capacitor is the most common implementation of anaJog memory,

and requires a means for refreshing the stored voltage [46-47] as well as consideration of

cnor:s due to charge injection from access transistors [48]. Multivalued memory is used

as analog memory, which allowed the storage of discrete voltages on capacitor. Error

con-ection of the analog memory contents has been demonstrated by E. Lee and

P.G.Gulak l49,50], Organization of the digital memory has been done in diffcn:nt ways
/
like seriaJly, in which all memory ct:lls are connected together as a single shift register ,

serial-parallel whert: a serial bit-stream is loaded into a horizontal shift register, the

contents of which are then strobed into a row of configuration memory indexed by the

bits in a vertical shifl register, und finally random access. where address lines determine

where the input configuration data goes. The latter two approaches can be used to

reconfigure parts of the IC while other parts continue to operate. It should be noted that

configuration memory could occupy a significant proportion of the total die area of an

FPAA integrated circuit. Field-programmable analog circuits to date have required

configuration bit-streams ranging from several hundred to a few thousand bits to

instantiate the circuits being prototyped on them [26].

56