Distributed by:

www.Jameco.com ✦ 1-800-831-4242
The content and copyrights of the attached
material are the property of its owner.

Jameco Part Number 53073INTEL

■

mu @
MCS@51
8-BIT CONTROL-ORIENTED MICROCONTROLLERS
Commercial/Express

8031AH18051AH18051AHP
8032N+18052N-I
8751W8751H-8
8751BW8752BI-I
■ High Performance HMOS Process ■ Boolean Processor
■ Internal Timers/Event Counters ■ Bit-Addressable RAM
■ 2-Level interrupt Priority Structure ■ Programmable Full Duplex Serial
■ 32 1/0 Lines (Four 8-Bit Ports)
Channel
■ 111 Instructions (64 Single-Cycle)
■ 64K External Program Memory Space
64K External Data Memory Space
■ Security Feature Protects EPROM Parts ■
Against Software Piracy ■ Extended Temperature Range
(–40”C to +85”C)

The MCS@51 controllers are optimized for control applications. Byte-processing and numerical operations on
small data structures are facilitated by a variety of fast addressing modes for accessing the internal RAM. The
instruction set provides a convenient menu of 8-bit arithmetic instructions, including multiply and divide instruc-
tions. Extensive on-chip support is provided for one-bit variables as a separate data type, allowing direct bit
manipulation and testing in control and logic systems that require Boolean processing.

The 8751H is an EPROM version of the 8051AH. It has 4 Kbytes of electrically programmable ROM which can
be erased with ultraviolet light. His fully compatible with the 8051AH but incorporates one additional feature: a
Program Memory Security bit that can be used to protect the EPROM against unauthorized readout. The
8751 H-8 is identical to the 8751 H but only operates up to 8 MHz.

The 8051AHP is identical to the 8051AH with the exception of the Protection Feature. To incorporate this
Protection Feature, program verification has been disabled and external memory accesses have been limited
to 4K.

The 8052AH is an enhanced version of the 8051AH. It is backwards compatible with the 8051AH and is
fabricated with HMOS II technology. The 8052AH enhancements are listed in the table below. Also refer to this
table for the ROM, ROMless and-EPROM versions of each product.

Intsrnal Memory Timera/

Device Interrupts
Program Data Event Counters

8031AH none 128 X 8 RAM 2 x 18-Bit 5

8051AH 4K X 8 ROM 128 X 8 RAM 2 x 16-Bit 5
6051AHP 4K X 6 ROM 128 X 8 RAM 2 x 16-Bit 5
8751 H 4K X 8 EPROM 128 X 8 RAM 2 x 16-Bit 5
8751 H-8 4K X 8 EPROM 128 X 6 RAM 2 x 16-Bit 5
6751 BH 4K X 8 EPROM 128 X 8 RAM 2 x 16-Bit 5
8032AH none 256 X 6 RAM 3 x 16-Bit 6
6052AH 8K X 8 ROM 256 X 8 RAM 3 x 16-Bit 6
8752BH 8K X 8 EPROM 256 X 8 RAM 3 x 16-Bit 6

I
Intel Corporationassumes no responsibilityfor the use of any circuit~ other than circuitryembodied in an Intel product.No other circuitpatent
licenses are implied.Informationcontained herein supersedes previouslypublishedspecificationson theaa davices from Intel.
O INTEL CORPORATION, 1994 October 1994 Order Numben 272318-002
MCS” 51 CONTROLLER

MO-M 7 P2.&P2 7

-
I
I

i fl 13 I I II ,, ,
b
JK2U 1==4
~M‘f2#fi+-oN,TMoD,TJ
Acc
STACK
POINTER

+1 L“ L-J
I <>1 I
1 ml ... ,, I, . . .. .
1

7’7
‘% “
I 9
PSEN
ALE TyG g~

E
RST-+ I
P0nT3
‘* II LATCH

h-+ T 119
i-
,,(-1

n --% =2

w x
=
PI O*1 7
———————————

Figure 1. MCSI@51 Controller Block Diagram

5
Pm 3

7
W
LHvI!RS

P] O-P3 7
————— —.. J

272318-1
I

PROCESS INFORMATION
The 8031AH/8051AH and 8032AH/8052AH devic-
es are manufactured on P414.1, an HMOS II pro-
cess. The 8751H/8751 H-8 devices are manufac-
tured on P421.X, an HMOS-E process. The 8751BH
and 8752BH devices are manufactured on P422.
Additional process and reliability information is avail-
able in Intel’s Components Quality and Reliability
Handbook, Order No, 210997.
 MCS@ 51 CONTROLLER

PACKAGES
Part Prefix Package Type ‘ja Ojc

8051AH P 40-Pin Plastic DIP 45°chV 16“C/W

8031AH D 40-Pin CERDIP 4!5”CIW 15“CAIV
8052AH N 44-Pin PLCC 46°C/W 18°CfW
8032AH
6752BH*
8751H D 40-Pin CERDIP 45”CIW 45“CIW
8751 H-8
8051AHP P 40-Pin Plastic DIP 45”CIW 16°CfW
D 40-Pin CERDIP 45°c/w 15“cf w
8751 BH P 40-Pin Plastic DIP 36”CIW 12°cf w
N 44-Pin PLCC 47”C1W 16”Cf W

NOTE:
*8752BHis 36”/10” for D, and 38”/22” for N.

All thermal impedance data is approximate for static air conditions at IW of power dissipation. Values will
change depending on operating conditions and application. See the Intel Pac/raging Handbook (Order Number
240800) for a description of Intel’s thermal impedance test methodology.

~“52’80320NL’ ~
L{
I’__”ll
T2 PI.’ 1 40 Vcc
T2EX P1.1 2 39 P’,’ ADO
P1.2 3 38 PO.1 AD1
P1.3 4 37 PO.2 A02
P1.4 5 36 PO.3 A03
P1.5 6 35 PO.4 AD4
P1,6 7 34 PO.5 AD5 PI.6 ::8:;
P1.7 6 33 P06 AD’ P*,7 .:,.:

‘1
RST 9 3 PO.7A07 RST io;
RU2 P3.O 10 3 EIJvpp” (Rxo) P3.O :ji:
TXD P3.1 11 Z ALEIPROG” neaslvsd**
INTO P3.2 12 29 3%FFI fTXD) P3.1
.1:;
8X5X
:ji;
INT1 P3,3 13 26 3 P2.7 A15 (INTo) P3.2 :!;;
TOP3 4 14 27 2 P2.6A14 (INT1) P3.3 :j:;
11 P3.5 15 26 3 P2.5 A13
fTo) P3.4 :>!:
~ P3.6 16 25 I P2.4 A12
t% P3.7 17 24 1 P2.3 Al 1
XTAL2 16 23 > P2.2 AlO
XTAL1 19 22 3 P2 1 A9

‘ss+!-- 21 X P20 A8

272318-2
DIP PLCC
●EPROM only
“*Do not connect reserved pins.

Figure 2. MCS@51 Controller Connections

3
MCS” 51 CONTROLLER
w

PIN DESCRIPTIONS Port 2 emits the high-order address byte during

fetches from external Program Memory and during
Vcc: Supply voltage. accesses to external Data Memory that use 16-bit
addresses (MOVX @DPTR). In this application it
Vss: Circuit ground. uses strong internal pullups when emitting 1‘s. Dur-
ing accesses to external Data Memory that use 8-bit
Port O:Port O is an 8-bit open drain bidirectional 1/0 addresses (MOVX @Ri),Port 2 emits the contents of
port. As an output port each pin can sink 8 LS TTL the P2 Special Function Register.
inputs.
Port 2 also receives the high-order address bits dur-
Port Opins that have 1‘s written to them float, and in ing programming of the EPROM parts and during
that state can be used as high-impedance inputs. program verification of the ROM and EPROM parts.

Port O is also the multiplexed low-order address and The protection feature of the 8051AHP causes bits
data bus during accesses to external Program and P2.4 through P2.7 to be forced to O,effectively limit-
Data Memory. In this application it uses strong inter- ing external Data and Code space to 4K each during
nal pullups when emitting 1‘s and can source and external accesses.
sink 8 LS TTL inputs.
Port 3: Port 3 is an 8-bit bidirectional l/O port with
Port O also receives the code bytes during program- internal pullups. The Port 3 output buffers can sink/
ming of the EPROM parts, and outputs the code source 4 LS TTL inputs. Port 3 pins that have 1‘s
bytes during program verification of the ROM and written to them are pulled high by the internal pull-
EPROM parts. External pullups are required during UPS,and in that state can be used as inputs. As
program verification. inputs, Port 3 pins that are externally pulled low will
source current (IIL on the data sheet) because of the
Port 1: Port 1 is an 8-bit bidirectional 1/0 port with pullups.
internal pullups, The Port 1 output buffers can sink/
source 4 LS TTL inputs. Port 1 pins that have 1‘s Port 3 also serves the functions of various special
written to them are pulled high by the internal pull- features of the MCS 51 Family, as listed below:
UPS,and in that state can be used as inputs. As
inputs, Port 1 pins that are externally pulled low will Port
source current (IIL on the data sheet) because of the Alternative Function
Pin
internal pullups.
P3,0 RXD (serial input port)
Port 1 also receives the low-order address bytes P3.1 TXD (serial output port)
during programming of the EPROM parts and during P3.2 INTO(external interrupt O)
program verification of the ROM and EPROM parts. P3,3 INT1 (external interrupt 1)
P3.4 TO(Timer Oexternal input)
In the 8032AH, 8052AH and 8752BH, Port 1 pins
P3.5 T1 (Timer 1 external input)
P1.O and P1.1 also serve the T2 and T2EX func-
tions, respectively. P3.6 WR (external data memory write strobe)
P3.7 ~ (external data memory read strobe)

I Port
Pin I Alternative Function
I RST: Reset input. A high on this pin for two machine
cycles while the oscillator is running resets the de-
P1.0 T2 (Timer/Counter 2 External Input) vice,
P1.1 T2EX (Timer/Counter 2
Capture/Reload Trigger) ALE/PROG: Address Latch Enable output pulse for
latching the low byte of the address during accesses
to external memory. This pin is also the program
Port 2: Port 2 is an 8-bit bidirectional l/O port with pulse input (PROG) during programming of the
internal pullups. The Port 2 output buffers can sink/ EPROM parts.
source 4 LS TTL inputs. Porl 2 pins that have 1‘s
written to them are pulled high by the internal pull- In normal operation ALE is emitted at a constant
UPS,and in that state can be used as inputs. As rate of 1/6the oscillator frequency, and may be used
inputs, Port 2 pins that are externally pulled low will for external timing or clocking purposes. Note, how-
source current (IIL on the data sheet) because of the ever, that one ALE pulse is skipped during each ac-
internal pullups. cess to external Data Memory.
 MCS” 51 CONTROLLER
w

PSEN: Program Store Enable is the read strobe to To drive the device from an external clock source,
external Program Memory. XTAL1 should be grounded, while XTAL2 is driven,
as shown in Figure 4. There are no requirements on
When the device is executing code from external the duty cycle of the external clock signal, since the
Program Memory, PSEN is activated twice each ma- input to the internal clocking circuitry is through a
chine cycle, except that two PSEN activations are divide-by-two flip-flop, but minimum and maximum
skipped during each access to external Data Memo- high and low times specified on the data sheet must
ry be observed.

~/Vpp: External Access enable ~ must be

strapped to VSS in order to enable any MCS 51 de- EXTERNAL
vice to fetch code from external Program memory OSCILLATOR XTAL2
locations starting at OOOOHup to FFFFH. ~ must SIGNAL
be strapped to VCCfor internal program execution.

Note, however, that if the Security Bit in the EPROM

devices is programmed, the device will not fetch
code from any location in external Program Memory. XTAL1

This pin also receives the programming supply volt-

age (VPP) during programming of the EPROM parts. Vss

C2 I
272318-4

El
XTAL2
Figure 4. External Drive Configuration

n
EXPRESS Version
XTAL1 The Intel EXPRESS system offers enhancements to
cl
the operational specifications of the MCS 51 family
of microcontrollers. These EXPRESS products are
Vss designed to meet the needs of those applications
whose operating requirements exceed commercial
= standards.
272318-3
Cl, C2 = 30 PF +10 PF for Crystals The EXPRESS program includes the commercial
For Ceramic Resonators contact resonatormanufacturer.
standard temperature range with burn-in, and an ex-
Figure 3. Oscillator Connections tended temperature range with or without burn-in.

XTAL1: Input to the inverting oscillator amplifier. With the commercial standard temperature range,
operational characteristics are guaranteed over the
XTAL2: Output from the inverting oscillator amplifi- temperature range of O“C to + 70”C. With the ex-
er, tended temperature range option, operational char-
acteristics are guaranteed over a range of –40”C to
+ 85”C.
OSCILLATOR CHARACTERISTICS The optional burn-in is dynamic, for a minimum time
XTAL1 and XTAL2 are the input and output, respec- of 160 hours at 125°C with VCC = 5.5V * 0.25V,
tively, of an inverting amplifier which can be config- following guidelines in MIL-STD-883, Method 1015.
ured for use as an on-chip oscillator, as shown in
Figure 3. Either a quartz crystal or ceramic resonator Package types and EXPRESSversions are identified
may be used. More detailed information concerning by a one- or two-letter prefix to the part number. The
the use of the on-chip oscillator is available in Appli- prefixes are listed in Table 1.
cation Note AP-155; “Oscillators for Microcontrol-
Iers,” Order No, 230659. For the extended temperature range option, this
data sheet specifies the parameters which deviate
from their commercial temperature range limits.

I 5
MCS@51 CONTROLLER

Table 1. EXPRESS Prefix Identification

Prefix Package Type Temperature Range Burn-In

P Plastic Commercial No
D Cerdip Commercial No
N PLCC Commercial No
TD Cerdip Extended No
TP Plastic Extended No
TN PLCC Extended No
LD Cerdip Extended Yes
LP Plastic Extended Yes
NOTE:
Contactdistributoror localsalesofficeto matchEXPRESSprefixwith properdevice.

DESIGN CONSIDERATIONS ● The 8051AHP cannot access external Program

If an 8751 BH or 8752BH is replacing an 8751 H in or Data memory above 4K. This means that the
following instructions that use the Data Pointer
a future design, the user should carefully com-
only read/write data at address locations below
pare both data sheets for DC or AC Characteris-
OFFFH:
tic differences. Note that the VIH and IIH specifi-
cations for the ~ pin differ significantly between
the devices.
MOVX A,@DPTR
MOVX (6JDPTR,
A
Exposure to light when the EPROM device is in
operation may cause logic errors. For this reason, When the Data Pointer contains an address
it is suggested that an opaque label be placed above the 4K limit, those locations will not be ac-
over the window when the die is exposed to am- cessed.
bient light.
To access Data Memory above 4K, the
MOVX @Ri,A or MOVX A,@Ri instructions must
be used.

6
 MCS” 51 CONTROLLER

ABSOLUTE MAXIMUM RATINGS* NOTICE:This is a productiondata sheet. It is valid for

the devices indicated in the revision history. The
Ambient Temperature Under Bias –40”C to + 85°C specificationsare subject to change without notice.
Storage Temperature . –65°C to + 150°C *WARNING:Stressing the device beyond the “Absolute
Voltage on EA/Vpp Pin to Vss Maximum Ratings” may cause permanent damage.
These are stress ratings orr~. Operation beyond the
8751 H . . . . . . . . . . . . . . . . . –0.5V to + 21.5V “Operating Conditions” is not recommended and ex-
8751 BH/6752BH –0.5V tO + 13.OV tended exposure beyond the “Operating Conditions”
may affect device reliabili~.
Voltage on Any Other Pinto Vss . –0.5V to + 7V
Power Dissipation. . . ... 1.5W

OPERATING CONDITIONS
Symbol Description Min Msx Units
TA Ambient Temperature Under Bias
Commercial o +70 “c
Express –40 +65 “c
Vcc SupplyVoltage 4.5 5.5 v
Fosc OscillatorFrequency 3.5 12 MHz

DC CHARACTERISTICS (Over Operating Conditions)

All parameter values apply to all devices unless otherwise indicated
Symbol Parameter Min Max Units Test Conditions
VIL Input Low Voltage (Except ~ Pin of –0.5 0.8 v
6751H and 8751H-8)
VIL1 Input Low Voltage to ~ Pin of o 0.7 v
6751H and 8751H-8
VIH Input High Voltage (Except XTAL2, RST) 2.0 Vcc + 0.5 v
VIH1 Input High Voltage to XTAL2, RST 2.5 Vcc + 0.5 v XTAL1 = Vss
VIH2 Input High Voltage to ~ pin 4.5 5.5V
of 6751BH and 8752BH
VoL Output Low Voltage (Ports 1,2, 3)* 0.45 v loL = 1.6 mA
VoLl Output Low Voltage (Port O,ALE, PSEN)*
8751 H, 8751 H-8 0.60 v ioL = 3.2 mA
0.45 v !OL = 2.4 mA
All Others 0.45 v IOL = 3.2 mA
VOH Output High Voltage (Ports 1,2,3, ALE, PSEN) 2.4 v IOH = –80 PA
VOH1 Output High Voltage (Port Oin 2.4 v IOH = –400 pA
External Bus Mode)
IIL Logical O Input Current (Ports 1,2,3, and RST) –500 pA VIN = 0.45V
IILI Logical O Input Current (~)
8751H and 8751H-8 –15 mA VIN = 0.45V
8751BH –lo mA VIN = Vss
8752BH –lo mA VIN = Vss
0.5 mA

7
MCS” 51 CONTROLLER

DC CHARACTERISTICS (Over Operating Conditions)

~—.-...—.—.
All oarameter values armlv
r.,
_r to.-.
all devices unless otherwise indicated (Continued)
Symbol Parameter Min Max Units Teat Conditions
11L2 Logical OInput Current (XTAL2) –3.2 mA VIN = 0.45V
ILI Input Leakage Current (Porf O)
8751 H and 8751 H-8 * 1or) pA 0.45< VIN < VCC
All Others t 10 pA 0.45< VIN < VCC
IIH Logical 1 Input Current (~)
8751H and 8751H-8 500 pA VIN= 2.4V
8751BH/8752BH 1 mA 4.5V < VIN < 5.5V
IIH1 Input Current to RST to Activate Reset 500 pA VIN < (Vcc – 1.5V)
Icc Power Supply Current:
8031AH/8051 AH/8051AHP 125 mA All Outputs
8032AH/8052AH/8751 BH/8752BH 175 mA Disconnected;
8751H/8751 H-8 250 mA m = Vcc
Clo Pin Capacitance 10 pF Test freq = 1 MHz
NOTES:
1. Capacitive loading on PortsO and 2 may csuse spurious noise pulses to be superimposed on the VOLS of ALE/PROG
and Ports 1 and 3. The noise is dueto externalbuscapacitancedischarginginto the PortOand Port2 pinswhenthesepins
make 1-to-Otransitionsduringbus operations.In the worst cases(capacitiveloading > 100 pF), the noise pulse on the
ALE/PROGpin mayexceed0.8V.In suchcasesit maybe desirableto qualifyALEwitha SchmittTrigger,or usean address
latchwith a Schmi~TriggerSTROBEinput.
2, ALE/PROGrefersto a pin on the 8751BH.ALErefersto a timingsignalthat is outputon the ALE/PROGpin.
3. Understeadystate(non-transient)conditions,loL mustbe externallylimitedas follows:
MaximumloL per port pin: 10 mA
MaximumloL per 8-bitpori -
Porto: 26 mA
Ports1, 2, and 3: 15 mA
Maximumtotal toL for all outputpins: 71 mA
If loL exceedsthe test condition,VOLmayexceedthe relatedspecification.Pinsare not guaranteedto sinkcurrentgreater
than the listedtest conditions.

8
 MCS@51 CONTROLLER

EXPLANATION OF THE AC SYMBOLS L: ~level LOW, or ALE

P: PSEN
Each timing symbol has 5 characters. The first char- Q: Output data
acter is always a ‘T’ (stands for time). The other R: ~ signal
characters, depending on their positions, stand for T: Time
the name of a signal or the logical status of that V: Valid
signal. The following is a list of all the characters and W: WR signal
what they stand for. X: No longer a valid logic level
Z: Float
A: Address
C: Clock For example,
D: Input Data
H: Logic level HIGH TAVLL = Time from Address Valid to ALE Low.
1:Instruction (program memory contents) TLLPL = Time from ALE Low to PSEN Low.

AC CHARACTERISTICS (Under Operating Conditions; Load Capacitance for Port O,ALE/PROG, and
PSEN = 100 pF; Load Capacitance for All Other Outputs = 80 pF)

EXTERNAL PROGRAM MEMORY CHARACTERISTICS

12 MHz Oscillator Variable Oscillator
Symbol Parameter Units
Min Max Min Max
1/TCLCL Oscillator Frequency 3.5 12.0 MHz
TLHLL ALE Pulse Width 127 2TCLCL–40 ns
TAVLL Address Valid to ALE Low 43 TCLCL–40 ns
TLLAX Address Hold after ALE Low 48 TCLCL–35 ns
TLLIV ALE Low to Valid Instr In
8751 H 183 4TCLCL– 150 ns
All Others 233 4TCLCL– 100 ns
TLLPL ALE LOW to PSEN LOW 58 TCLCL–25 ns
TPLPH PSEN Pulse Width
8751H 190 3TCLCL–60 ns
All Others 215 3TCLCL–35 ns
TPLIV PSEN Low to Valid Instr In
8751H 100 3TCLCL– 150 ns
All Others 125 3TCLCL– 125 ns
TPXIX Input Instr Hold after PSEN o 0 ns
TPXIZ Input Instr Float after PSEN 63 TCLCL–20 ns
TPXAV PSEN to Address Valid 75 TCLCL–8 ns
TAVIV Address to Valid Instr In
8751 H 287 5TCLCL–1 50 ns
All Others 302 5TCLCL–1 15 ns
TPLAZ PSEN Low to Address Float 20 20 ns
TRLRH ~ Pulse Width 400 6TCLCL– 100 ns
TWLWH WR Pulse Width 400 6TCLCL– 100 ns
TRLDV ~ Low to Valid Data In 252 5TCLCL– 165 ns
TRHDX Data Hold after ~ o 0 ns
TRHDZ Data Float after ~ 97 2TCLCL–70 ns
TLLDV ALE Low to Valid Data In 517 8TCLCL–1 50 ns
-.. .. . . . ,, . ,–,. , -—.—,.– .,. - nl-n, n, .ec --
I AVUV I Aaaress 10valla Ua[a m I I DUD I I Y I ~LUL— 103 I rm

9
MCS@51 CONTROLLER

EXTERNAL PROGRAM MEMORY CHARACTERISTICS (Continued)

‘arame’erI---%#
cillator VariableOscillator Units
Symbol
Max Min Max
TLLWL ALE Low to RD or WR Low 200 300 3TCLCL–50 3TCLCL+ 50 ns
TAVWL Address to ~ or WR Low 203 4TCLCL– 130 ns
TQVWX Data Valid to WR Transition
8751H
All Others
I 13
23
TCLCL–70
TCLCL–60
ns
ns
TQVWH Data Valid to WR High 433 7TCLCL– 150 ns
TWHQX Data Hold after WR 33 TCLCL–50 ns
TRLAZ RD Low to Address Float 20 I I 20 I ns I
TWHLH RD or WR High to ALE High
8751H 33 133 TCLCL–50 TCLCL+ 50 ns
All Others 43 123 TCLCL–40 TCLCL+40 ns

NOTE:
“The 8751H-8 is identicalto the 8751Hbut only o~eratesutI to 8 MHz.Whencalculatingthe AC Characteristicsfor the
8751 H-8, use the 8751 H formula for variable oscillators.

10
 MCS@51 CONTROLLER

EXTERNAL PROGRAM MEMORY READ CYCLE

w--- TLHLL _

ALE \ ,
/ \
TLLPL- ~ TPLPH
-TAVLL+ + TLLIV

PSEN
/

TLLAX

PORTO

PORT 2
x
1
AO -A15
x A8 -A15

272318-5

EXTERNAL DATA MEMORY READ CYCLE

ALE
Y \ /
+TLHLL+ TWHLH

PSEN
‘LLOv ~
— TLLWL TRLRH –—

m
+ TAVLL + b i ‘
—TRLDV4
_TLLAX
TRHOX+

PORTO AO-A7 FROM RI OR OPL OATA IN

.
. TAVOV b

PORT2 x r
P2.O-P2.7 OR A8-A15 FROMDPH x A8-A15 FROMPCH

272318-6

EXTERNAL DATA MEMORY WRITE CYCLE

ALE \ ,
\ /
TLHLL— TWHLH

m
/
‘TLLwL~TwLwH *

WT

1
TAVLL 1 ‘
k
TQVWX
TWHQX
+TLLAX
7t=-
II I
TQVWH : r
1
PORTO
AO-A7
FROMRIOR OPL M
OATAOUT
xx AO-A7 FROMFCL

I
PORT2 x P2.O-P2.7 OR A8-A15 FROMOPH
x A8-A15 FROMPCH

272318-7

11
M=” 51 CONTROLLER

SERIAL PORT TIMING—SHIFT

Test Conditions: Over ODeratina Conditions: Load Capacitance = 80 rJF
12 MHz Oscillator VariableOscillator
Symbol Parameter Unite
Min Max Min Max
TXLXL Serial Port Clock Cycle Time 1.0 12TCLCL ps
TQVXH Output Data Setup to Clock Rising 700 1OTCLCL– 133 ns
Edge
TXHQX Output Data Hold after Clock 50 2TCLCL–1 17 ns
Rising Edge
TXHDX Input Data Hold after Clock Rising o 0 ns
Edge
TXHDV Clock Rising Edge to Input Data 700 10TCLCL– 133 ns
Valid

;HI17REGISTERMODETIMINGWAVEFORMS

INSTRUCTION I O I 1 I 2 I 3 I 4 I 5 I 6 I 7 I 8 I
ALE n n n n n n n n n n n n n n n n n n I
I-TXLXL-7
CLOCK

WI-TXHQX I
OUTPUT OATA o 1)( 1 2 x 3 x 4 x 5 x 6 x 7
/
, +
SET TI
INPUT DATA

~ 4
SET RI
272318-8

12
 MCS@51 CONTROLLER

EXTERNAL CLOCK DRIVE

Symbol Parameter Min Max Units 1
1/TCLCL Oscillator Frequency (except 8751H-8) 3.5 12 MHz
8751H-8 3.5 8 MHz
TCHCX High Time 20 ns
TCLCX Low Time 20 ns
I TCLCH I Rise Time I I 20 I ns I
TCHCL Fall Time 20 ns

EXTERNAL CLOCK DRIVE WAVEFORM

— TCHCX — TCLCH _ — — ~ TCliCL

2.5 t a A
t 2.5

-— TCLCX —

+ TCLCL w

272318-9

AC TESTING INPUT, OUTPUT WAVEFORM

2.4
2.0 2.0

TEST POINTS
><
0.s 0.8
0.45

272318-10
AC Testing: Inputs are driven at 2.4V for a Logic “1” and 0.45V
for a Logic “O”. Timing measurements ara made at 2.OV for a
Logic “1” and 0.8V for a Logic“O”.
MCS@51 CONTROLLER

EPROM CHARACTERISTICS
Table3. EPROMProgramming
Modea
Mode RST PSEN ALE m P2.7 P2.6 P2.5 P2.4
Program 1 0 o* VPP 1 0 x x
Verify 1 0 1 1 0 0 x x
Security Set 1 0 o* VPP 1 1 x x
NOTE:
“1” = logichighfor that pin “VPP” = +21V *0.5V
“O” = logiclowfor that pin *ALEis pulsedlowfor 50 ms
“X” = “don’t care”

PROGRAMMING THE 8751H Note that the ~/VPP pin must not be allowed to go
above the maximum specified VPP level of 21.5V for
To be programmed, the part must be running with a any amount of time. Even a narrow glitch above that
4 to 6 MHz oscillator. (The reason the oscillator voltage Ievei can cause permanent damage to the
needs to be running is that the internal bus is being device. The VPP source should be well regulated
used to transfer address and program data to appro- and free of glitches.
priate internal registers.) The address of an EPROM
location to be programmed is applied to Port 1 and
pins P2.O-P2.3 of Port 2, while the code byte to be Program Verification
programmed into that location is applied to Port O. If the Security Bit has not been programmed, the on-
The other Porl 2 pins, and RST, PSEN, and ~/Vpp chip Program Memory can be read out for verifica-
should be held at the “Program” levels indicated in tion purposes, if desired, either during or after the
Table 3. ALE/PROG is pulsed low for 50 ms to pro- programming operation. The address of the Program
gram the code byte into the addressed EPROM lo- Memory location to be read is appiied to Port 1 and
cation. The setup is shown in Figure 5. pins P2.O-P2.3. The other pins should be held at the
“Verify” Ieveis indicated in Tabie 3. The contents of
Normally ~~is held at a logic highflntil just the addressed location will come out on Port O. Ex-
before ALE/PROG is to be pulsed. Then EA/Vpp is ternal pullups are required on Port O for this opera-
raised to +21 V, ALE/PROG is pulsed, and then tion.
~/Vpp is returned to a logic high. Waveforms and
detailed timing specifications are shown in later sec- The setup, which is shown in Figure 6, is the same
tions of this data sheet. as for programming the EPROM except that pin P2.7
is held at a logic low, or may be used as an active-
Iow read strobe
+5V

Vcc +5V

AOOR A&b? p? ?
—FFH w PGM DATA Vcc
P2.0–
U–All mu
P2.3
w + DATA
a 8751H —FFH (USE 10K

‘=’’-”TCAREJ=E
‘LEl=$=-
PULLUPS]
W51H
~ . ,,W,, CARE,. x - ~~b

U
X-9 P2.5 ALE
Vlli P2.7
VIL d P2.S VIH
XTAU 5 F&vPP
ENAS4E . P2 7 G
4-SUN* n
XTAU
XTAL1 RST VIH1 J-
4-6 MHZm RST h VIH1
Vss PSEN
XTAL1

. . Vss PSEN

27231 a-1 I .

27231S-12
Figure5. Programming
Configuration
Figure6. ProgramVerification

14
 MCS@51 CONTROLLER

EPROM Security +5V

X = OGN’T CARE”
o
The security feature consists of a ‘locking” bit which f
when programmed denies electrical access by any Vcc
external means to the on-chip Program Memory. PI
The bit is programmed as shown in Figure 7. The

‘-
m x
setup and procedure are the same as for normal P2.0-
EPROM programming, except that P2.6 is held at a X P2.3
8751H
logic high, Porl O,Port 1 and pins P2.O–P2.3 may be
in any state. The other pins should be held at the P2.4 ALE ALE/PROO
50 ma PULSE TO GND
“Security” levels indicated in Table 3. {:
P2.5
P2.6
VIM
Once the Security Bit has been programmed, it can P2,7 fi + EAYPP
be cleared only by full erasure of the Program Mem- XTAU
ory. While it is programmed, the internal Program
m RST — WH1
Memory can not be read out, the device can not be
XTAL1
further programmed, and it cannot executeout of
externalprogrammemory.Erasing the EPROM, Vss PSEN

thus clearing the Security Bit, restores the device’s * 7*

full functionality. It can then be reprogrammed.
272318-13

Figure7. Programming
the SecurityBit
Erasure Characteristics
The recommended erasure procedure is exposure
Erasure of the EPROM begins to occur when the to ultraviolet light (at 2537 Angstroms) to an integrat-
device is exposed to light with wavelengths shorter ed dose of at least 15 W-sec/cm2. Exposing the
than approximately 4,000 Angstroms. Since sunlight EPROM to an ultraviolet lamp of 12,000 pW/cm2
and fluorescent lighting have wavelengths in this rating for 20 to 30 minutes, at a distance of about
range, exposure to these light sources over an ex- 1 inch, should be sufficient.
tended time (about 1 week in sunlight, or 3 years in
room-level fluorescent lighting) could cause inadver- Erasure leaves the array in an all 1‘s state.
tent erasure. If an application subjects the device to
this type of exposure, it is suggested that an opaque
label be placed over the window.

EPROM PROGRAMMING AND VERIFICATION CHARACTERISTICS

TA = 21°C to 27”C; VCC = 5V + 10%; VSS = OV
Symbol Parameter Min Max Unita
VPP Programming Supply Voltage 20.5 21.5 v
IPP Programming Supply Current 30 mA
1/TCLCL Oscillator Frequency 4 6 MHz
TAVGL Address Setup to PROG Low 46TCLCL
TGHAX Address Hold after PROG 48TCLCL
TDVGL Data Setup to PROG Low 48TCLCL
TGHDX Data Hold after~ 48TCLCL
TEHSH P2.7 (ENABLE) High to VPP 48TCLCL
TSHGL VPP Setup to PROG Low 10 ps
TGHSL VPP Hold after PROG 10 ps
TGLGH PROG Width 45 55 ms
TAVQV Address to Data Valid 48TCLCL
TELQV ENABLE Low to Data Valid 48TCLCL
TEHQZ Data Float after ENABLE o 48TCLCL

15
MCS” 51 CONTROLLER

GI-” ”nl r“”” ”mrnmrlmn. w I-8. ” ,Lrl.. .“4-s . m“.. ..-. b. “..8.,”

PROGRAMMING VERIFICATION

P1.O-PI.7
( ADDRESS
P3,0-P3,3
$ J

PORTO DATAIN
{ ,

TOVGL — — —TGHOX

TAVGL — TGHAX
kLE/PROG
\ ~ ‘

TSHGL — — — TGHSL
TGLGH
21V * .5V
r
\
m HIGH TTL HIGH TTL HIGH
Fi.vPP

TSHSN
— TELOV

P3.7
(ENABLE) \
1 ‘
272318-14
For programmingconditionssee Figure 5. For verificationconditionssee Figure 6.

16
inlA MCS” 51 CONTROLLER

Programming the 8751BH/8752BH Normally ~&is held at a logic high until just
before ALE/PROG is to be pulsed. Then ~/Vpp is
To be programmed, the 875XBH must be running raised to Vpp, ALE/PROG is pulsed low, and then
with a 4 to 6 MHz oscillator. (The reason the oscilla- ~/Vpp is returned to a valid high voltage. The volt-
tor needs to be running is that the internal bus is age on the ~/Vpp pin must be at the valid EA/Vpp
being used to transfer address and program data to high level before a verify is attempted. Waveforms
appropriate internal registers.) The address of an and detailed timing specifications are shown in later
EPROM location to be programmed is applied to sections of this data sheet.
Porl 1 and pins P2.O- P2.4 of Port 2, while the code
byte to be programmed into that location is applied Note that the ~/Vpp pin must not be allowed to go
to Port O. The other Port 2 and 3 pins, and RST, above the maximum specified Vpp level for any
PSEN, and ~/Vpp should be held at the “Program” amount of time. Even a narrow glitch above that volt-
levels indicated in Table 1. ALE/PROG is pulsed low age level can cause permanent damage to the de-
to croaram the code bvte into the addressed vice. The Vpp source should be well regulated and
EPROfl location. The setu’p is shown in Figure 8. free of glitches.

+5V

Vcc

Po

1~ RST E/vpp ~ +12.75V

ALE/PROG ~25 100 p, PULSESTO GND

1~ P3.6

875X,, ~ ~“
1~ P3.7
P2.7 ~1

XTAL2 P2.6 ~o
lJ-
4-6 MHz ❑
T= ; XTAL1
P2.O
-P2,4
‘ks

=
272318-15
—. —
Figure8. Programming
the EPROM

Table4. EPROMProgramming
Modeafor 875XBH
ALE/ ml
MODE RST PSEN — P2.7 P2.6 P3.6 P3.7
PROG Vpp
Program Code Data 1 0 o* Vpp 1 0 1 1
Verify Code Data 1 0 1 1 0 0 1 1
Program Encryption Tabie 1 0 o* Vpp 1 0 0 1
Use Addresses O-1FH
Program Lock ~= 1 1 0 o* Vpp 1 1 1 1
Bits (LBx) x=2 1 0 o* Vpp 1 1 0 0
Read Signature 1 0 1 1 0 0 0 0

NOTES:
“1” = Validhighfor that pin
“O” = Validlowfor that pin
“vpp” = + 12.75V+ 0.25V
*ALE/PROGis pulsedlowfor 100USfor programming.(Quick-PulseProgramming)

17
MCS@51 CONTROLLER

QUICK-PULSE PROGRAMMING PROGRAM VERIFICATION

ALGORITHM
If the Lock Bits have not been programmed, the on-
The 875XBH can be programmed using the Quick- chip Program Memory can be read out for verifica-
Pulse Programming Algorithm for microcontrollers. tion purposes, if desired, either during or after the
The features of the new programming method are a programming operation. The address of the Program
lower Vpp (12.75 volts as compared to 21 volts) and Memory location to be read is applied to Port 1 and
a shorter programming pulse. For example, it is pos- pins P2.O - P2.4. The other pins should be held at
sible to program the entire 8 Kbytes of 875XBH the “Verify” levels indicated in Table 1. The con-
EPROM memory in less than 25 seconds with this tents of the addressed location will come out on Port
algorithm! O. External pullups are required on Port O for this
operation. (If the Encryption Array in the EPROM
To program the part using the new~rithm, Vpp has been programmed, the data present at Port O
must be 12,75 f 0.25 Volts. ALE/PROG is pulsed will be Code Data XNOR Encryption Data. The user
low for 100 pseconds, 25 times as shown in must know the Encryption Array contents to manual-
Figure 9, Then, the byte just programmed may be ly “unencrypt” the data during verify.)
verified. After programming, the entire array should
be verified. The Program Lock features are pro- The setup, which is shown in Figure 10, is the same
grammed using the same method, but with the setup as for programming the EPROM except that pin P2.7
as shown in Table 4. The only difference in program- is held at a logic low, or may be used as an active
ming Lock features is that the Lock features cannot low read strob~.
be directly verified. Instead, verification of program-
ming is by observing that their features are enabled.

, ~25p”LsEs ~
ALEM
n--------
100JM
10 P,MIN
I “ *lops

ALE/PROG:
0 1 272318-16

Figure9. PROGWaveforma

+~v

h 10kJl

‘r-F’
Vcc X8
PGM
AO-A7 P! Po
DATA

RST rmpp

ALE/PRW 1
P3.6

B75xBH = 0
1 P3.7
P2.7 0 (i-mm

L
XTAL2 P2.6 0

4-6 MHz ❑
XTAL1 P2.O
A8-A12
-P2.4
Vss
F
=
272318-17

Figure10.Verifyingthe EPROM

18
 MCS@51 CONTROLLER

PROGRAM MEMORY LOCK Table5. LockBitsandtheirFeatures

The two-level Program Lock system consists of 2 LogicEnabled

Lock bits and a 32-byte Encryption Array which are LB1
used to protect the program memory against soft-
ware piracy. u Minimum Program Lock features
enabled. (Code Verify WIIIstill be

ENCRYPTION ARRAY =
P u MOVC instructions executed from
Within the EPROM array are 32 bytes of Encryption external program memory are
Array that are initially unprogrammed (all 1s). Every disabled from fetching code bytes
time that a byte is addressed during a verify, 5 ad- from internal memory, EA is
dress lines are used to select a byte of the Encryp- sampled and latched on reset,
tion Array. This byte is then exclusive-NORed and further programming of the
(XNOR) with the code byte, creating an Encrypted EPROM is disabled
Verify byte. The algorithm, with the array in the un-
programmed state (all 1s), will return the code in its
original, unmodified form.
P
I P Same as above, but Verify is also
disabled

It is recommended that whenever the Encryption Ar-

U I P IReservedfor Future Definition I
ray is used, at least one of the Lock Bits be pro- = Programmed
= Unprogrammed
grammed as well.

LOCK BITS READING THE SIGNATURE BYTES

The signature bytes are read by the same procedure
Also included in the EPROM Program Lock scheme
are two Lock Bits which function as shown in Table as a normal verification of locations 030H and 031H,
5. except that P3.6 and P3.7 need to be pulled to a
logic low. The values returned are:
Erasing the EPROM also erases the Encryption Ar- (030H) = 89H indicates manufactured by Intel
ray and the Lock Bits, returning the part to full un- (031H) = 51H indicates 8751BH
locked functionality.
52H indicates 8752BH
To ensure proper functionality of the chip, the inter-
nally latched value of the ~ pin must agree with its
external state.

19
MCS” 51 CONTROLLER

ERASURE CHARACTERISTICS this type of exposure, it is suggested that an opaque

label be placed over the window.
Erasure of the EPROM begins to occur when the
8752BH is exposed to light with wavelengths shorter The recommended erasure procedure is exposure
than approximately 4,000 Angstroms. Since sunlight to ultraviolet light (at 2537 Angstroms) to an integrat-
and fluorescent lighting have wavelengths in this ed dose of at lease 15 W-see/cm. Exposing the
range, exposure to these light sources over an ex- EPROM to an ultraviolet lamp of 12,000 pW/cm rat-
tended time (about 1 week in sunlight, or 3 years in ing for 30 minutes, at a distance of about 1 inch,
room-level fluorescent lighting) could cause inadver- should be sufficient.
tent erasure. If an application subjects the device to
Erasure leaves the array in an all Is state.

EPROM PROGRAMMING AND VERIFICATION CHARACTERISTICS

(T,4 = 21°C to 27”C, Vcc = 5.OV + 10%, Vss = OV)
Symbol Parameter Min Max Units
Vpp Programming Supply Voltage 12.5 13.0 v

Ipp Programming Supply Current 50 mA

1/TCLCL Oscillator Frequency 4 8 MHz
TAVGL Address Setup to PROG Low 48TCLCL
TGHAX Address Hold After PROG 48TCLCL
TDVGL Data Setup to PROG Low 48TCLCL
TGHDX Data Hold After PROG 48TCLCL
TEHSH P2.7 (ENABLE) High to Vpp 48TCLCL
TSHGL Vpp Setup to PROG Low 10 ps
TGHSL Vpp Hold After PROG 10 ps
TGLGH PROG Width 90 110 ps
TAVQV Address to Data Valid 48TCLCL
TELQV ENABLE Low to Data Valid 48TCLCL
TEHQZ Data Float After ENABLE o 48TCLCL
TGHGL PROG High to PROG Low 10 ps

EPROM PROGRAMMING AND VERIFICATION WAVEFORMS

PROGRAMMING VERIFICATION

ADDRESS ADDRFSS

TAvQV

DATAIN DATAOUT
‘::=&z TDVGL ~ ~TGHDX
.- }
TAVGL Pu& TGHAX

TSHGL d TGHsL
TGLGH TGHGL
~wpp t
[A/HIGH

TELQV L TEHQZ

P2.7

272318-18

20
 MCS@51 CONTROLLER

DATA SHEET REVISION HISTORY

Datasheets are changed as new device information becomes available. Verify with your local Intel sales office
that you have the latest version before finalizing a design or ordering devices.

The following differences exist between this datasheet (272318-002) and the previous version (272318-001):
1. Removed QP and QD (commercial with extended burn-in) from Table 1. EXPRESS Prefix Identification.

This datasheet (272318-001) replaces the following datasheets:

MCS@51 Controllers (270048-007)
8051AHP (270279-004)
8751BH (270248-005)
8751 BH EXPRESS (270708-001)
8752BH (270429-004)
8752BH EXPRESS (270650-002)

21