Ssqu 017

Embedded System Design
using TIVA
SSQU017
Contents
Foreword……………………………………………………………………………………………..………10
1 Embedded Systems and Features ............................................................................................ 12
1.1 Introduction.......................................................................................................................................... 13
1.1.1 Hardware Components of Embedded System ....................................................................... 13
1.1.2 Instruction Set Architecture..................................................................................................... 19
1.2 ARM Architecture ................................................................................................................................ 20
1.2.1 A Basic architecture of the ARM7core .................................................................................... 21
1.2.2 Registers ................................................................................................................................. 21
1.2.3 Current Program Status Register (CPSR) .............................................................................. 22
1.2.4 Operating States ..................................................................................................................... 23
1.2.5 Operating Modes .................................................................................................................... 23
1.2.6 Programming Model ............................................................................................................... 24
1.2.7 Interrupt and Exception Handling ........................................................................................... 25
1.2.8 ARM Instruction Set ................................................................................................................ 26
1.2.9 Migration to Cortex Series ...................................................................................................... 33
1.2.10 ARM architecture v7 profile: ................................................................................................... 34
1.2.11 ARMv7-M architecture: ........................................................................................................... 35
1.2.12 Operating States and Operating Modes: ................................................................................ 38
1.2.13 Programming Model: .............................................................................................................. 39
1.2.14 Instruction Set: Tables with all categories of instructions with descriptions. Load/Store
instructions with addressing modes. ............................................................................................ 41
1.2.15 CMSIS: ................................................................................................................................... 49
1.2.16 Introduction to TIVA Microcontrollers ..................................................................................... 49
1.3 Summary ............................................................................................................................................. 53
1.4 Review Questions ............................................................................................................................... 54
2 Microcontroller Fundamentals for Basic Programming ......................................................... 55
2.1 Introduction.......................................................................................................................................... 56
2.2 Programming in Embedded Systems.................................................................................................. 56
2.2.1 Data Types.............................................................................................................................. 57
2.2.2 Bit-wise Operations................................................................................................................. 58
2.3 Programming Tiva CSeries ................................................................................................................. 58
2.3.1 Development Tools ................................................................................................................. 58
2.3.2 Introduction to Code Composer Studio .................................................................................. 58
2.4 Peripheral and Memory Address......................................................................................................... 60
2 Embedded System Design using TIVA

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2.4.1 Peripheral Addressing ............................................................................................................ 60

2.4.2 Memory Map ........................................................................................................................... 61
2.5 Programming GPIO in TivaTM Launchpad ......................................................................................... 65
2.5.1 GPIO Pins in Tiva Launchpad ................................................................................................ 66
2.5.2 Advanced features of GPIO in Tiva Launchpad ..................................................................... 67
2.5.3 Direction and Data Registers .................................................................................................. 67
2.5.4 Toggling Multicolor LED.......................................................................................................... 68
2.5.5 Using RGB LED Example ....................................................................................................... 70
2.6 Watchdog Timer .................................................................................................................................. 71
2.7 Interrupts ............................................................................................................................................. 72
2.7.1 Introduction to Interrupts and Polling ...................................................................................... 72
2.7.2 Interrupt vector table ............................................................................................................... 73
2.7.3 Predefined Interrupts (INT0-INT15)........................................................................................ 74
2.8 Low Power Microcontroller .................................................................................................................. 78
2.8.1 Need for Low Power Microcontroller....................................................................................... 78
2.8.2 Hibernation Module on TivaTM Microcontrollers .................................................................... 78
2.8.3 Programming Hibernation Module .......................................................................................... 80
2.9 Summary ............................................................................................................................................. 83
2.10 Review questions ................................................................................................................................ 84
3 Timers, PWM and Mixed Signal Processing ............................................................................ 85
3.1 Introduction.......................................................................................................................................... 86
3.2 Timers ................................................................................................................................................. 86
3.2.1 Basic Timers/Counters ........................................................................................................... 89
3.2.2 Real Time Clock (RTC) .......................................................................................................... 90
3.2.3 Timing Generation and Measurement .................................................................................... 91
3.3 Analog to Digital Converter (ADC) ...................................................................................................... 94
3.3.1 Block Diagram......................................................................................................................... 95
3.3.2 Functional Description ............................................................................................................ 96
3.4 Analog Comparators ........................................................................................................................... 97
3.4.1 Functional Description ............................................................................................................ 97
3.4.2 Analog Comparator Module Block Diagram ........................................................................... 99
3.5 Analog Interfacing and Data Acquisition ........................................................................................... 100
3.5.1 Analog Interfacing ................................................................................................................. 100
3.5.2 Data Acquisition .................................................................................................................... 101
3.6 Direct Memory Access (DMA) ........................................................................................................... 102
3.6.1 DMA Controller ..................................................................................................................... 102
3.6.2 Types of DMA ....................................................................................................................... 103
3.7 Pulse Width Modulation .................................................................................................................... 104
3.7.1 PWM using TIVA TM4C123HG6PM ..................................................................................... 104
3.7.2 Block Diagram....................................................................................................................... 105
3.7.3 Functional Description .......................................................................................................... 106
3.8 Quadrature Encoder Interface (QEI) ................................................................................................. 109
3.8.1 Interfacing QEI using Tiva TM4C123GH6PM....................................................................... 109
3.8.2 Functional Description .......................................................................................................... 110
3.9 Summary ........................................................................................................................................... 114
Embedded System Design using TIVA 3

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3.10 Review Questions ............................................................................................................................. 115

4 Communication Protocols and Interfacing with External Devices ...................................... 116
4.1 Introduction........................................................................................................................................ 117
4.2 Synchronous and Asynchronous protocols ....................................................................................... 118
4.3 Universal Asynchronous Receiver-Transmitter ................................................................................. 118
4.3.1 Half and Full duplex communication ..................................................................................... 118
4.3.2 Data Frame in UART ............................................................................................................ 119
4.3.3 Data transfer rate .................................................................................................................. 119
4.3.4 Serial I/O Standards ............................................................................................................. 119
4.3.5 Pin Map for RS232 (DB-9 connector) ................................................................................... 120
4.4 Programming UART on Tiva Platform............................................................................................... 122
4.4.1 UART Register Map .............................................................................................................. 123
4.4.2 Serial IR (SIR) ....................................................................................................................... 124
4.4.3 UART Control register (UARTCTL) ...................................................................................... 125
4.4.4 UART Line Control Register (UARTLCTH) .......................................................................... 125
4.4.5 UART Data Register (UARTDR)........................................................................................... 126
4.4.6 UART Transmission .............................................................................................................. 127
4.4.7 UART Reception ................................................................................................................... 127
4.4.8 Basic UART programing ....................................................................................................... 128
4.5 Inter IC (I2C) Communication Protocol ............................................................................................. 131
4.5.1 General Electrical Characteristics of I2C .............................................................................. 131
4.5.2 I2C in Tiva microcontroller TM4C123GH6PM ...................................................................... 133
4.5.3 I2C Network .......................................................................................................................... 134
4.5.4 Configuring GPIO for I2C Network ....................................................................................... 139
4.5.5 RTC interfacing (DS1307) with Tiva Microcontroller ............................................................ 140
4.6 Serial Peripheral Interface (SPI) ....................................................................................................... 143
4.6.1 SPI in Tiva Microcontroller .................................................................................................... 144
4.6.2 Configuring the SSI ............................................................................................................... 146
4.6.3 Bit Rate ................................................................................................................................. 147
4.6.4 Data Register ........................................................................................................................ 148
4.6.5 SPI data Transmission.......................................................................................................... 148
4.6.6 NVIC interrupt for SSI ........................................................................................................... 149
4.7 Summary ........................................................................................................................................... 153
5 Embedded Networking and Internet of Things (IoT) ............................................................. 155
5.1 Introduction........................................................................................................................................ 156
5.2 Embedded Networking Fundamentals .............................................................................................. 156
5.2.1 Embedded Network and Ethernet ........................................................................................ 157
5.3 TCP/IP Introduction IoT overview and architecture .......................................................................... 161
5.3.1 Internet Protocol version 6 (IPv6) ......................................................................................... 161
5.3.2 Internet of Things (IOT): ....................................................................................................... 162
5.3.3 Applications of IOT ............................................................................................................... 163
5.3.4 Architecture of IOT ................................................................................................................ 164
5.3.5 Challenges of IOT ................................................................................................................. 165
5.4 Wireless Sensor Networks ................................................................................................................ 166

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5.4.1 Wireless Connectivity in Embedded Networks ..................................................................... 168

5.5 Various Wireless Protocols and their Applications ............................................................................ 169
5.5.1 Near Field Communication (NFC) ........................................................................................ 169
5.5.2 ZigBee................................................................................................................................... 170
5.5.3 Bluetooth ............................................................................................................................... 171
5.5.4 Wi-Fi...................................................................................................................................... 171
5.6 Adding Wi-fi to a Microcontroller-Based System using CC3100 Simplelink Wi-fi Module ............... 171
5.6.1 Architecture of SimpleLink Wi-Fi CC3100 Module................................................................ 173
5.6.2 Features of Wi-Fi supported by CC3100 chip ...................................................................... 173
5.6.3 CC3100 SimpleLink Driver and its Application Programming Interface (API) ...................... 174
5.6.4 Programmer‟s model for CC3100 SimpleLink driver and its API ......................................... 175
5.7 Case Studies with SimpleLink Wi-Fi CC3100 and TIVA Launchpad ................................................ 176
5.7.1 Case Study -1 ....................................................................................................................... 176
5.7.2 Case Study -2 ....................................................................................................................... 180
5.8 Summary ........................................................................................................................................... 183

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List of Figures
Fig 1.1. Basic block diagram of an embedded system ................................................................................ 14
Fig 1.2. Processing Unit and System Bus ................................................................................................... 15
Fig 1.3. (a) Harvard Architecture and (b) Von-Neumann Architecture ........................................................ 16
Fig 1.4: Interconnection of RAM with Microprocessor ................................................................................. 17
Fig 1.5. Interconnection of external devices with Microprocessor ............................................................... 18
Fig 1.6. Stepper motor control embedded system ....................................................................................... 19
Fig 1.7. ARM 7 Architecture [an excerpt from Google image] ..................................................................... 20
Fig 1.8. User mode register set.................................................................................................................... 22
Fig 1.9. A generic CPSR Format ................................................................................................................. 22
Fig 1.11. Barrel Shifter with ALU.................................................................................................................. 28
Fig 1.12. Performance and capability graph of Classic ARM and Cortex embedded processors. .............. 33
Fig 1.13. Performance and capability graph of Classic ARM and Cortex application processors. ............. 34
Fig 1.14. Cortex M4 core architecture ......................................................................................................... 36
Fig 1.15. Operating States of ARM Core ..................................................................................................... 38
Fig 1.16. Operating Modes of ARM Core .................................................................................................... 39
Fig 1.17. Programming model...................................................................................................................... 40
Fig 1.18 xPSR diagram ................................................................................................................................ 41
Fig 1.22. IEEE 754 single precision format .................................................................................................. 47
Fig 1.20. TIVA TM4C123GH6PM Microcontroller block diagram. ............................................................... 50
Fig 1.21 TIVA TM4C129CNCZAD Microcontroller block diagram ............................................................... 51
Fig 2.1 Fire Alarm......................................................................................................................................... 56
Fig 2.2: Flowchart to glow onboard LED ...................................................................................................... 63
Fig 2.3 Memory Map File ............................................................................................................................. 64
Fig 2.4 Memory Configuration for the output file.......................................................................................... 64
Fig 2.5 Switches and RGB schematic connection to GPIO pins ................................................................. 68
Fig 2.6 Flowchart for line follower robot ....................................................................................................... 69
Fig 2.7 Operation of Watchdog Timer .......................................................................................................... 72
Fig 2.8 Flowchart for servicing timer interrupts ............................................................................................ 77
Fig 2.9 Debug Window ................................................................................................................................. 78
Fig 2.10 Power vs Flexibility ........................................................................................................................ 78
Fig 2.11 Block diagram of Hibernation module ............................................................................................ 79
Fig 3.1. Automatic Washing Machine .......................................................................................................... 86
Fig 3.2. GPTM block diagram ...................................................................................................................... 88
Fig 3.3. Real Time Clock with external power source.................................................................................. 91
Fig 3.4. Frequency Based Measurement System........................................................................................ 92
Fig 3.5. (a) Period based input Read with free running counter .................................................................. 93
Fig 3.5. (b) Period based input Read with counter that increments only while gate input is HIGH (Gate
connected to Period Based Input) .................................................................................................. 93
Fig 3.6. Block Diagram of working of an ADC ............................................................................................. 94
Fig 3.7. Implementation of two ADC blocks ................................................................................................. 94
Fig 3.8 ADC Module Block Diagram ............................................................................................................ 95
Fig 3.9 Structure of Comparator Unit ........................................................................................................... 98
Fig 3.10. Analog comparator module block diagram ................................................................................... 99
Fig 3.11. Analog Interfacing Network......................................................................................................... 100

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Fig 3.12. The Analog-Digital-Analog signal path with real time processing .............................................. 101
Fig 3.13. The DMA controller Architecture ................................................................................................. 103
Fig 3.14. PWM Module Block Diagram ...................................................................................................... 105
Fig 3.15. PWM Generator Block Diagram ................................................................................................. 106
Figure 3.16 (a). PWM Count-Down Mode ................................................................................................. 107
Figure 3.16 (b) PWM Count- Up/Down Mode............................................................................................ 107
Fig 3.17. QEI Input Signal Logic ................................................................................................................ 109
Fig 3.18. QEI Block Diagram ..................................................................................................................... 110
Fig 3.19. Schematic for motor control using TIVA ..................................................................................... 112
Fig 3.20. Flowchart for DC motor control using PWM ............................................................................... 113
Fig 4.1. Weather monitoring using sensor hub balloon ............................................................................. 117
Fig 4.2. Frame for ASCII „A‟ (01000001) ................................................................................................... 119
Fig 4.3. MAX 232 and microcontroller connection ..................................................................................... 120
Fig 4.4. DB-9 Connector ............................................................................................................................ 120
Fig 4.5. Different encoding schemes for serial communication ................................................................. 121
Fig 4.6. Simplified block diagram of UART ................................................................................................ 123
Fig 4.7. Baud rate registers........................................................................................................................ 123
Fig 4.8. UART Control (UARTCTL) register .............................................................................................. 125
Fig 4.9. UART Line Control (UARTLCTH) register .................................................................................... 125
Fig 4.10. UART Date Register (UARTDR) ................................................................................................. 126
Fig 4.11. UART Date Register (UARTDDR) .............................................................................................. 127
Fig 4.12. I2C Bus ........................................................................................................................................ 131
Fig 4.13. I2C START and STOP bits ......................................................................................................... 132
Fig 4.14. I2C Frame Format ....................................................................................................................... 132
Fig 4.15. I2C combined address and data ................................................................................................ 133
Fig 4.16. I2C Networking using Tiva microcontroller .................................................................................. 134
Fig 4.17. RunMode Clock Gating Control Register.................................................................................... 134
Fig 4.18. I2C Master Time Period Register ............................................................................................... 135
Fig 4.20. I2C Master Slave Address Register ............................................................................................ 137
Fig 4.20. I2C Master Data Register ........................................................................................................... 137
Fig 4.22. I2C Master Control/Status Register ............................................................................................ 137
Fig 4.23. Data transmission using (a) Master Single Transmit, (b) Single Master receive........................ 139
Fig 4.24. DS1307 Interfacing with TIVA ..................................................................................................... 140
Fig 4.25. RTC Control Register.................................................................................................................. 140
Fig 4.26. Serial Peripheral Interface .......................................................................................................... 143
Fig 4.27. SPI Timing Diagram .................................................................................................................... 144
Fig 4.28. Synchronous Serial Interface Run Mode Clock Gating Control CRCG (SSI) Register .............. 146
Fig 4.29. SSI Control O Register ............................................................................................................... 146
Fig 4.30. SSI Clock Prescaler Register ..................................................................................................... 147
Fig 4.31. SSI Control 1 Register ................................................................................................................ 148
Fig 4.32. SSI Data Register ....................................................................................................................... 148
Fig 4.33. SSI Status Register..................................................................................................................... 148
Fig 4.35 Booster Pack Pinout Standard ..................................................................................................... 151
Fig 4.36. Flowchart: Interfacing TIVA with Sensor Hub Booster Pack ...................................................... 152
Fig 5.1. Embedded Network ...................................................................................................................... 156

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Fig. 5.2. Embedded Network for Smart Home Application......................................................................... 157

Fig 5.3. Embedded networking with Ethernet ........................................................................................... 158
Fig 5.4 Transaction between an echo client and an echo server .............................................................. 159
Fig. 5.5 Smart Home Architecture with Ethernet interface to the sensor network ..................................... 161
Fig. 5.6 Smart Home Architecture with TCP/IP connectivity to the Internet ............................................... 161
Fig. 5.7. Main components of IoT ............................................................................................................... 163
Fig 5.8. The IOT Players ............................................................................................................................ 164
Figure 5.9. Architecture of IoT ................................................................................................................... 165
Fig. 5.10. A Typical Sensor Network Architecture ..................................................................................... 167
Fig. 5.11 Protocol stack of OSI .................................................................................................................. 168
Fig 5.12.. Comparison of different wireless technologies........................................................................... 169
Fig 5.14. Zigbee co-ordinator with end device ........................................................................................... 170
Fig. 5.13 Zigbee Protocol Stack ................................................................................................................. 170
Fig. 5.15 CC2640 Wireless MCU ............................................................................................................... 171
Fig. 5.16 Functional diagram of SimpleLink Wi-Fi CC3100 Module ........................................................... 172
Fig. 5.17 CC3100 Boosterpack (SimpleLink Wi-Fi) mounted on TIVA Launchpad .................................... 172
Fig. 5.18 Hardware Architecture for CC3100 ............................................................................................. 173
Fig 5.19.Block diagram of Get Weather application .................................................................................. 176
Fig 5.20. Get Weather Application Console Window ................................................................................. 176
Fig 5.21. Flow Chart of getting weather application ................................................................................... 177
Fig 5.22 Flowchart for configuring a static IP address for CC3100 module .............................................. 178
Fig. 5.23. Flowchart for using CC3100 as a WLAN Station ....................................................................... 179
Fig. 5.24. Flowchart for configuring CC3100 as a HTTP Server ................................................................ 180
Fig 5.25 Block diagram of Smart Plug with WiFi connectivity .................................................................... 181
Fig 5.26 Flow chart of Smart Plug with Wi-Fi connectivity ......................................................................... 182

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List of tables
Table 1.1. ARM Architecture Features and Benefits ................................................................................... 20
Table 1.2. Processor mode with binary Pattern mode Control bits [4:0] ..................................................... 24
Table 1.3. Exceptions and attributes ........................................................................................................... 26
Table 1.5. Barrel shift operation syntax for data processing instructions. ................................................... 28
Table 1.6. Instruction set table ..................................................................................................................... 29
Table 2.1: Data types (ISO C90) ................................................................................................................. 57
Table 2.2: Data types (ISO C99) ................................................................................................................. 57
Table 2.3: General Bit wise operations ........................................................................................................ 58
Table 2.4: Development Tools for Tiva C Series ......................................................................................... 59
Table 2.5: Memory Mapping in TM4C123GH6PM Chip .............................................................................. 61
Table 2.7 Switches: RGB and GPIO pin connection to the microcontroller................................................. 69
Table 2.8: Clock setup for TM4C123GH6PM ............................................................................................. 70
Table 2.9 Interrupt Vector Table for ARM Cortex M4 .................................................................................. 74
Table 2.10: Power Modes of Tiva ................................................................................................................ 80
Table 3.1: General purpose Timer signals ................................................................................................... 88
Table 3.2 ADC signals with GPIO pins ........................................................................................................ 95
Table 3.3: Samples and FIFO Depth of Sequencers ................................................................................... 96
Table 4.1: RCG12C Register Description .................................................................................................. 135
Table 4.2. TPR Values for I2C modes ........................................................................................................ 136
Table 4.3: TPR Values for High-Speed Mode ........................................................................................... 136
Table 4.4: I2CMCR Register Description ................................................................................................... 136
Table 4.6: RTC Control Register Description ............................................................................................ 141
Table 4.7. SPI Modes ................................................................................................................................ 144
Table 4.8: SPI. Pins Mux Utility.................................................................................................................. 145
Table 4.9: SPI Modules base address ....................................................................................................... 146
Table 4.9. SSICRO Register Description ................................................................................................... 147
Table 4.10: SSI Status Register Description ............................................................................................. 148
Table 4.11. SSI Interrupt Mask Register .................................................................................................... 149
Table 5.1: Wi-Fi features............................................................................................................................ 174

Foreword
In the present world, we are getting tech friendly. It has been observed that in our day to day life, we
interact with several systems which makes our life simpler and easier. From mobile phones, washing
machines, wrist watches to space craft‟s, submarines space rovers, automotive etc., everything relies
on design and development of such intelligent systems. These systems are smart enough to interact
with physical environment by themselves and act according to the conditions or information feed on
them.
Although, the embedded systems is not standalone technology, but the combination of various
technologies wisely implemented all together to develop an electronic product which could be user
friendly and could be adopted by the specific community depends on their needs. The functioning of
such gadgets and systems depends several aspects like the central processing unit capacity, inbuilt
memory and the input output devices connected to it. The devices connected are basically sensors
and actuators which could be analog or digital in nature. To make then compatible and synchronized
the developer need to choose the interfacing accordingly.
As it is clear now that, do develop such systems there is a need to understand the processing
elements and the way to address the desired function. The current adaptation of ARM architectures in
the modern controllers and processor is growing rapidly. The good reason behind that is scalability,
compatibility, energy efficiency and user friendliness offered by them. This book focus on ARM Cortex
–M family which is widely accepted by majority of manufactures and OEM‟s (Original Equipment
Manufacturers).
The Texas Instruments TIVA board or widely known as TIVA C series, is a high performance, cost
efficient device, having an ARM Cortex-M4 architecture. The board is used for code testing and
optimization. All the codes mentioned in this book can be executed on it.
In the current demanding environment, it is expected to get the hand on experience as soon as
possible, but it is hard to find a single source of information which can serve the purpose. The intention
to design this book is to help the researchers, students and embedded systems enthusiast, to
understand the basic principle of micro controllers, peripherals, embedded programing and interfacing
techniques with the help of practical application, which not only helps to develop the basic theoretic
concepts but also to observe how the processing unit handles the operation internally.
Considering current scenario, Embedded Systems curriculum requires an application and System
Design approaches balancing the performance, connectivity requirements and system cost with an eye
on power. This book is designed to inculcate this perspective in students using Cortex-M4 based TIVA,
an industrial standard hardware platform. This book helps in understanding 32-bit architecture and its
programming consideration using C language. The later part is focused on programming various inbuilt
features of the platform with a more focused approach on analog and digital interfacing concepts and
related protocols. Embedded systems, whether they are standalone or networked, needs various
communication interfaces and standards so that they communicate and process data from the external
world. This book covers topics on how to connect the device to external peripherals including those
need interconnectivity. Unit 5 of the book focuses on key wireless technologies that are the backbone
of Internet of Things. Implementing Wi-Fi capability in microcontroller is necessary to develop Internet
enabled products and IoT applications.
The under graduate curriculum implemented in most of the Universities related to Embedded Systems
Design, are not adequate to develop the necessary design skill needed at present. There is a wide gap
between the industry requirements and the design skill of students coming out from the university. The
purpose of developing new curriculum for the above-mentioned subject is to reduce the gap between
the requirements of the industry and the design skill of graduates coming out of the University.

Foreword www.ti.com
Expected Outcomes:
 It will help the teachers to teach the subject easily and make the students to learn the
subject in the class itself.
 A systematic exposure of the subject will motivate the students to develop expertise in the
system design. Students will gain confidence in system design.
 The gap between the design skill earned by the students and the Industry requirements will
get reduced.

Chapter 1
Embedded Systems and Features
The purpose of this book is to help beginners understand key concepts related to embedded system design
based on TIVA boards from Texas Instruments.
At the end of chapter 1, students should be able to recognize an embedded system and distinguish its
features from a general purpose computing system. This chapter covers basic hardware components
required to design an embedded system.
Readers will be able to acquire strong fundamental knowledge and develop skills for applications of core
knowledge on embedded system design. They will also acquire thorough knowledge on a mainstream
computing unit i.e. ARM processor with its basic architecture, programming considerations and different
architecture versions.
This chapter will guide readers on the parameters to select an appropriate ARM processor for specific
applications; enhanced features of ARM Cortex M4 core and how it differs from the basic ARM core. The
chapter also covers industry standard TIVA TM4C123X and TM4C129X, ARM Cortex M4 based platforms
and various applications that can be developed using these boards.
Topic Page
1.1 Introduction.......................................................................................................................................... 13
1.2 ARM Architecture ................................................................................................................................ 20
1.3 Summary ............................................................................................................................................. 53
1.4 Review Questions ............................................................................................................................... 54
12 Embedded Systems and Features

www.ti.com Introduction
1.1 Introduction
We live in an era where pervasive computing exists everywhere, right from a small handheld device
such as a mobile phone to the electronic control units within automobiles or avionics. Today, large
volumes of information is getting processed and communicated over the Internet every microsecond.
Buzz words such as Cloud Computing, Big Data Mining and Internet of Things are everywhere.
There are two broad classifications of computing systems - general purpose computing system and
embedded computing systems. If we define these in simple words, general purpose computing
systems are those used in desktop or laptop computers, which can process several different
applications. An embedded system refers to any device that has some computational intelligence in it.
It is generally used as a standalone system that repeatedly performs a specific task or as part of a
large system to perform multiple tasks with the requisite hardware and software embedded within.
Systems used in printers, washing machines, mp3 players, CT scan machines etc. are great examples
of embedded systems.
An embedded system is a constrained system and its design goals vary from a general purpose
system. The constraints are: high performance, low power consumption, small size and low cost of the
system.
The basic components of an embedded system include hardware, software and some mechanical
parts. Embedded hardware includes a processing unit, block of memory and I/O sub-unit which are
called as the system resources. The embedded software can be thought of as the application software
in a small computing system or both the system and the application software in case of a large
complex system. The system software mentioned here is the real time operating system (RTOS) used
to manage the usage of system resources by application software.
Embedded systems are used in every walk of life. Some of its application domains are: avionics,
automotives, industrial control, medical instrumentation, communication, networking, consumer
products, handheld electronic gadgets, surveillance, robotics system etc.
This chapter covers introduction of embedded systems with the basic functional blocks. It provides an
overview of the ARM processor core as a main computing element. The programmer‟s model of ARM7
processor is presented along with various operating modes of ARM core. The interrupt and exception
handling capabilities of ARM are also explained. The basic instruction set architecture is presented
with all its features. The next section introduces migration to ARM Cortex series of processors. In this
text book, Texas instruments TIVA development board is introduced with TIVATMTM4C123X and
TIVATMTM4c129X microcontrollers. These TI platforms are on Cortex-M4 core. So Cortex-M4
architecture with its programming model, operating modes and instruction set are introduced in the
subsequent sections.
1.1.1 Hardware Components of Embedded System

The basic hardware components of an embedded system shown in a block diagram in Fig 1.1
These include the processing unit, sensors and actuators, ADC, DAC, I/O unit and the memory block.
The processing unit could be a microprocessor, a microcontroller, FPGA i.e. field programmable gate
array or ASIC (Application Specific IC) depending on the application requirements.
Sensors such as sound sensor, ambient temperature sensor, motion sensor etc. are generally analog
in nature since they sense the data from outside world. This data is converted from analog to digital
and sent to a processing unit, post which required action is performed by actuators
Embedded Systems and Features 13

Introduction www.ti.com
Fig 1.1. Basic block diagram of an embedded system

Processing Unit
The processing unit could be a microprocessor, a microcontroller, embedded processor, DSP, ASIC or
FPGA selected for an embedded system based on the application requirements.
This processing unit executes the application program that is saved in the program memory ROM
(read only memory). The RAM (random access memory) is used as the data memory to hold the
system stack and the variables used in the program.
Stack is a portion in the RAM reserved to hold back the status of the program when the control is
transferred by a branch instruction. To make a system interactive, input-output (I/O) unit is required.
The memory block and the I/O units communicate with the processing unit through the system bus.
The system bus consists of three different bus systems: address bus, data bus and control bus.
Processor sends the address of the destination through the address bus. So address bus is
unidirectional from processor to the external end. Data can be sent or received from any unit to any
other unit in the diagram.
So data bus is bidirectional. Control bus is basically a group of control signals from the processing unit
to the external units

Fig 1.2. Processing Unit and System Bus

Microprocessor
Microprocessor is a programmable digital device which has high computational capability to run a
number of applications in general purpose systems. It does not have memory or I/O ports built within
its architecture. So, these devices need to be added externally to make a system functional. In
embedded systems, the design is constrained with limited memory and I/O features. So
microprocessors are used where system capability needs to be expanded by adding external memory
and I/O.
Microcontroller
A microcontroller has a specific amount of program and data memory, as well as I/O ports built within
the architecture along with the CPU core, making it a complete system. As a result, most embedded
systems are microcontroller based, where are used to run one or limited number of applications.
Embedded Processor
Embedded processors are specifically designed for embedded systems to meet design constraints.
They have the potential to handle multitasking applications. The performance and power efficiency
requirements of embedded systems are satisfied by the use of embedded processors.
DSP
Digital signal processors (DSP) are used for signal processing applications such as voice or video
compression, data acquisition, image processing or noise and echo cancellation.
ASIC
Application specific integrated circuit (ASIC) is basically a proprietary device designed and used by a
company for a specific line of products (for example Samsung cell phones or Cisco routers etc.). It is
specifically an algorithm called intellectual property core implemented on a chip.
FPGA
Field programmable gate arrays (FPGA) have programmable macro cells and their interconnects are
configured based on the design. They are used in embedded systems when it is required to enhance

the computational capability of the existing system or to make a system reprogrammable and
reconfigurable when the need arises.
Memory Block
The memory block consists of program and data memory. ROM is used as the program memory and
RAM is used as the data memory. There are two memory architectures: Harvard and Von-Neumann.
In Harvard architecture, the program and data memories are segregated with separate address and
data bus drawn to each. So there can be parallel access to both and performance of the system can
be improved at the cost of hardware complexity. On the other-hand, the Von-Neumann architecture
has one unified memory used for both program and data. The system is comparatively slower, but the
design implementation is simple and cost effective for an embedded system. Various ROM and RAM
devices are used in embedded systems based on the applications.
(a) (b)
Fig 1.3. (a) Harvard Architecture and (b) Von-Neumann Architecture

ROM
Read only memory (ROM) is non-volatile i.e. it retains the contents even after power goes off. It is
used as the program memory. In embedded systems, the application program after being compiled is
saved in the ROM. The processing unit accesses the ROM to fetch instructions sequentially and
executes them within the CPU. There are different categories of ROM such as: programmable read
only memory (PROM), erasable programmable read only memory (EPROM), electrically erasable
programmable read only memory (EEPROM) etc. There is also flash memory which is the updated
version of EEPROM and extensively used in embedded systems.
RAM
Random access memory (RAM) is volatile i.e. it does not retain the contents after the power goes off.
It is used as the data memory in an embedded system. It holds the variables declared in the program,
the stack and intermediate data or results during program run time. The Processing unit accesses the
RAM for instruction execution to save or retrieve data. There are different variations of RAM such as:

static RAM (SRAM), dynamic RAM (DRAM), pseudo static RAM (PSRAM), non-volatile RAM
(NVRAM), synchronous DRAM, (SDRAM) etc.
Fig 1.4: Interconnection of RAM with Microprocessor

I/O Unit
Embedded systems have to interact with the external environment through the input/output devices.
Input Device
Embedded systems receive user commands from input devices such as keypad, switch or a touch
screen device at the input port. The processing unit executes software instructions to process these
inputs to make decisions that further guide the operation of the system. A port is a termination point
that gives connectivity between the processing unit and the peripherals.
Output Device
Output devices are used to display results from the system or to sending data to another connected
system at the output port. Some examples of output devices are: light emitting diodes (LEDs), liquid
crystal diodes (LCDs), printers etc.

Fig 1.5. Interconnection of external devices with Microprocessor

I/O Communication Bus
I/O communication buses and protocols are used to communicate with the slower I/O devices. There
are two communication methods used in any system: serial communication and parallel
communication. Some of the communication protocols are: universal serial bus (USB), inter-
intergrated circuit (I2C), serial peripheral interface (SPI), peripheral component interconnect (PCI), IBM
standard architecture (ISA) etc. Each protocol defines a standard way of communication between the
devices. The features and usage of these protocols have been explained in subsequent chapters.
Sensors & Actuators
Sensors and electromechanical actuators are input and output devices used in real time embedded
systems to exchange real time data between the system and the external environment. Sensors
measure physical parameters such as temperature, pressure acceleration, proximity etc. being
connected at the system input ports through analog to digital converters (ADCs). Some of the
actuators used in embedded systems are: motor speed controllers, stepper motor controllers, relays
and power drivers etc. Actuators are connected at the system output ports through the digital to analog
converters (DACs).
An example of an embedded system
Here is a simple application to introduce a small embedded system – a stepper motor controller for a
robotics system. The stepper motor mentioned here is an electromechanical device that rotates in
discrete step angles when electrical pulses are applied to it. Suppose in an industrial environment, a
robot arm is employed to pick-up components from one container and deposit to another container.
The robot arm is operated by three stepper motors, one to move the arm from one container to the
other and other two to make a grip to tightly hold the component. To control these stepper motors, a
small embedded system can be designed as shown in Fig 1.6. The hardware components are a
microcontroller, three stepper motors and a robot arm. To make this system functional, three program
modules are required.
 Module1 for the stepper motor1 to rotate counter clockwise with definite angle so that robot arm
can move from container1 to container 2 also to rotate clockwise to move back to container1
when the component is picked.

 Module 2 for the stepper motors 2 & 3 to make the motor 2 to rotate in counter clockwise and
motor 3 to rotate in clockwise both simultaneously so that the robot arm can pick and make a grip
on the component.
Fig 1.6. Stepper motor control embedded system

1.1.2 Instruction Set Architecture
Instruction set can be defined as the communication interface between the processor and the
programmer. Every processor has its own instruction set implemented in the hardware to execute
instructions such as move, add or multiply data in a definite way. Programmers can either use any high
level language such as C, C++, Java etc. or assembly language to write the program. Accordingly, a
compiler or assembler can be used to translate the program into machine understandable language
following the processor instruction set. There are two classic architectures of instruction set
implementation, the complex instruction set computer (CISC) and the reduced instruction set computer
(RISC). Each has its own advantages and disadvantages. The CISC architecture has more complexity
in the hardware itself while RISC architecture offers more complexity to the software. The features of
each architecture are summarized as below.
Features of Complex Instruction Set Computer (CISC):
 Most of the instructions are complex in type.
 Instructions require multiple clock cycles for execution.
 More addressing modes are available in the instruction set.
 Fewer working registers and more frequent memory access.
 Load and Store operations are incorporated in instructions.
 High code density is achieved because of availability of multifunctional instructions.
 Pipeline implementation is difficult.
 More complexity is given to the hardware design.
Features of Reduced Instruction Set Computer (RISC):
 Most of the instructions are simple in nature.
 All the instructions are executed in single clock duration.
 The addressing modes available are fewer than in case of CISC.
 Instruction set has separate Load/Store architecture.
 Higher number of working registers so less frequent memory access.
 Most of the data transfer happens from register to register.

ARM Architecture www.ti.com
 Large code size compared to CISC architecture.

 Performance of RISC architecture is always better than CISC architecture.
 Pipeline implementation is easier compared to CISC.
 More complexity is offered to the compiler design.
1.2 ARM Architecture

ARM cores are designed specifically for embedded systems. The needs of embedded systems can be
satisfied only if features of RISC and CISC are considered together for processor design. So ARM
architecture is not a pure RISC architecture. It has a blend of both RISC and CISC features.
Table 1.1. ARM Architecture Features and Benefits
Features Benefits to embedded system

High Performance Ensures the system has a fast response
Low power consumption Makes the system more energy efficient
Low silicon area Reduces the size and also consumes less power
High Code density Helps embedded system to have less memory footprint
Used to load data from the memory to the ARM CPU register or store data
Load/store architecture from the CPU register to the memory; enables the memory access when
required
Register bank with large number Required to perform most of the operations within the CPU and provides
of working registers faster context switch in a multitasking applications
Fig 1.7. ARM 7 Architecture [an excerpt from Google image]

www.ti.com ARM Architecture
1.2.1 A Basic architecture of the ARM7core

ARM 7, the basic architecture of ARM series of cores, is introduced here in this section. A brief
introduction about each functional block of the architecture of ARM7 core shown in Figure.1.2 is
presented below.
The Register Bank has sixteen general purpose registers (R0-R15) and a current program status
register (CPSR) which are accessible by user applications. In addition to that, it has twenty numbers of
banked registers specifically used for different operating modes of ARM core. These are invisible to
user applications. The register bank has two read ports to read operand1 and operand2 and one write
port to write back the result of operation to the any register specified in the instruction. It has an
additional bidirectional port to update the program counter with address register and incrementer.
Address register content is incremented at every sequential byte access by the incrementer but the
program counter is incremented by four in ARM state of the core or is incremented by 2 in Thumb state
of the core at every instruction access. ARM and Thumb states of the core are discussed in section
1.3. Address register is directly connected to the address bus.
 The barrel shifter can shift or rotate operand 2 by specified number of bits prior to arithmetic or
logic operations.
 The 32 bit ALU performs the arithmetic and logic functions.
 The data in and data out registers hold the input and output data from and to the memory.
 The instruction decoder and associated control logic generates appropriate control signals for
the data path after decoding the fetched instruction.
 The MAC unit is to multiply two register operands and accumulate with another register
holding the partial sum of the products.
The encoded instruction byte of the program saved in the code memory is fetched through the data
bus and first enters into the data-in register of the ARM architecture from where it is delivered to the
instruction decoder. After the instruction is decoded, appropriate control signals are generated for the
data path. The required registers are activated in the register bank and the operands flow out from two
read ports of register bank to the ALU: operand1 through A-bus and operand2 through B-bus after
preprocessing at barrel shifter. The result of operation at ALU is written back to the result register
through a write port at register bank. For Load/Store instructions, after decoding the instruction, the
data memory address is first calculated at ALU as specified in the instruction and the pointer register is
updated at the register bank. The address in the pointer register is given to the address register to
access the memory and transfer data. If it is a load multiple or store multiple instruction, the core does
not halt before completing the required number of data transfers unless it is a reset exception.
1.2.2 Registers
Registers are for temporary data storage within processor architecture. As shown in Fig.1.8, ARM
processor has sixteen numbers of general purpose registers, R0-R15 and a current program status
register (CPSR) defined for user mode of operation. Each of these registers is of 32-bits. Out of these
registers, R13, R14 and R15 have special purposes.
R13: Used as the stack pointer that holds the address of the top of the stack in the current processor
mode.
R14: Used as the link register that saves the content of program counter on control transfer due to the
occurrence of exceptions or using the branch instructions in the program.
R15: Used as the program counter that points to the next instruction to be executed. In ARM state, all
instructions are of 32-bits (four bytes) for which, PC is always aligned to a word boundary. This means
that the least significant two bits of the PC are always zero. The PC can also be halfword (16-bit)
aligned for Thumb state (16 bit instructions) or byte aligned for Jazelle state (8-bit instructions)
supported by different versions of ARM architecture.

Fig 1.8. User mode register set
1.2.3 Current Program Status Register (CPSR)
Fig 1.9. A generic CPSR Format

CPSR, a 32-bit status register, holds the current state of the ARM core. As shown in Fig 1.4, the
register is divided into four different fields- flags, status, extension and control; each of 8-bits. The flag
field has the bit specification for four condition flags; N, Z, C and V and is used for arithmetic and logic
instructions.
 N-(Negation flag) = 1 indicates negative result from ALU.
 Z- (Zero flag) = 1 indicates zero result from ALU.

 C- (Carry flag) = 1 indicates ALU operation generated carry.

 V- (Overflow flag) =1 indicates ALU operation overflowed.
Most of the ARM instructions are conditionally executed. Based on the status of these condition flags,
condition codes are used along with instruction mnemonics to control whether or not the instruction
will be executed. Status and extension fields are reserved for future usage. In the control field, the
least significant five bits are used to save the modes of operation of ARM core. Processor mode can
be changed by directly modifying these control bits. The most significant three bits I, F and T have
significance as below:
 I = 1 indicates IRQ is disabled

0 indicates IRQ is enabled.
 F = 1 indicates FIQ is disabled

0 indicates FIQ is enabled.
 T= 1 indicates the Thumb state is active.

0 indicates ARM state is active.
These are processor specific features and are explained in detail in section 1.4.
1.2.4 Operating States

There could be three operating states of the ARM core depending on the implementation. These are
specified as ARM, Thumb and Jazelle. Correspondingly there are three instruction sets. The state of
the core determines which instruction set is currently used for execution. The status of Thumb T bit in
the CPSR register indicates whether the core is in ARM or Thumb state as explained in the previous
section. Similarly bit 24 of CPSR register reflects the status of Jazelle state if it is there in the
implementation. In ARM state, the core executes all 32 bits instructions. When core enters to Thumb
state, it executes all 16 bits Thumb instructions. In Jazelle state, instructions length is 8 bits only.
Since in Thumb and Jazzel state, the instructions lengths are reduced to half or one fourth of ARM
instruction length, high code density is achieved by using those states. So frequently called functions
are written in Thumb states to reduce the program length.
1.2.5 Operating Modes

ARM core has seven operating modes basically used to isolate users programs from the protected
memory or OS services. The operating modes are: user, system, fast interrupt request (FIQ), interrupt
request (IRQ), abort, supervisor and undefined mode. Out of these, only user mode is unprivileged,
remaining six are privileged modes. The basic difference between privileged and unprivileged mode is
the access permission to protected area of the memory and write access permission to CPSR_c given
to only privileged modes. All application programs run in user mode. All operating system kernel
functions and services run in system or supervisor mode. After reset, core enters to supervisor mode.
FIQ mode is for interrupt requesting faster response and low latency and IRQ mode correspond to the
low priority interrupt available on the processor itself. Processor enters abort mode to handle memory
access violation. In the execution flow, when processor encounters an instruction that is not supported
by the instruction set implementation, it enters to undefined mode. All exceptions are handled in
privileged modes. Privileged modes have complete read and write access to both flags and control
fields but unprivileged user mode has only read access to the control field while both read and write
access to the flags field. Processor mode is changed automatically by the occurrence of exceptions or

by modifying the control bits of CPSR by writing its binary pattern as shown in table 1.1, being in a
privileged mode.
Table 1.2. Processor mode with binary Pattern mode Control bits [4:0]
Abort (abt) 10111

Fast interrupt request( fiq) 10001
Interrupt request (irq) 10010
Supervisor( svc) 10011
System (sys) 11111
Undefined(und) 11011
User( usr) 10000
1.2.6 Programming Model

Programming model of a processor is basically a set of working registers used to perform the
operations defined in its instruction set. ARM programming model has total 37 registers in its register
bank which are segmented for different modes of operation as shown in Fig 1.10.User mode register
set is shared by the system mode also.
Each of the remaining privileged modes has a set of banked registers which are active and accessible
to the programmer only when the core enters to the corresponding mode. Banked registers for a
particular mode are physical replication of few of the user mode registers along with a saved program
status register (SPSR) shown by shading in the figure.
If the processor mode is changed, for example from user to FIQ mode due to occurrence of hardware
interrupt (fiq), the banked registersR8-R14 from the FIQ mode will replace the corresponding registers
in user mode but the remaining user mode registers (R0-R7) can still be used in FIQ mode after saving
the previous contents.
It means registers R8-R14 of user mode are unaffected by this mode change. The purpose of these
banked registers is to reduce the context saving overhead. There is only one dedicated PC (R15) and
one CPSR for all the operation modes.
When a mode is changed, the PC and CPSR contents are saved in the link register (R14) and SPSR
of the new mode respectively. While returning back to previous mode, special instructions are used to
restore back the saved register contents. There is no SPSR available in user mode and one important
feature is that, when a mode change is forced, CPSR content is not saved in SPSR. It happens only
when exception occurs.

Fig 1.10. Complete Register Bank
1.2.7 Interrupt and Exception Handling

Interrupt and exception handling mechanisms are used by any processor to respond to the I/O request
or when CPU intervention is required to handle any error that may occur during program execution.
CPU becomes forced to stop the normal execution to respond to the exception or interrupt at a faster
rate. ARM core supports seven exceptions including the hardware interrupts.
1.2.7.1 Interrupt Handling

Interrupt is used to get service from CPU by generating a request only when it is required. Two types
of interrupts are: hardware interrupt and software interrupt. Hardware interrupt comes from the
peripherals or I/O‟s connected in a system and software interrupt by executing an interrupt instruction.
When any interrupt occurs during program execution, CPU completes the current instruction
execution, saves the return address in the defined portion of the memory called the stack and then
responds to the interrupt. The control of program execution is transferred to the corresponding
interrupt vector address where interrupt service routine (ISR) is written. At the end of ISR execution,
the return address is retrieved from the stack and control resumes back at the address where it had
left. ARM core has two hardware interrupts FIQ and IRQ but those are considered also as exceptions
since core follows the same process of handling both interrupts and exceptions.
1.2.7.2 Exceptions Handling

An exception is any condition, an unexpected event or error that needs to halt the normal execution of
instructions. ARM core considers hardware interrupts under exceptions. It supports seven exceptions
as follows: reset, data abort, prefetch abort, FIQ, IRQ, SWI and undefined. Each of the ARM
exceptions is associated with certain operating mode and causes the ARM core to enter to that
particular mode automatically on exception entry. In the group of exceptions, there are supervisor calls
such as reset and software interrupts (SWI), undefined instruction trap, memory access failure such as
data abort and prefetch abort and hardware interrupts such as fast interrupt request (FIQ) and interrupt

request (IRQ). As more than one interrupt may occur simultaneously, exceptions are prioritized. In the
priorities list given in the table.2, the SWI and undefined exceptions have same priority as they are
mutually exclusive because both are caused by an instruction entering the execution stage. When any
exception occurs, the control transfers to the corresponding vector address. In the vector address,
certain branch instruction would be written to access the actual interrupt handler or ISR saved at a
different location. It is required as the vector addresses are sequentially separated by four bytes, only
one 32-bit ARM instruction can be written at each of it. The I and F bits in the control field of CPSR
register are disabled in combination while handling the exceptions. All the ARM exceptions are
executed in ARM state of the core. If the control is there in Thumb state it has to switch back to ARM
state to handle the exception. Table 1.2 gives information about all the attributes discussed here.
Table 1.3. Exceptions and attributes
Vector Address
Exceptions Operation Modes Priority I-bit in CPSR F-bit in CPSR
Low/High
Reset Supervisor 1 1 1 0x00000000/0xffff0000
Undefined Undefined 6 1 0 0x00000004/0xffff0004
SWI Supervisor 6 1 0 0x00000008/0xffff0008
Prefetch Abort Abort 5 1 0 0x0000000C/0xffff000C
Data Abort Abort 2 1 0 0x00000010/0xffff0010
IRQ IRQ 4 1 0 0x00000018/0xffff0018
FIQ FIQ 3 1 1 0x0000001C/0xffff001C
Exception Entry
When an exception occurs, ARM core goes through the following sequence of operations.
 It changes to the operating mode corresponding to the particular exception.
 It saves the return address, the content of PC (r15) in lr( r14) of the new mode.
 It saves the previous state of the core, the content of the CPSR in the SPSR of the new mode.
 It disables IRQs by setting bit 7 of the CPSR and, if the exception is a reset or fast interrupt,
disables further fast interrupts by setting bit 6 of the CPSR.
 PC is loaded with the vector address to begin executing the relevant exception handler.
Exception Exit
The user program is resumed once the interrupt handler execution is completed. The following steps
are followed in doing so.
 The saved context must be restored back from the handler's stack.
 The CPSR must be restored from the appropriate SPSR.
 The PC must be restored back from the link register of exception mode.
1.2.8 ARM Instruction Set

In any processor architecture, an instruction includes an opcode that specifies the operation to
perform, such as add contents of two registers or move data from a register to memory etc, with
specified operands, which may specify registers, memory locations, or immediate data. Instruction set
of a processor gives information about the instructions, addressing modes and the timing requirement
for the execution of each instruction. The instruction set is always specified by the processor designer.
Every processor implements its instruction set in the architecture. ARM Ltd being the processor core
designer and not the silicon manufacturer, it defines the instruction set to be implemented by the chip
manufacturers.
Features

ARM architecture has two instruction sets. The ARM instruction set and Thumb instruction set. In ARM
instruction set, all instructions are 32 bits wide and are aligned at 4-bytes boundaries in memory. On
the other hand, in thumb instruction set, all instructions are of 16 bits wide and are aligned at even or
two bytes boundaries in memory.
 The important features of the ARM and Thumb instruction set are:
 Most of the instructions are executed in one cycle.
 Load/Store architecture for accessing data from external memory with powerful auto-indexing
addressing modes.
 Inclusion of load and store multiple register instructions.
 3-address instructions: two source operand registers and the result register are all distinctly
specified.
 Data processing instructions act only on registers.
 Every instruction can be conditionally executed which improves the performance and code
density by reducing the number of branch instructions.
 The ability to execute a barrel shift operation and an ALU operation of a single complex
instruction in a single clock cycle.
 Inclusion of advanced DSP instructions in the ARM instruction set for the multiply and
accumulate (MAC) unit replaces the need of separate digital signal processor.
 Implementation of coprocessor instruction set with extension of the programming model.
 The Thumb instruction set is 16-bit compressed representation of the ARM instructions that
provides high code density.
ARM Instructions can be categorized into following broad classes:
 Data movement instructions
 Data Processing Instructions
o Arithmetic/logic Instructions
o Barrel shifting instructions
o Comparison Instructions
o Multiply Instructions
 Branch Instructions
 Load and store Instructions
o Load and Store register instruction
o Load and Store multiple register instructions
o Stack instructions
o Swap register and memory content
 Program Status register Instructions
o Set the values of the conditional code flag
o Set the values of the interrupt enable bit
o Set the processor mode
 Exception generating Instructions
o Software Interrupt Instruction
o Software Break Point instruction
1.2.8.1 Barrel Shifter

A unique and powerful feature of the ARM processor is the ability to shift or rotate the data in one of
the source registers by a specific number of positions before it enters the ALU, which increases the
functionality of many data processing operations.
Two operands are accessed from the register bank for data processing instructions as shown in Fig
1.11. Operand1 comes on the A-bus straight way to the ALU and operand2 comes on the B-bus is
preprocessed at the barrel shifter before entering to ALU. The barrel shifter is a combinational logic
unit that shifts or rotates the data as it is specified in the instruction. Then ALU performs the arithmetic

or logic operation on these operands and the result is written back into the register bank through the
ALU bus. Both the barrel shifting and ALU operations happen in the same instruction cycle.
The data processing instructions that do not use the barrel shift are: the MUL (multiply), CLZ (count
leading zeros), and QADD (signed saturated 32-bit add) instructions.
Fig 1.11. Barrel Shifter with ALU

Table 1.4 Barrel Shifting Operations
Mnemonic Description Shift Result
LSL Logical shift left xLSLy x<<y
LSR Logical shift right xLSRy (Unsigned)x>>y
ASR Arithmetic right shift xASRy (signed)x>>y
ROR Rotate right xRORy ((unsigned)x>>y) | (x<<(32 − y))
RRX Rotate right extended xRRX (c flag<<31) | ((unsigned)x>>1)
*Rm is operan2 in data processing operations.
Table 1.5. Barrel shift operation syntax for data processing instructions.
Shift Operations Syntax
Logical shift left „Rm‟ by shift immediate value Rm, LSL #shift_imm
Logical shift left„Rm‟ by the amount in register „Rs‟ Rm, LSL Rs
Logical shift right „Rm‟ by shift_ immediate value Rm, LSR #shift_imm
Logical shift right „Rm‟ by the amount in register „Rs‟ Rm, LSR Rs
Arithmetic shift right „Rm‟ by shift immediate value Rm, ASR #shift_imm
Arithmetic shift right „Rm‟ by register „Rs‟ Rm, ASR Rs
Rotate right „Rm‟ by shift immediate value Rm, ROR #shift_imm
Rotate right „Rm‟ by the amount in register „Rs‟ Rm, ROR Rs
Rotate right „Rm‟ with extend Rm, RRX

Example: Let the data in R1= 0X00000080, R2 = 0X00000004 and R3=0X000000FF

After executing the instruction MOV R3, R1, LSR R2
Data in R3= 0X00000008, R1=0X00000080 and R2= 0X00000004
Description:
 The data in register R1 is logically right shifted by the data that is there in R2.Which means
(0X00000080) >> (0X00000004). It becomes 0X00000008.
 Move this value to register R3. So R3=0X00000008 now. But data in R1 and R2 remain
unchanged.
Table 1.6. Instruction set table
Instruction Mnemonic Description Example Working
1. Data Movement instructions
Syntax: <instruction>{<condition>}{S} Rd, N

MOV r1, r2, LSL
MOV Move a 32-bit value into a register Move (r2<<4) to r1.
#4
Move the NOT of the 32-bit value into a
MVN MVN r1, r3 Move (~ r3) to r1.
register
2. Data Processing instructions
i. Arithmetic Instructions; Syntax:<instruction>{<cond>}{S} Rd, Rn, N

ADC Add two 32-bit values and carry ADC r1, r2, r3 r1= r2+r3+Carry
ADD r4, r5, r3, r4= r5+
ADD add two 32-bit values
LSR # r1 (r3>> by r1)
Reverse subtract with carry of two 32-bit r3= r1- r2 -
RSC RSC r3, r2, r1
values ! Carry
RSB Reverse subtract of two 32-bit values RSB r3, r2, r1 r3= r1- r2
SBC Subtract with carry of two 32-bit values SBC r2,r4, r6 r2=r4-r6- !Carry
SUB Subtract two 32-bit values SUB r2,r4, r6 r2=r4-r6
ii. Logical Instructions; Syntax:<instruction>{<cond>}{S} Rd, Rn, N
AND logical bitwise AND of two 32-bit values AND r7, r5, r2 r7= r5 & r2
ORR r6, r4, r1,
ORR logical bitwise OR of two 32-bit values r6= r4 | (r1>>r2)
LSR r2
EOR logical exclusive OR of two 32-bit values EOR r5, r1, r2 r5= r1 ^ r2
BIC logical bit clear (AND NOT) BIC r3, r1,r4 r3= r1 & ~ r4
iii. Comparison Instructions; Syntax:<instruction>{<cond>} Rn, N
Flags set as results
CMN Compare negated CMN r1, r2
of r1+r2
CMP Compare CMP r1, # 0XFF
of r1-0XFF
TEQ Test for equality of two 32-bit values TEQ r3, r5
of r3 ^ r5
TST Test bits of a 32-bit values TST r1, r2
of r1& r2
IV. Multiply Instructions; Syntax:MLA{<cond>}{S} Rd, Rm, Rs, Rn; MUL{<cond>}{S} Rd, Rm, Rs
MLA Multiply and accumulate MLA r1,r2,r3,r4 r1=(r2*r3)+r4
MUL Multiply MUL r3, r7, r6 R3= r7*r6

3. Branch instructions
Syntax: B{<cond>} label; BL{<cond>} label; BX{<cond>} Rm; BLX{<cond>} label | Rm

B Branch B label PC= label
PC=label and
Lr= Address of the
BL Branch with link BL label
next instruction after
BL.
PC=r5 & 0Xfffffffe
BX Branch exchange BX r5
and T= r5 & 1
PC=r6 &
0Xfffffffe, T=r6 & 1
BLX Branch exchange with link BLX r6 and lr= address of
the next instruction
after BLX.
4. Load/Store Instructions
I. Single register transfer; Syntax:<LDR|STR>{<cond>} Rd, Address

Load r0 with the
LDR content of memory
LDR Load register from memory
r0, [r2, #0X8] address pointed to
by [r2+0X8]
Store r1 into the
memory address
STR
STR Store register to memory pointed to by r4 and
r1, [r4], #0X10
update r4 by
[r4+0X10]
II. Multiple register transfer; Syntax:<LDM|STM>{<cond>}<addressing mode> Rn{!},{registers};
Addressing modes: IA-Increment after; IB-Increment before; DA-Decrement after; DB-Decrement before:-
Increment or decrement the memory pointer after or before the data transfer.
r2=[r6];
LDMIA r3= [r6+4];
LDM Load multiple registers from memory
r6!, {r2-r4} r4=[r6+8] and
update r6 by [r6+12]
[r1-4]=r5
[r1-8]=r4
STMDB
STM Store multiple registers to memory [r1-12]=r3 and
r1!, {r3-r5}
update r1 by
[r1-12}
III. Stack Operations ; Syntax:<LDM|STM><addressing mode> SP{!},{registers};

Addressing modes: FA-Full ascending ; FD-Full descending ;EA-Empty ascending ;ED –Empty descending;
r1= [Sp+4]
r2= [Sp+8]
Load multiple registers from stack LDMED
LDM r3= [Sp+12] and Sp
memory Sp!, {r1, r3}
is updated by
[Sp+12]
[Sp-4]= r6
[Sp-8]= r5
STMFD
STM Store multiple registers to stack memory [Sp-12]=r4 and
Sp!, {r4,r6}
Sp is updated by
[Sp-12]
IV. Swap instruction ; Syntax: SWP{B}{<cond>} Rd,Rm,[Rn]
SWP swap a word between memory and a SWP/SWPB Load a 32 bit word

register r0, r1, [r2] or a byte from the

memory address in
r2 into r0 and store
swap a byte between memory and a the data in r1 to the
SWPB
register memory address in
r2.
5. Program status register instructions
MRS{<cond>} Rd,<cpsr|spsr>;MSR{<cond>} <cpsr|spsr>_<fields>,Rm
MSR{<cond>} <cpsr|spsr>_<fields>,#immediate
Move the content of cpsr or spsr to a Move the content of
MRS MOV r1, CPSR
register. CPSR register to r1.
Update the flag field
Move an immediate data or register to a
MSR MSR CPSR_f, r1 of CPSR by the
specific field of cpsr or spsr.
content in r1.
6. Exception generating instructions
Software interrupt instruction ; Syntax: SWI{<cond>} SWI_number (immediate 24 bit)

Software interrupt for an operating Execute software
system routine. interrupt at
SWI Change to Supervisor mode. SWI 0X123456 0X123456 in ARM
CPSR is saved in SPSR. state of the core.
Control branches to interrupt vector. T =0 in CPSR.
1.2.8.2 Addressing modes

Addressing mode is the way of addressing data or operand in the instruction. Every processor
instruction set offers different addressing modes to determine the address of operands. Some
fundamental addressing modes used by most of the processors are: register addressing, immediate
addressing, direct addressing and register indirect addressing. In register addressing mode, the
operand is held in a register which is specified in the instruction. In immediate addressing mode, the
operand is held in the instruction. In direct addressing mode, the operand resides in the memory
whose address is specified in the instruction. Similarly in register indirect addressing mode, the
operand is held in the memory whose address resides in a register that is specified in the instruction.
Section 1.8.1 gives a clear view of addressing modes supported by ARM instruction set.
1.2.8.2.1 ARM Addressing modes:

 Register Addressing: The operands are in the registers.
MOV R1, R2 // move content of R2 to R1 //
SUB R0, R1, R2 //subtract content of R2 from R1 and move the result to R0 //
 Relative Addressing: Address of the memory directly specified in the instruction.

Bsubroutine1// branch to suroutine1 //
BEQ LOOP // branch to LOOP if previous instruction sets the zero flag i.e, Z=1 //
 Immediate Addressing: Operand2 is an immediate value.

SUB R0, R0, #1// Save (R0 –1) to R0 //
MOV R0, #0xFF00 // Put 0xFF00 to R0 //

 Register Indirect Addressing: Address of the memory location that holds the operands there
in a register.
LDR R1, [R2]//Load R1 with the data pointed by register R2. //

ADD R0, R1, [R2]//add R1 with the data pointed by R2 and put the result into R0//
 Register Offset Addressing: Operand2 is in a register with some offset calculation.

MOV R0, R2, LSL #3 // (R2 << 3), then move to R0 //
AND R0, R1, R2, LSR R3// (R2 >> R3), logically AND with R1 and move result to R0 //
 Register based with Offset Addressing: Effective memory address has to be calculated
from a base address and an offset. Offset can be an immediate offset, register offset or scaled
register offset.
 Pre-Indexed Addressing
LDR R2, [R3, #0x0F] // Immediate offset.
// Take value in R3, add to 0x0F, use it as address and load data from that address to
R2 //
STR R1, [R0, -R2] // Register offset

// Use (R0-R2) as address of the memory and store data of R1 to that address.//
LDR R3, [R1, R2 LSR #8] // Scaled register offset//

// Use (R1+ (R2>>8)) as address and load the data from that address to R3. //
 Pre-Indexed with write back also called auto-indexing with pre-indexed addressing.
symbol indicates that the instruction saves the calculated address in the base address
register.
LDR R0, [R1, #4]! // Immediate offset //
// Use (R1+4) as address and load the data from that address to R0 and update R1 by
(R1+4)//
STR R1, [R2, R0]! // Register offset //

// Use (R2+R0) as address and store the data from R1 to that address. Update R2 by
(R2+R0) //
STR R3, [R1, R2 LSL #4]! // Scaled register offset //

// Use (R1+ (R2<<4)) as address and store the data from R3 to that address. Update
R1
by (R1+ (R2<<4)) //
 Post-Indexed also called auto-indexing with post-indexed addressing.

LDR R0, [R1], #4 // Immediate offset //
// Load the data pointed to by R1 to R0 and then update R1 by (R1+4). //
STR R1, [R3], R4 // Register offset //

// Store the data in R1 to the memory location pointed to by R3 and then update R3 by
(R3+R4)//
LDR R2, [R0], -R3, LSR #4 // Scaled register offset //

// Load the data from the address pointed to by R0 to R2 and then update R0 to (R0-
(R3>>4)). //

1.2.9 Migration to Cortex Series

In the path of architectural evolution, ARM has contributed many versions of IP cores to the embedded
computing world. ARM pioneered embedded products are excelling in every visible spectrum. Since its
inception, ARM has migrated over a long meaningful road map starting from v4T ARM7TDMI to v7
Cortex series of architectures achieving many strong milestones in between. It is currently the new era
of feature rich ARM Cortex series architectures truly empowering the embedded computing world.
1.2.9.1 ARM architecture evolution
Fig 1.12. Performance and capability graph of Classic ARM and Cortex embedded processors.

Fig 1.13. Performance and capability graph of Classic ARM and Cortex application processors.
ARM architecture has been improved a lot in the road map from classic ARM to ARM Cortex. Fig1.7
and fig187 depict the performance and capability comparison of classic ARM with embedded cortex
and application cortex series of processors. Even though ARM had earlier versions of products i.e. v1,
v2, v3 and v4, the classic group of ARM starts with v4T. The classic group is divided into four basic
families called ARM7, ARM9, ARM10 and ARM11.
 ARM7 has three-stage (fetch, decode, execute) pipeline, Von-Numann architecture where
both address and data use the same bus. It executes v4T instruction set. T stands for Thumb.
 ARM9 has five-stage (fetch, decode, execute, memory, write) pipeline with higher
performance, Harvard architecture with separate instruction and data bus. ARM9 executes
v4T and v5TE instruction sets. E stands for enhanced instructions.
 ARM10 has six-stage (fetch, issue, decode, execute, memory, write) pipeline with optional
vector floating point unit and delivers high floating point performance. ARM10 executes v5TE
instruction sets.
ARM11 has eight-stage pipeline, high performance and power efficiency and it executes v6
instructions set. With the addition of vector floating point unit, it performs fast floating point operations
1.2.9.2 Nomenclature
ARM processor implementation is described by the product nomenclature as given below
ARM [x][y][z][T][D][M][I][E][J][F][-S]
x - Family
y - Memory management/memory protection unit.
z - Ache size
T- Thumb state
D - JTAG debug option
M - Fast multiplier
I - Embedded ICE macrocell
E - Enhanced instructions
J - Jazzel state
F - Vector floating point unit
S - Synthesizable version
Referring to the nomenclature, ARM7TDMI can be understood as an ARM7 processor with thumb
implementation, JTAG debug, multiplier and ICE macro cell. Similarly ARM926EJ-S is an ARM9
processor with MMU and cache implementation, enhanced instructions, Jazzel state and has a
synthesizable core.
1.2.10 ARM architecture v7 profile:

In order to provide a wide coverage of different application domains, addressing their specific
requirements, ARM core is evolved into architecture version7 which has three different profiles: the
application profile, real time profile and microcontroller profile. Architecture v7 should not be confused
with ARM7 which has been explained before under architecture v4.
1.2.10.1 Application profile (Cortex -A)

Cortex A series of architectures are multicores with power efficiency and high performance. Every
Cortex - A implementation is intended for highest performance at ultralow power design. It supports
with, in-built memory management unit. Being influenced by multitasking OS system requirements, it
has virtualization extensions and provides a trust zone for a safe and extensible system. It has
enhanced Java support and provides a secure program execution environment. These architectures

are typically designed for high end real time safety critical applications like automotive powertrain
system. Some
Cortex- A application products are smart phones, tablets, televisions and even high end computing
servers.
1.2.10.2 Real-time profile (Cortex -R)

Cortex R series of architectures are designed for deeply embedded real time multitasking applications.
They have low interrupt latency and predictability features for real time needs. It provides memory
protection for supervisory OS tasks being in privileged mode. It also provides tightly coupled memories
for fast deterministic access. Typical application examples are: hard disk drive controller and base
band controller for mobile applications and engine management unit where high performance and
reliability at very low interrupt latency and determinism are critical requirements.
1.2.10.3 Microcontroller profile (Cortex -M)

Cortex M series of architectures have v6-M as cortex M0, M0+ and M1 and v7-M with Cortex M3, M4
and other successors. This series of architectures developed for deeply embedded microcontroller
profile, offer lowest gate count so smallest silicon area. These are flexible and powerful designs with
completely predictable and deterministic interrupt handling capabilities by introducing the nested vector
interrupt controller (NVIC). The small instruction sets support for high code density and simplified
software development. Developers are able to achieve 32-bit performance at 8-bit price. The very low
gate count of Cortex M0 facilitates its deployment in analog and mixed mode devices. Due to further
demanding applications requiring even better energy efficiency, Cortex M0+ was designed with two
stage pipeline and achieved high performance with very low dynamic power consumption, reduced
branch shadow and reduced number of flash memory access. Cortex M1 was designed for
implementation in FPGA. It is functionally a subset of Cortex M3 and runs ARM v6 instruction set with
OS extension options. It has 32-bit AHB lite bus interface, separate tightly coupled memory interface
and JTAG interface to facilitate debug options. It has three stage pipeline implementation and
configurable NVIC for reducing interrupt latency.
1.2.11 ARMv7-M architecture:

Key features for ARMv7-M architectures are:
 Enable implementations with industry excelling power, performance and silicon area
constraints with simple pipeline design.
 Highly predictable and deterministic operation with Single/low cycle instruction execution and
minimum interrupt latency with cache less memory design.
 Exception handlers are standard C/C++ functions align with ARM‟s programming standard.
 Debug and software profiling support.
 Cortex M3 is the first architecture of ARMv7-M profile. Subsequently the architecture was
enhanced by DSP extensions and named as Cortex M4. Cortex M3 a general purpose CPU,
has optimized debug options for microcontroller applications. It has only Thumb-2 processing
core which has blend of ARM 32-bits and Thumb 16 bits instructions which removes the need
of ARM-Thumb interworking and offers high code density at high energy efficiency. A
hardware divide instruction was introduced in the instruction set and a number of multiply
instructions are also available to improve data processing performance. It supports only two
modes of operation called thread and handler mode. User programs run in thread mode and
exceptions are handled in handler mode which is privileged. All exceptions could be
programmed in C/C++. NVIC is part of Cortex-M3 macrocell. It is a 32 bit core with 18 working
registers: r0-r7 as low registers, r8-r12 as high registers, three special purpose registers, r13
stack pointer, r14 link register, r15 the program counter, one program status register xPSR
and one more stack pointer banked for handler mode. The Cortex-M3 and Cortex-M4
processors also support unaligned data accesses, a feature previously available only in high-

end processors. Cortex M4 comes under the nomenclature of ARMv7E-M. It was developed
as a high performance digital signal controller with 72 DSP instructions implemented along
with Cortex M3 instruction set retained. Single cycle execution of multiply and accumulate
instructions provides 45% speed improvement compared to Cortex M3.
1.2.11.1 Cortex M4 Features:

 Thumb2 instruction set delivers the significant benefits of high code density of Thumb with
32-bit performance of ARM.
 Optional IEEE754-compliant single-precision Floating Point Unit.
 Code-patch ability for memory system updates.
 Power control optimization by integrating sleep and deep sleep modes.
 Hardware division and fast multiply and accumulate for SIMD DSP instructions.
 Saturating arithmetic for noise cancellation in signal processing.
 Deterministic, low latency interrupt handling for real time-critical applications.
 Optional Memory Protection Unit(MPU) for safety-critical applications
 Extensive implementation of debug, trace and code profiling capabilities.
Fig 1.14. Cortex M4 core architecture

The ARM Cortex-M4 architecture is built on a high-performance processing core, with a 3-stage
pipeline. Harvard architecture, optional IEEE754-compliant single-precision floating-point computation,
a range of single-cycle and SIMD multiplication and multiply-with-accumulate capabilities, saturating
arithmetic and dedicated hardware division features make it typically suitable for high precision digital
signal processing applications. The processor delivers excellent energy efficiency at high code density
and significantly improving interrupt handling and system debug capabilities. A generic system on chip
architecture of Cortex M4 is shown in fig 1.14. The brief description of each functional block is given
below.
Nested Vectored Interrupt Controller (NVIC):
Tightly integrated with the processor core, NVIC is a configurable Interrupt Controller used to deliver
excellent real time interrupt performance. Very low interrupt latency is achieved through its hardware
stacking registers. The processor automatically saves and retrieves its state on exception entry and
exit removing the code overhead from ISRs. It also has the ability of interrupting the load and store
multiple atomic instructions that provides faster interrupt response. The NVIC includes a Non

Maskable Interrupt (NMI) and can provide up to 256 interrupt priority levels for each of 240 interrupts it
supports. A higher priority interrupt can preempt the currently running ISR facilitating interrupt nesting.
Wake Up Interrupt Controller (WIC):
To optimize low-power designs, the NVIC integrates with an optional peripheral called Wake up
interrupt controller to implement sleep modes and an optional deep sleep function. When the WIC is
enabled, the power management unit powers down the processor and makes it enter deep sleep
mode. When the WIC receives an interrupt, it takes few clock cycles to wake-up the processor and
restore its state. So it adds to interrupt latency in deep sleep mode. WIC is not programmable and
operates completely with hardware signals.
Memory Protection Unit:
In embedded OS, MPU is used for safeguarding memory used for kernel functions from unauthorized
access by user program. In OS environment, when any untrusted user program tries to access
memory protected by MPU, the processor generates a memory manage fault causing a fault
exception. MPU divides the memory map into a number of regions defining memory attributes for
each. MPU separates and protects the code, data and stack for each task required for safety critical
embedded systems. MPU can be implemented to enforce privilege access rules and separate tasks. It
is an optional block in Cortex M4.
Bus Matrix:
The processor contains a bus matrix that arbitrates the processor core and optional Debug
Access Port (DAP) memory accesses to both the external memory system, the internal System Control
Spaces and to various debug components. It arbitrates requests from different bus masters in the
system. Bus matrix is connected to the code interface for accessing the code memory, SRAM and
peripheral interface for data memory and other peripherals and the optional MPU for managing
different memory regions.
Debug Access Port (DAP):
DAP, the implementation of ARM debug interface enables debug access to various master ports on
the ARM SoC. It provides system access for the debugger tool using AHB-AP, APB-AP and JTAG-AP
without halting the processor. Embedded Trace Macrocell (ETM) generates instruction trace.
Instrumentation Trace Macrocell (ITM) allows software-generated debug messages and also to
generate timestamp information. Data Watchpoint and Trace (DWT) unit can be used to generate data
trace, event trace, and profiling trace information. Flash patch and break point (FPB) implements
hardware breakpoints, patches code and data from Code space to System space. Serial wire viewer
(SWV) is one bit ETM port. SWV provides different types of information like program counter values,
data read and write cycles, peripheral values, event counters and exceptions.
Floating Point Unit (FPU):
Cortex M4 architecture suggests an optional FPU which is IEEE 754 single precision compliant. The
core instruction set supports various signal processing operations. It executes single instruction
multiple data (SIMD) instructions with 16 bit data types. Floating point core supports addition,
multiplication and hardware division. It has a 32X32 multiply and accumulate (MAC) unit that produces
64 bit results. Embedded signal processing applications that involve data compression, statistical
signal processing, measuring, filtering and compressing real world analog signals can use Cortex M4
with FPU.
Floating point unit supports:
 Conversions between fixed point and floating point data formats and instructions with floating
point immediate data.
 Saturation math.
 Decouple 3-stage pipeline.

 Three modes of operations: full compliance mode, flush-to-zero mode and default NaN mode.
 To be disabled when it is not in use to conserve energy.
1.2.12 Operating States and Operating Modes:
Fig 1.15. Operating States of ARM Core

Cortex M4 has two operating states: thumb state and debug state as shown in fig 1.15. When it is
executing any instruction, it is in thumb state. The core operates on thumb2 technology. Most of the
instructions are 16 bit thumb instructions in addition to few 32 bit instructions. When any debug request
is received from the debugger on the host computer, or the execution flow hits with a break point
instruction, the core gets halted and enters to the debug state. Cortex M4 supports both JTAG and
serial wire viewer debug ports. When the debug condition is removed, the core is unhalted and
reenters to the thumb state.

Fig 1.16. Operating Modes of ARM Core

Cortex M4 has two operating modes: the thread mode and the handler mode as shown in fig 1.12.
After reset, the core enters to the thread mode and executes the OS kernel program or the initialization
code with a privileged access level. The thread mode with privileged access level can enter to an
unprivileged access level under program control to safe guard the trust zone of system software. But
the thread mode with unprivileged access level cannot revert back to a privileged access level. If
required so, the processor core has to make use of the exception mechanism. When an exception
occurs, the NVIC automatically saves the user program context to the selected stack of thread mode.
The core enters the handler mode and executes the exception handler code. In handler mode, the
core always has privileged access level. When it returns from the exception handler, it returns back to
the thread mode after restoring its state and context.
The implementation of privileged and unprivileged access mechanism ensures protection of memory
accesses to critical regions of code. In a system having an embedded OS, the kernel executes at
privileged access level and application tasks execute at unprivileged access level. The memory access
permissions can be assigned appropriately to application tasks using the Memory Protection Unit
(MPU) and shared memory corruption can be prevented.
1.2.13 Programming Model:

The programming model of the Cortex-M4 processors has 18 working registers shown in Fig 1.17.
Thirteen of them are general purpose 32-bit registers, three have special uses and two stack pointers.

Fig 1.17. Programming model

R0 - R12
Registers R0 to R12 are general purpose registers. The first eight (R0 - R7) are called low registers
and used by most of the 16-bit instructions due to the limited available bits in the instruction encoding
format. The high registers (R8 - R12) can be used with 32-bit instructions, and a few 16-bit
instructions.
R13: stack pointer (SP)

There are two different Stack Pointers in the register bank. The Main Stack Pointer (MSP) and the
process stack pointer (PSP). After reset, the processor core enters thread mode. MSP is the default
stack pointer selected. It is also used when the processor enters handler mode. The PSP can only be
used in Thread Mode by the user application code with unprivileged access level. In normal program
flow, only one of these Stack Pointers is visible. PSP is basically used when the stack of the OS kernel
and application tasks are needed to be separated. All applications may not require embedded OS. In
such cases PSP is not used and MSP is used both in thread and handler modes.
R14: link register (LR)

Link register is used to hold the return address to respond to a control transfer instruction while calling
a function or subroutine. At the end of the subroutine, the value of LR is loaded into the program

counter (PC), so that program control can resume the calling program. If a function needs to call
another function, it needs to save the value of LR in the stack before entering to the new function.
R15/ program counter (PC)

Program Counter points to the next instruction to be executed. It can also be used as a general
purpose register that can be both read and updated. When PC is used as a destination register, it
causes a branch operation. Since the instructions are of 16 bits or 32 bits length, the PC must be
aligned to half-word or word boundary by making the Least Significant Bit of it always zero.
Bit[0] of PC is loaded into the EPSR T-bit at reset and must be 1.
Program status registers (PSR)

The Program Status Register shown in Fig 1.18 is composed of three status registers:
 Application PSR (APSR)

 Interrupt PSR (IPSR)
 Execution PSR (EPSR)
Fig 1.18 xPSR diagram

The first row in the above PSR shows 32 bit APSR. N, Z, C, V and Q are negation, zero, carry,
overflow and DSP saturation flags respectively. These are the current state of the condition flags. The
second row indicates IPSR, whose bits [0-8] give current exception handler number. The third row is
the EPSR which contains the thumb state bit T and execution state bit for either IF-Then instruction or
an interruptible continual instruction.
1.2.14 Instruction Set: Tables with all categories of instructions with descriptions.
Load/Store instructions with addressing modes.
Mnemonic Operands Brief description
ADC, ADCS {Rd,} Rn, Op2 Add with Carry
ADD, ADDS {Rd,} Rn, Op2 Add
ADD, ADDW {Rd,} Rn, #imm12 Add
ADR Rd, label Load PC-relative Address
AND, ANDS {Rd,} Rn, Op2 Logical AND
ASR, ASRS Rd, Rm, <Rs|#n> Arithmetic Shift Right
B label Branch
BFC Rd, #lsb, #width Bit Field Clear
BFI Rd, Rn, #lsb, #width Bit Field Insert
BIC, BICS {Rd,} Rn, Op2 Bit Clear
BKPT #imm Breakpoint
BL label - Branch with Link -

BLX Rm Branch indirect with Link

BX Rm Branch indirect
CBNZ Rn, label Compare and Branch if Non Zero
CBZ Rn, label Compare and Branch if Zero
CLREX - Clear Exclusive
CLZ Rd, Rm Count Leading Zeros
CMN Rn, Op2 Compare Negative
CMP Rn, Op2 Compare
Change Processor State, Disable
CPSID i
Interrupts
Change Processor State, Enable
CPSIE i
Interrupts
DMB - Data Memory Barrier
DSB - Data Synchronization Barrier
EOR, EORS {Rd,} Rn, Op2 Exclusive OR N,Z,C
ISB - Instruction Synchronization Barrier
IT - If-Then condition block
LDM Rn{!}, reglist Load Multiple registers, increment after
Load Multiple registers, decrement
LDMDB, LDMEA Rn{!}, reglist
before
LDMFD, LDMIA Rn{!}, reglist Load Multiple registers, increment after
LDR Rt, [Rn, #offset] Load Register with word
LDRB, LDRBT Rt, [Rn, #offset] Load Register with byte
LDRD Rt, Rt2, [Rn, #offset] Load Register with two bytes
LDREX Rt, [Rn, #offset] Load Register Exclusive
LDREXB Rt, [Rn] Load Register Exclusive with Byte

LDREXH Rt, [Rn] Load Register Exclusive with Halfword
LDRH, LDRHT Rt, [Rn, #offset] Load Register with Halfword
LDRSB, LDRSBT Rt, [Rn, #offset] Load Register with Signed Byte
LDRSH, LDRSHT Rt, [Rn, #offset] Load Register with Signed Halfword
LDRT Rt, [Rn, #offset] Load Register with word
LSL, LSLS Rd, Rm, <Rs|#n> Logical Shift Left
LSR, LSRS Rd, Rm, <Rs|#n> Logical Shift Right
MLA Rd, Rn, Rm, Ra Multiply with Accumulate, 32-bit result
MLS Rd, Rn, Rm, Ra Multiply and Subtract, 32-bit result
MOV, MOVS Rd, Op2 Move
MOVT Rd, #imm16 Move Top
MOVW, MOV Rd, #imm16 Move 16-bit constant
Move from Special Register to general
MRS Rd, spec_reg
register
Move from general register to Special
MSR spec_reg, Rm
Register
MUL, MULS {Rd,} Rn, Rm Multiply, 32-bit result

MVN, MVNS Rd, Op2 Move NOT

NOP - No Operation
ORN, ORNS {Rd,} Rn, Op2 Logical OR NOT
ORR, ORRS {Rd,} Rn, Op2 Logical OR
PKHTB, PKHBT {Rd,} Rn, Rm, Op2 Pack Halfword
POP reglist Pop registers from stack
PUSH reglist Push registers onto stack
QADD {Rd,} Rn, Rm Saturating double and Add Q
QADD16 {Rd,} Rn, Rm Saturating Add 16
QADD8 {Rd, Rn, Rm Saturating Add 8
Saturating Add and Subtract with
QASX {Rd,} Rn, Rm
Exchange
QDADD {Rd,} Rn, Rm Saturating Add Q
QDSUB {Rd,} Rn, Rm Saturating double and Subtract Q
Saturating Subtract and Add with
QSAX {Rd,} Rn, Rm
Exchange
QSUB {Rd,} Rn, Rm Saturating Subtract Q
QSUB16 {Rd,} Rn, Rm Saturating Subtract 16
QSUB8 {Rd,} Rn, Rm Saturating Subtract 8
RBIT Rd, Rn Reverse Bits
REV Rd, Rn Reverse byte order in a word
REV16 Rd, Rn Reverse byte order in each halfword

Reverse byte order in bottom half word
REVSH Rd, Rn
and sign extend
ROR, RORS Rd, Rm, <Rs|#n> Rotate Right
RRX, RRXS Rd, Rm Rotate Right with Extend
RSB, RSBS {Rd,} Rn, Op2 Reverse Subtract
SADD16 {Rd,} Rn, Rm Signed Add 16 GE
SADD8 {Rd,} Rn, Rm Signed Add 8 GE
Signed Add and Subtract with Exchange
SASX {Rd,} Rn, Rm
GE
SBC, SBCS {Rd,} Rn, Op2 Subtract with Carry
SBFX Rd, Rn, #lsb, #width Signed Bit Field Extract
SDIV {Rd,} Rn, Rm Signed Divide
SEL {Rd,} Rn, Rm Select bytes
SEV - Send Event
SHADD16 {Rd,} Rn, Rm Signed Halving Add 16
SHADD8 {Rd,} Rn, Rm Signed Halving Add 8
Signed Halving Add and Subtract with
SHASX {Rd,} Rn, Rm
Exchange
Signed Halving Subtract and Add with
SHSAX {Rd,} Rn, Rm
Exchange
SHSUB16 {Rd,} Rn, Rm Signed Halving Subtract 16

SHSUB8 {Rd,} Rn, Rm Signed Halving Subtract 8

Signed Multiply Accumulate Long
SMLATB, SMLATT Rd, Rn, Rm, Ra
(halfwords) Q
SMLAD, SMLADX Rd, Rn, Rm, Ra Signed Multiply Accumulate Dual Q
Signed Multiply with Accumulate (32 x
SMLAL RdLo, RdHi, Rn, Rm
32 + 64), 64-bit result
SMLALBB,SMLALBT, Signed Multiply Accumulate Long,
RdLo, RdHi, Rn, Rm
SMLALTB, SMLALTT halfwords
SMLALD, SMLALDX RdLo, RdHi, Rn, Rm Signed Multiply Accumulate Long Dual
Signed Multiply Accumulate, word by
SMLAWB, SMLAWT Rd, Rn, Rm, Ra
halfword Q
SMLSD Rd, Rn, Rm, Ra Signed Multiply Subtract Dual Q
SMLSLD RdLo, RdHi, Rn, Rm Signed Multiply Subtract Long Dual
Signed Most significant word Multiply
SMMLA Rd, Rn, Rm, Ra
Accumulate
Signed Most significant word Multiply
SMMLS, SMMLR Rd, Rn, Rm, Ra
Subtract
SMMUL, SMMULR {Rd,} Rn, Rm Signed Most significant word Multiply
Signed dual Multiply Add Q
SMUAD {Rd,} Rn, Rm

SMULBB, SMULBT SMULTB,
{Rd,} Rn, Rm Signed Multiply (halfwords)
SMULTT
SMULL RdLo, RdHi, Rn, Rm Signed Multiply (32 x 32), 64-bit result
SMULWB, SMULWT {Rd,} Rn, Rm Signed Multiply word by halfword
SMUSD, SMUSDX {Rd,} Rn, Rm Signed dual Multiply Subtract
SSAT Rd, #n, Rm {,shift #s} Signed Saturate Q
SSAT16 Rd, #n, Rm Signed Saturate 16 Q
Signed Subtract and Add with Exchange
SSAX {Rd,} Rn, Rm
GE
SSUB16 {Rd,} Rn, Rm Signed Subtract 16
SSUB8 {Rd,} Rn, Rm Signed Subtract 8
STM Rn{!}, reglist Store Multiple registers, increment after
Store Multiple registers, decrement
STMDB, STMEA Rn{!}, reglist
before
STMFD, STMIA Rn{!}, reglist Store Multiple registers, increment after
STR Rt, [Rn, #offset] Store Register word
STRB, STRBT Rt, [Rn, #offset] Store Register byte
STRD Rt, Rt2, [Rn, #offset] Store Register two words
STREX Rd, Rt, [Rn, #offset] Store Register Exclusive
STREXB Rd, Rt, [Rn] Store Register Exclusive Byte
STREXH Rd, Rt, [Rn] Store Register Exclusive Halfword
STRH, STRHT Rt, [Rn, #offset] Store Register Halfword
STRT Rt, [Rn, #offset] Store Register word
SUB, SUBS {Rd,} Rn, Op2 Subtract
SUB, SUBW {Rd,} Rn, #imm12 Subtract

SVC #imm Supervisor Call

SXTAB {Rd,} Rn, Rm,{,ROR #} Extend 8 bits to 32 and add
SXTAB 16 {Rd,} Rn, Rm,{,ROR #} Dual extend 8 bits to 16 and add
SXTAH {Rd,} Rn, Rm,{,ROR #} Extend 16 bits to 32 and add
SXTB16 {Rd,} Rm {,ROR #n} Signed Extend Byte 16
SXTB {Rd,} Rm {,ROR #n} Sign extend a byte
SXTH {Rd,} Rm {,ROR #n} Sign extend a halfword
TBB [Rn, Rm] Table Branch Byte
TBH [Rn, Rm, LSL #1] Table Branch Halfword
TEQ Rn, Op2 Test Equivalence

TST Rn, Op2 Test
UADD16 {Rd,} Rn, Rm Unsigned Add 16 GE
UADD8 {Rd,} Rn, Rm Unsigned Add 8 GE
Unsigned Subtract and Add with
USAX {Rd,} Rn, Rm
Exchange GE
UHADD16 {Rd,} Rn, Rm Unsigned Halving Add 16
UHADD8 {Rd,} Rn, Rm Unsigned Halving Add 8
Unsigned Halving Add and Subtract with
UHASX {Rd,} Rn, Rm
Exchange
Unsigned Halving Subtract and Add with
UHSAX {Rd,} Rn, Rm
Exchange
UHSUB16 {Rd,} Rn, Rm Unsigned Halving Subtract 16
UHSUB8 {Rd,} Rn, Rm Unsigned Halving Subtract 8
UBFX Rd, Rn, #lsb, #width Unsigned Bit Field Extract
UDIV {Rd,} Rn, Rm Unsigned Divide
Unsigned Multiply Accumulate Long (32
UMAAL RdLo, RdHi, Rn, Rm
x32 + 32 +32), 64-bit result
Unsigned Multiply with Accumulate (32
UMLAL RdLo, RdHi, Rn, Rm
x 32 + 64), 64-bit result
UMULL RdLo, RdHi, Rn, Rm Unsigned Multiply (32 x 32), 64-bit result
UQADD16 {Rd,} Rn, Rm Unsigned Saturating Add 16
UQADD8 {Rd,} Rn, Rm Unsigned Saturating Add 8
Unsigned Saturating Add and Subtract
UQASX {Rd,} Rn, Rm
with Exchange
Unsigned Saturating Subtract and Add
UQSAX {Rd,} Rn, Rm
with Exchange
UQSUB16 {Rd,} Rn, Rm Unsigned Saturating Subtract 16
UQSUB8 {Rd,} Rn, Rm Unsigned Saturating Subtract 8
USAD8 {Rd,} Rn, Rm Unsigned Sum of Absolute Differences
Unsigned Sum of Absolute Differences
USADA8 {Rd,} Rn, Rm, Ra
and Accumulate
USAT Rd, #n, Rm {,shift #s} Unsigned Saturate Q
USAT16 Rd, #n, Rm Unsigned Saturate 16 Q
UASX {Rd,} Rn, Rm Unsigned Add and Subtract with

Exchange GE
USUB16 {Rd,} Rn, Rm Unsigned Subtract 16 GE
USUB8 {Rd,} Rn, Rm Unsigned Subtract 8 GE
UXTAB {Rd,} Rn, Rm,{,ROR #} Rotate, extend 8 bits to 32 and Add

UXTAB16 {Rd,} Rn, Rm,{,ROR #} Rotate, dual extend 8 bits to 16 and Add
Rotate, unsigned extend and Add
UXTAH {Rd,} Rn, Rm,{,ROR #}
Halfword
UXTB {Rd,} Rm {,ROR n} Zero extend a Byte
UXTB16 {Rd,} Rm {,ROR #n} Unsigned Extend Byte 16
UXTH {Rd,} Rm {,ROR #n} Zero extend a Halfword
VABS.F32 Sd, Sm Floating-point Absolute
VADD.F32 {Sd,} Sn, Sm Floating-point Add
Compare two floating-point registers, or
VCMP.F32 Sd, <Sm | #0.0> one floating-point register and zero
FPSCR
Compare two floating-point registers, or
VCMPE.F32 Sd, <Sm | #0.0> one floating-point register and zero with
Invalid Operation check FPSCR
Convert between floating-point and
VCVT.S32.F32 Sd, Sm
integer
Convert between floating-point and fixed
VCVT.S16.F32 Sd, Sd, #fbits
point
Convert between floating-point and
VCVTR.S32.F32 Sd, Sm
integer with rounding
Converts half-precision value to single-
VCVT<B|H>.F32.F16 Sd, Sm
precision
Converts single-precision register to
VCVTT<B|T>.F32.F16 Sd, Sm
half-precision
VDIV.F32 {Sd,} Sn, Sm Floating-point Divide
Floating-point Fused Multiply
VFMA.F32 {Sd,} Sn, Sm
Accumulate
Floating-point Fused Negate Multiply
VFNMA.F32 {Sd,} Sn, Sm
Accumulate
VFMS.F32 {Sd,} Sn, Sm Floating-point Fused Multiply Subtract
Floating-point Fused Negate Multiply
VFNMS.F32 {Sd,} Sn, Sm
Subtract
VLDM.F<32|64> Rn{!}, list Load Multiple extension registers
VLDR.F<32|64> <Dd|Sd>, [Rn] Load an extension register from memory
VLMA.F32 {Sd,} Sn, Sm Floating-point Multiply Accumulate
VLMS.F32 {Sd,} Sn, Sm Floating-point Multiply Subtract
VMOV.F32 Sd, #imm Floating-point Move immediate
VMOV Sd, Sm Floating-point Move register
Copy ARM core register to single
VMOV Sn, Rt
precision
VMOV Sm, Sm1, Rt, Rt2 Copy 2 ARM core registers to 2 single

precision
VMOV Dd[x], Rt Copy ARM core register to scalar
VMOV Rt, Dn[x] Copy scalar to ARM core register
Move FPSCR to ARM core register or
VMRS Rt, FPSCR
APSR
Move to FPSCR from ARM Core
VMSR FPSCR, Rt
register FPSCR
VMUL.F32 {Sd,} Sn, Sm Floating-point Multiply
VNEG.F32 Sd, Sm Floating-point Negate
VNMLA.F32 Sd, Sn, Sm Floating-point Multiply and Add
VNMLS.F32 Sd, Sn, Sm Floating-point Multiply and Subtract
VNMUL {Sd,} Sn, Sm Floating-point Multiply
VPOP list Pop extension registers
VPUSH list Push extension registers
VSQRT.F32 Sd, Sm Calculates floating-point Square Root
VSTM Rn{!}, list Floating-point register Store Multiple
VSTR.F<32|64> Sd, [Rn] Stores an extension register to memory
VSUB.F<32|64> {Sd,} Sn, Sm Floating-point Subtract
WFE - Wait For Event
WFI - Wait For Interrupt
1.2.14.1 Floating Point Number Representation:

Floating point is a method of representing real numbers in a computer. It supports a wide dynamic
range of values to be represented compared to fixed point numbers using the same number of bits.
Each number has an exponent and a fraction. There are several IEEE standards to represent floating
point numbers such as half precision (16bits), single precision (32bits), double precision (64bits) and
quadruple precision (128bits) formats.
Fig 1.22. IEEE 754 single precision format

The real value assumed by a given 32 bit data with a given biased exponent (e) of unsigned
integer and a 23 bit fraction is:
-i
−1 sign
(1+ 23
𝑖=1𝑏23−i 2 ) x (2e-127)
= (-1) sign X 1. Fraction X 2(exponent-127)
127 is the bias for single precision floating point. Sign bit is 1 for negative numbers and 0 for positive
numbers.
(i) Conversion from IEEE 754 single precision 32-bit binary to decimal:

Consider the 32 bit binary number: 01000011011010001000000000000000

0 10000110 11010001000000000000000
Sign Exponent Fraction
(-1)0 (2134 -127) (1+2-1+2-2 +2-4+2-8)
The real number is: 27 x 1.81640625 = (232.5)10

(ii) Conversion from decimal to IEEE 754 single precision 32-bit format:
Consider the decimal number: +103.625
Equivalent binary representation is: +1100111.101
The next step is to normalize the number by moving the binary point to the right of the left
most 1. So the normalized representation of 103.625 is:
= +1.100111101 X 26 // 6=e-127 (exponent-bias)
= +1.100111101 X 2133-127 // e=133
= +1.100111101 X 210000101-01111111
In IEEE 754 standard 32 bit single precision format:
0 10000101 10011110100000000000000
Sign bit is 0 as the number is positive. The 8-bit exponent is 10000101 which is binary equivalent of
133. The fraction part of the binary number after normalized is 100111101. It is of 9-bits.So the 23-bit
fraction is 10011110100000000000000 (zero extended to the right). When any binary number is
normalized, it infers that the bit before the binary point is a „1‟. So there is no need to save this bit.
1.2.14.2 Floating point instructions with examples

VABS.F32 Sd, Sm Floating-point Absolute
VADD.F32 {Sd,} Sn, Sm Floating-point Add
Compare two floating-point registers, or one floating-point
VCMP.F32 Sd, <Sm | #0.0>
register and zero FPSCR
Compare two floating-point registers, or one floating-point
VCMPE.F32 Sd, <Sm | #0.0>
register and zero with Invalid Operation check FPSCR
VCVT.S32.F32 Sd, Sm Convert between floating-point and integer
VCVT.S16.F32 Sd, Sd, #fbits Convert between floating-point and fixed point
VCVTR.S32.F32 Sd, Sm Convert between floating-point and integer with rounding
VCVT<B|H>.F32.F16 Sd, Sm Converts half-precision value to single-precision
VCVTT<B|T>.F32.F16 Sd, Sm Converts single-precision register to half-precision
VDIV.F32 {Sd,} Sn, Sm Floating-point Divide
VFMA.F32 {Sd,} Sn, Sm Floating-point Fused Multiply Accumulate
VFNMA.F32 {Sd,} Sn, Sm Floating-point Fused Negate Multiply Accumulate
VFMS.F32 {Sd,} Sn, Sm Floating-point Fused Multiply Subtract
VFNMS.F32 {Sd,} Sn, Sm Floating-point Fused Negate Multiply Subtract
VLDM.F<32|64> Rn{!}, list Load Multiple extension registers
VLDR.F<32|64> <Dd|Sd>, [Rn] Load an extension register from memory

VLMA.F32 {Sd,} Sn, Sm Floating-point Multiply Accumulate

VLMS.F32 {Sd,} Sn, Sm Floating-point Multiply Subtract
VMOV.F32 Sd, #imm Floating-point Move immediate
VMOV Sd, Sm Floating-point Move register
VMOV Sn, Rt Copy ARM core register to single precision
VMOV Sm, Sm1, Rt, Rt2 Copy 2 ARM core registers to 2 single precision
VMOV Dd[x], Rt Copy ARM core register to scalar
VMOV Rt, Dn[x] Copy scalar to ARM core register
VMRS Rt, FPSCR Move FPSCR to ARM core register or APSR
VMSR FPSCR, Rt Move to FPSCR from ARM Core register FPSCR
VMUL.F32 {Sd,} Sn, Sm Floating-point Multiply
VNEG.F32 Sd, Sm Floating-point Negate
VNMLA.F32 Sd, Sn, Sm Floating-point Multiply and Add
VNMLS.F32 Sd, Sn, Sm Floating-point Multiply and Subtract
VNMUL {Sd,} Sn, Sm Floating-point Multiply

VPOP list - Pop extension registers
VPUSH list - Push extension registers
VSQRT.F32 Sd, Sm Calculates floating-point Square Root
VSTM Rn{!}, list Floating-point register Store Multiple
VSTR.F<32|64> Sd, [Rn] Stores an extension register to memory
VSUB.F<32|64> {Sd,} Sn, Sm Floating-point Subtract
1.2.15 CMSIS:
The CortexTM microcontroller software interface standard (CMSIS) is a vendor-independent hardware
abstraction layer developed by ARM. The CMSIS has generic software libraries and simple software
interfaces to the processor and the peripherals. It also provides common APIs for various RTOSs.
CMSIS provides a compiler independent layer and can be compiled by all mainstream compilers
(ARMCC, IAR, GCC and TI‟s CCS). CMSIS DSP library for Cortex M4 has sixty functions written in „C‟
both in fixed point and floating point implementation to utilize the signal processing capabilities of FPU.
Separate functions are there for operating on 8-bit, 16-bit, 32-bit integers and 32-bit floating point
values. DSP library performs about two times faster on Cortex M4 in comparison to cortex M3 and ten
times faster with FPU hardware implemented.
1.2.16 Introduction to TIVA Microcontrollers

In this text book, TIVA platforms and launch pads are used to develop various embedded applications.
So in this section two TIVA series microcontrollers are introduced.

1.2.16.1 TIVA TM4C123GH6PM Microcontroller
Fig 1.20. TIVA TM4C123GH6PM Microcontroller block diagram.

The microcontroller block diagram shown in Fig 1.20 and Fig 1.21 have six functional units. The cortex
M4F core, on-chip memory, analog block, serial interface, motion control and system integration.
Features:
 TM4C123GH6PM microcontroller has 32 bit ARM Cortex M4 CPU core with 80 MHz clock
rate.
 Memory protection unit provides protected operating system functionality and floating point
unit supports IEEE single precision operations.
 JTAG/SWD/ETM for serial wire debug and trace.
 Nested vector interrupt controller (NVIC) reduces interrupt response latency.
 Serial control block holds the system configuration information.
 The microcontroller has a set of memory integrated in it: 256 KB flash memory, 32 KB SRAM,
2 KB EEPROM and ROM loaded with TIVA software library and bootloader.
 Serial communications peripherals such as: 2 CAN controllers, full speed USB controller, 8
UARTs, 4 I2C modules and 4 Synchronous serial interface modules.
 On chip voltage regulator, two analog comparators and two 12 channel 12-bit analog to digital
converter with sample rate I million samples per second are the analog functions in built to the
device.
 Two quadrature encoder with index module and two PWM modules are the advanced motion
control functions integrated into the device that facilitate wheel and motor controls.
 Various system functions integrated into the device are: Direct Memory Access controller,
clock and reset circuitry with 16 MHz precision oscillator, six 32-bit timers, six 64-bit timers,

twelve 32/64 bit capture compare PWM, battery backed hibernation module and RTC
hibernation module, 2 watchdog timers and 43 GPIOs.
Few Applications:
 Building automation system
 Lighting control system
 Data acquisition system
 Motion control
 IoT and Sensor networks.
1.2.16.2 TIVA TM4C129CNCZAD Microcontroller
Fig 1.21 TIVA TM4C129CNCZAD Microcontroller block diagram

Features:
 TM4C129CNCZAD microcontroller has 32 bit ARM Cortex M4F CPU core with 120 MHz clock
rate.

 Memory protection unit provides a privileged mode for protected operating system functionality
and floating point unit supports IEEE 754 compliant single precision operations.
 JTAG/SWD/ETM for serial wire debug and trace.
 Nested vector interrupt controller (NVIC) reduces interrupt response latency and high
performance interrupt handling for time critical applications.
 The microcontroller has a set of memory integrated in it: 1MB flash memory, 256 KB SRAM, 6 KB
EEPROM and ROM loaded with TIVAware, software library and bootloader.
 Serial communications peripherals such as: 2 CAN controllers, full speed and high speed USB
controller, 8 UARTs, 10 I2C modules and 4 Synchronous serial interface modules.
 On chip voltage regulator, three analog comparators and two 12 channel 12-bit analog to digital
converter with sample rate 2 million samples per second and temperature sensor are the analog
functions in built to the device.
 One quadrature encoder and one PWM module with 8 PWM outputs are the advanced motion
control functions integrated into the device that facilitate wheel and motor controls.
 Various system functions integrated into the device are: Micro Direct Memory Access controller,
clock and reset circuitry with 16 MHz precision oscillator, eight 32-bit timers, low power battery
backed hibernation module and RTC hibernation module, 2 watchdog timers and 140 GPIOs.
 Cyclic Redundancy Check (CRC) computation module is used for message transfer and safety
system checks. CRC module can be used in combination with AES and DES modules.
 Advanced Encryption Standard (AES) and Data Encryption Standard (DES) accelerator module
provides hardware accelerated data encryption and decryption functions.
 Secure Hash Algorithm/ Message Digest Algorithm (SHA/MD5) provides hardware accelerated
hash functions for secured data applications.

www.ti.com Summary
1.3 Summary
At the end of this chapter, readers should be able to understand basic concepts of embedded system
with its basic building blocks. Since this textbook is focused on TIVA series microcontrollers with ARM
cortex M4 based cores, this chapter is focused on ARM explained as the main stream processing unit.
The article covers generic architecture, programming models, operating modes and basic mechanism
of handling exceptions of ARM7 core. The instruction set and addressing modes have been discussed
with examples of instructions.
With an understanding of concepts such as the evolution of ARM core with the road map of different
core versions; ARM cortex M4 architecture, its floating point operations and generic view of the
instruction set; TIVA TM4C123X and TM4C129X and their features the reader is well placed to
understand subsequent chapters on microcontrollers, timers, mixed signal processing etc.

Review Questions www.ti.com
1.4 Review Questions

1. What is an embedded system? Give few examples of it.
2. What are the components of an embedded system? With a basic block diagram, briefly
explain about the main hardware components of an embedded system.
3. Differentiate between the Harvard and Von-Neumann architectures of memory design.
4. What is instruction set of a processor? Mention the features of CISC and RISC
architectures.
5. What are the specific features of ARM architecture? With a neat block diagram, explain the
basic architecture of ARM7 core.
6. Explain the bit specification of current program status register (CPSR).
7. Mention the operating modes ARM core supports. What are the privileged and unprivileged
modes of operation?
8. Illustrate on the complete programming model of ARM core corresponding to all the
operating modes.
9. What is exception and how it is different from an interrupt? What are the seven exceptions
handled by ARM core? Mention the operating modes associated with each exception. How
the status of F and I bits of CPSR manipulated while handling each exception?
10. What are the sequences of operations ARM core goes through during exception entry and
exit?
11. Mention few important features of ARM instruction set and categorize the ARM instructions
based on their operations into broad classes.
12. What is the importance of a barrel shifter in ARM core? With an example of instruction,
show how the barrel shifter along with the ALU, speeds up the execution.
13. With the example of instructions, explain the addressing modes, ARM instruction set
supports.
14. Describe about the migration of ARM architecture from v4T ARM7TDMI to v7 Cortex series
of processors along its path of evolution.
15. Briefly explain about the specific features of ARM Cortex A, M and R profiles of v7
architecture.
16. With a block diagram, explain the functional blocks of ARM Cortex M4 core. Mention few
features of ARM Cortex M4.
17. Illustrate on the operating states and operating modes of ARM Cortex M4 core and compare
those with their corresponding counter parts in ARM7 core.
18. What is floating point number representation? Explain the IEEE 754 single precision format.
19. For a binary number 11000011011010001000000000000000, show the process of
conversion from IEEE 754 single precision 32 bit binary to decimal. Similarly considering a
decimal number as +102.512 show the process of conversion to IEEE 754 single precision
32 bit form.
20. What are the features of TIVA TM4C123X and TIVA TM4C129X microcontrollers? Mention
few application domains of each.

Chapter 2
Microcontroller Fundamentals for Basic Programming
The previous chapter provided a detailed introduction to 32-bit microcontroller architecture and instruction
sets. It also covered the industry standard ARM based System on Chip architecture and its applications; the
TIVA C series microcontroller that has a wide range of applications in the field of security systems, IoT
gateway solutions.
Since most microcontrollers need to be programmed using assembly or high-level languages like C, C++,
and embedded JAVA to give more intelligence to overall system, this chapter provides an understanding of
how various components/peripherals of the microcontroller can be configured.
By the end of this chapter, readers will be equipped to understand basic C language, supported libraries
relevant to TIVA Architecture; learn how to program TIVA C Series using CC, and know more about low
power modes of TIVA microcontroller and peripheral and memory addressing in TIVA.
This chapter will also cover steps for GPIO programming and the working of watchdog timers and interrupts.'
Topic Page
2.1 Introduction.......................................................................................................................................... 56
2.2 Programming in Embedded Systems.................................................................................................. 56
2.3 Programming Tiva CSeries ................................................................................................................. 58
2.4 Peripheral and Memory Address......................................................................................................... 60
2.5 Programming GPIO in TivaTM Launchpad ......................................................................................... 65
2.6 Watchdog Timer .................................................................................................................................. 71
2.7 Interrupts ............................................................................................................................................. 72
2.8 Low Power Microcontroller .................................................................................................................. 78
2.9 Summary ............................................................................................................................................. 83
2.10 Review questions ............................................................................................................................... 84
Microcontroller Fundamentals for Basic Programming 55

2.1 Introduction
Typical embedded systems are designed using 8 to 32 bit microcontroller platforms. 32-bit controllers,
for example, find applications in consumer electronics, home automation, industrial automation,
automobile, security systems, IoT and healthcare segments. ARM based SoCs such as TIVA C Series
also find applications in the similar segments.
But microcontrollers can provide intelligence in the overall product design only if they are supported by
libraries and necessary software components. TIVA C series can be programed using Code Composer
Studio (CCS) and is well supported by libraries such as TIVAware, TI-RTOS etc. In this chapter, CCS
is the main tool for programming microcontrollers in C language.
To understand the controller capability we need to have knowledge about its memory and its
architecture and its peripherals. Memory addressing with respect to TIVA, including SRAM, flash
memory, internal memory, is important. A microcontroller has General-purpose input/output (GPIO),
which is used to take input and provide output from and to several devices such as sensors, switches
etc. In a fire alarm system, for example, the GPIO is interfaced with sensors. As sensors are analog in
nature, there needs to be an ADC to provide input to controller. The smoke sensor detects smoke in
the room and sends a signal (through GPIO) to switch on the buzzer, which warns users.
Fig 2.1 Fire Alarm
2.2 Programming in Embedded Systems

After its origin at AT&T Bell Labs by Dennis Ritchie between 1969 and 1973, the C programming
language has undergone many transformations. Most C programming environments are often provided
with third party libraries. Usage of these libraries has made it platform reliant and its true essence of
portability is somewhat lost. However, this aspect of C language had an immense impact on growth in
embedded development. Unlike assembly language, with few changes in the I/O access the same
code written in C, can be ported to various processors. In today‟s world, almost all hardware
development kits come with bundled static libraries and header files that is compatible with C
language. C is widely accepted language among embedded design engineers because of following
reasons.
 It is a structured programming language with high code efficiency
 It has excellent readability compared to assembly language
 It offers processor level control like assembly language
Small logic implementation in assembly language is quite easy. But as the complexity of a program
increases, managing it in assembly language becomes trivial. A higher level of hierarchy in
programming is necessary to counter this increase in complexity.
Due to the introduction of many third party libraries in C environment, it was difficult to preserve the
concept of portability of C. American National Standard Institute standardized C language first in 1989.
They released a standard C which came to be known as C89 or more commonly ANSI C .
Subsequently, in 1990, International Standardization Organization (ISO) recognized ANSI-C/C89 and
56 Microcontroller Fundamentals for Basic Programming

www.ti.com Programming in Embedded Systems
on same technical standards released C90. ISO further revised C90 in 1999 and 2011 and released
C99 and C11 respectively.
There is also a flavor of C especially committed to embedded application development called as
Embedded C. It is a collection of C extensions standardized by the C Standard Committee and
released in 2008. Embedded C is built in C language incorporating features like naming address
spaces, named-register storage classes, fixed-point arithmetic, and basic I/O hardware addressing.
2.2.1 Data Types

In the C programming language, data types refer to an extensive system for declaring variables of
different formats. C language provides basic arithmetic types and syntax to build an array, compound
and user data types using some primitive data types. These primitive data types have been
standardized in all ISO releases of C.
 Data Types (ISO C90)

The primitive data types supported in C90 are as follows
Table 2.1: Data types (ISO C90)
Data types Size Remarks

Represents character type variable. By default, char is unsigned. It can
char 1 byte
be specified as signed as well
short 2 bytes Reduces memory usage. By default, short is signed.
By default, int is signed. It takes 4 bytes for 32 bit MPUs but 2 bytes for
int 4 bytes
16 bit MPUs.
long int 4 bytes For 16 bit MPUs as well as 32 bit MPUs, it takes 4 bytes.
Single-precision floating-point format. Unsigned type cannot be specified.
float 4 bytes
The precision is 6 decimal places
Double-precision floating-point format. The precision is 15 decimal
double 8 bytes
places
long Double 10 bytes The precision is 19 decimal places.
 Data types (ISO C99)

Following primitive data types are added to ISO C90 in C99 release. These integer data types are
defined in a header file called stdint.h.
Table 2.2: Data types (ISO C99)
Data types Size Remarks
long long 8 bytes Represents signed and unsigned integer values
int8_t, uint8_t 1 byte
int16_t, uint16_t 2 bytes Can store integers in the range -(1 << x-1)+1 ~ (1 << x-1)-1, for all
int32_t, uint32_t 4 bytes intx_t.
int64_t, uint64_t 8 bytes

Programming Tiva CSeries www.ti.com
 Flexibility of data types with ARM

It must be noted that while in the 8-bit microcontrollers we have to use the right data type for our
variable, this is less of problem in 32-bit CPUs such as ARM.
Most 32-bit processor/microcontrollers have more plentiful memory under various hierarchies to
counter the apprehension of memory usage and allow padding for aligning access. Consider in a 8-
bit processor/microcontroller, memory fetch of a char, integer type (considering integer takes 2
bytes) and long integer type variable will take x, 2x, 4x cycles.
However, for a 32-bit microcontroller, the memory fetch for a char, integer type and long integer
type variable will take same access and computation time.
2.2.2 Bit-wise Operations

The C language has one of the most powerful features as an ability to perform bit manipulation. This
section describes the action of the bit-wise logic operators and provides some illustrations of how they
are used. Bitwise operators AND (&), OR (|), inverter (~), EX-OR (^), Right shift (>>), and Left shift
(<<). These operators are widely used in software designing for embedded systems.
Table 2.3: General Bit wise operations
y x&y x|y x^y ~ (x ^ y)
0 0 0 0 0 1
0 1 0 1 1 0
1 0 0 1 1 0
1 1 1 1 0 1
 Bitwise Shifting
There are two bit-wise shift operators in C. Shift Right (>> data >>) number of bit-positions to
be shifted right and Shift Left (<< data <<) number of bit-positions to be shifted left.
 Masking and Setting Bits

OR can be used to set a bit, and AND can be used to clear a bit. It can be observed that:
(i) Anything OR with a 1 result in a 1, anything OR with a 0 results in no change. (ii) Anything
AND with a 1 results in no change; anything AND with a 0 result in a zero. (iii) Anything EX-OR
with a 1 result in the complement; anything EX-OR with a 0 results in no change.
2.3 Programming Tiva CSeries
2.3.1 Development Tools

Tiva C Series microcontrollers can be programmed using various development tools like Embedded
Software from Mentor Graphics, IAR Systems, Keil MicroVision from ARM Ltd., and Code Composer
Studio (CCS) from Texas Instruments.
2.3.2 Introduction to Code Composer Studio

At this juncture of the book, it is important to concentrate on a single development tool for
programming the hardware. In this book, Code Composer Studio is used because it is free and is
supported by a large TI community commonly known as E2E. This forum is a congregation of
engineers and hobbyist working on TI products across the world.

www.ti.com Peripheral and Memory Address
Code Composer Studio (CCS):

CCS is a TI proprietary cross platform IDE used to convert C and assembly language code to
executable for TI processors, involving Digital Signal Processors, ARM, and other microcontrollers.
CCS combines editing, debugging and analysis tools into a single IDE based on Eclipse open source
development tool.
Compilation (Build Process):

CCS uses a Code Generation Tool (often called CGT) for compilation process also called as build
process. It is used to generate executables for a target device. This process takes source codes
written in C, C++ and/or Assembly Language and produces executable at the output called binaries.
This process undergoes many intermediated stages. A normal development flow of a compilation
process takes the source files written in C/C++ and compiles them to create assembly language files
using a compiler. For projects where source code is written in assembly language, this process is
bypassed. In many projects, some of the logic functions are written in assembly languages along with
other C/C++ source codes. After the assembly language files are generated by the compiler, an
assembler converts them to re-locatable object files. These object files are linked to the runtime
libraries included in the project by a linker. The linker produces executables from these files using
protocols mentioned in the command file. A command file typically consists of a list of all memories of
the part and the type of software compatible to them.
CCS uses C/C++ compiler and other compilation tools which are developed by engineers at TI over
the years and packaged into TI‟s code generation tools. They are commonly amalgamation of various
tools used in compilation processes, namely, Compiler, Assembler, Linker, Optimizer, Code
Generator, Parser, Linear Assembler, Archiver, Disassembler and many more.
Debugger
The CCS debugger depends on a configuration file and a general extension language (GEL) file. The
debugger initializes and loads the software on a target device using information provided by these
files. A target configuration file specifies
(i) Connection type to the target device,
(ii) Target device, and
(iii) About a startup script
Table 2.4: Development Tools for Tiva C Series
Product License Compiler IDE Debugger JTAG

Embedded
Software, 30-day full function GNU C/C++ Gdb Eclipse
Mentor Graphics
Full function.
KEIL MicroVision, Real View U-Link,
Onboard emulation μVision μVision
ARM Ltd. C/C++ 199 USD
limited
32KB code size
CCS, Texas Eclipse XDS100
limited. TI C/C++ CCS
Instruments 79 USD
Upgradeable
32KB code size
Embedded J-Link,
IAR Systems limited. IAR C/C++ C-SPY
Workbench 299 USD
Upgradeable

Peripheral and Memory Address www.ti.com
In CCS, startup scripts are specified to setup the memory map for debugger. It is also used to setup
any initial target state that is necessary for connection to the debugger using memory or register
writes. These scripts are known as GEL script file. „OnStartup()‟ function in the GEL file runs when the
debugger is launched. After the target is connected, „OnTargetConnect()‟defined in the GEL file is
executed.
Organization and Building a CCS Project

In CCS, designs are organized in workspaces and projects which are merely folders in the file system.
When CCS is launched, it prompts the users to provide a folder path to the workspace. This folder
consists of individual project folders and a folder named as ‘.metadata’. The .metadata folder consists
of CCS settings and preferences for the particular workspace. Along with source files, header files and
library files, each project folder contains the build and the tool settings for the project. It also contains
the target configuration file and the command file required by the debugger.
CCS has two predefined build configurations, namely, debug and release. It also provides custom
build configurations.
Debug – It is generally used when it is required to operate in debugging mode. It includes the symbol
tables and executes compilation without any optimization.
Release – Building project in this mode is suited when the user requires performance. It discards all
symbol tables and implements the full code optimization. It is therefore a noted convention to use this
mode only when the final version of a project is to be deployed on the hardware. For all other
intermediate versions, debug mode is rather preferred.
Custom Configuration – CCS also provide its users to add custom build configurations for a particular
project. It can be done by going to processor options under ‘properties -> build -> ARM Compilers‟.
TivaWareTM
TivaWareTM for C series is a free collection of libraries in the form of source codes and static libraries.
TivaWareTM caters to all TI Cortex M devices. It includes
 Peripheral driver library
 USB stacks
 Ethernet Stacks
 Graphics library
 Sensor library
 And other features
TivaWareTM specializes in minimizing programming complexities with optimized drivers and OS
independent support. It provides a large set of libraries which reduces prototyping time. It also provides
a higher abstraction level for programmers to access the hardware peripherals of the board. In this
book, TivaWareTM has been extensively used for programming.
2.4 Peripheral and Memory Address

A 32-bit processor can have 4 GB (=232) of address spaces. It depends on the architecture of the CPU
how these address spaces are segregated, among the memory and peripherals.
2.4.1 Peripheral Addressing

There are two complementary methods of addressing I/O devices for input and output between CPU
and peripheral. These are known as memory mapped I/O (MMIO) and port mapped I/O (PMIO).

In MMIO, same address bus is used to address both memory and peripheral devices. The address bus
of the CPU is shared between the peripheral devices and memory devices attached to the CPU. Thus,
any address accessed by the CPU may denote an address in the memory or a register of attached
peripheral. In these architectures, same CPU instructions used for memory access can also be used
for I/O access.
In PMIO, peripheral devices possess a separate address bus from general memory devices. This is
accomplished in most architectures by providing a separate address bus dedicated to the peripheral
devices attached to the CPU. In these CPUs, the instruction set includes separate instructions to
perform I/O access.
A TM4C123GH6PM chip employs MMIO which implies that the peripherals are mapped into the 32-bit
address bus.
2.4.2 Memory Map

A TM4C123GH6PM chip consists of a 256 KB of Flash memory and 32 KB of SRAM. Table 5 shows
the memory map of a TM4C123GH6PM chip with addresses.
Flash Memory
Flash memory is structured into multiple blocks of single KB size which can be individually written to
and erased. Flash memory is used for store program code. Constant data used in a program can also
be stored in this memory. Lookup tables are used in many designs for performance improvement.
These lookup tables are stored in this memory.
Table 2.5: Memory Mapping in TM4C123GH6PM Chip
Allocated size Allocated address
Flash 256KB 0x00000000 to 0x0003FFFF
Bit-banded on-chip
32 KB 0x20000000 to 0x20007FFF
SRAM
Peripheral All the peripherals 0x40000000 to 0x400FFFFF
SRAM
The on-chip SRAM starts at address 0x2000.0000 of the device memory map. ARM provides a
technology to reduce occurrences of read-modify-write (RMW) operations called bit-banding. This
technology allows address aliasing of SRAM and peripheral to allow access of individual bits of the
same memory in single atomic operation. For SRAM, the bit-band base is located at address
0x2200.0000. Bit band alias are computed according to following formula.
bitband alias= bitband base + byte offset *32 + bit number *4 (2.1)
Note: Bit banding is the technique to access and modifying content of bits in a register. It is helpful to
finish the read-modify operation in single machine cycle.
The region of the memory which device consider for modification is known as bit band region and the
region of memory to which device maps the selected memory is known as bit band alias.
The SRAM is implemented using two 32-bit wide SRAM banks (separate SRAM arrays). The banks
are partitioned in a way that one bank contains all, even words (the even bank) and the other contains

all odd words (the odd bank). A write access that is followed immediately by a read access to the
same bank. This incurs a stall of a single clock cycle.
Internal ROM
The internal ROM of the TM4C123GH6PM device is located at address 0x0100.0000 of the device
memory map. The ROM contains:
 TivaWare™ Boot Loader and vector table
 TivaWareTM Peripheral Driver Library (DriverLib) release of product-specific peripherals and
interfaces
 Advanced Encryption Standard (AES) cryptography tables
 Cyclic Redundancy Check (CRC) error detection functionality
The boot loader is used as an initial program loader (when the Flash memory is empty) as well as an
application-initiated firmware upgrade mechanism (by calling back to the boot loader). The Peripheral
Driver Library, APIs in ROM can be called by applications, reducing flash memory requirements and
freeing the Flash memory to be used for other purposes (such as additional features in the
application). Advance Encryption Standard (AES) is a publicly defined encryption standard used by the
U.S. Government and Cyclic Redundancy Check (CRC) is a technique to validate if a block of data
has the same contents as when previously checked.
Peripheral
All Peripheral devices, timers, and ADCs are mapped as MMIO in address space 0x40000000 to
0x400FFFFF. Since the number of supported peripherals is different among ICs of ARM families, the
upper limit of 0x400FFFFF is variant.
Memory Layout in TIVATM Launchpad

To observe the memory layout of TM4C123GH6PM, users can run an experiment on the board with a
simple code provided below. This is a simple code that results in the glow of the GREEN LED.

Example:
Fig 2.2: Flowchart to glow onboard LED

Pseudo code:
Start: Set clock (division| PLL| 16 Mhz| main OSC)
Configure the pins (Pin 1, 2, 3)
Output: Toggle the led (Pin1, 2, 3)
Delay generation (in nanoseconds)
Run infinite
Once this code is compiled, under workspace, if we expand <the project>/Debug, we can see the
memory map file. Please refer to Fig 2.3, you can find the memory map file is circled.
If we open this file, we can find the memory configuration is available. Refer Fig 2.4 where the memory
configuration is highlighted. We can see that SRAM and FLASH memory are used in this program.
Memory attributes like name, origin, length, used, unused, R/W/X attributes are provided

Fig 2.3 Memory Map File
Fig 2.4 Memory Configuration for the output file

www.ti.com Programming GPIO in TivaTM Launchpad
2.5 Programming GPIO in TivaTM Launchpad

General Purpose Input/output (GPIO) refers to pins on a board which are connected to the
microcontroller in a special configuration. Users can control the activities of these pins in real-time.
 GPIOs are used in devices like SoC, PLDs, and FPGAs, which inherit problems of pin scarcity.
 They are used in multifunction chips like audio codecs and video cards for connectivity
 They are extensively used in embedded systems designs to interface the microcontroller to
external sensors and driver circuits.
GPIO pins can be configured as both input and output. There are generally two states in a GPIO pin,
High=1 and Low=0. These pins can be easily enabled and disabled by the user. A GPIO pin can be
configured as input and used as an interrupt pin typically for wakeup events. We will see this later in
this chapter when we use a switch to force the system wake from hibernation. GPIO peripherals vary
quite widely. In some cases, they can exist as a group of pins that can be switched as a group to either
input or output. In others, each pin can be set up adaptable to either accept or act as a source for
different logic voltages, with configurable drive strengths and pull ups. Pin states of the GPIOs can be
accessed using software instructions. These instructions can be represented by one or more types of
interfaces. Memory mapped peripheral or a dedicated I/O port instruction can be used in this regard.
Voltage levels of GPIOs are critical and it is necessary that users take note of these voltages before
interfacing. Tolerant voltages at GPIO pins are not same as the board supply voltage. Some GPIOs
have 5 V tolerant inputs: even if the device has a low supply voltage (say 2 V), it can accept 5 V
without damage. However, a higher voltage may cause damage to the circuitry or may even fry the
board.

Programming GPIO in TivaTM Launchpad www.ti.com
2.5.1 GPIO Pins in Tiva Launchpad

In the Tiva Launchpad, the GPIO module is composed of six physical GPIO blocks. Each of these
blocks corresponds to an individual GPIO port. There are six ports in Tiva C series microcontrollers
namely, Port A through F. This GPIO module supports up to 43 programmable input/output pins.
(Although it depends on the peripherals being used.)
The GPIO module has the following features:
 The GPIO pins are flexibly multiplexed. This allows it to be also used as peripheral functions.
 The GPIO pins are 5-V-tolerant in input configuration
 Ports A-G are accessed through the Advanced Peripheral Bus (APB)
 Fast toggle capable of a change every clock cycle for ports on AHB, every two clock cycles for
ports on APB
Most of the GPIO functions can operate on more than one GPIO pin (within a single module) at a time.
Can be configured to be a GPIO or a peripheral pin. On reset, the default is GPIO. Note that not all
pins on all parts have peripheral functions, in which case, e the pin is only useful as a GPIO. The
below table shows the pin mux utility in Tiva Launchpad.
Table 2.6: Pin mux utility of Tiva

2.5.2 Advanced features of GPIO in Tiva Launchpad

The GPIO module in Tiva Launch Pad can be used in advanced configurations also. They can be used
for programmable control through interrupts. These interrupts can be triggered on rising, falling or both
edges of the clock. They can also be levelled sensitive for both high and low states. The state of these
pins is retained during hibernate mode. The programmable control for GPIO pad configuration includes
 Weak pull-up or pull-down resistors
 2-mA, 4-mA, and 8-mA pad drive for digital communication; up to four pads can sink 18-mA
for high-current applications
 Slew rate control for 8-mA pad drive
 Open drain enables
 Digital input enables
2.5.3 Direction and Data Registers

Generally, every microcontroller has a minimum of two registers associated with each of I/O ports,
namely Data Register and Direction Register. As the name suggests, Direction Register decides which
way the data will flow; Input or Output. Data register stores the data coming from the microcontroller or
from the pin.
The value assigned to Direction register is configure the pin as either input or output. When the
direction register is properly configured, the Data register can be used to write to the pin or read data
from the pin. When the Direction register is configured as output, the information on the Data register

is driven to the microcontroller pin. Similarly, when Direction register is configured as input, the
information on the microcontroller pin is written to the Data register.
Data Direction Operation: In Tiva C series Launchpad, the GPIO Direction (GPIODIR) register is
used to configure each individual pin as an input or output. When the data direction bit is cleared, the
GPIO is configured as an input, and the corresponding data register bit captures and stores the value
on the GPIO port. When the data direction bit is set, the GPIO is configured as an output, and the
corresponding data register bit is driven out on the GPIO port.
Data Register Operation: In Tiva C Series Launchpad, GPIODATA register is the data register in
which the values written in this register are transferred onto the GPIO port pins if the respective pins
have been configured as outputs through the GPIO Direction (GPIODIR) register. The GPIO ports
allow for the modification of individual bits in the GPIO Data (GPIODATA) register by using bits of the
address bus as a mask. In this manner, we can modify individual GPIO pins in a single instruction
without affecting the state of the other pins.
2.5.4 Toggling Multicolor LED

In this section we will understand how GPIOs are accessed. Embedded engineers have been using
on-board LEDs for a long time in debugging hardware programs. Thus blinking and LED serves a
much higher purpose beneath than it appears. The most famous example, called ‘Blinky,’ is used just
to light up a particular onboard LED.
Switches and RGB LED: The Tiva C Series LaunchPad comes with an RGB LED. This LED is used
in the preloaded RGB quick-start application and can be configured for use in custom applications.
And two switch buttons are included on the board, used in the preloaded quick-start application to
adjust the light spectrum of the RGB LED as well as go into and out of hibernation.
Three GPIO pins connected to the LEDs as outputs and two GPIO pins are connected to switches.
The LaunchPad board schematic and below table shows GPIO pins PF1, PF2 and PF3 are connected
to the red, blue and green colour of RGB LEDs and PF4, PF0 are connected to the SW1, SW2 of user
switches respectively.
Used
for
Configuration
Fig 2.5 Switches and RGB schematic connection to GPIO pins

Table 2.7 Switches: RGB and GPIO pin connection to the microcontroller
In the following example, we will understand how to access a GPIO pin as an output. This code uses
TivaWareTM and can be downloaded for free from the Texas Instruments website. After TivaWareTM
is installed, for a project, it is essential to complete three steps to include TivaWareTM in the project.
 Include TivaWareTM installation directory in path and build variables.
 Add/link driverlib.lib file from “<install_directory>\driverlib\ccs\Debug” to the project.
 Add startup_ccs.c file to the project. (If Applicable)
Example: In the line follower design there are servo motors employed for the movement, there is a IR
transmitter and receiver circuit in-built on the board. If the line follower is on the line then green led will
blink and it follow its path. If is turned then again it will try to follow it, but if there is no path or path is
damaged then it start blinking the red LED and the line follower stop at that point from which its path is
missing or damaged.
Fig 2.6 Flowchart for line follower robot

Code:
Start: Initialize peripherals
#DEFINE LED PIN1
#DEFINE LED PIN2
#DEFINE LED PIN3
#DEFINE IRin
#DEFINE IRout
Check the track
{
while (IR sense the darkness)
{
Turn on Green LED
Delay(nano secs)
}
while (IR sense the light)
{
Turn on Red LED
Delay (nano secs)
}
Run infinite
Table 2.8: Clock setup for TM4C123GH6PM
2.5.5 Using RGB LED Example

Clock setup
It is always advisable that the system clock is setup at the beginning. The following instruction will set
TM4C123GH6PM to 80MHz.
SysCtlClockSet(SYSCTL_SYSDIV_2_5|SYSCTL_USE_PLL|SYSCTL_OSC_MAIN|SYSCTL_XTAL_1
6MHZ);

www.ti.com Watchdog Timer
In this example, we have used the PLL which runs at 400 MHz (specified by SYSCTL_USE_PLL). It is
divided by a divisor 2.5 (specified by SYSCTL_SYSDIV_2_5). There is a divide by 2 in the clock tree
as mentioned in the datasheet. Thus, the effective clock can be calculated as
400MHz
 80MHz
 SYSCTL _ SYSDIV _ 2 _ 5  2
The clock is set to 80 MHz, to verify, SysCtlClockGet() function returns the value of the clock. In figure
3, we can observe that the clock frequency is 66MHz. This is because SYSCTL->DC1.MINSYSDIV,
which driverlib consults, insists that the minimum divider is 3, so it is not possible to operate at 80 MHz
Peripheral Setup
Then we need to enable the clk in the peripheral
SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOF);
SysCtlDelay(3);
Normally the clock is disabled in any peripheral to save power. Leave a delay after it. It is advised to
wait at least 3 clock cycles before configuring the peripheral you have just enabled.
SysCtlPeripheralEnable(uint32_t ui32Peripheral) is what you always use to turn on a peripheral. It's
what enables the clock for it. The parameter is the peripheral you want to enable. For GPIOs its
SYSCTL_PERIPH_GPIOx, being "x" the letter of the peripheral you want to enable.
SysCtlDelay(uint32_t ui32Count) specifies a delay of ui32Count cycles. This suggests that the
instruction pushes the microcontroller to enter an idle state for ui32Count cycles. Each value delays for
3 clock cycles, so in our case with the value 3, we delay 9 clock cycles.
Setting the GPIO pins to output

This part is simple, you use GPIOPinTypeGPIOOutput (uint32_t ui32Port, uint8_t ui8Pins) to set it to
an output.
Ui32Port is the GPIO base, in this case GPIO_PORTF_BASE, and ui8Pins is the pin you want to be
output, in this case GPIO_PIN_1. In the Launchpad, GPIO_PIN_1 suggests the red LED.
GPIOPinTypeGPIOOutput(GPIO_PORTF_BASE, GPIO_PIN_1);
2.6 Watchdog Timer

Every CPU has a system clock which drives the program counter. In every cycle, the program counter
executes instructions stored in the flash memory of a microcontroller. These instructions are executed
sequentially. There exist possibilities where a remotely installed system may freeze or run into an
unplanned situation which may trigger an infinite loop. On encountering such situations, system reset
or execution of the interrupt subroutine remains the only option. Watchdog timer provides a solution to
this.
A watchdog timer counter enters a counter lapse or timeout after it reaches certain count. Under
normal operation, the program running the system continuously resets the watchdog timer. When the
system enters an infinite loop or stops responding, it fails to reset the watchdog timer. In due time, the
watchdog timer enters counter lapse. This timeout will trigger a reset signal to the system or call for an
interrupt service routine (ISR).

Interrupts www.ti.com
The TM4C123GH6PM microcontroller has two Watchdog Timer modules, one module is clocked by
the system clock (Watchdog Timer 0) and the other (Watchdog Timer 1) is clocked by the PIOSC
therefore it requires synchronizers.
Features of Watchdog Timer in TM4C123GH6PM controller:
 32-bit down counter with a programmable load register
 Separate watchdog clock with an enable
 Programmable interrupt generation logic with interrupt masking and optional NMI function
 Lock register protection from runaway software
 Reset generation logic with an enable/disable
 User-enabled stalling when the microcontroller asserts the CPU halt flag during debug
Fig 2.7 Operation of Watchdog Timer

The watchdog timer can be configured to generate an interrupt to the controller on its first time out, and
to generate a reset signal on its second time-out. Once the watchdog timer has been configured, the
lock register can be written to prevent the timer configuration from being inadvertently altered.
2.7 Interrupts
The reader is aware that a microprocessor is connected to several input and output devices. It is
important at this point for us to know how a microprocessor manages these devices efficiently.
2.7.1 Introduction to Interrupts and Polling

A microprocessor executes instructions sequentially. Alongside, it is also connected to several
devices. Dataflow between these devices and the microprocessor has to be managed effectively.
There are two ways it is done in a microprocessor: either by using interrupts or by using polling.
Polling
Polling is a simple method of I/O access. In this method, the microcontroller continuously probes
whether the device requires attention, i.e. if there is data to be exchanged. A polling function or
subroutine is called repeatedly while a program is being executed. When the status of the device being
polled responds to the interrogation, a data exchange is initiated. The polling subroutine consumes

www.ti.com Interrupts
processing time from the presently executing task. This is a very inefficient way because I/O devices
do not always crave for attention from the microprocessor. But the microprocessor wastes valuable
processing time in unnecessarily polling of the devices.
Interrupts
However, in interrupt method, whenever a device requires the attention from the microprocessors, it
pings the microprocessor. This ping is called interrupt signal or sometimes interrupt request (IRQ).
Every IRQ is associated with a subroutine that needs to be executed within the microprocessor. This
subroutine is called interrupt service routine (ISR) or sometimes interrupt handler. The microprocessor
halts current program execution and attends to the IRQ by executing the ISR. Once execution of ISR
completes, the microprocessor resumes the halted task.
The current state of the microprocessor must be saved before it attends the IRQ in order to be able to
continue from where it was before the interrupt. To achieve this, the contents of all of its internal
registers, both general purpose and special registers, are required to be saved to a memory section
called the stack. On completion of the interrupt call, these register contents will be reinstated from the
stack. This allows the microprocessor to resume its originally halted task.
There are two types of interrupts namely software driven interrupts (SWI) and hardware driven
interrupts (HWI). SWIs are generated from within a currently executing program. They are triggered by
the interrupt opcode. A SWI will call a subroutine that allows a program to access certain lower level
service. HWIs are signals from a device to the microprocessor. The device sets an interrupt line in the
control bus high. Microprocessors have two types of hardware interrupts namely, non-maskable
interrupt (NMI) and interrupt request (INTR). An NMI has a very high priority and they demand
immediate execution. There is no option to ignore an NMI. NMI is exclusively used for events that are
regarded as having a higher priority or tragic consequences for the system operation. For example,
NMI can be initiated due to an interruption of power supply, a memory fault or pressing of the reset
button. An INTR may be generated by a number of different devices all of which are connected to the
single INTR control line. An INTR may or may not be attended by the microprocessor. If the
microprocessor is attending an interrupt, then no further interrupts, other than an NMI, will be
entertained until the current interrupt has been completed. A control signal is used by the
microprocessor to acknowledge an INTR. This control signal is called ACK or sometimes INTA.
2.7.2 Interrupt vector table

It is discussed in the previous section that when an interrupt occurs, the microprocessor runs an
associated ISR. IRQ is an input signal to the microprocessor. When a microprocessor receives an
IRQ, it pushes the PC register onto the stack and load address of the ISR onto the PC register. This
makes the microprocessor execute the ISR. These associated ISRs, corresponding to every interrupt,
become a part of the executable program. This executable is loaded in the memory of the device.
Under such circumstances, it becomes easier to manage the ISRs if there is a lookup table where
address locations of all ISRs are listed. This lookup table is called Interrupt vector table. Table 2.9
shows an interrupt vector table for ARM cortex-M microcontroller. In ARM microcontroller, there exist
256 interrupts. Out of these, some are hardware or peripheral generated IRQs and some are software
generated IRQs. However, first 15 interrupts, INT0 to INT15 are called the predefined interrupts. In
ARM Cortex-M microcontrollers, Interrupt vector table is an on-chip module, called as Nested Vector
Interrupt Controller (NVIC).
NVIC is an on-chip interrupt controller for ARM Cortex-M series microcontrollers. No other ARM series
has this on-chip NVIC. This means that the interrupt handling is primarily different in ARM Cortex-M
microcontrollers compared to other ARM microcontrollers

Table 2.9 Interrupt Vector Table for ARM Cortex M4
VECTOR NO. PRIORITY EXCEPTION TYPE VECTOR ADDRESS
0 - SP initial Value 0x0000.0000
1 -3 RESET 0x0000.0004
2 -2 NMI 0x0000.0008
3 -1 Hard Fault 0x0000.000C
4 Programmable Memory Management Fault 0x0000.0010
5 Programmable BUS Fault 0x0000.0014
Usage Fault (undefined instructions, divide

6 Programmable 0x0000.0018
by zero, unaligned memory access, etc.)
0x0000.001C to
7 - 10 - Reserved
0x0000.0028
11 Programmable SVCall 0x0000.002C
12 Programmable Debug Monitor 0x0000.0030
13 - Reserved 0x0000.0034
14 Programmable PendSV 0x0000.0038
15 Programmable SysTick 0x0000.003C
User Interrupts (interrupts generated from 0x0000.0040 to

16 -255 Programmable
peripherals and software) 0x0000.03FC
On system reset, the vector table is fixed at address 0x0000.0000.
2.7.3 Predefined Interrupts (INT0-INT15)

RESET
All ARM devices have a RESET pin which is invoked on device power-up or in case of warm reset.
This exception is a special exception and has the highest priority. On the assertion of Reset signal, the
execution stops immediately. When the Reset signal stops, execution starts from the address provided
by the Reset entry in the vector table i.e. 0x0000.0004. Hereby, to run a program on Reset, it is
necessary to place the program in 0x0000.0004 memory address.
NMI
In the ARM microcontroller, some pins are associated with hardware interrupts. They are often called
IRQs (interrupt request) and NMI (non-maskable interrupt). IRQ can be controlled by software masking
and unmasking. Unlike IRQ, NMI cannot be masked by software. This is why I is named as non-
maskable interrupt. As shown in Table 2.9, "INT 02" in ARM Cortex-M is used only for NMI. On
activation of NMI, the microcontroller load memory location 0x0000008 to program counter.
Hard Fault
All the classes of fault corresponding to a fault handler cannot be activated. This may be a result of the
fault handler being disabled or masked.

Memory Management Fault

It is caused by a memory protection unit violation. The violation can be caused by attempting to write
into a read only memory. An instruction fetch is invalid when it is fetched from non-executable region
of memory. In an ARM microcontroller with an on-chip MMU, the page fault can also be mapped into
the memory management fault.
Bus Fault
A bus fault is an exception that arises due to a memory-related fault for an instruction or data memory
transaction, such as a pre-fetch fault or a memory access fault. This fault can be enabled or disabled.
Usage Fault
Exception that occurs due to a fault associated with instruction execution. This includes undefined
instruction, illegal unaligned access, invalid state on instruction execution, or an error on exception
return may termed as usage fault. An unaligned address of a word or half-word memory access or
division by zero can cause a usage fault.
SVCall
A supervisor call (SVC) is an exception that is activated by the SVC instruction. In an operating
system, applications can use SVC instructions to contact OS kernel functions and device drivers. This
is a software interrupt since it was raised from software, and not from a Hardware or peripheral
exception.
PendSV
PendSV is pendable service call and interrupt-driven request for system-level service. PendSV is used
for framework switching when no other exception is active. The Interrupt Control and State (INTCTRL)
register is used to trigger PendSV. The PendSV is an interrupt and can wait until NVIC has time to
service it when other urgent higher priority interrupts are being taken care.
SysTick
A SysTick exception is generated by the system timer when it reaches zero and is enabled to generate
an interrupt. The software can also produce a SysTick exception using the Interrupt Control and State
(INTCTRL) register.
User Interrupts
This interrupt is an exception signaled either by a peripheral or by a software request and fed through
the NVIC based on their priority. All interrupts are asynchronous to instruction execution. In the
system, peripherals use interrupts to communicate with the processor. An ISR can be also propelled
as a result of an event at the peripheral devices. This may include timer timeout or completion of
analog-to-digital converter (ADC) conversion. Each peripheral device has a group of special function
registers that must be used to access the device for configuration. For a given peripheral interrupt to
take effect, the interrupt for that peripheral must be enabled.
/***************************************************************************
Aim: To understand how exceptions/interrupts work
***************************************************************************/
#include <stdint.h>
#include <stdbool.h>

#include "inc/tm4c123gh6pm.h"
#include "inc/hw_memmap.h"
#include "inc/hw_types.h"
#include "driverlib/sysctl.h"
#include "driverlib/interrupt.h"
#include "driverlib/gpio.h"
#include "driverlib/timer.h"
int main(void)
uint32_t ui32Period;
SysCtlClockSet(SYSCTL_SYSDIV_5|SYSCTL_USE_PLL|SYSCTL_XTAL_16MHZ|SYSCTL_OSC_M
AIN);
// SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOF);
GPIOPinTypeGPIOOutput(GPIO_PORTF_BASE, GPIO_PIN_1|GPIO_PIN_2|GPIO_PIN_3);
SysCtlPeripheralEnable(SYSCTL_PERIPH_TIMER0);
TimerConfigure(TIMER0_BASE, TIMER_CFG_PERIODIC);
ui32Period = (SysCtlClockGet() / 10) / 2;
TimerLoadSet(TIMER0_BASE, TIMER_A, ui32Period -1);
IntEnable(INT_TIMER0A);
TimerIntEnable(TIMER0_BASE, TIMER_TIMA_TIMEOUT);
IntMasterEnable();
TimerEnable(TIMER0_BASE, TIMER_A);
while(1)
{
}
}
void Timer0IntHandler(void)
{
// Clear the timer interrupt
TimerIntClear(TIMER0_BASE, TIMER_TIMA_TIMEOUT);
// Read the current state of the GPIO pin and
// write back the opposite state
if(GPIOPinRead(GPIO_PORTF_BASE, GPIO_PIN_2)) {
GPIOPinWrite(GPIO_PORTF_BASE, GPIO_PIN_1|GPIO_PIN_2|GPIO_PIN_3, 0);
}

Else {
GPIOPinWrite(GPIO_PORTF_BASE, GPIO_PIN_2, 4);
}
}
Fig 2.8 Flowchart for servicing timer interrupts

In the above program, we have commented following line of the code.
// SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOF);
This means that the code is accessing the peripheral without the peripheral clock being enabled. This
should generate an exception. We can see in figure 2.9 that when this code is executed, upon
suspension, execution has trapped inside the „FaultISR()‟ interrupt routine.
All of the exception ISRs are trapped in infinite loop in the provided code. This behavior of the program
should be avoided.
If the same code is run, only this time uncommenting un-commenting the „SysCtlPeripheralEnable‟
while building, then we can see the BLUE LED glow.

Low Power Microcontroller www.ti.com
Fig 2.9 Debug Window
2.8 Low Power Microcontroller
2.8.1 Need for Low Power Microcontroller

It is imperative for an embedded design to be low on its power consumption. Most embedded systems
and devices run on battery. Power demands are increasing rapidly, but battery capacity cannot keep
up with its pace. Therefore, a microcontroller which inherently consumes very less power is always
encouraging. However, embedded systems engineers usually need to optimize between power and
performance. Power and performance are inversely proportional to each other.
Let us consider an example where we are to design a system to monitor water level in a tank. When
the water level reduces below a particular level, water should be pumped in. There are many ways to
go about this design.
2.8.2 Hibernation Module on TivaTM Microcontrollers

This module manages to remove and restore power to the microcontroller and its associated
peripherals. This provides a means for reducing system power consumption. When the processor and
peripherals are idle, power can be completely removed if the Hibernation module is only the one
powered.
Fig 2.10 Power vs Flexibility

www.ti.com Low Power Microcontroller
To achieve this, the Hibernation (HiB) Module is added with following features:
(i) A Real-Time Clock (RTC) to be used for wake events
(ii) A battery backed SRAM for storing and restoring processor state. The SRAM consists of 16 32-bit
word memory.
The RTC is a 32- bit seconds counter and 15- bit sub second counter. It also has an add-in trim
capability for precision control over time. The Microprocessor has a dedicated pin for waking using
external signal. The RTC and the SRAM are operational only if there is a valid battery voltage. There is
a VDD30N mode, which provides GPIO pin state during hibernation of the device.
Thus we are actually shutting the power off for the device or part at the lowest power mode. Under
such circumstances, it is safe to assume that in the wake up we are actually coming out of reset. But
this will allow the device to the keep the GPIO pins in their state without resetting them. A mechanism
for power control is used to shut down the part. In TM4C123GH6PM we have an on-chip power
controller which controls power for the CPU only. There is also a pin output from the microcontroller
which is used for system power control.
It should be duly noted that in TIVA Launchpad, the battery voltage is directly connected to the
processor voltage and it is always valid. But in a custom design with TM4C123GH6PM microcontroller
running on a battery, if the battery voltage is not valid, it will not go into hibernation mode.
Fig 2.11 Block diagram of Hibernation module

The Hibernation module of TM4C123GH6PM provides two mechanisms for power control:
 The first mechanism uses internal switches to control power to the Cortex-M4F.

 The second mechanism controls the power to the microcontroller with a control signal (HIB)
that signals an external voltage regulator to turn on or off.
The Hibernation module power source is determined dynamically. The supply voltage of the
Hibernation module is the larger of the main voltage source (VDD) or the battery voltage source
(VBAT).
Hibernate mode can be entered through one of two ways:
 The user initiates hibernation by setting the HIBREQ bit in the Hibernation Control (HIBCTL)
register.
 Power is arbitrarily removed from VDD while a valid VBAT is applied
Power Modes
There are six power modes in which TM4C123GH6PM operates as shown in the below table. They are
Run, Sleep, Deep Sleep, Hibernate with VDD3ON, Hibernate with RTC, and Hibernate without RTC.
To understand all these modes and compare them, it is necessary to analyze them under a condition.
Let us consider that the device is operating at 40 MHz system clock with PLL.
Table 2.10: Power Modes of Tiva
2.8.3 Programming Hibernation Module

This code can be compiled and executed on a TIVA Launchpad. When this code executes, the
GREEN LED glows continuously. We can observe that after 4s, the system automatically goes into

www.ti.com Low Power Microcontroller
sleep and the LED stops glowing. When SW2 (switch on the right hand bottom corner of the
Launchpad) is pressed, it triggers a wake event and the GREEN LED starts glowing again. Now, after
4s, the system goes to sleep again. This shows that, the wakeup process is the same as powering up.
When the code starts, we can determine that the processor woke from hibernation and restore the
processor state from the memory.
Flow chart:
Fig 2.12. Flowchart for programming hibernation module
#include <stdint.h>
#include <stdbool.h>
#include "utils/ustdlib.h"
#include "inc/hw_types.h"
#include "inc/hw_memmap.h"
#include "driverlib/sysctl.h"

#include "driverlib/pin_map.h"
#include "driverlib/debug.h"
#include "driverlib/hibernate.h"
#include "driverlib/gpio.h"
int main(void)
{
SysCtlClockSet(SYSCTL_SYSDIV_5|SYSCTL_USE_PLL|SYSCTL_XTAL_16MHZ|SYSCTL_OSC_
MAIN); // System Clock set to 40 MHz
/***********************************************************************************
* Use the green LED (2=red=pin1, 4=blue=pin2 and 8=green=pin3) as an
* indicator that the device is in hibernation (off for hibernate and on for wake).
*
***********************************************************************************/
SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOF);
GPIOPinTypeGPIOOutput(GPIO_PORTF_BASE, GPIO_PIN_1|GPIO_PIN_2|GPIO_PIN_3);
GPIOPinWrite(GPIO_PORTF_BASE,GPIO_PIN_1|GPIO_PIN_2|GPIO_PIN_3, 0x08);
SysCtlPeripheralEnable(SYSCTL_PERIPH_HIBERNATE); //enable the hibernation module

HibernateEnableExpClk(SysCtlClockGet()); //defines the clock supplied to the hibernation
module
HibernateGPIORetentionEnable(); //enables the GPIO pin state to be maintained during
hibernation
//and remain active even when waking from hibernation.
SysCtlDelay(64000000); //delay 4 seconds for you to observe the LED
HibernateWakeSet(HIBERNATE_WAKE_PIN); //wake condition to the wake pin is set
GPIOPinWrite(GPIO_PORTF_BASE,GPIO_PIN_3, 0x00);//turn the green LED off before the device
goes to sleep
HibernateRequest(); //HibernateRequest()function requests the Hibernation module

//to disable the external regulator, removing power from the
//processor and all peripherals.
while(1)
{
}
}

www.ti.com Summary
2.9 Summary
In this chapter the readers will be able to have an understanding of programming the TIVA
microcontroller using TIVAWare Peripheral driver library. The chapter describes the ARM architecture
as a programming model with the operating states and modes supported by the ARM architecture.
ARM and Thumb operating states of TM4C123x are also described rendering a detailed explanation of
the instruction set of ARM Cortex- M4 core. The chapter also discusses the interrupt and exception
handling mechanisms in TIVA microcontroller. An important difference between TM4C123x and
TM4C129x series of microcontrollers of TIVA family is also explained emphasizing the application
development from user‟s viewpoint.
2.10

2.11 Review questions

1. What are the reasons for C language is widely accepted among embedded design engineers?
2. What is data type? Name all the data types supported in ISO C90.
3. What is bitwise operation? Discuss the bit-wise shift and masking operation.
4. Explain the various development tools in the TIVA c series programming.
5. Discuss the memory mapping of the TM4C123GH6PM in detail.
6. How many GPIO‟s are there in TIVA? Discuss the features of GPIO of TIVA Launchpad in
detail.
7. What is watchdog timer? How it works in TIVA?
8. What is an interrupt? Discuss the various hardware and software type of interrupts in detail.
9. What is low power microcontroller?
10. What is the Hibernation Module on Tiva Microcontrollers?

Chapter 3
Timers, PWM and Mixed Signal Processing
Chapter 2 set the base for GPIO configurations according to application, interrupt handling and the role of
watchdog timer and low power mode of TIVA using hibernation module. This chapter covers applications
of timer/counters in home automation, traffic light control etc. The role of PWM in applications such as
speed control of DC motor is discussed in this chapter.
By the end of this chapter, readers can expect to have a good understanding of timers and their
importance in embedded systems. They will also acquire knowledge about DMA how they provide fast
access to memory; importance of ADC and how it works in different applications and configurations with
TIVA.
The chapter also covers PWM mode and its application area as well as Quadrature Encoder Interface and
its applications.
Topic Page
3.1 Introduction.......................................................................................................................................... 86
3.2 Timers ................................................................................................................................................. 86
3.3 Analog to Digital Converter (ADC) ...................................................................................................... 94
3.4 Analog Comparators ........................................................................................................................... 97
3.5 Analog Interfacing and Data Acquisition ........................................................................................... 100
3.6 Direct Memory Access (DMA) ........................................................................................................... 102
3.7 Pulse Width Modulation .................................................................................................................... 104
3.8 Quadrature Encoder Interface (QEI) ................................................................................................. 109
3.9 Summary ........................................................................................................................................... 114
Timers, PWM and Mixed Signal Processing 85

3.1 Introduction
In our daily life, we have numerous applications of embedded systems in areas such as automobiles,
communication, home appliances etc. Consider an example of a washing machine, which uses various
modules such as temperature sensor, motor control, display systems and timer.
Fig 3.1. Automatic Washing Machine

A washing machine allows users to adjust motor speed, water temperature, washing time etc. Pulse
width modulation provides motor control technology, high-resolution timers help keep track of washing
time. Operation and configuration of pulse width modulation (PWM) module of TIVA C series finds
applications in motion control, voltage regulation in inverter applications, audio effects & amplifications,
power delivery etc.
Data acquisition is the major component of any data gathering and data logging applications, which
require the support of analog comparators, high resolution ADCs, DAC etc. Most automotive
applications require sophisticated control in term of the speed and direction of the motor. Quadrature
Encoder Interface (QEI) finds applications in automotive, motor control, mobile robot.
3.2 Timers
Timers are basic constituents of most microcontrollers. Today, just about every microcontroller comes
with one or more built-in timers. These are extremely useful to the embedded programmer - perhaps
second in usefulness only to GPIO. The timer can be described as the counter hardware and can
usually be constructed to count either regular or irregular clock pulses. Depending on the above
usage, it can be a timer or a counter respectively.
Sometimes, timers may also be termed as “hardware timers” to distinguish them from software timers.
Software timers can be described as a stream of bits of software that achieve some timing function.
The TM4C123GH6PM General-Purpose Timer Module (GPTM) contains six 16/32-bit GPTM blocks
and six 32/64-bit Wide GPTM blocks. These programmable timers can be used to count or time
external events that drive the Timer input pins. Timers can also be used to trigger μDMA transfers, to
trigger analog-to-digital conversions (ADC) when a time-out occurs in periodic and one-shot modes.
The GPT Module is one timing resource available on the Tiva™ C Series microcontrollers. Other timer
resources include the System Timer (SysTick) and the PWM timer in PWM modules.
86 Timers, PWM and Mixed Signal Processing

www.ti.com Timers
The General-Purpose Timer Module (GPTM) blocks with the following functional options:
 16/32-bit operating modes:
 16- or 32-bit programmable one-shot timer
 16- or 32-bit programmable periodic timer
 16-bit general-purpose timer with an 8-bit prescaler
 32-bit Real-Time Clock (RTC) when using an external 32.768-KHz clock as the input
 16-bit input-edge count- or time-capture modes with an 8-bit prescaler
 16-bit PWM mode with an 8-bit prescaler and software-programmable output inversion of
the PWM signal
 32/64-bit operating modes:
 32- or 64-bit programmable one-shot timer
 32- or 64-bit programmable periodic timer
 32-bit general-purpose timer with a 16-bit prescaler
 64-bit Real-Time Clock (RTC) when using an external 32.768-KHz clock as the input
 32-bit input-edge count- or time-capture modes with a16-bit prescaler
 32-bit PWM mode with a 16-bit prescaler and software-programmable output inversion of
the PWM signal
 Count up or down
 Twelve 16/32-bit Capture Compare PWM pins (CCP)
 Twelve 32/64-bit Capture Compare PWM pins (CCP)
 Daisy chaining of timer modules to allow a single timer to initiate multiple timing events
 Timer synchronization allows selected timers to start counting on the same clock cycle
 ADC event trigger
 User-enabled stalling when the microcontroller asserts CPU Halt flag during debug (excluding
RTC mode)
 Ability to determine the elapsed time between the assertion of the timer interrupt and entry into
the interrupt service routine
 Efficient transfers using Micro Direct Memory Access Controller (μDMA)
 Dedicated channel for each timer
 Burst request generated on timer interrupt

Timers www.ti.com
Fig 3.2. GPTM block diagram

The below table lists the external signals of the GP Timer module and describes the function of each.
The GP Timer signals are alternate functions for some GPIO signals and default to be GPIO signals at
reset. The column in the table below titled "Pin Mux/Pin Assignment" lists the possible GPIO pin
placements for these GP Timer signals. The TTL designation indicates the pin has TTL-compatible
voltage levels.
Table 3.1: General purpose Timer signals

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3.2.1 Basic Timers/Counters

A standard timer will comprise a pre-scaler, an N-bit timer/counter register, one or more N-bit capture
and compare registers. Usually N is 8, 16 or 32 bits. Along with these, there will also be registers for
control and status units responsible to configure and monitor the timer.
To count the incoming pulses, an up-counter is deployed as fundamental hardware. A counter can be
converted to a timer by fixing incoming pulses and setting a known frequency. Also note that the size
in bits of a timer should not be related directly to the size in bits of the CPU architecture. An 8-bit
microcontroller can have 16-bit timers (in fact mostly do), and a 32-bit microcontroller can have 16-bit
timers (and some do).
Pre-scaler
The pre-scaler takes the basic timer clock frequency as an input and divides it by some value
depending upon the circuit requirements before feeding it to the timer, to configure the pre-scaler
register(s). This configuration might be limited to a few fixed values (powers of 2), or integers from 1
to 2^m, where m is the number of pre-scaler bits.
Pre-scaler is used to set the clock rate of the timer as per your desire. This provides a flexibility in
resolution (high clock rate implies better resolution) and range (high clock rate causes quicker overflow
of timer). For instance, we cannot get 1us resolution and a 1sec maximum period using a 16-bit timer.
If we want 1us resolution we are restricted to about 65ms maximum period. If we want 1sec maximum
period, we are bounded to about 16us resolution. The pre-scaler allows us to manage resolution and
maximum period to fit your needs.
Timer Register
The timer register can be defined as hardware with an N-bit up-counter, which has accessibility of read
and write command rights for the current count value, and to stop or reset the counter. As discussed,
the timer is driven by the pre-scaler output. The regular pulses which drive the timer, irrespective of
their source are often called “ticks”. We may understand now that it is not necessary for a timer to time
in seconds or milliseconds, they do time in ticks. This enables us the elasticity to control the rate of
these ticks, depending upon the hardware and software configuration. We may construct our design to
some human-friendly value such as e.g. 1 millisecond or 1 microsecond, or any other design specified
units.

Timers www.ti.com
Capture Registers
A capture registers are those hardware which can be routinely loaded with the current counter value
upon the occurrence of some event, usually a change on an input pin. Therefore the capture register
is used to capture a “snapshot” of the timer at the instant when the event occurs. A capture event can
also be constructed to produce an interrupt, and the Interrupt Service Routines (ISR) can save or else
use the just-captured timer snapshot.
There is no latency problem in snapshot value as the capture occurs in hardware, which would be if
the capture was done in software. Capture registers can be used to time intervals between pulses or
input signals, to determine the high and low times of input signals.
Compare/Match Registers
Compare or match registers hold a value against which the current timer value is routinely compared
and shoots to trigger an event when the value in two registers matches.
 If the timer/counter is configured as a timer, we can generate events at known and precise
times. Events can be like output pin changes and/or interrupts and/or timer resets.
 If the timer/counter is configured as a counter, the compare registers can generate events
based on preset counts being achieved.
For instance, the compare registers can be used to generate a timer “tick”, a fixed timer interrupt used
for system software timing. For example, if a 2ms tick is desired, and the timer is configured with a
0.5us clock, setting a compare register to 4000 will cause a compare event after 2ms. If we set the
compare event to generate an interrupt as well as to reset the timer to 0, the result will be an endless
stream of 2ms interrupts.
Another notable use of a compare register can be to generate a pulse with variable width. Set an
output high/low when the timer is at 0, configure the compare register with value of pulse width, and on
the compare event set the output low/high. We may use a second compare register with a larger value,
to set the pulse interval by retuning the timer on compare.
3.2.2 Real Time Clock (RTC)

RTC is a mainframe clock that keeps track of the current time. RTCs are present in approximately
every electronic device which needs to maintain accurate time. The term RTC came into picture to
avoid confusion with regular hardware clocks which are merely signals that administer digital
electronics, and do not count time in human units.
Benefits of using RTC:
 Low power consumption
 Liberates the main system for time-critical tasks
 Increases accuracy if compared to other methods
A GPS receiver can cut down its startup time by comparing the current time as per its RTC, with the
moment of last valid signal. If it has been less than a few hours, then the previous ephemeris is still
usable.
With the option of alternative power source with RTCs, they can continue to keep time while the
primary power source being unavailable. This alternate source may be a lithium battery or a super-
capacitor.

www.ti.com Timers
Fig 3.3. Real Time Clock with external power source
3.2.3 Timing Generation and Measurement

In various microprocessor systems, it is desirable to use frequency to formulate measurements, rather
than the digital output of an ADC. Motivations for using frequency measurement include:
 In systems with ground offsets, signals can be capacitively coupled or optically isolated to
reduce ground loops and other damaging effects.
 Noise introduced during analog transmission may be eliminated by transmitting a logic-level
frequency signal instead.
 Measuring frequency instead of analog values may allow an uncomplicated microprocessor to
be used, since an ADC is not required.
Today mostly, we can convert an analog (physical quantity) input, such as temperature, to a time-
based signal that can be calculated with a microprocessor.
Microprocessor with Capture Capability
In a microprocessor with capture capability, the sensor output and microprocessor input can be
connected for pulse capture. In the block diagram below, one such capture system is described. Here,
a 16-bit register is used to capture a free-running, 16-bit counter when the input frequency changes
from the lower state to higher state. At the same instance, a short pulse is triggered to reset the
counter. In the illustration shown in Fig 3.4 below, one time period of the input is 90µs and the second
period is 100µs. The counter here will count up 90 counts for the first period and 100 counts for the
second period.
The count is recited by the microprocessor to calculate the period and hence the temperature.

Timers www.ti.com
Fig 3.4. Frequency Based Measurement System

Microprocessor without Capture Capability
To perform measurements similar to discussed previously on Microprocessors without capture
capability, we need to construct a counter free-run and join the frequency signal to an interrupt input.
Here, the counter can be an external or internal part that is clocked from an imitative of the
microprocessor clock. As an interrupt triggers, read and reset are performed by software to the
counter. Due to variable interrupt latency, this method is somewhat less accurate than the capture
method. In situation, when system latency should not affected by other interrupts, and also
microprocessor is available with a non-maskable interrupt input, then this should be used for the
frequency input.
The frequency input can be linked to the input of a timer, and the timer should be programmed to
increment with an external clock. The microprocessor then fetch/read the timer value on a periodic
basis to get the number of counts that arose in the measurement period. Issues like Interrupt latency
can be reduced by joining a period-based signal to a counter (running on the microprocessor clock),
but counts only when the input is high.
The counter will
 Count up while the input is high
 Hold the count while the input is low
The processor can read the count during the count is low. Until the count goes high again, the
processor keeps on reading. Hence, the count will be accurate.

www.ti.com Timers
Measuring Period Based Inputs with Free Running Counter
Fig 3.5. (a) Period based input Read with free running counter
Fig 3.5. (b) Period based input Read with counter that increments only while gate input is HIGH
(Gate connected to Period Based Input)

Analog to Digital Converter www.ti.com
3.3 Analog to Digital Converter (ADC)

ADCs are peripherals that convert a continuous analog voltage to a discrete digital number. In order to
convert to digital, the signal is sampled at higher frequencies to minimize the signal loss. Then the
amplitude at those sampled moments is converted with respect to their quantization level. Finally these
levels and moments are entitled to a unique code, which are simply the combinations of 0‟s and 1‟s –
this is called encoding.
Fig 3.6. Block Diagram of working of an ADC

Example:
Let us examine the working of ADC in Tiva – TM4C123GH6PM microcontroller.
The TM4C123GH6PM ADC module features 12-bit conversion resolution and supports 12 input
channels, plus an internal temperature sensor. Each ADC module contains four programmable
sequencers allowing the sampling of multiple analog input sources without controller intervention. Each
sample sequencer provides flexible programming with fully configurable input source, trigger events,
interrupt generation, and sequencer priority. In addition, the conversion value can optionally be
diverted to a digital comparator module. Each ADC module provides eight digital comparators. Each
digital comparator evaluates the ADC conversion value against its two user-defined values to
determine the operational range of the signal. The trigger source for ADC0 and ADC1 may be
independent or the two ADC modules may operate from the same trigger source and operate on the
same or different inputs. A phase shifter can delay the start of sampling by a specified phase angle.
When using both ADC modules, it is possible to configure the converters to start the conversions
coincidentally or within a relative phase from each other.
Here the Analog-to-Digital Converter (ADC) module uses a Successive Approximation Register (SAR)
architecture to deliver a 12-bit, low-power, high-precision conversion value. The successive
approximation uses a switched capacitor array to perform the dual functions of sampling and holding
the signal as well as providing the 12-bit DAC operation.
Fig 3.7. Implementation of two ADC blocks

www.ti.com Analog to Digital Converter
3.3.1 Block Diagram
Fig 3.8 ADC Module Block Diagram

Signal description: The below table lists the external signals of the ADC module and describes the
function of each. The AINx signals are analog functions for some GPIO signals.
Table 3.2 ADC signals with GPIO pins

Analog to Digital Converter www.ti.com
3.3.2 Functional Description

Sample Sequencers
The sampling control and data capture is handled by the sample sequencers. All of the sequencers are
identical in implementation except for the number of samples that can be captured and the depth of the
FIFO. Each sample that is captured is stored in the FIFO. In this implementation, each FIFO entry is a
32-bit word, with the lower 12 bits containing the conversion result.
After a sample sequence completes execution, the result data can be retrieved from the ADC Sample
Sequence Result FIFO registers. The FIFOs are simple circular buffers that read a single address to
"pop" result data. For software debug purposes, the positions of the FIFO head and tail pointers are
visible in the ADC Sample Sequence FIFO Status registers along with FULL and EMPTY status flags.
If a write is attempted when the FIFO is full, the write does not occur and an overflow condition is
indicated.
Following Table shows the maximum number of samples that each sequencer can capture and its
corresponding FIFO depth.
Table 3.3: Samples and FIFO Depth of Sequencers
Sequencer Number of Samples Depth of FIFO

SS3 1 1
SS2 4 4
SS1 4 4
SS0 8 8
Hardware Sample Averaging Circuit

Using the hardware averaging circuit we can generate higher precision results. However, the improved
results are at the cost of throughput. Up to 64 samples can be amassed and averaged to form a single
data entry in the sequencer FIFO. Throughput is reduced proportionally to the number of samples in
the averaging calculation. For example, if the averaging circuit is configured to average 16 samples,
the throughput is decreased by a factor of 16.
By default the averaging circuit is off, and all data from the converter passes through to the sequencer
FIFO. The ADC Sample Averaging Control register controls the averaging hardware. A single
averaging circuit has been implemented, hence, averaging received by all input channels is same
whether they are single-ended or differential.
Digital Comparator Unit
An ADC is frequently used to sample an external signal and to analyze/monitor its value to verify that it
remains in a given range. Each module is provided with eight digital comparators, to power-up this
monitoring procedure and reduce the processor overhead.
Conversions from the ADC that are directed to the digital comparators are equated against the user
programmable limits in the comparator range registers. The ADC can be configured to generate an
interrupt depending on whether the ADC is operating within the low, mid or high-band region
configured in the ADCDCCMPn bit fields. The four operational modes of digital comparators (Once,
Always, Hysteresis Once, Hysteresis Always) can be additionally applied to the interrupt configuration.

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Interrupts
The ADC module's interrupt signals are controlled by the state of the MASK bits in the ADC Interrupt
Mask (ADCIM) register. Interrupt status can be viewed at two locations: the ADC Raw Interrupt
Status (ADCRIS) register, which shows the raw status of the various interrupt signals; and the ADC
Interrupt Status and Clear (ADCISC) register, which shows active interrupts that are enabled by the
ADCIM register. Sequencer interrupts are cleared by writing a 1 to the corresponding IN bit in
ADCISC. Digital comparator interrupts are cleared by writing a 1 to the ADC Digital Comparator
Interrupt Status and Clear (ADCDCISC) register.
3.4 Analog Comparators

An analog comparator is a peripheral that compares two analog voltages and provides a logical output
that signals the comparison result. The comparator can provide its output to a device pin, acting as a
replacement for an analog comparator on the board. The comparator can also signal the application
through interrupts or trigger the start of a sample sequence in the ADC. The interrupt generation and
ADC triggering logic is separate and independent. This flexibility means, for example, that an interrupt
can be generated on a rising edge and the ADC triggered on a falling edge.
The TM4C123GH6PM microcontroller provides two independent integrated analog comparators with
the following functions:
 Compare external pin input to external pin input or to internal programmable voltage reference
 Compare a test voltage against any one of the following voltages:
o An individual external reference voltage
o A shared single external reference voltage
o A shared internal reference voltage

The comparator compares the VIN- and VIN+ inputs to produce an output, VOUT.
o Vout = 1, if Vin- < Vin+
o Vout = 0, if Vin- > Vin+
As shown in Figure 3.9 below, the input source for Vin- is an external input, Cn-, where n is the analog
comparator number. In addition to an external input, Cn+, input sources for Vin+ can be the C0+ or an
internal reference, VIREF.
A comparator is configured through two status/control registers, Analog Comparator Control
(ACCTL) and Status (ACSTAT). The internal reference is configured through one control register,
Reference Voltage Control (ACREFCTL). Interrupt status and control are configured through three
registers, Masked Interrupt Status (ACMIS), Raw Interrupt Status (ACRIS), and Interrupt Enable
(ACINTEN).
(Please note that first two character of registers used here designates to Analog comparator.)

Analog Comparators www.ti.com
Fig 3.9 Structure of Comparator Unit

Typically, the comparator output is used internally to generate an interrupt as controlled by the ISEN
bit in the control register (ACCTL). The output may also be used to drive one of the external pins
(Cno), or generate an ADC trigger.

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3.4.2 Analog Comparator Module Block Diagram
Fig 3.10. Analog comparator module block diagram

Note: This block diagram depicts the maximum number of analog comparators and comparator
outputs for the family of microcontrollers; the number for this specific device may vary.

Analog Interfacing and Data Acquisition www.ti.com
3.5 Analog Interfacing and Data Acquisition
3.5.1 Analog Interfacing

Figure 3.11 shows a typical sensor network. You will find a number of sensors and actuators
connected to a common bus to share information and derive a collective decision. This is a complex
embedded system. Digital camera falls under such a system.
Fig 3.11. Analog Interfacing Network
Stages of Analog Signal Processing

While the signal being analog in nature, we need to process it at various levels to gather information of
need and minimize the loss of data. This processing can be defined in following stages:
 Stage-1 Signal Amplification and Conditioning;
 Stage-2 Anti-aliasing Filter;
 Stage-3 Sample and Hold;
 Stage-4 Analog to Digital Converter;
 Stage-5 Digital Processing and Data manipulation in a Processor;
 Stage-6 Processed Digital Values are temporarily stored in a latch before D-A conversion;
 Stage-7 Digital to Analog Conversion;
 Stage-8 Removal of Glitches and Spikes;
 Stage-9 Final Low pass filtering

www.ti.com Analog Interfacing and Data Acquisition
Fig 3.12. The Analog-Digital-Analog signal path with real time processing
3.5.2 Data Acquisition

Data acquisition (DAS or DAQ) is the route of sampling signals that measure physical conditions and
converting the resulting samples into digital quantized values that can be deployed by a Computer on
Chip (i.e. microcontrollers). DAQ systems typically convert analog signals into digital values for
processing. The components of this system include:
 Sensors to convert physical quantities to electrical signals.
 Circuitry to convert sensor signals to a form that can be transformed to digital values.
 ADCs, which convert above transformed form to digital values.
Few software packages (Code Composer Studio, KIEL, etc.) provide all the necessary tools to attain
data from different hardware equipment. These tools are designed by the scientific community where
multifaceted experiment requires fast, reliable, flexible and adaptable software. These packages are
typically custom fit but more general data acquisition packages like the Maximum Integrated DAQ can
be easily personalized and are used in numerous physics experiments worldwide.
Sources and Systems
Data acquisition begins with the physical property or phenomenon to be calculated, like temperature,
fluid flow, light intensity, force, and gas pressure. Irrespective of the categories of physical properties
to be measured, that physical state must be converted into a unified form so that data acquisition
system can sample it. Sensors are required for such task of performing transformations. A DAQ
system is a group of software and hardware that allow us to control or measure physical
characteristics of real world quantities. The complete system consists of DAQ hardware, signal
conditioning hardware, sensors, actuators and a computer running DAQ software.
A hardware device, sensor, is used to converts a physical property into an equivalent electrical signal.
An acquisition system can measure different physical characteristics depending on the sensors‟ design
to detect those properties. If the signal from the transducer is not suitable for the Acquisition hardware,
then Signal conditioning becomes necessary. In such cases, the signal may need conditioning like
filtering, amplification, bridge completion, providing current or voltage excitation to the sensor,
isolation, linearization, etc.
DAQ Hardware
DAQ hardware usually interfaces between the microcontroller and signal. It could be in the form of
modules that can be coupled to the GPIO ports in microcontroller board, whether in parallel or serial
mode.

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DAQ cards mostly contain multiple components like ADC, DAC, multiplexer, TTL-IO, RAM, high speed
timers, etc. A controller is more flexible and inexpensive than a processor, so that it is allowable to
block it with simple polling loops. For example: received a trigger, starting the Analog to Digital
Conversion, matching up the time, waiting for the ADC to finish, storing values to RAM, switch
multiplexer, getting TTL input.
DAQ Device Drivers
In order to make the DAQ hardware work with a microcontroller unit, device drivers are needed. The
device driver executes low-level register reads and writes on the hardware, while exposing API for
developing user applications in a variety of programming environments. These drivers can be coded in
C or assembly language to let the MCU communicate with physical devices connected to it.
3.6 Direct Memory Access (DMA)

Direct Memory Access is a way of streamlining transfers of large blocks of data between two different
segments of memory or between an I/O device and memory. Reading from disk and store it in memory
is a kind of operation we talking about. For this we may prefer either of two mentioned below:
 The processor can read each byte at a time from the memory into a register, then store the
contents of the register to the suitable memory location. For each byte,
o processor must read an instruction,
o instruction decoding,
o read the data,
o execute read for next part of instruction,
o decode the instruction,
o Store the data.
Then the process starts over again for the next byte.
 The second option is a special device, called a DMA controller (DMAC), performs high-speed
transfers between memory and I/O devices. It is typically used in moving large sized data
clusters around the system. Using DMAC, we can bypass the processor by creating a channel
between the memory and the I/O device. Thus, data is read from the I/O device and written
into memory without executing the code to perform the transfer on a byte-by-byte basis.
3.6.1 DMA Controller

A DMA controller is a device that is programmed to perform data transfers (sequentially) on behalf of
the CPU. A DMA controller is allowed to access memory directly and is used to transfer data from one
address/location to another. It may be an I/O device address or a memory address. A DMA controller
handles several DMA channels. Each of these can be used as an individual or as a group,
programmed to perform these DMA transfers. Devices (typically I/O peripherals) that requires DMA
mode of data transfer must send a hardware DMA request (DRQ). This DMA request signal for each
channel is directed to the DMA controller. This signal is monitored and responded in the same way as
processor handles interrupts. When the DMA controller receives a DMA request, it responds by
performing data transfers from that I/O device into system memory or vice versa. DMA Channels must
be enabled prior to this by the processor for the DMA controller to respond to DMA requests. We may
program DMA channel to set conditions like, number of transfers to be performed, transfer modes to
be used, and memory locations to be accessed. Generally, A DMA controller shares the system
memory and I/O bus with the CPU which has both bus master and slave capability.

www.ti.com Direct Memory Acces
In bus master mode, the system bus is acquired by the DMA controller from the CPU to perform the
DMA transfers. This process is also referred to cycle stealing, as the CPU frees the system bus during
the transfer.
In bus slave mode, the CPU access DMA controller, to program its internal registers for DMA transfers.
The internal registers contain source and destination address registers along with transfer count
registers for each DMA channel. It also contains control and status registers.
Fig 3.13. The DMA controller Architecture
3.6.2 Types of DMA

There are four basic types of DMA:
 Standard block transfer is accomplished by the DMA controller executing a sequence of
memory transfers.
These transfers involve:
o a load operation from a source address
o a store operation to a destination address

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This type of transfer is initiated under software control and is preferred for moving data from one region
of memory to another region.
 Demand-mode transfer is analogous to standard mode apart from that the transfer is
controlled by an external device. This mode of transfer is used to move data between I/O and
memory or vice versa. The Input/output device requests and synchronizes the movement of
data.
 Data-chaining transfers allow DMA transfers to be accomplished as indicated by a linked list

in memory. The transfer is initiated by designating a pointer to a descriptor in memory. The
descriptor is a tabular source for specifying byte count, source and destination address, and
next descriptor address. The DMA Controller picks essential information for transfer from this
table and initiates data movement. The transfer mode remains high until the number of
transferred bytes equals the entry in the byte count field. Once finished, the pointer to the next
descriptor is loaded and continues until a null pointer is found.
 Fly-by transfer is high-speed data movement system. Unlike conventional DMA transfers, this
mode moves data from source to destination in a single access (i.e., the data is not read into
the processor before reaching the destination). Here, memory and I/O are provided with
different bus control signals. For instance, memory is given a read request at the same time
that an I/O device is given a write request. Data moves from the memory device straight into
the I/O device.
3.7 Pulse Width Modulation

Pulse width modulation (PWM) is a simple but powerful technique of using a rectangular digital
waveform to control an analog variable or simply controlling analog circuits with a microprocessor's
digital outputs. PWM is employed in a wide variety of applications, from measurement &
communications to power control and conversion.
3.7.1 PWM using TIVA TM4C123HG6PM

TM4C123GH6PM PWM module provides a great deal of flexibility and can generate simple PWM
signals, such as those required by a simple charge pump as well as paired PWM signals with dead-
band delays, such as those required by a half-H bridge driver. Three generator blocks can also
generate the full six channels of gate controls required by a 3-phase inverter bridge.
Each PWM generator block has the following features:
 One fault-condition handling inputs to quickly provide low-latency shutdown and prevent
damage to the motor being controlled, for a total of two inputs
 One 16-bit counter
o Runs in Down or Up/Down mode
o Output frequency controlled by a 16-bit load value
o Load value updates can be synchronized
o Produces output signals at zero and load value
 Two PWM comparators
o Comparator value updates can be synchronized
o Produces output signals on match
 PWM signal generator
o Output PWM signal is constructed based on actions taken as a result of the counter and
PWM comparator output signals
o Produces two independent PWM signals

www.ti.com Pulse Width Modulation
 Dead-band generator
o Produces two PWM signals with programmable dead-band delays suitable for driving a
half-H bridge.
o Can be bypassed, leaving input PWM signals unmodified.
 Can initiate an ADC sample sequence
The control block determines the polarity of the PWM signals and which signals are passed through to
the pins. The output of the PWM generation blocks are managed by the output control block before
being passed to the device pins.
3.7.2 Block Diagram

TM4C123GH6PM controller contains two PWM modules, each with four generator blocks that
generate eight independent PWM signals or four paired PWM signals with dead-band delays inserted.
TM4C123GH6PM controller contains two PWM modules, each with four generator blocks that
generate eight independent PWM signals or four paired PWM signals with dead-band delays inserted.
Fig 3.14. PWM Module Block Diagram

Fig 3.15. PWM Generator Block Diagram

Clock Configuration
The PWM has two clock source options:
 The System Clock
 A pre divided System Clock
The clock source is selected by programming the USPWMDIV bit in the Run-Mode Clock
Configuration (RCC) register. The PWMDIV bit field specifies the divisor of the system clock that is
used to create the PWM Clock.
PWM Timer
The timer in each PWM generator runs in one of two modes: Count-Down mode or Count-Up/Down
mode. In Count-Down mode, the timer counts from the load value to zero, goes back to the load value,
and continues counting down. In Count-Up/Down mode, the timer counts from zero up to the load
value, back down to zero, back up to the load value, and so on. Generally, Count-Down mode is used
for generating left- or right-aligned PWM signals, while the Count-Up/Down mode is used for
generating center-aligned PWM signals.
The timers output three signals that are used in the PWM generation process: the direction signal (this
is always Low in Count-Down mode, but alternates between low and high in Count-Up/Down mode), a
single-clock-cycle-width High pulse when the counter is zero, and a single-clock-cycle-width High
pulse when the counter is equal to the load value. Note that in Count-Down mode, the zero pulse is

www.ti.com Pulse Width Modulation
immediately followed by the load pulse. In the figures in this chapter, these signals are labelled "dir,"
"zero," and "load."
PWM Comparators
Each PWM generator has two comparators that monitor the value of the counter, when either
comparator matches the counter, they output a single-clock-cycle-width High pulse, labeled "cmpA"
and "cmpB" in the figures in this chapter. When in Count-Up/Down mode, these comparators match
both when counting up and when counting down, and thus are qualified by the counter direction signal.
These qualified pulses are used in the PWM generation process. If either comparator match value is
greater than the counter load value, then that comparator never outputs a High pulse.
Figure 3.16 (a). PWM Count-Down Mode
Figure 3.16 (b) PWM Count- Up/Down Mode

PWM Signal Generator

Each PWM generator takes the load, zero, cmpA, and cmpB pulses (qualified by the dir signal) and
generates two internal PWM signals, pwmA and pwmB. In Count-Down mode, there are four events
that can affect these signals: zero, load, match A down, and match B down. In Count-Up/Down mode,
there are six events that can affect these signals: zero, load, match A down, match A up, match B
down, and match B up. The match A or match B events are ignored when they coincide with the zero
or load events. If the match A and match B events coincide, the first signal, pwmA, is generated based
only on the match A event, and the second signal, pwmB, is generated based only on the match B
event.
Dead-Band Generator
The pwmA and pwmB signals produced by each PWM generator are passed to the dead-band
generator. If the dead-band generator is disabled, the PWM signals simply pass through to the pwmA'
and pwmB' signals unmodified. If the dead-band generator is enabled, the pwmB signal is lost and two
PWM signals are generated based on the pwmA signal. The first output PWM signal, pwmA' is the
pwmA signal with the rising edge delayed by a programmable amount. The second output PWM
signal, pwmB', is the inversion of the pwmA signal with a programmable delay added between the
falling edge of the pwmA signal and the rising edge of the pwmB' signal.
The resulting signals are a pair of active high signals where one is always high, except for a
programmable amount of time at transitions where both are low. These signals are therefore suitable
for driving a half-H bridge, with the dead-band delays preventing shoot-through current from damaging
the power electronics.

www.ti.com Quadrature Encoder Interface
3.8 Quadrature Encoder Interface (QEI)

A quadrature encoder, also known as a 2-channel incremental encoder, converts linear displacement
into a pulse signal. By monitoring both the number of pulses and the relative phase of the two signals,
you can track the position, direction of rotation, and speed. In addition, a third channel, or index signal,
can be used to reset the position counter.
A classic quadrature encoder has a slotted wheel like structure, to which a shaft of the motor is
attached and a detector module that captures the movement of slots in the wheel.
3.8.1 Interfacing QEI using Tiva TM4C123GH6PM

The TM4C123GH6PM microcontroller includes two quadrature encoder interface (QEI) modules. Each
QEI module interprets the code produced by a quadrature encoder wheel to integrate position over
time and determine direction of rotation. In addition, it can capture a running estimate of the velocity of
the encoder wheel.
Fig 3.17. QEI Input Signal Logic

The TM4C123GH6PM microcontroller includes two QEI modules providing control of two motors at the
same time with the following features:
 Position integrator that tracks the encoder position
 Programmable noise filter on the inputs
 Velocity capture using built-in timer
 The input frequency of the QEI inputs may be as high as 1/4 of the processor frequency (for
example, 12.5 MHz for a 50-MHz system)
 Interrupt generation on:
o Index pulse

Quadrature Encoder Interface www.ti.com
o Velocity-timer expiration
o Direction change
o Quadrature error detection

The QEI module interprets the two-bit gray code produced by a quadrature encoder wheel to integrate
position over time and determine direction of rotation. In addition, it can capture a running estimate of
the velocity of the encoder wheel. The position integrator and velocity capture can be independently
enabled, though the position integrator must be enabled before the velocity capture can be enabled.
The two phase signals, PhAn and PhBn, can be swapped before being interpreted by the QEI module
to change the meaning of forward and backward and to correct for misfiring of the system.
Alternatively, the phase signals can be interpreted as a clock and direction signal as output by some
encoders.
Fig 3.18. QEI Block Diagram

The QEI module input signals have a digital noise filter on them that can be enabled to prevent
spurious operation. The noise filter requires that the inputs be stable for a specified number of
consecutive clock cycles before updating the edge detector. The filter is enabled by the FILTEN bit in
the QEI Control (QEICTL) register. The frequency of the input update is programmable using the
FILTCNT bit field in the QEICTL register.
The QEI module supports two modes of signal operation:
 Quadrature phase mode, the encoder produces two clocks that are 90 degrees out of
phase, the edge relationship is used to determine the direction of rotation.

 Clock/direction mode, the encoder produces a clock signal to indicate steps and a
direction signal to indicate the direction of rotation. This mode is determined by the
SIGMODE bit of the QEICTL register.
When the QEI module is set to use the quadrature phase mode (SIGMODE bit is clear), the capture
mode for the position integrator can be set to update the position counter on every edge of the PhA
signal or to update on every edge of both PhA and PhB. Updating the position counter on every PhA
and PhB edge provides more positional resolution at the cost of less range in the positional counter.
When edges on PhA lead edges on PhB, the position counter is incremented. When edges on PhB
lead edges on PhA, the position counter is decremented. When a rising and falling edge pair is seen
on one of the phases without any edges on the other, the direction of rotation has changed.
The positional counter is automatically reset on one of two conditions:
 Sensing the index pulse or
 Reaching the maximum position value.
The reset mode is determined by the RESMODE bit of the QEICTL register.
 When RESMODE is set, the positional counter is reset when the index pulse is sensed. This
mode limits the positional counter to the values [0: N-1], where N is the number of phase
edges in a full revolution of the encoder wheel. The QEI Maximum Position (QEIMAXPOS)
register must be programmed with N-1 so that the reverse direction from position 0 can move
the position counter to N-1. In this mode, the position register contains the absolute position of
the encoder relative to the index (or home) position once an index pulse has been seen.
 When RESMODE is clear, the positional counter is constrained to the range [0: M], where M is
the programmable maximum value. The index pulse is ignored by the positional counter in this
mode. Velocity capture uses a configurable timer and a count register. The timer counts the
number of phase edges (using the same configuration as for the position integrator) in a given
time period.
The edge count from the previous time period is available to the controller via the QEI Velocity
(QEISPEED) register, while the edge count for the current time period is being accumulated in the QEI
Velocity Counter (QEICOUNT) register. As soon as the current time period is complete, the total
number of edges counted in that time period is made available in the QEISPEED register (overwriting
the previous value), the QEICOUNT register is cleared, and counting commences on a new time
period. The number of edges counted in a given time period is directly proportional to the velocity of
the encoder.

Quadrature Encoder Interface www.ti.com
Case Study: TIVA based embedded system application using ADC & PWM
This case study is for the application of the PWM based speed control of DC motor using
Potentiometer. In this study all the sensors are initialized and then synchronized with the
synchronization clock pulse. Here the sensor used is potentiometer which is connected to the ADC of
the Tiva C Series Launchpad and the Motor is connected to the PWM pin of Launchpad as shown in
the below diagram. The value read from the potentiometer is used to vary the duty cycle of the PWM to
which the motor is connected, the value will change as per the rotation of the potentiometer. After
executing this we can control the speed of the motor by adjusting the rotation of the potentiometer.
Fig 3.19. Schematic for motor control using TIVA

Fig 3.20. Flowchart for DC motor control using PWM

Summary www.ti.com
3.9 Summary
External devices are principal components to bring a real time embedded systems into existence.
Interfacing modules in microcontrollers are required to provide connection to external components
such as sensors and actuators. Various in built interfacing modules such as Analog to Digital
converters, comparators and DMA are discussed. Quadrature Encoder Interface, a new module is
implemented in TIVA microcontroller to convert linear displacement into pulse signals. Pulse width
modulation, a method to create varying analog waveforms by altering the duty cycle is explained and
discussed with the help of a case study.

www.ti.com Review Questions

1. What is timer? Discuss the various types of timer.
2. How timing generation and measurement effect the performance of microcontroller?
3. How analog to digital convertor works? Discuss with the help of block diagram with functional
detail.
4. How analog comparator works? Discuss the functioning of the analog comparator with the help of
block diagram.
5. How various analog sensors and actuators are interfaced with the microcontroller?
6. What is data acquisition? Discuss the DAQ hardware.
7. What is Direct Memory Access (DMA)? Discuss the various types of DMA in detail.
8. What is PWM (Pulse Width Modulation)? Discuss the functional importance of PWM using TIVA
TM4C123HG6PM.
9. How a Quadrature Encoder converts the linear displacement in the pulse signal?
10. How Quadrature Encoder is interfaced with TivaTM TM4C123GH6PM?

Chapter 4
Communication Protocols and Interfacing with External

Devices
Chapter 3 covered the programming of PWM module, timers, QEI, ADC and their usage in applications
such as voltage regulator, speed control of motor etc. The present chapter will focus on serial
communication between the controller and various types of internal / external digital interfaces of any
microcontroller. The communication is achieved through interfaces and protocols such as UA RT, SPI, and
I2C etc.
By the end of this chapter, the reader will be able to understand and comprehend different types of
communication protocols and distinguish between synchronous and asynchronous protocols.
The chapter also covers serial communication protocols such as I2C, UART, SPI and different modes and
application area of these protocols, especially in reference to TIVA C Series. Readers will also learn how to
configure and interface these protocols with TIVA C Series.
Topic Page
4.1 Introduction........................................................................................................................................ 117
4.2 Synchronous and Asynchronous protocols ....................................................................................... 118
4.3 Universal Asynchronous Receiver-Transmitter ................................................................................. 118
4.4 Programming UART on Tiva Platform............................................................................................... 122
4.5 Inter IC (I2C) Communication Protocol ............................................................................................. 131
4.6 Serial Peripheral Interface (SPI) ....................................................................................................... 143
4.7 Summary ........................................................................................................................................... 153
116 Communication Protocols and Interfacing with External Devices

4.1 Introduction
Microcontrollers or System on Chips (SoC) are important components of modern day electronic
systems. But microcontrollers alone can‟t make systems. For any system to work, it needs memory,
displays, real time clock, interfaces to the external world etc. This means that microcontrollers need to
communicate with other devices on the same PCB or with devices of other PCB from the same
system, to achieve the system functionality in applications such as digital audio, digital signal
processing, or telecommunications channels. Microcontroller is an intelligent component on the
system, which runs the software program to take decisions and control the other components of the
system. To take decisions, microcontroller needs data from various input sources and to execute the
decisions, it sends control signals to different devices/actuators interfaced on the system. For example,
several sensors (temperature, pressure, sound etc.) can be thought of as the components of input
system. These sensors gather data and communicate with the controller through a set of
communication interfaces. Consider a system shown in Fig 4.1, which highlight the various
components of weather monitoring systems. The weather monitoring systems usually monitor
atmospheric properties such as humidity, temperature, pressure etc. The various parameters are
gathered using sensors that are interfaced with microcontroller using popular serial interfaces such as
SPI, I2C, and UART etc. The same system can be used for upper atmospheric data gathering
missions by incorporating Wi-Fi and satellite connectivity with the ground station. Therefore,
communication between microcontroller and other devices on the system is very important to achieve
intended functionality.
Fig 4.1. Weather monitoring using sensor hub balloon

The modern day microcontrollers are enabled with several communication protocols to achieve the
requirement of communication. These communication protocols can be wireline or wireless. And it is
not new to have communication protocols on microcontrollers. The 8 bit microcontroller can
communicate with personal computers using serial communication interface (RS-232). In last three
decades several wireline and wireless communication protocols are evolved for embedded systems.
Communication between the microcontroller and other peripheral devices can be implemented in two
ways: parallel and serial. In parallel communication, 8-bit or 16-bit bus is connected with external
device with other appropriate control signal to establish meaningful communication. The simple
example is interfacing memory with microcontroller. The bus (8 or 16 or 32 bit) connected directly with
memory chip and ALE (Address Latch Enable) decides, whether bus carries address or data to write
into memory and read from memory. Parallel communication was commonly used in the early days of
microprocessor based systems.
As complexity in electronic systems arise, it became a challenge for the designer to optimize I/O‟s
available with microcontroller which can connect with several other devices. It was not possible to
Communication Protocols and Interfacing with External Devices 117

Synchronous and Asynchronous protcols www.ti.com
connect microcontroller with other components parallel, because I/O‟s were not available. And also it
increases the physical dimensions of PCB board which will directly increase the cost of production of
electronic systems. In the mid 80‟s, Philips was facing similar problem with I/O‟s and cost of
production, motivated Philips to invented a serial communication protocol:- Inter-IC protocol (I2C). To
solve the same problem, Motorola came up with Serial Peripheral Interface (SPI). Several other serial
communication protocols are developed in last two decades for different applications in automotive,
industrial control and consumer electronics. Examples: Controller Area Network (Automotive), Inter-IC
sound (I2S) etc. The parallel communication is easy to understand and implement. To optimize the
I/O‟s and cost of production, most of the modern day electronic systems designs use different variety
of serial communication protocols. Similarly, modern microcontrollers support wireless communication
protocols like Bluetooth, ZigBee etc.
4.2 Synchronous and Asynchronous protocols

Serial communication protocols can be categorized as Synchronous and Asynchronous protocols. In
synchronous communication, data is transmission and receiving is a continuous stream at a constant
rate. Synchronous communication requires the clock of transmitting device and receiving device
synchronized. In most of the systems, like ADC, audio codes, potentiometers, transmission and
reception of data occurs with same frequency. Examples of synchronous communication are: I2C, SPI
etc. In the case of asynchronous communication, the transmission of data requires no clock signal and
data transfer occurs intermittently rather than steady stream. Handshake signals between the
transmitter and receiver are important in asynchronous communications. Examples of asynchronous
communication are Universal Asynchronous Receiver Transmitter (UART), CAN etc.
Synchronous and asynchronous communication protocols are well-defined standards and can be
implemented in either hardware or software. In the early days of embedded systems, Software
implementation of I2C and SPI was common as well as a tedious work and used to take long
programs. Gradually, most the microcontrollers started incorporating the standard communication
protocols as hardware cores. This development in early 90‟s made job of the embedded software
development easy for communication protocols.
Microcontroller of our interest TM4C123 supports UART, CAN, SPI, I2C and USB protocols. The five
(UART, CAN, SPI, I2C and USB) above mentioned communication protocols are available in most of
the modern day microcontrollers. Before studying the implementation and programming details of
these protocols in TM4C123, it is required to understand basic standards, features and applications. In
the following sections, we discuss fundamentals of the above mentioned communication protocols.
4.3 Universal Asynchronous Receiver-Transmitter

Universal Asynchronous Receiver-Transmitter (UART) is commonly known as Serial Communication
Interface (SCI) when it was incorporated in microcontrollers. It is an asynchronous protocol and used
mainly in interfacing microcontrollers with personal computers. This protocol is also known as RS-232
protocol. UART can be used in various applications such as GPS units, modems etc.
4.3.1 Half and Full duplex communication

In data transmission, a duplex transmission is one in which data can be transmitted as well as
received. In a simplex transmission, device is configured as transmitter or receiver. One example is a
PC communicating with printers, in which the computer only sends data. Duplex transmissions are
categorized as half or full duplex. Data is transmitted one way at a time; it is called as half duplex.
Data transfer occurs both ways at the same time; it is referred as full duplex. Full duplex requires two
data lines, one for transmission and one for reception.

www.ti.com Universal Asynchronous Receiver-Transmitter
4.3.2 Data Frame in UART

The receiver and transmitter should agree on a set of rules called protocol, to understand the data
transmitted or received. It is difficult to sense the continuous stream of 1s and 0s. Generally protocols,
define how data is packed, how many bits make a character, how data begins and ends.
Asynchronous serial data communication is used for character transmissions. Between start and stop
bits, characters are packed. The start bit is always one bit but the stop bit can be one or two bits. The
start bit is always logic „0‟ (low) and the stop bit is logic „1‟ (high).
Example
:
Fig 4.2. Frame for ASCII „A‟ (01000001)
Fig 4.2 shows the ASCII character “A,” binary 0100 0001, is framed between the start bit and two stop
bits. LSB will go out first. When there is no data transfer, the logic „1‟ is transmitted. This is known as
mark. The logic „0‟ is referred as space. Peripheral chips can be programmed to receive or transmit 5,
6, 7 or 8 bits of data. In the initial days, 2 stop bits were used to give sufficient time to organize the
received data or to make suitable arrangements to transmit next chunk of data. The modern day
microcontrollers and personal computers will use 1 stop bit. In modern UARTs, total 10-bits are used.
8-bits are for ASCII code, one for start bit and one for stop bit. 4.3.3 Parity Bit
A parity bit can be added into the frame in order to check integrity of data. The parity bit may be even
or odd. Odd parity means odd number of 1‟s in the data (parity = logic „1‟). Even parity means even
number of 1‟s in the data (parity = logic „0‟). Ex: The binary of ASCII „A‟ is 0100 0001. Parity bit is logic
„0‟ (Even parity). UART implementations in microcontrollers will allow programmer to decide whether to
include parity or not. The parity bit is transmitted as MSB followed by a stop bit.
4.3.3 Data transfer rate

Data transfer rate in serial communication is measured in terms of bits per second (bps). This is also
called as baud rate. Baud rate and bps can be sued inter changeably with respect to UART.
Ex: The total number of bits gets transferred during 10 pages of text, each with 100 × 25 characters
with 8 bits per character and 1 stop bit is:
For each character a total number of bits are 10. The total number of bits is:
100 × 25 × 10 = 25,000 bits per page. For 10 pages of data it is required to transmit 2, 50,000 bits.
Generally baud rates of SCI are 1200, 2400, 4800, 9600, 19,200 etc. To transfer 2, 50,000 bits at a
baud rate of 9600, we need: 250000/9600 = 26.04 seconds (27 seconds).
4.3.4 Serial I/O Standards

RS-232 is used widely as serial communication standard. UART also follows RS-232 standards. RS-
232 is an interfacing standard adopted by Electronics Industries Association. RS represents
„Recommended Standard‟ in RS-232 and this standard is adopted in 1960, before the advent of CMOS
and TTL logic.

Universal Asynchronous Receiver-Transmitter www.ti.com
Fig 4.3. MAX 232 and microcontroller connection

So the input and output voltage levels are not compatible to TTL or CMOS. In RS-232, at the receiver,
logic „1‟ is represented by -3 to -25V and logic „0‟ between +3 to +25V. The voltage range between -3
to +3 is undefined. To connect RS-232 to other devices which are compliance with TTL, we need
voltage converter circuits. The most commonly used voltage converter devices are MAX232 or
MAX233. It is required to use voltage converters such as MAX232 or MAX233 to convert the TTL logic
levels to the RS232 voltage level and vice versa. The connections are shown in Fig 4.3.
4.3.5 Pin Map for RS232 (DB-9 connector)

The pins and their labels for the RS232 cable which is commonly known as DB-9 connector. The
personal computer serial port is shown in Fig 4.4.
Z
Pin Description
1 Data Carrier Detect (DCD)
2 Received data (RxD)
3 Transmitted data (TxD)
4 Data terminal ready (DTR)
5 Signal Ground (GND)
6 Data set ready (DSR)
7 Request to Send (RTS)
8 Clear to send (CTS)
9 Ring Indicator (RI)
Fig 4.4. DB-9 Connector

The handshaking mechanism is important to ensure fast and reliable data transfer between the two
devices. Few signals of RS-232 are used for handshaking.

www.ti.com Universal Asynchronous Receiver-Transmitter
DCD (Data carrier Detect)

This signal is also known as CD (Carrier Detect). The microcontroller asserts DCD to inform PC that a
valid carrier has been detected and connection is successfully established. DCD is an output from
microcontroller and input to PC.
DTR (Data Terminal Ready)
After self-test operation, DTR signal will inform microcontroller that it is ready for communication. DTR
is output of PC COM port.The DTR is active low signal and won‟t get activated when there is an error
in COM port.
DSR (Data Set Ready)
When microcontroller is turned on, it will undergo self-test for UART and asserts DSR to signal PC
COM port, that it is ready. This is an active low signal.
RTS (Request To Send)
When a PC COM port want to transmit the byte of data to microcontroller, it will signal the
microcontroller by asserting the RTS signal. RTS is an active low signal.
CTS (Clear To Send)
Microcontroller will respond to RTS signal by asserting the CTS line, indicating that it is ready to
receive data. This signal is output of microcontroller and input to PC COM port. PC will start
transmission once it receives CTS.
RI (Ring Indicator)
This signal is handshaking signal, which is not often used. Microcontroller can send RI to PC, so that
there will be telephone ringing and PC will receive it.
Note on Serial Communication in embedded systems:
There are many ways to encode the binary information during serial communication. The main
aim of using different techniques is to maximize the bandwidth and minimize errors.
Fig 4.5. Different encoding schemes for serial communication

NRZ (Non-Return to Zero) is one type of encoding in which signal is never go to zero voltage. To
maintain high energy on wires, this coding is used, such that data can be transmitted for long distance.
Voltages are measured with respect to ground in single wire (Ex: RS-232) and in twisted pairs,
voltages are differential (Ex: RS-422, USB). Binary values are encoded as positive or negative
voltages. Logic „1‟ will have positive voltage and logic „0‟ will have negative voltage in positive logic. In
negative logic, it is vice-versa.

Programming UART on Tiva Platform www.ti.com
Non-return to zero inverted (NRZI) is encoding method, in which binary signal is represented as
transitions in the signal. Binary information is encoded as the presence or absence of transition at the
clock boundary.
The interface logic chips like MAX232 will convert voltages between TTL/MOS/CMOS logic levels.
4.4 Programming UART on Tiva Platform

This section describes the UART serial port of Tiva TM4C123GH6PM microcontroller. The basics of
UART protocol is discussed in the previous section. TM4C123GH6PM microcontroller has got eight
UART ports. They are named as UART0-UART7. In the TI Launchpad, the UART0 port is connected
to the ICDI (In-Circuit Debug Interface). ICDI is further connected to USB port. Users can use UART0
for flash programming, debugging using JTAG. The UART features of TI Tiva TM4C123GH6PM
microcontroller is: -
 UART‟s have programmable baud-rate generator allowing speeds up to 5 Mbps for regular
speed and 10 Mbps for high speed.
 Separate 16x8 transmit (TX) and receive (RX) FIFOs to reduce CPU interrupt service
loading with programmable FIFO length
 Standard asynchronous communication bits for start, stop, and parity, Line-break generation
and detection
 Fully programmable serial interface characteristics
o 5, 6, 7, or 8 data bits
o Even, odd, stick, or no-parity bit generation/detection
o 1 or 2 stop bit generation
 IrDA serial-IR (SIR) encoder/decoder providing
o Programmable use of IrDA Serial Infrared (SIR) or UART input/output
o Support of IrDA SIR encoder/decoder functions for data rates up to 115.2 Kbps half-
duplex
o Support of normal 3/16 and low-power (1.41-2.23 μs) bit durations
o Programmable internal clock generator enabling division of reference clock by 1 to
256 for low-power mode bit duration
 Support for communication with ISO 7816 smart cards
 Modem flow control (on UART1)
 EIA-485 9-bit support
 Standard FIFO-level and End-of-Transmission interrupts
o Separate channels for transmit and receive
o Receive single request asserted when data is in the FIFO; burst request asserted at
programmed FIFO level
o Transmit single request asserted when there is space in the FIFO; burst request
asserted at programmed FIFO level.

www.ti.com Programming UART on Tiva Platform
4.4.1 UART Register Map

TI Tiva TM4C123GH6PM UART has got several Special Function Registers (SFR‟s) which needs to
program with appropriate values to achieve required UART functionality. In this section, UART0 is
taken as example in which virtual connection is possible on TI Tiva launch pad.
Fig 4.6. Simplified block diagram of UART

Baud Rate Generators: The SFR‟s used in setting the baud rate are UART Integer Baud-Rate Divisor
(UARTIBRD) and UART Fractional Baud-Rate Divisor (UARTFBRD). The block diagram of the
registers is given below:
Fig 4.7. Baud rate registers

The physical addresses for these UART baud rate registers are: 0x4000:C000+0x024 (UARTIBRD)
and 0x4000:C000+0x028 (UARTFBRD). Only lower 16 bit are used in UARTIBRD and lower 6-bits
are used in UARTFBRD. So it comes to total of 22 bits (16-bit integer + 6 bit of fraction). To reduce
the error rate and use the standard baud rate supported by the terminal programs it is required to use
both the registers when we program for the baud rate. The standard baud rates are: 2400, 4800, 9600,
19200, 57600 and 115200.
Baud rate can be calculated using the below formula:
Desired Baud Rate = SysClk / (16 × ClkDiv)

Where the SysClk is the working system clock connected to the UART and ClkDiv is the value
programmed into baud rate registers.
The baud-rate divisor (BRD) has the following relationship to the system clock, where BRDI is the
integer part of the BRD and BRDF is the fractional part, separated by a decimal place.
BRD = BRDI + BRDF = UARTSysClk / (ClkDiv * Baud Rate)
UARTSysClk is the system clock connected to the UART, and ClkDiv is 16 (if HSE in UARTCTL is
clear) or 8 (if HSE is set).
Alternatively, the UART may be clocked from the internal precision oscillator (PIOSC), independent of
the system clock selection. This will allow the UART clock to be programmed independently of the
system clock PLL settings.
TI Tiva Launchpad system clock is 16 MHz so desired Baud Rate can be calculated as:
Baud Rate = 16MHz / (16 × ClkDiv) = 1MHz / ClkDiv
The ClkDiv value includes both integer and fractional values loaded into UARTIBRD and UARTFBRD
registers. The integer part is easy to calculate and fraction part requires manipulations based on trial
and error.
Example:
System clock of TI Tiva Launchpad is16 MHz 16MHz is divided by 16 and it is fed into UART. So
UART operates at 1MHz frequency. So ClkDiv = 1MHz.
To generate a baud rate of 4800: 1MHz/4800 = 208.33
(a) 1MHz/4800 = 208.3333, UARTIBRD = 208 and UARTFBRD = (0.3333×64) +
0.5 = 21.8312 = 21
(b) 1MHz/9600 = 104.166666, UARTIBRD = 104 and UARTFBRD = (0.16666 × 64)
+0.5=11
(c) 1MHz/57600 = 17.361, UARTIBRD = 17 and UARTFBRD = (0.361 × 64) + 0.5
=23
(d) 1MHz/115200 = 8.680, UARTIBRD = 8 and UARTFBRD = (0.680 × 64) +0.5=44
4.4.2 Serial IR (SIR)

UART includes an IrDA (Infrared) serial IR encoder-decoder block. SIR block converts the data
between UART and half-duplex serial SIR interface. The SIR block provides a digitally encoded output
and decoded input to UART. SIR block uses UnTx and UnRx pins for SIR interface. These pins are
connected to IrDA SIR physical layer link. SIR block supports half-duplex communication. The IrDA
SIR physical layer specifies a minimum 10-ms delay between transmission and reception. The SIR
block has two modes of operation normal mode and low power mode.
ISO 7816 Support: UART support ISO 7816 smartcard communication. The UnTx signal is used as a
bit clock and the UnRx signal is used as the half-duplex communication line connected to the
smartcard. Any GPIO signal can be used to generate the reset signal to the smartcard.

4.4.3 UART Control register (UARTCTL)

This is a 32-bit register. The most important bits are RXE, TXE, HSE, and UARTEN.
Fig 4.8. UART Control (UARTCTL) register

 RXE (Receive enable): This bit should be enabled to receive data.
 TXE (Transmit Enable): This bit should be enabled to transmit data.
 HSE (High Speed enable): This bit is used to set the baud rate. By default the system clock is
divided by 16 before it is fed to the UART. The user can program HSE =1, to make system clock
divide by 8.
 UARTEN (UART enable): This bit allows user to enable or disable the UART. During the
initialization of the UART registers, this is disabled. To disable UART under any circumstances,
this bit is used.
 SIREN (SIR Enable): IrDA SIR Block is enabled. UART will transmit and receive data using
SIR protocol.
 SIRLP (SIR Low Power Mode): This bit selects the IrDA encoding mode: Normal mode or low
power mode.
 SMART (ISO 7816 Smart Card support): The UART operates in Smart Card mode when
SMART = 1. UART does not support automatic retransmission on parity errors. If a parity error
is detected on transmission, all further transmit operations are aborted and software must
handle retransmission of the affected byte or message.
 LBE (Loop Back Enable): The UnTx path is fed through the UnRx path when LBE =1.
 RTSEN (Enable Request to send): RTS hardware flow control is enabled. Data is only
requested when receive FIFO has available entries.
 RTS (Request to send): When RTSEN is clear, the status of this bit is reflected on the U1RTS
signal. If RTSEN is set, this bit is ignored on a write and should be ignored on read.
4.4.4 UART Line Control Register (UARTLCTH)

This register is used to set the length of data. The bits per character in a frame and number of stop bits
are also decided.
Fig 4.9. UART Line Control (UARTLCTH) register

 STP2 (Stop bit2): The stop bits can be 1 or 2. The default is 1 stop bit at the end of each frame.
If the receiving device is slow, we can use 2 stop bits by making the STP2=1.

 FEN (FIFO Enable): UART has an internal 16-byte FIFO (first in first out) buffer to store data for
transmission to keep the CPU getting interrupted for the reception and transmission of every
byte. Enabling FEN bit, we can write up to16 bytes of data block into its transmission FIFO
buffer and let transfer happen one byte at a time. There is also a separate 16 byte FIFO for the
receiver to buffer the incoming data. Upon Reset, the default for FIFO buffer size is 1 byte.
 WLEN (Word Length): The number of bits per character data in each frame can be 5, 6, 7, or 8.
we use 8 bits for each character data frame. Default world length mode is 5.
 BRK (Send Break): A Low level is continually output on the UnTx signal, after completing
transmission of the current character. For the proper execution of the break command, software
must set this bit for at least two frames (character periods).
 PEN (Parity Enable): Parity is enabled and parity bit is added to the data frame by making PEN
= 1. Parity checking is also enabled.
 EPS (Even Parity Select): Odd parity is performed, which checks for an odd number of 1s when
EPS = 0. Even parity generation and checking is performed during transmission and reception,
which checks for an even number of 1s in data and parity bits when EPS = 1.
4.4.5 UART Data Register (UARTDR)
Fig 4.10. UART Date Register (UARTDR)

Data should be placed in data register before transmission. Only lower 8 bits are used. In a similar
way, the received byte should be read and saved in memory before it gets overwrite by next byte.
During reception, we use other four bits (8, 9, 10 and 11) to detect error, parity etc. Another set of
registers are used to check the source of error. (UARTRSR/UARTRCR)
 OE: Overrun error (OE = 0: No data is lost).
 BE: Break error
 PE: Parity error
 FE: Framing error.
 4.4.6 UART Flag Register (UARTFR)
The UART Data Register holds one byte of data when FIFO buffer is disabled.
 TXFE (TX FIFO Empty): Transmitter loads one byte for transmission from the FIFO buffer.
When FIFO becomes empty, the TXFE is raised. The transmitter then frames the byte and
sends it out via TxD pin bit by bit serially.
 RXFF (RX FIFO Full): When a byte of data is received, byte is placed in Data register and
RXFF (RX FIFO full) flag bit is raised after receiving the complete byte.
 TXFF (TX FIFOI Full): When the transmitter is not busy, it loads one byte from the FIFO buffer
and the FIFO is not full anymore and the TXFF is lowered. We can monitor TXFF flag and upon
going LOW we can write another byte to the Data register.

Fig 4.11. UART Date Register (UARTDDR)

 RXFE (RX FIFO empty): Data register and lowers the RXFE bit when receive FIFO is empty.
This is essentially the opposite of RXFF flag bit. We can monitor RXFE flag and upon going
LOW (buffer not empty) we should read (retrieve) the data from Data register.
 Busy: When a byte is written to the Data register the busy flag goes high. While UART busy
transmitting data this bit remains high until the stop bit is gone. Upon transmission of the last bit
(stop bit), it goes low indicating the transmission is completed.
 RCGCUART (UART Run Mode Clock Gating Control): The RCGCUART register is used to
enable the clock to the UART. There is a each bit for each of the UART0 to UART7 modules. To
use UART0, we set to D0 = 1.
 I/O pins for UART: Along with special function registers, it is also required to configure I/O pins
for UART. When GPIO pins are used by peripherals like UART, we need to configure five more
registers: PORTx Run Mode Clock Gating Control, PORTx Digital Enable, PORTx ADC Mode
Selection, PORTx Alternate Selection and PORTx Port Control registers.
4.4.6 UART Transmission

Step to perform UART Transmission:
 Program the RCGCUART register to get clock on UART0.
 Program the RCGCGPIO register to get the clock for PORTA.
 Program UARTCTL to disable UART0.
 Program the integer part and fractional part into baud rate registers: UARTIBRD and
UARTFBRD for UART0.
 Program UARTCC to select the system clock as UART clock.
 Set the bits in UARTLCRH register for 1 stop bit, no interrupt, no FIFO use, and for 8-bit data
size (for UART 0).
 Program TxE and RxE in UARTCTL to enable transmitter and receiver.
 Make PA0 and PA1 pins to use as digital pins.
 Configure PA0 and PA1 pins for UART.
 Loop the program for wait on TxD output. Monitor the TXFF flag bit and when it goes low, write
a data into data register.
4.4.7 UART Reception

Step by Step Execution of UART Reception:
 Program the RCGCUART register to get clock on UART0.
 Program the RCGCGPIO register to get the clock for PORTA.
 Program UARTCTL to disable UART0.
 Program the integer part and fractional part into baud rate registers: UARTIBRD
and UARTFBRD for UART0.
 Program UARTCC to select the system clock as UART clock.

 Set the bits in UARTLCRH register for 1 stop bit, no interrupt, no FIFO use, and for
8 -bit data size (for UART 0).
 Program TxE and RxE in UARTCTL to enable transmitter and receiver.
 Make PA0 and PA1 pins to use as digital pins.
 Configure PA0 and PA1 pins for UART.
 Loop the program for wait on TxD output. Monitor the TXFF flag bit and when it
goes low, write a data into data register.
 Monitor the RXFE flag bit in UART Flag register and when it goes LOW read the received byte
from Data register and save before it gets overwrite.
4.4.8 Basic UART programing

Example 1:
Program to send the characters "HELLO" to HyperTerminal of PC
#include <stdint.h>
#include "tm4c123gh6pm.h"
void UART0Tx(char c);
void delayMs(int n);
int main(void)
SYSCTL->RCGCUART |= 1; /* enable clock supply to UART*/
SYSCTL->RCGCGPIO |= 1; /* enable clock supply to PORTA */
/* UART0 initialization */
UART0->CTL = 0; /* disable UART0 */
UART0->IBRD = 104; /* 9600 baud rate
UART0->FBRD = 11; /* fractional portion*/
UART0->CC = 0; /* configured to system clock */
UART0->LCRH = 0x60; /* 8-bit, no parity, 1-stop bit, no FIFO */
UART0->CTL = 0x301; /* configure UART0 and TXE, RXE */
/* UART0 TX0 and RX0 use PA0 and PA1. Set them up. */
GPIOA->DEN = 0x03; /* Make PA0 and PA1 as digital */
GPIOA->AFSEL = 0x03; /* Use PA0, PA1 alternate function */
GPIOA->PCTL = 0x11; /* configure PA0 and PA1 for UART */
delayMs(1); /* wait for output line to stabilize */
for(;;)
{
UART0Tx('H');
UART0Tx('E');
UART0Tx('L');
UART0Tx('L ');

UART0Tx('O');
}
}
/* UART0 Transmit */
void UART0Tx(char c)
{while((UART0->FR & 0x20) != 0); /* wait until Tx buffer not full */
UART0->DR = c; /* before giving it another byte */
}
Example 2 :
Program to receive data serially via UART0
#include <stdint.h>
#include "tm4c123gh6pm.h"
char UART0Rx(void);
void delayMs(int n);
int main(void)
{
char c;
SYSCTL->RCGCUART |= 1; /* enable clock supply to UART*/
SYSCTL->RCGCGPIO |= 1; /* enable clock supply to PORTA */
/* UART0 initialization */
UART0->CTL = 0; /* disable UART0 */
UART0->IBRD = 104; /* 9600 baud rate
UART0->FBRD = 11; /* fractional portion*/
UART0->CC = 0; /* configured to system clock */
UART0->LCRH = 0x60; /* 8-bit, no parity, 1-stop bit, no FIFO */
UART0->CTL = 0x301; /* configure UART0 and TXE, RXE */
/* UART0 TX0 and RX0 use PA0 and PA1. Set them up. */
GPIOA->DEN = 0x03; /* Make PA0 and PA1 as digital */
GPIOA->AFSEL = 0x03; /* Use PA0, PA1 alternate function */
GPIOA->PCTL = 0x11; /* configure PA0 and PA1 for UART */
for(;;)
{
c = UART0Rx(); /* get a character from UART */

}
}
/* UART0 Receive */
char UART0Rx(void)
{
char c;
while((UART0->FR & 0x10) != 0); /* wait until the buffer is not
empty */
c = UART0->DR; /* read the received data */
return c; /* and return it *

www.ti.com Inter IC (I2C) Communication Protocol
4.5 Inter IC (I2C) Communication Protocol

Inter IC (i2c) (IIC) is important serial communication protocol in modern electronic systems. Philips
invented this protocol in 1986. The objective of reducing the cost of production of television remote
control motivated Philips to invent this protocol. IIC is a serial bus interface, can be implemented in
software, but most of the microcontrollers support IIC by incorporating it as hard IP (Intellectual
Property). IIC can be used to interface microcontroller with RTC, EEPROM and different variety of
sensors. IIC is used to interface chips on motherboard, generally between a processor chip and any
peripheral which supports IIC. IIC is very reliable wireline communication protocol for an on board or
short distances. I2C is a serial protocol for two-wire interface to connect low-speed devices like
microcontrollers, EEPROMs, A/D and D/A converters, I/O interfaces and other similar peripherals in
embedded systems
IIC protocol uses two pins for data transfer: Serial Data Line (SDA) and Serial Clock Line (SCL). The
reduction in number of pins in comparison with parallel data transfer is evident. This reduces the cost
of production, package size and power consumption. IIC is also best suited protocol for battery
operated devices. IIC is also referred as two wire serial interface (TWI).
Fig 4.12. I2C Bus
4.5.1 General Electrical Characteristics of I2C

To implement I2C (For TIVA series microcontrollers or for most of the microcontrollers) a 4.7kilo ohm
pull-up resistor for each line is needed. This is required to implement wired-AND logic in IIC.
More than 100 devices can be connected to I2C bus theoretically. It is better to restrict to 15 devices
for better performance of the network. Each device is called as node. Nodes which generates clock are
called Master nodes and devices which work based on the clock generated by master node are called
Slave nodes. Generally, master nodes initiate and terminate the transmission. The four possible
modes of operation are: master transmitter, master receiver, slave transmitter and slave receiver.
Bit format: I2C data bit is transferred on the SDA line and should be synchronized by high to low
pulse of clock running on SCL line. As per the specifications of IIC, data line can‟t change when clock
is high, it can change during clock line is low. This rule is followed during data transfer and not
applicable for STOP and START bits.
START and STOP bits format: I2C has got START and STOP bits. START and STOP bits are
generated by master. These bits can be easily recognized. START and STOP are generated by
keeping the SCL high and changing the SDA line. START bit is generated by high to low transition in
SDA line when SCL is high. STOP bit is generated by low to high transition in SDA line when SCL is
low.

Inter IC (I2C) Communication Protocol www.ti.com
Fig 4.13. I2C START and STOP bits

I2C Frame Format: The frame size of the I2C (for both data and address) is 9 bit. The transmitter will
send first 8 bits on SDA line and receiver will put 9th bit (negative acknowledge bit). Clock is always
generated by master, whether it acts like transmitter or receiver. To allow acknowledge, the transmitter
release the SDA line during 9th clock pulse. The complete Data format sequence is:-
START bit+ ADDRESS of receiver + one or more DATA bytes + STOP
Fig 4.14. I2C Frame Format

I2C Address Format: Address format is nine bits long and it consists of seven address bits, one R/W
bit and ACK bit. With seven address bits, 128 devices can be accommodated in I2C bus network. But
few address like 0000 0000 is reserved for general call and address starting with 1111 xxx are
reserved. So I2C bus can be shared by 119 devices in the network. R/W bit is logic high, the master
will read the next byte from the slave, and else master will write the next byte on the bus. Slave will
acknowledge in the ninth clock cycle by pulling SDA line to low, when it detects its address on the bus.
Slave will not change the SDA line to low, when it is busy. During this condition, master transmits
STOP condition to terminate the transmission.
I2C Data Format: Data format consists of 8-bits of data to be transmitted and acknowledgement will
be the 9th bit. If the receiver receives the last byte of data it signals NACK leaving the SDA at logic
high. The master will terminate transmission. In data also, MSB is transmitted first.

Fig 4.15. I2C combined address and data

Clock Stretching: Any slave device in the network is not ready to receive data will stretch the clock by
holding the SCL low after bit of data is transacted. Due to this master cannot raise the clock to high
and master waits until slave releases the line. This process is called clock stretching.
Arbitration: In an I2C network, there can be many master devices. When two masters start using bus
at a same time, there will be conflict between the devices. The solution to this problem is through
arbitration mechanism. Wired AND logic is used for arbitration. The transmitting device has to check
the bus logic level and compare with the logic level it is driving, if there is a mismatch, then that device
has lost the arbitration and switches to slave mode. Logic „0‟ is the dominant bit in I2C. In a conflict for
bus, the master who transmits the logic „0‟ first will win the arbitration.
Example: If two devices A and B try to transmit data at the same time on the bus. Device A
wants to send “0001 0100” and B wants to send “0010 0100”. Who will get the access to bus?
(Means who wins the arbitration)
Sol. The first two bits of both A and B is “00”. And the third bit of device A is logic „0‟ and B is
logic „1‟. In I2C, logic „0‟ is dominant bit, and device A will win the arbitration and get the access
to the bus and transmits data.
Multi burst read and write in I2C: Burst mode means accessing the consecutive memory locations
for both reading and writing. In burst write, address of the first memory location and series of data is
provided. Consecutive bytes are written to consecutive memory locations. Burst mode supported I2C
devices increment the address internally to write the data until STOP condition is detected on bus. In
burst read device reads the data from the consecutive memory locations by incrementing the memory
address until STOP condition is reached.
4.5.2 I2C in Tiva microcontroller TM4C123GH6PM

 The TM4C123GH6PM controller includes four I2C modules with the following features:
Devices on the I2C bus can be designated as either a master or a slave
 Supports both transmitting and receiving data as either a master or a slave
 Supports simultaneous master and slave operation
 Four I2C modes
 Master transmit
o Master receive
o Slave transmit

o Slave receive
 Four transmission speeds:
o Standard (100 Kbps)
o Fast-mode (400 Kbps)
o Fast-mode plus (1 Mbps)
o High-speed mode (3.33 Mbps)
 Clock low timeout interrupt
 Dual slave address capability
 Glitch suppression
 Master and slave interrupt generation
 Master generates interrupts when a transmit or receive operation completes (or aborts due to
an error)
 Slave generates interrupts when data has been transferred or requested by a master or when
a START or STOP condition is detected
 Master with arbitration and clock synchronization, multi-master support, and 7-bit addressing
mode.
4.5.3 I2C Network

There are four on chip IIC modules in this Tiva microcontroller. The base address of each IIC module
is shown in below table:
Module Base Address

I2C 0 0x4002.0000
I2C 1 0x4002.1000
I2C 2 0x4002.2000
I2C 3 0x4002.3000
Fig 4.16. I2C Networking using Tiva microcontroller

Clock should be enabled to IIC module and system control register (SYSCTL) RCGCI2C needs to be
programmed. To enable the clock SYSCTL ->RCGCI2C | = 0x0F will enable clock to all four modules
Fig 4.17. RunMode Clock Gating Control Register

Clock should be enabled to IIC module and system control register (SYSCTL) RCGCI2C needs to be
programmed.

To enable the clock SYSCTL ->RCGCI2C | = 0x0F will enable clock to all four modules.
Clock Speed: I2CMTPR (I2C Master Timer Period) register is programmed to set the clock frequency
for SCL.
Fig 4.18. I2C Master Time Period Register

Table 4.1: RCG12C Register Description
Bit Function Description
R0 I2C0 clock gating control 1: Enable, 0: disable
The formula used to set the clock speed is given below:
SCL_PERIOD = 2 x (1+TPR) x (SCL_LP+ SCL_HP) x CLK_PRD

Where
CLK_PRD: System Clock period
SCL_LP: SCL low period and it is fixed at 6.
SCL_HP: SCL High period and it is fixed at 4.
Finally, the above equation can be written as:
SCL_PERIOD = (20 x (1+TPR)/ System clock frequency

The TPR can be calculated as:
TPR = ((System clock frequency x SCL_PERIOD)/20) - 1)

TPR = (System Clock frequency)/ (20 x I2C clock) - 1
With System clock frequency of 20MHz and with I2C clock is 333 KHz, we get TPR (Timer period) = 2.

TPR value to generate Standard, Fast and Fast mode plus SCL frequencies is given in below table:
Table 4.2. TPR Values for I2C modes
The HS bit in the I2CMTPR register needs to be set for the TPR value to be used in High-Speed
mode.
Table 4.3: TPR Values for High-Speed Mode
I2CMCR (I2C Master Configuration register) is used to configure microcontroller as master or slave.
The description of I2CMCR is below:
Fig 4.19. I2C Master Configuration Register
Table 4.4: I2CMCR Register Description

Name Function Description
LPBK I2C Loopback 0: Normal Operation; 1: Loopback
1: Enable Master function; 0: Disable
MFE I2C Master function Enable
master
SFE I2C Slave function Enable 1: Enable Slave function; 0: Disable
GFE I2C Glitch Filter Enable 1: Enable Glitch filter; 0: Disable

Slave Address:
In a master device, the slave address is stored in I2CMSA. Addresses in I2C communication is 7-bits.
I2CMSA stores D7 to D1 bits and LSB of D0 indicate master is receiver of transmitter.
Fig 4.20. I2C Master Slave Address Register
Data Register:
In transmit mode, a byte of data will be placed in I2CMDR (I2C Master Data Register) for transmission.
Fig 4.20. I2C Master Data Register

Control and Status Flag Register:
The I2CMCS (I2C Master Control/Status) register is programmed for both control and status. I2CMCS
register configures the I2C controller operation. The status whether a byte has been transmitted. That
is, transmission buffer is empty and ready to transmit the next byte. After writing a data into I2C Data
register and the slave address into I2C Master Slave address register, we can configure I2CMCS
register for the I2C to start a data transmission from Master to slave device. Writing 0x07 to I2CMCS
register has all the three of STOP = 1, RUN = 1, and START = 1 in it. To check the status of
transmission, we poll the BUSBSY bit of I2CMCS register. BUSBSY bit goes low after transmission
complete. Program should also check the ERROR bit to confirm that no error has occurred during
transmission. For any error in transmission, detected by transmitter or raised by slave, the ADRACK
and DATACK will be set. The bit ARBLST should be polled, to confirm transmitter has got access to
bus and not lost arbitration.
Fig 4.22. I2C Master Control/Status Register

Table 4.5: I2C MCS Register Description

1: Enables the master, so that
RUN I2C Master Enable
transmission can be started.
1: Enabled to generate START
START Generate START
condition
STOP Generate STOP 1: Enabled to generate STOP condition
ACK Data Acknowledge Enable 1: To generate auto ACK condition
HS High Speed Enable 1: High Speed operation enabled
BUSY I2C Busy 0: I2C controller is idle
ERROR Error in network 0: No Error detected in network
ADRACK Acknowledge address 0: Transmitted address acknowledged
DATRACK Acknowledge Data 0: Transmitted data acknowledged
ARBLST Arbitration lost 0: IIC controller won arbitration
IDLE I2C Idle 0: Bus is not idle
BUSBSY Bus Busy 0: Bus is idle
CLKTO Clock Timeout Error 0: No clock timeout error

4.5.4 Configuring GPIO for I2C Network

 GPIO pins are configured for IIC as follows:
 Enable the clock to GPIO pins by using system control register RCGCGPIO.
 Set the GPIO AFSEL (GPIO alternate function) for I2C pins.
 Enable digital pins in the GPIODEN register.
 I2C signals are assigned to specific pins using GPIOCTL register.
(a) (b)
Fig 4.23. Data transmission using (a) Master Single Transmit, (b) Single Master receive

4.5.5 RTC interfacing (DS1307) with Tiva Microcontroller

Real-time clock (RTC) is used to get accurate time and date information.
DS1307 is a serial RTC IC support I2C protocol. The DS1307 clock operates in either the 24-hour or
12-hour format with AM/PM indicator. The DS1307 has a built-in power-sense circuit that detects
power failures.
Fig 4.24. DS1307 Interfacing with TIVA

 X1 –X2: These pins are used to connect crystal oscillator. We must connect 32.768 kHz
crystal. (Pin 1 –Pin 2).
 Vbat: This pin is connected to +3V lithium battery, when VCC is not available. (Pin 3)
 GND: Ground (Pin 4)
 SDA (Serial Data): Serial Data line (pin 5)
 SCL (Serial Clock): Serial Clock line (pin 6)
 SWQ/OUT: This is an output pin, which provides 1 kHz, 4 kHz, 8 kHz or 32 kHz.
 VCC: Primary voltage supply to the chip.
The DS1307 has got 64 bytes of RAM space with addresses 00–3FH. The first seven locations are set
aside for RTC to store time and date (00-06). The next immediate byte is used as control register
(07h). The rest 56 bytes from addresses 07H to 3FH are used as general purpose data storage. The
DS1307 control register control the function of the SQW/OUT pin. RS1-RS0 (rate select) bits select
the frequency of the oscillator output.
Fig 4.25. RTC Control Register

www.ti.com Serial Peripheral Interface (SPI)
Table 4.6: RTC Control Register Description
RS1 RS0 Frequency
0 0 1 Hz
0 1 4.096 kHz
1 0 8.192 kHz
1 1 32.768 kHz
 Writing into DS1307

To write one or more bytes of data to DS1307, the following steps should be followed:
o To access the DS1307 for a write operation, after START condition, transmitter device
should transmit the address of DS1307 (1101 000) followed by 0 to indicate a write
operation.
o The first byte of data in the write operation will set the register pointer. To write into the
control register transmitter should send 0x07.
o Check the acknowledge bit.
o To write the data bytes, one should transmit them one byte at a time and check the
acknowledge bit for each byte.
o Transmit a STOP bit condition.
 Reading from DS1307

To read the data from DS1307 the following steps should be followed:
o To access the DS1307 for a read operation, it is required to set the register pointer. After a
START condition, one should transmit the address of DS1307 (1101 000) followed by 0 to
indicate a write operation (writing the register pointer).
o Check the acknowledge bit.
o The byte of data in the write operation will set the register pointer.
o Change the bus direction from a transmitter to receiver. Send a START condition, followed
by address of DS1307 (1101 000) followed by 1 to indicate a read operation.
o Transmit a STOP bit condition.
 Configuring the Time of DS1307

/* I2C to DS1307 single byte write */
/* The seconds, minutes, and hours are written one byte at a time. */
/* I2C1SCL PA6 I2C1SDA PA7 */
#include "TM4C123GH6PM.h"
#define SLAVE_ADDR 0x68 /* 1100 1000 */
void I2C1_init(void);
char I2C1_byteWrite(int slaveAddr, char memAddr, char data);
int main(void)
char timeDateToSet[7] = {0x55, 0x58, 0x16, 0x01, 0x19, 0x10, 0x09};
I2C1_init();
/* write hour, minute, second with single byte writes */
I2C1_byteWrite(SLAVE_ADDR, 0, timeDateToSet[0]); /* second */
I2C1_byteWrite(SLAVE_ADDR, 1, timeDateToSet[1]); /* minute */

Serial Peripheral Interface (SPI) www.ti.com
I2C1_byteWrite(SLAVE_ADDR, 2, timeDateToSet[2]); /* hour */

for (;;)/* initialize I2C1 as master and the port pins */
void I2C1_init(void)
SYSCTL->RCGCI2C |= 0x02; /* enable clock to I2C1 */
SYSCTL->RCGCGPIO |= 0x01; /* enable clock to GPIOA * /* PORTA 7, 6 for I2C1 */
GPIOA->AFSEL |= 0xC0; /* PORTA 7, 6 for I2C1 */
GPIOA->PCTL &= ~0xFF000000; /* PORTA 7, 6 for I2C1 */
GPIOA->PCTL |= 0x33000000;
GPIOA->DEN |= 0xC0; /* PORTA 7, 6 as digital pins */
GPIOA->ODR |= 0x80; /* PORTA 7 as open drain */
I2C1->MCR = 0x10; /* master mode */
I2C1->MTPR = 7; /* 100 kHz @ 16 MHz */
/* This function is called by the startup assembly code to perform system specific initialization
tasks. */
void SystemInit(void)
{ /* Grant coprocessor access */
/* This is required since TM4C123G has a floating point coprocessor */
SCB->CPACR |= 0x00f00000;
/* Wait until I2C master is not busy and return error code */
/* If there is no error, return 0 */
static int I2C_wait_till_done(void)
{while(I2C1->MCS & 1); /* wait until I2C master is not busy */
return I2C1->MCS & 0xE; /* return I2C error code */
}/* Write one byte only */
/* byte write: S-(saddr+w)-ACK-maddr-ACK-data-ACK-P */
char I2C1_byteWrite(int slaveAddr, char memAddr, char data)
char error;/* send slave address and starting address */
I2C1->MSA = slaveAddr << 1;
I2C1->MDR = memAddr;
I2C1->MCS = 3; /* S-(saddr+w)-ACK-maddr-ACK */
error = I2C_wait_till_done(); /* wait until write is complete */
if (error) return error;
/* send data */
I2C1->MDR = data;
I2C1->MCS = 5; /* -data-ACK-P */
error = I2C_wait_till_done(); /* wait until write is complete */

while(I2C1->MCS & 0x40); /* wait until bus is not busy */

error = I2C1->MCS & 0xE;
if (error) return error;
return 0; /* no e
4.6 Serial Peripheral Interface (SPI)

Serial peripheral interface (SPI) is a serial communication interface originally designed by Motorola in
late eighties. SPI and I2C came into existence almost at the same time. Most of the modern day
microcontrollers will support SPI protocol. Both SPI and I2C offer good support for communication with
low-speed devices, but SPI is better suited to applications in which devices transfer data streams.
Some devices use the full-duplex mode to implement an efficient, swift data stream for applications
such as digital audio, digital signal processing, or telecommunications channels, but most off-the-shelf
chips stick to half-duplex request/response protocols.
SPI is used to talk to a variety of peripherals, such a
 Sensors: temperature, pressure, ADC, touchscreens, video game controllers
 Control devices: audio codecs, digital potentiometers, DAC
 Camera lenses: Canon EF lens mount
 Memory: flash and EEPROM
 Real-time clocks
 LCD, sometimes even for managing image data
 Any MMC or SD card
Description: SPI is a synchronous serial communication protocol like I2C, where master generates
clock and data transfer between master and slave happens with respect to clock. Both master and
slave devices will have shift registers connected to input (MISO for master and MOSI for slave) and
output (MOSI for master and MISO for slave) as shown in figure.
Fig 4.26. Serial Peripheral Interface

Communication between the devices will start after CS (chip select) pin will go low. (CS is an active
low pin). In SPI, the 8-bit shift registers are used. After passing of 8 clock pulses, the contents of two
shift registers are interchanged. SPI is full duplex communication.
In SPI protocol both master and slaves use the same clock for communication When CPOL= 0 the idle
value of the clock is zero while at CPOL=1 the idle value of the clock is one.

CPHA=0 means sample data on the leading (first) clock edge, while CPHA=1 means sample data on
the trailing (second) clock edge. The idle value of the clock is zero the leading clock edge is a positive
edge but if the idle value of the clock is one, the leading clock edge is a negative edge.
In SPI protocol both master and slaves use the same clock for communication When CPOL= 0 the idle
value of the clock is zero while at CPOL=1 the idle value of the clock is one.
CPHA=0 means sample data on the leading (first) clock edge, while CPHA=1 means sample data on
the trailing (second) clock edge. The idle value of the clock is zero the leading clock edge is a positive
edge but if the idle value of the clock is one, the leading clock edge is a negative edge.
Fig 4.27. SPI Timing Diagram

Table 4.7. SPI Modes
SPI Mode CPOL CPHA Data Read and Change time
0 0 0 Read on positive (rising) edge, changed on falling edge
1 0 1 Read on negative (falling) edge, changed on rising edge
2 1 0 Read on negative (falling) edge, changed on rising edge
3 1 1 Read on positive (rising) edge, changed on falling edge
4.6.1 SPI in Tiva Microcontroller

The TM4C123GH6PM microcontroller includes four Synchronous Serial Interface (SSI) modules. Each
SSI module is a master or slave interface for synchronous serial communication with peripheral
devices that have Freescale SPI, MICROWIRE, or Texas Instruments synchronous serial interfaces.
The TM4C123GH6PM SSI modules have the following features:
 Programmable interface operation for Freescale SPI, MICROWIRE, or Texas Instruments
synchronous serial interfaces
 Master or slave operation
 Programmable clock bit rate and prescaler
 Separate transmit and receive FIFOs, each 16 bits wide and 8 locations deep
 Programmable data frame size from 4 to 16 bits
 Internal loopback test mode for diagnostic/debug testing

 Standard FIFO-based interrupts and End-of-Transmission interrupt

 Separate channels for transmit and receive
 Receive single request asserted when data is in the FIFO; burst request asserted when FIFO
contains 4 entries
 Transmit single request asserted when there is space in the FIFO; burst request asserted
 When four or more entries are available to be written in the FIFO.
Most SSI signals are alternate functions for some GPIO signals and default to be GPIO signals at
reset. The exceptions to this rule are the SSI0Clk, SSI0Fss, SSI0Rx, and SSI0Tx pins, which default to
the SSI function. The AFSEL bit in the GPIO Alternate Function Select (GPIOAFSEL) register should
be set to choose the SSI function.
Table 4.8: SPI. Pins Mux Utility
Each data frame is between 4 and 16 bits long depending on the size of data programmed and is
transmitted starting with the MSB. There are three basic frame types that can be selected by
programming the FRF bit in the SSICR0 register:
 Texas Instruments synchronous serial
 Freescale SPI

Microwire
For all three formats, the serial clock (SSInClk) is held inactive while the SSI is idle, and SSInClk
transitions at the programmed frequency only during active transmission or reception of data. The idle
state of SSInClk is utilized to provide a receive timeout indication that occurs when the receive FIFO
still contains data after a timeout period.

For Freescale SPI and MICROWIRE frame formats, the serial frame (SSInFss) pin is active Low, and
is asserted (pulled down) during the entire transmission of the frame.
We focus on the SPI features of SSI module. This microcontroller supports four SSI modules. The SSI
modules are located at the following base addresses:
Table 4.9: SPI Modules base address
Module SSI0 SSI1 SSI2 SSI3
Base Address 0x40008000 0x40009000 0x4000A000 0x4000B000
Clock to SSI: RCGCSSI register is used to enable the clock to SSI modules. We need to write
RCGSSI = 0x0F to enable the clock to all SSI modules.
Fig 4.28. Synchronous Serial Interface Run Mode Clock Gating Control CRCG (SSI) Register
4.6.2 Configuring the SSI

SSICR0 (SSI control register 0) is used to configure the SSI. The generic SPI is used to transfer the
byte size of data, the SSI in Tiva microcontroller allows transfer of data between 4 bits to 16bits.
Fig 4.29. SSI Control O Register

Table 4.9. SSICRO Register Description
Bits Name Function Description

0-3 DSS SSI Data Size select 0x3: for 4-bit; 0x7: for 8-bit; 0xF: 16-bit data
4-5 FRF 0 for SPI, 1 for TI, and 2 for MICROWIRE frame
SSI frame format select
format
6 SPO SSI serial clock polarity Clock Polarity
7 SPH SSI serial clock phase Clock Phase
8-15 SCR SSI serial clock rate BR = SysClk/(CPSDVSR * (1+SCR))
4.6.3 Bit Rate

SSI module clock source can be either from System Clock or PIOSC (Precision Internal Oscillator).
The selected frequency is fed to pre-scaler before it is used by the Bit Rate circuitry. The CPSDVSR
(CPS Divisor) value comes from the pre-scaler divisor register. The lower 8 bits of SSICPSR (SSI
Clock Prescale) register are used to divide the CPU clock before it is fed to the Bit Rate circuitry. Only
even values can be used for the pre-scaler since the D0 must be 0. For the pre-scaler register, the
lowest value is 2 and the highest is 254.
The SSICR0 (SSI Control register 0) allows the Bit Rate selection among other things. The output of
clock pre-scaler circuitry is divided by 1 + SCR and then used as the SSI baud rate clock. The value of
SCR can be from 0 to 255. The below formula is used to calculate the bit rate.
Bit Rate (BR): BR=SysClk/(CPSDVSR × (1 + SCR))
Fig 4.30. SSI Clock Prescaler Register
Example:
For a Bit Rate=50 KHz and SCR=03 in SSICR0 register.
The pre-scaler register value for a given system clock frequency of 16MHz, the BR can be calculated
using above formula as:
BR = SysClk / (CPSDVSR × (1 + SCR))
50 KHz = 16 MHz / (X × (1 + 3).
The pre-scaler value is 0x50 in Hex.
SPI module can act like slave or a master. The value in a MS bit in SSI control register 1 (SSICR1)
decide the microcontroller as master or slave. SSE bit in the SSICR1 register is used to enable/
disable the SPI.

Fig 4.31. SSI Control 1 Register
4.6.4 Data Register

The SSIDR is used for both as transmitter and receiver buffer. In SPI handling 8-bit data, will be placed
into the lower 8-bits of the register and the rest of the register are unused. In the receive mode, the
lower 8-bit holds the received data.
Fig 4.32. SSI Data Register

Status Flag Register: SSISR is used to monitor transmitter/receiver buffer is empty.
Fig 4.33. SSI Status Register

Table 4.10: SSI Status Register Description
Name Function Description
TFE Transmit FIFO empty 1: Transmit FIFO is empty
TNF Transmit FIFO full 1: Transmit FIFO is not empty
RNE Receive FIFO not empty 1: Receive FIFO is not empty
RFF Receive FIFO full 1: Receive FIFO is full
BSY SSI Busy Bit 1: transmission or reception is under progress
4.6.5 SPI data Transmission

To perform SPI data transmission, follow the steps given below:
 Enable the clock to SPI module in system control register RCGCSSI.
 Before initialization, disable the SSI via bit 1 of SSICR1 register.
 Set the Bit Rate with the SSICPSR prescaler and SSICR0 control registers.
 Select the SPI mode, phase, polarity, and data width in SSICR0 control register.
 Set the master mode in SSISCR1 register.
 Enable SSI using SSICR1 register.

 Assert slave select signal.

 Wait until the TNF flag in SSISR goes high, then load a byte of data into SSIDR.
 Wait until transmit is complete that is, transmit FIFO empty and SSI not busy.
 De-assert the slave signal
4.6.6 NVIC interrupt for SSI

Interrupt handler can be used for transmission and reception of data. By enabling the interrupt in
SSIIM (SSI Interrupt mask) register, NVIC interrupt controller will enable interrupts from SSI and
execute the corresponding interrupt service routine. All SSI interrupts are masked upon reset.
Table 4.11. SSI Interrupt Mask Register

RORIM Receive overrun interrupt mask 0: Receive FIFO overrun interrupt is masked; 1: not
masked
RTIM Receive Time out interrupt mask 0: Receive FIFO time out interrupt is masked; 1: not
masked
RXIM Receive FIFO interrupt mask 0:Receive FIFO interrupt is masked ; 1: not masked
TXIM Transmit FIFO interrupt mask 0: Transmit FIFO interrupt is masked; 1: not masked
* Program for Tiva Microcontroller to use SSI1 (SPI) to transmit A to Z characters */

#include "TM4C123GH6PM.h"
void init_SSI1(void);
void SSI1Write(unsigned char data);
int main(void)
{ unsigned char i;
init_SSI1(); for(;;)
{for (i = 'A'; i <= 'Z'; i++)
{SSI1Write(i); /* write a character */
}void SSI1Write(unsigned char data)
{GPIOF->DATA &= ~0x04; /* assert SS low */
while((SSI1->SR & 2) == 0); /* wait until FIFO not full */
SSI1->DR = data; /* transmit high byte */
while(SSI1->SR & 0x10); /* wait until transmit complete */
GPIOF->DATA |= 0x04; /* keep SS idle high */
void init_SSI1(void)

{ SYSCTL->RCGCSSI |= 2; /* enable clock to SSI1 */

SYSCTL->RCGCGPIO |= 8; /* enable clock to GPIOD for SSI1 */
SYSCTL->RCGCGPIO |= 0x20; /* enable clock to GPIOF for slave select */
/* configure PORTD 3, 1 for SSI1 clock and Tx */
GPIOD->AMSEL &= ~0x09; /* disable analog for these pins */
GPIOD->DEN |= 0x09; /* and make them digital */
GPIOD->AFSEL |= 0x09; /* enable alternate function */
GPIOD->PCTL &= ~0x0000F00F; /* assign pins to SSI1 */
GPIOD->PCTL |= 0x00002002; /* assign pins to SSI1 */
/* configure PORTF 2 for slave select */
GPIOF->DEN |= 0x04; /* make the pin digital */
GPIOF->DIR |= 0x04; /* make the pin output */
GPIOF->DATA |= 0x04; /* keep SS idle high */
/* SPI Master, POL = 0, PHA = 0, clock = 4 MHz, 16 bit data */
SSI1->CR1 = 0; /* disable SSI and make it master */
SSI1->CC = 0; /* use system clock */
SSI1->CPSR = 2; /* prescaler divided by 2 */
SSI1->CR0 = 0x0007; /* 8 MHz SSI clock, SPI mode, 8 bit data */
SSI1->CR1 |= 2; /* enable SSI1 */
void SystemInit(void)
{ SCB->CPACR |= 0x00f00000;
}

Case study: Tiva based “Sensor Hub BoosterPack”

Weather broadcasting system require some smart technique to monitor the weather conditions of
different places. It is useful for the meteorological department for the detection of the environmental
condition with the help of a balloon. In this case study we are using four sensors Accelerometer,
gyroscope, temperature sensor and pressure sensor. The Tiva booster pack with various sensors is
mounted on the balloon and accelerometer used for the detection of acceleration of the balloon and
gyro scope is used for the position detection of the balloon and pressure and temperature sensor
senses pressure and temperature of the environment respectively. These all gathered information sent
to the ground station with the help of satellite communication system installed at the balloon and the
meteorological department‟s ground station. The collected information is used for the public weather
broadcasting.
Fig 4.35 Booster Pack Pinout Standard

Fig 4.36. Flowchart: Interfacing TIVA with Sensor Hub Booster Pack

www.ti.com Summary
4.7 Summary
The chapter discusses several serial communication protocols used for data transfer between
microcontroller and external devices. Serial communication protocols like UART, SPI and I2C are used
for connecting various analog sensors, actuators, external components such as memory, camera etc.
The TIVA microcontroller consists of serial modules such as UART, SPI, I2C and CAN protocol
embedded in a single Synchronous communication interface (SCI) module. The chapter discusses the
programming of serial communication modules where the reader will be able to configure and use the
communication protocol with the help of TIVAware peripheral driver library. The chapter concludes with
a case study involving SensorHub BoosterPack interfacing with TIVA microcontroller.


1. What types of protocols supported by Microcontroller?
2. What is the asynchronous and synchronous protocol in the Microcontroller?
3. What is UART? What are different -different modes for the communication of UART?
4. Explain the UART register map With the TIVATM TM4C123GH6PM Microcontroller.
5. What is inter IC (i2 C) communication protocol?
6. Explain the characteristics of the I2C Protocol in detail.
7. Explain the status and flag registers in I2C in TIVATM TM4C123GH6PM.
8. How I2C bus is configured in TIVATM TM4C123GH6PM?
9. What is SPI? Discuss SPI protocol in detail.
10. How data transmission takes place in the SPI? How SPI bus is configured in TIVATM
Microcontroller?

Chapter 5
Embedded Networking and Internet of Things (IoT)
The previous chapter covered the process of communication between devices with wired medium using
different protocols such as UART, I2C, and SPI for sensor based and data logging applications.
As a next step, the current chapter covers IoT applications by configuring the CC3100 Wi-Fi module in
access point mode to achieve the applications like get weather, smart plug etc.
By the end of this chapter, readers can expect to have a better understanding of embedded networking and
know IoT fundamentals including its architecture and applications. This chapter also covers wireless
connectivity protocols and their application areas.
Readers will also acquire knowledge about CC3100 SimpleLink Wi-Fi module and its architecture and learn
how to interface CC3100 module with TIVA Launchpad
Topic Page
5.1 Introduction........................................................................................................................................ 156
5.2 Embedded Networking Fundamentals .............................................................................................. 156
5.3 TCP/IP Introduction IoT overview and architecture .......................................................................... 161
5.4 Wireless Sensor Networks ................................................................................................................ 166
5.5 Various Wireless Protocols and their Applications ............................................................................ 169
5.6 Adding Wi-fi to a Microcontroller-Based System using CC3100 Simplelink Wi-fi Module ............... 171
5.7 Case Studies with SimpleLink Wi-Fi CC3100 and TIVA Launchpad ................................................ 176
5.8 Summary ........................................................................................................................................... 183
Embedded Networking and Internet of Things (IoT) 155

5.1 Introduction
Embedded networking technologies such as ZigBee, NFC, Bluetooth, Wi-Fi etc. are key elements in
designing internet enabled applications. For example, in a residential set-up, these enable control of all
devices remotely, even if there is no one physically present in the house. Such a „Smart home’
allows the owner to monitor and control all smart equipment including power controls, security devices
such as surveillance camera, etc. remotely. That is possible by using Wi-Fi technology, gateway
solutions that provide connection to Cloud and of course the Internet to access the devices. Other
typical application areas are monitoring, smart Grid, Smart Transport, smart plug, wearable devices,
health monitoring etc.
Fig 5.1. Embedded Network

This chapter covers wireless sensor networks as well as different wireless protocols, which provide
connectivity between smart devices and gateway solutions. Readers will also learn about the CC3100
wireless module and how its architecture that provides wireless connectivity can be interfaced with
TIVA C Series. The chapter also discusses the configuration of this module in access point mode with
the TIVA launchpad for use in typical IoT applications.
5.2 Embedded Networking Fundamentals

Microcontrollers are used to design intelligent embedded systems such as smartphones, netbooks,
digital TVs, mp3 players, smart-watches, smart-sensors, etc. These smart things can be connected
together to form an embedded network that imparts intelligence to bigger things like homes, buildings,
fields, forests and cities. Fig. 5.1 shows different sensors and systems involved in a typical smart-home
application. An embedded network of smart things like automatic home appliances, lights, door
sensors, CCTV cameras, refrigerators, etc. can provide smart-home users with more convenient and
high-quality living experience.
156 Embedded Networking and Internet of Things (IoT

www.ti.com Embedded Networking Fundamentals
Fig. 5.2. Embedded Network for Smart Home Application
5.2.1 Embedded Network and Ethernet

Today's embedded systems designers and developers are increasingly asked to incorporate Ethernet
connectivity into their systems. Ethernet's ubiquity and longevity in connecting to a network makes it an
attractive networking choice for embedded systems.
Ethernet is a local area network (LAN) technology that is widely used to connect computers using
wires or cables. Ethernet is similar to Wi-Fi technology, but with a different medium. Ethernet is wired,
and Wi-Fi is wireless.
Ethernet is based on standards (IEEE802.3) that ensure reliability of network connections and data
transmission and interoperability. Ethernet networks are scalable from the simplest to most complex
networks or up to 2^48 network nodes.
Once equipment is connected to an Ethernet network, it can be monitored or controlled through the
Internet removing any distance barrier that may have inhibited remote communication previously.
Based on its ease of use, low cost, high bandwidth, stability, security and compatibility across devices,
Ethernet has become the de facto standard of network access for 32-, 16- and even 8-bit
microcontrollers.
As we see from the below block diagram, MCU and Ethernet controller can make any device
connected to the World Wide Web. Thus it helps in monitor, control or access devices over internet.

Embedded Networking Fundamentals www.ti.com
Fig 5.3. Embedded networking with Ethernet

User Datagram Protocol (UDP)
UDP is one of the core members of the Internet protocol suite and it uses a simple connectionless
transmission model with a minimum of protocol mechanism. It has no handshaking dialogues, and thus
exposes the user's program to any unreliability of the underlying network protocol. UDP provides
checksums for data integrity, and port numbers for addressing different functions at the source and
destination of the datagram.
UDP is smaller, faster, and more suitable for fast embedded network communication. UDP allows
embedded devices to use the Internet Protocol (IP) to send data to, and receive data from remote
network nodes. The remote nodes can be on the same local network, or on remote networks that are
accessible over the Internet.
UDP data is sent in connectionless packets. That means the UDP and IP protocols do not guarantee
delivery, the node sending data cannot assume the intended recipient received the data just because
the data was sent onto the network. So UDP packets requires acknowledgement of receipt must be
manually acknowledged by the receiving application.
Network Addressing
A network address is an identifier for a node or network interface of a telecommunications network.
Different nodes on the same network are identified by their IP address. Each single network node can
run multiple applications that use the same network interface, and therefore use the same IP address.
Different applications running on the same network node, and therefore at the same IP address, are
identified by their port number.
The source and destination address of each UDP packet is therefore a combination of an IP address
and a port number.
Sockets and Binding
Sockets are conceptual end points of a network communication. Sockets can send and receive data.
Each socket needs a unique address. As already stated, an address is the combination of an IP
address and a port number. When a socket is created it assumes the IP address of the network node
158 Embedded Networking and Internet of Things (IoT)

www.ti.com Embedded Networking Fundamentals
that created it. If a socket has an IP address but not a port number, it is said to be 'unbound'. An
unbound socket cannot receive data because it does not have a complete address. When a socket
has both an IP address and a port number it is said to be 'bound to a port', or 'bound to an address'. A
bound socket can receive data because it has a complete address. The process of allocating a port
number to a socket is called 'binding'.
Client and Server
Servers are applications that wait for and then reply to incoming requests. Clients are applications that
send requests to servers. In this context, the requests and replies go over the network and clients need
to locate servers. Servers do not need to know the client's address in advance, they just send their
replies to the address from which the client's request originated and therefore clients can bind to nearly
any port number.
The sequence diagram below shows a socket being created and bound on both an echo client and an
echo server, and then a single echo transaction between the client and the server. Echo servers simply
echo back the data sent to them by clients.
Fig 5.4 Transaction between an echo client and an echo server

Static IP Address: An Internet Protocol address is an address used in order to uniquely identify a
device on an IP network. The address is made up of 32 binary bits, which can be divisible into a
network portion and host portion with the help of a subnet mask. If the IP address is 'static' then it is
pre-assigned and never changed. Static IP addresses are useful during application development.
Dynamic Host Configuration Protocol (DHCP): As we discussed in the above concept the IP
address can be pre-assigned but it is impractical for product deployment and cannot be pre-assigned
to products without prior knowledge of the network environment in which the products will be deployed.
And also there is no prior knowledge of how many nodes will exist on the network, or indeed how
many of the possible total number of nodes will be active at any one time.
DHCP provides an alternative to static IP address assignment. DHCP servers exist on local networks
to dynamically allocate IP addresses to nodes on the same network. When a network enabled product
Embedded Networking Fundamentals www.ti.com
boots up it contacts the DHCP server to request its IP address, removing the need for each node to be
statically configured.
Sub-netting / Netmask: A subnetwork, or subnet, is a logical, visible subdivision of an IP network. The
practice of dividing a network into two or more networks is called sub-netting. Sub-netting is a way of
determining whether a destination IP address exists on the local network or a remote network. Like the
IP address, the subnet mask can be configured either statically or dynamically from a DHCP server. If
a destination IP address bitwise ANDed with the subnet mask matches the local IP address bitwise
ANDed with the subnet mask then the two IP addresses exist on the same network.
Gateways and Routers: A gateway acts as a conversion from one protocol to another. A router works
by looking at the IP address in the data packet and decides if it is for internal use or if the packet
should move outside the network. If a destination IP address bitwise ANDed with the subnet mask
does not match the local IP address bitwise ANDed with the subnet mask then the two IP addresses
do not exist on the same network. In this case the packet being sent to the destination address cannot
be sent directly, and must instead be sent to a gateway for intelligent inter-network routing.
Domain Name System (DNS): The Domain Name System (DNS) is a hierarchical distributed naming
system for computers, services, or any resource connected to the Internet or a private network. It
associates various information with domain names assigned to each of the participating entities. Most
prominently, it translates domain names, which can be easily memorized by humans, to the numerical
IP addresses needed for the purpose of computer services and devices worldwide. The Domain Name
System is an essential component of the functionality of most Internet services because it is the
Internet's primary directory service. For example, entering "ping www.freertos.org" in the command
console of a desktop computer will show a ping request being sent to the IP address 195.8.66.1 (today
anyway) a DNS server resolved the string "www.freertos.org" to the IP address 195.8.66.1.
Address Resolution Protocol (ARP): The Address Resolution Protocol (ARP) is a telecommunication
protocol used for resolution of network layer addresses into link layer addresses, a critical function in
multiple-access networks.
Assuming a conventional wired network is used, UDP messages are sent in Ethernet frames. UDP
messages are sent between IP addresses, but Ethernet frames are sent between MAC (hardware)
addresses. Therefore, the MAC address of the destination IP address must be known before an
Ethernet frame can be created. The Address Resolution Protocol (ARP) is used to obtain MAC address
information.
In a smart home application, Ethernet can be used to monitor and control entry to the house by
enabling the door sensors of all the entry points. Fig. 5.5 shows the various components of an Ethernet-
based smart home. User can send a command to activate all the door sensors with the click of a
mouse. This message is sent from the user PC to the Gateway device over Ethernet connection. This
gateway device then delivers this message to the network of door sensors using wireless technology
like ZigBee.

www.ti.com TCP/IP Introduction IoT overview and architecture
Fig. 5.5 Smart Home Architecture with Ethernet interface to the sensor network
5.3 TCP/IP Introduction IoT overview and architecture

Communication between computers or embedded devices in a network involves exchanging useful
messages over a medium like air, telephone line, Ethernet, etc. Each device must have an address or
ID using which, it can be uniquely identified in the network. The devices must follow some rules while
communicating with each other, so that messages are exchanged in a proper manner. IP (Internet
Protocol) provides a set of unique addresses to the devices, whereas TCP (Transport Control Protocol)
describes a set of rules to be followed to exchange messages in a proper way.
In the smart home application shown in fig. 5.6, TCP/IP protocol can be used over Ethernet to provide
Internet connectivity to the outside world. As shown in fig. 5.4, this will enable the user to monitor or
control the smart home functions from anywhere in the world using a PC, laptop or a smartphone.
Fig. 5.6 Smart Home Architecture with TCP/IP connectivity to the Internet
5.3.1 Internet Protocol version 6 (IPv6)

IPv6 is the most recent version of the Internet Protocol (IP), the communications protocol that provides
an identification and location system for computers on networks and routes traffic across the Internet.

TCP/IP Introduction IoT overview and architecture www.ti.com
IPv6 advantages for IoT:
 Adoption: The Internet Protocol is a must and a requirement for any Internet connectivity. It is
the addressing scheme for any data transfer on the web.
 Scalability: IPv6 offers a highly scalable address scheme. The present scheme of Internet
Governance provides at most 2 x 1019 unique, globally routable, addresses.
 Solving the NAT barrier: Due to the limits of the IPv4 address space, the current Internet had
to adopt a stopgap solution to face its unplanned expansion: the Network Address Translation
(NAT). It enables several users and devices to share the same public IP address. The NAT
users are borrowing and sharing IP addresses with others. While this technique allows single
stakeholders to mount large applications, it becomes completely unmanageable if the same
end-points are to be used by many different stakeholders; this would occur in an IoT
deployment where the same sensors are to be used by multiple, independent, stakeholders.
Secondly the mechanism cannot be used to access specific end-points from the Internet.
 Multi-Stakeholder Support: IPv6 provides for end devices to have multiple addresses and an
even more distributed routing mechanism than the IPv4 Internet. This allows different
stakeholders to assign IoT end-device addresses that are consistent with their own application
and network practices. Thus multiple stakeholders can deploy their own applications, sharing a
common sensor/actuation infrastructure, without impacting the technical operation or
governance of the Internet.
5.3.2 Internet of Things (IOT):

Klevin Ashton introduced the term “Internet of Things” (IOT), to the world of technology in 1999. Since
then, IoT has generated a lot of interest, and it is expected that the number of „things‟ connected to
IoT will grow from 20 billion things in 2015 to an estimated 200 billion by 2020. It refers to a scenario
in which all the real-life things (including objects, people and animals) are connected to internet, and
can transfer data over it preferably to a cloud. This data can then be used by businesses and the
people, to create a world of new possibilities and to benefit from it. Fig. 5.7 shows the three main
components of IoT i.e. things, data (cloud) and the people. For e.g. a smart refrigerator can sense the
quantity of items inside it, and then automatically generate a shopping list to be ordered on-line. This
list is put by the smart refrigerator on the cloud, where the best deals are offered for online purchase.
Table 1 shows the mapping of the components of the IoT architecture to the smart refrigerator
example.

Fig. 5.7. Main components of IoT

IOT is considered as a scenario of accessing any information from anywhere and accessible to
everyone. This is described as follows:
 Anything: Eventually, any device, appliance or entity will be seamlessly connected to the
Internet. Connectivity will not be the main feature of the device, but will extend the device‟s
capabilities.
 Anywhere: Any conceived wireless connectivity framework should be abstract enough to run
from any location – both geographically and from a network topology perspective. The former
refers to Internet-based ubiquity; the latter, refers to the ability to clone the framework into
intranet environments where Internet access is limited or undesired. Acknowledging the
structure of the Internet beyond the public domain is important to enable the expansion of the
IoT paradigm.
 Anyone: Currently, not all things are connected to the IoT. But an IoT ecosystem that is easy
to use and secure is not that far away. This will make the IoT accessible to anyone. Anyone
will be able to connect their product to the Internet, and also customize it to their personal
preferences.
5.3.3 Applications of IOT

With the industry’s broadest IoT-ready portfolio of wired and wireless connectivity technologies,
microcontrollers, processors, sensors and analog signal chain and power solutions, TI offers cloud-
ready system solutions. From high-performance home, industrial and automotive applications to
battery-powered wearable and portable electronics or energy-harvested wireless sensor nodes, TI
makes developing applications easier with hardware, software, tools and support to get anything
connected as an IoT device.
In automotive appliances, IoT is mainly used for infotainment purposes such as connecting between
the phones and the speakers of the car, activating the engine through voice control etc.
The IoT paradigm discussed may be encountered in a wide variety of venues that span across various
activity circles throughout the day using different kinds of devices. In the personal area network we

TCP/IP Introduction IoT overview and architecture www.ti.com
encounter wearable devices for entertainment and location tracking. For example, it can be a Bluetooth
headset or a GPS tracker. These devices facilitate the user to help enhance their health and wellness,
and to gather information around the user. At home we are surrounded with an ever-growing number of
appliances, multimedia devices and other consumer gadgets. In home automation systems,
IoT applications include monitoring and controlling the devices inside a home in an intelligent way.
They include lighting and temperature control among the connected appliances for effective use of
energy.
While on-the-go, we use private or public transportation vehicles and infrastructure to improve our
mobility time utilization. In industries, sensors might be introduced for production efficiency,
maintenance and failure management. And at a metropolitan level smart building management
systems include smart cities equipped with smart city lights, residential e-meters, surveillance cameras
for traffic control, pipeline leak detection etc. Healthcare IoT applications include remote monitoring of
patients for example heart rate, blood pressure level etc.
5.3.4 Architecture of IOT

The IoT players: We need to get a wider view of the IoT playground. To do that, the key players must
first be identified. We classify the players into three clusters: users, things and services (Figure 5.8).
 Users are human participants that use services and their own end equipments. They mostly
consume information and may inspire actions through profile settings and other decision-
making processes.
 Things are physical or virtual endpoints representing either a data source, data sink or both.
They feed or consume information to and from the Internet.
 Services are information aggregators and may provide tools for data analysis of different kinds.
In some cases can be used to carry out actions requested by clients, either users or things.
Fig 5.8. The IOT Players

The different devices and environments needed in IoT can be layered as shown in the Figure 5.3. The
sensors and devices needed in the IoT environment are the bottom layer. The different types of
sensors can be temperature, pressure, moisture etc. The data captured by the sensors needs to be
processed using processors and enabling technologies. The technologies include RFID detection,
motion sensing etc. Some of the technologies that enable these devices are discussed further in the
Wireless Sensor networks section. Examples include Bluetooth, Wi-Fi etc. The processed data can be
stored using cloud infrastructures and thus in turn provide different IoT services. The different types of
IoT services include Home automation, healthcare services, energy management, emergency services
among others.
Figure 5.9. Architecture of IoT
5.3.5 Challenges of IOT

Preparing the lowest layers of technology for the horizontal nature of the IoT requires manufacturers
to deliver on the most fundamental challenges, including:
 Connectivity: There is not one connectivity standard that “wins” over the others. There are a
wide variety of wired and wireless standards as well as proprietary implementations used to
connect the things in the IoT. The challenge is getting the connectivity standards to talk to one
another with one common worldwide data currency.

Wireless Sensor networks www.ti.com
 Power management: More things within the IoT need to be battery powered or use energy
harvesting to be more portable and self-sustaining. Line-powered equipment need to be more
energy efficient. The challenge is making it easy to add power management to these devices
and equipment. Wireless charging incorporates connectivity with charge management.
 Complexity: Manufacturers are looking to add connectivity to devices and equipment that has
never been connected before to become part of the IoT. Ease of design and development is
essential to get more things connected especially when typical RF programming is complex.
Additionally, the average consumer needs to be able to set-up and use their devices without a
technical background
 Rapid evolution: The IoT is constantly changing and evolving. More devices are being added
everyday and the industry is still in its naissance. The challenge facing the industry is the
unknown; unknown devices, unknown applications, unknown use cases. Given this, there
needs to be flexibility in all facets of development. Processors and microcontrollers4 that range
from 16–1500 MHz to address the full spectrum of applications from a microcontroller (MCU) in
a small, energy-harvested wireless sensor node to high-performance, multi-core processors for
IoT infrastructure. A wide variety of wired and wireless connectivity technologies are needed to
meet the various needs of the market. Last, a wide selection of sensors, mixed-signal and
power-management technologies are required to provide the user interface to the IoT and
energy-friendly designs.
 There are several fundamental features that a “thing” has to encompass to be a good IoT
solution. Among these, the most important features are energy efficiency, security, data
handling and simplicity.
 Energy Efficiency: As the number of devices grows, even small amounts of excessive power
are a noticeable waste. When it comes to power, the challenge is to ensure that adding
Internet connectivity does not impose a change to the power supply. In other words, ideally it
should fit within the existing power budget headroom. The TIVA Launchpad, being an ultra-low
power MCU ensures that the IoT application takes minimal power.
 Security: Security is always a challenge in data networks. This challenge intensifies in the case
of the IoT simply because there are more entry points thereby creating more penetration
points. This increased system vulnerability makes the battle for security inevitable. In an IoT
solution, threats also take a new level of magnitude since it is not just data that is put at risk.
With IoT the damage potential is much higher (e.g., opening a door remotely, taking a burglar
alarm system offline). There will surely be a never-ending fight towards better security. This
provides inbuilt security features to address major security requirements.
 Data handling: Massive deployment of endpoints results in higher node density. This requires
demand for higher capacity. Furthermore, large quantities of data that are generated create a
need for accessible storage. In addition, real network latency introduces a challenge to limited
resource systems. The TI wireless modules provide easy interfacing with the TIVA Launchpad
to provide connectivity that suits the need of the IoT application.
5.4 Wireless Sensor Networks

Wireless Sensor Networks (WSNs) are networks of tiny, battery powered sensor nodes with limited on-
board processing, storage and radio capabilities. Recent advances in micro-electro-mechanical
systems (MEMS) technology, embedded electronics and wireless communication have made it

www.ti.com Wireless Sensor Networks
possible to develop low-power and low-cost sensor nodes that are small in size and communicate
using wireless medium over short distances. The sensor units in the nodes can sense any desired
parameter (like temperature, pressure humidity, movement etc.) in an area that is covered by the
network. The sensed data is then relayed through the network to the base station, where information
can be generated and acted upon to serve the purpose for which the network has been deployed.
Thing Smart Refrigerator
Cloud services A place to store the shopping list generated by the

smart refrigerator
The owner of the smart refrigerator

People
The company that finds and offers the best deals for
online purchase
WSNs are on the verge of being utilized for many challenging real-life applications like early
earthquake warning systems, battlefield surveillance, environment and habitat monitoring, healthcare,
smart homes and buildings etc... This involves deploying a large number of nodes in the area to be
sensed by the network. This large-scale deployment often requires the nodes to possess self-
organizing capability to form a network without any human intervention. A typical cluster-based sensor
network topology as shown in Fig. 5.10 consists of a base station, cluster-head nodes and sensor
nodes. The base station is normally connected to the outside world through internet link or a user
terminal.
Fig. 5.10. A Typical Sensor Network Architecture

Wireless Sensor Networks www.ti.com
5.4.1 Wireless Connectivity in Embedded Networks

Wireless communication has become a preferred choice for connecting the devices in embedded
networks. Communication technologies like NFC, ZigBee, Bluetooth, WiFi, and cellular have already
become popular with developers working on Smart Homes, Sensor Networks and IoT based
applications. The choice of a connectivity option depends upon various factors like communication
range, bandwidth requirements, security issues, and power consumption.
Before learning more detail about these wireless communication technologies, a brief overview of the
Open System Interconnection (OSI) model used for communication between two entities is given
below:
OSI Model for Communication
OSI model is a conceptual model that is used to organize the various functions of a communication
system by arranging them into seven different layers as shown in Fig. 5.11. The function performed by
each layer in implementing an end-to-end
communication system is described below:
1. Physical Layer: This layer specifies the physical
medium used to transmit bits between communicating
systems. In wired systems, the physical layer may
specify the use of copper wires or fiber optic cable for
wired systems. Similarly for wireless technology like
ZigBee, the physical layer specifications mention the
use of 2.4 GHz ISM frequency band as one of the
options for communication.
2. Data Link Layer: When two or more nodes try to use
the physical media simultaneously for data transfer, the
data packets may collide and, the nodes need to try
again for access to the media. In this case, data link
layer acts as a local traffic cop to regulate the medium
access by the nodes of the network. Another important
role of the data link layer can be to detect and correct
the errors that may occur when data is transferred on
the medium.
3. Network Layer: The primary function of network layer
is to forward data packets (received from higher layers) Fig. 5.11 Protocol stack of OSI
from one point to another over the network. The data Model
packets may travel across many different networks, guided on the way by gateway and router devices,
to their final destination.
4. Transport Layer: This layer provides a reliable end-to-end connection oriented data transfer along
with error and flow control services. Transmission Control Protocol (TCP) is the most common transport
layer protocol used on Internet.
5. Session Layer: The reliable end-to-end connection provided by transport layer is used to set-up an
interactive session between the two communicating computers or end-user applications. The session
layer protocols are responsible to open, manage and close these sessions to support effective data
communication.
www.ti.com Various Wireless Protocols and their Applications
6. Presentation Layer: This layer ensures that the data presented to the application layer is in proper
format and ready to be used. For example, data transmitted in EBCDIC-code by the sender may be
converted at the receiver end by presentation layer to ASCII code format used by the application layer.
7. Application layer: The protocols used in this layer define the user interface that finally displays the
information to the user.
The protocol stack of the OSI model is a valuable reference to understand the working and underlying
differences between many wireless technologies as discussed in the following text.
5.5 Various Wireless Protocols and their Applications
Fig 5.12.. Comparison of different wireless technologies
5.5.1 Near Field Communication (NFC)

NFC is a wireless communication technology that enables two devices to interact when they are in
very close proximity to each other. For example, smartphones and other such devices can use NFC to
interact with NFC-enabled machines (for e.g. battery-charging portals, ticket-vending machines, ATM,
etc.) to exchange information at a distance of less than 10cm. NFC-enabled devices use globally
available unlicenced radio frequency ISM band of 13.56 MHz on standard ISO/IEC 18000-3 air
interface at rates ranging from 106 kbit/s to 424 kbit/s. Each full NFC device can work in 3 modes:
1. NFC Card Emulation mode – devices act like smart cards, to allow users to perform
transactions like payment or ticketing.
2. NFC Reader/ Writer mode – allows NFC-enabled devices to read information stored on NFC
tags embedded in labels or smart posters.
3. NFC Peer-to-peer mode – NFC-enabled devices can form an adhoc network to communicate
and exchange information with each other.

Various Wireless Protocols and their Applications www.ti.com
5.5.2 ZigBee
ZigBee is an industry-standard wireless networking technology that is suitable for applications that
require infrequent low-power data transfer at low data rates within a 100m range, such as inside a
home or a building. It is an IEEE 802.15.4 based specification for a suite of high-level communication
protocols used to create personal area networks (PAN’s) with small, low-power digital radios. ZigBee-
based PAN’s are suitable for applications like - home entertainment and control, building automation,
industrial control and implementing
wireless sensor networks. It operates in
the ISM radio bands with data rates that
can vary from 20 kbit/s to 250 kbit/s.
The protocol stack for ZigBee (Fig. 5.13)
builds on the physical layer and MAC
layer defined in IEEE standard 802.15.4
for low-rate wireless PAN’s (WPAN’s).
To this, ZigBee adds on specifications
for network layer and application layer.
The ZigBee network layer supports star,
tree and mesh network topologies. The
application layer provides an interface
between ZigBee system and the end-
user applications. A ZigBee network
Fig. 5.13 Zigbee Protocol Stack
may consist of the following three types of
devices:
 ZigBee Coordinator (ZC): It is the most capable device in the network. Each ZigBee network
must have exactly one coordinator device, and it is responsible to build and maintain the network.
The ZC forms the root of the network and also connects to the other networks.
 ZigBee Router (ZR): In addition to communicating with ZC, a ZR device can perform the
function of forwarding/routing data received from other devices.
 ZigBee End Device (ZED): A ZED device can only talk to its parent node, a ZC or a ZR device.
Fig 5.14. Zigbee co-ordinator with end device

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5.5.3 Bluetooth
It is an important short-range communication technology that is widely used in smartphones and many
other fixed as well as mobile devices, for data transfer and building personal area networks. It operates
in the 2.4 GHz ISM frequency band and uses frequency hopping spread spectrum technique. Bluetooth
is a packet-based protocol with a master-slave structure. One master may communicate with upto 7
slaves in a piconet. Two or more piconets can be connected to form a bigger network, called a
scatternet. Bluetooth is widely used in applications like handsfree headset, smartphone-to-smartphone
data transfer, wireless communication between smartphone and car-stereo system, cable-free
connection between PC and I/O modules like mouse, keyboard, printer etc.
Bluetooth in its new avatar as Bluetooth Low Energy (BLE) or
Bluetooth Smart, is expected to be a key technology in near future
for wearable devices that will connect to the IoT, probably through
the smartphones and other such options. Bluetooth Smart is meant
to provide low-cost and low-power consumption while maintaining
the same range as Bluetooth.
Application development with Bluetooth Smart: Texas Instrument’s
CC2460 is a wireless MCU that can be used to design
Fig. 5.15 CC2640 Wireless MCU
Bluetooth Smart enabled applications. The CC2640 contains a
32-bit ARM Cortex-M3 processor running at 48-MHz as the
main processor and a rich peripheral feature set, including a unique ultra-low power sensor controller,
ideal for interfacing external sensors and/or collecting analog and digital data autonomously while the
rest of the system is in sleep mode. The Bluetooth Low Energy controller is embedded into ROM and
run partly on an ARM Cortex®-M0 processor. The Bluetooth Smart stack is available free of charge
from www.ti.com.
5.5.4 Wi-Fi
Wi-Fi is a wireless local area network (WLAN) technology that allows electronic devices to network
using the 2.4 GHz or 5 GHz ISM radio bands. It is based on the IEEE 802.11 MAC and physical layer
standards for WLAN and is the most pervasive choice for connectivity with the Internet, especially in
the home LAN environment. Wi-Fi supports very fast data transfer rates, but consumes a lot of power
which makes it unviable for low-power applications. Nevertheless, the embedded networks, wireless
sensor network applications and Internet-of-Things implementations explicitly make use of Wi-Fi as a
preferred choice for connectivity to the Internet.
5.6 Adding Wi-fi to a Microcontroller-Based System using CC3100 Simplelink Wi-fi Module
To illustrate the use of wireless connectivity in embedded networks, this section discusses the usage
of Wi-Fi technology with a microcontroller. Wi-Fi is very widely used to provide connectivity between
user and embedded systems. For example, a user can interact with utility systems (like AC, Garage
door, Coffee machine, etc.) in a smart-home using a smartphone, provided both (smart-home and
smartphone) are connected to the internet.
TI provides low-power and easy-to-use Wi-Fi solutions that include battery-operated Wi-Fi designs with
more than a year of battery life on two AA batteries. TI’s Simple Link Wi-Fi CC3100 module is
a wireless network processor with on-chip Wi-Fi, internet, and robust security protocols. It can be used

Adding Wi-fi to a Microcontroller-Based System using CC3100 Simplelink Wi-fi Module www.ti.com
to connect any low-cost microcontroller (MCU). A functional block diagram of CC3100 module is shown
in Fig. 5.15
Fig. 5.16 Functional diagram of SimpleLink Wi-Fi CC3100 Module
Fig. 5.17 CC3100 Boosterpack (SimpleLink Wi-Fi) mounted on TIVA Launchpad

5.6.1 Architecture of SimpleLink Wi-Fi CC3100 Module

It is important to understand the hardware and software architecture of any device before using it in a
design. Fig. 5.17 shows the hardware architecture for SimpleLink Wi-Fi CC3100 module, that can be
used to provide Wi-Fi connectivity to
any micro-controller based system. It
consists mainly of two parts:
I. Wi-Fi Network Processor
Subsystem
II. Power-management
Subsystem
Wi-Fi Network Processor
Subsystem:
The Wi-Fi Network Processor
subsystem mainly consists of the
following:
1. Dedicated ARM MCU – It
executes the Wi-Fi and
Internet protocols required to
communicate over the Internet
using Wi-Fi connectivity.
2. ROM – stores pre-
programmed Wi-Fi driver and
multiple Internet protocols
3. TCP/IP Stack – supports
communication with
computer systems on the Fig. 5.18 Hardware Architecture for CC3100
Internet
4. Crypto Engine – provides fast, and secure Wi-Fi as well as Internet connectivity
5. 802.11 b/g/n Radio, Baseband and Medium Access Control - for wireless transmission and
reception of data
6. SPI/ UART Interface – connects the CC3100 module to the host MCU.
Power Management Subsystem
The power management subsystem of CC3100 module provides the CC3100 module with an
integrated DC-to-DC converter with a wide range of power supply from 2.3 to 3.6 V. This subsystem
enables low-power consumption modes such as hibernate with RTC mode, which requires
approximately 7 μA of current.
5.6.2 Features of Wi-Fi supported by CC3100 chip

The Wi-Fi network processor sub-system in SimpleLink Wi-Fi CC3100 device integrates all protocols
for Wi-Fi and Internet, greatly minimizing MCU software requirements. With built-in security protocols,
SimpleLink Wi-Fi provides a simple yet robust security experience. This section discusses the features
of Wi-Fi supported by the CC3100 device. A list of features and the functionality provided by them is
given in Table-1.

Adding Wi-fi to a Microcontroller-Based System using CC3100 Simplelink Wi-fi Module www.ti.com
Table 5.1: Wi-Fi features

Sr. No. Wi-Fi Feature Function/ Utility
Provides 13 channels in 2.4 GHz
1 Supports 1-13 Wi-Fi channels
frequency band
2 Support for WEP, WAP, WAP2 Secure Wi-Fi access
Provides additional security for
3 Enterprise Security
enterprise networks
4 Wi-Fi Protected Set-up with WPS2
Access Point mode with internal HTTP Provisioning methods to connect to
5 Wi-Fi
server
6 SmartConfig technology
Transmits and receives Wi-Fi
7 802.11 Transceiver
packets
8 Supports IPv4 Internet Protocol
802.11 Power save and device deep
9 sleep power with three user Low Power Operation
configurable policies
Up to 8 open sockets
10 User Application Sockets
Up to 2 secured application sockets
5.6.3 CC3100 SimpleLink Driver and its Application Programming Interface (API)
In order to simplify the development using the SimpleLink Wi-Fi devices, TI provides a simple and user
friendly host driver software. This driver software allows any MCU (like TIVA platform) to interact with a
SimpleLink device and performs the following functions:
1. Provides a simple API for user application development.

2. Handles the communication of MCU with the SimpleLInk device.
3. Provides flexibility in working with a MCU, with or without an OS.
4. Works with existing UART or SPI physical interface drivers
5. Compatible with 8-bit, 16-bit or 32-bit MCUs
The SimpleLink Host Driver includes a set of six logical and simple API modules:
 Device API – Manages hardware-related functionality such as start, stop, set, and get device
configurations.
 WLAN API – Manages WLAN, 802.11 protocol-related functionality such as device mode (station, AP,
or P2P), setting provisioning method, adding connection profiles, and setting connection policy.
 Socket API – The most common API set for user applications, and adheres to BSD socket APIs.
 NetApp API – Enables different networking services including the Hypertext Transfer Protocol (HTTP)
server service, DHCP server service, and MDNS client\server service.
 NetCfg API – Configures different networking parameters, such as setting the MAC address, acquiring
the IP address by DHCP, and setting the static IP address.
 File System API – Provides access to the serial flash component for read and write operations of
networking or user proprietary data.

5.6.4 Programmer’s model for CC3100 SimpleLink driver and its API
A programmer using a SimpleLink device needs to know about the different software blocks needed to
build a networking application. This topic describes the recommended flow for most applications.
However, program developers have complete flexibility on how to use the various software blocks.
Programs using the SimpleLink device consist of the following software blocks:
o Wi-Fi subsystem initialization – Wakes the Wi-Fi subsystem from the hibernate state.
o Configuration – WiFi sub-system. This phase refers to init time configuration that does not
happen very often. For instance, changing the WiFi sub-system from a WLAN STA to WLAN
soft AP, changing the MAC address and so forth.
o WLAN connection – The physical interface needs to be established. There are numerous
ways to do so, all of which will be explained in this document. The simplest way is to manually
connect to an AP as a wireless station.
 DHCP – Although not an integral part of the WLAN connection, you need to wait for
the receiving
IP address before continuing to the next step of working with TCP\UDP sockets.
o Socket connection – At this point, it is up to the application to set up their TCP\IP layer.
Separate this phase into the following parts:
 Creating the socket – Choosing to use TCP, UDP or RAW sockets, whether to use a
client or a server socket, defining socket characteristics such as blocking\non-
blocking, socket timeouts, and so forth.
 Querying for the server IP address – In most occasions, when implementing a client
side communication, you will not know the remote server side IP address, which is
required for establishing the socket connection. This can be done by using DNS
protocol to query the server IP address by using the server name.
 Creating socket connection – When using the TCP socket, it is required to establish
a proper socket connection before continuing to perform data transaction.
o Data transactions – Once the socket connection was established, it is possible to transmit
data both ways between the client and the server. Basically implementing the application logic.
o Socket disconnection – Upon finishing the required data transactions, it is recommended to
perform a graceful closure of the socket communication channel.
o Wi-Fi subsystem hibernate – When not working with the Wi-Fi subsystem for a long period of
time, it is recommended to put it into hibernate mode.

Case Studies with SimpleLink Wi-Fi CC3100 and TIVA Launchpad www.ti.com
5.7 Case Studies with SimpleLink Wi-Fi CC3100 and TIVA Launchpad
5.7.1 Case Study -1

Get Whether application using CC3100.
This application demonstrates how to connect to openweathermap.org server and request for weather
details of a city. The application opens a TCP socket w/ the server and sends a HTTP Get request to
get the weather details. The received data is processed and displayed on the console window as
shown below.
Fig 5.19.Block diagram of Get Weather application
Fig 5.20. Get Weather Application Console Window

www.ti.com Case Studies with SimpleLink Wi-Fi CC3100 and TIVA Launchpad
Fig 5.21. Flow Chart of getting weather application

To perform this application, we need to set an IP address for the device CC3100 with TIVA
Launchpad. We can set IP address for the device CC3100 statically or dynamically as we discussed in
the session. The below steps demonstrates the configuration of a static IP address for CC3100 TIVA
Launchpad. Here the device connects to the Access Point (AP) with the configured static IP. The static
IP address is stored inside the non-volatile memory of CC3100.The basic steps for assigning IP
address to a CC3100 device are given in the flowchart shown in fig. 5.22.

Fig 5.22 Flowchart for configuring a static IP address for CC3100 module
In this case study the module CC3100 is configured as a Wireless Local Area Network (WLAN) Station
to connect to the internet and open weather.org as a server. A wireless local area network (WLAN) is a
wireless computer network that connects two or more devices without wires within a confined area for
example within a building. This facilitates the users to stay connected without physical wiring
constraints and also access Internet. Wi-Fi is based on IEEE 802.11 standards including IEEE 802.11a
and IEEE802.11b.
All nodes that connect over a wireless network are referred to as stations (STA). Wireless stations can
be categorized into Wireless Access Points (AP) or clients. Access Points (AP) work as the base station
for a wireless network. The Wireless clients could be any device such as computers, laptops, mobile
devices, smartphones etc. The flowchart for this case study is shown in fig. 5.23.

Fig. 5.23. Flowchart for using CC3100 as a WLAN Station

We can also make CC3100 module as a HTTP server with TIVA Launchpad. HTTP is an acronym for
Hyper Text Transfer Protocol. HTTP is a client/server protocol used to deliver hypertext resources
(HTML web pages, images, query results, and so forth) to the client side. HTTP works on top of a
predefined TCP/IP. ( Transmission Control Protocol / Internet Protocol). HTTP web server allows end-
users to remotely communicate with the CC3100 by using a standard web browser. The HTTP web
server enables the following functions:
 Device configuration
 Device status and diagnostic
 Application-specific functionality
The HTTP server handles the HTTP request by listening on the HTTP socket id which is by default 80.
Based on the request type, such as HTTP GET or HTTP POST, the server handles the request URI
resource and content. The server then composes the appropriate HTTP response and returns it to the
client. The server communicates with the serial flash file system, which hosts the web page files. The
files are saved in the serial flash with their individual filenames.

If we configure CC3100 as a server then it will be in Access Point (AP) mode with a pre-defined SSID-
NAME and uses the sample HTML pages stored in Flash which can be accessed by the clients. Clients
can connect to CC3100 and request for web-pages using the IP of device from any standard web
browser. There are pre-programmed html pages already residing on the flash and new HTML pages
can be downloaded on serial-flash of CC3100 using CCS_UniFlash utility using a separate tool EMU-
BOOST. The scope of this study will be to use the existing html pages already pre-programmed in the
flash by default. The flowchart for using CC3100 device as a HTTP server is given in fig. 5.24
Fig. 5.24. Flowchart for configuring CC3100 as a HTTP Server
5.7.2 Case Study -2

Smart Plug with Remote Disconnect and Wi-Fi Connectivity
In this application, the WiFi enabled Smart plug helps you to control any connected device from home
or remotely from anywhere in the world with internet access such as home appliances like control
portable heaters or window ac, turn on a light, Smart Grid and in building automation. A smart plug is
an electronic device, generally connected to other devices or networks via different wireless protocols
such as Bluetooth, NFC, WiFi, 3G, etc., that can operate to some extent interactively and
autonomously.
Now an day all application like home automation and building automation requires two main aspects of
Smart Plug technology.

 Android and cloud based remote access.

 Remote disconnect and Wi-Fi connectivity based upon power consumption.
In this case study the WiFi enabled Smart Plug utilizes a TIVA Launchpad to monitor the energy
consumption for a single load and control the high-voltage side of the design. This data is then passed
to a CC3100 module to communicate the data over Wi-Fi to a Cloud server. A solid state relay enables
the application to control the load, based on its energy consumption. And this system is powered from
a highly compact and efficient UCC28910D High-Voltage Flyback Switcher with Primary-Side
Regulation and Output Current Control.
Fig 5.25 Block diagram of Smart Plug with WiFi connectivity

Fig 5.26 Flow chart of Smart Plug with Wi-Fi connectivity

www.ti.com Summary
5.8 Summary
The various connectivity protocols for realizing IoT applications are discussed. TI specific Wi-Fi
connectivity module and its interfacing with TIVA Launchpad is also implemented at the later stage of
the chapter. Various Wi-Fi connectivity concepts used to integrate microcontroller devices with cloud
Systems are also highlighted in the chapter. By understanding these technologies students are able to
implement Wi-Fi connectivity in microcontroller and able to design internet enabled IoT devices.\
Embedded Networking and Internet of Things (IoT 183


1. Name the networking technology that is standardized as IEEE 802.3 standard.
2. Name two topologies that can be used in Ethernet. Also specify the data rates used for
communication between nodes in Ethernet.
3. Name the networking technology that is standardized as IEEE 802.11 standard.
4. What do you understand by the term „IoT (Internet of Things)‟?
5. Name three main components of an IoT application.
6. Name at least five wired/wireless technologies that can used for providing connectivity among
different components of an IoT architecture.
7. Full form of TCP/IP is __________
8. List some basic differences between IPv4 and IPv6 of IP protocol.
9. Give any three points of comparison between ZigBee and Bluetooth technologies.
10. Review the role of CC3100 Wi-Fi booster pack for building IoT applications.
11. Draw OSI model for communication between two entities on a network and briefly mention the
function of all the layers in OSI model.
12. Specify the role of TCP protocol when two devices are communicating with each other on
Internet.
13. Discuss the architectural requirements of an IoT application with the help of a diagram.
14. Draw and explain the basic architecture of a Wireless Sensor Network.
15. With the help of a diagram, discuss the protocol stack for ZigBee technology

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Embedded System Design

2 Embedded System Design using TIVA

2.4.1 Peripheral Addressing ............................................................................................................ 60

Embedded System Design using TIVA 3

3.10 Review Questions ............................................................................................................................. 115

4 Embedded System Design using TIVA

5.4.1 Wireless Connectivity in Embedded Networks ..................................................................... 168

Embedded System Design using TIVA 5

6 Embedded System Design using TIVA

Embedded System Design using TIVA 7

Fig. 5.2. Embedded Network for Smart Home Application......................................................................... 157

8 Embedded System Design using TIVA

9 Embedded System Design using TIVA

Embedded System Design using TIVA 10

Embedded System Design using TIVA 11

Embedded Systems and Features

12 Embedded Systems and Features

1.1.1 Hardware Components of Embedded System

Embedded Systems and Features 13

Fig 1.1. Basic block diagram of an embedded system

14 Embedded Systems and Features

Fig 1.2. Processing Unit and System Bus

Embedded Systems and Features 15

Fig 1.3. (a) Harvard Architecture and (b) Von-Neumann Architecture

16 Embedded Systems and Features

Fig 1.4: Interconnection of RAM with Microprocessor

Embedded Systems and Features 17

Fig 1.5. Interconnection of external devices with Microprocessor

18 Embedded Systems and Features

Fig 1.6. Stepper motor control embedded system

Embedded Systems and Features 19

 Large code size compared to CISC architecture.

1.2 ARM Architecture

Features Benefits to embedded system

Fig 1.7. ARM 7 Architecture [an excerpt from Google image]

20 Embedded Systems and Features

1.2.1 A Basic architecture of the ARM7core

Embedded Systems and Features 21

Fig 1.8. User mode register set

1.2.3 Current Program Status Register (CPSR)

Fig 1.9. A generic CPSR Format

22 Embedded Systems and Features

 C- (Carry flag) = 1 indicates ALU operation generated carry.

 I = 1 indicates IRQ is disabled

 F = 1 indicates FIQ is disabled

 T= 1 indicates the Thumb state is active.

1.2.4 Operating States

1.2.5 Operating Modes

Embedded Systems and Features 23

Abort (abt) 10111

1.2.6 Programming Model

24 Embedded Systems and Features

Fig 1.10. Complete Register Bank

1.2.7 Interrupt and Exception Handling

1.2.7.1 Interrupt Handling

1.2.7.2 Exceptions Handling

Embedded Systems and Features 25

1.2.8 ARM Instruction Set

26 Embedded Systems and Features