Synthesis Assignment - 1
Synthesis Assignment - 1
1 . Realize the hardware for below rtl and also justify whether the realized logic is correct
in-terms of timing requirement
module block1 (
output reg q ,
Input a, b, c,
Input clk,rst_n) ;
always @(posedge clk or negedge rst_n)
if (!rst_n) q <= 0 ;
else begin: logic
reg d ;
d = a & b ;
q <= d ;
end
assign y = q & c ;
Endmodule
3. Estimate rising and falling prorogation delays of a 2-input NAND driving “h” identical
gates using Elmore Delay
4. For the figure shown below, calculate the minimum clock period:
5. Realize hardware for below rtl and analyse the realized hardware against the rtl code and
also list out the bugs if any in the rtl