X-Ray Tubes - Machlett

Mysono 201 Contents
CONTENTS
A TABLE OF CONTENTS
Section 1. Basic Information
1. What is Mysono201?
2. Mysono201 Configuration
2.1 Main body
2.2 Monitor
2.3 Probe
2.4 Accessory
2.5 peripheral unit (Option)
3. Safety precautions
3.1 Safety standard
3.2 Electrical safety
3.2.1 Protection of equipment
3.2.2 Battery safety
3.2.3 Symbol
3.3 Physical safety
3.4 Maintenance and cleaning
3.4.1 Probe
3.4.1.1 Cleaning
3.4.1.2 Disinfection and Sterilization
3.4.2 Biopsy guide adapter and Needle guide
3.4.2.1 Stainless biopsy guide cleaning
3.4.2.2 Stainless biopsy guide sterilization
3.4.2.3 Plastic biopsy guide cleaning
3.4.2.4 Plastic biopsy guide sterilization
3.4.3 The surface of equipment
3.4.1 Cleaning
3.4.2 Sterilization
4. Mysono201 installation
4.1 Probe setting and removing
4.2 Battery setting and removing
4.3 Battery charging and discharging
4.4 System power ON / OFF
4.5 Using AC adapter
5. Mysono201 Function
Mysono201 Precautions Check List
Service Manual Published by Customer Service Department

Mysono 201 Contents
A TABLE OF CONTENTS
Section 2. Description of System
1.System Block Diagram
2. Front End Board (F/E)
2.1General Description
2.2 Block Diagram
2.3 Signal Definition
2.3.1 CPLD Signal Definition
2.3.2 Connector signals between DSC and FE
2.3.3 Connector signals between Power and FE
2.3.4 Connector signals between FE Adapter and FE
2.3.5 Connector signals between FE Adapter and SPC(System Probe Connector)
2.3.6 Connector signals between SPC(System Probe Connector) and Probe
2.4 Scanline Definition
2.4.1 Normal Mode
2.4.2 Synthetic Mode
2.5 Pulser vs Elements
2.6 Specific Description
2.6.1 TGC Amp
2.6.2 Reordering
2.6.3 LPF
2.6.4 Beamfoming IC MCB014A
2.7 PCB Board Lay Out
2.7.1 F/E Top Side
2.7.2 F/E Bottom Side
2.8 Timing Chart
2.8.1 Normal TX Focusing
2.8.2 Synthetic TX Focusing
2.8.3 Control Timing
2.9 Wave Form
3.DSC Board
3.1. Description Overall
3.2. Block Diagram
3.4 Specification explain
3.4.1 B/W Data Receiving & FM storing Part
3.4.1.1 Mid Processor (MGA015)3.4 Specification explain

Mysono 201 Contents
A TABLE OF CONTENTS
3.4.1.2 Pattern generator
3.4.1.3 Before FM controller (MGA001)
3.4.1.4 FM controller (MGA001)
3.4.2 Frame Memory & Cine Memory Flash Memory Part
3.4.2.1 Frame Memory (VRAM)
3.4.2.2 Cine Memory (DRAM)
3.4.2.3 Flash Memory
3.4.2.4 Memory Path by mode
3.4.2.5 Scanline Masking Window
3.4.3 CRD, Graybar, Overlay Post Memory Part
3.4.3.1 CRD
3.4.3.2 Graybar
3.4.3.3 Overlay
3.4.3.4 Overlay Control Scheme
3.4.3.5 Post Memory
3.4.4 Non interlace Output Display Path part
3.4.4.1 Function
3.4.4.2 VGA
3.4.4.3 VHS
3.4.4.3.1 74ACT715 control
3.4.4.4 Non Interlaced B/W (NI B/W)
3.4.5 Interlace TSC/PAL Display Part
3.4.5.1 Frame Grabber CPLD & Memory
3.5.1 DSC Top Side
3.5.2 DSC Bottom Side
3.6 Timing Chart
3.6.1 CRD Timing Chart
3.7 Wave Form
4. Power B/D
4.1 Specification
4.2 Block Diagram
4.3 Specification explain
5.Probe
5.1.General Description

Mysono 201 Contents
A TABLE OF CONTENTS
5.2. Specification explain
5.3 Probe Connector Pin Define
5.5 Probe ID
5.6 PCB Lay Out
5.6.1 PB Main Top Side
5.6.2 PB_ODD Top/Bottom Size
5.6.3 PB_EVEN Top/Bottom Size
6.ASIC Data Sheet

6.1 MAGA0010A Manual (draft): Frame Memory Controller
6.1.1 Description
6.1.1 Description
6.1.3 PIN Diagram
6.2 MAGA003A Manual (draft): Clocks Generators
6.2.1 Description
6.2.2 Main Features
6.2.3 Block Diagram
6.2.4 Pin Diagram
6.3 MAGA005 Manual
6.3.1 Description
6.3.2 Block Diagram
6.3.3 Pin Diagram
6.4 MCB014 Manual
6.4.1 Main Features
6.4.2 Block Diagram
6.4.3 Pin Diagram
6.5 MGA015A Manual
6.5.1 Main Features
6.5.2 Block Diagram
6.5.3 I/O Signal Overview
6.5.4 PIN Diagram
7. I/O Map

Mysono 201 Contents
A TABLE OF CONTENTS
Section 3. Sub Apparatus
1.LCD
1.1 General Description
1.1.1General Display Characteristics
1.2 Maximum Ratings
1.3 Electrical Specifications
1.4 Optical Specifications
1.5 Interface Connections
1.6 Power Sequence
1.7 Mechanical Characteristics
1.8 International Standards ( TBD )
1.8.1. Safety
1.8.2. EMC
1.9 Handling Precautions
1.9.1.Mounting Precaution
1.9.2. Operation Precaution
1.9.3 Electrostatic Discharge Control
1.9.4 Precaution For Strong Light Exposure
1.9.5 Storage
1.9.6 Handling precautions For Protection Film
1.9.7 Safety
A 1 Brightness
A 2 Response Time
A 3 Viewing angle
2. Adapter
2.1 Spec. and Range of application
2.2 Block Diagram
2.3 Schematic Diagram
Section 4. Trouble Shooting

1. Trouble shooting
1.1 System Booting Diagnosis .
1.2 Image1 Diagnosis
1.3 Battery Diagnosis
1.4 Etcetera Diagnosis
2. Debug Mode
2.1 Debug Menu

Mysono 201 Contents
A TABLE OF CONTENTS
Section 4. Trouble Shooting
2.2 Image Memory Debugger Menu
2.3 Keyboard Menu
2.4 Biopsy Menu
2.5 Monitor Menu
2.6 8085 I /O Debugger Menu
Section 5. Replacement Procedures

1.Spare Parts Assembling Diagram
1.1 TFT LCD Monitor Replacement Method
1.2 KEY Matrix PCB Replacement Method
1.3 Trackball Replacement Method
1.4 Each PCB Board Replacement
1.4.1 DSC Board Replacement Method
1.4.2 Front End Board Replacement Method
1.4.3 Power Board Replacement Method
2.Parts List
2.1 Cover Body Bottom Assy Exp.
2.2 Power Assy Exp.
2.3 AY_FE_Board_Exp.
2.4 Adapter B/D Exp.
2.5 Cover Assy Body Top Mysono Exp
2.6 SPC Board Assy Exp.
Section 6. Additional Information

1.Specification
1.1 Technical Specification
1.2 Safety Standard
1.3 Range of measurement and accuracy
1.3.1 B mode Range and accuracy
1.3.2 M mode Range and Accuracy
2. Mysono 201 Compatibility Matrix

Mysono 201 Section 1.1
1. What is Mysono201?
l Mysono201 manufactured by Medison Co.,Ltd is the newest subminiature and portable

ultrasound system with high resolution, deep transmission and variable function for
measurement.
l The several probes such as Curved probe, Linear probe are available for wide usage.
Mysono201 can be used in a variety of applications Abdomen, Obstetrics, Gynecology,
Vascular, Extremity, Pediatric, Cardiac, Urology.
l Mysono201 offers to excellent image quality, several measurement functions such as a
standards distance, area, girth, volume by application for Obstetrics, Cardiac, etc.

Mysono 201 Section 1-2. System Constitution
2. System constitution
The system consists of main body, monitor, probe, accessory, etc.
[Figure 1.1 Mysono201]
MEDISON or local distributor will make available on request circuit diagrams, components
part list, descriptions, calibration instructions or other information which assist your
appropriately qualified technical personnel to repair those parts of equipment which are
designed by Medison as repairable
2.1 Main body

The system is classified by inside for making ultrasound image and by outside for connection
to other parts. The housing of system has controllers, probe connector, connector for monitor
or other accessories, handle and power switch.

2.2 Monitor
It is TFT LCD Monitor and displays ultrasound image and related information.
It connects to the main body lack of which can control the angle and the height.
[Figure 1.2 LCD Warning]
[Figure 1.3 LCD Warning]

2.3 Probe
Probe generates ultrasound beam and gain the data for display the image.
Probe list and BIOPSY kit available Mysono201 is as follows;
Application
ID Probe Biopsy kit
Mysono201(Human)
BPL-50/65 Small parts(Breast / Thyroid / Testicle), Muscular,
12 L4-7CD
Skeletal, pediatric, Peripheral-vascular
BPL-75 Small parts(Breast / Thyroid / Testicle), Muscular,

13 L5-9CD
Skeletal, pediatric, Peripheral-vascular
BPL-50/65 Small parts(Breast / Thyroid / Testicle), Muscular,
14 L5-9/60CD
Skeletal l, pediatric, Peripheral-vascular
00 C2-5/60BD Reserved Abdomen, Obstetrics, Gynecology, Fetal heart
BPC-50 Abdomen, Obstetrics, Gynecology, Fetal heart,
03 C4-7BD
Pediatric
EC4- BPC-65-E/C Obstetrics, Gynecology, Urology
04 9/13CD
Vaginal
Human : Image setting, Safety, EMC, AP&I, QA – Total 6 Probe Release.
2.4 Parts
There are supplied with main body.
① Coupling gel
② Power code
③ Power adapter
④ Battery (Option)
⑤ RCA Jack
⑥ Video output cable
⑦ Portable Case
⑧ Operation manual (User guide)
⑨ Smart media (Option) – available hereafter
2.5 Accessories (Option)

It is the optional accessories to connect to the main system. Please refer to supplement OB of
user guide.
① B/W Printer
② VCR
③ Non-Interlaced B / W Monitor
④ VGA Monitor
⑤ VHS Monitor
⑥ HMD

Mysono 201 Section 1-3. Safety Precaution
3. Safety Precautions
[Notes to users]
Thank you for purchasing the Mysono201 Ultrasound system.
To ensure safe operation and long terms performance stability, it is essential that you fully
understand the functions, operating and maintenance instructions by reading this manual
before operating your equipment. The system must be operated only by, or under supervision
of a qualified person.
“Warning” is used to indicate the presence of a hazard that can cause severe personal injury,
death, or substantial property damage if the warning is ignored.
“Caution” is used to indicate the presence of a hazard that will or can cause minor personal
injury or property damage if the warnings ignored.
“Note” is used to notify the user of installation, operation, or maintenance information that is
important but not hazard related. Hazard warnings should never be included under the Note
signal word.
3.1 Safety Precautions

l Classification:
- Class I equipment with Type BF applied parts
- Ordinary Equipment
- Non-AP/APG
l Electromechanical safety standards met:

_ CSA C22.2 No.601.1, Canadian Standards Association, Medical Electrical Equipment
- EN60601-1, Second Edition, including Amendments 1 and 2, European Norm, Medical
Electrical
l Equipment
- EN60601-1-2, First Edition, European No rm, Collateral Standard, Electromagnetic
Compatibility
- IEC61157: 1992, International Electro technical Commission, Requirements for the
declaration of the acoustic output of medical diagnostic ultrasonic equipment
- UL 2601-1, Underwriters Laboratories, Medical Electrical Equipment

3.2 Electrical Safety Precaution

It is classified Class I equipment with Type BF applied parts
To ensure user safety, check the following.
Never open the system safety cover.;

There is a dangerous voltage in system inside. If any repairing or exchanging
of parts is desired, ask to the authorized dealer for the service.
Do not place the system near of flammable gas or anesthesia gas. It has a
danger of explosion.
Before using the system, check the housing and the cables. If it has any crack
on the housing or wear away on cable, stop to use.
Whenever cleaning the system, take off the power code and the battery to
avoid the danger of an electric shock.
To avoid the danger of an electric shock, use the standard device for digital
WARNING
interface of which achieved IEC certificate. (I.e. IEC60950/EN60950 for the
data processing device, IEC60601-1/EN60601-1 for medical device.)
For the more, all parts of system meet standard requirement of IEC60601-1-
1/ EN60601-1-1.
Check whether the peripheral device of input or output port meet standard
requirement of IEC60601-1-1/EN60601-1-1 when add it.
Do not connect to the system signal in/outlet and the patient at the same
time.
It is for preventing to leakage current caused by over the maximum
permissible range.
Even though the system passed the test of EMI/EMC standard, it could be
down the image quality or could damage the system under using magnetic
filed.
If you have a poor image or image problem, check whether the source of
electromagnetic waves is near of the system or not such as Mobile phone,
Pager, Radio, TV or Microwave machine. Please move them far from the
system or move the system from affected zone of electromagnetic waves.
CAUTION Electrostatic discharge (ESD) is a shock occurred by Static electricity and a
phenomenon in nature. ESD occurs in dry condition such like under using
heater or air conditioner.
The static electricity occurred by a user or a patient can affect to the system
or the probe sometimes. To prevent this problem, please be well aware as
follow.
: - Spray the prevent of static electricity spray to carpet or Linoleum
- Use met for protection of static electricity
- Connect a ground between the system and table or bad for patient

3.2.1 System care

Check the following.
In case that tie too much or twist the probe connected with patient, system
could be wrong work.
Wrong cleaning or sterilization of the parts connected with patient is
dangerous.
Refer to “3.4 Maintenance & Cleaning” in this manual.
Do not soak the cable in liquid. It cannot prevent flood.
Do not use strong solvents such as thinner or benzene, or abrasive
cleansers.
Since these will damage the cabinet.
CAUTION
In general, only treat with waterproof on the ultrasound lens part (Safety
grade: IPX7). Do not soak the probe in liquid except the special case with
cleaning guide.
Do not turn the system off under store the image. That will damage the
memory inside.
Turn the system off when remove the probe form the system or connect it
to the system.
Do not keep the system over one hour with close LCD monitor under the
system is working. That will damage the keyboard.
WARNIN The turning radius is limited to suitable use. If it is over the limitation, that
G will damage LCD monitor.
[Safety Figure1. Warning for LCD angle]

[Safety Figure2. Warning for LCD angle]
3.2.2 Battery
Keep in mind the warning and caution to prevent explosion, heat or smoke generation in
battery.,
Do not disassemble or modify the battery.

Keep the circumstance temperature condition when using the battery.
- Charge: 0O ~ 45 O C
- Discharge: -10O ~ 60 O C
Do not short between terminals of battery.
WARNING Do not use the battery under the circumstance like as fire, moisture.
Do not charge the battery where is near of fire or heater.
Keep out of the sun when keep the battery.
Keep out the sharp material to face with battery and do not deliver the
shock directly to it.
Take away the battery from the system when do not use it for a long time.
Do not use the battery except supplied by Medison

Do not use a battery except made by Medison.
Do not charge a battery with non- allowed method.
(Don’t use other charge method)
Keep a battery from moisture.
CAUTION If smell or burn under using battery, discontinue use of system prompt,
remove a battery.
Keep the battery under the circumstance temperature -20O ~ 50 O C.
System working condition and a number of charge/discharge times of
battery affect to time of charge/discharge.
Medison guaranty the battery during 6 month (battery capacity 50%).

3.2.3 Safety Symbols

The international Electrotechnic Commission (IEC) has established a set of symbols for
medical electronic equipment that classify a connection or warm of any potential hazards. The
classifications and symbols are shown below.
Isolated patient connection (IEC 601-1-Type BF)
Power Switch represent ON and OFF, respectively.
This symbol identifies a safety note. Ensure you understand the function of
! this control before using it. Control function is described in the appreciate
operation manual.
Output port or Parallel port of VGA
Output port of VHS

Non-interlaced B/W Printer port
Printer remote output port
Humidity protect

3.3 Physical Safety Precaution
If you have experienced any trouble with the equipment, switch it off
immediately, and contact to Service center or its authorized dealer for
assistance.
Do not use the system under working wrong or trouble.
Non-continuous scanning is caused by hardware problem. It must be
repaired.
WARNING
The using of Ultrasound always needs a careful attention.
Under the principles of ALARA, energy delivered should be “as low as
reasonably achievable” to perform study.
Read the explanation about biopsy before using it. Refer to user
explanation parts of probe an appendix.
Certify biopsy Needle before using it. Do not use curved needle.
ALARA TRAINING PROGRAM
Ultrasound is considered safe at low clinical levels. At high levels and longer exposures,
however, its safety is not completely understood. For this reason, always exercise caution when
exposing patients to ultrasound. Always use the lowest transmit power levels.
And minimize time of exposure. Under the principles of ALARA, energy delivered should be “as
low as reasonable achievable” to perform your study.
The following is a public statement by the one of United Stated Ultrasound Association, AIUM,
on the safety of ultrasound diagnosis.
Ultrasound has been in use since the 1950’s. AIUM declares the clinical safety of ultrasound
scanning and acknowledges its effectiveness as the type medical equipment and its possible
use for diagnosis of pregnant women.
There has been no case which shows cause of any physical damage to either patient or user
during properly performed diagnosis with an ultrasound scanner. Although it might be possible
that unknown effects of ultrasound may come to light in the future, so far the benefits far
outweigh any unproved danger. Theoretically, there are two possible ways that ultrasound
could have negative affect on the human body.
One is the heat generated by ultrasound as it passes through the human body. Doppler
produces the most heat, and it followed by color and B- mode imaging. However, even in the
case of Doppler the amount of heat is so minor that there is no equipment that can measure it.
The other one is the possible formation of a cavity by the ultrasound. However, there has been
no clear evidence that this can actually occur in the human body.
In conclusion, no negative biological effects of ultrasound have been proven thus far.

3.4 Maintenance and cleaning
Whenever maintain or clean the system, turn off the power and remove
WARNING the plug from the power supply. (Remove the battery from the system,
too)
3.4.1 Probe
Always use protective eyewear and gloves when cleaning and disinfecting
WARNING
probes and Biopsy guide adapter.
Probes must be cleaned after each use. Cleaning the probe is an essential
step prior to effective disinfection or sterilization. Be sure to follow the
manufacturer’s instructions when using disinfectants.
CAUTION
Do not allow sharp objects, such as scalpels or cauterizing knives, to touch
probes or cables.
When handling a probe, do not bump the probe on hard surfaces.
Probe is very important part to judge the image quality. The optimum image can display under
using the correct probe.
3.4.1.1 Cleaning
Do not use lacquer thinner ethylene oxide or any other organic solutions,
as these can destroy the membrane of the probe.
Do not use a surgeon’s brush when cleaning probes. The use of even soft
brushes can damage the probe.
CAUTION
During cleaning, disinfection, and sterilization, orient the parts of the
probe that must remain dry higher than the wetted parts until all parts are
dry. This will help keep liquid from entering non-liquid-tight areas of the
probe.
1) Disconnect the probe from the system.

2) Remove any sheaths, biopsy guide adapters, or biopsy needle guides (biopsy guide
adapters are re-usable portion of the biopsy guide and can be sterilized.)
3) Discard sheaths (sheaths are single-use item)
4) Use a soft cloth lightly dampened in a mild soap or compatible cleaning solution to
remove any particulate matter or body fluids that remain on the probe or cable.
5) To remove remaining particulates, rinse with water up to the immersion point.
6) Wipe with a dry cloth; or wipe with a water-dampened cloth to remove soap
residue, and then wipe with a dry cloth.

3.4.1.2 Sterilization
Apply this sterilization way to EC4-9/13CD probe only.
A 10- 6 reduction in pathogens should be reached following the sterilization procedures in this
manual and using the following MEDISON recommended solutions. The following disinfectants
are recommended because of both its biological effectiveness (as qualified through the FDA
510(k) process) and its chemical compatibility with MEDISON ultrasound product materials.
Solution Country Type Active ingredient FDA 510(k)
Cidex USA Liquid Gluteraldehyde K934434
If a pre-mixed solution is used, be sure to observe the solution

expiration date. The level of disinfection required for a device is
dictated by the type of tissue it will contact during use. Ensure that
WARNING the solution strength and duration of contact are appropriate for
disinfection or sterilization. Be sure to follow the manufacturer’s
instructions.
In neurosurgical application, sterilized probes should be used with a
pyrogen-free sheath.
Using a non-recommended disinfection solution, incorrect solution

strength, or immersing a probe deeper or for a period longer than
recommended can damage or discolor the probe and will void the
probe warranty.
CAUTION Do not immerse probes longer than one hour, unless they are
sterilizable. Probes may be damaged by longer immersion times.
Sterilize probes using only liquid solutions. Using autoclave, gas(EtO),
or other non-MEDISON-approved methods will damage your probe
and void your warranty.
7) Mix the disinfection solution (or sterilization solution, for sterilizable probe)
compatible with your probe according to label instructions for solution strength. A
disinfectant qualified by the FDA 510(k) process is recommended.
8) Immerse the probe into the disinfection solution (or sterilization solution, for
sterilizable probe) as shown in the figures below for your probe.
9) Follow the instructions on the disinfection (or sterilization, for sterilizable probe)
label for the duration of probe immersion. Do not immerse probes longer than one
hour, unless they are sterilizable.
10) Using the instructions on the disinfectant or sterilization label, rinse the probe up to
the point of immersion, and then air dry or towel dry with a clean cloth (or a sterile
cloth, for sterilizable probe).
11) Examine the probe for damage such as cracks, splitting, fluid leaks, or sharp edges
or projections. If damage is evident, discontinue use of the probe and contact your
customer service representative.

3.4.2 Biopsy guide adaptor and Needle guide

The reusable external surface of biopsy guide adaptor can sterilize under the condition as
below. It is possible to reduce the pathogens up to 10- 6 as following process.
Gloves and safety mask should be worn during cleaning and sterilizing
WARNING
the probe and biopsy guide adapters.
Biopsy guide have to clean after using. It is very important process.

When using the disinfecting solution, follow the user guide published
CAUTION by manufacturer.
Keep out of the sharp things such like a mess for a surgical operation.
Be careful to avoid striking the biopsy guide with hard material.
3.4.2.1 Cleaning of the stainless biopsy guide

1) Take off the biopsy guide assembly parts from the probe after using.
2) Disassemble the biopsy guide parts each one.
3) Remove an alien substance still remained on each part using by small brush and water.
4) Rinse it with water to remove again an alien substance.

3.4.2.2 Sterilizing of the stainless biopsy guide

Sterilize it by using an autoclave or Ethylene Oxide.
1) Complete the following process after sterilization.
2) Check the biopsy guide adaptor whether it has a crack, division, or any other damage
on it. If there is some damage, stop to use and contact to Medison service agency or its
authorized local service agency.
3.4.2.3 Cleaning of plastic biopsy guide

Take off the biopsy guide assembly parts from the probe after using.
1) Disassemble the biopsy guide parts each one. The consumable parts cannot sterilize.
2) Remove an alien substance still remained on reusable part using by small brush and
water.
3) Rinse it with water to remove again an alien substance.
3.4.2.4 Sterilizing of plastic biopsy guide
Sterilize only a chemical pasteurization at a low temperature.

CAUTION It can get the permanent damage by sterilization using autoclave, gas
or radioactivity.
4) Sterilize it by using a chemical pasteurization at a low temperature approved by FDA

510(K). Check the time (normal 10 hours) and the temperature of solution.
It is a biologically, chemically suitable disinfecting solution approved by FDA 510(k) in

U.S.A.
Solution Country Type Active ingredient FDA 510(k)
Cidex USA Liquid Gluteraldehyde K934434
Cidex Plus USA Liquid Gluteraldehyde K923744
5) Complete the following process after sterilization.

6) Check the biopsy guide adaptor whether it has a crack, division, or any other damage
on it. If there is some damage, stop to use and contact to Medison service agency or its
authorized local service agency.

3.4.3 Surface of system
Follow as below..
Gloves and safety mask should be worn during cleaning and sterilizing
WARNING
the surface of system.
CAUTION Use only the solution recommended by Medison.
3.4.3.1 Cleaning
1) Turn the system off and then remove the plug from the power source.
2) Use a soft cloth lightly moistened with a mild soap or detergent solution to clean the
system surface.
3.4.3.2 Sterilization
3) Use a disinfecting solution with suitable concentration recommended by user guide.
Medison recommend the solution approved by FDA 510(k) in U.S.A.
4) Check the using time and the concentration of the solution as following the caution on
the label.
5) Dry it with a soft sterile cloth.

Mysono 201 Section 1-4. Installation
4.Installation of Mysono201
4.1 Connecting and removing the probe
The system has only one probe connector.
l How to connect the probe

1) Connect the probe to the probe connector located at the right side of the system.
2) Turn the locking lever on the probe connector clockwise to fix the probe.
l How to remove the probe

1) Turn the locking lever on the probe connector counter-clockwise to remove the probe.
2) Take off the probe from the system.
4.2 Connecting and removing the battery

It is optional part to supply the battery.
l How to connect the battery

1) Remove the cover of battery connector located at the bottom of system by pushing
forward outside.
2) Insert the battery to the battery connector by matching the bottom of the battery and
the system. After fixing the locat ion of the connector pin between the battery and
system, press it softly until complete the connection.
3) After complete connection, close the cover of battery connector of the system.
l How to remove the battery

1) Turn off the system power.
2) Remove the cover of battery connector located at the bottom of system by pressing
forward outside.
3) Take hold of the battery handle and lift it slightly. Then push it forward outside of the
system.
4) After remove the battery, close the cover of the system battery connector.
4.3 Charge and discharge of the battery

The battery has to charge before using.
l How to charge the battery

1) Insert the battery as how to connect the battery
2) Connect the system and AC adaptor supplied with the system. Refer to [appendix 0b.
connecting the peripheral device] in user manual.
3) The battery is charging during AC adaptor connecting.
It is possible to charge under the state both the system on and off.

Mysono 201 Section 1-4. Installation
In case of the system on, it takes about 5 hours to charge.

In case of the system off, it takes about 3 hours to charge.
If need a more information of the time for charge or discharge, refer to [Appendix C.
System specification] in the user manual.
Check the battery state by LED color on the system during charging.
- Without Battery: No Color
- Under charging: Orange
- Complete charging: Yellow
- Take off the adaptor: Red
Discharge the battery

When the battery is discharged (the system is working without AC adaptor), the system power
will be compulsorily turned off after a period of time (90 minutes) for safety and efficiency of
battery and user will hear the warning “beep” sound every 10 seconds.
4.4 Power ON / OFF

Hold the pressing the power switch located at the left side of the system for minimum 1sec.
whenever turns on/off the system. It is to prevent the system down and battery discharge.
l How to turn on the system

1) Hold the pressing the power switch for minimum 1sec. with connecting the AC adaptor
or inserting the charged battery.
2) Check the image display on the monitor.
l How to turn off the system

1) Hold the pressing the power switch for minimum 1sec.
2) Check the image disappears on the monitor and switch off.
4.5 Using AC adaptor

It takes about 5 hours to charge completely under connection of AC adaptor to the system.
Refer to [Appendix 0b. connecting the peripheral device] in user manual.

Mysono 201 Section 1-5. Function
5.Mysono201 Function
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2
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4
14
5
6 13
8 9
12
10 11
7
No. CONTROLS DESCRIPTION

1 Power switch Turns power on / off à about 1 sec.
Control the Brightness of LCD monitor.
2 Brightness Turn it to clockwise for brightness
Turn it to counter-clockwise for darkness
Use either Near dial or Far dial

3 Near / Far When control the Near gain, use Near dial
When control the Far gain, use Far dial
Control the image gain

4 Gain Turn it to clockwise for increasing the gain
Turn it to counter-clockwise for decreasing the gain
5 Set-up Change the mode into set-up
Delete the value on the image area such as Text, Body

6 Clear
Marker, Indicator, measured value, etc.
Display the status of Battery.
Disconnect the Battery: No Color
7 Battery LED Charging the battery: Orange
Full charge: Yellow
Remove the battery adapter: Red
8 GA Measure GA(Gestational Age)

No. CONTROLS DESCRIPTION
Mode for measuring of distance, volume, circumference,

9 Measure
etc.
10 Touch pad Touch pad
Control the image depth.
11 Depth Up key for shallow depth of the image
Down key for deep depth of the image
12 Printer Print the indicated image.
Save the present image on the monitor.
It is possible to check the saved image by using I-View.
13 Store
And can be back up by using smart media. (This
function will be added in the future.)
ON/OFF the image scan.
Cine function, the image saving, printing or measuring
14 Freeze
is available under freeze.
But the image saving is available only 2D mode.
Control knobs to select the image mode
2D/SYN: To 2D mode, press it one time. To Synthetic
mode, press it again under 2D mode.
M: Change 2D/M by pressing this button.
Display 2D image on the left side of the monitor and M
mode image on the right side of the monitor.
15 2D/SYN, M, DUAL
Change only M mode by pressing again this button
under 2D/M mode.
This button works as toggle button between 2D/M and
M mode under M mode.
Dual: Change Dual mode.
It works as alteration to left/right of activated Image.
16 Key board Use it when input the text or set the image.
Display most of information for using such like a
17 LCD monitor
ultrasound image, data, user menu, etc.

Mysono201 P/M Check List
Date: Distributor:
Hospital System Serial
Customer S/W Version

Address
Tel. no Warranty
Instructions :
This information is for warranty check. Please fill up all items.
Items Good Bad Remarks
Ι. Check the packing items (compare with packing list) ¨ ¨
ΙΙ. Condition of system housing ¨ ¨
ΙΙΙ. Probe condition ¨ ¨
A. Functional operation & test (system initialization state)

1. System works well when power on. ¨ ¨
2. Monitor TEST ¨ ¨
3. Key Board TEST ¨ ¨
B. Probe test (each probe)

1. Check the probe shape ¨ ¨
2. Knife TEST ¨ ¨
C. Operational Mode Tests

1. 2D Mode/SYN ¨ ¨
DUAL Mode ¨ ¨
M Mode ¨ ¨
2. Measurement TEST ¨ ¨
D . Electrical Test & Calibration
1. Power Supply ¨ ¨
2. System Calibration ¨ ¨
3. Power Cord/Plug and 110/220 switch ¨ ¨
E. Mechanical operation
1. Circuit boards, plugs, jacks, and connectors seated ¨ ¨
3. Seating & connection of cables & cords to peripherals ¨ ¨
F. Echo printer, External monitor, Multi-form camera, VCR ¨ ¨
When you finish filling all up, please send this sheet to Medison by fax or air mail.
Confirmation Signature
Service agency: Customer signature

Mysono201 Section 2-1. System Block Diagram.
1. System Block Diagram
B/W Printer
or VCR
LCD Monitor Inverter
or HMD
VGA Monitor
Key Board Touch Pad
Non-Interlaced B/W
Monitor
Digital Scan Converter DSC Video Jack

(DSC) (VJ)
Front End System Probe Connector

FE Adaptor Probe
(FE) (SPC)
Power Adaptor Power Smart Media
System Bolck Diagram

Mysono201 Section 2-2. Front End Board (F/E)
2. Front-End Board (F/E)

2.1 General Description
F/E board receives the echo signal of ultrasound and the signal clamps the high voltage to +/ -
0.6 V by Limiter then pass through TGC Amp. And then it reordering and its signal path is
reduced in half by OP Amp Adder that add the Symmetrical signal per scanline.
Then, to reduce the Aliasing, pass through the Low pass Filter and travels it to Beamforming IC
after converting it to A/D. Beamforming IC control the signals of 8 channel by Rx focusing, and
forward them to Mid Processor IC MGA015A on DSC.
Its main components are ;
- MOSFET Driver EL7222 x 16 ea
- PMOS TP2520 x 16 ea
- NMOS TN2524 x 16 ea
- Dual TGC Amp AD604 x 8 ea
- Cross Point Switch (16 x 8) MT8816 x 1 ea
- OP Amp AD812 x 8 ea
- Beamforming IC MCB014A x 2 ea
- XC95144 for Control x 1 ea
2.2 Block Diagram

U8 EXT_A[0-20]
GND
=
A/D 7
Probe
A/D 6 Connector
BFIC U8
A/D 5
A/D 4
Reordering
Adder TGC AMP
U8 EXT_B[0-20]
U7 EXT_A[0-20]
16x8 MUX Limiter Pulser

LPF 0~7 0 ~7 0 ~15
MT8816 1 EA 0 ~15 0 ~15
AD812 8 EA AD604 8 EA
=
A/D 3
A/D 2
BFIC U7
Clock : 25.2MHz
A/D 1
1 A/D 0
U7 EXT_B[0-20]
BF_OUT

2.3.1 CPLD Signal Definition
Name I/O Description
ADDR[0-5] Input HOST Address

/RPT Input Rate Pulse Train
/P_O_RESET Input Power On Reset by RC Time Constant

DATA[0-7] Input/Output HOST Data
DATA[0-15] for MCB014A(BFIC)
/PRB_INS Input Low : Probe Inserted

High : Probe Not Inserted
If Probe is inserted, then /PRB_INS=Low
FREEZE Input Freeze

If scanning is stopped, then FREEZE=high
/CPU_RD Input HOST I/O Read
MASTER_CK Input 25.2 MHz Clock (50.4MHz/2)
/CPU_WR Input HOST I/O Write

/ETRG Input Exciting Trigger
PRB_ID[0-4] Input Probe Identity Number
PROBE_ID[3] : default Low
PRB_ID[3] is not used.
TDI Input CPLD download TDI
TMS Input CPLD download TMS

TCK Input CPLD download TCK
TDO Output CPLD download TDO
HV_ON Output High : High Voltage On
Low : High Voltage Off
High Voltage On when probe connect to the
system
/AD_EN Output A/D Converter Enable

Default Low
INIT_MODE[2] Output BFIC Initial Mode
Real Mode : High
Download Mode : Low
/TX_MASK Output Tx Fire Disable
Display Low under Probe Disconnection or
Freeze mode

/P_WR Output BFIC P Register Write Strobe

Use it when latch the Scanline on BFIC
/BFIC_CS[0-1] Output BFIC Chip Select
/BFIC_CS[0] : A/D Channel 0-3
/BFIC_CS[1] : A/D Channel 4-7
/BFIC_RST Output BFIC Reset
/DATA_RD Output Host Data Read
/DATA_WR Output Host Data Write

/DATA_EN Output Host Data Enable
BFIC_ADDR[0-2] Output BFIC Address

2.3.2 Connector signals between DSC and FE

FE_CTRL_CLK Input Front End Control Clock
MT8816 Control Clock 16 ea
HVSW Clock 24 ea
/FE_CTRL_LE Input HVSW Latch Enable

FE_CTRL_RST Input MT8816 Reset
FE_CTRL_ADDR[0-5] Input MT8816 Address 0-15
FE_CTRL_DATA[0-7] Input MT8816 Control

AY[0-2]=DATA[0-2]
CPSW_DATA,CS = DATA[3]
HVSW Control
/HVSW_DATA[0-3]=DATA[4-7]
SCANLINE[0-7] Input Scanline 0-255
SYNTHETIC Input Low : Normal Tx
High : Synthetic Tx
CTRL_RESERVED Input Reserved / Default Low
FREEZE Input High : Freeze
Low : Real
25.2MHZ Input Master Clock 25.2MHZ
/EX_TRG Input Exciting Trigger
/B_EOF Output Beamforming Data Enable

Use it on MPIC MGA015 of DSC
/OF Input One Frame
/RP Input Rate Pulse

TGC_D[0-7] Input TGC Data
T_SBCLK Output Battery Clock
T_SBDATA Output Battery Data

PRINT_REMOTE Input Echo Printer Remote
B_FREEZE_REMOTE Output Freeze/Remote
The switch on the VET probe is using for toggle.
Using for Freeze, press it short.
Using for Store, press it long (over 3secs.)
FP[0-2] Input Focal Point / FP[2] = Default Low
CLK_120KHZ Input Power Clock 120KHZ

CLK_240KHZ Input Power Clock 240KHZ

VP5D Output +5V
VP3.3D Output +3.3V
VP12A Output +12V

VP5A Output +5V
VN5A Output -5V
/CPU_WR Input Host Write
/CPU_RD Input Host Read

EXT_B[0-16] Output Beamforming Data
LCDVR_A Output LCD Brightness Knob
LCDVR_B Output LCD Brightness Knob

GAIN_A Output GAIN Knob
GAIN_B Output GAIN Knob
NEAR_A Output NEAR Knob

NEAR_B Output NEAR Knob
FAR_A Output FAR Knob
FAR_B Output FAR Knob
2.3.3 Connector signals between Power and FE
PRINT_REMOTE Output Echo Printer Remote
CLK_120KHZ Output Power Clock 120KHZ

CLK_240KHZ Output Power Clock 240KHZ
High : High Voltage On
HV_ON Output
Low : High Voltage Off
T_SBCLK Input Battery Clock

Input/Outp
T_SBDATA Battery Data
ut
VP5D Input +5V

VP3.3D Input +3.3V
VP12A Input +12V
VP5A Input +5V

VN5A Input -5V
HVP Input +80V
HVN Input -80V

2.3.4 Connector signals between FE Adapter and FE
PLS_OUT[0-15] Input/Outp Ultrasound Echo

ut
+80VA Output +80V
-80VA Output -80V
+5VA Output +5V

/HVSW_DATA[0-3] Output High Voltage Control Data
HVSW_CLK Output High Voltage Control Clock
3.15MHz Clock 24 ea
/HVSW_LE Output High Voltage Control Latch Enable
PRB_ID[0-4] Input Probe ID

FREEZE_REMOTE Input Freeze Remote
Short Click : Freeze
Long Click : Store
2.3.5 Connector signals between FE Adapter and SPC(System Probe Connector)
PLS_OUT[0-15] Input/Outp Ultrasound Echo

ut
+80VA Output +80V
-80VA Output -80V
+5VA Output +5V

/HVSW_DATA[0-3] Output High Voltage Control Data
HVSW_CLK Output High Voltage Control Clock
3.15MHz Clock 24 ea
/HVSW_LE Output High Voltage Control Latch Enable
PRB_ID[0-4] Input Probe ID

FREEZE_REMOTE Input Freeze Remote
Short Click : Freeze
Long Click : Store

2.3.6 Connector signals between SPC(System Probe Connector) and Probe
1 2 3 4 5 6
A ECHO 0 GND ECHO 1 GND ECHO 2 GND

B GND ECHO 3 GND ECHO 4 GND ECHO 5
C ECHO 6 GND ECHO 7 GND ECHO 8 GND
D GND ECHO 9 GND ECHO 10 GND ECHO 11
E ECHO 12 GND ECHO 13 GND ECHO 14 ECHO 15
F N.C. N.C. GND + 80 V + 80 V GND
G GND - 80 V - 80 V GND +5V GND
H /DAT0 0 /DATA 1 GND /DATA 2 /DATA 3 GND
J Remote HVSW_CLK /HVSW_LE N.C. N.C. PRB_ID 0
K PRB_ID 1 PRB_ID 2 GND PRB_ID 3 PRB_ID 4 /PRB_INS

2.4 Scanline Definition

2.4.1 Normal Mode
SL 10
SL 11
SL 12
SL 13
SL 14
SL 15
SL 16
SL 17
SL 18
SL 19
SL 20
SL 21
SL 22
SL 23
SL 24
SL 25
SL 26
SL 27
SL 28
SL 29
SL 30
SL 31
SL 32
SL 33
SL 34
SL 35
SL 36
SL 37
SL 0
SL 1
SL 2
SL 3
SL 4
SL 5
SL 6
SL 7
SL 8
SL 9
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
SL 16
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
Scanline 16
Tx 7 T x 6 T x 5 T x 4 T x 3 T x 2 T x 1 T x 0 T x 0 T x 1 T x 2 T x 3 T x 4 T x 5 T x 6 T x 7
Element 1 ~ 16
Rx 7 Rx 6 R x 5 Rx 4 R X 3 Rx 2 Rx 1 Rx 0 Rx 0 R x 1 Rx 2 Rx 3 Rx 4 R x 5 Rx 6 Rx 7
SL 17
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
Scanline 17
T x 7 T x 6 T x 5 T x 4 T x 3 T x 2 T x 1 T x 0 T x 1 T x 2 T x 3 T x 4 T x 5 T x 6 T x 7 Tx 8
Element 2 ~ 17
Rx 7 R x 6 Rx 5 R X 4 Rx 3 Rx 2 Rx 1 Rx 0 R x 1 Rx 2 Rx 3 Rx 4 R x 5 Rx 6 Rx 7 x
SL 18
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
Scanline 18
T x 7 Tx 6 Tx 5 Tx 4 Tx 3 Tx 2 Tx 1 Tx 0 Tx 0 Tx 1 Tx 2 T x 3 Tx 4 Tx 5 Tx 6 Tx 7
Element 2 ~ 17
Rx 7 R x 6 Rx 5 Rx 4 RX 3 Rx 2 Rx 1 Rx 0 R x 0 Rx 1 Rx 2 Rx 3 R x 4 Rx 5 Rx 6 Rx 7
SL 19
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 18 19
Scanline 19
Tx 7 Tx 6 Tx 5 Tx 4 Tx 3 Tx 2 Tx 1 Tx 0 Tx 1 Tx 2 T x 3 Tx 4 Tx 5 Tx 6 Tx 7 Tx 8
Element 3 ~ 18
R x 7 Rx 6 Rx 5 RX 4 Rx 3 Rx 2 Rx 1 R x 0 Rx 1 Rx 2 Rx 3 R x 4 Rx 5 Rx 6 Rx 7 x

2.4.2 Synthetic Mode
Synthetic Scanline 32
SL 32
Element 1 ~ 32
1 2 3 4 5 6 7 8 9 10 11~14 15 16 17 18 19~22 23 24 25 26 27 28 29 30 31 32 33 34
t x 7 t x 6 t x 5 ~ t2x 1 t x 0 t x 0 t x 1 t x 2 ~ 5t x 6 t x 7
r x 1 5r x 1 4
r x 1 3r x 1 2r x 1 1r x 1 0r x 9 r x 8 r x 8 r x 9 r x 1 0r x 1 1
r x 1 2r x 1 3r x 1 4r x 1 5
Synthetic Scanline 33
SL 33
Element 2 ~ 33
1 2 3 4 5 6 7 8 9 10 11 12-15 16 17 18 19~22 23 24 25 26 27 28 29 30 31 32 33 34
t x 7 t x 6 t x 5 - 2t x 1 t x 0 t x 1 t x 2 ~ 5t x 6 t x 7 tx 8
rx 15
r x 1 4r x 1 3r x 1 2r x 1 1r x 1 0r x 9 r x 8 r x 8 r x 9 r x 1 0r x 1 1
r x 1 2r x 1 3r x 1 4r x 1 5 x
Synthetic Mode :
Scanline 중심에 있는 Element 16 개를 Firing 하고 수 usec 이후 HVSW를
다시 Control하여 Firing 되지않은 주변의 Element 16개에서 Echo
Signal을 수신한다. 그리고 Echo Processor IC는 Normal Mode의 신호와
Synthetic Mode의 신호를 합친다.

2.5 Pulser vs Elements
TX_OUT_P[7] Pulser 15 PLS_OUT[15] ELEMENT 16, 32, 48, 64, 80, 96
TX_OUT_P[5] Pulser 13 PLS_OUT[13 ELEMENT 14, 30, 46, 62, 78, 94
2nd BFIC
Clock : 25.2MHz TX_OUT_P[4] Pulser 12 PLS_OUT[12] ELEMENT 13, 29, 45, 61, 77, 93
TX_OUT_P[0-7],
TX_OUT_N[0-7] TX_OUT_P[3] Pulser 11 PLS_OUT[11] ELEMENT 12, 28, 44, 60, 76, 92
are Active Low

1
1st BFIC
Clock : 25.2MHz TX_OUT_P[4] Pulser 4 PLS_OUT[4] ELEMENT 5, 21, 37, 53, 69, 85
TX_OUT_P[0-7],
TX_OUT_N[0-7] TX_OUT_P[3] Pulser 3 PLS_OUT[3] ELEMENT 4, 20, 36, 52, 68, 84
are Active Low

1

2.6 Detail Description

2.6.1 TGC Amp
The main chip of TGC Amp is AD604. Two Variable Gain Amp is located inside of the chip and
they are composed of 2 channels TGC Amp. The ultrasound signal that was reflected or
propagated from a medium can compensate by Variable Gain as time, that is to say it is a
proceeded distance, at this stage.
Gain Range : 0 ~ 48 dB (Preamp Gain = + 14 dB)
Input resistance : 300 kohm
Variable Gain Scaling : 20 dB/V
Gain [dB] = 20[dB/V] * TGC_Curve[v] - 5 [dB]
Output Impedance : 2 ohm
Load resistance > 500 ohm
Reference Voltage : 2.5V (Gain Scaling 20 dB/V)
2.6.2 Reordering
One MT8816 generate 16 ×8 MUX.
It is controlled by Scan Lind regardless TX Focal Point or Probe type.
[Normal Tx Mode]
The ultrasound signal symmetrically controls the reordering around Center Element. But at
the point of BFIC Channel, the Center of signal could be moved as Scanline because it has
sixteen MUX (6x1) as High Voltage Switching IC in the Probe Box.
Thus it is possible to control BFIC RX Control date size by reordering this signal.
Delay
Delay
Reordering
0 16 Channel 0 8
Delay
0 16
Delay
0 16

그림 1
[Synthetic Tx mode]
To achieve 1 scanline image, the element that used Tx or Rx is the same in Normal Tx mode.
Under Synthetic Tx mode, it is the same as Tx element but RX receive the first signal from the
center 16 elements and receive again the second signal from the near side 16 elements. As the
result, RX generate 32 channel image in MGA015A Mid Processor ASIC by adding two scanline
Beamforming data in RF domain
2.6.3 LPF
Low-Pass Filter located the edge of the Analog Receiver Channel is worked both noise
suppression as stop band and Anti-aliasing Filter as reduce aliasing caused by high frequency
probe such as 7.5MHz Probe
VOFFSE
Adder
Output
[Figure 5. Low-Pass Filter]
A/D clock is 25.2 MHz and maximum center frequency of probe is 7.5MHz.
And 3dB cut off frequency for Trade-off is 10MHz.
LPF works as Bessel filter and constructs the circuit by 4th step for reducing a ringing.
2.6.4 Beamforming IC MCB014A

For Reordering, it is necessary 8 Channel A/D Converters. BFIC has 4 Channels. To make a
Beamforming, two BFICs are required.
Tow’s Compliment is output and Bit 1 to 16 is used at the last output.
Both of main clock and the last output data rate are 25.2Mhz. It is possible to control Tx Delay
by twice frequency and to control Tx Period under 25.2MHz, 40nsec.
To prepare the next calculation of scanline during Beamforming, have to provide the next
scanline between /RPT rising point and /ETRG rising point.

2.7 PCB BOARD LAY OUT

2.7.1 F/E TOP SIDE
1.7 PCB BOARD LAY OUT

1.7.1 F/E TOP SIDE
1.8.2
F/E

2.7.2 F/E BOTTOM SIDE

2.8 Timing Chart

2.8.1 Normal TX Focusing
Normal TX Focusing
/ETRG
10 usec
SL
N N+1 N N+1 N+2 N+1
HVSW
ROM
Conrol
N= Current scanline
N+1 = Next Scanline
If Next scanline is M Mode Line,

then N+1 means M mode scanline.
2.8.2 Synthetic Tx Focusing
Synthetic TX Focusing
/ETRG
normal synthetic
10 usec
SL
n n n n n+1 n
10 usec
BF_SYNTH
low high low low low high
ETIC
HVSW
ROM
Conrol

2.8.3 Control Timing
FE_CTRL_ADDR[0-4] 0 1 ... 14 15 16 ... 23
FE_CTRL_DATA[0-7] 0 1 ... 14 15 16 ... 23
FE_CTRL_CLK 24 EA ...
3.15MHz
/FE_CTRL_LE
317 nsec
CPSW_AX[0-3]
CPSW_AY[0-2]
0 1 ... 14 15 16 ... 23
CPSW_DATA
/HVSW_DATA[0-3]
CPSW_STRB 16 EA ...
FE_CTRL_CLK 24 EA ...
/HVSW_LE

2.9 Wave Form

/EOF Master_ck (U8,182) = 29ns /ETRG /EOF (U8,182) = 5.26us
/ETRG (U25,2) , Master_ck (U25,19) = 24.5ns /OF(TP10) => CH1,/RPT(TP16) => CH2
/ETRG(TP17) => CH3(C2-5/60BD)
/OF(TP10) => CH1,/RPT(TP16) => CH2 /OF(TP10) => CH1,/RPT(TP16) => CH2
/ETRG(TP17) => CH3 /ETRG(TP17) => CH3,/RPT Event 143 = 2.4us
/RPT Event 1 /RPT Blank = 14.8us
/RPT /ETRG rising gap = 225us
/OF(TP10) => CH1,/RPT(TP16) => CH2 /RPT(TP16)=>TP1,/P_WR(U8(MCB014)PIN 138)

/ETRG(TP17) => CH3 /P_WR Blank = 800ns
/RPT Event72 /RPT /ETRG rising gap = 10.1us

/RPT Scan line(MCB014 = PIN 137) Event2 /RPT Scanline(MCB014 = PIN 137) / P_WR
when /P_WR rising, MCBO14 latch it as next
scanline hold
/RPT B_FREEZE_REMOTE /RPT B_HV_ON (R171)

In VET probe, it turns Low when press the switch. Connecting with Probe, High = 5.05V
Connecting without Probe, Low = 360mV
/RPT B_PRBINS (U28,18) /RPT CPSW_STRB,CPSW_AX0 (U4,5)

Connecting with Probe, Low = 0V
Connecting without Probe, Low = 3.3V
/RPT CPSW_STRB,CPSW_AX0 = 325ns /RPT CPSW_STRB,CPSW_AX1 (U4,24)

/RPT CPSW_STRB,CPSW_AX2 (U4,25) /RPT CPSW_STRB,CPSW_AX3 (U4,4)
/RPT CPSW_STRB,CPSW_AY0 (U4,26) /RPT CPSW_STRB,CPSW_AY1 (U4,27)
/RPT CPSW_STRB,CPSW_AY2 (U4,2) /RPT CPSW_STRB,CPSW_DATA (U4,42)

= 4.74us
/RPT CPSW_STRB,CPSW_RST(U4,3) = /RPT HVSW_CLK(R170) = 7.52us

300ns

/RPT HVSW_CLK(R170) = 7.52us /RPT HVSW_CLK /HVSW_DATA0 (R188)

= 320ns
/RPT HVSW_CLK /HVSW_DATA1 (R189 /RPT HVSW_CLK /HVSW_DATA2(R190)
/RPT HVSW_CLK /HVSW_DATA3(R191) /RPT HVSW_CLK /HVSW_LE(R178)
/RPT SPSW_STRB(U4 PIN20) = 7.5us, /RPT TGC_CURVE(R147) = 3.02V

24ea clock

/RPT SPSW_STRB(U4 PIN20) = 7.5us, /RPT SPSW_STRB(U4 PIN20) = 7.5us,

24 ea clock 24ea clock
/RPT TGC_REF (TP14) = 2.504V /RPT VREF_0.1 (R141) = 143Mv
/ETRG /TX_OUT_P [0], C11 = ±80V (∆ = /ETRG /TX_OUT_P [0]

162V) C3 = 5V -> 12V -> 80V (∆ = 11V)
/ETRG /TX_OUT_N [0] /E/TRG = CH3

C4 = 5V -> 12 -> -80V (∆ = 12V) /TX_OUT_P [0] (U1, 4) = CH2
/TX_OUT_N [0] (U1, 2) = CH1

/ETRG /TX_OUT_P [0], EL7222, pin_5 /ETRG /TX_OUT_P [0], TP1 = (∆ =

= 5V 142V)
-> 12V
/ETRG /TX_OUT_N [0], TP3(±9) /RPT /INIT_MODE [2] = High
/OF /RPT, SYATHETIC (U8, PIN129) /RPT, BFIC_ADDR [0,1,2] = Low

Normal = low
Synthetic = high
/RPT /BFIC_CS [0] = High 3.27V /RPT /BFIC_RST = High 3.27V

/RPT /BFIC_CS [1] = High 3.27V

/RPT /BFIC_RST, INIT_MODE [2] /RPT /FP [0-2] =

Booting, Low -> High -> Low Power ON, High = 3.27V
Low = 30mV
/RPT /DATA_RD = High 2.25V /RPT /DATA_WR = High 2.25V
/RPT /FP [0-2] = /RPT /INIT_MODE [2] =

Change from 0 to 3 under Focal point Booting 시 Low -> High -> Low
moving
/RPT, TP9 = LPF output 30Mv /RPT, TP7 = Adder output 30mV

/RPT /TX_MASK = Real = High /RPT (U3, PIN1), C19 = 2.61V

Freeze = Low
/RPT (U3, PIN22), TP5 = 2.59V /RPT (U3, PIN23), R20 = 2.53V
/RPT (U3, PIN24), R19 = TGC – CURVE /RPT (U3, PIN3), C21 = 2.61V
/RPT (U3, PIN4), C21 = 226mV /RPT (U6, PIN6) AD9283 /A2N 950Mv
Service Manual Published by SERTECH

Function generator Function generator

voltage = 1.17 V frequency = 3.5 M voltage = 1.17 V frequency = 3.5 M
/ETRG /TX_OUT_N [0], TP3 /ETRG /TX_OUT_N [0], TP3

/RPT, TP7 /RPT, TP9

/RPT (U3, PIN1), C19 /RPT (U3, PIN1), C19


/RPT (U3, PIN2), C21 /RPT (U3, PIN22), TP5

/RPT (U3, PIN23), R20 /RPT (U3, PIN24), R19 = TGC – CURVE

Voltage = 1.17 V frequency = 3.5 M voltage = 1.17 V frequency = 3.5 M
/RPT (U3, PIN4), C21 /RPT (U3, PIN4), C21
Function generator
voltage = 1.17 V frequency = 3.5 M
/RPT (U6, PIN6) AD9283 /A2N

Mysono201 Section 2-3. DSC board
3.DSC Board
3.1. Description Overall
- B/F data pass to FIFO through MID Processor and the data is sampling by ADCLK on
Clock Generator (MGA003) and then transfer to Frame Average (MGA001).
- MGA003 generates the Clock by integrating the standard signal (/OF, /RP, /EADC) come
form RTC Controller (FPGA0), Sampling Clock information as Scan Line inside SCG• DCG
ROM and Display Clock information.
- MGA001 works as Frame Average Function by using /OF, /RP, /EADC come from RTC
Controller (FPGA0) under controlling Frame GDC, and then transfer the data to Frame
Memory and Cine Memory.
- In Real mode, the data come from MGA001A is stored both Frame Memory and Cine
Memory simultaneously. But the data come from Frame Memory transfer to CRD
(MGA005).
- In Cine mode, the data come from MGA001A is not transfer either Frame Memory or
Cine Memory and the data stored in Cine Memory pass to CRD (MGA005) and display on
the screen.
- The Port out Command in CPU of Cine Controller (FPGA1) control the Cine Memory.
- The data come from Frame Memory (or Cine memory) is variable DCG rate each H-Sync.
CRD (MGA005) interpolate it by 12.6MHz unit in 1D (Horizontal Interpolation) and make
a data as equal then pass it to Post Memory for displaying.
- Port out command of CPU input into Overlay GDC. Overlay GDC generates Overlay data
and then pass them to Post memory. And generate the general Control signals that are
necessary in Overlay.
- Post Memory integrates the data come from CRD and Overlay GDC and makes the image
adapted on 640x480. Then pass it to Video Buffer (AL422) and display it on the LCD (or
Monitor).
- Video Buffer (AL422) receive the control signals come from Video Output Controller to
adjust Refresh Rate of LCD (or Monitor) and output the Image data as 25.2MHz and then
transfer them to DAC (TDA8775).

3.2. Block Diagram

A[0-15] Input HOST Address
AD[0-15] HOST DATA

RST 8085 CPU RESET
ALE OUTPUT DATA ADDRES ENABLE
/IO_W OUTPUT IO CHIP WRITE ENABLE
/RD IO READ
IO_D[0-7] UPD72020 의 DATA BUS
/OL_GDC_RAS OVERLAY GDC RAS

OL_GDC_BLK OVERLAY GDC BLK
/OL_GDC_DBIN OVERLAY GDC DBIN

/OL_GDC_RD OVERLAY GDC READ
/OL_GDC_WR OVERLAY GDC WRITE
CLK3.15 POWER CLOCK 3.15Mz

FE_CTRL_CLK Input Front End Control Clock
MT8816 Control Clock 16 개
HVSW Clock 24 ea
/FE_CTRL_LE Input HVSW Latch Enable

FE_CTRL_RST Input MT8816 Reset
FE_CTRL_ADDR[0-5] Input MT8816 Address 0-15
FE_CTRL_DATA[0-7] Input MT8816 Control

AY[0-2]=DATA[0-2]
CPSW_DATA,CS = DATA[3]
HVSW Control
/HVSW_DATA[0-3]=DATA[4-7]
SCANLINE[0-7] Input Scanline 0-255
SYNTHETIC Input Low : Normal Tx
High : Synthetic Tx
CTRL_RESERVED Input Reserved
Default Low
FREEZE Input High : Freeze

Low : Real
25.2MHZ Input Master Clock 25.2MHZ
/EX_TRG Input Exciting Trigger

/B_EOF Output Beamforming Data Enable
Use it on MPIC MGA015 of DSC

/OF Input One Frame

/RP Input Rate Pulse
TGC_D[0-7] Input TGC Data

T_SBCLK Output Battery Clock
T_SBDATA Output Battery Data
/CPU_RD Input Host Read
EXT_B[0-16] Output Beamforming Data

LCDVR_A Output LCD Brightness Knob
LCDVR_B Output LCD Brightness Knob
GAIN_A7 Output GAIN Knob

GAIN_B Output GAIN Knob
NEAR_A Output NEAR Knob
NEAR_B Output NEAR Knob

FAR_A Output FAR Knob
PRINT_REMOTE Input Echo Printer Remote
B_FREEZE_REMOTE Output Freeze/Remote

The switch on the probe is using for
toggle.
Using for Freeze, press it short.
Using for Store, press it long (over
3secs.)
FP[0-2] Input Focal Point

FP[2] = Default Low
l NOTE : Refer to Article 5. in chapter 2. [ASIC PIN definition]


3.4.1 B/W Data Receiving & FM Storing Part
MID PROCESSOR
FRAME MEMORY
(ECHO) BW_DATA
FIFO
MGA015
8 8
574 273
/MOD_BW_CLK_O /AD_LATCH_CLR_OUT
(FPGA1 - bw_clk_o from MGA015) (FPGA0 - /AD_LATCH_CLR_IN(MGA003)
& B_BW_RDY(MGA015))
/RP
/BW_OUT_EN
/FIFO_WR /ACK
Pattern (FPGA0 - not /AD_LATCH_CLR_OUT)
BW_TST (FPGA0 -
Generator REQ(MGA001) B_EMPTY_FLAG(FIFO)) ADC
(FPGA0) 8
8
(Toggle)
574
/BW_TST_EN
/AD_LATCH_CLK
(FPGA0 - EADC & ADCLK from MGA003)
RAM_D
FRAME
MEMORY 8
/BADDR_EN
(VRAM) (FPGA1 -
B_DSP, B_GDC, ADDR_SEL, B_MENA, FRAME MEMORY
B_REAL from MGA001) CONTROLLER
R_A RAM_A 245 RAM_AD (MGA001)
8 8 8
IO_D
8
574
/P77_WR
/MADDR_EN (FPGA1 - IO portout IOWR(77H)) M_CLK6.3M
(FPGA1 - (two inverting CLK6.3M(MGA003))
B_DSP, B_GDC, ADDR_SEL, B_MENA
from MGA001) MASTER CLOCK(50.4M)
B/W data receiving FRAME

GDC GDC_D[0-7]
M_CLK6.3M
& FM storing part
GDC_AD[0-7]
(two inverting CLK6.3M(MGA003)) 25
GDC_A[8-16]
3.4.1.1 Mid-Processor (MGA015A)

l Mid-processor plays as converter RF data come from F/E board into BW data that can
use in DSC pass through several digital signal processing.
l MGA015A ASIC clock divides system master clock 50.4MHz into 25.2MHz on MGA003
and pass through it to Clock buffer. As the result, it uses 25.2MHz.
l The data of Internal MGA015A is controlled by CPU Portout downloading. Host
controller (FPGA1– host data, host address, host_wr, host_rd) works as the download
interface.
l RF data, the first TX/RX result come from B/F, is stored SRAM in MGA015A. But
external SRAM is necessary to display BW data that generated by summing up the
second R/F data of TX/RX result.
l MGA015A makes /BW_CLK_0 that 74HCT574 located on the back stage is to latch the
BW data. But because /BW_CLK_0 do not make any clock during /RP blank period,
/RP the last data remain in 74HCT574. Thus the first sampling data in /RP enable
period is possible to be the last data during hole /RP period. As the result, white spot
symptom appears at near part on the image. To remove this symptom, use
/MOD_BW_CLK_0 include dummy clock. It clears 74HCT574 data within RP blank
period.

External
RAM
Synthetic
From DTGC Decimation 1/N DC Cancel Quadrature
Aperture
BF FIR Filter Decimation FIR Filter Mixer
Control
Dynamic
FIR Filter
M/N Decimation Pixel Decimation Log Envelope Moving

to nearest FIR Filter Compressio Detection Average
n
M/N Decimation
To to nearest
Zone BHF BW Post Filter B/W
Blend NSF DSC
To
Color &
to Doppler
ATGC
BF
Figure 1. Mid-Processor (MGA015)

3.4.1.2 Pattern generator

l FPGA0 drives Pattern generator.
l Pattern generator is a block that makes a test pattern to check DSC function whether
it works well or not.
l According to test pattern on/off, change from /BW_OUT_EN to /BW_TST_EN.
l Test pattern on/off is set by CPU portout.
[Test pattern type and the bit value of 7BH port]
Bit7 : test pattern on/off Bit6: Row/Colume selection

Bit5 : m-mode test pattern on/off Bit4~Bit0: increment value
2sec
Blinking
White : 1sec
Black : 2sec
3.4.1.3 Before FM controller (MGA001)
l BW data sampling get according to /AD_LATCH_CLK.
l /AD_LATCH_CLK is a clock that generated by masking ADCLK come form MGA003
into /EADC.
l Master reset of 74HCT27 is achieved by /AD_LATCH_CLR_OUT . /AD_LATCH_CLR_IN
signal generated by MGA003 match the BW data sampling point as masking
/BW_RDY.
l Frame memory FIFO stores the BW data with scanline direction temporary and
support to write the data on the Frame memory. To match the timing point, FIFO
write clock uses an inverter type of /AD_LATCH_CLK.
l The clock that read Frame Memory FIFO receive the BW data using /EMPTY_FLAG.
/ACK is a clock to read Frame FIFO and receive BW data using REQ and
/EMPTY_FLAG.
l REQ represent whether MGA001 is ready to BW data process and /EMPTY_FLAG
check whether the FIFO is empty.

3.4.1.4 FM controller (MGA001)

l MGA001 for exclusive use of FMC design to generate several signals under ASIC
Technology.
l The related signals of Frame memory are DATA & Address Bus, Control signal such as
/RAS , /CAS, /OE, /WE, etc.
l Data Bus of Frame memory is connected with Frame Average Logic at chip inside and
average factor is 6ea. Mysono201 used 4ea among them.
l MGA001 use two cloc ks. Master clock is 50.4MHz and 6.3MHz clock same as Frame
GDC. In case of 6.3MHz clock, use 6.3MHz half clock of MGA003 with the result of
passing through inverter twice since clock slew rate is not fine.
l Frame GDC generate the standard signals such as FM_GDC_HS, FM_GDC_BLK,
/FM_GDC_RAS, /FM_GDC_DBIN and perform the factor data and functions. However,
for /FM_GDC_RAS signal, use /FM_GDC_RAS_LATCH signal with latching the rising
edge as 50.4MHz to match the necessary point at MGA001
l FMC is connected with address bus and data bus for Frame memory.
In M- mode, to store a designated scanline data in a designated FM address, the latch
that portout the address form CPU is connected with address bus.
l M mode CPU portout latch output and 245buffer output of FMC address bus are
working as either enabling or switching by BADDR_EN and /MADDR_EN that use
integrating the signals come from MGA001 such as /DSP, /GDC, /ADDR_SEL, /M_ENA,
/REAL according to mode status.

3.4.2 FRAME MEMORY & CINE MEMORY FLASH MEMORY PART
M_CLK6.3M
(two inverting CLK6.3M(MGA003))
FRAME
GDC
25 GDC_D[0-7]
GDC_AD[0-7]
GDC_A[8-16]
LS_OUT, RS_OUT S_OUT

8 8
RAM_D
FRAME
/BADDR_EN
8 MEMORY DLS_CLK, DRS_CLK
(FPGA1 - (VRAM) (FPGA1 - ULA_CLK(MGA003)) 573 273 FM_OUT
B_DSP, B_GDC, ADDR_SEL, B_MENA,
B_REAL from MGA001)
FRAME MEMORY RAM_AD 245 RAM_A R_A /LB_WIN, /RB_WIN 8
CONTROLLER (FPGA1 - /L_WIN, /R_WIN
8 8 8 (MGA003) & not cine_read_on) /LATCH_CLR
(MGA001) (MGA003)
/S_CLK
/R_RAS, /R_CAS, /LM_WE, /RM_WE (FPGA1 -
MASTER CLOCK(50.4M) IO_D (MGA001) ULA_CLK(MGA003) CLK50_4M 2
/FLS_CLK, /RS_CLK delay) CRD
8
(FPGA1) M_LATCH_CLR (MGA005)
M_CLK6.3M /P77_WR
(FPGA1 -
(two inverting CLK6.3M(MGA003)) (FPGA1 - IO portout IOWR(77H)) 574 /ADDREN (FPGA1 - when real_write, enable)
/MADDR_EN /LATCH_CLR, LS_CLK, RS_CLK(MGA
(FPGA1 - 003))
B_DSP, B_GDC, ADDR_SEL, B_MENA CLK12.6M
from MGA001) (MGA003)
245 CNA
8 8
/DATAEN (FPGA1 - when real_write, enable)
245 IMG_D
8 8 8
CINE LD_OUT
FLM_D 8
8 8 MEMORY
8
FIFO
FLASH MEMORY
8 573
FLM_CLE, FLM_ALE
/LFIFO_WR
/FLM_WE, /FLM_WP
(FPGA1 - B_CN_OE)
/FLM_SE, /FLM_RE
(FPGA1 - CPU PORTOUT) /LFIFO_RST
CINE DRAM (FPGA1 - FM_GDC_BLK(FMGDC))
CONTROLLER /LFIFO_RD
(FPGA1 - not LS_CLK(MGA003))
CINE MEMORY
& D_CINE_CLK
(DRAM) (FPGA1 - LS_CLK, CLK50.4M( ))
SMARTMEDIA /LFT_WIN
FLASH MEMORY (FPGA1 - cine_read_on)
CONTROLLER
/CN_RAS, /CN_CAS,
/CN_OE0, /CN_OE1,
/CN_WE0, /CN_WE1
MASTER CLK50.4M (FPGA1 - mode change as to CPU PORTOUT)
CLK25.2M (MCLK 2 div. in FPGA1)

3.4.2.1 Frame Memory (VRAM)
There is two Frame Memory type, RM and LM.
B – MODE B/M – MODE B/B - MODE M-Mode
LEFT Frame Memory B B LB Not used
RIGHT Frame Memory Not used M RB M
l Operation for writing on Frame memory is achieved by MGA001 control signal such as
/R_RAS, /R_CAS, /LM_WE, /RM_WE, etc.
l Operation for reading on Frame memory is recognized by Display clock at SAM. (cf.
VRAM = DRAM + FIFO) And latch it by 573 latch data.
3.4.2.2 Cine Memory (DRAM)
256
256
256 #0 #1 #2 #3 #16 #17 #18 #19
#4 #5 #6 #7 #20 #21 #22 #23
#8 #9 #10 #11 #24 #25 #26 #27
#12 #13 #14 #15 #28 #29 #30 #31
Cine Memory #0 Cine Memory #1
l Cine memory store total 32 frame and use for image store include Cine image.
l Cine memory controller (FPGA1) controls the cine memory.
l Under Real mode, Cine memory is stored with Frame memory at the same time using
the data come from FMC directly and control signal such as /R_RAS, /R_CAS,
/RM_WE, /LM_WE. But under Cine mode, data is output from Cine memory instead of
FM and connected with Cine memory FIFO of DRAN back stage to work as VRAM.
l Frame memory data path and Cine memory data path meet at Data bus, called
S_OUT.
And 573 latch is enable by toggle signal of /LFT_WIN, /LB_WIN (or /RB_WIN)
according to mode.

DRAM Memory(CINE Memory) Map
256 x 4
512 x 256
1 FRAME 2nd 3th 4th
1st
5th 6 7 8
512 x 4
9 10 11 12
13 14 15 16
DRAM(CINE MEMORY)
* mysono201 내부에는 2개의 DRAM이 있고 한개당 16개의

frame이 들어 갈 수 있다. 그러므로 CINE는 총 32장을 제공한다.
* CINE memory에 있는 image를 FLASH memory로 저장(store)하

는 방법은 두개의 ROW(256 bytes) 가 한조가 되어 한개의
page(512 bytes)에 저장 된다. 이렇게 총 256개의 조가 저장되고
1개의 block이 16page이므로 총 16개의 block이 필요한 샘이다.
.
Figure 1. Cine Memory Map
3.4.2.3 Flash Memory
Flash memory is a NAND type and use a backup memory for image saving.
l It is controlled at Flash memory controller (FPGA 1) generated by CPU Portout.
l Flash memory control is achieved at Flash memory controller (FPGA1) under CPU
portout. But as CPU controls by the control signals such as FLM_CLE, FLM_ALE,
/FLM_WE, /FLM_RE that are selected through CPU portout, Flash memory
controller work as simple interface.

1 Frame in Flash
35
44
512 x 256
* 430 Dots x Scanline Image Area
02CH~02CH+430
* Max Scanline = 176
474
511
VRAM(=DRAM)
* VRAM에서 RAS Addr기준으로 43까지는 Image가 없는 영역이다.

이 것은 256 x 43 bytes 만큼이 비어 있다는 이야기이고,
이 것은 256 x 32 (512 x 16 = 1 block), 즉 총 16 block 중 1번째 block에는
image data가 존재하지 않는 것을 의미한다.
그러므로 첫번째 block은 다른 용도로 사용이 가능하며,
현재 이부분에는 ULA, System parameter, Report data, 화면 Display data 등
이 들어가 있다.
Figure 2. Fresh Memory Map

3.4.2.4 Memory Path by Mode
l Real Mode
FRAME
MEMORY
(VRAM)
Frame
Memory
Controller
(MGA001)
Cine
Memory
(DRAM)
Flash Cine Controller & Frash Controller

Memory (FPGA1)
Smartmedia
l Cine Mode
FRAME
MEMORY
(VRAM)
Frame
Memory
Controller
(MGA001)
Cine
Memory
(DRAM)

Memory (FPGA1)
Smartmedia

l Flash Memory Save
FRAME
MEMORY
(VRAM)
Frame
Memory
Controller
(MGA001)
Cine
Memory
(DRAM)
During saving
After saving
Memory (FPGA1)
Smartmedia
3.4.2.5 Scanline Masking Window

l When change the Mode (BMàB or BBàB) or control the Gain, an unsuitable image
display on the monitor due to save unsuitable data out of image area since VRAM
address control unstable
l Display clock is a regular according to probe element.
It occurs as much as scanline.

Display clock is constant by probe element. That is to say, Display clock generates as much as
scanline. Thus, if count a number of scanline and use it for the Master reset of 74HCT27 on the
front stage of MGA005, the dummy scanline problem can be solved by pass through only the
data under image area. The other data out of image area is reset.
However, due to only the display clock is available that pass through the disable period of
/LATCH_CLR, make a new signal of /M_LATCH_CLR and use to /MR in 74HCT273.
/RP
FPGA
/EADC
/ADC_LATCH_
CLR OUT MGA003
/ETRG
014 DLY구간
/EOF
MGA014
MGA015
/BW_RDY
015 DLY구간

3.4.3 CRD, Graybar, Overlay Post Memory Part
GRAY BAR
GENERATOR CRD_O[4-7]
POST MEMORY
MGA003 CONTROLLER
(FPGA1)
CRD
POST_IN IO_D 245
CONTROLLER
(CPU portout)
8
/POST_EN
CRD (from CPUPORTOUT)
4
/LATCH_CLR
8 (MGA003)
/POST_WR
(/IOWR 5DH port)
CRD
FM_OUT CRD_O[0-7] 245 POST_IN VIDEO
(MGA005) POST_OUT BUFFER
8 8 8 (N/I)
8
CLK12.6M DULA_CLK_50
(MGA003) (FPGA1 -
ULA_CLK(MGA003) CLK50_4M 3
delay)
CLK3.15Mhz 1/2 CLK1.57Mhz

(MGA003) OVERLAY, MENU
Div. POST
(FPGA0 - OL_D(ovl mem) & CLK12.6M(MGA003)) MEMORY
OVERLAY GDC
/OL_GDC_RAS
OL_GDC_HS
OL_GDC_BLK IO_D POST_SWT
OL_AD[0-15] /OL_GDC_DBIN OVERLAY
8 VIDEO
CONTROLLER
(FPGA0) 5 BUFFER
POST_SWT_CLK
(FPGA1 - /IOWR 62H port) 574 (I)
OVERLAY GDC/MEM interface
/POST_SWT_OC
(FPGA1 - always enable)
OL_A
OL_D
8 16
/OL_CAS,
/OL_OE,
CRD, Graybar, Overlay

/OL_RAS,
/OL_GMC_WE
OVERLAY MEMORY
(FPGA0 -
Post Memory part

/OL_GDC_RAS, OL_GDC_HS, OL_GDC_
BLK,
/OL_GDC_DBIN(Overlay GDC)
& CLK12.6M(MGA003)
3.4.3.1 CRD
l Display the ultrasound image of the Convex probe on the monitor, system
recognize and read the data of Frame memory by Display clock that generated on
DCG (Display Clock Generator).
l One scanline will be interpolated to the Horizontal Sync (HSYNC) as fixed Scanline
number from the system and the frequency of interpolation DCG Clock will be
changed whenever the HSYNC is generated according to the Vertical Sync (VSYNC).
The image from Far-Field is interpolated as low frequency DCG Clock and there is a
possibility of mosaic problem on actual display.
l The CDR Logic uniformly converts the frequency of signal as 12.6 MHz that input to
the Monitor by 1D interpolation to horizontal axis for the data that is interpolated
from the Frame Memory as Monitor Dot Clock 12.6 MHz.
l MGA003 gives a parameter required for CRD, treat it as Dot Clock.
Input clock receive the data using DULA_CLK_50.
l The parameter that need to CRD get from MGA003, and process it by Dot clock.
But the received clock gets the data by using DULA_CLK_50 that delays the ULA
clock.

3.4.3.2 Graybar
l Graybar generate 4 Bit data come from MGA003.
l The signal related with Graybar is as follows;
- GRAY_OE : Controlled by MGA003 and manages the output point of Graybar data
- CRD_O[4-7] : Graybar data and share both MGA005 output bus and upper 4bit.
- /BMODE_EN : It is a Enable signal to control data output of MGA005
The basic schema of Graybar is as follows;
DCG CLK
SCAN
LINE
Sampling point
CRD point
3.4.3.3 Overlay
l Overlay data is generated by using overlay memory with controlling overlay GDC
by CPU. It goes to FPGA0 and processed to C, G, M, MENU then the final output is
overlay data and menu data. The data processing method is described as below
block diagram. GMC-D is the data that is processed by overlay GDC in overlay
memory and 12.6 MHz of dot_clock is used.
l This data is serially output from FPGA0 and combined with image in post memory.
frame 00 CD_LATCH
GMC_D _sel
01 GD_LATCH
10 MD_LATCH
11 MENU_LATCH
dot_clk
latch_en
Shift Right 16bit

OVL_EN
b_dot_clk CD_Q
CD_LATCH
b_dot_clk GD_LATCH GD_Q
b_dot_clk MD_LATCH MD_Q

OVL_EN
MENU
b_dot_clk MENU_LATCH MENU_Q

Mysono201 Medison Co.,Ltd.
3.4.3.4 Overlay Control Schema
640 COL:40*4
C plan
Men Men Men
Row:0 C G M u C G M u C G M u
480
Row:4 C G M
Men
C G M
Men
u u
1 plane consists of 640x480 pixel, and

overlay data is mapped by 1bit to 1 pixel.
1 picture=(40 COL x16)x480 Row
Row:8 C G M Men
u
C G M Men
u
C plan
A16=0
A17=0
G plan
A16=1
A17=0
OVL GDC
M plan
A16=0
A17=1
Row:4*480 C G M
Men
C G M
Men
C G M
Men
u u u
Menu
A16=1 <DRAM Memory allocation>

A17=1
When GDC write to DRAM:

Column:
GDC manage the external RAM address like above picture, DRAM_A0 <= OL_AD16
and each picture plane is overlaped like following . DRAM_A1 <= OL_AD17
Row:
Menu DRAM_A0 <= 0
M plan DRAM_A1 <= 0
G plan
C plan When GDC write to DRAM:
Column:
DRAM_A0,1: 0~3 in a GDC_RAS pulse
Row:
DRAM_A0 <= 0
DRAM_A1 <= 0

3.4.3.5 Post Memory

l Post memory consists of SRAM. It combines an image data and an overlay data into the
data displayed on the screen.
l It could change the display settings such as Gamma setting by control the data in Post
memory.
3.4.4 Noninterlace Output Display Path Port
/FB0_RE, /FB1_RE /EX_SYNC

(FPGA0 -/NI_HS, /NI_VS (FPGA0 -/NI_HS, /NI_VS
from CLK25.2M(MGA003)) from CLK25.2M(MGA003))
/FB0_WE,
/FB1_WE
(FPGA0 -
OL_GDC_BLK
& CLK12.6M VHS[1] NONINTERLACE B/W
(MGA003))
LCD_OUT DAC 5 order Filer OP-AMP DISPLAY
Video Buffer LCD_GRAY (SA5500)
(TDA8775)
(AL422)
8
Noninterlace 574
part
LCD_CLK
(FPGA0 - 25.2M /NI_BLANK
(FPGA0 inter-div) (FPGA0 -/NI_HS from
FB_WCK CLK25.2M(MGA003)) NON_INT_R
OP-AMP
(FPGA0 - EVEN
CLK12.6M 8
(MGA003)) ODD
NON_INT_G
FB_RCK OP-AMP
VGA DISPLAY
5 order Filer
(FPGA0 -
CLK25.2M DAC
(MGA003)) (TDA8775)
NON_INT_R
OP-AMP
LCD_R
6
574
LCD DISPLAY
6
Noninterlace output OP-AMP LCD_AD_DATA LCD_G
display path A/D 574

CONVERTER
OP-AMP 6 LCD_B
REF_0.8V
6
574
LCD_CLK_AD
(FPGA0 -MGA003 25.2Mhz)
3.4.4.1 Function
à Non-Interlaced B/W Monitor
(Recommended by Medison. Medison supplies this monitor.)
à VGA Monitor (We does not fixed specify model. You can use any type.)
à NTSC or PAL VHS Monitor (We does not fixed specify model. You can use any type.)
à NTSC or PAL VCR Record (Only Record. Does not support VCR Play Function.)
à B/W Echo Printer

3.4.4.2 VGA
Generally it has same specification as VGA Signal. It consists of R, G, B, HS, VS.
Pin array meets a standard and a detail wiring diagram is as follows;
Pin Name Dir Description

1 RED à Red Video (75 ohm, 0.7 V p-p)
2 GREEN à Green Video (75 ohm, 0.7 V p-p)
3 BLUE à Blue Video (75 ohm, 0.7 V p-p)
6 RGND à Red Ground
7 GGND à Green Ground
8 BGND à Blue Ground
13 HSYNC à Horizontal Sync (or Composite Sync)
14 VSYNC à Vertical Sync
1) Video signal converted D/A at TDA8775 (DAC) transfer output signal of VGA Monitor
through 6M LOW-PASS-FILTER.

2) Each value of R, G, B is amplified 1.5 times at EL4393 OP-AMP and is output.

3) HSYNC, VSYNC output the FPGA signal by Buffering through 74HCT245 without
amplification.
3.4.4.3 VHS
1) Video signal converted D/A at TDA8775 (DAC) transfer output signal of VHS Monitor
2) SYNC for INTERLACE used Programmable Sync Generator made by 74ACT715. As
booting INTERLACE SYNE, CPU (8085) select the data by downloading according to
VIDEO type whether it is NTSC or PAL. Please refer to below information regarding how
to control it and the Table for Down Load Data.
3) The Clock used this generator is different from VIDEO type.
In case of NTSC, it is used 24.5454M. Otherwise in case of PAL, it is used 29.5M.
They are selected by muxing of PAL_NTSC signal that produced on CPU

3.4.4.3.1 Control 74ACT715

1) DATA is located in “KERNEL.SRC” SOURCE.
2) SYNC could make by programming register number set in 74ACT715.
3) DOWN LOAD DATA table is as follows.
REGISTE DOWN LOAD DATA

R DESCRIPTION NTSC PAL
NUMBER
Status Register
00 (Hsync, Vsync Polarity = Active H, Non- 0580H 0580H
Interlace)
01 Horizontal Front Porch 0032H 00C0H
02 Horizontal Sync Pulse End (HFP+HSYNC WIDTH) 00A6H 0100H
03 Horizontal Blank Width 0118H 0260H
04 Horizontal Period 0618H 0760H
05 Vertical Front Porch 0009H 0047H
06 Vertical Sync Pulse End (VFP+VSYNC WIDTH) 0011H 004DH
07 Vertical Blank Width 002DH 0091H
08 Vertical Period (1frame) 020DH 0271H
09 Equalization Pulse End (HFP+Equalization Pulse 0060H 0074H
Width)
10 Serration Pulse End (HFP+HPER/2-HSERR+1) 02BEH 0350H
11 Equalization & Serration Pulse Vertical Start 0001H 0041H
12 Equalization & Serration Pulse Vertical End 0019H 0053H
13 Vertical Interrupt Activate Time 0029H 0029H
14 Vertical Interrupt Deactivate Time 020EH 0272H
15 HGATE Delay 0026H 002EH
16 HGATE Enable (HSYNC) 009AH 00BAH
17 VGATE Delay 0001H 0001H
18 VGATE Enable (VSYNC) 0015H 0015H
4) To make a stable initialization, do data Port Out on Register no.0 lately after Register
Port Out Sequence from 1 to 18.
5) How to control horizontally the position of screen (move it left and right) :
Register 4 controls the HSYNC cycle and register 3 controls the start point of Blank (that
is the begging point of image display). Change the value both of them as suitable and be
careful that “No.4 register – No.3 register” is always 500H. It is to maintain the Blank width
as 640 DOT constantly.
1) How to control vertically the position of screen (move it up and down):

Register 8 controls the VSYNC cycle and register 7 control the start point of Vertical
Blank. Change the value both of them as suitable and be careful that “No.8 register – No.7
register” is always 1E0H.

3.4.4.4 Non-Interlaced B/W (NI-B/W)
1) Video signal converted D/A at TDA8775 (DAC) transfer output signal of NI-B/W Monitor
2) What is NI-B/W?
Using the NON-INTERLACE type even though it has one signal line including both SYNC
and Signal such as general INTERLACE.
It combines the strength each one to make less image vibration than VHS or RF Monitor
and better contrast than VGA monitor.
3) Monitor is the same as SA5500 monitor. Only change the case for external usage.
4) Concept of SYNC Generation is described above figure.
VSYNC can detect during “HSYNC 3” term of the monitor for control the image position
to the center. T hat is to say, detect it faster than EVVS.

3.4.5 Interlace NTSC/PAL Display Part
/FB2_WE
(FPGA0 - OL_GDC_BLK&
CLK12.6M (MGA003))
5 order Filer OP-AMP
VHS[0]
IMG_GRAB_D INT_OUT
DAC
8 (TDA8775)
574
Video Buffer
interlace
NTSC/PAL
part PAL_NTSC
(AL422) (FPGA0 - CPU 2FH portout)
CLK24.545M
INT_CLK
FB_WCK MUX
(FPGA0 - ICSYNC, IBLANK
CLK12.6M (MGA003)) SYNC GENERATOR
CLK29.5M
(74ACT715)
IO_D
8
245 IMG_RAM_D
8 8
I_CLKX2
(INT_CLK 1/2 Div.)
IMG_GRAB_A
/IBLANK FRAME
(I_CLKX2 & not IBLANK)
GRABBER
FRAME
MEMORY
GRABBER
CPLD
IO_D
/IMG_GRAB_OE,
8 /IMG_GRAB_WE,
MASTER CLOCK
/IMG_GRAB_CS
(50.4MHz)
(CPU 99H, 9FH portout)
Interlace NTSC/PAL Display part

3.4.5.1 Frame Grabber CPLD & Memory
l Frame grabber continuously upgrades the data of 640X480 to FGM (Frame Grabber
Memory) in real mode. When input new frame grab, stop to upgrade and change the
mode to CPU access mode, then transfer the FGM data into Flash memory under
controlling by CPU.
Video
Buffer
(AL422)
Frame Grabber
Buffer
Memory
Frame Grabber CPLD
Flash
Flash
CPU Controller
Memory
(FPGA1)
Real Mode
[Figure. Real Mode] FIGURE) Real Mode
Video
Buffer
(AL422)
Buffer
Frame Grabber
Memory
Frame Grabber CPLD
Flash
Flash
CPU Controller
Memory
(FPGA1)
Frame Grab Mode
[Figure. Grab Mode]



3.5.1 DSC Top Side

3.5.2 DSC Bottom Side

3.6 Timing Chart

3.6.1 CRD Timing Chart
CRD Timing Diagram

80n
(12.6MHz)
40n
ULA_CLK
20n
DULA_CLK_20
30n
DULA_CLK_50
FM.OUT[0..7] 1 3 7 B
Y[0..7] 1 3 7 B
X[0..7] 1 3 7
WGT[0..3] 0 0 0 1 0 1 2 3 0
WGT[4..7] 1 2 4 4
OUT[0..7] 0 1 2 3 4 5 6 7

3.7 Wave Form
CH1: /BF_CLK25.2M CH1:/ATGC_PRF CH2: GC_CLK

Measure it by active probe. CH3:ATGC_D.
CH1:ATGC_PRF CH1:/BW_RDY CH2:AD_LATCH

CH2:TGC_CLK CH3: ATGC_D[0] CH3:BW_DATA.
CH1:/BW_RDY CH2:/AD_LATCH_CLK CH1:/BW_RAY CH2:/FIFO_WR

CH3:BW_DATA[0] CH3:BW_DATA[0]
CH1:/R_RAS CH2:R_CAS CH1:/CL_BLK CH2:DLS_CLK

CH3:/LM_WE CH4:RAM_D[0] CH3:LS_OUT

CH1:EVEN_VS CH2:DLS_CLK CH1:EVEN_VS CH2:DRS_CLK

CH3:LS_OUT CH3:RS_OUT
CH1: EVEN_VS CH2:S_CLK CH1:

CH3:S_OUT[0]
CH1:DUAL_CLK50 CH2:FM_OUT[0] CH1:N_VS CH2FB_WCK

CH3:POST_OUT
CH1:/CL_BLK CH2: LCD_CLK CH1:IBLANK CH2:/IMG_GRAB_WE

CH3:LCD_OUT[0] CH3:/MG_GRAB_D[0]

CH1:/OL_BLK CH2:FB_RCK CH1:/OL_BLK CH2:/CN_RAS

CH3:MG_GRAB_D[0] CH3:/CN_CAS
CH1: /OL_BLK CH2: /CN_CAS CH1:/OL_BLK CH2:/LFIFO_WR

CH3:/CN_OE0 CH4:MG_D[0] CH3:MG_D[0]
CH1:/OL_BLK CH2:DLS_CLK CH1:/OL_BLK CH2:CLK25.2M

CH3:LCD_OUT[0] CH3:INT_OUT[0]
CH1:/OL_BLK CH2:CLK25.2M CH1:/OL_BLK CH2:CLK25.2M

CH3:LCD_GRAY[0] CH3:LCD_CLK_AD CH4:LCD_AD_DATA[0]

CH1:O_EFLD CH2:IVSYNC CH1:O_EFLD CH2:IVSYNC

CH3:IHSYNC CH4:ICSYNC CH3:IHSYNC CH4:ICSYNC
CH1:O_EFLD CH2:IVSYNC
CH3:IHSYNC CH4:ICSYNC

Mysono201 Section 2-4. Power B/D
4. Power B/D
4.1 Specification
1) Abstract and application range
2) It is for Power supply device of Mysono201.
3) It supply DC±80V, 12V, ±5V, 3.3V, 6V to each parts of the system by converter DC16V
4) Model name : Mysono201 DC/DC

5) Input voltage - Adaptor : DC16V±1V
- Battery :12.7V ~ 10.5V
[Output voltage and current]

Before loading
Output
Ripple &
Voltage Normal MA DC16V+Battery
Noise
3.3V 2.0 3.35±0.1 3.35±0.1 3.35±0.1 70 ㎷↓
+ 5VA 1.5 5.0±0.15 5.0±0.15 5.0±0.15 100 ㎷↓
- 5V 0.5A - 5.0±0.15 - 5.0±0.15 - 5.0±0.15 100 ㎷↓
+ 12V 0.6A 12.0±0.3 12.0±0.3 12.0±0.3 200 ㎷↓
+ 80V 0.01A 80±3 80±3 80±3 500 ㎷↓
- 80V 0.01A - 80±3 - 80±3 - 80±3 550 ㎷↓
6V 0.8A 6.0±0.2 5.8±0.2 6.0±0.2 150 ㎷↓
Note) * Allowable Ripple Voltage is measured by connecting both 100uF electrolytic

capacitor and 0.1uF Ceramic capacitor at the edge of the probe.
* Using Scope is 100MHz Analog Scope.(50mV/0.5msec)
* Ripple Voltage = Measured value – Input Ripple Voltage
6) Alarm for Battery voltage discharge : 10.1±0.2V
7) Cutoff Voltage for Battery discharge : 9.2±0.2V
8) Battery charge Voltage : 12.45~12.75V

9) Cooling Type : Natural air cooling and forced circulation
10) Safety Standard : meet IEC60601-1.
11) Efficiency : Over 75 % (Input 16V , MAX load)
12) Using Environment
(1) Temperature range : 0℃ ~40℃
(2) Humidity range : 10% ~90%RH

13) Keeping Environment
(1) Temperature range : -15℃ ~70℃
(2) Humidity range : 10% ~95%RH

14) The others

5V 3.3V -5V 6V 12V 80V – 80V
OCP Protect Protect Protect Protect Protect
4A~6A 4A~6A
range Short Short Short Short Short
Setup/O Within Within Within Within Within Within Within
ff Time 100 ㎳ 50 ㎳ 100 ㎳ 100 ㎳ 100 ㎳ 1.5sec 1.5sec
Rising/F
Within Within Within Within Within Within Within
alling
30 ㎳ 30 ㎳ 100 ㎳ 100 ㎳ 100 ㎳ 1sec 1sec
Time
15) Battery
(1) Maker : Saehan Industries Inc.
(2) Model name : SH-202A
16) LED Operation

(1) When Battery discharge : RED
(2) When Battery charge : Orange
(3) When Battery charge finish : Yellow
(4) Using Adaptor (NO Battery) :No Color
17) Supply or Cutoff the power

Using Toggle function of Tack S/W (SW1)

4.2 Block Diagram


l Lin Sensing : supervise total current flow into DC/DC Power Board.
Battery Charge Control : The circuit for Battery charge
It stops to work by using SD-Charger or Vfbchg when Battery is discharged
l Charge Current Sensing : Control the charging current flow into Battery Maximum
charging current is limited 3A. When charging current flow under 300mA, charger stops
to charge because of recognizing as full charge. Charging current Sensing amplify the
voltage measured both end of R5 and then generate that voltage level at U-Com.
l Battery Voltage Sensing : Check Battery voltage.
When insert Battery to the system, recognize the condition whether Battery need to
charge or not.
When recognized Battery voltage is under 12V, start to charge until the voltage value
reach to 12.6V.
But after reaching 12.6V, it check Charge Current Sensing and then continuously charge
Battery until the Charging current reach to about 300mA.
l Control IC Max 1631 : DC/DV Control IC for output 3.3V, 5V by using BUCK S/W type.
IC works when high voltage input into Pin 23(ON/OFF DC/DC) of IC and starts to
switching.
By rectifying each value, it gains output as 3.3V, 5V. The constant voltage such as 3.3V,
5V drive the output voltage and then pass a feedback signal to FB3 (3Pin) and FB5 (12Pin).
Also – 5V and 6V are proportioned each coil rate and print out by winding.
l 80V,-80V,12V Output : This value can be gained by Flyback circuit consist of
U13(KA3843), Q17, and circumstance control circuit. At this time, the basic voltage is
12V and its value is output as ±87V proportioned to rate of coil. And also ±80V is output
through the constant voltage circuit when the output is ±87V.
l Comparator : Its reference value is about 2.6V under the standard setting output is ±
80V.
If the standard setting output reduce below 60V at any side of ±80V, the reference value
could be down. And the down voltage can sensing by U-Com and finally cutoff ±80V by
HV_SHDN on it.
l Color display of LED
1) Using only Adaptor : No Color.
2) Under Charging : Orange.
3) Under Discharging : Red.
4) Finishing the recharge: Yellow
l Working description of U-Com :
1) ON/ OFF (5Pin): Input terminal to control a hole Power Board by Toggle S/W
2) PWM (6Pin) : Control the Battery charging current by On/Off Duty
3) ON/ OFF FAN (8Pin) : Fan work by recognizing “H” signal from the output of 14Pin

when a temperature around LM35 increase over the standard temperature.

4) SD_Charger (10Pin) : When the charging circuit dose not work, control LED and
shutdown it by moving 1PIN of U3 to Low.
5) BAT_WARNING (11Pin) : Warning display when the Battery Voltage decrease
below 9.2±0.2V.
6) HV_SHDN (12Pin) : It could be off when the output voltage of ±80V is wrong.
7) Temp_Sensing (14Pin) : Fan work by recognizing 0.1mV/1℃ when a temperature
around LM35 increase over the standard temperature.

8) HV_Sensing (15Pin) : Checking the output of ±80V whether its value is good or
not.
9) Iin_Sensing (16Pin) : Checking and Limiting the inflow current from outside.
10) BAT_Voltage (17Pin) : Checking and Limiting the charging voltage of Battery
11) Ich_Sense (16Pin) : Checking and Limiting the charging current of Battery
12) Vad_EN : Check IN/OUT of adapter.
l Battery Alarm sound: When the battery voltage drops to 10.2V, Alarm sounds each
10sec to notice about it.
l Battery Cutoff Voltage: When Battery voltage drops to 9.2V, the system cut off it. As the
result, the battery voltage increases to about 10V.

Mysono201 Section 2-5. Probe
5.Probe
5.1.General Description
The probe element is the same as a standard probe of SA600, Sa9900 with 96 elements.
When apply the probe with 128 elements to the system, only use 96 elements among them.
There is 16 channel type and embody 1x6 Mux switch with HV20220 as main device.
Probe box consists of PB_Main board , PB_Odd board and PB_Even board to separate the
element as odd or even.
5.2. Detail description

Probe ID connects to the system with Pull up resistance at 3.3V. To make ID bit Low, short
between ID bit and Ground. The signal that probe connect with the system is pull up in system
inside and the Probe insert signal is set as ground at probe. Thus when /PRB_INS is low, High
Voltage also turn 0V into +/ - 80 V and it is possible to firing. 5V TTL drive HVSW HV20220
Control signal. The signal is buffering at PB_main board and divides PB_Odd and PB_Even.
Some of ultrasound signals, Echo 0,2,4,..,14, connect to PB_Odd, and some of them, Echo
1,3,5,..,15, connect to PB_Even.
5.3 Probe Connector Pin Define

Using ITT Cannon 60 Pin Male Connector its array is 6x10 matrix.
The bottom of left under take a view of Female connector connected the system is 1A pin.
The define of each pin is as bellows;
1 2 3 4 5 6
A ECHO 0 GND ECHO 1 GND ECHO 2 GND
B GND ECHO 3 GND ECHO 4 GND ECHO 5

C ECHO 6 GND ECHO 7 GND ECHO 8 GND
D GND ECHO 9 GND ECHO 10 GND ECHO 11
E ECHO 12 GND ECHO 13 GND ECHO 14 ECHO 15
F N.C. N.C. GND + 80 V + 80 V GND
G GND - 80 V - 80 V GND +5V GND
H /DAT0 0 /DATA 1 GND /DATA 2 /DATA 3 GND
J Remote HVSW_CLK /HVSW_LE N.C. N.C. PRB_ID 0
K PRB_ID 1 PRB_ID 2 GND PRB_ID 3 PRB_ID 4 /PRB_INS

Echo [0-15] I/O Pulser Output & Echo Signal

TEMP_DXP O Not use even it define as temperature Sensor. (Pin 1F)
TEMP_DXN O Not use even it define as temperature Sensor. (Pin 2F)
+ 80V I High voltage power
- 80V I High voltage power

+ 5V I TTL power
/DATA[0-3] I HVSW Control Data
Buffer the data from PB_main board to Not Gate
HVSW_CLK I 3.15MHZ Clock 24 ea
/HVSW_LE I Latch the data in HVSW inside by changed to Low when input
the last 24th data
Remote O The switch on the probe is using for toggle.
Using for Freeze : Press it short
Using for Store : Press it long (about 3 seconds )
PRB_ID[0-4] O Probe Identity Number

Default: High (To change Low, short it with Ground terminal)
To distinguish probe type, use PRB_ID 4’
- Convex : Low
- Linear : High
/PRB_INS O Ground
It is pull up as follows to check whether the probe connect with
system or not.
Default in system, Ground in PB_main board

5.5 Probe ID
ID Bit 4 3 2 1 0 Probe Name BF Delay BF Mid Triple

š : Open data Rom Rom Rom
˜ : Short
0x10 š ˜ ˜ ˜ ˜ L2-5/120CD 0xFF9B K16 K17 K18

0x11 š ˜ ˜ ˜ š L2-5/150CD 0xFF9B K19 K20 K21
0x12 š ˜ ˜ š ˜ L4-7CD 0xFF9B K22 K23 K24

0x13 š ˜ ˜ š š L5-9CD 0xFF9B K25 K26 K27
0x14 š ˜ š ˜ ˜ L5-9/60CD 0xFF9B K28 K29 K30
0x15 š ˜ š ˜ š L2-5/170CD 0xFF9B K31 K32 K33

0x16 š ˜ š š ˜ LV4-7AD 0xFF9B K34 K35 K36
0x17 š ˜ š š š LV5-9AD 0xFF9B K37 K38 K39
0x00 ˜ ˜ ˜ ˜ ˜ C2-5/60BD 0xFFE0 K40 K41 K42

0x01 ˜ ˜ ˜ ˜ š Reserved 0xFFE0 K43 K44 K45
0x02 ˜ ˜ ˜ š ˜ C4-9/10ED 0xFFD0 K46 K47 K48
0x03 ˜ ˜ ˜ š š C4-7BD 0xFFD0 K49 K50 K51
0x04 ˜ ˜ š ˜ ˜ C4-9/13CD 0xFFD0 K52 K53 K54

0x05 ˜ ˜ š ˜ š C5-8BD 0xFFE0 K55 K56 K57
0x06 ˜ ˜ š š ˜ Reserved K58 K59 K60
0x07 ˜ ˜ š š š Not supported

5.6 PCB Lay Out

5.6.1 PB Main Top Side
1 PB-EVEN LAYER 8 59
2 LAYER 1 60
6 PB-MAIN
0G
5
1G
4 ITT CANNON MALE
Probe Cable 2G
3 TOP VIEW
3G
2
4G
1
A B C D E F G H J K
60 PB-ODD LAYER 8 2
59 LAYER 1 1

5.6.2 PB_ODD Top/Bottom Size
ELM 49
ELM 47
U11 U7 U2 .
.
.
` .
.
PB-ODD LAYER 8
ELM 3
ELM 1
REMOTE 1
REMOTE 0
ELM 95
ELM 93
U1 U6 U10
.
.
.
.
PB-ODD LAYER 1
ELM 53
ELM 51

5.6.3 PB_EVEN Top/Bottom Size
ELM 50
ELM 48
. U3 U8 U12
.
.
.
`
.
PB-EVEN LAYER 1
ELM 4
ELM 2
VCC
TEMP_DXP
ELM 96
ELM 94
U13 U9 U4
.
.
.
` .
.
PB-EVEN LAYER 8
ELM 54
ELM 52

Mysono201 Section 2-6. ASIC Data Sheet
6. ASIC Data Sheet

6.1 MAGA0010A Manual: Frame Memory Controller
6.1.1 Description
MGA001A is ASIC for FMC use only and design to make a various signal under ASIC
Technology.
The signal related with Frame memory is Data and Address bus, Control signal such as
/RAS ,/CAS, /OE, /WE, etc.
Total Frame Average Factor is 6ea since Data Bus in Frame memory connect with Frame
Average Logic at chip inside. Mysonon201 use only 4ea among them.
RAM DATA
FIFO OUTPUT Frame

averaging logic
Data
Address
/IORD CPU interface
/IOWR CPU access
logic
logic
RAM ADDRESS
Real address
count
/RAS,/CAS,/OE,/WE
Control logic

6.1.3 Pin Diagram
128
129
130
131
132
133
134
135
136
36
35
34
33
31
30
29
28
27
14
13
12
11
9
8
7
6
BDC_AD1
BDC_AD0
GDC_D0
GDC_D1
GDC_D2
GDC_D3
GDC_D4
GDC_D5
GDC_D6
GDC_D7
GDC_D8
BDC_A9
BDC_A8
BDC_A7
BDC_A6
BDC_A5
BDC_A4
BDC_A3
BDC_A2
BDC_A16
BDC_A15
BDC_A14
BDC_A13
BDC_A12
BDC_A11
BDC_A10
94
CPU_D0
95
CPU_D1
96
CPU_D2
97
CPU_D3
101
CPU_D4
102
CPU_D5
103
CPU_D6
104
CPU_D7
81
LC_BNK0
117 108
CPU_A0 LC_BNK1
118
CPU_A1
119 110
CPU_A2 LC_BNK2
120 111
CPU_A3 LC_BNK3
122 112
CPU_A4 LC_BNK4
123 113
CPU_A5 LC_BNK5
124 114
CPU_A6 LC_BNK6
125 115
CPU_A7 LC_BNK7
126
/IORD
127 82
/IOWR /REAL
83
REQ
157 84
ADC0 /L_OE
158 85
ADC1 /LS_OE
159 86
ADC2 /L_WE
160 88
ADC3 /R_OE
2 89
ADC4 /RS_OE
3 90
ADC5 /R_WE
4 92
5
ADC6
ADC7 MGA001A NRAB
/GDC_RD
/GDC_WR
105
106
93 107
E_HS CINE_NML
78 80
/BI_PLANE /GDC
77 79
PT2 /DSP
76 52
PT1 /CINE_CAS
74 51
EVEN_VS /CINE_WE
73 50
/ACK /FC_OE
66 57
/L_BEN /R_CAS
65 56
/R_BEN /R_RAS
55
ADDR_SEL
45 54
/EXT_BRAS220 /CINE_RAS
39
/EXT_FC_OE
38 46
/EXT_DATA_EN PORT46_B2
37 47
ALL_FC PORT46_B3
40 49
EXT_SEL0 PORT46_B4
42 50
EXT_SEL1 PORT46_B5
43 51
EXT_SEL2 PORT46_B6
72 137
FREEZE SUM0
71 138
/BMODE SUM1
67 141
CCLKS2 SUM2
70 142
/PWR_ON_RST SUM3
75 143
/OF_O_E SUM4
63 144
/B_RP SUM5
64 146
/B_OP SUM6
44 147
MASTER_CLK SUM7
RAM_D8
RAM_D7
RAM_D6
RAM_D5
RAM_D4
RAM_D3
RAM_D2
RAM_D1
RAM_D0
RAM_A0
RAM_A1
RAM_A2
RAM_A3
RAM_A4
RAM_A5
RAM_A6
RAM_A7
RAM_A8
15
16
17
18
19
23
24
25
26
156
155
154
153
152
151
150
149
148

6.2 MAGA003A Manual :Clocks Generators

MGA003A: Gate Array designed by ASIC technology
About 7500 gates
208 pin QFP package
6.2.1 Description
MGA 003A is composed of 5 different parts such as Sampling Clock Generator ( SCG ), Display
Clock Generator ( DCG ) , Gray Bar Display ( GBG ) , Constant Rate Display ( CRD ) control
logic , and address decoding logic.
6.2.2 Main Features

- SCG ( Sampling Clock Generator ) : Basically sampling clock is generated from ROM data
containing LOOK-UP table which is the clock – map .
These data are composed BASE - value , CORRECTION – value , and BLANK – value .
The correction data has AD clock pattern ( map ) and 2048 deferent clocks can be made.
- DCG (Display Clock Generator ) : Display clock is generated by using the ROM’s data of
display clock having this bit pattern. Mysono201 support 8 different display clock for each liner
and convex probe.
- GBU ( Gray Bar Generator ) : To make gray bar and overlay shadow by using hardware.
- Adrress decoding logic : The many kinds of I/O ports used in DSC are decoded in this logic.
- CRD (Constant Rate Display ) : Supply Read Clock of Frame Memory
6.2.3 Block Diagram
SCG ROM sampling

sampling
data clock
clock
generater
DCG ROM
data
CPU data CPU display DCG rom address
address INTERFACE clock
generater display clock
/WR,/RD LOGIC
HS,VS,E_VS
/VS,
SYNC EVS gray bar
CS,VD gray bar
GENERATER generater
HS,VS,BLANK
constant
denominator
rate display
numerattor or CRD
control logic
various
PORT OUT

6.2.4 Pin Diagram
136
135
134
133
132
129
128
127
126
125
122
121
120
119
118
116
115
114
113
112
101
102
103
104
105
106
107
108
109
ADDR9
ADDR8
ADDR7
ADDR6
ADDR5
ADDR4
ADDR3
ADDR2
ADDR1
ADDR0
ROND0
ROND1
ROND2
ROND3
ROND4
ROND5
ROND6
ROND7
ROND8
ADDR16
ADDR15
ADDR14
ADDR13
ADDR12
ADDR11
ADDR10
PRB_ID2
PRB_ID1
PRB_ID0
75
96 TST_REAL
163 TST25.2W 165
162 OVERPLAY Q0 166
123 /BLANK Q1 167
124 /HWND Q2 168
137 /VWND Q3 170
175 /H_SYNC Q4 171
176 VD Q5 172
CS Q6 173
Q7 164
178 /BMODE_EN 174
179 D0 GRAY_OE 177
180 D1 /RAMDAC_WR 188
181 D2 /RAMDAC_RD 189
184 D3 /LATCH_CLR 190
185 D4 L_C 191
186 D5 /TMR_CS0 192
187 D6 /TMR_CS1 194
D7 DACLK0 195
DACLK1 193
153 WIN0 197
154 A8 WIN1 198
155 A9 /ROM_CS0 199
156 A10 /ROM_CS1 200
158 A11 /ROM_CS2 201
159 A12 /ROM_CS3 138
160 A13 DIV0 139
161 A14 DIV1 140
A15 DIV2 141
149 DIV3 142
151 CON_LIN ULA_CLK0 144
152 /EADC ULA_CLK1 145
100 ZOOM/NML
/M_ENA MGA003A WGT0
WGT1
WGT2
146
147
148
WGT3
99
98 IO/W 95
97 /CPU_WR BRS2 94
/CPU_RD BRS1 93
48 BRS0
/PWR_ON_RST 90
204 /FIFO_WR 81
203 /RPT /AD_LATCH_CLR 80
202 /RP /AD_LATCH_CLK 77
/OF ADCLK 74
/ETRG 73
150 DBLK_DRP 72
MASTER_CLK CVX_BLK_WND
58
Z_ADC/4 76
Z_ADC/2 82
Z_ADC 71
/CLOCK_CS 46
/PORT_53_WR 47
/OL_GDC_BUF_EN 110
/OL_GDC_RD 111
/OL_GDC_WR 84
/UART1_CS 83
/UART0_CS 89
/TNR04_CS 88
/TNR03_CS 87
/TNR02_CS 86
/TNR01_CS 85
/TNR00_CS
45
/W_WR 35
/W_RD 19
/IOWR 7
/IORD
92
CLK2.52W 59
CLK3.15W 44
CLK5.04W 34
CLK6.3W 18
CLK10.8W 21
CLK12.5W 8
CLK25.5W
N_A10
N_A11
N_A12
N_A13
N_A14
N_A15
N_A16
C_A10
C_A11
C_A12
C_A13
C_A14
C_A15
C_A16
C_A17
N_D7
N_D6
N_D5
N_D4
N_D3
N_D2
N_D1
N_D0
C_D7
C_D6
C_D5
C_D4
C_D3
C_D2
C_D1
C_D0
N_A0
N_A1
N_A2
N_A3
N_A4
N_A5
N_A6
N_A7
N_A8
N_A9
C_A0
C_A1
C_A2
C_A3
C_A4
C_A5
C_A6
C_A7
C_A8
C_A9
10
11
12
14
15
16
17
22
23
24
25
28
29
30
31
32
208
207
206
205
35
36
37
38
40
41
42
43
60
61
62
63
64
66
67
68
69
70
57
56
55
54
52
51
50
49
9
5
4
3
2

6.3 MAGA005 Manual

6.3.1 Description
l To display the ultrasound image of the Convex probe on the monitor, system recognize
and read the data of Frame memory by Display clock that generated on DCG (Display
Clock Generator).
l One scanline will be interpolated to the Horizontal Sync (HSYNC) as fixed Scanline
number from the system and the frequency of interpolation DCG Clock will be changed
whenever the HSYNC is generated according to the Vertical Sync (VSYNC). The image
from Far-Field is interpolated as low frequency DCG Clock and there is a possibility of
mosaic problem on actual display.
l The CDR Logic uniformly converts the frequency of signal as 12.6 MHz that input to the
Monitor by 1D interpolation to horizontal axis for the data that is interpolated from the
Frame Memory as Monitor Dot Clock 12.6 MHz.
6.3.2 Block Diagram
FM_OUT[0..7] 8
CRD[0..3] 74 4 8 CRD_O[0..7]
HC
283
MGA005
CRD[4..7] 74 4
HC
283
12.6MHz
DULA_CLK50
005 내부
8 8 8
FM_OUT
A− B
X
A
A− B
X
A
DULA_Clk_50 +
CRD[0..7] B
Y
A
B
Y
12.6MHz WGT[0..7] A
B=WGT[0..3]
A=WGT[4..7]


6.3.3 Pin Diagram
7 32
8 D0 DD0 31
9 D1 DD1 30
10 D2 DD2 29
11 D3 DD3 26
12 D4 DD4 25
13 D5 DD5 24
14 D6 DD6 23
D7 DD7
42
43 B0
1
2
B1
B2 MGA005A
3 B3
B4
35
36 A0
37 A1
40 A2
41 A3
A4
18 11
21 CLR_/ULA ULA_CLK 4
34 CLR_/OUT CRD_CLK
CLR_/CRD
19
20 /RESET
OUT_/EN
6.4 MCB014 Manual

6.4.1 Main Features
- 4 Channel RX & 8 channel TX in one chip
- Up to 4 parallel beam receiving in each RX channel
- Full TX function including TX apodization, Coded exitation
- Throughput up to 62 MSPS
- Extended accuracy focusing delay: RX: Up to ± 3ns, TX: Up to ± 4ns
- Internal small micro-processor for internal initialization data computing
- Reduced initialization data sets for external initialization
- Initialization data loading (or computing) while running
- Powerful board debugging functions
- +3.3V Power Supply

6.4.2 Block Diagram
S/R : Shift Register Coef. Bank Apo. Curve
Out of the
FDCU:Focusing Delay
Computation Unit
Memory
MCB014A
Chip to each filter
Apo.
FDCU
Generator
E_FIFO0 S/R
10
E_FIFO1 S/R M
A/D I_FIFO U FIR Filter GFIFO
E_FIFO2 S/R X
E_FIFO3 S/R
Apo.
FDCU M_FIFO
Generator
E_FIFO0
EXT IN/OUT
10 S/R
E_FIFO1 M
S/R
E_FIFO2 S/R X
E_FIFO3 S/R
Apo.
FDCU L_FIFO
Generator
10 E_FIFO0 S/R
E_FIFO1 M
S/R
E_FIFO2 S/R X
E_FIFO3 S/R
EXT OUT/IN
Apo.
FDCU M_FIFO
Generator
10 E_FIFO0 S/R
E_FIFO1 M
S/R
A/D I_FIFO U FIR Filter GFIFO Data Path
E_FIFO2 S/R X
Control Logic
E_FIFO3 S/R
Reset,
TX Pulse Micro- Command Register,
Micro- Host Interface
Generator Processor Init. Data Calc.
Processor Test Output Interface,
TX Pulse
Etc.

6.4.3 Pin Diagram
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
EXT_PREG_DATA15
EXT_PREG_DATA14
EXT_PREG_DATA13
EXT_PREG_DATA12
EXT_PREG_DATA11
EXT_PREG_DATA10
EXT_PREG_DATA9
EXT_PREG_DATA8
EXT_PREG_DATA7
EXT_PREG_DATA6
EXT_PREG_DATA5
EXT_PREG_DATA4
EXT_PREG_DATA3
EXT_PREG_DATA2
EXT_PREG_DATA1
EXT_PREG_DATA0
ELEN_SEL0 232
157 223
H_ADDR0 ELEN_SEL1
156 65
H_ADDR1 ELEN_SEL2
155 H_ADDR2 ELEN_SEL3 66
178 15
177 H_DATA0 TX_OUT_P0 17
H_DATA1 TX_OUT_P1
176 21
H_DATA2 TX_OUT_P2
175 25
H_DATA4 TX_OUT_P4
172 35
H_DATA5 TX_OUT_P5
171 39
H_DATA7 TX_OUT_P7
167
H_DATA8
166 15
165 H_DATA9 TX_OUT_N0 18
H_DATA10 TX_OUT_N1
164 22
H_DATA11 TX_OUT_N2
160 31
H_DATA13 TX_OUT_N4
159 36
H_DATA14 TX_OUT_N5
42
TX_OUT_N7
152
B_H_RD
154
153
B_H_WR
B_H_CS MGA014A
151 B_RESET
150 120
B_PRF_IN B_DATA_READY
180
B_H_INT
145 SUB_LINE_TYPE0 B_PRF_OUT 181
144
SUB_LINE_TYPE1
143 225
147 SUB_LINE_TYPE2 TX_APOD0/ELEN_SEL11 226
LINE_TYPE0 TX_APOD1/ELEN_SEL10
146 229
LINE_TYPE1 TX_APOD2/ELEN_SEL01
230
121 TX_APOD3/ELEN_SEL00 67
TX_CLK TX_APOD4/ELEN_SEL20
223 68
TX_PN_EXCHANGE TX_APOD5/ELEN_SEL20
80 69
81 TX_P_POLARITY TX_APOD6/ELEN_SEL30 70
TX_N_POLARITY TX_APOD7/ELEN_SEL31
82
TX_PATTERAN
83
B_TX_MASK
179
RX_CLK
TX_APOD_CLK0/TX_OUT_N3 218
141 219
INIT_MODE0 TX_APOD_CLK1/TX_OUT_P3
140 220
INIT_MODE1 TX_APOD_CLK2/TX_OUT_N1
139 INIT_MODE2 TX_APOD_CLK3/TX_OUT_P1 221
73
TX_APOD_CLK4/TX_OUT_N7
149 77
EXT_DIR TX_APOD_CLK5/TX_OUT_P7
118 B_HEADER_A TX_APOD_CLK6/TX_OUT_N5 78
119 79
DATA_OUT_EN_A TX_APOD_CLK7/TX_OUT_P5
70
AD_CLK_OUT
B_HEATER_B 183
182
DATA_OUT_EN_B
117
EXT_A0
116 EXT_A1
112 184
EXT_A2 EXT_B0
111 185
107 EXT_A3 EXT_B1 189
EXT_A4 EXT_B2
106 190
EXT_A5 EXT_B3
105 194
104 EXT_A6 EXT_B4 195
EXT_A7 EXT_B5
103 196
EXT_A8 EXT_B6
101 197
100 EXT_A9 EXT_B7 198
EXT_A10 EXT_B8
99 200
EXT_A11 EXT_B9
98 201
97 EXT_A12 EXT_B10 202
EXT_A13 EXT_B11
93 203
EXT_A14 EXT_B12
92 EXT_A15 EXT_B13 204
88 208
EXT_A16 EXT_B14
87 209
EXT_A17 EXT_B15
86 EXT_A18 EXT_B16 213
85 214
EXT_A19 EXT_B17
84 215
EXT_A20 EXT_B18
EXT_B19 216
217
EXT_B20
AD_DATA00
AD_DATA01
AD_DATA02
AD_DATA03
AD_DATA04
AD_DATA05
AD_DATA06
AD_DATA07
AD_DATA08
AD_DATA09
AD_DATA10
AD_DATA11
AD_DATA12
AD_DATA13
AD_DATA14
AD_DATA15
AD_DATA16
AD_DATA17
AD_DATA18
AD_DATA19
AD_DATA20
AD_DATA21
AD_DATA22
AD_DATA23
AD_DATA24
AD_DATA25
AD_DATA26
AD_DATA27
AD_DATA28
AD_DATA29
AD_DATA30
AD_DATA31
AD_DATA32
AD_DATA33
AD_DATA34
AD_DATA35
AD_DATA36
AD_DATA37
AD_DATA38
AD_DATA39
234
235
236
237
238
239
240
1
2
3
4
5
6
7
8
10
9
11
12
13
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63

6.5 MGA015A Manual

6.5.1 Main Features
- Synthetic Aperture summing and Multi-beam demultiplexing (external RAM needed)
- Digital TGC, SGC (scan-line gain compensation)
- RF Decimation Filter and Decimation
- DC Cancelling Filter
- Mixer with variable frequency NCO(Numerically Controlled Oscillator)
- Dynamic FIR Filter
- Moving Averager
- N/M nearest decimation for I/Q
- Envelope Detector using Square-Root and Square
- Log Compression
- Decimation Filter for B/W and N/M nearest decimation for B/W
- Zone Blend
- Non-linear Black-Hole Filling & Noise Suppression Filter for B/W
- Anti-Aliasing and/or Edge Enhence filter for B/W
- Analog TGC (including analog SGC) data for Beamformer
6.5.2 BLOCK DIAGRAM
External
RAM
Synthetic Decimati 1/N DC Cancel Quadratur

Fro Apertur DTGC
on Decimat FIR Filter e
m e FIR ion Mixer
Dynamic
FIR Filter
M/N Pixel Log Envelop Moving

Decimation Decimation Compres e Average
to nearest FIR Filter sion Detecti
M/N
To
Zone BHF Decimation
BW Post B/W
Blend NSF DSC to nearest
Filter
To
Color
to &
ATGC
BF

6.5.3 I/O Signal Overview
RF_IN[15:0] I_OUT[15:0]
Q_OUT[15:0]
SC_INFO_I[7:0] Mid-Proce
IQ_RDY
ssor
SC_NO[7:0]
Main IQ_RDY1
PRF
Signal
IQ_CK_O
Flow RP
IQ_CK_O1
CK
BW_OUT[10:0]
RESET
BW_RDY
BW_CK_O
H_DATA[15:0
BM_INDEX[1:0]
]
H_ADDR[3:0] RP_OUT
H_WR
Host ATGC_OUT[11:0]
H_RD
Interface H_CS
ATGC_CK_O
RAM_DATA0[15:0
]
RAM_DATA1[15:0
]
ATGC ATGC_PRF
RAM_ADDR0[15:0
Part ]
ATGC_INFO[1:0] RAM_ADDR1[15:0
]
RAM_WR0
RAM_WR1
RAM
RAM_OE0 Interface
RAM_OE1

6.5.4 Pin Diagram
131: BW_OUT[10]
144: BW_OUT[0]
143: BW_OUT[1]
142: BW_OUT[2]
140: BW_OUT[3]
139: BW_OUT[4]
138: BW_OUT[5]
136: BW_OUT[6]
135: BW_OUT[7]
134: BW_OUT[8]
132: BW_OUT[9]
168: Q_OUT[15]
167: Q_OUT[14]
166: Q_OUT[13]
165: Q_OUT[12]
163: Q_OUT[11]
162: Q_OUT[10]
189: I_OUT[15]
188: I_OUT[14]
187: I_OUT[13]
186: I_OUT[12]
184: I_OUT[11]
183: I_OUT[10]
161: Q_OUT[9]
160: Q_OUT[8]
158: Q_OUT[7]
157: Q_OUT[6]
156: Q_OUT[5]
155: Q_OUT[4]
153: Q_OUT[3]
152: Q_OUT[2]
151: Q_OUT[1]
150: Q_OUT[0]
190: IQ_CK_O1
147: BW_CK_O
182: I_OUT[9]
181: I_OUT[8]
179: I_OUT[7]
178: I_OUT[6]
177: I_OUT[5]
176: I_OUT[4]
174: I_OUT[3]
173: I_OUT[2]
172: I_OUT[1]
171: I_OUT[0]
191: IQ_RDY1
146: BW_RDY
130: RP_OUT
185: VDD
175: VDD
164: VDD
154: VDD
145: VDD
137: VDD
129: VDD
192: VSS
180: VSS
170: VSS
169: VSS
159: VSS
149: VSS
148: VSS
141: VSS
133: VSS
VDD :193 128: VSS
IQ_RDY:194 127: BM_INDEX[0]
IQ_CK_O:195 126: BM_INDEX[1]
VSS:196 125: VDD
RAM_DATA0[15] :197 124: RF_IN[0]
RAM_DATA0[14] :198 123: RF_IN[1]
RAM_DATA0[13] :199 122: RF_IN[2]
VDD :200 121: RF_IN[3]
RAM_DATA0[12] :201 120: RF_IN[4]
RAM_DATA0[11] :202 119: RF_IN[5]
RAM_DATA0[10] :203 118: RF_IN[6]
VSS :204 117: RF_IN[7]
RAM_DATA0[9] :205 116: VSS
RAM_DATA0[8] :206 115: RF_IN[8]
RAM_DATA0[7] :207 114: RF_IN[9]
VDD :208 113: RF_IN[10]
RAM_DATA0[6] :209 112: RF_IN[11]
RAM_DATA0[5] :210 111: RF_IN[12]
RAM_DATA0[4] :211 110: RF_IN[13]
VSS :212 109: RF_IN[14]
RAM_DATA0[3] :213 108: VSS
RAM_DATA0[2] :214 107: RF_IN[15]
VDD 215 106: VSS
RAM_DATA0[1] :216 105: CK
RAM_DATA0[0] :217 104: VSS
VSS :218 103: PRF
RAM_ADDR0[15] :219 102: RP
RAM_ADDR0[14] :220 101: TESTEN
RAM_ADDR0[13] :221 100: CWK_SEL
MGA015A
RAM_ADDR0[12] :222 99: H_CS
VDD :223 98: H_RD
NC :224 97: H_WR
RAM_ADDR0[11] :225 96: VSS
RAM_ADDR0[10] :226 95: H_ADDR[0]
RAM_ADDR0[9] :227 94: H_ADDR[1]
RAM_ADDR0[8] :228 93: H_ADDR[2]
VSS :229 92: RESET
RAM_ADDR0[7] :230 91: VSS
RAM_ADDR0[6] :231 90: H_ADDR[0]
RAM_ADDR0[5] :232 89: H_DATA[1]
RAM_ADDR0[4] :233 88: H_DATA[2]
VDD :234 87: H_DATA[3]
RAM_ADDR0[3] :235 86: VDD
RAM_ADDR0[2] :236 85: H_DATA[4]
RAM_ADDR0[1] :237 84: H_DATA[5]
RAM_ADDR0[0] :238 83: H_DATA[6]
VSS :239 82: H_DATA[7]
RAM_WR0 :240 81: VSS
RAM_OE0 :241 80: H_DATA[8]
VDD :242 79: H_DATA[9]
RAM_DATA1[15] :243 78: H_DATA[10]
RAM_DATA1[14] :244 77: H_DATA[11]
RAM_DATA1[13] :245 76: VDD
VSS :246 75: H_DATA[12]
RAM_DATA1[12] :247 74: H_DATA[13]
RAM_DATA1[11] :248 73: H_DATA[14]
RAM_DATA1[10] :249 72: H_DATA[15]
VDD :250 71: VSS
RAM_DATA1[9] :251 70: ATGC[0]
RAM_DATA1[8] :252 69: ATGC[1]
RAM_DATA1[7] :253 68: ATGC[2]
VSS :254 67: ATGC[3]
RAM_DATA1[6] :255 66: ATGC[4]
VSS :256 65: VDD
1: VDD
2: RAM_DATA1[5]
3: RAM_DATA1[4]
4: RAM_DATA1[3]
5: VSS
6: RAM_DATA1[2]
7: RAM_DATA1[1]
8: RAM_DATA1[0]
9: VDD
10: RAM_ADDR1[15]
11: RAM_ADDR1[14]
12: RAM_ADDR1[13]
13: RAM_ADDR1[12]
14: VSS
15: RAM_ADDR1[11]
16: RAM_ADDR1[10]
17: RAM_ADDR1[9]
18: RAM_ADDR1[8]
19: VDD
20: RAM_ADDR1[7]
21: RAM_ADDR1[6]
22: RAM_ADDR1[5]
23: RAM_ADDR1[4]
24: VSS
25: RAM_ADDR1[3]
26: RAM_ADDR1[2]
27: RAM_ADDR1[1]
28: RAM_ADDR1[0]
29: VDD
30: RAM_WR1
31: RAM_OE1
32: VSS
33: VSS
34: SC_INFO[7]
35: SC_INFO[6]
36: SC_INFO[5]
37: SC_INFO[4]
38: SC_INFO[3]
39: SC_INFO[2]
40: SC_INFO[1]
41: SC_INFO[0]
42: SC_NO[7]
43: SC_NO[6]
44: SC_NO[5]
45: SC_NO[4]
46: SC_NO[3]
47: SC_NO[2]
48: SC_NO[1]
49: SC_NO[0]
50: VDD
51: ATGC_INFO[1]
52: ATGC_INFO[0]
53: ATGC_PRF
54: VSS
55: ATGC_CK_O
56: ATGC[11]
57: ATGC[10]
58: ATGC[9]
59: ATGC[8]
60: VDD
61: ATGC[7]
62: ATGC[6]
63: ATGC[5]
64: VSS

Mysono201 Section 2-7. I/O Map
7. I/O Map
I/O PORT DESCRIPTION

TIMER 01 start address
10H
/OF, /RPCLK -> rate pulse blank
Timer 01 start address
14H
/RP1,/ DELAY OF, /EADC1; /EADC1
18H
/RP2, DELAY OF /EADC2, /EADC2
1CH
20H
Analog gain control on MYSONO201
2CH ;Write only port
; bit [4..7] : Gain
DFC curve Offset & Triple Freq. control
; on MYSONO201
2DH ; Write only port
; bit [0..3] : DFC curve Offset
; bit [6..7] : Triple Frequency
B/B mode control port for scg on SA5000II
; Write only port
2EH
; bit 0 : High --> BB mode on
; Low --> BB mode off
Video format control port on SA5000II
; Write only port
2FH
; bit 0 : High --> NTSC method
; Low --> PAL method
MGA003A PORT
Bit [1..0] : Image Scale(Magnification) data
for SCG(Sampling Clock Gen.)
30H ; 00 .... most zoom-out image
; 01
; 10
; 11 .... most zoom-in image
MGA003A PORT
; bit [4..0] : Probe ID data for SCG(Sampling Clock Gen.)
31H
; 1xxxx .. linear probes
; 0xxxx .. convex probes
40H..41H Frame momory GDC access ports
Bit 0 : bank0 /bank1 selection flag [0/1]

42H
Bit [1..7] : reserved
43H Frame memory column address Offset data
44H Frame memory raw address Offset data

Bit 0 : B-mode raw address Offset data bit 8

Bit 1 : B-mode raw address counter Down/Up flag[1/0]
Bit [2..4] : Frame average Factors
000 … 1:0
001 … 1:0.33
010 … 1:0.6
011 … 1:1
45H
100 … 1:1.67
101 … 1:3
Bit 5 : Ping-Pong On/ Off flag[1/0]
Bit 6 : Double/Single scan flag[1/0]
[1/0] sector mode only /default
Bit 7 : Dual/Single mode flag [1/0]
[1/0] right/ left memory GDC access
Bit 0 : Cine/normal mode flag [1/0]
Bit 1 : B-mode direction left/right change flag[1/0]
46H
Bit [2..6] : Reserved
Bit 7 : You can not use this bit
Test port of MGA001A [read/write]
47H You can test the CPU address and data lines of MGA001A using this test
port.
; bit 0 : video display On/Off flag [1/0]
; (only image data)
; bit 1 : Linear/Convex flag [1/0]
; bit 2 : image Up/Down flag [1/0]
; bit 3 : memory selection flag
; [Bank0/Bank1 - 0/1]
; bit [5..4] : mode flag bits [1..0]
48H
; 00 - B-mode
; 01 - M-mode
; 10 - B/B-mode
; 11 - B/M-mode
; bit 6 : B/B or B/M mode initialization
; On/Off flag [1/0]
; bit 7 : You can not use this port.
bit [1..0] : image scale (Magnification) for DCG (Display Clock Gen.)
; control bits [1..0]
49H ; bit [5..2] : probe ID bits [5..2]
; bit 6 : Normal/Fast mode flag [1/0]
; bit 7 : gray bar On/Off flag [1/0]
Display clock data
4AH ; ROM Offset address
; [left image in B/B mode]
Display clock data
4BH ; ROM Offset address
; [right image in B/B mode]
; Bit [2..0] : BRS[2..0] of RAMDAC
4CH
; bit [7..3] : You can not use these bits.

4DH You can not use this port
4EH BT478 RAM ADDRESS (B/W)
4FH MGA003A TEST PORT
Timer 0 start address - VERTICAL WINDOW delay of /VWND

;,clk=HS, gate=/VS,
50H ; /VWND
;,clk=HS, gate=delay of /VWND
; reserved
Timer 1 start address - HORIZONTAL WINDOW
; delay of /HWND
;clk=CLK6.3M, gate=/HS,
54H
; /HWND
;clk=CLK6.3M, gate=delay of /HWND
; reserved
Battery Voltage A/D convert port
58H ; B0 : BAT_AD_CLK
; B7 : /BAT_AD_EN
Host Address
; Bit[3:0] - Address Area
; Bit[5:4] : 11-Mid_Processor_CS(Default/disable:0)
; : 0-MCB014 0_CS, 1_CS select(Default/0) - ?
; : 1-F/E_CPLD_CS(Default/disable:0)
;>>> MID porcessor control address
; 30~37H - h_addr0~7(p_bfic_addr0~7)
59H ;>>> BFIC & F/E board control address
; 00~07H - h_addr0~7(p_bfic_addr0~7)
; 21H - CPU_mode_addr(p_dbf_CPUmode)
; 22H - board_ver_read_addr(p_dbf_version)
; 23H - board_buf_en_addr(p_dbf_bufferenable)
; 24H - bfic_select_addr(p_dbf_bficselect)
; 25H - bfic_reset_addr(p_dbf_reset)
; 26H - txmask_initmode_addr(p_dbf_txmask_init)
5AH Host Data Low[7:0]
5BH Host Data High[15:8]
; B7 : LCD control
5CH
; B0 : LCD_ENABLE(default enable)
5DH POST_WR, POST_RD
* When this port is written,

; Post address will be reset.
5EH ; B1 : POST_OVL(default disable)
; B2 : POST_MENU(default disable)
; B7 : /POST_EN(default disable)

Probe element output only port

; B1..0 : Probe element
; 0 : 64el
; 1 : 80el
; 2 : 96el
5FH
; 3 : 128el
; B7..3 : Probe ID
; B7 : 1=LINEAR, 0=CONVEX
; B6 : 0
; B5 B4 B3 = PROBE ID
60H Overlay GDC parameter & status port
61H Overlay GDC command port
POST MEMORY ADDRESS SELECT PORT

62H
; B0..B4, 32 post memory
Period out port
; 3EH .... 0.8 MHz probe
; 18H .... 2 MHz probe
; 0DH .... 3.5 MHz probe
63H ; 09H .... 5 MHz probe
; 06H .... 7.5 MHz probe
; 04H .... 10 MHz probe
; 03H .... 12.5 MHz probe
; Freq = (50.4Mhz)E-1 ;= 19.84ns
70H SCAN LINE data
; bit [2..0] : Low Pass Filter selection data 600CINE

71H
; bit [4..3] : Triple Frequency
; bit 0 : Probe Selection flag
; If cart unit is not exist, This bit is not mean.
; bit [3..1] : Focal point ID data
; 000 .... nearest point
72H
; 111 .... farest point
; 00, 01, 10, 11
; FP1 FP2 FP3FP4
; bit [7..4] : Dynamic Range control data [DR]
; read only port
; bit 0 : clock second bit
; bit 1 : NTSC/PAL selection flag [0/1]
; bit 2 : Probe disconnection flag
73H
;[No_probe/Probe..1/0]
; bit [7..3] : Probe ID data
; 1xxxx .... linear
; 0xxxx .... convex

; only bit[2..0] is used

; bit 0 : Character display enable flag
; [Enable/Disable..1/0]
; bit 1 : Graphic display enable flag
74H ; [Enable/Disable..1/0]
; bit 2 : Mark display enable flag
; bit 3 : Menu display enable flag
; bit [5..0] :
; Program memory bank selection data
; for access of 0000H -- BFFFH
; (i.e. A15..A14 ==> 00,01,10),
; [EX_A19..EX_A14==> 000000]
75H
; for access of C000H -- FFFFH
; (i.e. A15..A14 ==> 11),
; Bit [5..0] : [EX_A19..EX_A14]
; B6 : reserved
; B7 : Gate Enable flag of /RP2 timer [Disable/Enable..1/0]
High Voltage control data
; 00h .... : 55V ; 10H
76H
; 7Fh .... : 65V ; :
; FFh .... : 75V ; 70H
77H M-mode column address (write only)
; Before /MENA 0
78H ; after /MENA 1
; Generate /SCG_RP, /LOAD_OF
; Doubling flag : ON = 0 ; 1 ; by falcon 94.11.07
79H
; OFF = 1 ; 0 ; by falcon 94.11.07
Focal Point Id Map
; bit1,bit0 ... 1st Focal Point Id
7AH ; bit3,bit2 ... 2nd Focal Point Id
; bit5,bit4 ... 3rd Focal Point Id
; bit7,bit6 ... 4th Focal Point Id
F/M test port
; bit4..0 : increment of counter
7BH ; bit5 : 0=off/1=blink function
; bit6 : 0=row/1=col
; bit7 : 0=off/1=on
7CH ; Focal point

; test port of Xilnx4003H

7EH You can test the CPU address and data lines of Xilinx4003H using this test
port.
test port of Xilnx4003H
7FH You can test the CPU address and data lines of Xilinx4003H using this
test port.
80H Clock_cs READ port
Flash Momory Command port
; B0: ALE
; B1: CLE
; B2: Flash Chip Enable 1=Enable, 0=Disable
090H ; B3: Smart Midea Chip Enable
; B4: Flash2 Chip Enable
; B5: ECC generation mode 1=512B, 0=256B
; B6:
; B7: Flash, Smart, Flash2 Spare Area Enable 0=Enable
091H Flash Memory Data Port
092H CINE DRAM ADDR ROW

093H CINE DRAM ADDR COL
094H CINE DATA port
CINE Access frame (1frame :256x256)
; B[6..0] : Frame #
095H
; B7 : 1=high block, 0=low block
;ROW addr : 256-512, 0-255 <--- only concept
VIDEO Access Mode
096H ; B1: 1=noninterace V_buffer read stop on, 0=off
; B2: 1=noninterace or interace V_buffer write hold on, 0=off
FLASH MEMORY
; B0: Flash Ready/Busy
; B1: Smart Media Ready/Busy
097H
; B2: Flash2 Ready/Busy
; B[3..6]:Reserved
; B7: Smart media insert 1=insert, 0=not insert

SRAM Command
;B0: SRAM addr16
;B1: SRAM addr17
;B2: SRAM addr18
;B[3..6]: reserved
099H
;B7: 1=CPU access, 0=SYSTEM access
;B2&B1 B0
; 0 x : Frame grabber addr space
; 1 0 : OS_buff front, for smart me dia
; 1 1 : OS_buff back, for temp memory
CINE Command Port
; B0: Cine on command 1: Cine on, 0: Cine off
09AH ; B1: FM_CINE Select command 1:FM Display, 0: Cine Display
; B2: 1=CPU access to DRAM, 0=SYSTEM access to DRAM
; B3: mode change LOW-->HIGH-->LOW One shot pulse
CINE Current Writing Frame
09BH ; B[6:0]
; B7: Cine Full Flag
CINE Current Reading Frame
09CH
;B[6:0]
CINE Status
; B0:
; B1: Clear_on_off 1:Clear On, 0:Clear End
09DH
; B2:
; B3: REAL WT ON 1:real 0:not real
; B4: CINE RD ON 1:CINE read, 0:not CINE
09EH ; B[0..7]: SRAM Addr
09FH ; B[0..7]: SRAM Data
0A0H UART2 Chip [8250 used for PC interface] on MYSONO201
Status write & read port in MYSONO201
status write port on MYSONO201
; bit0 - Probe not_exist/_exist
; bit1 - BB/_B mode flag for SCG on MYSON201
0A8H ; bit7 - Print on
status read port in MYSONO201I
; bit0 - RSTSI - for keyboard
; bit1 - RSTSE - for Remote controller
; bit2 - RSTSP - for PC interface

0B0H 74ACT715 Programmable Video Sync Generator Address Register

0B1H Data Low : Temporary BIT
0B3H Data High : Temporary BIT
0B4H Modified M-mode ETRG length
0B5H M-mode Fixed /ETRG Window Trigger Signal for FPGA
0B7H B5 : EVEN V-SYNC
BATTERY RELATIVE STATE OF CHARGE 1-100
; B7 - 1 : battery exist, 0 : no
0B8H
; B5 - 1 : transition exist, 0 : no
; B4..B0 : state of charge
B0 : beamforming ETRG enable
; 1 : start download trigger
0B9H
; 0 : end download trigger
; B1-B7 : Not used
0E0H Clock Chip [RP5C01]
0F0H UART0 Chip [8250 used for key interface]
0F8H UART1 Chip [8250 used for remcon unterface]

Mysono 201 Section 3-1. LCD.
1.LCD
1.1General Description
The LG LCD model LP064V1 LCD is a Color Active Matrix Liquid Crystal Display with an integral Cold
Cathode Fluorescent Tube (CCFT) back light system. The matrix employs a-Si Thin Film Transistor as the
active element.
It is a transmissive type display operating in the normally white mode. This TFT-LCD has a 6.4 inch
diagonally measured active display area with VGA resolution (480 vertical by 640 horizontal pixel array).
Each pixel is divided into Red, Green and Blue sub-pixels or dots which are arranged in vertical stripes.
Gray scale or the brightness of the sub-pixel color is determined with a 6-bit gray scale signal for each dot,
thus, presenting a pallete of more than 262,144 colors.The LP064V1 LCD is intended to support applications
where low power consumption, weight and thickness are critical factors and graphic displays are important.
In combination with the vertical arrangement of the sub-pixels, the LP064V1 characteristics provide an
excellent flat panel display for office automation products such as portable computers and NTSC application.
Timing Controller
R[0:5]
G[0:5]
(GVC10029
B[0:5] Column Driver (UP)
CLK
Raw Driver
HSYNC
VSYNC 640 x RGB x 480
DTMG
TFT LCD Array
+5V Column Driver (DOWN)

Power Supply
VSS DC/DC
+12V
VSS INVERTER
B/L
CN

1.1.1General Display Characteristics

The following are general feature of the model LP064V1 LCD;
6.4 inches( cm) diagonal

Active display area
168W x 123 H x 9.0D mm Typ.
Outsize dimensions
0.204 mm * 0.204 mm
Pixel pitch
640 hor. By 480 ver. Pixels
Pixel format
RGB stripe arrangement
6-bit
Color depth
transmissive mode, normally white
Display operating mode
hard coating(2H),
Surface treatment
anti-glare treatment of the front polarizer
1.2 Maximum Ratings

The following are maximum values which, if exceeded, may cause faulty operation or damage
to the unit.
Table 1 Absolute Maximum Rations

Parameter symbol Values Units Notes
Min. Max.
Power Input Voltage VD D -0.5 +5.5 Vdc at 25℃
Logic Input Voltage VL/H 0 VD D +0.5 Vdc at 25℃
Operating Temperature TO P 0 +50 ℃ 1
Storage Temperature T ST -20 +60 ℃ 1
1.3 Electrical Specifications

The LP064V1 requires two power inputs. One is employed to power the LCD electronics and
to derive the voltages to drive the TFT array and liquid crystal. The second input which powers
the backlight CCFT, is typically generated by an inverter. The inverter is an external unit to the
LCD.
Table 2 Electrical Characteristics:
Parameter Symbol Values Units Notes
Min. Typ. Max.
MODULE:
Power Supply Input Voltage VD D 4.5 5.0 5.5 Vdc
Power Supply Input Current ID D - 180 280 mA 1
Ripple/Noise - - - 60 mV
Logic Input Level, High VI H 0.7VD D - VDD Vdc 2
Logic Input Level, Low VI L Vss - 0.3VD D Vdc 2
Power Consumption P - 0.9 1.54 W 1
BACKLIGHT
Backlight Input voltage VB L - 355 385 VR M S 3
Backlight Current IB L 3.0 5.0 9.0 mA
Lamp Kick-Off Voltage - - 680 VR M S 25±2℃
- - 860 0℃
Operating Frequency FB L 35 55 80 KHz

1.4 Optical Specifications

Optical characteristics are determined after the unit has been ‘ON’ and stable for
approximately 30 minutes in a dark environment at 25℃. The values specified are at an
approximate distance 50cm from the LCD surface at a viewing angle of Φ and θ equal to 0°.
Appendix A presents additional information concerning the specified characteristics.
Table 2 Optical Characteristics

Parameter Symbol Values Units Notes
Min. Typ. Max.
Contrast Ratio CR 100 - - 1
Surface Brightness, white(IBL=5.0mA) SBWH 100 120 - cd/m2 2
Brightness Variation SBV - - 1.4 3
Response Time
Rise Time TrR 20 50 msec 4
Decay Time TrD - 35 50 msec 4
CIE Color Coordinates
Red xR 0.557 0.587 0.617 5
yR 0.322 0.352 0.382 5
Green xG 0.254 0.284 0.314 5
yG 0.522 0.552 0.582 5
Blue xB 0.114 0.144 0.174 5
yB 0.092 0.122 0.152 5
White xW 0.292 0.322 0.352 5
yW 0.289 0.319 0.349 5
Viewing Angle(CR>10:1)
x axis, right (Φ=0º) θ 40 6
x axis, left(Φ=180º) θ 40 degree, °
y axis, up(Φ=90º) θ 10
y axis, down (Φ=270º) θ 30
1.5 Interface Connections

This LCD employs two interface connections, a 31 pin connector is used for the module and a three pin
connector is used for the integral backlight system. The electric interface connector is a model DF9B-31P -1V,
manufactured by Hirose. The mating connector part number is DF9-31S-1V or equivalent. The pin
configuration for the connector is shown in the table below.

Table 3 Module Connector Pin Configuration

Pin Symbol Description Notes
1 Vss Ground Connect to Vss, see Note 1
2 CLK Main clock
3 Hsync Horizontal sync.
4 Vsync Vertical sync.
6 R0 Red data Red data least significant bit(LSB)
7 R1 Red data
8 R2 Red data
9 R3 Red data
10 R4 Red data
11 R5 Red data Red data most significant bit(MSB)
13 G0 Green data Green data least significant bit(LSB)
14 G1 Green data
15 G2 Green data
16 G3 Green data
17 G4 Green data
18 G5 Green data Green data most significant bit(MSB)
20 B0 Blue data Blue data least significant bit(LSB)
21 B1 Blue data
22 B2 Blue data
23 B3 Blue data
24 B4 Blue data
25 B5 Blue data Blue data most significant bit(MSB)
26 Vss Ground
27 DTMG Data Timing Signal
28 Vdd Power(+5V) Connect to Vdd, see Note 2
29 Vdd Power(+5V) Connect to Vdd, see Note 2
30 OAS O/A, A/V Selection see Note3
31 NC No Connection
The backlight interface connector is a model BHR-03VS-1, manufactured by JST. The mating
connector
part number is SM02(8.0)B-BHS-1-TB or equivalent. The pin configuration for the connector
is shown in the table below.
Table 4 Backlight Connector Pin Configuration

Pin Symbol Description Notes
1 HV Lamp power input 1
2 NC No connect
3 LV Ground

1.6 Power Sequence
4.5V 4.5V
0.7V
POWER SUPPLY VDD
t1
for LOGIC
t4
t2 t3
DATA VALID
INTERFACE SIGNAL Vi
t5
t6
CCFL INVERTER INPUT POWER
POWER SEQUENCE
t1≤ 40msec, 0<t2≤ 50msec, 0<t3≤ 50msec, t4<1sec, 0< t5≤ 2 sec,
0<t6≤ 2sec
* Set 0 Volt ＜ Vi(t) ≤VD D (t)

Here Vi(t), VDD (t) indicate the transitive state of Vi, VDD when power supply is turned ON or
OFF
1.7 Mechanical Characteristics

The chart below provides general mechanical characteristics for the model LP064V1 LCD. The
surface of the LCD has an anti-glare coating to minimize reflection and a 2H hard coating to
reduce scratching. In addition, the figure below is a detailed mechanical drawing of the LCD.
Note that dimension is given for reference purposes only.
Outside dimensions Width 168 mm

Height 123 mm
Thickness 9.0 mm
Active Display area Width 130.56 mm
Height 97.92 mm
Diagonal 163.2 mm
Weight (approximate) 230 g Typ.

9.0


1.8 International Standards (TBD)

1.8.1. Safety
UL1950 “Safety of Information Technology Equipment Including Electrical Business
Equipment.
Third Edition” Underwriters Laboratories, Inc. 1995
CAS C22.2 “Safety of Information Technology Equipment Including Electrical
Business Equipment.
Third Edition” Canadian Standards Association, 1995
EN 60950 “Safety of Information Technology Equipment Including Electrical Business
Equipment.”
European Committee for Electro technical Standardization(CENELEC), 1995
Ref. No. EN 60950: 1992 + A1: 1993 + A2: 1993 + A3: 1995 E
(IEC 950: 1991 + A1: 1992 + A2: 1993 + A3: 1995, modified )
1.8.2. EMC
ANSI C63.4 “Methods of Measurement of Radio-Noise Emissions from Low-Voltage
Electrical and
Electronic Equipment in the Range of 9kHz to 40GHz.”
American National Standards Institute(ANSI),1992.
C.I.S P.R “Limits and Methods of Measurement of Radio Interference Characteristics of
D.Information
Technology Equipment.”International Special Committee on Radio Interference
EN 55 022 “Limits and Methods of Measurement of Radio Interference Characteristics of
Information
Technology Equipment.”European Committee for Electro technical
Standardization
(CENELEC),1988
1.9 Handling Precautions

Please pay attention to the followings when you use this TFT/LCD module with Back-light unit.
1.9.1. Mounting Preacaution

1) You must mount Module using mounting holes arranged in 4 corners.
Be sure to turn off the power when connecting or disconnecting the circuit.
2) Note that the polarizers are easily damaged. Pay attention not to scratch or press this
surface with any hard object.
3) When the LCD surface become dirty, please wipe it off with a soft material.
(ie.cottonball)
Protect the module from the ESD as it may damage the electronic circuit (C-MOS).
Make certain that treatment person’s body are grounded through wrist bend.

4) Protect the module from the ESD as it may damage the electric circuit(C_MOS).
Make certain that treatment person’s body are grounded through wrist bend.
5) Do not disassemble the module and be careful not to incur a me chanical shock that
might occur during installation. It may cause permanent damage.
6) Do not leave the module in high temperatures, Particularly in areas of high humidity for
a long time.
7) The module not be expose to the direct sunlight.
8) Avoid contact with water as it may a short circuit within the module.
1.9.2. Operating Precaution

1) The spike noise causes the mis-operation of circuits.
Be lower the spike noise as follows :
VDD=±200mV, V1=±200mV( Over and under shoot voltage.)
2) Response time depends on the temperature. (In lower temperature, it becomes longer.)
3) Brightness depends on the temperature. (In lower temperature, it becomes lower.)
And in lower temperature, response time (Required time that brightness is stable after
turn on) becomes longer.
4) Be careful for condensation at sudden temperature change. Condensation make damage
to polarizer or electrical contact part. And after fading condensation, smear or spot
will occur.
5) When fixed pattern are displayed at long times, remnant image is likely to occur.
6) Module has high frequency circuit. If you need to shield the electromagnetic noise.
Please do in yours.
7) When Back-light unit is operating, it sounds.
If you need to shield the noise, please do in yours.
1.9.3 Electrostatic Discharge Control

Since module is composed with electronic circuit, it is not strong to electrostatic discharge.
Make certain that treatment persons are connected to ground through list band etc.. And don’t
touch I/F pin directly.
1.9.4 Precaution For Strong Light Exposure.

Strong light exposure causes degradation of polarizer and color filter.
1.9.5 Storage
When storing module as spares for long time, the following precautions are necessary.
1) Store them in a dark place: do not expose then to sunlight or fluorescent light. Keep the
temperature between 5 and 35 at normal humidity.
2) The polarizer surface should not come in contact with any other object. It is
recommended that they be stored in the container in which they were shipped.

1.9.6 Handling Precautions For Protection Film

1) When the protection film is pealed off, static electricity is generated between the film
and the polarizer. This film should be pealed off slowly and carefully by people who are
electrically grounded and with well ion-blown equipment or in such a condition. etc.
2) The protection film is attached the polarizer with a small amount of glue.If some stress
is applied to rub the protection film against the polarizer during the time you peal off
the film, the glue is apt to remain more on the polarizer. So please carefully peal off the
protection film without rubbing it against the polarizer.
3) When the module with protection film attached is stored for long time, sometimes there
remains a very small amount of glue still on the polarizer after the protection film is
pealed off. Please refrain from storing the module at the high temperature and high
humidity for glue is apt to remain in these conditions.
4) The glue may be taken for the modules failure, but you can remove the giue easily.
When the glue remains on the polarizer surface or its vestige is recognized, please wipe
them off with absorbent cotton waste or other soft material like chamois soaked with
Normal-hexane.
1.9.7 Safety
1) If module is broken, be careful to handle not to injure. (TFT/LCD and lamp are made of
glass)
Please wash hands sufficiently when you touch the liquid crystal coming out from broken
LCDs.
2) As it is possible for PCB or other electronic parts of module to small to smoke and to
take fire because of the short circuit. Please design the circuit of your instrument not to
flow the electric current to TFT/LCD module more than 500mA. (by apply the fuse for
example)
3) As Back-light unit has high voltage circuit internal, do not open the case and do not
insert foreign materials in the case.

A-1 Brightness
<measuring point>
160 320 480 ( pixel)
120
1 2
3 240
360
4 5
A-2 Response Time

The response time is defined as the following figure and shall be measured by switching
the input signal for “black” and “white”.
TrR TrD
%
100
90
Optical
Response
10
white white
0
black

A-3 Viewing angle
<Definition of viewing angle range>
θ = 0。
φ = 90。 z A
yu
(12:00)
θ
φ = 180。 φ = 0。
xl
(9:00) (3:00) xr
TFT LCD φ = 270。

z' yd
MODULE (6:00)

Mysono 201 Section 3-2. Adapter.
2.Apapter
2.1 SPEC. and Application Range
It is electric power supply of myso201, and the output is DC16V which is supplied by AC power
source.
- Model Name : MYSONO201 ADAPTOR
- Inputting voltage and frequency : 50/60Hz±3Hz AC 90V – 264V
- Inputting current : Max 1.3A
- Outputting voltage and a rated current
Voltage Min. Normal Max. Ripple &

Current Non-load 2.3A 3.3A Noise
Output 16V±1 16V±1 16V±1 400 mV
notice)
1) For measuring Allowed Ripple Voltage, 100uF electrolytic condenser on end of Probe and
0.1uf Ceramic condenser are closely connects with load.
2) measurement Scope is 100MHz Analog Scope.(50mV/0.5msec)
- cooling method : natural air cooling
- safety, electric wave, standard : satisfies IEC60601-1
- efficiency : the above 75 % (inputting 220V , MAX load standard)
- Environment of operation
1) the range of temperature : 0℃ ~40℃
2) the range of humidity : 10% ~90%RH(be careful dewdrop)
- Environment of storage
1) the range of temperature :-15℃ ~70℃
2) the range of humidity :10% ~95%RH(be careful dewdrop)
- the range of OCP 1) 16V :6A~10A
- the range of OVP 1) 16V :18A~21A
- Setup/Off Time(basis of Max Load)
1) AC260V : below 2 sec
2) AC90V : below 6 sec
- Rising/Falling Time
1) 16V : below 30 ㎳
- Inrush current 1) Max 70A
- Over/Undershoot 1) below 3% output

Mysono 201 Section 3-2. Adapter.
2.2 Block Diagram
AC IN OUTPUT
INPUT FILTER RECTIFIER 1 RECTIFIER 2
TRAN
S
SWITCHING&
CONTROL
ERROR AMP
Photo Co.
OVP DETECT

Mysono 201 Medison Co.,Ltd.
2.3 Schematic Diagram
J7
AC(AC90V-264V) IN
F1
250V 3.15A RV1
Main_Board
AC IN1 10G 471 AC_IN1 D1
1 1 Vin
C1 R36A
CON1 101
Board2
T1 T2 2 C2 27 GND_BD2
J8 F2
AC IN2 3 150u/400V
1 5mH 5mH 471
250V 3.15A C6
CON1 4 C40A C31A C39A
AC_IN2 104 47uF 50V
R3 C4 C5 GBU6A Vchg_BD2
J9 1.5M 0.5W 474 250VAC 224 250VAC NTC1 47uF 50V
GND EARTH NTC3D_9
1 R39A Vout_BD2
1.5k
8
7
6
5
CON1 NTC2
NTC3D_9
OUT
VCC
GND
Vref
C8 TO J2 R40A R41A
103 630V T3 C3 150p/1kv 1k 5.6k 1%
Vin U6A
Vchg Vcc_2 FNA7554 ISO1A
10k 1%
R10 OUT_2 PC817
R42A
Rt/Ct
J10
S/S
47k 2W D3 L1 IS_2 C32A
FB
IS
R12 D4 UF4007 Vout 104
5uH 1 GND_BD2
C38A
1
2
3
4
47k 2W C41 D15SC20M C13 T O CON1 104
C19 C11 C12 JACK
Vcc 47u 20V OS Vout_BD2
R15 68p/1kv 47u 20 OS 47u 20 OS 470/25 J11 U7A
R14 27 GND2
AC_IN1 GND2 1 D12A KA431
GND1
R13 C33A C34A
D5 UF4007 0.02 1% CON1 182 103 R44A1k 18V
150k 1W EER2828
104
C35A
J3 C36A ISO2A R51A
Vchg 102 Vcc_2 PC817 R52A 10
Vout 1 1k
G ctl 2 GND_BD2
Is/bat- 3 R45A
Vcc Q2 IinSense 4 1k 1%
OUT SSN12N60 5
IS Vbat- 6
7
8
9
R23 10
0.51 3W Vbat+ 11 GND2_BD2
12
CON12
CON4
Vcc
C22 LED_GREEN LED_RED IS 1
222 250V OUT 2
LED1 3
4
G R LED 2COLOR J4
PSTEK(Power System Technology Co. Ltd.)

1-32 Pho-Dong Shiheung-City
Kyunggi-Do, Korea
TEL: 82-32-696-0096
Title
CHARGER
Size Document Number Rev

B Mysono revision1.0 Designed by Cha.Y.M 3.0
Date: Thursday, August 24, 2000 Sheet 1 of 1

Mysono 201 Section 4-1. Trouble Shooting
1. Trouble shooting
1.1System Booting Diagnosis
Power On
(Press 1 sec)
Power Check Insert Power

beep sound? N Adapter LED N Power Adapter N Cablet & Power
ON Cable On
Y Check Power
Adapter
Insert System
Check System
N Power Cable &
Y Power Cable
Power On
Check System
Power
Check Logo
N Check LCD Cable
Display
Message :
Check Image
N Probe is not N Check DSC
Display
installed
Y Power off &

insert probe &
power on
Check Key Check Key Test

N
operation Program
Check Touch Check Key board

N
Pad Connector
OK

1.2Image1 Diagnosis
Power On
Check Probe
Check Probe Check System
N ID N
Name Probe Connector
(Notes 1)
Check FE
Y Adapter & FE 80
pin
Connector(J3)
Check Gain
Check Image Check FE /EOF
N control & N
Display or DSC MGA015A
Noise Display
Check FE
High Voltage N Check Power
(Notes 2)
Y Y
Check Probe
HVIC
Check Notes 1 : Probe Pin 1A is left bottoam

N OK
scanline blank ID4 -- 5K
ID3 -- 4K
ID2 -- 2K
ID1 -- 1K
Y
ID0 -- 6J
GND -- 3K
short means low
open means high
Try Knife Test
Blank One : Check Probe Element or Probe Box Element Cable
Notes 2 : +HV -- 4F,5F
Blank Five : Check FE Pulser or TGA AMP
-HV -- 2G,3G
Symetry Blank on aperure shape inside : Check A/D Converter or OP
GND -- 6F
Amp(AD812)
/PRB_INS and ground must be shorted

1.3 Battery Diagnosis
Battery with
Battery Only
System
Press Check Check Battery Check System

N Fix Battery
Button LED Power
LED ON Y
LED Off : No Battery

OK LED RED : Battery Discharging without Power Adaptor
LED Yellow : Battery Charging with Power Adaptor
LED Green : Battery Full Charged with Power Adaptor
Beep sound
Check System
somtimes &
Power
LED Red
N
Recharge
Connect Power
Adapter

1.4 Etcetera Diagnosis
Defect symptom Help index
1. Does the image appear on the screen?

(only LCD does not display)
è Y : check the bad connecting with keyboard and main
System is no booting body.
2. Does parts get damaged?
(Overlay GDC, CPU, FPGA, PROM, SYSTEM ROM..etc)
è Y : Change the parts
1. Does DSC board and F/E board connector is normal?
è N : check the connector connecting
The image is not
2. When inputting image pattern in Debug mode, Does pattern
appeared
appear are normal?
è Y : hardly output data from F/E board. /
1. Does DSC board and F/E board connector is normal?

The image is appeared èN : check the connector connecting
as frosty 2. Does Frame Memory is normal?
èN : change the FM
The image is appeared Does Cine memory is normal? (or peripheral buffer)
as frosty in Cine mode è Change the Cine memory (0~15, 16~31)
M-mode image is not Does Right Frame Memory is normal? (or peripheral latch)
appeared or broken è N : change the Memory and Latch
Does some part of Key test is not working?

Keyboard
è Y : check the bad connecting with Keyboard and
defectiveness
Main body and check the Key Rom
1. Does Probe is normal?(recognize Probe ID)

è change the Probe
2. Do SPC and FE connector or F/E and DSC connector are
Not able to recognize
normal?
Probe
è check the connector connecting
3. Does F/E CPLD is normal?
è change the parts
1. How much space Does Flash memory have?

The image not be able
è N : image all delete and initialize
to
2. Does flash memory is normal?
save or Ii-view does
è N : change the Flash memory
not working
è Y : check the Flash memory controller(FPGA1)

Mysono 201 Section 4-2. Debug Mode
2. Debug Mode
2.1 Debug Menu
Debugger
MemoryChk KeyTest Biopsy Monitor PortChk ImgTunning
MemoryChk Connect the Memory test mode

KeyTest Connect the Keyboard test mode
Biopsy Connect the Biopsy setting mode
Monitor Connect the Monitor display test mode
PortChk Connect the CPU I/O port test mode
ImgTunning It is Reserved mode. Not in use.

2.2 Image Memory Debugger Menu
IMAGE MEMORY DEBUGGER
1) Read 1 page from SRAM

From Image Grabber SRAM of special address, read the data as the unit of 1page(512
bytes).
3 bytes write :1s t byte bit7 = 1 : cpu access, bit7=0 : system access
1s t byte bit5..3 not used
1s t byte bit2..0 address
2nd, 3rd byte address
ex1) From 800000 – 00000H, read 512 data.
ex2) From 870000 – 70000H, read 512 data.
2) Write 1 page to SRAM
On Image Grabber SRAM of special address, write the data as the unit of 1page.
4 bytes write : 1s t, 2nd, 3rd is same with reading data.
4th data increment
ex1) write the 512 data such as 80000001 – ffh, 00h, 01h, 02h, … .
ex2) write the 512data such as 80000002 – ffh, 01h, 03h, 05h, … .
3) DUMP RAM
CPU memory(ROM, RAM) area was read as the unit of 128 bytes.
RAM area is by a000h~bfffh.
ROM area is 0000h~ffffh except RAM area.
ex1) From 0000 – 0000h address, read 128 bytes data.
ex2) From a000 – a000h address, read 128 bytes data.
4)CLEAR RAM
After Clear CPU NVRAM, initialize the system.
After initialize, user must perform Erased All Flash certainly.
5) Read 1 page from FLASH
From Flash memory of special area, read data as unit of 1page.
ccXXYY :
1) cc is chip number, 01=1, chip, 02=2, chip, 04=smart media
2) XXY is block address(0~1023)
3) Y is page address(0~15)
ex1) 010000 – read the 0 page among the first flashe memory 0th black.
ex2) 02000a – read the a(10) page among the second flash memory.
ex3) 04000f – read the f(15) page among the smart media 0th block.
ex4) 010014 – read the 4th page among the first flash memory 1th block.

6) Write 1 page to FLASH

On Flash memory of special area, write data as the unit of 1page.
ccXXYYii :
1) ccXXYY is such as reading.
2) ii is increment value of writing data
.
7) Read 1 page from DRAM
Read data as the unit of 1page on special range of Cine DRAM.
ffXX :
1) ff means frame number, 0~31
2) XX means row address, 0~256
ex) Read row data in 0000 – 0 of frame
8) Write 1 page to DRAM
Write data as the unit of 1page on range of special in Cine DRAM.
ffXXii :
1) ffXX is such as read
2) ii is increment value of writing data
ex) 050002 – 5 번 frame, 0 번 row 에 2 씩 증가하는 data 를 write 함
9) Initialize FLASH
Initialize the flash memory. Not in use.
10) Erase all FLASH
Delete all data in flash memory. But remain the biopsy data.
11) HOST Chip Select
When choose the 014, 015 chip, HOST Chip Select is used.
XY :
X : 0 = first 014, 1 = second 014, 2 = 015
Y : 0 = internal memory, 1= external memory
ex1) 00 – It is for access to first 014 internal memory .
ex2) 20 – It is for access to 015 internal memory.
12) HOST Address Select
- Choose 014, 015 internal or external memory address.
ex) 12f4h : choose the 01f4h address
13) HOST Data Write
This function is to write data of 2byte on selected address.
ex) 1155h – Write 1155h data from Selected chip 12f4h address.
14) HOST Data Read
This function is to read data of 2bytes on selected address.
ex) dd77h – Read data of 2bytes from selected chip 12f4h address.
15) HOST Data Dump
This function is to read data of 128bytes from selected address.

16) HOST Halt mode off

This function is to return to real mode, If this function is not work, Press “R” key which
is short cut.
2.3 Keyboard Menu
KEYBOARD
It is Keyboard test mode. When press the special key, appear and flick the letter on pressed
key.
And In upper left, appear the scan code value applicable to the key. If user want to go out this
mode, press the ”y” button, next press the enter button.

2.4 BIOPSY Menu
BIOPSY
“ Addition sight which has the line”
It is Biopsy setting menu. Biopsy supply 3 type and every one biopsy take 3 biopsy line on the
screen. Middle-line is throughway of biopsy niddle and both side-line indicate a range of
allowable error on throughway of niddle. Biopsy line information is saved in flash memory.
Flash memory does not delete absolutely, unless user delete on purpose. Although some flash
memory was broken, biopsy line is working normal because save the same information at
three place on the flash memory.
When draw up a Biopsy line, It have to be applied to each 4 depth. When operate the
direction and inverter function, user must check that whether niddle follow biopsy line or not.
When Choose the Setup button, appear sub- menu, Press the biopsy button in the sub- menu.
There is Biopsy line on/off function in the biopsy menu. That function button is toggle key. If
biopsy line is on, it is not deleted absolutely without mode change condition.
2.5 MONITOR Menu
MONITOR
Cross Hat Circle Full H
“Addition 3 display mode”
Cross Hat Display overlay data as a checkered on the screen.

Circle Display overlay data as a circle on the screen.
Full H Display fill up the “H” letter on the screen.

2.6 8085 I /O DEBUGGER Menu
8085 I /O DEBUGGER
1) LOOPING READ I/O PORT

- Repeat reading the data on special CPU I/O.
2) LOOPING WRITE I/O PORT
- Repeat writing the data on special CPU I/O.
3) LOOPING WRITE/READ I/O PORT
- Repeat reading and writing the data on special CPU I/O.
4) READ I/O PORT ONCE
- Read data on special CPU I/O port, only one time.
5) WRITE I/O PORT ONCE
- Read data on special CPU I/O port, only one time.
6) READ RAM MEMORY
- Not in use.
7) WRITE TO RAM MEMORY
- Not in use.
8) OVL ++, X. OVL –
- Not in use.
9) READ RAM MEMORY
- Not in use.
10) SCANLINE FIX
- Print one scanline after fixed to change All scanline as one scanline.
11) SCANLINE NORMAL
- It is made normal scanline printed condition.
12) SET PARM2.
- Fix the writing value on the frame memory.
13) FM/WR COL ADDR
- Fix the column address on the frame memory.
14) FM/WR ROW ADDR.
- Fix the row address on the frame memory.
15) WRITE F/M STEP
- Not in use.
16) FILL F/M BANK0
- Fixed parameter value fill up on the Frame memory.

Mysono 201 Section 5-1. Assembling Diagram
1.Spare Parts Assembling Diagram

1.1 TFT LCD Monitor Replacement Method
screw
Figure1.1 Moving the Battery
Battery
1) Remove battery.(option)
2) To remove 6 screw on the cover body bottom, use “+” screwdriver.
screw
COVER BOTTOM
ARM
screw
Figure1.2 Moving the LCD monitor

3) To remove 6 screw on the COVER BOTTOM ARM, use “+” screwdriver.

4) To remove 6 screw on the LCD monitor cover, use ”+” screwdriver.
screw
CON1 ( 12-pin)
CN1 ( 12-pin )
5) Remove 4 screw on the LCD monitor.

6) Disconnect with CN1(12pin) on the LCD INVERT board and CON1(31 pin) on the LCD
main board.
7) Replace the LCD Display.

1.2 Key Matrix PCB Replacement Method
screw
screw
1) Remove battery on the cover body bottom.

2) Remove 6 screw on the cover body bottom.
3) When remove 2 screw on the cover body front, upper body cover is disconnected.
4) Disconnect Trackball & KEY MATRIX PCB J2 ( 8-pin flex circuit ).
5) Disconnect J5, J6 on the KEY MATRIX.
6) To remove 21 screw, use “+” screwdriver.
7) Key Matrix PCB Replacement.

J6
J5
J2
Figure 1.3 Removing the KEY MATRIX PCB
1.3 Trackball Replacement Method
screw
screw

1) Remove battery.
2) When remove 6 screw on the cover body bottom, upper body cover is disconnected.
J6 J5
J2
Trackball
4) Disconnect J5, J6 on the KEY MATRIX PCB.

5) Remove 21 screw, use “+” screwdriver.
6) Disconnect Trackball & KEY MATRIX PCB J2 ( 8-pin flex circuit ).
Trackball guard
Trackball
Trackball Wire Haness
Figure 1.4 Removing the Trackball

7) Trackball Replacement

1.4 PCB Boards Replacement
1.4.1 DSC Board Replacement Method
screw
screw
Video-
screw screw
Figure 1.5 Removing the Video-output B/D from DSC B/D

1) Remove battery.
2) When remove 2 screw on the cover body bottom, upper body cover is disconnected.
4) Remove 11 screw on the DSC BOARD and Disconnect Video-output B/D.
Ｊ１４
Kｎｏｂ
Figure 1.5.1 Removing the Video-output B/D from DSC B/D

5) Remove Knob.
6) Disconnect J14 ( 9-pin ) connector.
1.4.2 Front End Board Replacement Method
Ｊ１４（９－ＰＩＮ）
ＡＤＡＰＴＥＲ
Ｂ／Ｄ
ＳＣＲＥＷ
Figure 1.5.2 Removing the Adapter B/D from the Frend End B/D

1) For disconnecting, ADAPTER B/D, to remove 6 screw by “+” screwdriver.

2) For disconnecting, user pulled ADAPTER B/D.
PCB surpport
Cover-
shield-f/e
screw
Rear Front
J4 (50-pin)
PCB support
3) Remove 8 PCB support on the F/E board.

4) Disconnect the connector which coupled with J4(50-pin) on F/E board and Power
board.
5) Disconnect cover-shield-f/e.
6) Replace F/E B/D.

1.4.3 Power Board Replacement Method
J3 ( 2-pin )
Cover-shield-
power
PCB
1) Remove J3 (2-pin) on the POWER board.
2) Remove 7 PCB support.
3) After remove 13 screw, disconnect cover-shield-power.
4) Replace Power board.

Mysono 201 Section 5-2. Parts List
2. Parts List
2.1 Cover Body Bottom Assy Exp.
15
14
9
6 19
1
13
12
10
5
22
21
4
20

Table 2.1 Cover Body Bottom Assy Exp.
No. Part No. Description

1 215-M-108 COVER BODY BOTTOM
2 215-M179 COVER-BATTERY -Mysono201
3 262-M-001 KEY-S/W-POWER-Mysono201
4 BD-333-SPC Mysono201 SPC B/D
5 215-P-205 COVER-SHIELD-SPC-Mysono201
6 AY-333-POWER Mysono201 201 POWER ASSY
7 EL-HEX3*5 M3*20 SPACER
8 CAP-SMART -MEDISA-Mysono201
9 269-M-040 CAP-PRISM-LED2-Mysono201
10 AY-FAN-333-BACK Mysono201 FAN ASSY
11 AY-FAN-333-BACK Mysono201 FAN ASSY
12 313-T-046 CUSHION FANL
13 EL-HEXN3*5 M3*10 SPACER
14 BD-000-F/E Mysono201 F/E B/D
15 267-M-039 KNOB-ENCORDER-Mysono201
19 BD-333-ADAPTA Mysono201 ADAPTA B/D
20 311-R-149 RUBBER CAP1-Mysono201
23 EL-MS3*6A3A M3*5 SCREW
24 EL-MS3*6A3AWA M3*6 SCREW WITH WASHER

2.2 Power Assy Exp.
1
2
Table 2.2. POWER ASSY EXP
1 Power 333 Mysono201 Power

2 215-P198 Cover-shield-power-Mysono201
3 EL-MS3*6A3AWA M3*6 screw with washer

2.3 AY_FE_BOARD_EXP
2
7
3 5
8
5
Table 2.3 AY_FE_BOARD_EXP
1 BD-333-FE Board f/e Mysono201

2 215-P-182 Cover-shield-f/e1-Mysono201
3 215-P-183 Cover shield f/e2
4 215-P-203 Cover-shield-f/e3-Mysono
5 215-P-204 Cover-shield-f/e4-Mysono
6 312-Z-029 Gasket F/E
7 323-T-006 Insulator F/E
8 EL-MS3*5A3A M3*5 Screw

2.4 Adapter B/D Exp.
5
1
6
2
Table.2.4 ADAPTER B/D EXP

1 PCB-333-ADAP-0A Adapter board Mysono201
2 Berg 50*2 female
3 215-P-206A Cover shield adapt bd1 Mysono201
4 215-P-207 Cover shield adapt bd2 Mysono201
5 312-Z-028 Gasket adapt board Mysono201

2.5 Cover Assy Body Top Mysono201 Exp.
18
2
8 5
20
7 6 3
13 21
16
12
10
17
14 19
15
11
22

Table.2.5 Cover Assy Body Top Mysono201 Exp.

1 311-R-140 KEY S/W RUBBER 1 Mysono201
5 215-M-184 COVER BODY TOP SUB Mysono201
6 213-M-074 CASE LOWER GRID POINT
7 213-M-121 CASE SUPPORT GLIDE/P
10 PCB-333-KM-DA KEY METRIC BOARD Mysono201
11 257-L-011 HINGE TORQUE C Mysono201
12 257-M-186 COVER TOP ARM Mysono201
13 257-L-012 HINGE TORQUE L Mysono201
14 257-L-013 HINGE TORQUE R Mysono201
15 246-M-010 BUSHING TORQUE L/R
16 215-M-185 COVER BOOTOM ARM Mysono201
17 215-M-188 COVER LCD UPPER Mysono201
18 215-M-187 COVER LCD LOWER Mysono201
19 MNT -LCD/LP064V1 LCD TFT MNT Mysono201
20 228-Z-047 PLATE NAME Mysono201
21 254-Z-001 LOCK LATCH MAGNET LCD Mysono201
22 254-Z-002 LOCK LATCH MAGNET LCD Mysono201
23 323-T-007 INSULATOR LCD BOTTOM
26 EL-WDS3*6A3A 3*6 SCREW

2.6 SPC Board Assy Exp.
2
4
Table.2.6 SPC Board Assy Exp.
1 BD 333 SPC Board spc Mysono201
2 235-P-132 Bracket-connector-Mysono201
3 EL-HEX3*5 M3*5 Spacer

Mysono 201 Section 6-1. Specification
1.Specification
1.1 Technical Specification
Width: 255 mm
Height: 300 mm
Physical Dimensions
Depth: 90 mm
Weight: less than 4.0kg
2D real-time
Dual 2D real-time
Imaging modes
2D/M-mode
M-Mode
Gray Scale Internal 64 levels, External 256 levels
Channels 16 transmit channels
Dynamic transmit focusing, maximum of four points
Focusing (one point selectable)
Digital dynamic receive focusing (continuous)
Curved Linear Array
C2-5/60BD(CLA3.5MHz/60R/60D)
C4-7BD(CLA5.0MHz/40R/60D)
EC4-9/13CD(CLA6.5MHz/13R/120D)
Linear Array
L4-7CD(LA5.0MHz/65mm)
L5-9CD(LA7.5MHz/40mm)
L5-9/60CD(LA7.5MHz/60mm)
Probes
Reserved Probes
C4-9 / 10ED (Reserved)
C5-8BD (Reserved)
VE5-8ED (Reserved)
L2-5 / 120CD (Reserved)
LV4-7AD (Reserved)
LV5-9AD (Reserved)
Probe connection 1 probe connector
Monitor 6.4 inch LCD monitor
B/W Printer
Peripherals
VCR

Non-Interlaced B / W Monitor
VGA Monitor
VHS Monitor
HMD
Cine memory (maximum 32 frames)
Image Storage
Image Storage (maximum 50 frames)
Fetal, Abdominal, Pediatric, Small organ, Intra-vascular,
Application Peripheral-vascular, Muscular-skeletal, Cardiac, Trans-rectal,
Trans-vaginal
Measurement of various parameters
Obstetrical analysis:
Standard gestational age tables: BPD, HC, FL, AC, AD,
CRL, GS.
6 equations for fetal weight (Osaka University, Merz,
Calculation and
Shepard, Hadlock, Tokyo University 1, and Tokyo University
Quantification
2 method)
User-created tables
Cardiac analysis:
LV, AV, and MV,
Heart rate
Near, Far, Overall Gain control
Dynamic aperture
Dynamic apodization
Signal processing Dynamic range control (adjustable)
(Pre-processing) M-mode sweep speed control
Frame average Gamma -scale windowing
Image orientation (left/right and up/down)
White on black
Touch pad control of multiple calipers
Measurement B-mode: Distance, circumference, area, ellipse, volume .
M-mode: Velocity, time, slope

Coupling gel
Power cord
Power adaptor
Battery (Option)
Accessories RCA Jack
Video output cable
Carrying case
Operator’s manual
Smart Media (Option) (Reserved)
Operating: 700hPa to 1060hPa
Pressure Limits
Transmit & Storage: 700hPa to 1060hPa
Operating: 30% to 75%
Humidity Limits
Transmit & Storage: 20% to 90%
Operating: 10 O C ~ 35O C (recommended: 17 O C ~ 23O C)
Temperature Limits
Transmit & Storage: -25 O C ~ 60O C
Power adaptor Input: 100-240VAC, 1A, 50/60Hz
Electrical Power adaptor Output: DC15V, 4A
System Input: DC15V, 4A
Run-Time: Approx. 1.5 hour
Battery Recharge Time (System On): Approx. 5 hour
Recharge Time (System Off): Approx. 3 hour
System On without battery: No color
During recharge: Orange
LED display
Recharge completed: Yellow
System On without adaptor: Red
1.2 Safety Standard
l Classification:
Class I equipment with Type BF applied parts
Ordinary Equipment
Non-AP/APG
l Electromechanical safety standards met:
CSA C22.2 No.601.1, Canadian Standards Association, Medical Electrical Equipment
EN60601-1, Second Edition, including Amendments 1 and 2, European Norm, Medical
Electrical Equipment

EN60601-1-2, First Edition, European Norm, Collateral Standard, Electromagnetic
Compatibility
IEC61157: 1992, International Electrotechnical Commission, Requirements for the
declaration of the acoustic output of medical diagnostic ultrasonic equipment
UL 2601-1, Underwriters Laboratories, Medical Electrical Equipment

1.3 Range of measurement and accuracy
1.3.1 B mode range and accuracy
Accuracy
Measurement Type Range
(Whichever is greater)
Axial Distance 1 - 250 mm +/- 2% or +/- 2 mm
Lateral Distance 1 - 250 mm +/- 2% or +/- 2 mm
Diagonal Distance 1 - 250 mm +/- 2% or +/- 2 mm
Area 1 - 10,000 mm2 +/- 4% or 25mm2
Circumstance 3 - 1,000 mm +/- 3% or +/- 5 mm
Note:
The accuracy’s are using following equations:

Distance error (2% or 2mm) = Image Pixel error (1% or 1mm) + Hardware error (1% or 1mm)
Area error (4%)= Distance 1 x Distance 2
Circumference error (3% or 5mm)= Distance error (2% or 2mm) + Calculation precision (1% or
3mm)
Measurement accuracy is constrained by the cursor placement capability limit in additional to

the specifications in the above table
1.3.2 M mode range and accuracy
Accuracy
Measurement Type Range
(Whichever is greater)
Depth 1 - 250 mm +/- 2% or +/- 2 mm
Time 0.1 - 10.2 sec +/- 2% or 0.2 sec
Slope 1 - 10,000 mm /sec +/- 4 %
Note:
The accuracy’s are using following equations:

Distance error (2% or 2mm ) = Image Pixel error (1% or 1mm) + Hardware error (1% or 1mm)
Time error (2% or 0.2 sec )= Image Pixel error (1% or 0.1 sec) + Hardware error (1% or 0.1
sec)
Velocity error (4%)= Distance / Time
Measurement accuracy is constrained by the cursor placement capability limit in additional to

the specifications in the above table

MEDISON CO., LTD QUALITY CONTROL
MYSONO201 COMPATIBILITY MATRIX
REVISION STATUS REV

INITIAL RELEASE 001
Correcting probe information (2000.12.07) 002
DC No : 01-201-001 DSC B/D revision-up to 1A (2001.01.26) 003
DC No : 00-201-010 Power circuit revision-up to 01 (2000.12.26) 004
DC No : 01-201-004 Power circuit revision-up to 02 (2001.02.15) 005
DOCUMENT NUMBER
MSF-QA-801-CM201
APPROVALS
Originator Manager
Y.J.CHOI S.H.KOH
Please, refer to HOMEPAGE for details: HTTP://WWW.MYSONO.COM
DISTRIBUTION STATEMENT
THIS DOCUMENT CONTAINS CONFENTIAL INFORMATION WHICH IS PROPRETARY TO MEDISON CO., LTD. NEITHER THE DOCUMENT NOR THE INFORMATION
CONTAINED THEREIN SHOULD BE DISCLOSED OR REPRODUCED IN WHOLE OR IN PART WITHOUT CONSENT OF MEDISON CO., LTD. AND IF DESIGN CHANGE
OCCURS AFTER THE DATE OF LAST UPDATE, THIS DOCUMENT WILL BE EXPIRATION OF VALIDITY.
Last updated : 01-02-15 1/5 CM-M201-005

MEDISON CO., LTD. QUALITY CONTROL
MYSONO201 COMPATIBILITY MATRIX

S/W VER.
COMPANY CONFIDENTIAL
(VET) 1.01.00V
1.01.00H
1.00.00
1.00.01
1.00.02
Initial applied
Classification NAME PART NAME Rev HARDWARE COMMENTS S/N of System
BOARD ADAPTER BD-333-ADAPTER 0A Initial release(2000.11.11)
BOARD DSC BD-333-DSC 0A Initial release(2000.11.11)

1A DC No:01-201-002 (2001.01.26)
A/W change related to EMI, stability, VGA load
BOARD FRONT END BD-333-F/E F Initial release(2000.11.11)

0A DC No: (2000.11.25)
Official product for release(Sale)
0B DC No: 00-201-005(2000.12.06)
Stablilize TX pulse and delete pull down resistor
BOARD KEY MATRIX BD-333-KEY/M 0A Initial release(2000.11.11)
BOARD POWER AY-333-POWER 00 Initial release(2000.11.11)

01 DC No: 00-201-010(2000.12.26)
Correct noise and assembly problem
02 DC No: 01-201-004(2001.02.15)
Allowable current limit increased (R65,87:10->4.7)
BOARD SPC BD-333-SPC 1A Initial release(2000.11.11)
Last updated : 01-02-15 2/5 CM-M201-005

S/W VER.
(VET) 1.01.00V
1.01.00H
1.00.00
1.00.01
1.00.02
Initial applied
Rev
Classification NAME PART NAME HARDWARE COMMENTS S/N of System
EXT POWER ADAPTER AY-333-ADAPTER 0A Initial release(2000.11.11)
EXT LI-ION BATTERY BT-10.8V-4.8A Initial release(2000.11.11)

SAEHAN BATTERY SH-202
EXT LCD MNT-LCD-LP064V1 0A Initial release(2000.11.11)
EXT SMART MEDIA OPT-333-S/M 1A Initial release(2000.11.11)

RESERVED
(PC-FLASH/PATH) Flash Disk(2M, 4M, 8M, 16M)
EXT BAG 213-Z-125A 00 Initial release(2000.11.11)
EXT GLIDE POINT 351-C-003A 00 Initial release(2000.11.11)
Last updated : 01-02-15 3/5 CM-M201-005

S/W VER.
(VET) 1.01.00V
1.01.00H
1.00.00
1.00.01
1.00.02
Application
REV
Classification NAME Biopsy Kit (H) : For Human, (V) : For Veterinary Probe Image
PROBE L4-7CD BPL-50/65 (H) OB, Abdomen, Pediatric
PB-MYL4-7CD (V) Equine tendon, Bovine back fat, Small ani abdomen
L5-9CD BPL-75 (H) Breast/Thyroid/Testes, C Artery, Noenatal, PV
PB-MYL5-9CD (V) Equine tendon, Bovine back fat, Small ani abdomen
L5-9/60CD BPL-50/65 (H) Breast/Thyroid/Neck/Testes, C Artery, Pediatric
PB-MYL5-9/60CD (V) Equine tendon, Bovine back fat, Small ani abdomen
L2-5/120CD
PB-MYL2-5/120CD (V) Porchine pregnancy detection, Abdomen
L2-5/150CD
PB-MYL2-5/150CD (V) Porchine back fat and Lean percent
L2-5/170CD
PB-MYL2-5/170CD (V) Bovine back fat and marbling score detection
LV4-7AD
PB-MYLV4-7AD (V) Large animal pregnancy detection and OB/GYN
LV5-9AD
PB-MYLV5-9AD (V) Large animal pregnancy detection and OB/GYN
C5-8BD
PB-MYC5-8BD (V) Small animal abdomen
C2-5/60BD BPC-35 (H) OB, GYN, Third Trimester OB, Abdomen
PB-MYC2-5/60BD reserved (V) Large animal abdomen
C4-7BD BPC-50 (H) OB, GYN, Abdomen, Breast/Thyoid/Testes, Ped
PB-MYC4-7BD (V) Small animal abdomen
EC4-9/13CD BPC-65-E/C (H) OB, GYN, Third Trimester OB, Abdomen
PB-MYEC4-9/13CD
C4-9/10ED
PB-MYC4-9/10ED (V) Small animal cardiac and Abdomen
VE5-8BD
PB-MYVE5-8BD (V) Large animal OPU
Last updated : 01-02-15 4/5 CM-M201-005

S/W VER.
(VET) 1.01.00V
1.01.00H
1.00.00
1.00.01
1.00.02
Initial applied
Classification Version Major Change Description S/N of System
PERIPHERAL B/W PRINTER SONY 890 MD OPT-PRT-SONY
Mitubish P91E OPT-PRT-P91E
Mitubish P91W OPT-PRT-P91W
Mitubish M90U OPT-PRT-MITS-1
Mitubish M90E OPT-PRT-MITS-2
HMD HMD-I/GASSES Virtual I glasses

Don't use it in PAL system
VCR VCR VCR RECORDING AVAILABLE
EXTERNAL MONITOR VGA MONITOR *

B/W MONITOR *
MANUAL REV.
S/W Initial release for sale
1.00.00 (2000.11.10) MAN-mysono201-E(D)10000
Bugs patched
1.00.01 (2000.11.15) MAN-mysono201-E(D)10000
CHG key in M mode, LMP reset in ID, Message of Setup store and freeze,
Bug patched
1.00.02 (2000.11.18) MAN-mysono201-E(D)10000
An error in Doing autorun after deleting a stored image
Bugs patched
1.01.00 (2000.01.08) MAN-mysono201-E(D)10100
Errors : NTSC/PAL settiing, Saving changed Depth in setup mode
1.01.00 only for VET Initial release for VET version
MAN-mysono201V-E(D)10100
(2000.01.08) Patient ID, GA table, Bodymark, Cardiac measurement are different from Human use
Last updated : 01-02-15 5/5 CM-M201-005

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2.5 peripheral unit (Option)

3.2 Electrical safety

3.2.1 Protection of equipment

3.2.2 Battery safety

3.3 Physical safety

3.4 Maintenance and cleaning

3.4.1.2 Disinfection and Sterilization

3.4.2 Biopsy guide adapter and Needle guide

3.4.2.1 Stainless biopsy guide cleaning

3.4.2.2 Stainless biopsy guide sterilization

3.4.2.3 Plastic biopsy guide cleaning

3.4.2.4 Plastic biopsy guide sterilization

3.4.3 The surface of equipment

4.2 Battery setting and removing

4.3 Battery charging and discharging

4.4 System power ON / OFF

4.5 Using AC adapter

Service Manual Published by Customer Service Department

2.2 Block Diagram

2.3 Signal Definition

2.3.1 CPLD Signal Definition

2.3.2 Connector signals between DSC and FE

2.3.3 Connector signals between Power and FE

2.3.4 Connector signals between FE Adapter and FE

2.3.5 Connector signals between FE Adapter and SPC(System Probe Connector)

2.3.6 Connector signals between SPC(System Probe Connector) and Probe

2.4 Scanline Definition

2.4.1 Normal Mode

2.4.2 Synthetic Mode

2.5 Pulser vs Elements

2.6 Specific Description

2.6.1 TGC Amp

2.6.4 Beamfoming IC MCB014A

2.7 PCB Board Lay Out

2.7.1 F/E Top Side

2.7.2 F/E Bottom Side

2.8 Timing Chart

2.8.1 Normal TX Focusing

2.8.2 Synthetic TX Focusing

2.8.3 Control Timing

2.9 Wave Form

3.2. Block Diagram

3.3 Signal Definition

3.4 Specification explain

3.4.1 B/W Data Receiving & FM storing Part

3.4.1.1 Mid Processor (MGA015)3.4 Specification explain

Service Manual Published by Customer Service Department

3.4.1.4 FM controller (MGA001)

3.4.2 Frame Memory & Cine Memory Flash Memory Part

3.4.2.1 Frame Memory (VRAM)

3.4.2.2 Cine Memory (DRAM)

3.4.2.3 Flash Memory

3.4.2.4 Memory Path by mode

3.4.2.5 Scanline Masking Window

3.4.3 CRD, Graybar, Overlay Post Memory Part

3.4.3.4 Overlay Control Scheme

3.4.3.5 Post Memory

3.4.4 Non interlace Output Display Path part

3.4.4.3.1 74ACT715 control