IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 55, NO.

1, JANUARY 2008 133

Analysis of Fourth-Order DC–DC Converters:

A Flow Graph Approach
Mummadi Veerachary, Senior Member, IEEE

Abstract—The signal flow graph (SFG) nonlinear modeling fourth-order converter for power factor correction has been
approach is well known for modeling dc–dc converters and it reported [4], [5]. Although higher order increases complexity
is a powerful analysis tool for higher order converter systems. in the dynamics, they have several desired features such as:
Modeling of several specific fourth-order dc–dc converter circuits
have been reported using conventional state-space averaging. Par- 1) step-up/down conversion with continuous input and output
ticular emphasis has been given, so far, only to arrive at any current. This is a desirable feature for high frequency converters
of the large, small-signal (SS) and steady-state models but not as this reduces the EMI filtering requirement; 2) since the
a generalized one. This paper gives the generalized SFG model fourth-order topologies uses two inductors, it is possible to
of the fourth-order dc–dc converter topology that is useful for apply the ripple steering phenomena [6], [7], thereby the con-
generating different types of fourth-order dc–dc converter circuits
unified models. Further, it is shown that the deduction of large, verter draws almost constant input current; 3) wide variety of
SS and steady-state models from these unified SFGs is easy and conversion ratios with single switch topology; and 4) simplicity
straightforward. All possible fourth-order dc–dc converter circuits in the control, etc.
from its generalized topology have been identified and an analysis Modeling of a few individual fourth-order converter circuits
of a few converter circuits is given here for illustration of the have been addressed in part by several authors. However, there
proposed modeling method. Large-signal (LS) models are devel-
oped for different topology configurations and are programmed in is a need to develop a generalized model of the fourth-order
SIMULINK simulator. LS responses against supply and load dis- topologies from which it should be possible to predetermine a
turbances are obtained. Experimental observations are provided complete system behavior. State-space averaging method is the
to validate the proposed modeling method. most popular approach used for modeling of the dc–dc switch-
Index Terms—Fourth-order converters, large-signal (LS) ing converters [8]. However, this method is tedious, especially
model, modeling, signal flow graph (SFG), small-signal (SS) when the converter circuit contains a large number of elements
model. [9]. Furthermore, the linearized models do not predict the large-
signal (LS) stability information, and are only sufficient to
I. I NTRODUCTION predict small-signal (SS) stability [10]–[15]. LS models are
proposed, but these models do not provide a generalized model

T HE SWITCH-MODE dc–dc converter has evolved into an

essential component in electronic equipment [1], [2] and
finding widespread application in computers, battery chargers,
that will predict the complete behavior of the circuit. To over-
come some of the problems previously mentioned, a signal flow
graph (SFG) nonlinear modeling method was developed for the
solar cell-based power converters used in space power con- PWM converters [16]–[19]. The advantages of this method are:
ditioning systems, etc. The wide variety of converter topolo- 1) it converts the switching converter, two or multistate, into a
gies have been developed by different researchers to cater to unified dynamic model; 2) from the unified model, it is possible
predefined needs. These include simple basic converters such to derive large, SS and steady-state models with minimum
as buck, boost and buck–boost, isolated converters, complex mathematical manipulations; 3) it provides the designer an easy
converters such as cascade, interleaved converters, etc. A sys- way of getting LS global behavior when it is combined with the
tematic procedure and classification of pulsewidth-modulation TUTSIM and/or SIMULINK simulator; and 4) it is possible to
(PWM) dc–dc converters is discussed in [3]. This paper identi- derive various relationships among the circuit variables without
fies the basic fundamental converter cell and then derives var- any difficulty, particularly it provides a simple method and
ious possible topologies. It is devoted mainly for two and four less mathematical manipulations in arriving at the SS transfer
switch topologies with two or three energy storage elements. functions of the switch-mode dc–dc converter. However, the
The exhaustive treatment given is useful for identifying the SFG method so far applies only for specific converters like
nature of conversion, suitability for the given application, etc. buck, boost and buck–boost converters, etc. Furthermore, there
Among the various possibilities the two switch, two inductor are no prescribed guidelines while drawing the flow graphs for
and one capacitor topologies are finding major application the dc–dc converters. This paper presents a generalized analysis
in the area of switch-mode converters. These circuit configu- of fourth-order switch-mode dc–dc converter topologies using
rations belong to the fourth-order topologies. Application of SFG theory.

Manuscript received January 29, 2005; revised August 8, 2007.

The author is with the Department of Electrical Engineering, Indian Insti- II. G ENERAL R ULES FOR D RAWING SFG S
tute of Technology Delhi, New Delhi 110016, India (e-mail: mvchary@ee.
iitd.ernet.in). The SFG is a pictorial representation of flow of signals
Digital Object Identifier 10.1109/TIE.2007.907677 through a network and is helpful in visualizing the operation of

0278-0046/$25.00 © 2008 IEEE

134 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 55, NO. 1, JANUARY 2008

a network [21]. For any linear circuit, we can draw a different

number of SFGs depending on the choice of variables. How-
ever, the variables of choice should include the known quan-
tities and the desired quantities. The following are the general
rules useful for drawing the SFGs of the dc–dc converter sys-
tem. 1) Formulate the linearly independent system of equations
for the given switch-mode converter so that this equation set
is consistent and completely defines the nature of the system.
2) The sequence of nodes is the sequence of elements, inductor
or capacitor, appearing in the circuit. Improper sequence of
nodes results in a graph in which the number of closed loops
Fig. 1. Block diagram of the generalized fourth-order converter topology.
and forward paths are different from the true graph. 3) Draw
the SFG’s voltage node first and then current node should
be indicated for inductive elements. For capacitive elements, the fourth-order converters, is developed to avoid unnecessary
current node first and then the voltage node should follow. mathematical work and complexity involved in the model de-
4) Individual loops must be considered while writing down velopment of each and every converter circuit derived from the
the circuit loop voltage equations using Kirchhoff voltage law. general topology.
5) Shunt branch currents must be expressed in terms of other
currents at junction points using the Kirchhoff current law.
A. Generalized SFG of the Fourth-Order DC–DC
6) The source current node is a sink node and receives signals
Converter Topology
from all those inductors that have a common terminal with the
source. The path transmittance of “1” or switching function de- In this section, a generalized SFG method for the analysis
pends on the boost or buck mode of operation of the converter. of the fourth-order dc–dc converters operating in a continuous
7) The number of switching functions, (k1 , k2 , . . . , kj , where current mode (CCM) is discussed. The analysis of the system
j is no. of operating modes = 2, 3, . . . N ), depends on the no. is carried out under the following assumptions: 1) switching
of operating modes of the circuit. 8) In the simplified SFG, elements of the converter are assumed to be ideal; 2) the
the closed loops mainly form with the inductive and capacitive equivalent series resistance of the capacitance C1 and stray
branch nodes. The above general rules are valid for all the capacitances are neglected; 3) passive components (R, L, C)
dc–dc converters including positive output and negative output are assumed to be linear time-invariant; and 4) the two inductor
converters. currents are assumed to be continuous.
To generate the USFG for the fourth order converter, first we
assume, at random, that the element-1 is inductor-1, element-2
III. D EVELOPMENT OF U NIFIED SFG (USFG) M ODEL
is switch, element-3 is diode, element-4 is capacitor, element-5
FOR THE F OURTH -O RDER C ONVERTER
is inductor-2. This sequence generates a useful switch-mode
The switch-mode fourth-order converter mainly consists of topology. Although the above element sequence results in the
active, passive switch (diode), two inductors and a capacitor boost converter with load LC-filter, the procedure given in
in addition to load capacitance. The generalized representation the following lines is a generalized one and is valid for all
is shown in Fig. 1. Depending on the position of the above possible element sequence in addition to the one given above.
elements, different fourth-order converter topologies can be With single switch topology, if the switch-mode converter is
generated. Although many different circuit topologies can be operating in CCM of operation, it generates two linear circuits:
generated, by shifting the position of the circuit elements, one for switch-on period and the other for switch-off period.
only a few of them are physically realizable and are useful During the time 0 < t ≤ tON , mode-1, the switch S; and during
for the power conversion process. All possible topologies are tON < t ≤ T , mode-2, the diodes D are, respectively, conduct-
generated but only the topologies that are useful for switch- ing and thus generating two different subcircuits. The converter
mode conversion are discussed here. The number of physically switches between these two subcircuits (which are linear) and
realizable converter circuits with: 1) element-1 as switch: 3; a linear system theory can be extended. Considering the switch
2) element-2 as switch: 3; 3) element-3 as switch: 2; and S operation as reference, SFGs GON , GOFF are generated for
4) element-4 as switch: 1. The respective topologies in each ON , OFF-state subcircuits, respectively, sharing common nodes
case correspondingly are: a) ZETA converter, buck–boost con- and part of the branches. A systematic algorithm, given in
verter with LC output filter, buck converter with LC output Section II, is used while drawing the SFGs, GON and GOFF .
filter; b) SEPIC converter, CUK converter, boost converter with The two SFGs GON , GOFF are combined to form a simplified
LC output filter; c) buck–boost converter with LC input filter, SFG. While merging the two SFGs, GON and GOFF , into a
buck converter with LC input filter; and d) boost converter with single graph G, some of the branches exist in the two graphs
LC input filter. This section describes the USFG development and some may not. Branches that exist in GON but not in
of fourth-order converters. In general case many different types GOFF are replaced by k1 branches, and the branches that exist
of converter topologies, as discussed above, are possible and in GOFF but not in GON are replaced by k2 branches. The
the flow graph development to each and every topology is a resulting graph topology can be mathematically written as G =
tedious task. A generalized SFG model, useful for analyzing all (k1 GON + k2 GOFF ), where k1 , k2 are the switching functions
VEERACHARY: ANALYSIS OF FOURTH-ORDER DC–DC CONVERTERS: A FLOW GRAPH APPROACH 135

satisfying the relationship k1 + k2 = 1, whose values depend

on the switching times, defined by the following expressions:


1, for 0 < t ≤ tON
k1 = (1)
0, for tON < t ≤ T


0, for 0 < t ≤ tON
k2 = (2)
1, for tON < t ≤ T.

Employing the above switching functions and the two SFGs, Fig. 2. USFG model of the fourth-order boost converter with output filter.
GON and GOFF , a USFG is generated as shown in Fig. 2. Using
a similar procedure, one more unified graph is generated for
the switching sequence: element-1 is inductor-1, element-2 is
capacitor-1, element-3 is switch, element-4 is inductor-2, and
element-5 is diode. This sequence results into a buck–boost
converter with LC input filter and the corresponding graph is
shown in Fig. 3. A similar procedure, not given here to avoid
repetitiveness, is adopted for other elements sequence to draw
the USFG of the corresponding topologies. Close observation Fig. 3. USFG model of the fourth-order buck–boost converter with input filter.
of all these different topologies’ flow graphs, generated from
Fig. 1, reveals a few important points that lead to the merging
of all graphs into a single generalized graph valid for a dif-
ferent element sequence of the fourth-order converters: 1) all
physically realizable dc–dc converter circuits, generated from
fourth-order topology, will generate connected graphs having
identical nodes; 2) two nodes are required for representation of
any electrical element, active or passive, voltage and current
relationship. The total number of nodes in the unified graph
of the fourth-order topology is (2N + 2), where N is no. of
energy storage elements. In this case, there are four energy
storage elements and hence 8 nodes required for these ele-
ments, the remaining two nodes are required for the source;
3) connectivity of various nodes mainly decided by the ele- Fig. 4. Generalized SFG model of the fourth-order dc–dc converter topology.
ments position, element-1 to 5; and 4) the basic or primitive
graph for all physically realizable dc–dc converter circuits, tances are 0, ±1, ±k1 , ±k2 , where “0” branch transmittance
obtained from the fourth-order topology, is the same but the indicates that there will not be any connection between the
branches may have either constant transmittance or a switching two nodes. Branch transmittance is “k1 ” when switch conducts,
function. The nature of branch transmittance, constant trans- branch transmittance is “k2 ” when diode conducts. The variable
mittance or a switching function is basically decided by the transmittances, B1 to B8 , exists in all the converter circuits
position of elements-1 to 5. derived from the fourth-order topology. The remaining trans-
Since the energy storage elements are not going to change, mittances (B9 , B10 ), (B11 , B12 ) appears only in the specific
the number of nodes in the generalized graph is fixed. The converter circuits ZETA and SEPIC, respectively. For ready
voltage, current nodes and branch transmittance connecting reference, the branch transmittances, B1 to B12 , are listed in
these nodes define each energy storage element. As a general Table I. Using this table together with generalized SFG given
rule, assign the location and notation of the nodes according to in Fig. 4, a USFG of any physically realizable dc–dc converter
the sequence in which a particular element comes first while circuit derived from the fourth-order topology can easily be
traversing from source to load. To ensure simplified layout, drawn.
the final resulting graph should not have any overlapping or Justification for the Table I entries can easily be done from
crossover of branches. Once this location and notation is fixed, the switch position in the fourth-order converter topology,
even if the element position is changed in the actual converter shown in Fig. 1. For example, for a buck–boost converter with
circuit, the individual nodes position is not going to change. The input filter, the incoming branches of nodes v2 , vo become
only change is that, the branches connecting different element switching branches, B4 = −k1 , B6 = k2 , due to the presence
nodes will be different, which mainly depends on element of a switch and diode, respectively. Consider another topology,
position. Employing the steps given above and in Section II a 3: A boost converter with input filter. In this topology, L1 ,
generalized graph is drawn with fixed as well as variable branch C1 and L2 forms a T -network on the supply side and this
transmittances. The fixed transmittances are indicated in the is followed by the switch, diode, capacitor C2 and load. The
USFG, shown in Fig. 4, and the variable transmittances value load node points v0 , i0 receives signal from the inductor node
B1 to B12 depends on the position of elements in the fourth- points v2 , i2 only when the diode is conducting. As already
order topology. The parameter values for these branch transmit- mentioned in the preceding paragraph, when the diode conducts
136 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 55, NO. 1, JANUARY 2008

TABLE I C. SS Model
VARIABLE BRANCH TRANSMITTANCES
An SS SFG model for any of the fourth-order converter
system can be obtained from its USFG by simply replacing the
switching branches, “k1 ” and “k2 ,” with their corresponding SS
equivalent models. SS equivalents are derived for the switching
branches “k1 ,” “k2 ” in the following lines. For the switching
branch “k” the input and output signals are related as

y(t) = x(t)di (t), i = 1, 2. (4)

Let X, Y , D be the operating points and x̂(t), ŷ(t), dˆ1 (t)

are the corresponding SS perturbations satisfying x(t) = X +
x̂(t), y(t) = Y + ŷ(t), d1 (t) = D1 + dˆ1 (t), d2 (t) = D2 −
dˆ2 (t). Inserting these relationships in (4) results in the follow-
ing equation:
 
Y + ŷ(t) = (X + x̂(t)) D1 + dˆ1 (t) (5)
 
then the switching function “k2 ” will be the connecting branch Y + ŷ(t) = (X + x̂(t)) D2 − dˆ2 (t) . (6)
transmittance. From the generalized graph, the branches con-
necting the node variables (i2 → i0 ), (v2 → v0 ), respectively, Substituting the condition for operating point, Y = XDi ,
are B5 , B6 . We can verify this from Table I, where “k2 ” is the and on the assumption of neglecting second-order perturba-
branch transmittance of B5 , B6 , which is in agreement with tions, x̂(t)dˆ1 (t), x̂(t)dˆ2 (t), the SS switching equations for k1 ,
our discussion above. Once the USFG of any specific fourth- k2 branches, respectively, are
order converter is known, then developing large, SS and steady-
state models is a matter of replacing the switching branches ŷ(t) = D1 x̂(t) + X dˆ1 (t) (7)
with their corresponding equivalent large, SS and steady-state
ŷ(t) = D2 x̂(t) − X dˆ2 (t) (8)
branches. A systematic procedure for developing the large, SS
and steady-state models from this USFG is illustrated in the where D1 , D2 are the duty ratios control functions of switch-
following sections. on and switch-off modes, respectively. The above equations
define the graphical representation of SS switching branches.
Upon substitution of the above SS switch branches in the USFG
B. LS and Steady-State Models and on simplification, an SS SFG can be generated. This SS
model, can be used to derive all the SS performance transfer
Assuming the filter corner frequency is much smaller [18],
functions between any two nodes for frequencies up to about
[19] than the switching frequency, the effective signals carried
half of the switching frequency (fs ). This generalized treatment
at the outputs of k1 , k2 switching branches having average
is valid for all the fourth-order converter circuits generated
values d1 (t), d2 (t), respectively, are
from Fig. 1. To deduce large, SS and steady-state models
from the USFG, some illustrative examples are considered in
y(t) = x(t)di (t) (3) the following sections. However, developing the SFGs for the
remaining converter circuits should be quite similar to the one
presented here.
where i = 1, 2. Equation (3) indicates that the output signal
y(t) from the switching branches k1 , k2 are the product of the
input signal and the duty ratio control signal d1 (t) or d2 (t). IV. SS, LS AND S TEADY -S TATE M ODELS OF
From these equations the LS models for switching branches F OURTH -O RDER C ONVERTER T OPOLOGIES
are developed. Incorporating these LS models for the switching
A. SS Models
branches in the graph G results in an LS SFG. This LS model
can be directly entered into any of the system level simulator SS transfer functions are essentially needed to study the SS
such as TUTSIM or SIMULINK to study its LS behavior. From behavior and to design the controller. The easiness and simplic-
the LS switching branch models, the steady-state switching ity involved in the SFG method, while finding the SS transfer
branch models are derived. In the steady-state, “k1 ” branch functions, is demonstrated by considering some fourth-order
will have a transmittance of “D1 ” and “k2 ” branch will have converters. As already mentioned in Section III, depending
a transmittance of “D2 .” Simplifying the LS flow graph with on the switch position, the converter topologies are going to
the above steady-state switching branch models and setting change. For example, consider one topology for each switch
complex frequency s → 0, a steady-state model is obtained. position of Fig. 1(b). Namely: 1) element-1: switch → buck–
From this SFG, various steady-state relations can easily be boost converter with load output filter; 2) element-2: switch →
derived. SEPIC converter; 3) element-3: switch → buck converter with
VEERACHARY: ANALYSIS OF FOURTH-ORDER DC–DC CONVERTERS: A FLOW GRAPH APPROACH 137

two forward paths (v̂g −v̂1 − î1 − îC1 −v̂C1 −v̂2 − î2 − î0 −v̂0 ),
(v̂g − v̂1 − î1 − î0 − v̂0 ), exists between v̂g , v̂0 , and their path
transmittances, respectively, are

td1 d22 td2

p1 = ; p2 =
C1 s(sL1 + r1 )(sL2 + r2 ) (sL1 + r1 )

where t = R(1 + src C2 )/[1 + sC2 (R + rc )]. Six loops

formed by nodes (v̂1 − î1 − îC1 − v̂C1 − v̂1 ), (v̂2 − î2 − î0 −
v̂0 − v̂2 ), (v̂1 − î1 − îC1 − v̂C1 − v̂2 − iˆ2 − î0 − v̂0 − v̂1 ),
(îC1 − v̂C1 − v̂2 − iˆ2 − îC1 ), (v̂1 − î1 − î0 − v̂0 − v̂1 ),
Fig. 5. SS SFG model of the fourth-order SEPIC converter.
(v̂1 − iˆ1 − iˆ0 − v̂0 − v̂2 − î2 − îC1 − v̂C1 − v̂1 ) exists and
their loop transmittances are given in the following:

−d22
l1 =
C1 s(sL1 + r1 )
−td22
l2 =
(sL1 + r1 )
−d21
l4 =
C1 s(sL2 + r2 )

Fig. 6. SS SFG model of the boost converter with input filter.

−td1 d32
l3 = l6 =
C1 s(sL1 + r1 )(sL2 + r2 )
input filter; and 4) element-4: switch → boost converter with
−td22
input filter. l5 = .
(sL1 + r1 )
For the above converters, by substituting the branch trans-
mittances (given in Table I) in the generalized fourth-order
In this SS flow graph, two nontouching loop pairs exist,
converter graph (given in Fig. 4), USFGs are deduced. Upon
which are (l1 , l2 ), (l4 , l5 ). The determinant of the graph is
substitution of the SS switching branches defined by (7) and
(8) in the USFGs, an extra branch with node “d” ˆ is going to

6
be introduced. Combining all such nodes to one single node re- ∆=1− lj + (l1 l2 + l4 l5 ). (9)
ˆ branches to one common place. While
quires moving all the “d” j=1
moving these branches in the signal flow direction, the branch
transmittance is going to multiply with that path transmittance. Applying Mason’s gain formula [16], the input-to-output (also
On the other hand, if the movement of the branch is opposite called audio susceptibility), which describes the input-to-output
to the signal flow direction, then the branch transmittance is noise transmission is
going to divide by the corresponding path transmittance. Taking 
these points into consideration, a simplification is made and the v̂0 (s)  pj ∆j
Mv (s) = = (10)
final SS SFGs of the above converters are generated. Because v̂g (s) d(s)=0
ˆ ∆
of the limitation on the number of figures here, SS SFG models  
are shown (Figs. 5 and 6) only for the SEPIC and boost v̂0 (s) te1 d2 d1 d2 + C1 e2 s + d21
= (11)
converter with output filter. Derivation of SS transfer functions v̂g (s) [e1 et + te2 d42 ]
is given below for the SEPIC converter. Due to the limitation
on the number of pages, detailed derivation of transfer func- where ∆1 = 1, ∆2 = (1 − l4 ), e = e1 e2 e3 , e1 = (sL1 + r1 ),
tions for other converters is not given here. However, for the e2 = (sL2 + r2 ), e3 = sC1 , et = [e + e2 d22 + 2te2 d22 C1 s +
remaining converters, the final transfer functions are tabulated 2td1 d32 + e1 d21 + td21 d22 ]. Adopting a similar procedure, various
for ready reference and these can easily be obtained with other transfer functions can be obtained. The open-loop input
simple mathematical manipulations as is used for the SEPIC impedance obtained as
converter.   
To demonstrate the suitability and simplicity of the proposed v̂g (s)  e1 et + te2 d42
Zi (s) =  = . (12)
SFG method, the following four commonly used transfer func- îg (s) d(s)=0 e1 [e + te2 e3 d22 + e1 d21 ]
tions’ detailed derivation is given below. In a given graph to
find the gain, using Mason’s gain expression between any two
The open-loop output impedance is
nodes requires identifying the forward paths and loops. Any
discrepancy in identifying the forward paths, individual and   
v̂0 (s)  e1 e + e1 d21 + e2 d22
nontouching loops will ultimately lead to improper determi- Z0 (s) = = . (13)
nant of the graph “∆.” In the SEPIC converter SFG (Fig. 5), î0 (s) d(s)=0 [e1 et + te2 d42 ]
138 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 55, NO. 1, JANUARY 2008

TABLE II TABLE V
SS TRANSFER FUNCTIONS OF THE BUCK STEADY-STATE EXPRESSIONS OF THE FOURTH-ORDER CONVERTERS
CONVERTER WITH INPUT FILTER

sponding duty ratios. Accordingly, the LS models of fourth-

order converter topologies can be obtained easily from the
USFG (Fig. 4) by substituting the branch transmittances given
TABLE III
in Table I. For the steady-state models, the switching function
SS TRANSFER FUNCTIONS OF THE BOOST “k” in Table I should read as “D.”
CONVERTER WITH INPUT FILTER These models can be directly entered into any of the system
level simulator to study its LS behavior. The detailed simulation
studies have been carried out using the LS SFG models devel-
oped above and these are given in the results and discussion
section. From the LS switching branch models, the steady-
state switching branch models are derived. In the steady-state,
“k1 ” branch will have a transmittance of “D1 ” and “k2 ” branch
will have a transmittance of “D2 .” Simplifying the LS flow
graphs with the above steady-state switching branch models
and setting complex frequency s → 0, steady-state models are
obtained. Adapting a similar procedure, using Mason’s gain
TABLE IV formula as outlined in Section IV-A, various relationships
SS TRANSFER FUNCTIONS OF THE BUCK–BOOST among the state variables are obtained and they are given in
CONVERTER WITH OUTPUT FILTER Table V for ready reference. The performance characteristics
tabulated in Tables II–V are derived from the SFG method
and are in agreement with those obtained from state-space
averaging method. Although the method demonstrated here for
CCM operation, it can easily be extended to DCM operation by
simply introducing mode-3 operation in the analysis.

V. R ESULTS AND D ISCUSSION

Comprehensive simulation studies were made to investigate
the SFG modeling of fourth-order converter topologies. To ver-
ify the generalized SFG of fourth-order topologies and the SFG
The control-to-output transfer function is models developed from it for different fourth-order converters,
  
v̂0 (s) 
several simulations have been carried out on the LS SFGs.
ak e1 e + e1 d21 + e2 d22
Tp (s) =  = (14) However, for illustration, some results are given here for: 1)
ˆ 
d(s) [e1 et + te2 d42 ] buck–boost converter with output filter; 2) SEPIC converter; 3)
vg (s)=0
buck converter with input filter; and 4) boost converter with
where ak = ak = d2 (V0 + VC1 )/e2 [1 + (d1 d2 /e1 e3 )] − (I1 + input filter. The parameters chosen for these converters are
I2 )[1 + (d1 d2 /e2 e3 )]. Adopting the same procedure given given in Table VI.
above, we can easily obtain at the SS transfer functions of To illustrate the LS response analysis of the aforementioned
the remaining fourth-order converter topologies and the final converter systems, the LS SFG models developed from their
transfer functions are tabulated in Tables II–IV. corresponding USFGs are programmed in the SIMULINK sim-
ulator. Several simulations were obtained, but for illustration,
some important results at a duty ratio of D = 0.5 are given
B. LS and Steady-State Models
here for two cases: 1) load disturbance; and 2) supply voltage
Adopting the procedure outlined in Section III, the LS SFG disturbance. However, due to the limitation on the number
models can easily be obtained. These are identical to USFGs of figures, the simulation and experimental load disturbance
except that the switching functions are replaced by the corre- results are given for buck–boost converter with output filter and
VEERACHARY: ANALYSIS OF FOURTH-ORDER DC–DC CONVERTERS: A FLOW GRAPH APPROACH 139

TABLE VI
CONVERTER PARAMETERS

Fig. 9. Dynamic response of the buck converter with input filter (SFG).

Fig. 7. Dynamic response of the buck–boost converter with output

filter (SFG).

Fig. 10. Dynamic response of the boost converter with input filter (SFG).

the next paragraph, closely match with those obtained from the
SFG analysis method.
To verify the proposed modeling method, experimental pro-
totype fourth-order converter topologies with parameter values
given above have been built and measurements were taken from
the prototypes. The semiconductor devices used are MOSFET:
IRF530, Diode: MUR820. Inductor, capacitor and load values
are chosen accordingly as in simulation studies. An Interna-
tional Rectifier IR2110 gate driver drives the MOSFET switch-
Fig. 8. Dynamic response of the SEPIC converter (SFG).
ing device. The converters’ dynamic responses against: 1) load
disturbance; and 2) supply voltage disturbances were measured
source voltage disturbance results for the remaining converters. and they are given in Figs. 11–14. Fig. 11 shows the buck–boost
In the ideal case, the load voltage is almost constant against converter, Fig. 12 shows the SEPIC converter, Fig. 13 for
load disturbance. But in practice, the increase in load slightly the buck converter and Fig. 14 is for the boost converter.
decreases the load voltage on account of increased voltage drop Comparing all these experimental LS response studies with the
in the converter switching devices and parasitic elements. This corresponding simulated results, given in Figs. 7–10, it can be
phenomenon is observed in all the converters. Converter load noted that the developed models are able to predetermine the
voltage depends on the duty ratio and input supply voltage. converter behavior. However, in the simulation during the in-
For a given duty ratio the converter load voltage is going to termediate dynamics period, the response shows an oscillatory
change whenever there is any change in the supply voltage, nature, and reaches the final steady-state values. This behavior
but it undergoes dynamics before it settles to the new steady- is mainly due to the variable step size used in the simulator
state value. This is verified for all the converters by taking equation solver and also depends on the converter parameters.
the corresponding LS models and the results are plotted in As expected, in all converters, the measured load voltage is less
Figs. 7–10. To validate the SFG analysis results, experimental than the simulated value by 1 to 2 V. This is because of the
LS responses were also obtained and these results, given in voltage drop in the converter parasitic components.
140 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 55, NO. 1, JANUARY 2008

Fig. 11. Dynamic response of the buck–boost converter with output filter.
Fig. 13. Dynamic response of the buck converter with input filter.

Fig. 12. Dynamic response of the SEPIC converter.

Fig. 14. Dynamic response of the boost converter with input filter.
Experimental results are slightly different from the simulated
values. This difference is due to: 1) the difficulty of accurate output filter, SEPIC converter, buck converter with input filter,
representation of the nonidealities of the converter in the sim- boost converter with input filter models are deduced from the
ulations; 2) use of built-in differential equation solvers and generalized SFG model and then small, LS and steady-state
variable step size limitations; 3) errors in the measuring instru- performance expressions were determined. Models of fourth-
ments, if any; and 4) in simulation, the step disturbance (source order dc–dc converters lead to simple graphical circuits that
or load) created is instantaneous while in the experimentation, are very much suitable for analysis and simulation. Analytical
the step disturbances were created manually, which may not be results, obtained from the proposed modeling method, were val-
a sudden step as that created in the simulation profile. This is idated with the experimental results. Further, the performance
one of the main reasons that reflects the dynamic response of expressions are in agreement to those obtained from the state-
the system. space averaging method, thus validating the proposed modeling
method.
VI. C ONCLUSION
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and analysis of interleaved dc–dc parallel converters,” Int. J. Electron., the Institution of Engineers India. He is currently serving as an Associate
vol. 88, no. 9, pp. 1015–1033, 2001. Editor of the IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS and IEEE
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graphs,” in Proc. IEEE IECON, 2006, pp. 5307–5312. Who’s Who in Science and Engineering 2003.