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    Tutorial Sheet 5

    Uploaded by

    Shashank Singh
    This document contains 9 problems related to the design and analysis of CMOS inverters. The problems cover topics such as calculating threshold voltage based on transistor parameters, determining transistor sizes to meet timing specifications, and analyzing voltage transfer characteristics and delay times.

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    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd

    Tutorial Sheet 5

    Uploaded by

    Shashank Singh
    441 views2 pages
    This document contains 9 problems related to the design and analysis of CMOS inverters. The problems cover topics such as calculating threshold voltage based on transistor parameters, determining transistor sizes to meet timing specifications, and analyzing voltage transfer characteristics and delay times.

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    This document contains 9 problems related to the design and analysis of CMOS inverters. The problems cover topics such as calculating threshold voltage based on transistor parameters, determining transistor sizes to meet timing specifications, and analyzing voltage transfer characteristics and delay times.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    441 views2 pages

    Tutorial Sheet 5

    Uploaded by

    Shashank Singh
    This document contains 9 problems related to the design and analysis of CMOS inverters. The problems cover topics such as calculating threshold voltage based on transistor parameters, determining transistor sizes to meet timing specifications, and analyzing voltage transfer characteristics and delay times.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    of 2

    Tutorial Sheet – 5

    1. Consider a CMOS inverter with the given parameters- kn’=140 µA/V2, kp’=60
    µA/V2, Vto, n=0.7 V, Vto, p= - 0.7 V, VDD=3 V.
    (a) If the design is ideal and symmetrical, then find out the ratio of (W/L)p and
    (W/L)n.
    (b) Take the case when (W/L)p = (W/L)n, then find out the inverter threshold
    voltage.

    2. A CMOS inverter is built in a process where kn’=100 µA/V2, kp’=42 µA/V2,


    Vto, n=0.7 V, Vto, p= - 0.8 V and a power supply of VDD=3.3 V is used. Calculate
    the inverter threshold voltage Vth if (W/L)n=10 and (W/L)p=14.

    3. Find the ratio kn/kp needed to obtain a CMOS inverter threshold voltage of
    Vth=1.3 V with a power supply of 3 V. Assume that Vto, n=0.6 V and Vto, p= -
    0.82 V. What would be the relative device sizes if the mobility values are
    related by µn=2.2µp?

    4. Consider a resistive-load inverter circuit with VDD=5 V, kn’= 20 µA/V2, Vt0=


    0.8 V, RL= 200 KΩ, and W/L = 2. Calculate the critical voltages-VOL, VOH, VIL,
    VIH on the VTC and find the noise margins of the circuit.

    5. Design a resistive-load inverter with R=1 KΩ, such that VOL = 0.6 V. The
    enhancement-type nMOS driver transistor has the following parameters:
    kn’=22 µA/V2, Vto, n=1 V, γ=0.2 V1/2, VDD=5 V.
    (a) Determine the required aspect ratio, W/L.
    (b) Determine VIL, VIH.
    (c) Determine noise margins NML and NMH.

    6. Consider the CMOS inverter circuit with VDD = 3.3 V. The I-V characteristics
    of the nMOS transistor are specified as follows: when VGS = 3.3 V, the drain
    current reaches its saturation level IDSAT = 2 mA for VDS≥ 2.5 V. Assume
    that the input signal applied to the gate is a step pulse that switches
    instantaneously from 0 V to 3.3 V. Using the data above, calculate the delay
    time necessary for the output to fall from its initial value of 3.3V to 1.65V,
    assuming an output load capacitance of 300 fF.
    7. For the CMOS inverter with a power supply voltage of VDD = 5 V, determine
    the fall time tfall which is defined as the time elapsed between the time point
    at which Vout = VDD*90% = 4.5 V and the time point at which Vout = VDD
    *10% = 0.5 V. Use both the average-current method and the differential
    equation method for calculating tfall ,Assume output load capacitance is 1 pF.
    The nMOS transistor parameters are given as
    µnCox = 20 µA/V2
    (W/L)n = 10
    Vt,n = 1.0 V

    8. Consider a CMOS inverter, with the following device parameters:


    Vt0,n = 0.8 V
    Vt0,p= -1.0 V
    Wmin =1.2µm
    Design this CMOS inverter by determining the channel widths Wn and Wp
    of the nMOS and pMOS transistors, to meet the following performance
    specifications. Vth = 1.5 V for VDD = 3 V
    Propagation delay times tPHL ≤ 0.2 ns and tPLH ≤ 0.15 ns,
    A falling delay of 0.35 ns for an output transition from 2 V to 0.5 V,
    Assuming a combined output load capacitance of 300fF and ideal step input.

    9. Consider a CMOS inverter, with the following device parameters:


    µnCox = 120 µA/V2 Vt0,n = 0.8 V
    Vt0,p=-1.0 V µpCox = 120 µA/V2
    The power supply voltage is VDD = 5 V. Both transistors have a channel
    length of Ln= Lp= 1µm. The total output load capacitance of this circuit is
    Cout = 2 pF, which is independent of transistor dimensions.

    (a) Determine the channel width of the nMOS and the pMOS transistors
    such that the switching threshold voltage is equal to 2.2 V and the output
    rise time is trise = 5ns.
    (b) Calculate the average propagation delay time tp.

    (c) How do the switching threshold Vth and the delay times change if
    the power supply voltage is dropped from 5 V to 3.3 V. Provide an
    interpretation of the results.

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