EE-231 Electronics I: Engr. Dr. Hadeed Ahmed Sher

EE-231 Electronics I
Engr. Dr. Hadeed Ahmed Sher
Ghulam Ishaq Khan Institute of Engineering Sciences and Technology, TOPI 23460
[email protected]
May 6, 2018
Engr. Dr. Hadeed Ahmed Sher (FEE, GIKI) Week 14 Resources May 6, 2018 1 / 19
1 Field Effect Transistor (FET)
Introduction
Junction field effect transistor (JFET)
Transfer characteristics
2 JFET biasing
Fixed biasing
Field Effect Transistor (FET) Introduction
Introduction
They are just like the BJT.

It is usually a three terminal device. However, occasionally a fourth
terminal is provided by the manufacturer in some kinds of FET
(enhancement type MOSFET).
The three terminals for an FET are called Gate, Source and Drain.
An FET is a unipolr device becuase current conduction in it results from
the flow of only one of the two kinds of charge carriers i.e holes or
electrons.
It is a voltage controlled device i.e. externally applied voltage controls the
amount of current.
It is generally classified in two types.
Metal oxide semiconductor field effect transistor (MOSFET)
Field Effect Transistor (FET) Junction field effect transistor (JFET)
Figure shows the basic structure of an N channel JFET.
A bar of n type material is used such that two p type bars are embedded
on each side.
The p type regions are electrically connected and only one common
connection is provided to the user. This connection is called the gate
terminal (G). One end of the n type bar is called drain (D) and the other
end has a terminal called source (S).
The area in between the two p type bars is called channel.

The transistor shown on slide4 is therefore an n-channel JFET.
If the p and n material are interchanged then the JFET is called a
p-channel JFET.
Figure shows the basic JFET with the terminals connected to the dc
supply.
When a voltage is applied between drain and source such that the drain in
positive with respect to the source then current flows through the n
material from the source to the drain.
The resistance of n type material is the only resistance for this flow of
current.
In designing a JFET circuit the gate terminal is made reverse biased by

applying voltage between gate and the source.
The reverse bias creates a pair of depletion layer expanded inside the
n-channel.
The channel is more lightly doped than the gate, therefore the expansion
of depletion layer is more into the n-channel. The expansion of depletion
layer depends on the magnitude of the reverse biased voltage (VGS ).
If (VGS )is made negative the depletion layer expands and therefore
decreases the flow of current ID from drain to source.
If (VGS ) is made zero and (VDS ) is increased slightly above 0, then (ID )
increases proportionally as shown below.
This is because the resistance of n-channel is constant and hence the

current ID obays ohm’s law.
If VDS is increased further, then depletion layer begin to form in the
channel as shown. The shape of depletion layer is broader near the drain
and narrow near the source.

It is because ID creates a voltage drop along the length of channel. Near
the drain terminal the channel voltage is nearly equal to VDS therefore a
large reverse biasing voltage is available between n-channel and p-gate.
The voltage is reduced as we move towards the source therefore the
depletion layer becomes narrower.

If VDS is increased to a large value such that the depletion region meet at
a point near the drain then such condition is called pinch-off.
Because it is the Drain to source voltage that reverse bias the gate to
channel junction the pinch off voltage is considered a negative value. An
absolute value of Vp is used in the figure. At the Vp the current saturates
and is called saturation current (IDSS ) i.e. drain to source current with
gate shorted.
When VDS exceeds —VP — the current continues to flow. It is because it

is self regulating.
Suppose that an increase in VDS cause ID to increase then there would be
an increased voltage drop that expand the depletion layer further and
reduce the current. As the current is ceased to flow at pinch off, the
depletion layer would shrink and current flow would resume. Therefore,
the ID is self regulated at a constant value IDSS .

A typical values are Vp and IDSS are -4V and 12mA.
Now if VGS =-1V then depletion region is penetrated into the channel. If
VDS is increased above 0, the current ID begins to increase linearly as
shown below.
The slope however for VGS =-1V is not as steep as that for VGS =0V¿ It si
because the channel is narrower and therefore offers more resistance. For
the case when VGS =-1V the pinch off is now reached at 3V because there
is already a -1V reverse bias between the gate and the channel.

Now if VGS =-2V then depletion region is penetrated more into the channel
and the pinch off is reached at VDS =2V.
The increase in VGS causes the pinch-off condition to occur at smaller
values of VDS and a smaller saturation current results.
The dashed line which is parabolic joins the point on each curve where
pinch-off occurs. Moreover, the value of VDS on parabola is called VDS(sat) .
VDS(sat) =VGS − Vp . The equation of parabola is

2
VDS(sat)

ID = IDSS (1)
Vp
In the figure shown on slide 13 the region to the right of the parabola is
called pinch-off region and this is the region in which amplification
happens. It is also called the active region or the saturation region.
The region to the left of parabola is called ohmic region or the voltage
controlled resistance region. It is also called the triode region. In this
region the resistance between drain to source is controlled by VGS . The
FET acts like a voltage controlled resistor in this region.
At VGS =VP the current ID =0. Therefore, the pinch off voltage is also
called the gate to source cutoff voltage.

The JFET offers a high input impedance and this is because the gate to
source is reverse biased.The only current that can flow in a reverse biased
condition is the small leakage current. Therefore, a very small current is
drawn from the signal source driving the gate.
If the gate to source is made positive then this would drastically decreases
the gate to source resistance and in most cases this would not be tolerable
to a signal source driving an FET.
Field Effect Transistor (FET) Transfer characteristics
The JFET transfer characteristics are a plot of output current (ID versus
the input voltage VGS at constant output voltage VDS .
Draw a vertical line on the drain characteristics and note the values of ID
for each intersection. Plotting these values with respect to the gate to
source voltage results in transfer characteristic.
Field Effect Transistor (FET) Transfer characteristics
Note that equal increments in the values of VGS on the drain

characteristics(∆VGS = 1V ) do not produce equally spaced lines and that
is why the transfer characteristics is a non-linear curve.
Note that the intercepts of these transfer characteristics are IDSS on y axis
and Vp on the x axis.
The characteristic curve can be expressed in terms of
VGS 2

ID = IDSS 1 − (2)
Vp
Using the above equation when VGS =0 then ID = IDSS . Similarly, when
VGS = Vp then ID =0.
The transfer characteristics are often called square-law characteristics.
JFET biasing Fixed biasing
Fixed biasing
Like BJT, FET also requires biasing for amplification applications.
Under common source configuration (source common to both the input
and output) the input voltage is VGS and the output voltage is VDS . The
bias circuit must set quiescent values (Q point)for VDS and ID .Figure
below shows one such method called as fixed bias circuit for an n-channel
JFET.
Two power supplies are used. VDD is connected to drain through a resistor
RD and VGS is connected to the gate terminal.
JFET biasing Fixed biasing
Fixed biasing
In this method the gate to source voltage is fixed by the constant voltage
applied across the gate to source terminals. Applying KVL around the
outer loop.
VDS = VDD − ID RD (3)

VDS is a positive quantity for an n-channel JFET. The Above equation can
be rearranged as
1 VD D
ID = − VDS + (4)
RD RD
The above equation is called the dc load line equation and it can be
plotted on the drain characteristics to determine the Q-point. Note that to
ensure FET operation at Q-point the VDS must be greater than Vp − VGS .
The values of IDSS and Vp vary widely among JFETs of a given type.
Under a change in these parameters the fixed bias is not a stable circuit.

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EE-231 Electronics I

Engr. Dr. Hadeed Ahmed Sher

They are just like the BJT.

Junction field effect transistor (JFET)

Figure shows the basic structure of an N channel JFET.

Junction field effect transistor (JFET)

The area in between the two p type bars is called channel.

Junction field effect transistor (JFET)

Junction field effect transistor (JFET)

In designing a JFET circuit the gate terminal is made reverse biased by

Junction field effect transistor (JFET)

This is because the resistance of n-channel is constant and hence the

Junction field effect transistor (JFET)

Junction field effect transistor (JFET)

Junction field effect transistor (JFET)

When VDS exceeds —VP — the current continues to flow. It is because it

Junction field effect transistor (JFET)

Junction field effect transistor (JFET)

Junction field effect transistor (JFET)

VDS(sat) =VGS − Vp . The equation of parabola is

Junction field effect transistor (JFET)

Note that equal increments in the values of VGS on the drain

VDS = VDD − ID RD (3)

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