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RTL8192CE-GR

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SINGLE-CHIP IEEE 802.11b/g/n 2T2R WLAN
CONTROLLER w/PCI EXPRESS INTERFACE
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DATASHEET
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Rev. 0.1
29 October 2009
Track ID:
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Realtek Semiconductor Corp.

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No. 2, Innovation Road II, Hsinchu Science Park, Hsinchu 300, Taiwan
Tel.: +886-3-578-0211. Fax: +886-3-577-6047
www.realtek.com
 RTL8192CE
Datasheet

COPYRIGHT
© 2009 Realtek Semiconductor Corp. All rights reserved. No part of this document may be reproduced,
transmitted, transcribed, stored in a retrieval system, or translated into any language in any form or by any
means without the written permission of Realtek Semiconductor Corp.

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DISCLAIMER
Realtek provides this document “as is”, without warranty of any kind, neither expressed nor implied,
including, but not limited to, the particular purpose. Realtek may make improvements and/or changes in this
document or in the product described in this document at any time. This document could include technical

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inaccuracies or typographical errors.

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TRADEMARKS
Realtek is a trademark of Realtek Semiconductor Corporation. Other names mentioned in this document are
trademarks/registered trademarks of their respective owners.
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USING THIS DOCUMENT
This document is intended for the software engineer’s reference and provides detailed programming
information.
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Though every effort has been made to ensure that this document is current and accurate, more information
may have become available subsequent to the production of this guide. In that event, please contact your
Realtek representative for additional information that may help in the development process.
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REVISION HISTORY
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Revision Release Date Summary

0.1 2009/11/2 Preliminary release.
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 RTL8192CE
Datasheet

Table of Contents
1. GENERAL DESCRIPTION ..............................................................................................................................................1

2. FEATURES .........................................................................................................................................................................3

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3. APPLICATION DIAGRAMS ...........................................................................................................................................5

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3.1. 11N COMPATIBLE SINGLE-BAND 2X2 RF APPLICATION ...............................................................................................5
4. PIN ASSIGNMENTS..........................................................................................................................................................6
4.1. PACKAGE IDENTIFICATION ...........................................................................................................................................7

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5. PIN DESCRIPTIONS.........................................................................................................................................................7
5.1. PCI EXPRESS TRANSCEIVER INTERFACE ......................................................................................................................7
5.2. EEPROM INTERFACE ..................................................................................................................................................7
5.3. POWER PINS .................................................................................................................................................................8
5.4. RF INTERFACE .............................................................................................................................................................8

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5.5. LED INTERFACE ..........................................................................................................................................................9
5.6. CLOCK AND OTHER PINS ............................................................................................................................................10
6. ELECTRICAL AND THERMAL CHARACTERISTICS............................................................................................11
6.1. TEMPERATURE LIMIT RATINGS ..................................................................................................................................11
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6.2. DC CHARACTERISTICS ...............................................................................................................................................11
7. MECHANICAL DIMENSIONS......................................................................................................................................12
7.1. MECHANICAL DIMENSIONS NOTES .............................................................................................................................13
8. ORDERING INFORMATION........................................................................................................................................14
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List of Tables
TABLE 1. PCI EXPRESS TRANSCEIVER INTERFACE ........................................................................................................................7
TABLE 2. EEPROM INTERFACE ....................................................................................................................................................7
TABLE 3. POWER PINS ...................................................................................................................................................................8

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TABLE 4. RF INTERFACE ...............................................................................................................................................................8
TABLE 5. LED INTERFACE.............................................................................................................................................................9
TABLE 6. CLOCK AND OTHER PINS ..............................................................................................................................................10

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TABLE 7. TEMPERATURE LIMIT RATINGS ....................................................................................................................................11
TABLE 8. DC CHARACTERISTICS .................................................................................................................................................11
TABLE 9. ORDERING INFORMATION .............................................................................................................................................14

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List of Figures
FIGURE 1. 11N COMPATIBLE SINGLE-BAND 2X2 SOLUTION－RTL8192CE-GR (11N 2X2 MAC/BB/RF + 2 PAS) .......................5
FIGURE 2. PIN ASSIGNMENTS .........................................................................................................................................................6
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Datasheet

1. General Description
The Realtek RTL8192CE is a highly integrated single-chip MIMO (Multiple In, Multiple Out) Wireless
LAN (WLAN) solution for the wireless high throughput 802.11n specification. It combines a MAC, a 2T2R
capable baseband, and RF in a single chip. The RTL8192CE provides a complete solution for a high

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throughput performance wireless client.

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The RTL8192CE baseband implements Multiple Input, Multiple Output (MIMO) Orthogonal Frequency
Division Multiplexing (OFDM) with 2 transmit and 2 receive paths (2T2R) and is compatible with the
IEEE 802.11n specification. Features include two spatial streams transmission, short guard interval (GI) of

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400ns, spatial spreading, and transmission over 20MHz and 40MHz bandwidth. Moreover, RTL8192CE
provides one spatial stream space-time block code (STBC) to extend the range of transmission. At the
receiver, extended range and good minimum sensitivity is achieved by having receiver diversity up to 2
antennas. As the recipient, the RTL8192CE also supports explicit sounding packet feedback that helps

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senders with beamforming capability. With 2 independent RF blocks, the RTL8192CE can perform fast
roaming without link interruption. RP
For legacy compatibility, direct sequence spread spectrum (DSSS), complementary code keying (CCK) and
OFDM baseband processing are included to support all IEEE 802.11b and 802.11g data rates. Differential
phase shift keying modulation schemes, DBPSK and DQPSK with data scrambling capability, are available
along with complementary code keying to provide the data rates of 1, 2, 5.5 and 11Mbps with long or short
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preamble. The high speed FFT/IFFT paths, combined with BPSK, QPSK, 16QAM, and 64QAM
modulation of the individual subcarriers and rate compatible punctured convolutional coding with coding
rate of 1/2, 2/3, 3/4, and 5/6, provides the maximum data rate of 54Mbps and 300Mbps for IEEE 802.11g
and 802.11n MIMO OFDM respectively.
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The RTL8192CE builds in an enhanced signal detector, an adaptive frequency domain equalizer, and a
soft-decision Viterbi decoder to alleviate the severe multi-path effects and mutual interference in the
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reception of multiple streams. For better detection quality, receive diversity with maximal-ratio-combine
(MRC) applying up to 2 receive paths are implemented. Robust interference detection and suppression are
provided to protect against bluetooth, cordless phone, and microwave oven. Receive vector diversity for
multi-stream application is implemented for efficient utilization of MIMO channel. Efficient IQ-imbalance,
DC offset, phase noise, frequency offset and timing offset compensations are provided for the radio
frequency front-end impairments. Selectable digital transmit and receiver FIR filters are provided to meet
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transmit spectrum mask requirements and to reject adjacent channel interference, respectively.
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Datasheet
The RTL8192CE supports fast receiver automatic gain control (AGC) with synchronous and asynchronous
control loops among antennas, antenna diversity functions, and adaptive transmit power control function to
obtain the better performance in the analog portions of the transceiver.

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The RTL8192SCE MAC supports 802.11e for multimedia applications, 802.11i for security, and 802.11n
for enhanced MAC protocol efficiency. Using packet aggregation techniques such as A-MPDU with BA

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and A-MSDU, protocol efficiency is significantly improved. Power saving mechanisms such as U-APSD,
APSD, and MIMO power saving reduces the power wasted during idle time, and compensates for the extra
power required to transmit MIMO OFDM. The RTL8192CE provides simple legacy and 20MHz/40MHz
co-existence mechanisms to ensure backward and network compatibility.

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2. Features
General MAC Features

 64-pin QFN  Frame aggregation for increased MAC

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efficiency (A-MSDU, A-MPDU)
 CMOS MAC, Baseband MIMO PHY, and

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RF in a single chip for IEEE 802.11b/g/n  Low latency immediate High-Throughput
compatible WLAN Block Acknowledgement (HT-BA)

 Complete 802.11n MIMO solution for  Long NAV for media reservation with
2.4GHz band CF-End for NAV release

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 2x2 MIMO technology for extended  PHY-level spoofing to enhance legacy
reception robustness and exceptional compatibility
throughput

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 MIMO power saving mechanism
 Maximum PHY data rate up to 150Mbps
using 20MHz bandwidth, 300Mbps using  Channel management and co-existence
40MHz bandwidth
 Multiple BSSID feature allows the
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 Compatible with 802.11n specification RTL8192CE to assume multiple MAC
identities when used as a wireless bridge
 Backward compatible with 802.11b/g
devices while operating at 802.11n data rates  Supports Wake-On-WLAN via Magic Packet
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and Wake-up frame
Host Interface
 Transmit Opportunity (TXOP) Short
 Complies with PCI Express Base Inter-Frame Space (SIFS) bursting for higher
Specification Revision 1.1 multimedia bandwidth
Standards Supported Peripheral Interfaces
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 IEEE 802.11e QoS Enhancement (WMM,  General Purpose Input/Output (10 pins)
WMM-SA Client mode)
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 4-wire EEPROM control interface (93C46)

 IEEE 802.11h TPC, Spectrum Measurement
 Three configurable LED pins
 IEEE 802.11k Radio Resource Measurement
 Configurable Bluetooth Coexistence
 IEEE 802.11i (WPA, WPA2). Open, shared Interface
key, and pair-wise key authentication
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services PHY Features

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 Cisco Compatible Extensions (CCX) for  IEEE 802.11n MIMO OFDM

WLAN devices
 Two Transmit and Two Receive path (2T2R)
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Datasheet
 20MHz and 40MHz bandwidth transmission  OFDM receive diversity with MRC using up
to 2 receive paths. Switch diversity used for
 Short Guard Interval (400ns) DSSS/CCK.
 One spatial stream STBC transmission for  Hardware antenna diversity
extended coverage

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 Selectable digital transmit and receiver FIR
 Sounding packet filters

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 DSSS with DBPSK and DQPSK, CCK  Programmable scaling in transmitter and
modulation with long and short preamble receiver to trade quantization noise against
increased probability of clipping
 OFDM with BPSK, QPSK, 16QAM, and

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64QAM modulation. Convolutional Coding  Fast receiver Automatic Gain Control
Rate: 1/2, 2/3, 3/4, and 5/6 (AGC).
 Maximum data rate 54Mbps in 802.11g and  On-chip ADC and DAC

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300Mbps in 802.11n
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3. Application Diagrams
3.1. 11n Compatible Single-Band 2x2 RF Application

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RTL8192CE
NV Memory

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RX I/Q Ext Interface

ADC
Tx/Rx

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2.4GHz 2.4GHz
Matching PA MAC PCI Express
AntennaB Circuit Transceiver Configuration
Control and Host
Memory Interface
Tx/Rx 2.4GHz

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2.4GHz

DAC
Matching Transceiver
PA
AntennaA Circuit
TX I /Q

Baseband
SPS/LDO (PHY)
Regulators
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3.3V 40MHz
Crystal
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Figure 1. 11n Compatible Single-Band 2x2 Solution－RTL8192CE-GR (11n 2x2 MAC/BB/RF + 2 PAs)
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4. Pin Assignments

LED1 / ANT_SEL_N

LED0 / ANT_SEL_P
GPIO2 / BT_STATE

GPIO0 / WL_ACT
GPIO3 / BT_PRI

GPIO1 / WL_RX

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CK_BT_40M

TRSWN[1]

TRSWP[1]
VD12A

VD15A

VD33A

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RETX
NC

XO

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48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
PDn 49 32 VD33A

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WAKEn 50 31 TX2G_PAON[1]
CLKREQn 51 30 TX2G_PAOP[1]
PERSTn 52 29 RX2G_IP[1]
VD12D 28 RX2G_IN[1]

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VD15D 54 27 VD33A
HSON 55 26 VD15A
HSOP 56 25 PAPE[1]
REFCLK_N 57
RP 24 RX2G_IN[0]
REFCLK_P 58 23 RX2G_IP[0]
HSIN 59
RTL8192CE 22 VD15A
HSIP 60 LLLLLLL 21 TX2G_PAOP[0]
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GND 61 TXXXV 20 TX2G_PAON[0]
VD12A 62 65 GND (Exposed Pad) 19 VD33A
NC 63 18 TRSWP[0]
NC 64 17 PAPE[0]
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
EEPROMSEL / EESK
GPIO4

GPIO5

GPIO7 / EEDI
GPIO6 / EEDO
LX

EECS
GND

VD12D
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VD33D

VD33A

TSSI_0
GPIO9

GPIO8 / TRSWN[0] / LED2

GPIO10
VD33A
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Datasheet

4.1. Package Identification

Green package is indicated by a ‘G’ in the location marked ‘T’ in Figure 2.

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5. Pin Descriptions

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The following signal type codes are used in the tables:

I: Input O: Output

T/S: Tri-State bi-directional input/output pin S/T/S: Sustained Tri-State

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O/D: Open Drain P: Power pin

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5.1. PCI Express Transceiver Interface
Table 1. PCI Express Transceiver Interface
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Symbol Type Pin No Description
HSIN/HSIP I 59/60 PCI Express Receive Differential Pair
HSON/HSOP O 55/56 PCI Express Transmit Differential Pair
REFCLK_P/R I 57/58 PCI Express Differential Reference Clock Source: 100MHz ± 300ppm
EFCLK_N
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CLKREQn O 51 Reference Clock Request Signal

This signal is used by the RTL8192CE-GR to request starting of the PCI
Express reference clock
WAKEn O/D 50 Power Management Event: Open drain, active low
Used to reactivate the PCI Express slot’s main power rails and reference clocks.
PERSTn I 52 PCI Express Reset Signal: Active low
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When the PERSTB is asserted at power-on state, the RTL8192CE-GR returns

to a pre-defined reset state and is ready for initialization and configuration
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after the de-assertion of the PERSTB.

5.2. EEPROM Interface

Table 2. EEPROM Interface
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Symbol Type Pin No Description

EESK O 14 EESK in 93C46 Programming or Auto-Load Mode
EEDI O 13 EEDI in 93C46 Programming or Auto-Load Mode
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EEDO IO 12 EEDO in 93C46 Programming or Auto-Load Mode

EECS O 15 EEPROM Chip Select

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 RTL8192CE
Datasheet

5.3. Power Pins

Table 3. Power Pins
Symbol Type Pin No Description
LX P 7 Switching Regulator Output

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VD33A P 1, 6, 19, 27, 32, 37 VDD 3.3V for Analog
VD33D P 5 VDD 3.3V for Digital

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VD15A P 22, 26, 39 VDD 1.5V for Analog
VD15D P 54 VDD 1.5V for Digital
VD12A P 40,62 Analog 1.2V Regulator Output
VD12D P 9, 53 Digital 1.2V Regulator Output

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GND P 8, 61 Ground
REXT P 38 24k (1%) Precision Resistor for Bandgap

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5.4. RF Interface
Table 4. RF Interface
Symbol Type Pin No Description
TRSWN[0] O 4
RP Transmit/Receive Path Select 0
Shared with LED2, can be selected by control register
PAPE[0] O 17 2.4GHz Transmit Power Amplifier Power Enable 0
TRSWP[0] O 18 Transmit/Receive Path Select 0
TX2G_ON[0] O 20 RF TX0 Negative Signal
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TX2G_OP[0] O 21 RF TX0 Positive Signal

RX2G_IP[0] I 23 RF RX0 Positive Signal
RX2G_IN[0] I 24 RF RX0 Negative Signal
PAPE[1] O 25 2.4GHz Transmit Power Amplifier Power Enable 1
RX2G_IN[1] I 28 RF RX1 Negative Signal
RX2G_IP[1] I 29 RF RX1 Positive Signal
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TX2G_OP[1] O 30 RF TX1 Positive Signal

TX2G_ON[1] O 31 RF TX1 Negative Signal
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TRSWP[1] O 33 Transmit/Receive Path Select 1

TRSWN[1] O 34 Transmit/Receive Path Select 1
ANT_SEL_P O 35 Antenna Control Positive Signal
Shared with LED0, can be selected by control register
ANT_SEL_N O 36 Antenna Control Negative Signal
Shared with LED1, can be selected by control register
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5.5. LED Interface

Table 5. LED Interface
Symbol Type Pin No Description
LED0 O 35 LED Pins (Active Low)
Shared with ANT_SEL_P, can be selected by control register

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LED1 O 36 LED Pins (Active Low)
Shared with ANT_SEL_N, can be selected by control register

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LED2 O 4 LED Pins (Active Low)
Shared with TRSWN[0] or GPIO8, can be selected by control register

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5.6. Clock and Other Pins

Table 6. Clock and Other Pins
Symbol Type Pin No Description
XI I 41 40MHz OSC Input

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Input of 40MHz Crystal clock reference
XO O 42 Output of 40MHz Crystal Clock Reference

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CK_BT_40M O 43 Buffered 40M clock outputs for other peripheral IC
PDn I 49 This Pin can Externally Shutdown RTL8192CE without Extra Power Switch
This pin can also support WLAN Radio off function with host interface
remaining connected.
EEPROMSEL/EESK I 14 Trap function: Weakly pull high at power on to indicate the presence of

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external EEPROM. 1: external EEPROM, 0: internal eFuse.
EEPROM Interface EESK Signal
GPIO0/WLAN_ACT IO 45 General Purpose Input/Output Pin or Bluetooth Coexistence WLAN_ACT
Pin

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The WLAN_ACT signal indicates when WLAN is either transmitting or
receiving in the 2.4GHz ISM band.
GPIO1/WLAN_RX IO 46 Trap Function: Weakly pull high at power on to turn on CK_BT_40M.
General Purpose Input/Output Pin or Bluetooth Coexistence WLAN_RX Pin
WLAN_RX is an indicator for wireless LAN RX activity.
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GPIO2/BT_STATE IO 47 General Purpose Input/Output Pin or Bluetooth Coexistence BT_STAT Pin
The BTSTAT signal indicates when normal Bluetooth packets are being
transmitted or received.
GPIO3/BT_PRI IO 48 General Purpose Input/Output Pin or Bluetooth Coexistence BT_PRI Pin
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The BTPRI signal indicates when a high priority Bluetooth packet is being
transmitted or received.
GPIO4 IO 10 General Purpose Input/Output Pin
GPIO5 IO 11 General Purpose Input/Output Pin
GPIO6/EEDO IO 12 General Purpose Input/Output Pin or EEPROM Interface EEDO Signal
GPIO7/EEDI IO 13 General Purpose Input/Output Pin or EEPROM Interface EEDI Signal
GPIO8/TRSWN[0]/LED2 IO 4 General Purpose Input/Output Pin or RF TX/RX path select or LED2.
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GPIO9 IO 3 General Purpose Input/Output Pin

GPIO10 IO 2 General Purpose Input/Output Pin
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Datasheet

6. Electrical and Thermal Characteristics

6.1. Temperature Limit Ratings
Table 7. Temperature Limit Ratings

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Parameter Minimum Maximum Units
Storage Temperature -55 +125 C

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Ambient Operating Temperature 0 70 C
Junction Temperature 0 125 C

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6.2. DC Characteristics
Table 8. DC Characteristics
Symbol Parameter Minimum Typical Maximum Units

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VDD33 3.3V I/O Supply Voltage 3.135 3.3 3.465 V
VDD12 1.2V Core Supply Voltage 1.10 1.2 1.32 V
VDD15 1.5V Supply Voltage 1.425 1.5 1.575 V
IDD33 3.3V Rating Current 800 mA
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7. Mechanical Dimensions

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7.1. Mechanical Dimensions Notes

Symbol Dimension in mm Dimension in inch

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Min Nom Max Min Nom Max
A 0.75 0.85 1.00 0.030 0.034 0.039
A1 0.00 0.02 0.05 0.000 0.001 0.002

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A2 0.55 0.65 0.80 0.022 0.026 0.032
A3 0.20REF 0.008REF
b 0.18 0.25 0.30 0.007 0.010 0.012
D/E 9.00BSC 0.354BSC

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D1/E1 8.75BSC 0.344BSC
D2/E2 5.25 5.5 5.75 0.206 0.216 0.226
e 0.50BSC 0.020BSC
L 0.30 0.40 0.50 0.012 0.016 0.020

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θ 0o - 14o 0o - 14o
aaa - - 0.15 - - 0.006
bbb - - 0.10 - - 0.004
ccc - - 0.10 - - 0.004
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ddd - - 0.05 - - 0.002
eee - - 0.08 - - 0.003
fff - - 0.10 - - 0.004
Note1: DIMENSIONS D1 AND E1 DO NOT INCLUDE MOLD PROTRUSION.
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Note2: CONTROLLING DIMENSION: MILLIMETER (mm).
Note3: REFERENCE DOCUMENTL: JEDEC MO-220.
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8. Ordering Information
Table 9. Ordering Information
Part Number Package Status
RTL8192CE-GR QFN-64, ‘Green’Package Engineering Sample

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Realtek Semiconductor Corp.

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Headquarters
No. 2, Innovation Road II, Hsinchu Science Park,
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Hsinchu, 300, Taiwan, R.O.C.

Tel: 886-3-5780211 Fax: 886-3-5776047
www.realtek.com
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