PRELIMINARY TECHNICAL DATA

a Energy Metering IC
with Integrated Oscillator
Preliminary Technical Data ADE7757*
FEATURES The ADE7757 specifications surpass the accuracy require-
ments as quoted in the IEC1036 standard. Due to the
On Chip Oscillator as clock source similarity between the ADE7757 and AD7755, the Appli-
High Accuracy, Supports 50 Hz/60 Hz IEC 521/1036 cation Note AN-559 can be used as a basis for a descrip-
Less than 0.1% Error Over a Dynamic Range of tion of an IEC1036 low cost watt-hour meter reference
500 to 1 design.
The ADE7757 Supplies Average Real Power on the
Frequency Outputs F1 and F2 The only analog circuitry used in the ADE7757 is in the
The High Frequency Output CF Is Intended for sigma-delta ADCs and reference circuit. All other signal
Calibration and Supplies Instantaneous Real Power processing (e.g., multiplication and filtering) is carried
Direct Drive for Electromechanical Counters and out in the digital domain. This approach provides superior
Two Phase Stepper Motors (F1 and F2) stability and accuracy over time and extreme environmen-
Proprietary ADCs and DSP Provide High Accuracy over tal conditions.
Large Variations in Environmental Conditions and The ADE7757 supplies average real power information on
Time the low frequency outputs F1 and F2. These outputs may
On-Chip Power Supply Monitoring be used to directly drive an electromechanical counter or
On-Chip Creep Protection (No Load Threshold) interface with an MCU. The high frequency CF logic
On-Chip Reference 2.5 V ⴞ 8% (30 ppm/ⴗC Typical) output, ideal for calibration purposes, provides instanta-
with External Overdrive Capability neous real power information.
Single 5 V Supply, Low Power (15 mW Typical)
The ADE7757 includes a power supply monitoring circuit
Low Cost CMOS Process
on the VDD supply pin. The ADE7757 will remain in reset
AC Input only
mode until the supply voltage on VDD reaches approxi-
mately 4 V. If the supply falls below 4 V, the ADE7757
GENERAL DESCRIPTION will also reset and the F1, F2 and CF outputs will be in
The ADE7757 is a high accuracy electrical energy mea- their non-active modes.
surement IC. It is a pin reduction version of AD7755 Internal phase matching circuitry ensures that the voltage
with an enhancement of a precise oscillator circuit that and current channels are phase matched while the HPF in
serves as a clock source to the chip. The ADE7757 the current channel eliminates dc offsets. An internal no-
eliminates the cost of an external crystal or resonator, load threshold ensures that the ADE7757 does not exhibit
thus reducing the overall cost of a meter built with this creep when no load is present.
IC. The chip directly interfaces with shunt resistor and
only operates with AC input. The ADE7757 is available in 16-lead SOIC narrow-body
package.

FUNCTIONAL BLOCK DIAGRAM

VDD AGND DGND

ADE7757
POWER
SUPPLY MONITOR
SIGNAL
PROCESSING
V2P ∑∆ ...110101... BLOCK
V2N ADC MULTIPLIER LPF
PHASE
CORRECTION HPF
V1N ∑∆ ...11011001...
V1P ADC Φ
DIGITAL-TO-FREQUENCY
CONVERTER
2.5V 4kV
INTERNAL
REFERENCE OSCILLATOR

REFIN/OUT RCLKIN RESERVED SCF S0 S1 CF F1 F2

*U.S. Patents 5,745,323, 5,760,617, 5,862,069, 5,872,469; other pending.

REV. PrC.
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, USA.
which may result from its use. No license is granted by implication or Tel: 781/329-4700 World Wide Web Site: http://www.analog.com
otherwise under any patent or patent rights of Analog Devices. Fax: 781/326-8703 © Analog Devices, Inc., February 2002
 PRELIMINARY TECHNICAL DATA
(VDD = 5 V ⴞ 5%, AGND = DGND = 0 V, On-Chip Reference, rCKLIN = 5 kΩ 0.1% 5ppm/°C,
ADE7757–SPECIFICATIONS TMIN to TMAX = –40ⴗC to +85ⴗC)
Parameter Value Units Test Conditions/Comments
1, 2
ACCURACY
Measurement Error1 on Channel V1 Channel V2 with Full-Scale Signal (±165 mV),+25°C
TBD % Reading typ Over a Dynamic Range 500 to 1
Phase Error1 Between Channels Line Frequency = 45 Hz to 65 Hz
V1 Phase Lead 37°
(PF = 0.8 Capacitive) ±0.1 Degrees(°) max
V1 Phase Lag 60°
(PF = 0.5 Inductive) ±0.1 Degrees(°) max
AC Power Supply Rejection1 S0 = S1 = 1,
Output Frequency Variation (CF) TBD % Reading typ V1 = V2 = 100 mV rms, @50 Hz
Ripple on VDD of 200 mV rms @ 100 Hz
DC Power Supply Rejection1 S0 = S1 = 1,
Output Frequency Variation (CF) TBD % Reading typ V1 = 100 mV rms, V2 = 100 mV rms,
VDD = 5 V ±250 mV
ANALOG INPUTS See Analog Inputs Section
Channel V1 Maximum Signal Level ± 30 mV max V1P and V1N to AGND
Channel V2 Maximum Signal Level ±165 mV max V2N and V2P to AGND
Input Impedance (DC) TBD kΩ min rCKLIN = 5 kΩ 0.1% 5ppm/°C
Bandwidth (–3 dB) 7 kHz typ rCKLIN = 5 kΩ 0.1% 5ppm/°C
ADC Offset Error1, 2 ±25 mV max See Terminology and Performance Graphs
Frequency Output Error1 TBD % Ideal typ External 2.5 V Reference,
V1 = 30 mV DC, V2 = 165 mV dc
Gain Error1 ±7 % Ideal typ External 2.5 V Reference, Gain = 1
V1 = 30 mV dc, V2 = 165 mV dc
REFERENCE INPUT
REFIN/OUT Input Voltage Range 2.7 V max 2.5 V + 8%
2.3 V min 2.5 V – 8%
Input Impedance TBD kΩ min
Input Capacitance 10 pF max
ON-CHIP REFERENCE Nominal 2.5 V
Reference Error ±200 mV max
Temperature Coefficient 30 ppm/°C typ
ppm/°C max
LOGIC INPUTS3
SCF, S0, S1,
Input High Voltage, VINH 2.4 V min VDD = 5 V ± 5%
Input Low Voltage, VINL 0.8 V max VDD = 5 V ± 5%
Input Current, IIN ±3 µA max Typically 10 nA, VIN = 0 V to VDD
Input Capacitance, CIN 10 pF max
LOGIC OUTPUTS3
F1 and F2
Output High Voltage, VOH ISOURCE = 10 mA
4.5 V min VDD = 5 V
Output Low Voltage, VOL ISINK = 10 mA
0.5 V max VDD = 5 V
CF
Output High Voltage, VOH ISOURCE = 5 mA
4 V min VDD = 5 V
Output Low Voltage, VOL ISINK = 5 mA
0.5 V max VDD = 5 V
POWER SUPPLY For Specified Performance
VDD 4.75 V min 5 V – 5%
5.25 V max 5 V + 5%
IDD TBD TBD TBD
NOTES
1
See Terminology Section for explanation of specifications.
2
See Plots in Typical Performance Graphs.
3
Sample tested during initial release and after any redesign or process change that may affect this parameter.
Specifications subject to change without notice.
–2– REV. PrC.
 PRELIMINARY TECHNICAL DATA
ADE7757
(VDD = 5 V ⴞ 5%, AGND = DGND = 0 V, On-Chip Reference, rCKLIN = 5 kΩ 0.1% 5ppm/°C,
TIMING CHARACTERISTICS1, 2 TMIN to TMAX = –40ⴗC to +85ⴗC)
Parameter A, B Versions Units Test Conditions/Comments
t13 550 ms F1 and F2 Pulsewidth (Logic Low)
t2 See Table II sec Output Pulse Period. See Transfer Function Section
t3 1/2 t2 sec Time Between F1 Falling Edge and F2 Falling Edge
t43, 4 180 ms CF Pulsewidth (Logic High)
t5 See Table III sec CF Pulse Period. See Transfer Function Section
t6 TBD sec Minimum Time Between F1 and F2 Pulse
NOTES
1
Sample tested during initial release and after any redesign or process change that may affect this parameter.
2
See Figure 1.
3
The pulsewidths of F1, F2 and CF are not fixed for higher output frequencies. See Frequency Outputs Section.
4
The CF pulse is always 18 µs in the high frequency mode. See Frequency Outputs section and Table III.
Specifications subject to change without notice.

t1

F1
.t 6
.t 2

F2 .t 3

t4 .t 5

CF

Figure 1. Timing Diagram for Frequency Outputs

ORDERING GUIDE

Model Package Description Package Options

ADE7757ARN SOIC narrow-body RN-16
EVAL-ADE7757EB Evaluation Board Evaluation Board

REV. PrC. –3–

 PRELIMINARY TECHNICAL DATA
ADE7757
ABSOLUTE MAXIMUM RATINGS* 16-Lead Plastic SOIC, Power Dissipation . . . . . . . . . 350mW
(TA = +25°C unless otherwise noted) θJA Thermal Impedance** . . . . . . . . . . . . . . . . . 124.9°C/W
VDD to AGND . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V Lead Temperature, Soldering
VDD to DGND . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . +215°C
Analog Input Voltage to AGND Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . +220°C
V1P, V1N, V2P and V2N . . . . . . . . . . . . . . . –6 V to +6 V *Stresses above those listed under Absolute Maximum Ratings may cause
Reference Input Voltage to AGND . . . –0.3 V to VDD + 0.3 V permanent damage to the device. This is a stress rating only; functional
Digital Input Voltage to DGND . . . . . –0.3 V to VDD + 0.3 V operation of the device at these or any other conditions above those listed in the
Digital Output Voltage to DGND . . . . –0.3 V to VDD + 0.3 V operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
Operating Temperature Range
Industrial (A, B Versions) . . . . . . . . . . . . –40°C to +85°C **JEDEC 1S Standard (2 layer) Board Data
Storage Temperature Range . . . . . . . . . . . –65°C to +150°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . +150°C

CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
WARNING!
Although the ADE7757 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD ESD SENSITIVE DEVICE
precautions are recommended to avoid performance degradation or loss of functionality.

TERMINOLOGY ADC OFFSET ERROR

This refers to the small dc signal (offset) associated with the
MEASUREMENT ERROR analog inputs to the ADCs. However, the HPF in Channel V1
The error associated with the energy measurement made by the eliminates the offset in the circuitry. Therefore, the power cal-
ADE7757 is defined by the following formula: culation is not affected by this offset.
Energy registered by ADE7757 − True Energy
%Error = × 100% FREQUENCY OUTPUT ERROR
True Energy The frequency output error of the ADE7757 is defined as
the difference between the measured output frequency (mi-
nus the offset) and the ideal output frequency. The differ-
PHASE ERROR BETWEEN CHANNELS
ence is expressed as a percentage of the ideal frequency.
The HPF (High Pass Filter) in the current channel (Channel
The ideal frequency is obtained from the ADE7757 trans-
V1) has a phase lead response. To offset this phase response
fer function—see Transfer Function section.
and equalize the phase response between channels, a phase
correction network is also placed in Channel V1. The phase
GAIN ERROR
correction network matches the phase to within ±0.1° over a
The gain error of the ADE7757 is defined as the differ-
range of 45 Hz to 65 Hz and ±0.2° over a range 40 Hz to 1
ence between the measured output frequency (minus the
kHz. See Figures 19 and 20.
offset) and the ideal output frequency. It is measured with
a gain of 1 in channel V1. The difference is expressed as a
POWER SUPPLY REJECTION
percentage of the ideal frequency. The ideal frequency is
This quantifies the ADE7757 measurement error as a percent-
obtained from the ADE7757 transfer function—see Trans-
age of reading when the power supplies are varied.
fer Function section.
For the ac PSR measurement a reading at nominal supplies
(5 V) is taken. A 200 mV rms/100 Hz signal is then introduced
onto the supplies and a second reading obtained under the
same input signal levels. Any error introduced is expressed as a
percentage of reading—see Measurement Error definition.
For the dc PSR measurement a reading at nominal supplies
(5 V) is taken. The supplies are then varied ±5% and a second
reading is obtained with the same input signal levels. Any error
introduced is again expressed as a percentage of reading.

–4– REV. PrC.

 PRELIMINARY TECHNICAL DATA
ADE7757
PIN FUNCTION DESCRIPTIONS

Pin No. Mnemonic Description

1 VDD Power Supply. This pin provides the supply voltage for the circuitry in the ADE7757. The
supply voltage should be maintained at 5 V ± 5% for specified operation. This pin should be
decoupled with a 10 µF capacitor in parallel with a ceramic 100 nF capacitor.
2,3 V2P, V2N Analog Inputs for Channel V2 (voltage channel). These inputs provide a fully differential
input pair. The maximum differential input voltage is ±165 mV for specified operation. The
maximum signal level at these pins is ±165 mV with respect to AGND. Both inputs have
internal ESD protection circuitry and an overvoltage of ±6 V can also be sustained on these
inputs without risk of permanent damage.
4, 5 V1N, V1P Analog Inputs for Channel V1 (current channel). These inputs are fully differential voltage
inputs with a maximum signal level of ±30 mV with respect to pin V1N for specified opera-
tion. The maximum signal level at this pin is ±165 mV with respect to AGND. Both inputs
have internal ESD protection circuitry and in addition an overvoltage of ±6 V can be sus-
tained on these inputs without risk of permanent damage.
6 AGND This provides the ground reference for the analog circuitry in the ADE7757, i.e., ADCs and
reference. This pin should be tied to the analog ground plane of the PCB. The analog ground
plane is the ground reference for all analog circuitry, e.g., antialiasing filters, current and
voltage sensors, etc. For accurate noise suppression, the analog ground plane should only be
connected to the digital ground plane at one point. A star ground configuration will help to
keep noisy digital currents away from the analog circuits.
7 REFIN/OUT This pin provides access to the on-chip voltage reference. The on-chip reference has a nomi-
nal value of 2.5 V ± 8% and a typical temperature coefficient of 30 ppm/°C. An external
reference source may also be connected at this pin. In either case this pin should be
decoupled to AGND with a 1 µF tantalum capacitor and 100 nF ceramic capacitor.
8 SCF Select Calibration Frequency. This logic input is used to select the frequency on the calibra-
tion output CF. Table III shows calibration frequencies selection.
9,10 S1, S0 These logic inputs are used to select one of four possible frequencies for the digital-to-fre-
quency conversion. With this logic input, designers have greater flexibility when designing an
energy meter. See Selecting a Frequency for an Energy Meter Application.
11 RCLKIN To enable the internal oscillator as a clock source to the chip, a precise 5 kΩ resistor must be
connected from this pin to DGND.
12 RESERVED Reserved pin. No load should be connected to this pin.
13 DGND This provides the ground reference for the digital circuitry in the ADE7757, i.e., multiplier,
filters and digital-to-frequency converter. This pin should be tied to the digital ground plane
of the PCB. The digital ground plane is the ground reference for all digital circuitry, e.g.,
counters (mechanical and digital), MCUs and indicator LEDs. For accurate noise suppres-
sion the analog ground plane should only be connected to the digital ground plane at one
point only, e.g., a star ground.
14 CF Calibration Frequency Logic Output. The CF logic output provides instantaneous real power
information. This output is intended for calibration purposes. Also see SCF pin description.
15,16 F2,F1 Low Frequency Logic Outputs. F1 and F2 supply average real power information. The logic
outputs can be used to directly drive electromechanical counters and two phase stepper mo-
tors. See Transfer Function.

VDD 1 16 F1
V2P 2 15 F2
PIN CONFIGURATION
V2N 3 14 CF
SOIC-16nb Package
V1N 4 ADE7757 13 DGND
V1P 5 TOP VIEW 12
RESERVED
(Not to Scale)
AGND 6 11 RCLKIN
REFIN/OUT 7 10 S0
SCF 8 9 S1

REV. PrC. –5–

 PRELIMINARY TECHNICAL DATA
ADE7757 –Typical Performance Characteristics

TBD TBD
Figure 5. Error as a % of Reading over Temperature with
Figure 2. Error as a % Reading over Temperature on-chip
reference (PF=1) External Reference (PF=0.5)

TBD TBD
Figure 3. Error as a % of Reading over Temperature with Figure 6. Error as a %of Reading over Input Frequency
on-chip reference (PF=0.5)

VDD

100nF 10 µF

602k Ω VDD U3 K7
V2P F1
220V 200 Ω 150nF F2
U1
ADE7757 CF

TBD
200 Ω
V2N K8
150nF PS2501-1
40A TO
40mA RESERVED
200 Ω
V1P 5 kΩ
RCLKIN
150nF VDD
500µΩ
200 Ω
V1N 10k Ω
150nF
S0
S1
REFIN/OUT
1µF 100nF SCF
AGND DGND 10nF 10nF 10nF

Figure 4. Error as a % of Reading over Temperature with Figure 7. Test Circuit for Performance Curves
External Reference (PF=1)

–6– REV. PrC.

 PRELIMINARY TECHNICAL DATA
ADE7757

TBD TBD
Figure 10. PSR with External Reference
Figure 8. Channel V1 Offset Distribution

TBD
Figure 9. PSR with Internal Reference

REV. PrC. –7–

 PRELIMINARY TECHNICAL DATA
ADE7757
THEORY OF OPERATION phase. Figure 12 displays the unity power factor condition
The two ADCs digitize the voltage signals from the cur- and a DPF (Displacement Power Factor) = 0.5, i.e., cur-
rent and voltage sensors. These ADCs are 16-bit sigma- rent signal lagging the voltage by 60°. If we assume the
delta with an oversampling rate of 450 kHz. This analog voltage and current waveforms are sinusoidal, the real
input structure greatly simplifies sensor interfacing by power component of the instantaneous power signal (i.e.,
providing a wide dynamic range for direct connection to the dc term) is given by:
the sensor and also simplifies the antialiasing filter design.
A high pass filter in the current channel removes any dc  V × I
  × cos (60°)
component from the current signal. This eliminates any  2 
inaccuracies in the real power calculation due to offsets in This is the correct real power calculation.
the voltage or current signals. Because the HPF is always
enabled, the IC will only operate with AC Input—see HPF INSTANTANEOUS INSTANTANEOUS REAL
POWER
and Offset Effects. POWER SIGNAL POWER SIGNAL

The real power calculation is derived from the instanta-

neous power signal. The instantaneous power signal is V× I
generated by a direct multiplication of the current and 2
voltage signals. In order to extract the real power compo-
nent (i.e., the dc component), the instantaneous power 0V TIME
signal is low-pass filtered. Figure 11 illustrates the instan-
CURRENT
taneous real power signal and shows how the real power VOLTAGE
information can be extracted by low-pass filtering the in-
POWER
stantaneous power signal. This scheme correctly calculates INSTANTANEOUS INSTANTANEOUS REAL
real power for sinusoidal current and voltage waveforms at POWER SIGNAL POWER SIGNAL

all power factors. All signal processing is carried out in the

digital domain for superior stability over temperature and
V×I
time. cos ( 60°)
2
0V TIME
DIGITAL-TO-
FREQUENCY
HPF
F1
PGA ⌺
CH1 ADC F2 VOLTAGE CURRENT
LPF
60°°
60
MULTIPLIER DIGITAL-TO-
FREQUENCY
CH2 ADC
⌺ CF
Figure 12. DC Component of Instantaneous Power Signal
Conveys Real Power Information PF < 1
INSTANTANEOUS INSTANTANEOUS REAL
POWER SIGNAL- p (t) POWER SIGNAL Nonsinusoidal Voltage and Current
The real power calculation method also holds true for
VⴛI p(t) = i(t)ⴛv(t)
WHERE:
nonsinusoidal current and voltage waveforms. All voltage and
VⴛI
VⴛI v(t) = Vⴛcos(␻t)
i(t) = Iⴛcos(␻t) 2
current waveforms in practical applications will have some
2 harmonic content. Using the Fourier Transform, instantaneous
p(t) = VⴛI {1+cos (2␻t )}
2
voltage and current waveforms can be expressed in terms of
TIME their harmonic content.
∞
Figure 11. Signal Processing Block Diagram
v( t ) = V0 + 2 × ∑ Vh × sin (hωt + αh ) (1)
The low frequency outputs (F1, F2) of the ADE7757 is h≠0
generated by accumulating this real power information.
where:
This low frequency inherently means a long accumulation
time between output pulses. Consequently, the resulting v(t) is the instantaneous voltage
output frequency is proportional to the average real power. VO is the average value
This average real power information is then accumulated Vh is the rms value of voltage harmonic h
(e.g., by a counter) to generate real energy information. and
Conversely, due to its high output frequency and hence ␣h is the phase angle of the voltage harmonic.
shorter integration time, the CF output frequency is pro- ∞
portional to the instantaneous real power. This is useful i( t ) = I 0 + 2 × ∑ I h × sin (hωt + βh ) (2)
for system calibration, which can be done faster under h ≠0
steady load conditions.
where:
i(t) is the instantaneous current
Power Factor Considerations IO is the dc component
The method used to extract the real power information from Ih is the rms value of current harmonic h
the instantaneous power signal (i.e., by low-pass filtering) is still and
valid even when the voltage and current signals are not in ␤h is the phase angle of the current harmonic.
–8– REV. PrC.
 PRELIMINARY TECHNICAL DATA
ADE7757
Using Equations 1 and 2, the real power P can be ex- Channel V2 (Voltage Channel )
pressed in terms of its fundamental real power (P1) and The output of the line voltage sensor is connected to the
harmonic real power (PH). ADE7757 at this analog input. Channel V2 is a fully differen-
tial voltage input with maximum peak differential signal
P = P1 + PH of ±165 mV. Figure 14 illustrates the maximum signal
where: levels that can be connected to the ADE7757 Channel V2.

V2

P1 = V1 × I1 cos φ1 +165mV

(3) V2P
φ1 = α1 − β1 DIFFERENTIAL INPUT
± 165mV MAX PEAK V2
V2N
VCM
COMMON-MODE VCM
and ± 25mV MAX

-165mV AGND

∞
PH = ∑V
h ≠1
h × I h cos φ h Figure 14. Maximum Signal Levels, Channel V2
(4) Channel V2 is usually driven from a common-mode volt-
φh = αh − βh age, i.e., the differential voltage signal on the input is
referenced to a common mode (usually AGND). The
analog inputs of the ADE7757 can be driven with com-
As can be seen from Equation 4 above, a harmonic real mon-mode voltages of up to 25 mV with respect to
power component is generated for every harmonic, pro- AGND. However best results are achieved using a com-
vided that harmonic is present in both the voltage and mon mode equal to AGND.
current waveforms. The power factor calculation has pre- Typical Connection Diagrams
viously been shown to be accurate in the case of a pure Figure 15 shows a typical connection diagram for Channel V1.
sinusoid, therefore the harmonic real power must also A shunt is the current sensor selected for this example because of
correctly account for power factor since it is made up of a its low cost compared to other current sensors such as the CT
series of pure sinusoids. (current transformer). This IC is ideal for low current
Note that the input bandwidth of the analog inputs is meters.
14 kHz with.
Rf V1P
ANALOG INPUTS Cf
Channel V1 (Current Channel ) ±30mV V1N
SHUNT
The voltage output from the current sensor is connected to the
ADE7757 here. Channel V1 is a fully differential voltage input. Rf Cf
AGND
V1P is the positive input with respect to V1N.
PHASE NEUTRAL
The maximum peak differential signal on Channel V1 should
be less than ±30 mV (21 mV rms for a pure sinusoidal signal) Figure 15. Typical Connection for Channel V1
for specified operation. Figure 16 shows a typical connection for Channel V2.
Typically, ADE7757 is biased around the neutral wire,
V1
and a resistor divider is used to provide a voltage signal
+30mV that is proportional to the line voltage. Adjusting the ratio
V1P of Ra, Rb and VR is also a convenient way of carrying out
DIFFERENTIAL INPUT a gain calibration on a meter.
± 30mV MAX PEAK V1
V1N
VCM
COMMON-MODE Ra* Cf
± 6.25mV MAX VCM

Rb*
-30mV AGND ± 165mV V2P
VR*
Rf V2N

Figure 13. Maximum Signal Levels, Channel V1 * Ra >> Rf + VR

Cf
PHASE NEUTRAL
* Rb + VR = Rf
The diagram in Figure 13 illustrates the maximum signal
levels on V1P and V1N. The maximum differential voltage Figure 16. Typical Connections for Channel V2
is ±30 mV. The differential voltage signal on the inputs
must be referenced to a common mode, e.g. AGND. The
maximum common mode signal is ±6.25 mV as shown in
Figure 13.

REV. PrC. –9–

 PRELIMINARY TECHNICAL DATA
ADE7757
POWER SUPPLY MONITOR
The ADE7757 contains an on-chip power supply monitor.
DC COMPONENT (INCLUDING ERROR TERM) IS
The power supply (VDD) is continuously monitored by the EXTRACTED BY THE LPF FOR REAL POWER CALCULATION
Vos × I os
ADE7757. If the supply is less than 4 V, the ADE7757
V× I
will reset. This is useful to ensure proper device operation 2
at power-up and power-down. The power supply monitor
has built in hysteresis and filtering that provide a high
degree of immunity to false triggering from noisy sup- I os × V
plies.
Vos × I
As can be seen from Figure 17, the trigger level is nomi- 0
nally set at 4 V. The tolerance on this trigger level is FREQUENCY - Rad/s
within ±5%. The power supply and decoupling for the
part should be such that the ripple at VDD does not exceed Figure 18. Effect of Channel Offset on the Real Power
5 V ± 5% as specified for normal operation. Calculation
The HPF in Channel V1 has an associated phase response
VDD
that is compensated for on-chip. Figures 19 and 20 show
5V the phase error between channels with the compensation
4V network activated. The ADE7757 is phase compensated up
to 1 kHz as shown. This will ensure correct active har-
monic power calculation even at low power factors.

0V 0.30

TIME
0.25

INTERNAL 0.20
ACTIVATION INACTIVE ACTIVE INACTIVE
PHASE - Degrees

0.15

0.10
Figure 17. On-Chip Power Supply Monitor
0.05
HPF and Offset Effects
Figure 18 illustrates the effect of offsets on the real power cal- 0
culation. As can be seen, offsets on Channel V1 and Channel
-0.05
V2 will contribute a dc component after multiplication. Since
this dc component is extracted by the LPF and used to gener- -0.10
0 100 200 300 400 500 600 700 800 900 1000
ate the real power information, the offsets will contribute a
FREQUENCY - Hz
constant error to the real power calculation. This problem is
easily avoided by the built-in HPF in Channel V1. By removing Figure 19. Phase Error Between Channels (0 Hz to 1 kHz)
the offsets from at least one channel, no error component can
be generated at dc by the multiplication. Error terms at the line
frequency (ω) are removed by the LPF and the digital-to- 0.30

frequency conversion—see Digital-to-Frequency Con ver-

Conver-
0.25
sion.
0.20

The equation below shows how power calculation is affected by

PHASE - Degrees

0.15
the dc offsets in the current and voltage channels:
0.10

{Vcos(ωt) + Vos }× {I cos(ωt ) + I os } = 0.05

V×I
+ Vos × I os + Vos × I cos(ωt ) + I os × V cos(ωt )
0

2 -0.05
V×I
+ × cos( 2ωt ) -0.10
2 40 45 50 55 60 65 70
FREQUENCY - Hz

Figure 20. Phase Error Between Channels (40 Hz to 70 Hz)

–10– REV. PrC.

 PRELIMINARY TECHNICAL DATA
ADE7757
DIGITAL-TO-FREQUENCY CONVERSION ing it to a frequency. This shorter accumulation period
As previously described, the digital output of the low-pass filter means less averaging of the cos (2ωt) component. Conse-
after multiplication contains the real power information. How- quently, some of this instantaneous power signal passes
ever, since this LPF is not an ideal “brick wall” filter imple- through the digital-to-frequency conversion. This will not
mentation, the output signal also contains attenuated be a problem in the application. Where CF is used for
components at the line frequency and its harmonics, i.e., calibration purposes, the frequency should be averaged by
cos(hωt) where h = 1, 2, 3, . . . etc. the frequency counter which will remove any ripple. If CF
The magnitude response of the filter is given by: is being used to measure energy; for example, in a micro-
processor-based application, the CF output should also be
1 averaged to calculate power.
H( f ) =
f2 (5)
Because the outputs F1 and F2 operate at a much lower
1+ frequency, a lot more averaging of the instantaneous real
8.9 2 power signal is carried out. The result is a greatly attenu-
For a line frequency of 50 Hz this would give an attenua- ated sinusoidal content and a virtually ripple-free fre-
tion of the 2ω (100 Hz) component of approximately – quency output.
22 dB. The dominating harmonic will be at twice the line
frequency (2ω) due to the instantaneous power calculation.
Interfacing the ADE7757 to a Microcontroller for Energy
Figure 21 shows the instantaneous real power signal at the Measurement
output of the LPF which still contains a significant amount The easiest way to interface the ADE7757 to a
of instantaneous power information, i.e., cos (2ωt). This microcontroller is to use the CF high frequency output
signal is then passed to the digital-to-frequency converter with the output frequency scaling set to 2048 x F1, F2.
where it is integrated (accumulated) over time in order to This is done by setting SCF = 0 and S0 = S1 = 1, see
produce an output frequency. The accumulation of the Table III. With full-scale ac signals on the analog inputs,
signal will suppress or average out any non-dc components the output frequency on CF will be approximately
in the instantaneous real power signal. The average value 2.867 kHz. Figure 22 illustrates one scheme which could
of a sinusoidal signal is zero. Hence the frequency gener- be used to digitize the output frequency and carry out the
ated by the ADE7757 is proportional to the average real necessary averaging mentioned in the previous section.
power. Figure 21 shows the digital-to-frequency conver-
sion for steady load conditions, i.e., constant voltage and CF
current. FREQUENCY
RIPPLE

AVERAGE
FREQUENCY ±10%

F1
FREQUENCY

DIGITAL-TO-
FREQUENCY
F1
∑ TIME
V F2
LPF
TIME
MULTIPLIER MCU
DIGITAL-TO- ADE7757
FREQUENCY CF
COUNTER
I
FREQUENCY

∑ CF CF
LPF TO EXTRACT
REAL POWER
(DC TERM)
V× I TIME TIMER
2
cos ( 2 ωt )
ATTENUATED BY LPF

ω 2ω
Figure 22. Interfacing the ADE7757 to an MCU
0
FREQUENCY (RAD/S) As shown, the frequency output CF is connected to an
INSTANTANEOUS REAL POWER SIGNAL MCU counter or port. This will count the number of
(FREQUENCY DOMAIN)
pulses in a given integration time which is determined by
Figure 21. Real Power-to-Frequency Conversion
an MCU internal timer. The average power is propor-
tional to the average frequency is given by:
As can be seen in the diagram, the frequency output CF is
seen to vary over time, even under steady load conditions. Counter
This frequency variation is primarily due to the cos (2ωt) Average Frequency = Average Power =
Time
component in the instantaneous real power signal. The
output frequency on CF can be up to 2048 times higher The energy consumed during an integration period is
than the frequency on F1 and F2. This higher output fre- given by:
quency is generated by accumulating the instantaneous
real power signal over a much shorter time while convert- Counter
Energy = Average Power × Time = × Time = Counter
Time
REV. PrC. –11–
 PRELIMINARY TECHNICAL DATA
ADE7757
For the purpose of calibration, this integration time could Table I. F1–4 Frequency Selection
be 10 to 20 seconds in order to accumulate enough pulses
to ensure correct averaging of the frequency. In normal S1 S0 F1–4 (Hz)
operation the integration time could be reduced to one or 0 0 0.85
two seconds depending, for example, on the required up- 0 1 1.7
date rate of a display. With shorter integration times on 1 0 3.4
the MCU the amount of energy in each update may still 1 1 6.8
have some small amount of ripple, even under steady load
NOTE
conditions. However, over a minute or more the measured
*F1–4 is a binary fraction of the internal oscillator frequency
energy will have no ripple.
Example
Power Measurement Considerations In this example, with ac voltages of ±30 mV peak applied
Calculating and displaying power information will always to V1 and ±165 mV peak applied to V2, the expected
have some associated ripple that will depend on the inte- output frequency is calculated as follows:
gration period used in the MCU to determine average
power and also the load. For example, at light loads the F1− 4 = 0.85 Hz, S0 = S1 = 0
output frequency may be 10 Hz. With an integration pe-
riod of two seconds, only about 20 pulses will be counted. V1rms = 0.03/ 2 volts
The possibility of missing one pulse always exists as the
ADE7757 output frequency is running asynchronously to V 2 rms = 0.165/ 2 volts
the MCU timer. This would result in a one-in-twenty or
5% error in the power measurement. Vref = 2.5 V (nominal reference value).
TRANSFER FUNCTION NOTE: If the on-chip reference is used, actual
Frequency Outputs F1 and F2 output frequencies may vary from device to device
The ADE7757 calculates the product of two voltage signals (on due to reference tolerance of ±8%.
Channel V1 and Channel V2) and then low-pass filters this
product to extract real power information. This real power 515 .85 × 0 .03 × 0 .165 × 0 .85
information is then converted to a frequency. The frequency Freq = = 0 .175
information is output on F1 and F2 in the form of active low 2 × 2 × 2 .5 2
pulses. The pulse rate at these outputs is relatively low,
e.g., 0.175 Hz maximum for ac signals with S0 = S1 = Table II. Maximum Output Frequency on F1 and F2
0—see Table II. This means that the frequency at these
outputs is generated from real power information accumu- Max Frequency
lated over a relatively long period of time. The result is an S1 S0 for AC Inputs (Hz)
output frequency that is proportional to the average real 0 0 0.175
power. The averaging of the real power signal is implicit 0 1 0.35
to the digital-to-frequency conversion. The output fre- 1 0 0.7
quency or pulse rate is related to the input voltage signals 1 1 1.4
by the following equation:
Frequency Output CF
515.84 × V 1rms × V 2 rms × F1− 4 The pulse output CF (Calibration Frequency) is intended for
Freq =
Vref 2 calibration purposes. The output pulse rate on CF can be up to
2048 times the pulse rate on F1 and F2. The lower the F1–4
where: frequency selected, the higher the CF scaling (except for the
high frequency mode SCF = 0, S1 = S0 = 1). Table III shows
Freq = Output frequency on F1 and F2 (Hz) how the two frequencies are related, depending on the states of
the logic inputs S0, S1 and SCF. Due to its relatively high
V1rms = Differential rms voltage signal on Channel V1 pulse rate, the frequency at CF logic output is proportional to
(volts) the instantaneous real power. As with F1 and F2, CF is derived
from the output of the low-pass filter after multiplication. How-
V 2 rms = Differential rms voltage signal on Channel V2 ever, because the output frequency is high, this real power
(volts) information is accumulated over a much shorter time. Hence
less averaging is carried out in the digital-to-frequency con-
Vref = The reference voltage (2.5 V ± 8%) (volts) version. With much less averaging of the real power signal, the
CF output is much more responsive to power fluctua-
F1− 4 = One of four possible frequencies selected by us- tions—see Signal Processing Block in Figure 11.
ing the logic inputs S0 and S1—see Table I.

–12– REV. PrC.

 PRELIMINARY TECHNICAL DATA
ADE7757
Table III. Maximum Output Frequency on CF Column 4 of Table V. The closest frequency in Table V
will determine the best choice of frequency (F1–4). For
SCF S1 S0 CF Max for AC Signals (Hz) example, if a meter with a maximum current of 25 A is
1 0 0 128 x F1, F2 = 22.4 being designed, the output frequency on F1 and F2 with
0 0 0 64 x F1, F2 = 11.2 a meter constant of 100 imp/kWhr is 0.153 Hz at 25 A and
1 0 1 64 x F1, F2 = 22.4 220 V (from Table IV). Looking at Table V, the closest
0 0 1 32 x F1, F2 = 11.2 frequency to 0.153 Hz in column four is 0.175 Hz. There-
1 1 0 32 x F1, F2 = 22.4 fore F3 (3.4 Hz—see Table I) is selected for this design.
0 1 0 16 x F1, F2 = 11.2 Frequency Outputs
1 1 1 16 x F1, F2 = 22.4 Figure 1 shows a timing diagram for the various frequency
0 1 1 2048 x F1, F2 = 2.867 kHz outputs. The outputs F1 and F2 are the low frequency outputs
that can be used to directly drive a stepper motor or elec-
tromechanical impulse counter. The F1 and F2 outputs
SELECTING A FREQUENCY FOR AN ENERGY provide two alternating low frequency pulses. The
METER APPLICATION pulsewidth (t1) is set such that if F1 and F2 falls below
As shown in Table I, the user can select one of four fre- 1100 ms (0.909 Hz) the pulsewidth of F1 and F2 is set to
quencies. This frequency selection determines the maxi- half of their period. The maximum output frequencies for
mum frequency on F1 and F2. These outputs are intended F1 and F2 are shown in Table II.
for driving an energy register (electromechanical or oth-
ers). Since only four different output frequencies can be The high frequency CF output is intended to be used for
selected, the available frequency selection has been opti- communications and calibration purposes. CF produces a
mized for a meter constant of 100 imp/kWhr with a maxi- 180 ms-wide active high pulse (t4) at a frequency propor-
mum current of between 10 A and 120 A. Table IV shows tional to active power. The CF output frequencies are
the output frequency for several maximum currents (IMAX) given in Table III. As in the case of F1 and F2, if the
with a line voltage of 220 V. In all cases the meter con- period of CF (t5) falls below 360 ms, the CF pulsewidth is
stant is 100 imp/kWhr. set to half the period. For example, if the CF frequency is
20 Hz, the CF pulsewidth is 25 ms.
Table IV. F1 and F2 Frequency at 100 imp/kWhr NOTE: When the high frequency mode is selected, (i.e.,
SCF = 0, S1 = S0 = 1) the CF pulsewidth is fixed at
I MAX F1 and F2 (Hz) 36 µs. Therefore t4 will always be 36 µs, regardless of
12.5 A 0.076 output frequency on CF.
25.0 A 0.153
40.0 A 0.244 NO LOAD THRESHOLD
60.0 A 0.367 The ADE7757 also includes a “no load threshold” and “start-
80.0 A 0.489 up current” feature that will eliminate any creep effects in
120.0 A 0.733 the meter. The ADE7757 is designed to issue a minimum
output frequency. Any load generating a frequency lower than
The F1–4 frequencies allow complete coverage of this range of this minimum frequency will not cause a pulse to be issued on
output frequencies (F1, F2). When designing an energy meter F1, F2 or CF. The minimum output frequency is given as
the nominal design voltage on Channel V2 (voltage) should be 0.0014% of the full-scale output frequency for each of the F1–4
set to half-scale to allow for calibration of the meter constant. frequency selections—see Table I. For example, an energy
The current channel should also be no more than half-scale meter with a meter constant of 100 imp/kWhr on F1, F2
when the meter sees maximum load. This will allow over cur- using F3 (3.4 Hz), the minimum output frequency at F1
rent signals and signals with high crest factors to be accommo- or F2 would be 0.0014% of 3.4 Hz or 4.76 x 10–5 Hz.
dated. Table V shows the output frequency on F1 and F2 when This would be 3.05 x 10–3 Hz at CF (64 x F1 Hz) when
both analog inputs are half-scale. The frequencies listed in SCF = S0 = 1, S1 = 0. In this example the no load
Table V align very well with those listed in Table IV for maxi- threshold would be equivalent to 1.7 W of load or a start-
mum load. up current of 8 mA at 220 V. Comparing this value to
the IEC1036 specification which states that the meter
Table V. F1 and F2 Frequency with Half-Scale AC Inputs must start up with a load equal to or less than 0.4% Ib.
For a 5A (Ib) meter 0.4% of Ib is equivalent to 20 mA.
Frequency on F1 and F2–
S1 S0 F1–4 CH1 and CH2 Half-Scale AC Inputs
0 0 0.85 0.0438 Hz
0 1 1.7 0.0875 Hz
1 0 3.4 0.175 Hz
1 1 6.8 0.35 Hz

When selecting a suitable F1–4 frequency for a meter de-

sign, the frequency output at IMAX (maximum load) with a
meter constant of 100 imp/kWhr should be compared with

REV. PrC. –13–

 PRELIMINARY TECHNICAL DATA
ADE7757
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).

16-Lead SOIC narrow-body

0.3937 (10.00)
0.3859 (9.80)

16 9
0.1574 (4.00) 0.2440 (6.20)
0.1497 (3.80) 0.2284 (5.80)
1 8

PIN 1 0.050 (1.27) 0.0688 (1.75)

0.0196 (0.50)
BSC 0.0532 (1.35) × 45°
0.0099 (0.25)

8°
0.0098 (0.25) 0.0192 (0.49) SEATING 0.0099 (0.25) 0° 0.0500 (1.27)
0.0040 (0.10) 0.0138 (0.35) PLANE
0.0075 (0.19) 0.0160 (0.41)

–14– REV. PrC.