FORMAT : QP09 KCE/DEPT.

OF ECE

DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING

ME VLSI DESIGN

SUBJECT : VLSI SIGNAL PROCESSING

SEMESTER : II

COURSE PLAN (VL 5291)

(Version : 1)

PREPARED BY
Mr. P.RAJA PIRIAN, AP/ECE

VLSI SP 1 KCE/I M.E VLSI / VLSI SP

FORMAT : QP09 KCE/DEPT. OF ECE

VL5291 VLSI SIGNAL PROCESSING LTPC

3003
UNIT I PIPELINING AND PARALLEL PROCESSING OF DIGITAL FILTERS 9
Introduction to DSP systems Typical DSP algorithms, Data flow and Dependence grap hs critical
path, Loop bound, iteration bound, Longest path matrix algorithm, Pipelining and Parallel processing
of FIR filters, Pipelining and Parallel processing for low power.

UNIT II ALGORITHMIC STRENGTH REDUCTION TECHNIQUE I 9

Retiming definitions and properties, Unfolding an algorithm for unfolding, properties of
unfolding, sample period reduction and parallel processing application, Algorithmic strength
reduction in filters and transforms 2 - parallel FIR filter, 2-parallel fast FIR filter, DCT architecture,
rank-order filters, Odd - Even merge - sort architecture, parallel rank - order filters.

UNIT III ALGORITHIMIC STRENGTH REDUCTION II 9

Fast convolution Cook - Toom algorithm, modified Cook Toom algorithm, Pipelined and parallel
recursive filters Look - Ahead pipelining in first - order IIR filters, Look
Ahead pipelining with power of - 2 decomposition, Clustered look - ahead pipelining, Parallel
processing of IIR filters, combined pipelining and parallel processing of IIR filters.

UNIT IV BIT - LEVEL ARITHMETIC ARCHITECTURES 9

Bit - level arithmetic architectures parallel multipliers with sign extension, parallel carry - ripple
and carry - save multipliers, Design of Lyons bit - serial multipliers using Horners rule, bit - serial
FIR filter, CSD representation, CSD multiplication using Horners rule for precision improvement,
Distributed Arithmetic fundamentals and FIR filters

UNIT V NUMERICAL STRENGTH REDUCTION, WAVE AND

ASYNCHRONOUS PIPELINING 9
Numerical strength reduction sub expression elimination, multiple constant multiplication,
iterative matching, synchronous pipelining and clocking styles, clock skew in edge - triggered single
phase clocking, two phase clocking, wave pipelining. Asynchronous pipelining bundled data versus
dual rail protocol.
TOTAL: 45 PERIODS

SIGNATUR OF STAFF INCHARGE HOD/ECE

( P.RAJA PIRIAN )

VLSI SP 2 KCE/I M.E VLSI / VLSI SP

FORMAT : QP09 KCE/DEPT. OF ECE

DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING

COURSE PLAN

Sub. Code : VL 5291 Branch / Year / Sem : M.E VLSI/ I / II

Sub.Name : VLSI SIGNAL PROCESSING Batch : 2017 -2019
Staff Name : Mr. P.Raja Pirian Academic Year : 2017-18 (EVEN)

COURSE OBJECTIVE

To introduce techniques for altering the existing DSP structures to suit VLSI
implementations.
To introduce efficient design of DSP architectures suitable for VLSI

REFERENCES:

R1. Keshab K. Parhi, VLSI Digital Signal Processing Systems, Design and implementation,
Wiley, Interscience, 2007.

WEB RESOURCES

W1. http://galia.fc.uaslp.mx/~rmariela/RTDSP/ch4.pdf. (Topic : 07)

W2. http://www.iro.umontreal.ca/~dift6221/demicheli4/retiming.4.ps.pdf. (Topic : 09)
W3. http://web.cecs.pdx.edu/~mperkows/CAPSTONES/DSP1/parapipe.ppt. (Topic : 24)
W4. http://www.win.tue.nl/~cberkel/2IN35/Parhi/chap13.pdf. (Topic : 26)
W5. http://ics.kaist.ac.kr/ee877_2015s/A4_Numerical_Strength_Reduction.pdf. (Topic : 34)

Topic Topic Books for Page No. Teaching No. of Cumulative

VLSI SP 3 KCE/I M.E VLSI / VLSI SP
FORMAT : QP09 KCE/DEPT. OF ECE

Hours No. of
No Reference Methodology
Required periods
UNIT I PIPELINING AND PARALLEL PROCESSING OF DIGITAL FILTERS (09)
Introduction to DSP
01. R1 1 BB 1 1
systems
Typical DSP
02. R1 2-26 BB 1 2
algorithms
Data flow and
03. R1 36-40 BB 1 3
Dependence graphs
04. Critical path R1 45 BB 1 4
Loop bound,
05. R1 45-47 BB 1 5
Iteration bound
Longest path
06. R1 47-50 BB 1 6
matrix algorithm
Pipelining and
R1 63-76 BB
07. Parallel processing 2 8
W1 1-46 PPT
of FIR filters
Pipelining and
08. Parallel processing R1 76-83 BB 1 9
for low power
LEARNING OUTCOME
At the end of unit, students should be able to
Understand the concepts of different dataflow algorithm.
Describe the behaviors of digital filters.
Acquire knowledge about Parallel Processing.
UNIT II ALGORITHMIC STRENGTH REDUCTION TECHNIQUE I (09)
Retiming
R1 91-112 BB
09. definitions and 1 10
W2 1-9 PPT
properties
Unfolding an
10. algorithm for R1 119-126 BB 1 11
unfolding
Properties of
11. R1 127-128 BB 1 12
unfolding
Sample period
reduction and
12. R1 128-140 BB 1 13
parallel processing
application
Algorithmic
strength reduction
13. R1 255-256 BB 1 14
in filters and
transforms.
No. of Cumulative
Topic Books for Teaching
Topic Page No. Hours No. of
No Reference Methodology
Required periods

VLSI SP 4 KCE/I M.E VLSI / VLSI SP

FORMAT : QP09 KCE/DEPT. OF ECE

Parallel FIR filter,

14. parallel fast FIR R1 256-275 BB 1 15
filter,
DCT architecture,
15. rank Order filters R1 275-296 BB 1 16

Odd - Even merge -

16. sort architecture R1 286-288 BB 1 17

Parallel rank -
17. order filters. R1 289-293 BB 1 18

LEARNING OUTCOME
At the end of unit, students should be able to
Understand the concepts retiming.
Describe about the reduction methods.
Acquire knowledge about different DCT architectures.

UNIT III ALGORITHIMIC STRENGTH REDUCTION II (09)

Fast convolution
18. Cook - Toom R1 227-234 BB 1 19
algorithm
Modified Cook
19. R1 234-242 BB 2 21
Toom algorithm,
Pipelined and
20. parallel recursive R1 313-320 BB 1 22
filters
Look - Ahead
21. pipelining in first - R1 320-321 BB 1 23
order IIR filters
Look Ahead
pipelining with
22. R1 321-324 BB 1 24
power of - 2
decomposition
Clustered look -
23. R1 327-328 BB 1 25
ahead pipelining
Parallel processing R1 339-345 BB
24. 1 26
of IIR filters W3 1-13 PPT
Combined
pipelining and
25. R1 345-348 BB 1 27
parallel processing
of IIR filters.
No. of Cumulative
Topic Books for Teaching
Topic Page No. Hours No. of
No Reference Methodology
Required periods

VLSI SP 5 KCE/I M.E VLSI / VLSI SP

FORMAT : QP09 KCE/DEPT. OF ECE

LEARNING OUTCOME
At the end of unit, students should be able to
Understand the concept of fast convolution algorithm.
Describe the pipelining algorithms used for FIR and IIR filter.
Acquire knowledge about pipelining and parallel processing of IIR filters..

UNIT IV BIT - LEVEL ARITHMETIC ARCHITECTURES (09)

Bit - level arithmetic R1 477-478 BB
26. architectures 1 28
W4 1-38 PPT
Parallel multipliers
27. R1 478-481 BB 1 29
with sign extension
Parallel carry - ripple
28. and carry - save R1 481-483 BB 1 30
multipliers
Design of Lyons bit -
29. serial multipliers R1 490-495 BB 1 31
using Horners rule
30. Bit - serial FIR filter R1 499-501 BB 1 32
31. CSD representation R1 505-507 BB 1 33
CSD multiplication
using Horners rule
32. R1 507-511 BB 1 34
for precision
improvement
Distributed
Arithmetic
33. R1 511-518 BB 2 36
fundamentals and
FIR filters

LEARNING OUTCOME
At the end of unit, students should be able to
Understand the concepts of various Bit level arithmetic architectures.
Describe Horners rule for Lyons bit serial multipliers.
Acquire knowledge about the arithmetic fundamentals used in FIR filter.
UNIT V NUMERICAL STRENGTH REDUCTION, WAVE AND ASYNCHRONOUS
PIPELINING (09)
Numerical strength R1 BB
34. 559 1 37
reduction W5 PPT
Sub expression
35. R1 560 BB 1 38
elimination
Multiple constant
36. R1 560-566 BB 1 39
multiplication
37. Iterative matching R1 561-562 BB 1 40
No. of Cumulative
Topic Books for Teaching
Topic Page No. Hours No. of
No Reference Methodology
Required periods

VLSI SP 6 KCE/I M.E VLSI / VLSI SP

FORMAT : QP09 KCE/DEPT. OF ECE

Synchronous
38 pipelining and R1 593-600 BB 1 41
clocking styles
39. Clock skew in edge R1 601-602 BB 1 42
Triggered single
40. phase clocking, R1 602-603 BB 1 43
Two phase
604
41. Clocking, R1 BB 1 44
606-611
wave pipelining.
Asynchronous
pipelining bundled
42. R1 619-621 BB 1 45
data versus dual
rail protocol.
LEARNING OUTCOME
At the end of unit, students should be able to
Understand the concepts numerical reduction in pipelining.
Describe effectiveness of clock signals in the pipelining.
Acquire knowledge about asynchronous pipelining and dual rail protocol.
COURSE OUTCOME
At the end of the course, the students will be able to
Know about Pipelining in parallel processing of digital filters.
Get an idea about algorithmic reduction techniques.
Understand the concept of BIT level arithmetic algorithms in Pipelining.
Get familiar with various reduction technique and also know about clock signal operations
in pipeline.
CONTENT BEYOND THE SYLLABUS
1. Signal Processing in Neural Network Using VLSI Implementation.

INTERNAL ASSESSMENT DETAILS

TEST NO. I II MODEL

Topic Nos. 1-17 18-33 1-42
Date

Prepared by Verified By
Mr.P.Raja Pirian HOD/ECE

Approved by
PRINCIPAL

REVIEW SHEET

VLSI SP 7 KCE/I M.E VLSI / VLSI SP

FORMAT : QP09 KCE/DEPT. OF ECE

After Completion of syllabus

Faculty experience in handling / covering syllabus

Unit I :

Unit II :

Unit III :

Unit IV :

Unit V :

Difficulties (if any)

Feedback on University Question Paper

SIGNATURE OF STAFF HOD/ECE

VLSI SP 8 KCE/I M.E VLSI / VLSI SP