LAB3
LAB3
LAB3
LAB#3
( Due: See course web page )
Objective
Based on the experience from LAB#1&2, learn how to design, simulate, synthesize, program on
FPGA and test FSM(Finite State Machine) digital system using Altera Quartus II CAD SW and DE1
FPGA board.
Learn and become familiar with logic design using Verilog Hardware Description Language
Instructions
1. Your LAB#3 project name should be L3Cyyy, where yyy=your CID(e.g., L3C079 if your CID=079).
2. [Golden Solution] The golden solution .pof and .sof files are provided. In any LAB, student must
play with golden solution as a reference whenever he/she has a question during design. Also check with
golden solution before going to Demo to make sure your design follows it. Do not forget reading " Rules
when you use a golden solution:" in LAB#1 document.
2. Use Verilog HDL design. Use the following Verilog top-level module interface code for your design.
No part of this code is allowed to be modified. The top-level module name must be same as your LAB
project name.
module L3Cyyy( // where yyy=your CID. For example, L3C079 if your CID=079
input [9:0] sw, // ten up-down switches, SW9 - SW0
input [3:0] key, // four pushbutton switches, KEY3 - KEY0
input clock, // 24MHz clock source on Altera DE1 board
output [9:0] ledr, // ten Red LEDs, LEDR9 - LEDR0
output [7:0] ledg, // eight Green LEDs, LEDG8 - LEDG0
output reg [6:0] hex0, hex1, hex2, hex3 // four 7-segment, HEX3 - HEX0
);
3. Our acceptable timing margin for real-time clock operation is -30% and +30%.
Soda VM(Vending Machine) Controller Design
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A vending machine company requests you to design a Soda Vending Machine(VM) controller circuit
with following specifications. The price of a soda was set to 35 cents.
1) Initial state
When power is turned on, your DE1 board must be in the following initial state:
all SWs are in DOWN position
no key is PRESSED
all leds(ledg and ledr) are OFF
VM is in stop state(i.e., not started yet)
HEX[3:0] displays your CID. For example, HEX[3:0]=0097 if your CID=097
(Reminder: Golden solution has HEX[3:0]=0353 since it's CID=353)
WARNING: DO NOT operate VM with more than one sw are UP(="Multiple SW input error").
ELSE IF sw[9] = 1 (with all other sw are down) { // This is Report mode. This is a pause (not reset!) operation.
hex[0] displays the total number of dispensing made only by coin input(NOT by One-doll-bill or
Credit-card-input!) since the board power was turned on.
Therefore, DO NOT make One-dollar-bill input or Credit-card input before testing sw[9]=1 function.
Only coin input is allowed BEFORE testing this condition.
hex[0] is in hex with modulo-16 format. hex[3:1] = OFF.
The sw[8](=Reset input) should NOT reset the total number of dispensing value to 0.
WARNING:
This sw[9]=1 operation pauses(not reset!) the current operation. Therefore it should NOT CHANGE
the value of current variables in your design, such as Deposit balance or Change balance. So, when
sw[9] returns back to 0(down, i.e., Normal mode), hex[3:0] must resume displaying the previous
value that it was displaying before sw[9] went 1(up). For example, hex[3:0]= 3515 if it had been
displaying 3515.
}
3) Dispensing indication
Whenever the Deposit balance is 35 or more, a dispensing occurs with following action(s).
(For example, a dispensing occurs after three dimes followed by a quarter(=55 cents) )
When NOT dispensing, all LEDs(i.e., both green and red) are OFF.
When dispensing, all green LEDs(ledg[7:0]) are blinking(half-second period with 50% duty cycle)
4.3) Credit Card input when hex[3:0]=3500 and LEDG blinking(i.e., when Deposit=35 and Change=00)
This is another error case when hex[3:0] should display "Err ".
How to clear(=reset) the "Err " display and continue normal operation?
The "Err " display should be cleared to hex[3:0]=0000(i.e., value of Deposit and Change balance are reset to
zero) by either pressing EnterKey or Reset input. Then normal operation can continue.