Lab Workbook SDK Lab

SDK Lab
Introduction
This lab guides you through the process of adding timer and interrupt controller to an embedded system
and writing a software application that utilizes these timer and interrupt controller. The SDK will be used
to create and debug the software application.

Objectives
After completing this lab, you will be able to:

Utilize the XPS timer with interrupt controller

Assign an interrupt handler to the timer
Develop an interrupt handler function
Use SDK Debugger to set break points and view the content of variables and memory

Design Description
The purpose of this lab exercise is to extend the hardware design created in lab 5 to include an XPS
interrupt controller and XPS Timer (see Figure 5-1). You will develop an interrupt handler to count the
interrupts generated from the timer.

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Figure 1. Design Updated from Previous Lab

Procedure
This lab is separated into steps that consist of general overview statements that provide information on
the detailed instructions that follow. Follow these detailed instructions to progress through the lab.

This lab comprises 5 primary steps: You will add a timer and interrupt controller, create an SDK software
project, write an interrupt handler, add linker script and, finally, verify operation in hardware.
Note: If you are unable to complete the lab at this time, you can download the original lab files for this
module from the Xilinx University Program site at http://www.xilinx.com/university

General Flow for this Lab

Step 1: Add Step 2: Step 3: Step 4: Step 5:
a Timer and Create an Write an Add Linker Verify
Interrupt SDK Interrupt Script Operation in
Controller Software Handler Hardware
Project

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Add a Timer and Interrupt Controller Step 1

1-1. Create a lab5 folder and copy the contents of the lab4 folder into the lab5
folder, or copy the content of the labsolution\ lab4 folder into the lab5
folder. Launch Xilinx Platform Studio (XPS) and open the project file.

1-1-1. Create a lab5 folder in the C:\ xup\ embedded\ labs directory and copy the contents from lab4 to
lab5, or copy the content of the labsolution\ lab4 folder into the lab5 folder.

1-1-2. Open XPS by selecting Start All Programs Xilinx ISE Design Suite 13.2 EDK
Xilinx Platform Studio.

1-1-3. Browse to the lab5 directory and open the project system.xmp.

1-2. Add the XPS timer and XPS Interrupt Controller peripherals to the design
from the IP Catalog, and connect them to the system according to the
following table.

xps_intc_0 instance
Intr timer1
Irq Microblaze_0_INTERRU
PT
delay instance
CaptureTrig0 net_gnd
Interrupt timer1
microblaze_0 instance
INTERRUPT Microblaze_0_INTERRU
PT

1-2-1. Add the XPS Timer/Counter peripheral from the DMA and Timer section of the IP Catalog,
check Only One Timer is present option, and change its instance name to delay.

1-2-2. Add the XPS Interrupt Controller peripheral from the Clock, Reset, and Interrupt section of the
IP Catalog with default settings.

1-2-3. Connect the timer and interrupt controller device to the PLB bus (see Figure 2).

Figure 2. Add and Connect the Interrupt Controller and Timer Peripherals

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1-2-4. Select Address tab and click Generate Addresses.

1-2-5. The generated addresses should look similar to that indicated in the figure below:

Figure 3. Generate Addresses for Interrupt Controller and Timer peripherals

1-2-6. In the Ports section, type in timer1 as the Interrupt port connection of the delay instance, and
hit Enter key.

1-2-7. Make a new net connection (see Figure 4) for the INTERRUPT (external interrupt request) port
on the microblaze_0 instance by selecting New Connection from the drop-down box. This will
create a net called microblaze_0_INTERRUPT.

Figure 4. Make a new net connection to connect the MicroBlaze Interrupt port

1-2-8. Connect the interrupt controller and timer as follows (refer to Figure 5).
Connect interrupt output port Irq of the xps_intc_0 instance to the MicroBlaze interrupt input
port using the microblaze_0_INTERRUPT net.
Click in intr field of xps_intc_0 field to open the Interrupt Connection Dialog. Click on
timer1 on left side, and click on sign to add to the Connected Interrupts field (right),
and then click OK.

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Figure 5. Connecting the Timer and Interrupt Controller

Connect CaptureTrig0 port of delay instance to net_gnd to avoid erroneous interrupt request
generated due to noise on the unconnected input port.

Figure 6. Connections Snapshot between Timer and Interrupt Controller

1-2-9. Select Hardware Generate Bitstream to generate new system.bit file.

Create an SDK Software Project Step 2

2-1. Launch SDK and create a new software application project for the lab5 XPS
project. Import the lab5.c source file.
Skip steps starting from 2-1-3 to 2-1-7 and remove lab4.c, if you were
continuing with lab4.

2-1-1. Open SDK by selecting Project Export Hardware Design to SDK...

2-1-2. Click on Export & Launch SDK button with default setting and browse to
C:\xup\embedded\labs\lab5\SDK\SDK_Export.

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This will implement the design if necessary and generate system.bit and system_bd.bmm

Figure 7. Export to SDK and Launch SDK

Skip steps starting from 2-1-3 to 2-1-7 and remove lab4.c, if you were continuing with lab4.

2-1-3. Click on File in the Xilinx SDK window and select New Xilinx C Project.

2-1-4. Enter lab5 in the Project Name field and choose Empty Application in Project type window.

2-1-5. Click Next, Enter Testapp in the Project name field.

2-1-6. Click Finish.

2-1-7. Select lab5 in the project view, right-click, and select Import.

2-1-8. Extend the General folder and double-click on File System and browse to
c:\ xup\ embedded\ lab\source. Select lab5.c and click Finish.

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Figure 8. Importing Source Code

2-1-9. Note that both the Problems and Console tabs on the bottom report several compilation errors
Note also that the project outline on the right side is updated to reflect the libraries and routines
used in the source file.

2-2. Correct the errors.

2-2-1. In the Problems tab, double-click on the first red x for the parse error. This will open the source
file bring you around to the error place.

Figure 9. First Error

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2-2-2. Add the missing global variable declaration as unsigned int, initialize it to the value of 1, and
save the file. The first error message should disappear.

2-2-3. Click the next error message to highlight the problem in the source code.

Figure 10. Second Error

2-2-4. Add the missing global variable declaration as int, inititalize it to the value of 0, and save the file.
The additional error messages should disappear.

Write an Interrupt Handler Step 3

3-1. Create the interrupt handler for the XPS timer.

3-1-1. Go to where the interrupt handler function has already been stubbed out in the source file (a fast
way to do this is to click on the function in the outline view).

3-1-2. Create new local variable for the timer_int_handler function:

unsigned int csr;

3-2. The first step in creating an XPS timer interrupt handler is to verify that the
XPS timer caused the interrupt. This can be determined by looking at the
XPS Timer Control Status Register. Open the API documentation to
determine how the Control Status Register works.

3-2-1. In the XPS System Assembly View window, right-click the delay instance and select View PDF
Datasheet to open the data sheet.

3-2-2. Go to the Register Description section in the data sheet and study the TCSR0 Register. Notice
that bit 23 has the following description:

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Timer0 Interrupt

Indicates that the condition for an interrupt on this timer has occurred. If the timer mode is capture
and the timer is enabled, this bit indicates a capture has occurred. If the mode is generate, this bit
indicates the counter has rolled over. Must be cleared by writing a 1
Read:
0 - No interrupt has occurred

1 - Interrupt has occurred

Write:
0 No change in state of T0INT

1 Clear T0INT (clear to 0)

The level 0 driver for the XPS timer provides two functions that read and write to the Control
Status Register. View the timer API doc by right-clicking on the delay instance in the System
Assembly View and selecting Driver:tmrctr_v2_00_a View API Documentation. In the API
document, click on the File List link at the top of the document, then click on the link labeled
xtmrctr_l.h in the file list. This brings up the document on identifiers and the low-level driver
functions declared in this header file. Scroll down in the document and click on the link for the
XTmrCtr_GetControlStatusReg( ) function to read more about this function. Use this function to
determine whether an interrupt has occurred. The following is the pertinent information found in
the XPS timer documentation:

XTmrCtr_GetControlStatusReg ( BaseAddress, TmrCtrNumber )

Get the Control Status Register of a timer counter

o Parameters:
BaseAddress is the base address of the device.
TmrCtrNumber is the specific timer counter within the device, a zero-based number, 0
(XTC_DEVICE_TIMER_COUNT - 1)
o Returns:
The value read from the register, a 32-bit value

3-2-3. Add the XTmrCtr_GetControlStatusReg function call to the code with the associated
parameters. The resulting 32-bit return value should be stored in the variable csr.

csr=XTmrCtr_GetControlStatusReg(XPAR_DELAY_BASEADDR,0);

Note: Substitute XPAR_DELAY_BASEADDR with the base address for the delay peripheral.
Refer to xparameters.h

3-2-4. Complete the Interrupt handler (see Figure 11) according to the steps below:

Test to see if bit 23 is set by ANDing csr with the XTC_CSR_INT_OCCURED_MASK parameter.

Increment a counter if an interrupt was taken.

Display the count value by using the LEDs_8Bit peripheral and print the value using xil_printf
(same functionality as printf with the exception of floating-point handling)

Hint: You may use the XGpio_DiscreteWrite () function

Clear the interrupt by using the following function call:

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XTmrCtr_SetControlStatusReg(baseaddr, 0, csr);

The completed handler should look like as shown in the next figure

Figure 11. Completed Interrupt Handler Code

3-2-5. Save the file, this should compile the source successfully.

Add Linker Script Step 4

4-1. Generate the linker script by assigning code section to ilmb and data
section to xps_bram. Set heap and stack to 0x400 each.

4-1-1. Right-click Testapp in project view and select Generate Linker Script.

4-1-2. Set the heap and stack size to 0x400 (1024) each.

4-1-3. Assign Code section to ilmb_cntlr_dlmb_cntlr and Data, Stack and Heap sections to
xps_bram_if_cntlr(this is necessary as each of the memory is too small to hold everything).

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Figure 12. Generate Linker Script

4-1-4. Click Generate to generate the linker script, add to the project and recompile the program.

4-1-5. Look in the console to answer the following question:

Question 1
What is the size of the compiled program?

.text segment: ____________________

.data segment: ____________________
.bss segment: ____________________
Total in decimal: ____________________
Total in hexadecimal: ____________________

Verify Operation in Hardware Step 5

5-1. Download to the xc3s500efg320-4 Board.

5-1-1. Connect and power the board.

5-1-2. Select Xilinx Tools Program FPGA.

5-1-3. Browse and select system.bit and system_bd.bmm files from the lab5\ implementation (this
step is required for 12.2 version. For other version, you may skip this step and try with the default
paths to see if it works).

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Figure 13. Setting Up Run Configuration

5-1-4. Click Program.

This will execute Data2Mem program to combine the bootloop executable with hardware
bitstream, generate the download.bit file, and configure the FPGA.

5-1-5. Select Terminal tab (near console area), and click on New Terminal Connection
( ).

5-1-6. Select serial as connection type and correct COM port and 115200 baud rate, and click OK.

5-2. Launch Debugger and debug.

5-2-1. Select Testapp, from the SDK Menu, select Run Run configurations ...

This will present a screen summarizing the existing Launch Configurations.

5-2-2. Under Configurations, select Xilinx C/C++ ELF.

5-2-3. Right click on it then select New to add a new Launch configuration.

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Figure 14. Setting Up Run Configuration

5-2-4. Click on the Run button. The application will run. You should see messages in the Console and
the LEDs should be flickering.

Figure 15. Resuming an Application

5-2-5. Click Debug to invoke the debug session.

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5-2-6. Click YES to stop the current execution. Click YES to launch the Debug perspective.

5-2-7. Right click in the Variables tab and select Add Global Variables... All global variables will be
displayed. Select count variable and click OK.

5-3. Monitor variables and memory content.

5-3-1. Double-click to set a breakpoint on the line in lab5.c where count is written to LED.

Figure 16. Setting Breakpoint

5-3-2. Click on Resume button to continue executing the program up until the breakpoint.

5-3-3. Click on the memory tab. If you do not see it, go to Window Show View Memory.

5-3-4. Click the sign to add a Memory Monitor.

Figure 17. Adding Memory Address

5-3-5. Enter the address for the count variable as follows, and click OK.

Figure 18. Monitoring a Variable

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5-3-6. Click the Resume button to continue execution of the program.

Notice that the count variables increment every time you click resume.

Figure 19. Viewing Memory Content of the count variable

5-3-7. Terminate the session by clicking on the Terminate button.

Figure 20. Terminating a Debug Session

5-3-8. Close the SDK application and close the XPS project.

Conclusion
This lab led you through adding an XPS timer and interrupt controller, and assigning an interrupt handler
function to the interrupting device via the software platform settings. You developed an interrupt handler
function and tested it in hardware. Additionally, you used the SDK debugger to view the content of
variables and memory.

Answer
1. What is the size of the compiled program?

.text segment: 6706

.data segment: 388
.bss segment: 2118
Total in decimal: 9212
Total in hexadecimal: 23fc

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Completed MHS File

# ##############################################################################
# Created by Base System Builder Wizard for Xilinx EDK 13.2 Build EDK_O.61xd
# Tue Jul 12 06:55:41 2011
# Target Board: Xilinx Spartan-3E Starter Board Rev D
# Family: spartan3e
# Device: XC3S500e
# Package: FG320
# Speed Grade: -4
# Processor number: 1
# Processor 1: microblaze_0
# System clock frequency: 50.0
# Debug Interface: On-Chip HW Debug Module
# ##############################################################################
PARAMETER VERSION = 2.1.0

PORT fpga_0_RS232_DCE_RX_pin = fpga_0_RS232_DCE_RX_pin, DIR = I

PORT fpga_0_RS232_DCE_TX_pin = fpga_0_RS232_DCE_TX_pin, DIR = O
PORT fpga_0_LEDs_8Bit_GPIO_IO_O_pin = fpga_0_LEDs_8Bit_GPIO_IO_O_pin, DIR = O, VEC =
[0:7]
PORT fpga_0_DDR_SDRAM_DDR_Clk_pin = fpga_0_DDR_SDRAM_DDR_Clk_pin, DIR = O
PORT fpga_0_DDR_SDRAM_DDR_Clk_n_pin = fpga_0_DDR_SDRAM_DDR_Clk_n_pin, DIR = O
PORT fpga_0_DDR_SDRAM_DDR_CE_pin = fpga_0_DDR_SDRAM_DDR_CE_pin, DIR = O
PORT fpga_0_DDR_SDRAM_DDR_CS_n_pin = fpga_0_DDR_SDRAM_DDR_CS_n_pin, DIR = O
PORT fpga_0_DDR_SDRAM_DDR_RAS_n_pin = fpga_0_DDR_SDRAM_DDR_RAS_n_pin, DIR = O
PORT fpga_0_DDR_SDRAM_DDR_CAS_n_pin = fpga_0_DDR_SDRAM_DDR_CAS_n_pin, DIR = O
PORT fpga_0_DDR_SDRAM_DDR_WE_n_pin = fpga_0_DDR_SDRAM_DDR_WE_n_pin, DIR = O
PORT fpga_0_DDR_SDRAM_DDR_BankAddr_pin = fpga_0_DDR_SDRAM_DDR_BankAddr_pin, DIR =
O, VEC = [1:0]
PORT fpga_0_DDR_SDRAM_DDR_Addr_pin = fpga_0_DDR_SDRAM_DDR_Addr_pin, DIR = O, VEC =
[12:0]
PORT fpga_0_DDR_SDRAM_DDR_DQ_pin = fpga_0_DDR_SDRAM_DDR_DQ_pin, DIR = IO, VEC =
[15:0]
PORT fpga_0_DDR_SDRAM_DDR_DM_pin = fpga_0_DDR_SDRAM_DDR_DM_pin, DIR = O, VEC =
[1:0]
PORT fpga_0_DDR_SDRAM_DDR_DQS_pin = fpga_0_DDR_SDRAM_DDR_DQS_pin, DIR = IO, VEC
= [1:0]
PORT fpga_0_DDR_SDRAM_ddr_dqs_div_io_pin = fpga_0_DDR_SDRAM_ddr_dqs_div_io_pin, DIR =
IO
PORT fpga_0_clk_1_sys_clk_pin = CLK_S, DIR = I, SIGIS = CLK, CLK_FREQ = 50000000
PORT fpga_0_rst_1_sys_rst_pin = sys_rst_s, DIR = I, SIGIS = RST, RST_POLARITY = 1
PORT dip_GPIO_IO_I_pin = dip_GPIO_IO_I, DIR = I, VEC = [0:3]
PORT push_GPIO_IO_I_pin = push_GPIO_IO_I, DIR = I, VEC = [0:3]
PORT lcd_ip_0_lcd_pin = lcd_ip_0_lcd, DIR = O, VEC = [0:6]

BEGIN microblaze
PARAMETER INSTANCE = microblaze_0
PARAMETER C_AREA_OPTIMIZED = 1
PARAMETER C_USE_BARREL = 1
PARAMETER C_DEBUG_ENABLED = 1
PARAMETER HW_VER = 8.20.a
BUS_INTERFACE DLMB = dlmb
BUS_INTERFACE ILMB = ilmb
BUS_INTERFACE DPLB = mb_plb

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BUS_INTERFACE IPLB = mb_plb

BUS_INTERFACE DEBUG = microblaze_0_mdm_bus
PORT MB_RESET = mb_reset
PORT INTERRUPT = microblaze_0_INTERRUPT
END

BEGIN plb_v46
PARAMETER INSTANCE = mb_plb
PARAMETER HW_VER = 1.05.a
PORT PLB_Clk = clk_50_0000MHz
PORT SYS_Rst = sys_bus_reset
END

BEGIN lmb_v10
PARAMETER INSTANCE = ilmb
PARAMETER HW_VER = 2.00.b
PORT LMB_Clk = clk_50_0000MHz
PORT SYS_Rst = sys_bus_reset
END

BEGIN lmb_v10
PARAMETER INSTANCE = dlmb
PARAMETER HW_VER = 2.00.b
PORT LMB_Clk = clk_50_0000MHz
PORT SYS_Rst = sys_bus_reset
END

BEGIN lmb_bram_if_cntlr
PARAMETER INSTANCE = dlmb_cntlr
PARAMETER HW_VER = 3.00.b
PARAMETER C_BASEADDR = 0x00000000
PARAMETER C_HIGHADDR = 0x00001fff
BUS_INTERFACE SLMB = dlmb
BUS_INTERFACE BRAM_PORT = dlmb_port
END

BEGIN lmb_bram_if_cntlr
PARAMETER INSTANCE = ilmb_cntlr
PARAMETER HW_VER = 3.00.b
PARAMETER C_BASEADDR = 0x00000000
PARAMETER C_HIGHADDR = 0x00001fff
BUS_INTERFACE SLMB = ilmb
BUS_INTERFACE BRAM_PORT = ilmb_port
END

BEGIN bram_block
PARAMETER INSTANCE = lmb_bram
PARAMETER HW_VER = 1.00.a
BUS_INTERFACE PORTA = ilmb_port
BUS_INTERFACE PORTB = dlmb_port
END

BEGIN xps_uartlite
PARAMETER INSTANCE = RS232_DCE
PARAMETER C_BAUDRATE = 115200
PARAMETER C_DATA_BITS = 8
PARAMETER C_USE_PARITY = 0
PARAMETER C_ODD_PARITY = 0

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PARAMETER HW_VER = 1.02.a

PARAMETER C_BASEADDR = 0x84000000
PARAMETER C_HIGHADDR = 0x8400ffff
BUS_INTERFACE SPLB = mb_plb
PORT RX = fpga_0_RS232_DCE_RX_pin
PORT TX = fpga_0_RS232_DCE_TX_pin
END

BEGIN xps_gpio
PARAMETER INSTANCE = LEDs_8Bit
PARAMETER C_ALL_INPUTS = 0
PARAMETER C_GPIO_WIDTH = 8
PARAMETER C_INTERRUPT_PRESENT = 0
PARAMETER C_IS_DUAL = 0
PARAMETER HW_VER = 2.00.a
PARAMETER C_BASEADDR = 0x81440000
PARAMETER C_HIGHADDR = 0x8144ffff
BUS_INTERFACE SPLB = mb_plb
PORT GPIO_IO_O = fpga_0_LEDs_8Bit_GPIO_IO_O_pin
END

BEGIN mpmc
PARAMETER INSTANCE = DDR_SDRAM
PARAMETER C_NUM_PORTS = 1
PARAMETER C_SPECIAL_BOARD = S3E_STKIT
PARAMETER C_MEM_TYPE = DDR
PARAMETER C_MEM_PARTNO = MT46V32M16-6
PARAMETER C_MEM_DATA_WIDTH = 16
PARAMETER C_PIM0_BASETYPE = 2
PARAMETER HW_VER = 6.04.a
PARAMETER C_MPMC_BASEADDR = 0x8c000000
PARAMETER C_MPMC_HIGHADDR = 0x8fffffff
BUS_INTERFACE SPLB0 = mb_plb
PORT MPMC_Clk0 = clk_100_0000MHzDCM0
PORT MPMC_Clk90 = clk_100_0000MHz90DCM0
PORT MPMC_Rst = sys_periph_reset
PORT DDR_Clk = fpga_0_DDR_SDRAM_DDR_Clk_pin
PORT DDR_Clk_n = fpga_0_DDR_SDRAM_DDR_Clk_n_pin
PORT DDR_CE = fpga_0_DDR_SDRAM_DDR_CE_pin
PORT DDR_CS_n = fpga_0_DDR_SDRAM_DDR_CS_n_pin
PORT DDR_RAS_n = fpga_0_DDR_SDRAM_DDR_RAS_n_pin
PORT DDR_CAS_n = fpga_0_DDR_SDRAM_DDR_CAS_n_pin
PORT DDR_WE_n = fpga_0_DDR_SDRAM_DDR_WE_n_pin
PORT DDR_BankAddr = fpga_0_DDR_SDRAM_DDR_BankAddr_pin
PORT DDR_Addr = fpga_0_DDR_SDRAM_DDR_Addr_pin
PORT DDR_DQ = fpga_0_DDR_SDRAM_DDR_DQ_pin
PORT DDR_DM = fpga_0_DDR_SDRAM_DDR_DM_pin
PORT DDR_DQS = fpga_0_DDR_SDRAM_DDR_DQS_pin
PORT DDR_DQS_Div_O = fpga_0_DDR_SDRAM_ddr_dqs_div_io_pin
PORT DDR_DQS_Div_I = fpga_0_DDR_SDRAM_ddr_dqs_div_io_pin
END

BEGIN clock_generator
PARAMETER INSTANCE = clock_generator_0
PARAMETER C_CLKIN_FREQ = 50000000
PARAMETER C_CLKOUT0_FREQ = 100000000
PARAMETER C_CLKOUT0_PHASE = 90
PARAMETER C_CLKOUT0_GROUP = DCM0

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PARAMETER C_CLKOUT0_BUF = TRUE

PARAMETER C_CLKOUT1_FREQ = 100000000
PARAMETER C_CLKOUT1_PHASE = 0
PARAMETER C_CLKOUT1_GROUP = DCM0
PARAMETER C_CLKOUT1_BUF = TRUE
PARAMETER C_CLKOUT2_FREQ = 50000000
PARAMETER C_CLKOUT2_PHASE = 0
PARAMETER C_CLKOUT2_GROUP = NONE
PARAMETER C_CLKOUT2_BUF = TRUE
PARAMETER C_EXT_RESET_HIGH = 1
PARAMETER HW_VER = 4.02.a
PORT CLKIN = CLK_S
PORT CLKOUT0 = clk_100_0000MHz90DCM0
PORT CLKOUT1 = clk_100_0000MHzDCM0
PORT CLKOUT2 = clk_50_0000MHz
PORT RST = sys_rst_s
PORT LOCKED = Dcm_all_locked
END

BEGIN mdm
PARAMETER INSTANCE = mdm_0
PARAMETER C_MB_DBG_PORTS = 1
PARAMETER C_USE_UART = 1
PARAMETER HW_VER = 2.00.b
PARAMETER C_BASEADDR = 0x84400000
PARAMETER C_HIGHADDR = 0x8440ffff
BUS_INTERFACE SPLB = mb_plb
BUS_INTERFACE MBDEBUG_0 = microblaze_0_mdm_bus
PORT Debug_SYS_Rst = Debug_SYS_Rst
END

BEGIN proc_sys_reset
PARAMETER INSTANCE = proc_sys_reset_0
PARAMETER C_EXT_RESET_HIGH = 1
PARAMETER HW_VER = 3.00.a
PORT Slowest_sync_clk = clk_50_0000MHz
PORT Ext_Reset_In = sys_rst_s
PORT MB_Debug_Sys_Rst = Debug_SYS_Rst
PORT Dcm_locked = Dcm_all_locked
PORT MB_Reset = mb_reset
PORT Bus_Struct_Reset = sys_bus_reset
PORT Peripheral_Reset = sys_periph_reset
END

BEGIN xps_gpio
PARAMETER INSTANCE = dip
PARAMETER HW_VER = 2.00.a
PARAMETER C_GPIO_WIDTH = 4
PARAMETER C_ALL_INPUTS = 1
PARAMETER C_BASEADDR = 0x81420000
PARAMETER C_HIGHADDR = 0x8142ffff
BUS_INTERFACE SPLB = mb_plb
PORT GPIO_IO_I = dip_GPIO_IO_I
END

BEGIN xps_gpio
PARAMETER INSTANCE = push
PARAMETER HW_VER = 2.00.a

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PARAMETER C_GPIO_WIDTH = 4
PARAMETER C_ALL_INPUTS = 1
PARAMETER C_BASEADDR = 0x81400000
PARAMETER C_HIGHADDR = 0x8140ffff
BUS_INTERFACE SPLB = mb_plb
PORT GPIO_IO_I = push_GPIO_IO_I
END

BEGIN lcd_ip
PARAMETER INSTANCE = lcd_ip_0
PARAMETER HW_VER = 1.00.a
PARAMETER C_BASEADDR = 0xcf400000
PARAMETER C_HIGHADDR = 0xcf40ffff
BUS_INTERFACE SPLB = mb_plb
PORT lcd = lcd_ip_0_lcd
END

BEGIN bram_block
PARAMETER INSTANCE = bram_block_0
PARAMETER HW_VER = 1.00.a
BUS_INTERFACE PORTA = xps_bram_if_cntlr_0_PORTA
END

BEGIN xps_bram_if_cntlr
PARAMETER INSTANCE = xps_bram_if_cntlr_0
PARAMETER HW_VER = 1.00.b
PARAMETER C_SPLB_NATIVE_DWIDTH = 32
PARAMETER C_BASEADDR = 0x88208000
PARAMETER C_HIGHADDR = 0x88209fff
BUS_INTERFACE SPLB = mb_plb
BUS_INTERFACE PORTA = xps_bram_if_cntlr_0_PORTA
END

BEGIN xps_timer
PARAMETER INSTANCE = delay
PARAMETER HW_VER = 1.02.a
PARAMETER C_ONE_TIMER_ONLY = 1
PARAMETER C_BASEADDR = 0x83c00000
PARAMETER C_HIGHADDR = 0x83c0ffff
BUS_INTERFACE SPLB = mb_plb
PORT Interrupt = timer1
PORT CaptureTrig0 = net_gnd
END

BEGIN xps_intc
PARAMETER INSTANCE = xps_intc_0
PARAMETER HW_VER = 2.01.a
PARAMETER C_BASEADDR = 0x81800000
PARAMETER C_HIGHADDR = 0x8180ffff
BUS_INTERFACE SPLB = mb_plb
PORT Irq = microblaze_0_INTERRUPT
PORT Intr = timer1
END

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