Super-Regenerative Receiver For UWB-FM Rui - Hou - 2008 PDF
Super-Regenerative Receiver For UWB-FM Rui - Hou - 2008 PDF
Super-Regenerative Receiver For UWB-FM Rui - Hou - 2008 PDF
Rui Hou
Department of Microelectronics
Rui Hou
Master of Science
in
Microelectronics
Supervisors:
Nitz Saputra
Thesis committee:
Nitz Saputra
signed for short-range, low- and medium-data-rate wireless applications such as the
personal area network (PAN). These applications often require simple, integrated
This coherent detection method oers the best performance in general but is not
2 GHz RF bandwidth.
The goal of this research is to explore the possibility of reducing power consump-
4.5 GHz. Circuit simulations show that a receiver sensitivity of -82.2 dB is attainable
for a 100 kbps baseband data-rate and 106 bit-error-rate. The whole receiver draws
This work is, according to the author's knowledge, the rst time the super-
regeneration principle is used for UWB-FM detection. The 1.8 mW power dissipation
is also by far the smallest among UWB-FM receivers reported in the literature.
the quenching waveform for WBFM detection and a novel low-power driven design
i
ii
Acknowledgments
The work presented in this thesis could not have been done without the help and
for his constant guidance and support. I have beneted greatly from his expertise,
Additionally, I am very grateful to Ph.D student Nitz Saputra, who is also taken
care of my work from beginning to end. His broad knowledge has brought me out
of trouble quite a few times. Our discussions are always delightful, full of insights
and enlightenment. I thank him for his valuable feedback regarding my thesis.
I would also like to thank the committee members, Prof. Leo de Vreede and
Prof. Ko Makinwa for their time reading this thesis and attending the defense.
Working in the Electronics group has been quite a pleasant experience, due to
the kind and intelligent people there. In particular, I thank my college student
Yixiong Hu and Yousif Shamsa. We have been cooperating for two years, and it has
This two years studying in Delft University of Technology has been colorful and
the professors and teachers who gave me lectures and trainings. Evidently, I will
benet from the knowledge they imparted for the rest of my life. I thank all my
Last but not least, I am deeply thankful for the love, encouragement and support
Rui Hou
iii
iv
Contents
1 Introduction 1
1.1 Motivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
2 Background 3
2.1 UWB-FM Modulation Scheme . . . . . . . . . . . . . . . . . . . . . . 3
3 Super-regeneration 7
3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3.4.3 Gain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.5 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4 Architecture Design 21
4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
v
vi CONTENTS
4.2.3.2 Linearity . . . . . . . . . . . . . . . . . . . . . . . . 25
4.3.2 Limiter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
4.3.3 FM Discriminator . . . . . . . . . . . . . . . . . . . . . . . . 28
4.3.4 AM Demodulator . . . . . . . . . . . . . . . . . . . . . . . . . 31
5.4.3.1 Minimum Ft . . . . . . . . . . . . . . . . . . . . . . 64
5.4.4.1 Unilateralization . . . . . . . . . . . . . . . . . . . . 67
5.4.4.2 Neutralization . . . . . . . . . . . . . . . . . . . . . 68
5.4.5.2 Neutralization . . . . . . . . . . . . . . . . . . . . . 70
6 Auxiliary Circuits 80
6.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
6.2.4.1 Specication . . . . . . . . . . . . . . . . . . . . . . 82
6.3.2.1 Comparator . . . . . . . . . . . . . . . . . . . . . . . 88
8 Conclusions 114
8.1 Summary of Results . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
Bibliography 117
List of Figures
UWB signal. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
4.7 The spectrum of the UWB-FM signal at the input of the receiver. . 34
4.10 The simulated baseband signal, oscillations, their envelopes and the
quenching waveform. . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
5.5 The waveform of the total conductance and the tail current for the
SRO. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
5.8 The baseband signal, output oscillations and the SRO biasing current. 52
ix
x LIST OF FIGURES
6.11 The transient simulation result of the LNA under dynamic biasing. . 93
6.15 Voltage output of the peak detector and the buered version. . . . . 98
7.6 The dynamic biasing circuits for the SRO and the LNA. . . . . . . . 109
7.7 Delay-line voltages and biasing currents of the SRO and the LNA. . 110
5.3 Output SNR vs. LNA transconductance and noise gure budget. . . 60
7.1 The comparison of current consumption between the slope- and step-
xii
Chapter 1
Introduction
1.1 Motivation
During the last 10 years, the rapidly advanced short-range communication tech-
nologies are creating new opportunities for interconnections such as personal area
networks (PAN) and wireless sensor networks (WSN). These networks have many
network nodes are necessarily simple and highly integrated so they can be massively
produced to reduce the cost. Low power consumption is also an indispensable fea-
ture for these devices, since consumer products with bulky batteries are unattractive
between distributed nodes. Reducing its cost and power consumption leads to global
cost and power saving, comfortably portable consumer products and extended life-
for short-range, low- and medium-data-rate (LDR and MDR) PAN and WSN ap-
is the process of amplifying radio frequency (RF) signals through the periodically
1
2 CHAPTER 1. INTRODUCTION
objective.
for UWB-FM applications. Chapter 2 provides the background about the UWB-FM
modulation scheme, previous work and the current approach. Chapter 3 analyzes
5 concentrates on the circuit design of the RF part of the receiver, including a super-
for WBFM detection and a novel low-power driven design procedure for the LNA.
Chapter 6 focuses on the circuit design of the analog part of the receiver, including a
current saw-tooth waveform generator for the SRO, a dynamic biasing circuit for the
LNA, an output buer for testability and a current reference for biasing. In Chapter
7, the simulation set-up of the complete receiver is introduced and the simulation
result is presented. This chapter also details a global power reduction attempt and
an iteration of the design process. Chapter 8 concludes the thesis with a summary
Background
range, low- and medium-data-rate wireless applications [1]. This scheme involves
digital baseband signal, d (t), having a data rate of 20, 40 or 100 kbps, modulates
a triangular subcarrier of 1-2 MHz, m (t), using FSK with a modulation index of
1. The subcarrier, m (t), then modulates the RF carrier of 3-5 GHz, v (t), using
FM, to spread its spectrum to a bandwidth of 500 MHz. The modulation indexes
and the RF carrier frequency shown in the graph have been modied for the sake of
visibility.
The power spectrum of a UWB-FM signal centering at 4.5 GHz, being modu-
lated by a 1 MHz triangular wave, is shown in Fig. 2.2. The low-cost low-power
this research.
[11, 12]. The block diagram of such a demodulator is shown in Fig. 2.3. A delay
element rst converts the input FM signal into a PM signal. Then a multiplier,
operating as a phase detector, recovers the modulation signal. This coherent de-
tection scheme provides the best dynamic range in principle [13]. However, since a
mixer and a high gain amplier are used at the RF frequency, UWB-FM receivers
3
4 CHAPTER 2. BACKGROUND
Amplitude (V)
0.5
0
0.5
1
1.5
0 1 2 3 4 5 6
Time (us)
Subcarrier m(t)
1.5
1
Amplitude (V)
0.5
0
0.5
1
1.5
0 1 2 3 4 5 6
Time (us)
RF Carrier v(t)
1.5
1
Amplitude (V)
0.5
0
0.5
1
1.5
0 1 2 3 4 5 6
Time (us)
Figure 2.1: The time-domain waveform of the baseband data, subcarrier and UWB
signal.
40
Power Spectral Density (dBm/MHz)
45
50
55
60
65
70
4 4.1 4.2 4.3 4.4 4.5 4.6 4.7 4.8 4.9 5
Frequency (GHz)
Multiplier
Vrf Vdemod
Amplifier
frf fsub
Delay Element
ogy, consumes 9.6 mW power [11]. Another one including an LNA, implemented in
condition. Oscillations were periodically built up from weak RF excitation and then
since their drawbacks are also conspicuous. Firstly, super-regenerators are inherently
also an oscillator. The spurious emission of these receivers can easily cause inter-
simplicity and huge gain, are naturally a candidate architecture. Typically, this
type of receivers have been designed for simple narrow-band modulation schemes
such as on-o keying (OOK) [4, 5, 6, 7, 8, 9, 10], providing that proper measures
[14, 15] are taken to improve the poor selectivity and inherent frequency instability.
Occasionally, they were also used to detect spread spectrum [16, 17] and pulse based
6 CHAPTER 2. BACKGROUND
UWB signals [18, 19, 20], beneting from the alleviated selectivity and frequency-
detuned from the RF center frequency so as to generate variable gain for frequency
variation. Other techniques [22, 23] are also seen in the literature.
Chapter 3
Super-regeneration
3.1 Introduction
Super-regenerative receivers, despite their structural simplicity , are quasi-periodical
results the commonly used cut and try design methodology. In fact, the underlying
theory [3, 24] is so complex that it has never been understood by more than a handful
of people at a given time [25]. However, many trade-os occurring in this design
practice rely on the underlying mathematics, as will be presented in the rest of the
thesis.
Super-regenerative receivers have two modes of operations, the linear and the log-
arithmic mode. In the linear operation mode, growing-up oscillations are quenched
before the amplitude saturation shows its eect. In such a way, the peaking oscilla-
tion amplitude has a linear relationship with the initial RF excitation amplitude. In
contrast, the logarithmic operation mode quenches the oscillations after the ampli-
tude saturation. In doing so, all the pulses have the same amplitude. The dierent
excitation yields faster oscillation building-up, and vice versa. The duration of os-
nary dierential equation with variable coecients, whose analytical solution does
not necessarily exist. Therefore, this chapter focuses on the linear-mode response
of the system. Since the properties of the two modes dier only at the end of an
oscillation build-up cycle, many results obtained in this analysis are also relevant to
in Section 3.2 and solved in Section 3.3. Based on this solution, the characteristics
7
8 CHAPTER 3. SUPER-REGENERATION
Quenching
Oscillator
of a parallel RLC resonant tank. SROs originated from delay-line oscillators can be
they are mathematically equivalent, the rest of this chapter will use Fig. 3.1 as the
The dierential equation characterizing the time varying dynamical system shown
dv
(t) 1
C + G (t) v (t) + v (t) dt = i (t) . (3.1)
dt L
" #
G (t) 1 G (t) i (t)
v (t) + v (t) + + v (t) = , (3.2)
C LC C C
where
The waveforms of the varying conductance are shown in Fig. 3.2 and 3.3. A
quenching cycle starts from time 0. The total conductance of the tank is positive
during the period from time 0 to t1 , and negative during the period from t1 to t2 .
If the transition of conductance at t1 and t2 are slow, such that the regeneration
period includes many oscillation cycles, as shown in Fig. 3.2, the SRO is called
conductance at t1 and t2 are fast compared with oscillation cycles, as shown in Fig.
3.2. DRIVEN PARAMETRIC OSCILLATOR MODEL 9
G0
G(t) 1111111111
0000000000
0000000000
1111111111
0000000000
1111111111
0000000000
1111111111
0000000000
1111111111
A+
0000000000t111111
1111111111 00000
00000
11111
00000
11111
0 A t2 t
G1 00000
11111
Damping Regeneration Super Damping
regeneration
1 s(t)
0 t1 t2 t
1 p(t) 11111111111111111111
00000000000000000000
00000000000000000000
11111111111111111111
00000000000000000000
11111111111111111111
00000000000000000000
11111111111111111111
00000000000000000000
11111111111111111111
0 t111111111111111111111
00000000000000000000
t2 t
Figure 3.2: Slope-controlled state: the conductance G (t), sensitivity s (t) and pulse
envelope p (t).
G0
G(t) 1111111111
0000000000
0000000000
1111111111
0000000000
1111111111
0000000000
1111111111
0000000000
1111111111
A+
0000000000t111111
1111111111 00000
0 00000
11111
00000
11111
A t2 t
G1 00000
11111
Damping Super Damping
regeneration
1 s(t)
0 t1 t2 t
p(t) 1111111111111111111
0000000000000000000
0000000000000000000
1111111111111111111
1
0000000000000000000
1111111111111111111
0000000000000000000
1111111111111111111
0 t1
0000000000000000000
1111111111111111111
t2 t
Figure 3.3: Step-controlled state: the conductance G (t), sensitivity s (t) and pulse
envelope p (t).
10 CHAPTER 3. SUPER-REGENERATION
The division of receiver operation into two states is historical and articial. In
the following analysis, it will be shown that the generic solution suitable for all types
of waveforms is too general to be of any practical use. The two operation states are
the two extreme situations, whose solutions in closed analytical forms exist. The
operation using any other conductance waveforms, e.g. a sinusoidal wave, can be
variable coecients. The next section derives the solution of this equation.
can be represented as
" #
h i c1
v (t) = vz1 (t) vz2 (t) + vp (t) (3.4)
c2
where the rst term is the general solution and the second term, the particular
the dynamical system, when no stimulus is applied. The particular solution, on the
other hand, is the forced response, or zero-state response, of the dynamical system,
when a particular stimulus is applied to a system initiating from the relaxed state.
vector containing vz1 (t) and vz2 (t), is rst derived from the corresponding homo-
geneous equation. Then the particular solution, vp (t), is derived using the method
discussed.
3.2
h i
v (t) + 2 (t) 0 v (t) + 02 + 20 (t) v (t) = 0 , (3.5)
where
G (t)
(t) = (3.6)
2C0
is the time-varying damping factor, and
1
0 = (3.7)
LC
3.3. SOLUTION OF THE ODE 11
is the natural frequency. Equ. 3.5 represents an undriven parametric oscillator. The
t
v (t) = x (t) exp 0 (t) dt . (3.8)
0
t
v (t) = [x (t) 0 (t) x (t)] exp 0 (t) dt (3.9)
0
n h io t
2 2
v (t) = x (t) 20 (t) x (t) + x (t) 0 (t) 0 (t) exp 0 (t) dt
0
(3.10)
1
into Equ. 3.5 yields
h i
x (t) + 02 02 2 (t) + 0 (t) x (t) = 0 . (3.11)
Equ. 3.11 can be further simplied into the equation of free oscillation
on condition that
2 (t) 1 (3.13)
and
(t) 0 . (3.14)
We shall briey examine these conditions before going on. Equ. 3.13 implies
in order to validate the free oscillation simplication, the instantaneous quality factor
0 C 1
Q (t) = = 0.5 . (3.15)
G (t) 2 (t)
Equ. 3.14 implies a slow conductance variation compared with the oscillation fre-
Given that conditions 3.13 and 3.14 are satised, Equ. 3.11 degenerates into
s2 X (s) sX 0 X 0 + 02 X (s) = 0 ,
(3.16)
sX (0 ) + X (0 )
X (s) = . (3.17)
s2 + 02
3.12 " #
X (0 )
x (t) = X 0 cos 0 t +
sin 0 t u (t) (3.18)
0
" #
h i Vi
x(t) = cos (0 t) sin (0 t) u (t) , (3.19)
Vq
where u (t) is the Heaviside step function and Vi and Vq are real constants represent-
ing the inphase and quadrature amplitude of the free oscillation to be determined by
boundary conditions. Substituting Equ. 3.19 into Equ. 3.8, we obtain the general
t h "
i V
#
i
vz (t) = exp 0 (t) dt cos (0 t) sin (0 t) u (t) . (3.20)
0 Vq
oscillator. We can observe from this equation that when no input is applied, the
fundamental system as the one derived from its corresponding homogeneous equation
t h "
i v (t)
#
i
vp (t) = exp 0 (t) dt cos (0 t) sin (0 t) (3.21)
0 vq (t)
3.3. SOLUTION OF THE ODE 13
where vi (t) and vq (t) are the time-varying inphase and quadrature amplitudes to
If Equ. 3.21 satises the homogeneous equation, vi (t) and vq (t) need to be
t h "
i v (t)
#
i
exp 0 (t) dt cos (0 t) sin (0 t) =0. (3.22)
0 vq (t)
Substituting Equ. 3.21 into Equ. 3.2 and applying Equ. 3.22, we obtain
t h "
i v (t)
#
d i i (t)
exp 0 (t) dt cos (0 t) sin (0 t) = . (3.23)
dt 0 vq (t) C
Combining Equ. 3.22 and 3.23, we can solve vi (t) and vq (t) using Crammer's rule,
resulting
0 y (t) sin (0 t)
i(t)
C
sin (0 t) y (t) + 0 cos (0 t) y (t) sin (0 t) i (t)
vi (t) = = (3.24)
W (t) y (t) 0 C
y (t) cos (0 t) 0
cos (0 t) y (t) 0 sin (0 t) y (t) i(t)
C cos (0 t) i (t)
vq (t) = = , (3.25)
W (t) y (t) 0 C
where t
y (t) = exp 0 (t) dt (3.26)
0
y (t) cos (0 t) y (t) sin (0 t)
W (t) = .
cos (0 t) y (t) 0 sin (0 t) y (t) sin (0 t) y (t) + 0 cos (0 t) y (t)
(3.27)
Integrating Equ. 3.24 and 3.25 and substituting the result back into Equ. 3.21
t
y (t) i ( )
vp (t) = [sin (0 t) cos (0 ) cos (0 t) sin (0 )] d . (3.28)
0 C 0 y ( )
We further simplify the solution by applying the angle sum identity and substituting
t t
1
vp (t) = exp 0 (t) dt i ( ) exp 0 (t) dt sin 0 (t ) d .
0 C 0 0 0
(3.29)
14 CHAPTER 3. SUPER-REGENERATION
We split the second exponential integral interval into [0, t1 ] and [t1, ]. The for-
mer one becomes independent and can be moved out, combined with the rst
t t
1
vp (t) = exp 0 (t) dt i ( ) exp 0 (t) dt sin 0 (t ) d .
0 C t1 0 t1
(3.30)
t
1
vp (t) = Ks p (t) i ( ) s ( ) sin 0 (t ) d (3.31)
0 C 0
where t2
Ks = exp 0 (t) dt (3.32)
t1
t
p (t) = exp 0 (t) dt (3.33)
t2
t
s (t) = exp 0 (t) dt (3.34)
t1
oscillators under arbitrary stimulus. In this project, we are more interested in the
where A is the constant envelope, is the constant phase and is a slowly varying
d
i (t) = A sin (t + ) + t . (3.36)
dt
We further assume that the variation of the frequency in one quenching cycle is
d
t when t [0, Tq ] (3.37)
dt
3.3. SOLUTION OF THE ODE 15
t
A
vp (t) = Ks p (t) s ( ) sin (t + ) sin 0 (t ) d . (3.39)
0 C 0
t
A
vp (t) = Ks p (t) s ( )
20 C 0
Assuming 0 , the integral of the rst cosine term is nearly zero because of its
t
A
vp (t) Ks p (t) s ( ) cos [ ( 0 ) + 0 t + ] d. (3.41)
20 C 0
general solution given by Equ. 3.20 and its particular solution given by Equ. 3.41.
unnecessary.
often make natural responses of SROs negligible compared with magnitudes of input
signals in that period, because forced responses provide amplication and natural
responses are input independent. The suppression of the natural response is achieved
determined by its input, the SRO is called to be working in the noncoherent state.
Otherwise, when the build-up of oscillations are not only triggered by the input
signal, but also initiated by the residue oscillation from a previous quenching cycle,
it is called hang-over and the SRO is called to be working in the coherent state.
excitation. Based on this result, this section analyzes an SRO with respect to its
t
s (t) = exp 0 (t) dt . (3.42)
t1
its exponential dependence on time, this curve is normally sharp. Practically, it can
s (t) is close to zero when t is far away from t1 , we can change the integral interval
of Equ. 3.41 from [0, t] to [0, t2 ] or even [, +] when t is out of the sensitivity
period. We can then write the Equ. 3.41 as
t2
A
vp (t) Ks p (t) s ( ) cos [ ( 0 ) + 0 t + ] d (3.43)
20 C 0
or even
A
vp (t) Ks p (t) s ( ) cos [ ( 0 ) + 0 t + ] d. (3.44)
20 C
We now separately study the two types of operations, namely the slope-controlled
state and the step-controlled state. As shown in Fig. 3.2, the slope-controlled state
has gradual damping transition from positive to negative values. Equ. 3.6 in this
case is specied as
(t t1 )
sl (t) = , (3.45)
2C0
where denotes the absolute slope of conductance. Applying Equ. 3.42, we have
" #
(t t1 )2
ssl (t) = exp . (3.46)
4C
3.4. CHARACTERISTICS OF AN SRO 17
G0
2C0
when t < t1
st (t) = , (3.47)
G1 when t t1
2C0
and
exp G0 (t1 t) when t < t1
2C
sst (t) = . (3.48)
exp G1 (tt1 ) when t t1
2C
t
p (t) = exp 0 (t) dt . (3.49)
t2
At t = t2 , it shows the maximum value of 1. When t > t2 , the damping and its
integral are both positive, so the sensitivity decays with time. When t < t2 , the
damping is negative but its integral is positive, so the sensitivity also decays as t is
on time, this curve is sharp. Practically, the oscillation envelope is a sharp pulse at
t2 .
Following the same procedure that we use to derive the sensitivity curves, we
can also obtain the oscillation envelope in slope-controlled state, in the form of a
as shown in Fig. 3.2, and the one in step-controlled state, in the form of a double-
exp G0 (t2 t) when t < t2
2C
pst (t) = . (3.51)
G (tt2 )
exp 1
2C
when t t2
3.4.3 Gain
In the literature, the gain of a super-regenerative oscillator is divided into 3 parts,
namely the passive gain, the regenerative gain and the super-regenerative gain.
The passive gain originates from the passive resonant tank. It is dened as
1
K0 = , (3.52)
G0
which trivially converts an input current into an output voltage.
The regenerative gain quanties the amplication eect in the regeneration pe-
riod. It is dened as t2
G0
Kr = s (t) dt , (3.53)
2C 0
which is determined by the area under the sensitivity curve. A wide sensitivity
the negative-conductance period. It is derived from Equ. 3.32 and rewritten here as
t2 t2
1
Ks = exp 0 (t) dt = exp G (t) dt . (3.54)
t1 2C t1
t2
A 1
vp (t) = K0 Kr Ks p (t) t2 s ( ) cos [ ( 0 ) + 0 t + ] d. (3.55)
0 s (t) dt 0
0
when the receiver is tuned to the frequency of the input signal, Equ. 3.55 becomes
which indicates that the response of an SRO to a tuned signal is an oscillation with
ej (0 ) ej(0 t+) ej (0 ) ej(0 t+)
A
vp (t) = Ks p (t) s ( ) + d.
20 C 2 2
(3.57)
3.5. CONCLUSION 19
() = s (t) exp (jt) dt = F {s (t)} , (3.58)
A
Ks p (t) ( 0 ) ej(0 t+) + ( 0 ) ej(0 t+)
vp (t) = (3.59)
40 C
A
Ks p (t) Re ( 0 ) ej(0 t+)
= (3.60)
20 C
A
= Ks p (t) | ( 0 )| cos [0 t + + ( 0 )] (3.61)
20 C
Equ. 3.61 implies that when the frequency deviation is small compared with the
2 1 2
eat e 4a (3.62)
2a
0 +
G0 G1
t jt t jt
|st ( 0 )| = e 2C e dt + e 2C e dt (3.64)
q 0
2 2
+ ( 0 )2 + ( 0)
(G0 G1 )2
G G
1 0
4C 2 4C 2
= h 2 ih 2 i (3.65)
G0 2 G1 2
4C 2
+ ( 0 ) 4C 2
+ ( 0 )
3.5 Conclusion
In this chapter, the characteristics of super-regenerative oscillators are mathemat-
ically examined. First, a driven parametric oscillator model is presented, and de-
cients. Then, the general solution and a particular solution under an excitation of a
tion envelope, gain and frequency response are derived for SROs working in slope-
20 CHAPTER 3. SUPER-REGENERATION
in the equation solving process given in this chapter are instrumental to the ar-
chitecture and circuit design presented in the rest of the thesis. For example, in
and a step-controlled quenching yields the desirable receiver behavior for UWB-FM
reception. In this stage, we can already predict by using Equ. 3.51 and 3.63 that the
resulting frequency response has a Gaussian shape and the oscillation pulses have
Architecture Design
4.1 Introduction
In this chapter, the design issues in the architecture level are discussed. Section 4.2
derives the system specication based on the application background. The whole
design process tries to satisfy the specication given at the end of this section. From
the aspect of FM demodulation, Section 4.3 determines necessary blocks and their
of the UWB-FM receiver front-end is presented and explained in Section 4.4 and
band FSK demodulator. The former 2 components constitute the receiver front-end
to be implemented in this project, as shown in Fig. 4.1. The specication for com-
plete UWB-FM receivers has been proposed in My Personal Adaptive Global NET
WBFM FSK
LNA
Demodulator Demodulator
21
22 CHAPTER 4. ARCHITECTURE DESIGN
Parameter Value
Subsection 4.2.1 and 4.2.2 outline the input RF signal and the output subband
UWB-FM systems utilize the 3-5 GHz frequency band with several multiple
access schemes available. The two which have inuence to the receiver architecture
for this project is 500 MHz, and only 1 subcarrier is carried in each RF channel.
tion [29] to -41.3 dBm/MHz EIRP (Equivalent Isotropic Radiated Power), in the
frequency range between 3.1 and 10.6 GHz. This rule sets a maximum transmitting
carrier power of
where PT is the transmitter power and KT is the antenna gain at the transmitter
side.
4.2. SYSTEM SPECIFICATION 23
n
4d
P L (d) = (4.2)
where d, and n are the distance, carrier wavelength and propagation exponent,
ponent seldom exceeds 2 [30]. In other words, transmission loss is often proportional
to less than square of the distance. Assuming free space propagation, which has a
P T KT KR
PR = (4.3)
(4d/)2
used omni-directional antennas provide a few dB gain (2.3 dB for a dipole antenna).
But imperfect matching could cause several dB of loss. So, it is still sensible to as-
sume the use of isotropic antennas at both ends of the channel. For a communication
4 10m
PR = 14dbm 20 log( 3108 m/s
) = 80dBm. (4.4)
4.5109 Hz
According to [27], the subband signal is specied in Tab. 4.2. In this project,
Parameter Value
The modulation index of FSK is dened as the ratio of the maximum frequency
24f
F SK = . (4.7)
fm
1
4fF SK = F SK fm = 50 kHz (4.8)
2
and
For orthogonal BFSK modulation, and optimum detection (with a matched lter)
plication analysis, a maximum bit error rate of 106 is required for low-data-rate
(LDR) physical layer [31]. In that case, we need a Eb /N0 of nearly 14 dB.
R
= 0.5, (4.11)
BWF SK
and the signal-to-noise ratio needed from the output of WBFM demodulator is then
Eb R
SN Ro = = 14dB 3dB = 11dB. (4.12)
N0 BW
4.2. SYSTEM SPECIFICATION 25
A negative noise gure is indeed possible in UWB-FM receivers, since the subcar-
ltering can be applied after the RF front-end to distinguish signal from noise. The
BWRF 500MHz
Gp = = = 34dB. (4.14)
BWF SK 200kHz
4.2.3.2 Linearity
Non-linearity distortion jeopardizes the amplitude of a signal. For FM signals, since
information is carried only on the frequency, they are immune to amplitude distor-
amplitude limiting device in receivers are commonly used although they do cause
front-ends can be made nonlinear. This permits the use of integrators and super-
could produce considerable power in RF frequencies and has the potential to violate
radiated power (EIRP) for receivers should not exceed -47 dBm in frequency range
Parameter Value
The choice between the FM-AM and the FM-PM intermediate transformation
tween the incoming PM signal and a reference signal. Coherent detection oers the
best performance at the cost of complexity and power consumption. On the other
herent amplitude detectors, such as square-law and peak detectors are commonly
used for low-complexity receivers. The penalty paid for noncoherent detection is the
derived in Section 4.2 are satised. If the performance of the noncoherent detection
is not adequate, the coherent amplitude detection can still be performed. Therefore,
where A is the constant amplitude, is the constant initial phase and (t) is the
LNA
Vi f Vi
signal is
A general FM-AM receiver structure is shown in Fig. 4.2. The 3 building blocks,
namely, the limiter, frequency discriminator and AM detector are discussed in detail
4.3.2 Limiter
An ideal FM signal has a constant amplitude. In reality, however, channel propa-
gation induces amplitude noise. The eect of this noise can be derived by adapting
and
The rst term in Equ. 4.18 is called the radial component, which carries no informa-
tion but interference. The second term, named the tangential component, carries the
amplitude noise, amplitude limiters are frequently used before FM-AM converters
reduces amplitude noise. The total noise is partially discriminated and removed.
On the other hand, the nonlinearity of the limiter reduces the dynamic range of the
receiver as well. In other words, input signals are suppressed more than the noise.
Thus, the net eect of amplitude limiting depends on the input SNR.
The relationship between the output and input SNR of an ideal UWB-FM de-
modulator is shown in Fig. 4.3. The performance of another demodulator used for
commercial FM (20 kHz wide baseband and 75 kHz maximum frequency deviation)
is also plotted as a comparison. From the gure, it can be observed that FM demod-
28 CHAPTER 4. ARCHITECTURE DESIGN
80
70
60
SNRo (dB)
50
40
30
20
10
0
0 5 10 15 20 25 30 35 40 45 50
SNRi * Gp (dB)
ulators exhibit thresholds, below which the output SNRs degrade dramatically as
the input SNRs decrease. If an FM receiver operates above the threshold, amplitude
limiting yields improvement of output SNR. Conversely, if the input SNR is lower
than the threshold, limiting the amplitude leads to a degradation of output SNR
[13].
and a processing gain of 34 dB, as derived in Equ. 4.6 and 4.14. This leads to an
output SNR of around 90 dB. As shown in Fig. 4.3, the receiver is operating 1 dB
above the threshold of the UWB-FM system. Therefore, for a UWB-FM receiver,
the advantage and drawback of the amplitude limiter countervail each other. The
According to the preceding analysis of the amplitude limiter, two design decisions
are made. Firstly, the amplitude limiter is not going to be implemented in this
receiver, since it is not eective for UWB-FM. Secondly, the nonlinearity of the
LNA can be tolerated, since it has the same eect as an amplitude limiter. This
receiver. However, for FM receivers, this distortion also suppresses the amplitude
noise.
4.3.3 FM Discriminator
FM discriminators convert FM signals into AM-FM ones. Any circuit having a non-
H(j) = j (4.19)
amplitude linearly. Furthermore, when additive white Gaussian noise (AWGN) with
a power spectral density of N0 is applied to the signal, the output noise power is
which quadratically shapes the noise in such a way that low frequencies have low
noise level. This noise shaping is the fundamental reason of the SNR improvement
of FM systems [13].
1
H(j) = (4.21)
j
which converts frequency nonlinearly. For AWGN with a power spectral density of
N0
Nout = |H(j)|2 N0 = (4.22)
2
which shapes the noise in a wrong way that the noise power is concentrated in the
band-pass form.
shown in Equ. 3.63. The frequency response of the step-controlled SROs is similar
to the response of a pair of loosely coupled tuned circuits [3], as shown in Equ. 3.65.
conversion. However, both of the shapes are nonlinear and the noise is also shaped
in a wrong way.
Tuned Filters Vs. Detuned Filters Tuned dierentiators and integrators con-
0
0 0.5 1 1.5 2 t (us)
4.25 4.5 4.75 f (GHz)
0
0.5
1.5
2
t (us)
0
0 0.5 1 1.5 2 t (us)
4.25 4.5 4.75 f (GHz)
0
Instantaneous Frequency of the FM Input
0.5
1.5
2
t (us)
since their frequency responses are not monotonic within the FM bandwidth. The
FM-AM conversion eect of a tuned lter is illustrated in Fig. 4.4 (a). If the fol-
demodulated.
The common remedy to tackle this problem is to detune a lter (or an SRO)
away from the center frequency of an FM signal in such a way that the amplitude
response of the lter is monotonic within the frequency band of interests, as shown
in Fig. 4.4 (b). The penalty paid is that half of the lter bandwidth is opened to
so that a tuned lter (or SRO) and a noncoherent AM detector can be used together.
Since the signal to be recovered is an FSK modulated signal which carries informa-
tion only on its frequency, not on its amplitude, the information carried in the
heavily and doubles the frequency. More specically, as shown in Fig. 4.4 (a), a 1
4.3.4 AM Demodulator
AM detection can be synchronous or asynchronous. Asynchronous, or noncoherent,
detectors retrieve the amplitude modulus of the AM signal. The modulus of the
q
Vmod = ksn (t)k = A2 (t) + A2 (t) 2 (t). (4.23)
where snq (t) and rq (t) are the quadrature of sn (t) and r (t), dened as
snq (t) = A (t) sin [ (t) t + ] + A (t) (t) cos [ (t) t + ] (4.26)
RF Circuits
Substituting Equ. 4.18, 4.24, 4.26 and 4.27 into Equ. 4.25 yields
Vprj = A cos A sin B sin + A sin +A cos B cos (4.28)
= AB sin cos +AB sin2 +AB sin cos +AB cos2 (4.29)
= AB (4.30)
Comparing Equ. 4.23 and 4.30, coherent detection can distinguish the ampli-
tude noise from signal while the noncoherent detection cannot. This drawback for
Coherent detectors, although provide the best achievable performance [13], are
power consuming since at least one multiplier is necessary for the projection calcu-
coherent detectors, a peak detector, for its structural simplicity and low power con-
sumption. Its inferior noise performance is partially made up by the high gain of
part of the receiver, consisting of an LNA, an SRO and a peak detector, originates
4.5. SYSTEM-LEVEL SIMULATION 33
from the generic FM receiver plotted in Fig. 4.2. The LNA suppresses the noise
of following stages, matches the impedance of the antenna for maximum power
transmission and shields the high-power oscillation of SRO from coupling back into
the antenna. The SRO provides most of the receiver gain and converts the incoming
FM signal into AM. The peak detector extracts the envelope of the periodically
cuit, an output buer and a current reference. The waveform generator produces
a certain biasing waveform to bias the SRO for a certain frequency response. The
dynamical biasing circuit shut the LNA down in the quenching period of SRO to
save power. The output buer drives the measurement instrumentation. And the
are accepted. The clock and the amplitude signals adjust the time-constants
and amplitude of the quenching waveform. The delay signal controls the warm-up
time of the LNA before the SRO starts to work. The frequency signal tunes the
in this chapter.
The top-level simulation setup is shown in Fig. 4.6. A 4.5 GHz, 500 MHz band-
the signal to -80 dBm at 100 ohm resistance as specied in Equ. 4.4. The spectrum
The three blocks shown at the bottom of Fig. 4.6, namely the GM, sro and
PeakDetector, model the LNA, SRO and peak detector in a receiver. Block Ga
provides a rectangular quenching waveform. The purpose of the feedback from the
output of the peak detector to the input amp of the SRO is to model the amplitude
The model of the SRO is plotted in Fig. 4.8. It is described by the second
order time-varying dierential equation 3.2 modeling the circuit shown in Fig. 3.1.
FM K
i
Repeating ZeroOrder Channel
Sequence Hold FM
Modulator
Passband
1 2
Vbase Vrf
K i
GM Quench v Vi Vo 5
Venv
amp
PeakDetector
sro
Ga
3 4
Vquench Vosc
105
Power Spectral Density (dBm/MHz)
110
115
120
125
130
135
140
4 4.1 4.2 4.3 4.4 4.5 4.6 4.7 4.8 4.9 5
Frequency (GHz)
Figure 4.7: The spectrum of the UWB-FM signal at the input of the receiver.
4.5. SYSTEM-LEVEL SIMULATION 35
1 du/dt K v 1 v 1 v
i 1
s s
Derivative invC1 v
Sum Integrator Integrator1
invC
Product
K
3
invLC
amp 1e3
Lookup Table G
G0
Subtract
2
Quench Product1
1
Vi
K u K
e 1
K
s
1 invnVt Math I0 1
Subtract1 invC Integrator Vo
Function
Vbias Subtract4
Subtract
Ve
0
1e5
Vref
Itail
K u K
e 1
0.4 K Vrefout
s
invnVt1 Math I1
Vth Subtract3 invC1 Integrator1 To Workspace
Function1
Subtract2 Ve1
The peak detector block, shown in Fig. 4.9, models the simplest peak detector,
formed by a diode, a capacitor and a current source. Despite its structural simplicity,
the correct operation relies on the dynamic nonlinearity of the circuit. In essence,
t
1 VB + Vi VE
VE = I0 exp Itail dt. (4.31)
C 0 VT
In every integration step, VE is calculated by this equation and the output of the
Vo = VE VE1 . (4.32)
36 CHAPTER 4. ARCHITECTURE DESIGN
The simulation result is shown in Fig. 4.10. As shown in the graph, the restored
4.3.3.
Intensive simulations are performed to verify that the gain, output pulse shape
and frequency response of the receiver are adjustable by tuning the amplitude, duty-
Subcarrier (Vbase)
1
Amplitude (V)
0.5
0.5
1
0 200 400 600 800 1000 1200 1400 1600 1800 2000
Time (ns)
Oscillation Amplitude (Vosc)
300
200
Amplitude (mV)
100
0
100
200
300
0 200 400 600 800 1000 1200 1400 1600 1800 2000
Time (ns)
Oscillation Envelope (Venv)
250
200
Amplitude (mV)
150
100
50
0
0 200 400 600 800 1000 1200 1400 1600 1800 2000
Time (ns)
Conductance Waveform (Vquench)
1
Conductance (mS)
0.5
0.5
0 200 400 600 800 1000 1200 1400 1600 1800 2000
Time (ns)
Figure 4.10: The simulated baseband signal, oscillations, their envelopes and the
quenching waveform.
Chapter 5
5.1 Introduction
In Chapter 4, receiver specications are derived and a block-level receiver structure
is proposed. The design and implementation of the RF building blocks, namely the
super-regenerative oscillator, the peak detector and the low-noise amplier, utilizing
Since a detailed specication for each circuit block is not available at the begin-
and the peak detector are designed to realize the receiver functionality with minimal
power dissipation. Then, we use the noise and swing information of these stages to
determine the LNA specications, namely the gain, noise gure and reverse isola-
tion. After the LNA is worked out, quenching generators for SRO and LNA are
The super-regenerative oscillator, peak detector and low-noise amplier are in-
troduced in Section 5.2, 5.3 and 5.4, respectively. The other building blocks, namely
the biasing waveform generator for SRO, the dynamic biasing circuit for LNA, the
minimal power. Maximal gain of SRO is desirable because rstly, it shields the
receiver back-end from jeopardizing system sensitivity, and secondly, the gain of
38
5.2. SUPER-REGENERATIVE OSCILLATOR 39
mance. Nevertheless, we avoid using them as resonators for the following reasons.
First of all, the use of o-chip components increases the component count and de-
creases the integration level. These lead to an increased production cost which is
parasitics can be prohibitively large and even worse, dicult to control. Therefore,
Quartz crystals and SAW devices have been the choice for high-performance
narrow-band SROs since their high quality factor solves the inherent low-selectivity
devices are incompatible with silicon technology and normally incapable of operating
BAW devices also have high Q factors and they can work at UWB frequencies.
transmission lines are also high-Q devices. However, physical dimensions of trans-
mission lines are normally unfavorable for integration. For instance, 4.5 GHz signals
LC tanks are the oldest type of lters used in SROs, originating from Armstrong's
patent in 1922. They have been the most popular choice because of the abundance of
suer from the low Q caused by the resistance of metals and substrate coupling.
In conclusion, despite their high-loss, integrated lumped components are the best
Vdd
Vfrq
M1 M2
Vbias M3
parallel with the LC resonation tank. A periodic biasing current yields a periodically
interpreted in Chapter 3.
A dierential oscillator structure is chosen for 3 reasons. First of all, it does not
consume more power than a single-ended one, for a given voltage swing. However,
designs because supply voltage can be lowered without inuencing the voltage swing.
discussed in Subsection 5.2.6, enhanced Q factor yields power and noise reduction of
oscillators. The latter one further leads to LNA power reduction. Thirdly, common-
to negative conductance transitions decide the shape of frequency response and the
Moreover, the operation states of an SRO can be categorized into two types,
gradual for a slope-control and sharp for a step-control, as shown in Fig. 3.2 and
3.3.
shapes, select the most favorable combination for the low-power UWB-FM demod-
ulation and design the favored biasing waveform for the SRO.
5.2. SUPER-REGENERATIVE OSCILLATOR 41
Frequency response
1
Slopecontrolled
0.9 Stepcontrolled
0.8
0.7
Normalized gain
0.6
0.5
0.4
0.3
0.2
0.1
0
4.25 4.3 4.35 4.4 4.45 4.5 4.55 4.6 4.65 4.7 4.75
Frequency (GHz)
the sensitivity curve of an SRO has a Gaussian shape (Equ. 3.46), whose Fourier
transform is also Gaussian shaped (Equ. 3.63). On the other hand, step-controlled
Equ. 3.65. The frequency responses of these two types of quenching are shown in
Fig. 5.2.
The bandwidth of the frequency response is tunable for both slope- and step-
Since the frequency response of the SRO is used for FM to AM conversion, the
one with the maximum conversion gain is preferred. Direct observation of Fig. 5.2
may not lead to the correct conclusion because the curve shapes are adjustable.
A meaningful comparison should be made when both of them are tuned to their
paragraphs.
We use the slope factor , the changing rate of conductance, in Equ. 3.63 as
the tuning variable for slope-controlled SROs. A set of frequency response curves
are generated as shown in Fig. 5.3, when ranges from 105 to 106 Siemens per
42 CHAPTER 5. RECEIVER CIRCUIT DESIGN
0.6
0.5
0.4
0.3
0.2
0.1
0
4.25 4.3 4.35 4.4 4.45 4.5 4.55 4.6 4.65 4.7 4.75
Frequency (GHz)
second (S/s). If we apply the UWB-FM signal (triangular wave modulated) to such
FM-AM conversion curves and change the horizontal axis to time, the curves would
1
Aslope = f () cos d (5.1)
where f () and are the AM waves and their phase. A parameter sweep shows
that the best FM-AM conversion curve is obtained when = 0.359 106 S/s, or
to 3 mS yield the frequency response curves shown in Fig. 5.4. Applying Equ. 5.1 to
this set of curves, we obtain the best FM-AM conversion curve when G1 = 0.681
mS. The normalized output amplitude is 0.387.
The comparison of best conversion gain of slope- and step-controlled SROs are
listed in Tab. 5.1. The theoretically best conversion gain, 0.5, is also listed as a
It can be observed from Tab. 5.1 that slope-controlled SROs oer a nearly
SRO.
5.2. SUPER-REGENERATIVE OSCILLATOR 43
0.9 G1=1.334 mS
G1=0.562 mS
0.8 G1=0.237 mS
G1=0.100 mS
0.7
Normalized gain
0.6
0.5
0.4
0.3
0.2
0.1
0
4.25 4.3 4.35 4.4 4.45 4.5 4.55 4.6 4.65 4.7 4.75
Frequency (GHz)
Table 5.1: The comparison of FM-AM conversion gain of slope-, step-control and
the ideal case.
44 CHAPTER 5. RECEIVER CIRCUIT DESIGN
Conductance Waveform
1
Conductance (mS)
0.5
0.5
1
0 10 20 30 40 50 60 70 80 90
Time (ns)
Tailcurrent Waveform
1.5
Current (mA)
0.5
0 10 20 30 40 50 60 70 80 90
Time (ns)
Figure 5.5: The waveform of the total conductance and the tail current for the SRO.
oscillation envelope of an SRO has a Gaussian shape (3.50), as shown in Fig. 3.2.
yield exponential growing and decaying envelope (Equ. 3.51), as shown in Fig. 3.3.
the peak amplitude happens when the conductance polarity is changing. At this
time, the biasing current is not maximum, which may lead to gain compression and
waveform. The designed conductance waveform is plotted in Fig. 5.5. In the gure,
the slope of the positive to negative conductance transition is set to 0.359 mS/ns
source. The waveform of this source is shown in Fig. 5.5. The maximum current is
1.2 mA determined by the voltage swing requirement and the passive tank resistance.
The current ramp takes 15 ns, this implies a current slope of 0.08 mA/ns.
At the starting-up phase, MOSFETs of the cross-coupled pair are in weak inver-
1 1 Id 1 Itail
GM = gm = = (5.2)
2 2 nVT 4 nVT
where gm , Id and n are the small-signal transconductance, drain current and slope
factor of one transistor, and VT is the thermal voltage. So before transistors M1 and
M2 shown in Fig. 5.1 are saturated, the negative conductance is proportional to the
biasing current. The IBM 90-nm NMOS we used has a slope factor, n, of 1.37. So
0.08 mA/ns
= = 0.561 mS/ns. (5.3)
4 1.37 26 mV
As the current grows larger, the I-V relation deviates from the exponential law.
The absolute value of the conductance slope is becoming smaller and smaller. The
critical point happens at this phase. When Itail reaches 340 uA, the positive-to-
negative transition of the conductance occurs. Ideally, at this critical point, the
When current grows large, the I-V behavior of pair transistors is more and more
close to the square law. Then the negative transconductance is more accurately
approximated by
1 1p 1p
GM = gm = 2KId = KItail , (5.4)
2 2 2
where K = Cox W/L. From this equation, we can determine the width of the MOS-
FETs. First of all, the width inuences the gain of the SRO. A larger width yields
a larger -GM and thus a larger negative area below this -GM curve. Secondly, the
width aects the position of the critical point. A smaller width yields a compara-
tively higher current density and thus an early transition and a longer square-law
region.
We select the width based on the amount of gain needed. For a given input RF
signal strength, specic LNA gain and output oscillation amplitude, the gain of the
SRO is a determinable constant. Since the maximum biasing current is set by the
voltage swing, the slope is xed by the frequency response, only width is adjustable
When the receiver needs the gain control, for example, when a communication
46 CHAPTER 5. RECEIVER CIRCUIT DESIGN
Im
1 2
Re
1 2
range is smaller than the maximum designed distance, then a smaller gain is still
attainable after fabrication by slightly tuning the maximum current or the rise-time
of the ramp. These adjustments detune the frequency response and the oscillation
amplitude from their optimum values. But since decreasing the gain implies that a
shorter communication distance and a better input SNR are available, the receiver
The GM compression eect shown in Equ. 5.4 is actually desirable. The reasons
First of all, the absolute conductance has an upper bound for certain frequency
shown in Fig. 5.6. A passive resonant tank has a pair of conjugate poles at position
parameters
1
0 = LC
is the natural oscillation frequency,
G0 G1 (t)
= 2C
is the damping factor, and
p
= 02 2 is the damped oscillation frequency.
5.2. SUPER-REGENERATIVE OSCILLATOR 47
GM Nonlinearity
1
0.9
0.8
0.7
0.6
GM / gm
0.5
0.4
0.3
0.2
0.1
0
0 0.05 0.1 0.15 0.2 0.25 0.3
Voltage Swing (V)
When Equ. 3.15 is satised, the damping oscillation frequency is approximately the
0 . (5.5)
If the negative GM is too large, however, Equ. 5.5 does not hold any more. Then
Secondly, the tail current has a lower bound for certain voltage swing, since the
voltage swing across a resonant tank is linearly proportional to the biasing current,
the resonant tank to provide an optimum frequency response for FM-AM conver-
sion. Current biasing is suitable to generate this waveform for 2 reasons. Firstly,
when MOSFETs are in weak inversion, the negative conductance is linearly propor-
tional to biasing current. Secondly, when the MOSFETs are saturated, the negative
lationship, as shown in Equ. 5.4), which relaxes the trade-o between frequency
mA. This value is a trade-o between the dynamic range and the power consumption.
Super-regenerative oscillators have 2 operation modes, the linear and the log-
arithmic mode. The latter one is normally undesirable because it performs the
smaller gain than that of small signals and noise. So the SNR at the output is in-
herently reduced, even if the amplication is noiseless. The gain compression caused
dissipation. A larger biasing current leads to a larger available voltage swing, and
simulations are performed with the biasing current gradually increased from a small
value, until an acceptable output SNR is obtained. In this way, certain amount of
Our design goal for the SRO is to reduce power consumption. For an RLC resonant
0 Etank
Ploss = (5.7)
Q
where 0 , Etank and Q are the resonant frequency, energy stored in the tank, and
the quality factor. In order to reduce power dissipation, we could either increase Q
or decrease Etank . However, the latter method reduces the oscillation voltage swing
1 2
Etank = CVsig (5.8)
2
where C is the tank capacitance and Vsig is the voltage across the capacitor. The
kT
Vn2 = , (5.9)
C
5.2. SUPER-REGENERATIVE OSCILLATOR 49
(Vsig/ 2)2 Etank
SN R = = , (5.10)
Vn2 kT
where k and T are the Boltzmann's constant and absolute temperature. A clear
SN R Q
= . (5.11)
Ploss 0 kT
Since 0 kT is practically a constant, if we want high SNR and low power consump-
In IBM 90-nm RF CMOS design library, a scalable model for symmetrical inductors
dimension of 75-to-300 um, a coil width of 7.02-to-15 um and a line spacing of 3-to-
goal is to gure out the parameter combination yielding the highest Q factor and a
to the substrate. This measure reduces the induced current owing in the ohmic
substrate, which increases the Q factor. Furthermore, noise coupling between the
inductor and the substrate is also shielded. The penalty of this measure is the
coupling among adjacent lines. This measure increases the inductance and the
conductor width and the number of turns. As a result, the inductor with the highest
Q factor and a reasonably high self-resonant frequency is selected with its parameters
Parameter Value
The maximal voltage swing can reach up to twice as large as this value. While these
eration threatens the integrity of gate oxide. As the device dimensions shrink down,
oxide thickness also decreases. Thin oxide is vulnerable to stressing voltages. The
thickness of gate oxide for IBM 90-nm CMOS is 1.4 nm, which has a breakdown
voltage of 1.32 V. Even below this value, gradual oxide degradation still happens
voltage swing. For a nominal voltage supply of 1 V, a 20% variation of this voltage
is normally acceptable. So the positive voltage swing of this SRO is limited to be 1.2
that this maximum of 1.2 V is not going to cause oxide breakdown or degradation.
Further increasing the voltage swing and reducing the power consumption requires
However, the minimum supply voltage is limited by LNA which is likely to use
a cascode structure for reverse isolation. Moreover, the input transistor is likely
to be biased in strong inversion for a decent transit frequency, which needs a gate-
source voltage of around 600 mV. Taking these factors into consideration, we decide
consumption, because the lack of receiver back-end specication requests the uni-
versality and adaptability of this receiver front-end. In other words, this frond-end
5.2. SUPER-REGENERATIVE OSCILLATOR 51
should not impose severe noise requirement to its following stages. This objective
Given the supply voltage of 900 mV and a maximum voltage limit of 1.2 V, the
voltage swing amplitude should not exceed 300 mV, i.e. a single-ended peak-to-peak
IBM's technology design manual [33]. For a product lifetime of 100 KPOH (thousand
permitted transient voltage of 1.6 V. So a 300 mV voltage swing amplitude (i.e. 1200
degradation.
The stimulus to the SRO is a 4.5 GHz RF carrier being modulated by a 1 MHz
Fig. 5.8, from 0 to 1000 ns. At t=0 and 1000 ns, the subcarrier has the minimum
t=500 ns, the subcarrier is at its maximum, generating the RF signal with 4.75
GHz instantaneous frequency. At t=250 and 750 ns, the subcarrier is 0, so the RF
The single-ended voltage output of the SRO is shown in the middle of Fig. 5.8.
The frequency response of the SRO can be observed. When the input signal has
a frequency of 4.5 GHz, the SRO outputs the maximum oscillation amplitude of
around 0.3 V. The deviation of frequency from its center yields the reduction of
output amplitude. When the RF frequency is at 4.25 or 4.75 GHz, the output
The biasing current waveform is shown in the bottom of Fig. 5.8. In every
biasing period of 35 ns, the current ramps from 0 to 1.2 mA in 15 ns. Then it drops
to 0 at once and keeps a 0 value for the rest 20 ns. This SRO draws 0.257 mA in
Subcarrier
0.5
Voltage (V)
0.5
0 100 200 300 400 500 600 700 800 900 1000
Time (ns)
SRO Oscillation Output
0.3
0.2
Voltage (V)
0.1
0.1
0.2
0 100 200 300 400 500 600 700 800 900 1000
Time (ns)
SRO Biasing Current
1.5
Current (mA)
0.5
0
0 100 200 300 400 500 600 700 800 900 1000
Time (ns)
Figure 5.8: The baseband signal, output oscillations and the SRO biasing current.
5.3. PEAK DETECTOR 53
Vi Vo
peaks. They are frequently used as simple amplitude demodulators. In this project,
The design goal for this peak detector is the maximum conversion gain and low
with that of mixers, which is the output envelope magnitude divided by the input
oscillation amplitude.
and a resistor. Assuming an ideal diode for simplicity and an RC time constant much
larger than the incoming signal, we can describe its operation as follows. When a
peak comes and Vi > Vo , the diode conducts; Vo follows Vi and the capacitor is
charged. After the peak, Vi < Vo , the diode is tuned o; the capacitor hold the peak
voltage and the resistor slowly discharges the capacitor. The discharge speed is set
in such a way that when the next peak comes, Vo is always slightly smaller than
Vi to close the diode, charge the capacitor and track the pulse while maintain the
The circuit used in our design is shown in Fig. 5.10. Two diode-connected
MOSFETs, M1 and M2, substitute the diode in Fig. 5.9 to track both positive and
capacitor instead of the resistor. A dummy duplicate of this circuit, M1'M3' copies
the same voltage drop to output a reference voltage, so that Vo will be zero when
The dierential structure is used for 2 reasons. First of all, it tracks the dieren-
tial output peaks of both polarities. So the discharge speed could be twice as much
54 CHAPTER 5. RECEIVER CIRCUIT DESIGN
Vdd Vdd
Vip Vin
M1 M2 M1 M2
M3 Ctail + Vo - M3
this receiver because the oscillation envelope is exponentially shaped pulses, which
are sharp and require fast tracking. The second reason to use a dierential struc-
The design parameters to be determined are the biasing current, the capacitor
Traditionally, diodes and bipolar transistors are used as the nonlinear switches.
Both types of them have an exponential V-I relationship. The transfer characteristic
r
2Vi
Vo = Vi VT ln , (5.12)
VT
where Vi , Vo and VT are the input and output amplitude and thermal voltage,
respectively [34].
When MOSFETs are working in weak-inversion, the V-I relationship is still ex-
ponential, expressed as
Vgs
Id = Id0 exp (5.13)
nVT
where n>1 is called the nonideal or slope factor, and VT is the thermal voltage.
r
2Vi
Vo = Vi nVT ln . (5.14)
nVT
1 W
Id = n Cox (Vgs Vth )2 . (5.15)
2 L
1 W 2
Id = n Cox Vgs + Vi cos (t) Vth (5.16)
2 L
1 W 2
= n Cox Vgs Vth + 2 Vgs Vth Vi cos (t) + Vi2 cos2 (t) (5.17)
,
2 L
where
Vgs = VG Vs , (5.18)
VG and Vs are the DC gate voltage and transient source voltage. Since M1 and M2
are alternatively switched on and o for 50% of the time by nearly identical peak
amplitudes, they share the bias current evenly. And the average tail current of M1
T
Itail 1 2 W h 2 i
= Id = n Cox Vov + 2Vov Vi cos (t) + Vi2 cos2 (t) dt (5.19)
2 T2 2 L
Vi2
1 W 2
= Id = n Cox Vov + , (5.20)
2 L 2
where Itail and Id are the tail biasing and average drain current, and
is the transient overdrive voltage. For M1' and M2', the tail current is also evenly
Itail 1 W 2
= Id0 = n Cox Vgs0 Vth . (5.22)
2 2 L
r
Vi2
Vov = (Vov0 )2 , (5.23)
2
56 CHAPTER 5. RECEIVER CIRCUIT DESIGN
0.35
Output Envelope (V)
0.3
0.25
0.2
0.15
0.1
0.05
0
0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5
Input Oscillation Amplitude (V)
where
Vov0 = VGS
0
Vth = VG VS0 Vth (5.24)
is the overdrive voltage of MOSFET M1' and M2'. The output voltage of the peak
detector is dened as
Vo = Vs VS0 (5.25)
r
Vi2
Vo = Vov0 (Vov0 )2 . (5.27)
2
Equ. 5.27 is the transfer characteristic of a peak detector using square-law nonlinear
devices.
in weak- and strong-inversion, is now possible by using Equ. 5.14 and 5.27. Fig.
5.11 plots the transfer characteristics of peak detectors utilizing bipolar transistors,
MOSFETs working in weak-inversion with a slope factor of 1.5 and those working in
strong inversion with an overdrive voltage of 0.5 V. As shown in the graph, bipolar
peak detectors have the highest conversion gain of 0.873. Weakly inverted MOSFETs
cause a slightly inferior conversion gain of 0.826. Strongly inverted MOSFETs yields
the worst result, a conversion gain of 0.578, which is signicantly lower than the other
5.3. PEAK DETECTOR 57
two.
technologies can also perform as the bipolar ones by using dynamic threshold MOS-
connections from their bodies to their gates, which form parasitic bipolar transis-
tors. However, DTMOSs are not used in this design since the use of PMOSs needs
AC coupling and triple-well NMOSs require 3 additional masks. In other words, the
extra gain squeezed out by DTMOSs is too little to justify the trade-os.
capacitor value Ctail and the width of M1 and M2. The previous subsection con-
cludes that MOSFETs should be biased in deep subinversion to have the maximum
conversion gain. This implies a large transistor width and a small tail current.
The largest transistor width is limited by the parasitic capacitances between the
two gates. Since the peak detector is in shunt with the resonation tank, all these
capacitances contribute to the tank. The frequency stability can be severely inu-
enced if these parasitics dominate the tank capacitance. Considering the inductor
we selected, a 655 fF total capacitance is required for the tank to resonate in 4.5
GHz. We limit the parasitics to 10% of this total value, i.e. 65 fF, so that a 20%
The tail current and source capacitor together determine the discharge time
and output dynamic range. A slow discharge accurately follows the peak, but only
a small envelope variation can be followed. On the other hand, a fast discharge can
follow fast envelope variation, but it detects not only the peaks, but also the rising
curve before peaks. In our design, the maximum voltage drop between 2 peaks is
around 30 mV, in a period of 0.22 ns. This determines the current-capacitance ratio
to be
Itail Vdrop 30 mV 30 uA
= = = . (5.28)
Ctail Tperiod 0.22 ns 0.22 pF
The source capacitor should be much larger than, or should take into account,
the input capacitance of the following stage. Otherwise the discharge time constant
would be dierent. In our design, a voltage buer for measurement purpose is the
load of the peak detector. We choose a Ctail of 100 fF, then the biasing current is
It is worth mentioning here that the kT/C noise should not be considered when
choosing the value of Ctail . Sooner or later, after the envelope detection, a band-
pass lter has to be applied to extract the subband signal. The bandwidth of this
58 CHAPTER 5. RECEIVER CIRCUIT DESIGN
0.18
0.16
0.12
0.1
0.08
0.06
0.04
0.02
0
0 0.05 0.1 0.15 0.2 0.25 0.3
Input Oscillation Amplitude (V)
bandpass lter is smaller than the bandwidth determined by Ctail . So a large source
The transfer characteristic showing the voltage amplitude of the input and the out-
put is plotted in Fig. 5.12. From the graph, it can be observed that a 0-to-300
conversion gain of around 0.6. Furthermore, the nonlinearity of conversion gain can
be observed from Fig. 5.12 (and also Fig. 5.11) when the input oscillation ampli-
tude is small. This reduced conversion gain sets the minimum detectable oscillation
amplitude (about 40 mV), which can be benecial since the small oscillations caused
plotted in Fig. 5.13. As shown in the graph, the envelope is extracted from the
The peak detector draws 30 uA from the 0.9 V supply, yielding a power con-
sumption of 27 uW.
5.3. PEAK DETECTOR 59
SRO Oscillation
300
200
100
Voltage (mV)
100
200
300
0 50 100 150 200 250 300 350 400 450 500
Time (ns)
100
Envelope (mV)
50
0
0 50 100 150 200 250 300 350 400 450 500
Time (ns)
100 20 9
20 14 3
10 11.3 0.3
1 4.2 -6.8
Table 5.3: Output SNR vs. LNA transconductance and noise gure budget.
plies the received weak RF signal to a certain level such that noise in following
ing network between the antenna and the following SRO. Thirdly, it shields the
high-power oscillation of SRO from coupling back into the antenna. As a result, the
LNA has to satisfy several requirements in order for the system to operate properly.
test-bench simulation with the already designed SRO, peak detector and an ideal
nd out the transconductance that yields the minimum acceptable output SNR.
More specically, from Section 4.2, the worst-case RF signal is -80 dBm (Equ. 4.4)
when the receiver is 10 meters away from the transmitter. And the required output
SNR is 11 dB (Equ. 4.12) for a data-rate of 100 kbps and a bit-error-rate of 106 .
For super-regenerative receivers, we argue the necessity of using the transcon-
is following an LNA, it modies the load resistance of the LNA constantly. The
the load impedance of an LNA (since it increases the load resistance). The volt-
age and power gain is also changing, so they are time-varying. On the other hand,
tween LNA transconductance and output SNR listed in Tab. 5.3. As shown in the
table, there is a trade-o between the gain and noise gure requirements. A high
gain suppresses the noise of following stages so the LNA NF dominates the receiver
NF. On the other hand, a low gain brings the noise of following stages into play and
the NF requirement is tightened. A sensible choice for LNA specication from Tab.
passive tank resistance of 1046 ohm, as the load. Then, the voltage gain of the LNA
is calculated as
Av = GM RL = 20.9, (5.29)
Vo2
RL RS
S21 = Vi2
= A2v = 41.8 = 16.2 dB. (5.30)
RL
RS
stitute) imposes a narrow-band spurious emission limitation of less than -47 dBm
EIRP (Eective Isotropic Radiated Power) [32]. In our design the SRO produces
high-power oscillation at 4.5 GHz, which needs to be attenuated to satisfy the spu-
2
Vrms 2 0.32
Posc = = = 0.17 mW = 7.6 dBm, (5.31)
RL 1046
when applied on the 1046 ohm load resistance. The required LNA isolation can then
be calculated as
M1 and M2 are the common-source input stage with their sources degenerated by
Ls, to provide a real part of the input impedance. MOSFETs M3 and M4 are the
62 CHAPTER 5. RECEIVER CIRCUIT DESIGN
Parameter Value
Vdd Vdd
Vdd Vdd
M8 M3 Vfreq M4
M7
M5 M6
Vdd
Vdd Vdd
Matching
Network
Rs
M1
Vs
Cgs
Ls
cascode which provide reverse isolation and increase the output impedance to avoid
loading the oscillator tank. Extra reverse isolation is provided by the neutralization
MOSFETs M5 and M6. The matching network at each side is formed by the degen-
eration inductor Ls , biasing inductor Lg , a shunt and a series capacitor, the ESD
and even-order harmonics suppression. Common-source input stage is chosen for its
matching functionality. We use the cascode stage not only to provide reverse iso-
lation, but also to prevent the output impedance from loading the oscillation tank.
cedure which is quite dierent from the classical methodology [25], which is, from
The design procedure discussed in this subsection derives the minimum power for a
certain gain and bandwidth, given the device characteristics of a certain fabrication
process.
64 CHAPTER 5. RECEIVER CIRCUIT DESIGN
5.4.3.1 Minimum Ft
We derive the relationship between the LNA transconductance and the transition
The input part of the LNA is redrawn in Fig. 5.15. We neglect the cascode
and neutralization MOSFETs since they do not contribute or inuence the LNA
vs
is = . (5.33)
2Rs
and all the current is owing into the degenerated resistor. Then the voltage across
Cgs is expressed as
is vs
vgs = = = jQvs (5.34)
jCgs jCgs 2Rs
where Q is the quality factor of the input network
1
Q= . (5.35)
2Cgs Rs
id vgs gm T
GMsingle = 2 GM = = jQ gm = = , (5.36)
vgs vs j2Cgs Rs 2jRs
of the input MOSFET. From Equ. 5.36, we observe that for an operating frequency
of 4.5 GHz, a source impedance of 50 ohm, and GM > 20 mS the transit frequency
is
2 GM 2jRs
ft = > 18 GHz (5.37)
2
voltage sweep. The plots of transit frequency and current density vs. gm/Id are
given in Fig. 5.16 and 5.17. We use the parameter gm/Id to indicate the degree of
inversion. From Fig. 5.16, we observe that a gm/Id of no less than 14 is required to
achieve the transit frequency of 18 GHz. In Fig. 5.17, we pick a current density of
1 The
gate to source voltages, Vgs , of M1 and M2 are increased to Q times the input voltage,
Vi+ or Vi . So the equivalent transconductance of the LNA is also Q times larger than the
transconductance of the dierential pair, as will be shown in Equ. 5.36.
5.4. LOW-NOISE AMPLIFIER 65
90
80
70
Transit Frequency (GHz)
60
50
40
30
20
10
0
0 5 10 15 20 25
gm/Id
2
10
Current Density (uA / um)
1
10
0
10
1
10
2
10
3
10
0 5 10 15 20 25
gm/Id
5.5
5
Gate Capacitance (fF)
4.5
3.5
3
0 5 10 15 20 25
gm/Id
Until now, the power dissipation is still unclear but the drain current to MOSFET
According to our bandwidth requirement of 500 MHz and the center frequency of
f0
Q= = 9. (5.38)
BW
Substituting this Q into Equ. 5.35, we can derive the Cgs requirement of
1
Cgs = = 39 fF. (5.39)
2QRs
The gate capacitance as a function of gm/Id is shown in Fig. 5.18 for a transistor
of 3.6 um. When gm/Id=12, we have a gate capacitance of around 5 fF. We need
to scale it 8 times larger to satisfy the Cgs requirement, which yields a MOSFET
width of 30 um.
RL RL Vo
Vbias Vo V
i
Vx Vbias
Vi
input by parasitics. For super-regenerative receivers, the ampliers output has large
The reverse coupling is mainly caused by the drain to gate capacitance, Cgd , of a
common-source stage. Commonly used techniques to mitigate the reverse coupling
of Cgd are the unilateralization and neutralization [35]. In this LNA design, the
Simulations show that a 10% mismatch of the neutralization MOSFETs still leads
to acceptable results.
5.4.4.1 Unilateralization
Unilateralization techniques plug in devices in series with the signal path to atten-
uate signals in one direction. The two commonly used unilateralization method are
the CS-CG and the CD-CG combinations, as shown in Fig. 5.19. Both schemes
are actually 2-stage designs exploiting the shielding eect of the CG stage. The
that the output resistance of a cascode stage is higher than that of a CD-CG stage.
This prevents the output resistance of the LNA from loading the oscillation tank of
The shielding eect of a cascode stage can be demonstrated by its reverse transfer
68 CHAPTER 5. RECEIVER CIRCUIT DESIGN
function
vx 1
= ro , (5.41)
vo gm ro + Ro1
+ sCgs ro + 1
where gm , ro and Cgs are the transconductance, drain-to-source resistance and gate-
to-source capacitance, and Ro1 are the output resistance of the CS stage. In this
expression, Cgd of the cascode is neglected for simplicity. In a reasonable design, the
second and the third term of the denominator in Equ. 5.41 cannot be much larger
2
than 1. So the main attenuation is given by the intrinsic gain of the cascode stage.
Since 90-nm short-channel devices have their intrinsic gain no more than 10, we
increase the length of the cascode MOSFETs to 200 nm. Further increase of length
has a diminished return of intrinsic gain but a more serious ft trade-o. Smaller ft
of the cascode transistors yields a smaller gm that is incapable of suppressing Miller
eect, and a large Cgs that lowers the 2nd pole. The 200 nm transistors provide an
intrinsic gain of 20, which implies a reverse isolation of -26 dB. Accounting for the
The preceding analysis shows that barely cascoding cannot provide sucient
5.4.4.2 Neutralization
Neutralization techniques plug in devices in parallel with the signal path to produce a
180-degree phase shift. Because the LNA has a dierential structure, it is convenient
to cross couple the output back using the equal amount of coupling capacitance. As
shown in Fig. 5.14, transistor M5 and M6 are identical with M1 and M2. The signal
coupled by Cgd of M5 has the same amplitude as that coupled by Cgd of M1, but is
180-degree out of phase. So the two signals cancel each other. The same eect is
The eect of cancellation highly depends on the matching of Cgd , which is not
only process- but also voltage-dependent. When devices are perfectly matched, the
total reverse isolation of -52 dB. A 10% mismatch analysis shows that all the LNA
unique problems are tackled in this design. Firstly, the super-regenerative oscillator
2 The
Miller eect is mitigated by letting 1/gm Ro1 , i.e. gm Ro1 1 which implies that Ro1
and ro are in the same order of magnitude. Furthermore, the 2nd pole at the node vx should not
be dominant, i.e. gm/Cgs = gm ro/Cgs ro BW , so signals within the bandwidth yield sCgs ro not
much larger than 1.
5.4. LOW-NOISE AMPLIFIER 69
Id
Zin
Cgs gm ro RL
Ls
following the LNA is a time-varying load. The large load variation leads to input
mismatch for bilateral ampliers. Secondly, special issues arise when neutralization
capacitors are used together with inductive degeneration. Last but not least, low-
1 1
Zin = + jLs (1 + ) = + jLs + T Ls (5.42)
jCgs jCgs
where = T/j is the forward current gain. This expression, however, implicitly
assumes RL ro . For most of LNAs, this condition is true or can be made true by
An SRO varies the tank conductance periodically between positive and negative
values. The maximum sensitivity of the SRO is obtained at the critical point, when
the total tank conductance is zero, as shown in Equ. 3.42. At this time point,
however, the load resistance to the LNA is innite. So we need a more accurate
The exact input impedance of the circuit shown in Fig. 5.20 is, after elaboration,
1 gm ro
Zin = + jLs || (ro + RL ) + Ls , (5.43)
jCgs Cgs ro + RL + sLs
where || denotes in parallel with. We can observe that when RL is small, Equ. 5.43
70 CHAPTER 5. RECEIVER CIRCUIT DESIGN
simplies to 5.42. On the other hand, when RL becomes large, the real part of the
input impedance decreases. At the critical point, when all the positive resistance
given by the tank and the LNA are canceled, the input impedance has no real part.
Intuitively, when the drain to ground resistance (RL in this case) is innite, no
current is owing into the drain and no current is owing out from the source. Source
We may expand this conclusion to all source current involved impedance matching
The LNA load and input resistance changing with the quenching wave is plotted
in Fig. 5.21. Our LNA designed so far has a dierential output resistance of around
15.8 kohm. When the absolute value of tank resistance is much (10 times) smaller
than 15.8 kohm, as denoted between the dashed lines in Fig. 5.21, the LNA is
ical point is fundamentally dicult. At the output side, to drive an innite resis-
tance, a voltage output should be used. But low output impedance loads the tank
and brings down the Q factor, which involves several dimensional trade-os. At
the input side, we need a low impedance to load the output of the LNA in order
not to inuence the input matching. This implies that a current buer should be
inserted in, between the LNA and the SRO. This implication justies the cascoding
applied in the rst place. Further cascoding does make the LNA more unilateral,
5.4.5.2 Neutralization
A simple inductive degeneration generates a real part of input impedance being pro-
A simple way to show the eect is to observe the current ow through gate-drain
and
Cgd = Cn = C , (5.46)
5.4. LOW-NOISE AMPLIFIER 71
Conductance Waveform
1
Conductance (mS)
0.5
0.5
1
0 10 20 30 40 50 60 70 80 90
Time (ns)
Load Resistance of LNA
10
Resistance (Kohm)
10
0 10 20 30 40 50 60 70 80 90
Time (ns)
Input Resistance of LNA
150
Resistance (ohm)
100
50
0 10 20 30 40 50 60 70 80 90
Time (ns)
in1 in2
Cn Cn
Vg1 Cgd i1 Vd1 Vd2 i2 Cgd Vg2
Cgs gm ro RL RL ro gm Cgs
Ls Ls
we have
i1 = (vd vg ) sC (5.47)
i2 = (vd vg ) sC (5.49)
Therefore, the current owing out of node vg1 via capacitances Cgd and Cn is
This extra current ow, ig1 , caused by Cgd and Cn , changes the input impedance
1 gm ro 1
Zin = + jLs || (ro + RL ) + Ls || . (5.52)
jCgs Cgs ro + RL + sLs 2jC
The input resistance of the LNA with and without the inuence of Cgd and Cn
(the real part of Equ. 5.42 and 5.52), as a function of the degenerated inductance,
Ls , are plotted in Fig. 5.23. Two phenomena can be observed from the graph.
larger Ls value. Secondly, Cgd and Cn cause a maximum of input resistance looking
into the gate. Before this maximum happens, an increase of the source inductance,
5.42 and 5.43. However, increasing Ls further after the peak of gate resistance can
160
140
120
Rin (ohm)
100
80
60
40
20
0
0 1 2 3 4 5 6 7 8 9 10
Ls (nH)
wide-band matching. The narrow-band matching turns the center frequencies of all
the cascading lters to the operating frequency. For low-loss networks, the insertion
loss could be close to 0 dB at the center frequency. The drawback is that the
bandwidth is determined by the Q factor of the network and the operating frequency.
The wide-band matching, on the other hand, tunes the cascading lters away from
the center in such a way that the stacked frequency response is at in the passband.
factor and the operating frequency. The penalty paid is the insertion loss, which
cannot be zero even if loss-less components are used. This LNA uses a narrow-band
matching technique, which yields the smallest insertion loss for a given number of
In order to achieve the 500 MHz bandwidth, we need the Q factor of the matching
network to be
f0 4.5 GHz
Q= = = 9. (5.53)
BW 500 MHz
Following analysis shows that this Q requirement is dicult to achieve for low-power
LNAs.
The matching network and its equivalent simplied representation are shown in
2 nH. The bond-pad and ESD (Electrostatic Discharge) diodes are all capacitance
paths to the ground, which constitutes parts of Cp0 . Cp , another capacitor is added
0
to Cp so they resonate with Lb at the operating frequency. The Q factor of this L
74 CHAPTER 5. RECEIVER CIRCUIT DESIGN
Vdd
Vdd
Rs Lb Pad Cs
M1
Vs Cp Lg
Cgs
Ls
R1 R2
Rs Lb Cs Cgs
Ls
match is
0 L 2 4.5 109 2 109
Q1 = = = 1.13. (5.54)
Rs 50
The resistance looking to the source after this transformation, denoted as R1 , is
At the input transistor's side, we split the shunt inductor Lg into Lg1 and Lg2 for
The rest of the network transforms this 5 kohm resistance down to 114 ohm, then
the matching is done. This transformation network, Cs and Lg1 should have a Q
factor of r
R2
Q3 = = 6.62 , (5.57)
R1
which requires the inductor to be
R2
Lg1 = = 26.7 nH. (5.58)
0 Q2
5.4. LOW-NOISE AMPLIFIER 75
Lg2 is resonating with the input capacitance of the transistor at 4.5 GHz, which is
1
Lg2 = = 14.2 nH, (5.59)
02 Cin
where
is the input capacitance looking into the gate of M1. The total inductance of Lg is
then
The preceding analysis argues that using loss-less components and fairly unlim-
ited values, the minimum-power LNA satisfying all the specications are feasible.
However, two practical problems destroy this feasibility. First of all, the limited
Q factor of Lg jeopardizes the gain and the noise gure of the LNA. For example,
nearly equal to the input resistance, R2 , calculated in Equ. 5.56. This leads to a
3 dB decrease of signal power and a 1.76 dB increase of noise power. This implies
a 3 dB gain reduction and 4.76 dB noise gure degradation. Secondly, one induc-
tor's value, Lg = 9.3 nH, is prohibitively large. It is worth mentioning that using
a shunt-inductor topology has yielded the minimum inductance possible, since the
2 inductors, Lg1 and Lg2 are in parallel. Even if the large physical dimension is
to be of any use.
The fundamental cause of these problems is the small power consumption and
thus the smallCin . If power is doubled, i.e. Cin is doubled, then Lg2 is halved, R2 is
quartered and Lg1 is thus halved, according to Equ. 5.59, 5.56 and 5.58, respectively.
Therefore, we are dealing with the ultimate power-gain-noise trade-o, but from a
power-aware perspective. We increase the width of the input MOSFETs and biasing
current to increase the gain and decrease the noise gure until they satisfy the LNA
network. The total capacitance between the chip-input to the ground, shown as Cp0
in Fig. 5.24, is resonating with Lb at 4.5 GHz. So it has a value of
1
Cp0 = = 625 fF. (5.62)
02 Lb
76 CHAPTER 5. RECEIVER CIRCUIT DESIGN
ESD Current
1.5
Current (A)
1
0.5
0
0.5 0 0.5 1 1.5 2 2.5 3
Time (us)
Pad Voltage
3
Voltage (V)
0
0.5 0 0.5 1 1.5 2 2.5 3
Time (us)
The parasitics of Cs also take several fF. The rest capacitance budget is given to
ESD devices.
We utilize the double-diode ESD protection scheme with minimum dimension for
its minimum additional capacitance. A 2 kV HBM (Human Body Model) ESD event
is applied to the input and ground. The voltage at the input node and the current
owing through the diodes are plotted in Fig. 5.25. We can observe a maximum
manual [33]. For a product lifetime of 100 KPOH (thousand of power-on hours), a
gate-biasing voltage of 594 mV, this protection scheme can withhold a total amount
The same ESD event applied between the input and the Vdd is also veried with
no gate-oxide breakdown.
The S11 of the LNA from 4 to 5 GHz is shown in Fig. 5.26. It can be observed
from the plot that the LNA is matched well at 4.5 GHz, with an S11 of -37.5 dB. At
4.25 and 4.75 GHz, the S11 is 5.3 and 6.5 dB, respectively. S11 is not matched to
-10 dB in the whole 500 MHz bandwidth since low power low-Q matching involves a
5.4. LOW-NOISE AMPLIFIER 77
S11
0
10
15
S11 (dB)
20
25
30
35
40
4 4.1 4.2 4.3 4.4 4.5 4.6 4.7 4.8 4.9 5
Frequency (GHz)
to 50% of its power at the edge of the bandwidth. The -3 dB S11 happens at 4.13
GHz and 4.99 GHz frequency. Hence, for a low-loss input matching network, the -3
The forward power gain, S21, is plotted in Fig. 5.27. As shown in the graph,
by the load of the LNA. This bandwidth barely means that the load resonant tank
has a Q factor of
f0 4.5 GHz
Q= = = 20.5 . (5.63)
BW 220 MHz
The reverse power gain of the LNA is shown in Fig. 5.28. As shown in the
graph, a minimum of 52 dB reverse isolation is obtained, satisfying the S12 < -39.4
limitation is satised.
The noise gure of the LNA is shown in Fig. 5.29. As shown in the graph, the
minimum noise gure of 2.5 dB is achieved at 4.5 GHz. At 4.25 and 4.75 GHz, the
Two current paths each draws 1.22 mA from the 0.9 V supply. Therefore, the
LNA consumes 2.2 mW power. This continuous power consumption can be reduced
by duty cycling using an auxiliary circuit, which biases the LNA dynamically during
the SRO sampling period and turns it o during the quenching period.
78 CHAPTER 5. RECEIVER CIRCUIT DESIGN
S21
16
14
12
10
S21 (dB)
2
4 4.1 4.2 4.3 4.4 4.5 4.6 4.7 4.8 4.9 5
Frequency (GHz)
S12
50
55
60
S12 (dB)
65
70
75
4 4.1 4.2 4.3 4.4 4.5 4.6 4.7 4.8 4.9 5
Frequency (GHz)
Noise Figure
4.4
4.2
3.8
Noise Figure (dB)
3.6
3.4
3.2
2.8
2.6
Auxiliary Circuits
6.1 Introduction
Super-regenerative receivers need auxiliary circuits to work properly. First of all,
every SRO needs a time-varying biasing. The complexity of biasing circuits depends
a large voltage swing and low-power dissipation, this design uses a special waveform
possible if the LNA is shut down during the quenching period. Super-regenerative
receivers are inherently sampling circuits which deal with only discrete time signals.
LNA is only useful in certain periods to provide gain and matching. At the rest of
the time, it can be put to rest for power saving consideration as long as its reverse
demodulated subcarrier. This stage is mainly designed for testing and measurement
reference circuit is designed for the biasing of all the functional blocks.
The detailed design of the biasing waveform generator for SRO, the dynamic
biasing circuit for LNA, the output buer and the current reference are presented
ied in Subsection 5.2.4 to bias the SRO. We assume that an external clock is
available. The duty cycle of the clock should be tunable in order for the SRO to
have a variable gain. The peak of biasing waveform is also designed to be exter-
nally tunable, so that the external control of the oscillation amplitude, gain, and
80
6.2. BIASING WAVEFORM GENERATOR FOR SRO 81
Vdd Vdd
SRO
Vclk M1 C
Vamp Rf
Ibias
Ri M2
+
M3 M4 OTA
M5 M6
circuit rst converts the external rectangular clock signal into a saw-tooth voltage
tance block.
half of the circuit shown in Fig. 6.1. The circuit consists of a capacitor, 2 switches
M1 and M2, a resistor Ri and a current mirror formed by transistor M3 and M4.
charged by the DC current, and the voltage across the capacitor is growing linearly
with time. When a positive to negative transition of the clock occurs, M2 becomes
open and M1 is closed, which short-circuits the capacitor and discharges it sharply.
This short is continued until the next positive cycle begins. In this way, the shape
voltage Vamp . A large voltage yields a large current charging the capacitor, and for
the waveform preserved. The circuit is shown in the right part of Fig. 6.1, which
82 CHAPTER 6. AUXILIARY CIRCUITS
0.9
0.8
0.7
0.6
|Y(f)|
0.5
0.4
0.3
0.2
0.1
0
0 100 200 300 400 500 600 700 800 900 1000
Frequency (MHz)
The OTA, transistor M5 and Rf form a negative feedback loop. For a given gate
voltage of M5, a current is generated. Resistor Rf converts this current into a voltage
and feeds it back to the positive input of the OTA. If this voltage is higher than the
voltage across the capacitor, the OTA applies a positive incremental voltage to the
gate of M5, which yields an increased current and a reduced voltage at the positive
input of the OTA. In this way, the negative feedback linearize the transconductance
Io 1
GM = (6.1)
Vin Rf
the OTA. Therefore, the design goal for this OTA is to minimize the power while
6.2.4.1 Specication
The power of an OTA is determined by its gain-bandwidth product. For a cascode
structure, the DC gain is a fairly constant value while the bandwidth is not. So
6.2. BIASING WAVEFORM GENERATOR FOR SRO 83
we need to specify the minimum bandwidth requirement for the OTA. A discrete
Fourier transform yields the amplitude spectrum of the saw-tooth biasing waveform.
Its normalized version is plotted in Fig. 6.2. As can be observed from the graph,
the main power of the biasing waveform is concentrated in frequencies below 500
ADC
Av = , (6.3)
1 + j ffc
where ADC and fc are the DC-gain and -3 dB bandwidth, respectively. Then the
Av gm ADC gm
GMcl = = , (6.4)
1 + Av gm Rf 1 + ADC gm Rf + j ffc
loop transconductance is
available for this technology, ADC is around 100 or 40 dB. Since the output current
of M5 is a biasing waveform, gm is signal dependent and time-varying. To simplify
the calculation, we further assume that the loop-gain is mainly supplied by the OTA,
i.e.
gm Rf 1. (6.6)
BW3dB
fc = 5 MHz. (6.7)
1 + ADC
Equ. 6.6 determines a trade-o between the power consumption and tracking
errors at the start of ramps. If we assume gm Rf 1, we need a fast OTA with large
fc , consuming quite some power. On the other hand, if we assume gm Rf 1, it is
invalid at the starting up of a ramp, since the drain current of M5 is small, so is the
Vdd
Vin Vip
current slope deviating from its voltage reference can be observed. The simulation
structure is used for its high gain compared with those using uncascoded current
sources as loads. Since the input voltage ranges from 500 mV to 900 mV, a pair of
The lengths of all the transistors are scaled to 200nm for the improved intrinsic
gain and reduced threshold voltage. All transistors are biased in moderate inversion
GHz. The NMOS transistors have a basic width of 10 um except the input ones,
which are 40 um wide. PMOSs are 3 times larger in width. As a result, 100 uA is
voltage, op-amp virtual ground, the gate voltage of the tail current source and the
biasing voltage for the SRO are shown in Fig. 6.4. The amplitude control voltage,
From the saw-tooth waveform at the second row, we can observe the charge-
injection eect caused by the small capacitor and comparatively large switches.
The small capacitor is desirable since a small current is needed to charge it. Large
switches are used so that the conducting resistance is small. Charge injection is not
6.2. BIASING WAVEFORM GENERATOR FOR SRO 85
External Clock
1000
Voltage (mV)
500
0
0 20 40 60 80 100 120 140
Time (ns)
Sawtooth Voltage Waveform
1000
Voltage (mV)
800
600
0 20 40 60 80 100 120 140
Time (ns)
Virtual Ground
1000
Voltage (mV)
800
600
0 20 40 60 80 100 120 140
Time (ns)
OpAmp Output Voltage
600
Voltage (mV)
400
200
0 20 40 60 80 100 120 140
Time (ns)
SRO Biasing Current
1.5
Current (mA)
0.5
0
0 20 40 60 80 100 120 140
Time (ns)
a serious issue in this application because the continuous charging and discharging
current conducts the charges quickly and the limited bandwidth of the feedback loop
By carefully inspecting the biasing current waveform shown in the bottom of Fig.
6.4, a slope deviation can be observed at the starting part of a ramp. This eect
their gates is low. At this phase, Equ. 6.6 is not satised and the loop-gain of the
transconductance loop is small, yielding this tracking error. Careful simulations are
performed to formulate Equ. 6.6 in such a way that the tracking error only appears
before the SRO is reaching its critical point. So the biasing slope at the critical
The op-amp constantly drains 408 uA from the 0.9 V power supply. The current
sensor path (Rf and M5), op-amp biasing and the switched capacitor consume 26
Two measures can be taken to trade performance o for less power. Firstly,
the 500 MHz bandwidth specied in Equ. 6.2 can be compromised, which leads to
larger contribution to the loop gain by violating Equ. 6.6, which causes larger slope
deviation at the starting part of a ramp. Both measures degrade the controllability
of the SRO.
The power dissipation of this biasing circuit is 1.6 times as large as that consumed
by the SRO. This extra power consumption, caused by the complex saw-tooth cur-
rent generator brings us back to the selection of the biasing waveform for the SRO.
biasing causes power overhead that outweighs the benet. An SRO working in
step-controlled state is, under the circumstances, worth a try (see Section 7.3).
are sampling ampliers, which amplify only a portion of the signal in a certain
period. For the power-saving purpose, LNAs can be turned o when SROs are in
the quench period or when oscillations have already been built up.
point. Signals right before a transition are at least as important as they are after
6.3. DYNAMIC BIASING FOR LNA 87
Dynamic Ibias
Biasing
Network Lg
Cs
M1 M2
Cp
Ls
the transition. So an LNA should start working before an SRO is turned on.
How long an LNA should start before an SRO depends on the characteristics
of both of them. Intensive analysis in Chapter 3 deals with the sensitivity curve of
SROs. This subsection analyzes the warm-up time of the LNA introduced in Section
5.4.
The schematic involving the dynamic biasing of the LNA is shown in Fig. 6.5.
Transistor M2 is the input stage of the LNA. Inductors Ls and Lg and capacitors
Cs and Cp are used for input power matching. Transistor M1 is a part of a current
mirror, which feeds the biasing voltage through Lg to the gate of M2. The biasing
current source is controlled by switching events and thus it can be treated as a step
stimulus.
When a steep power-up current is generated, it faces 2 paths. The rst path
is the resistance of the diode-connected MOSFET M1, which is around 1/gm . The
At high frequencies, this second path has a lower impedance than that of M1. So
the initial part of the power-up current is bypassed, without generating a voltage
through M1.
since the bypassing components are also parts of the power matching network, which
should not be modied. Simulation result (plotted in the bottom of Fig. 6.11) shows
and a NAND gate to deal with logics, and a switch, M6, to quench the current
88 CHAPTER 6. AUXILIARY CIRCUITS
Vdd Vdd
Vclk Vswt
M1 C M6
M4 M5
M2 Vrmp +
CMP Vcmp Iref Ibias
Vref
M3
LNA
Figure 6.6: The schematic of the dynamic biasing network for LNA.
mirror.
The ramp voltage generator converts the negative portion of the clock into a
ramp. The detailed mechanism is identical with the other one discussed in Subsec-
tion 6.2.2.
an external reference voltage, Vref . By doing this, Vref is able to control the amount
The logics enforce the LNA to work at both the warm-up and the amplication
period. The waveform of the node voltages are shown in Fig. 6.7. In the gure, Vclk
is inverted at rst. Then its quenching parts are converted to ramps, denoted as
Vr . After that, the comparison between Vref and Vr generates positive to negative
transitions of Vcmp . It is these transitions that trigger the start-up of the LNA.
Finally, the NAND combines the warm-up period and the working period of the
LNA into one signal, Vswt , which controls the switch of the current mirror M6.
The physical dimension of the switch, M6, involves the trade-o between charge
injection and current leakage. A large M6 has a small conducting resistance and
the LNA is quenched completely. However, charge injection can be clearly observed.
On the other hand, a small M6 has a relatively large on-resistance. When Iref is
owing through this resistance, the voltage drop leads to a leaking current owing
in the LNA. A compromise between the two yields the dimension of M6 as L=100
6.3.2.1 Comparator
The schematic of the comparator is shown in Fig. 6.8. The input stage is an N-input
dierential pair with a current mirror as the load. Its main purpose is to provide
gain. The second stage is an NMOS driving a PMOS current source. Extra gain
6.3. DYNAMIC BIASING FOR LNA 89
Vclk
/Vclk
Vrmp Vref
Vcmp
Vswt
Ibias
and a rail-to-rail voltage swing are provided by this stage. Since the load of this
comparator is an NAND gate, which has a small dimension, the comparator also
use small transistors (L=200 nm, W=1 um). Biasing current of 10 uA is consumed
drives M1, M2 and the NAND gate, it has a width of 10 um for the NMOS and
20 um for the PMOS. The NAND gate only drives the switch M6, so it has the
minimum dimension. Because NMOSs in the NAND gate is in series, they have the
period ranging from 0 to 20 ns, i.e. 16 mV/ns. After the LNA and the SRO are
plugged in, simulations further show that a power-o period ranging from 0 to 17.5
ns produces almost identical SRO output amplitude compared with one another.
For a 17.5 ns power-o, the control voltage, Vref should be 620 mV.
90 CHAPTER 6. AUXILIARY CIRCUITS
Vdd Vdd
Vbiasp
Vcmp
Vrmp Vref
Vbiasn
Vdd Vdd
A B
X Y
Y
The transient results of node voltages and the biasing current are plotted in Fig.
6.10 and 6.11. The simulation is performed at a control voltage of 620 mV.
Fig. 6.10 is the simulated version of Fig. 6.7, showing the external clock, the
inverted clock, the voltage ramp, the comparator output and the switching signal.
Fig. 6.11 plots the switching signal again with the gate voltage of the mirror,
the gate voltage of the input pair and the LNA current. The slow start-up behavior
The power consumption of this dynamic biasing circuit consists of the static
power, consumed by the rst stage of the comparator and the current mirror, and
the dynamic power, consumed by the logic gates, the switched-capacitor and the
second stage of the comparator. All the dynamic power caused by gate switching
is neglected in this analysis since the power supply voltage is low and the gates are
small. The static current consumed is 30 uA, consisting of 20 uA by the rst stage of
the comparator and 10 uA by the current mirror of the LNA (M4 in Fig. 6.6). The
average of the dynamic current consumed is between 5.7 uA to 11.4 uA, depending
on the duty-cycle of the comparator output. In detail, the switched capacitor draws
5.7 uA in average and the second stage of the comparator draws 0 to 5.7 uA. In
conclusion, this dynamic biasing circuit draws around 36-to-42 uA current from the
At a control voltage of 620 mV (the best power saving situation without perfor-
mance degradation), the average biasing current of the LNA is 601 uA single-ended
and 1.20 mA in total, compared with the 2.44 mA current consumption if the LNA
operating frequency. Vref controls the warm-up time of the LNA. By tuning these
500
0
0 10 20 30 40 50 60 70 80 90 100
Time (ns)
Inverted Clock (/Vclk)
1000
Voltage (mV)
500
0
0 10 20 30 40 50 60 70 80 90 100
Time (ns)
Voltage Ramp (Vrmp)
1000
Voltage (mV)
800
600
0 10 20 30 40 50 60 70 80 90 100
Time (ns)
Comparator Output (Vcmp)
1000
Voltage (mV)
500
0
0 10 20 30 40 50 60 70 80 90 100
Time (ns)
Switching Voltage (Vswt)
1000
Voltage (mV)
500
0
0 10 20 30 40 50 60 70 80 90 100
Time (ns)
Figure 6.10: The transient simulation result of the dynamic biasing network.
6.4. OUTPUT BUFFER 93
800
Voltage (mV)
600
400
200
0
0 10 20 30 40 50 60 70 80 90 100
Time (ns)
Gate Voltage of the Mirror (M4 and M5)
1000
800
Voltage (mV)
600
400
200
0
0 10 20 30 40 50 60 70 80 90 100
Time (ns)
LNA Biasing Voltage
600
Voltage (mV)
500
400
300
0 10 20 30 40 50 60 70 80 90 100
Time (ns)
LNA Drain Current
1.5
Current (mA)
0.5
0
0 10 20 30 40 50 60 70 80 90 100
Time (ns)
Figure 6.11: The transient simulation result of the LNA under dynamic biasing.
94 CHAPTER 6. AUXILIARY CIRCUITS
100
50
0
0 50 100 150 200 250 300 350 400 450 500
Time (ns)
Amplitude Spectrum of the Ouput Pulses
Normalized Amplitude Spectrum
0.8
0.6
0.4
0.2
0
0 50 100 150 200 250 300 350 400
Frequency (MHz)
signal which contains abundant information is the pulses at the output of the peak
detector. By observing this signal, the operating frequency, gain, pulse shapes,
The output signal to be buered is plotted at the top of Fig. 6.12. It can be
observed that a maximum voltage swing of 150 mV is required for the output buer.
amplitude spectrum is plotted at the bottom of Fig. 6.12. As shown in the graph,
a bandwidth of around 300 MHz is needed to preserve most of the output signal
power.
The signal source, i.e. the peak detector, has a specic output capacitance of 100
fF, which should not be inuenced. Otherwise, the discharge time constant of the
peak detector would be modied and a reduced conversion gain and slow tracking
The rst stage is a folded cascode OTA with NMOS input dierential pair. We
choose a folded cascode input for its large gain compared with single dierential
pair and small voltage headroom requirement compared with a telescopic structure.
The NMOS input pair is chosen since the input biasing is relatively high, around
570 mV.
The second stage is an NMOS common source with a PMOS current source. The
main purpose of this stage is to drive the 20 pF capacitive load. A source follower
is not used in this design since the limited voltage swing of the previous stage and
The lengths of all the transistors are scaled to 200nm for the improved intrinsic
gain and reduced threshold voltage. All transistors are biased in moderate inversion
to balance the speed and power consumption. More specically, the overdrive voltage
is selected to obtain a gm/Id of 15, which yields a current density of 10 uA/um and
a transit frequency of 1 GHz. The second stage has a width of 600 um (1800 um for
the PMOS), in order to have a biasing current of 6 mA and a slew rate of 0.3 V/ns.
The rst stage is a 3 times scaled version of the OTA designed in Subsection 6.2.4
The input capacitance of this buer stage is around 128 fF, slightly larger than
the 100 fF capacitor used in the peak detector. Simulations show that the sub-
stitution of the 100 fF capacitor used in the peak detector by this 128 fF input
The buer amplier has its own power supply so that the power consumption of
the frequency compensation, plotted in Fig. 6.14. As shown in the graph, a phase
A transient simulation is performed, and the voltage output of the peak detector
and the buered version are plotted in Fig. 6.15. From the graph, nearly identical
96 CHAPTER 6. AUXILIARY CIRCUITS
+ Vdd Vin M1 M2
Cc Load
Ibias Ibias
This output buer draws 9.86 mA from a 0.9 V power supply, i.e. a power
reference.
M1 and its K times scaled up version, M2, have a square-law I-V relationship, so the
voltage between their gates are nonlinearly depending on their drain currents, which
are forced to be equal by a current mirror (M3 and M4). On the other hand, the
resistor, R, has a linear I-V relationship. In order for the voltage between the gates
of M1 and M2 and the voltage across the resistor to be equal, the drain current of
M1, or M2, has to be a certain value (besides zero), dened by the cross point of
the nonlinear curve and the linear one. M5 is a start-up device which guarantees a
current ow at zero condition. The capacitor, C, bypasses voltage variation caused
Amplitude Response
60
50
40
Amplitude (dB)
30
20
10
10
20
0 1 2 3 4 5 6 7 8 9
10 10 10 10 10 10 10 10 10 10
Frequency (Hz)
Phase Response
0
50
Phase (degree)
100
150
200
0 1 2 3 4 5 6 7 8 9
10 10 10 10 10 10 10 10 10 10
Frequency (Hz)
Considering chip area and process variation, R is chosen to be 1 kohm. For a peaking
current source, the current is not a monotonic growing function of the power supply.
the power supply sensitivity, K is chosen in such a way that the current is locally
independent on the voltage supply around the nominal current value. This condition
The current vs. the supply voltage is plotted at the left of Fig. 6.17. The peak
of the current is tuned to the nominal power supply voltage of 0.9 V. The derivative
variation (from 0.81V to 0.99V) causes a maximum output change from 95.64 uA
from 88 to 115 uA as plotted at the right of Fig. 6.17. Thus, a positive temperature
720
700
680
Voltage (mV)
660
640
620
600
580
560
0 50 100 150 200 250 300 350 400 450 500
Time (ns)
Buffer Output
740
720
700
680
Voltage (mV)
660
640
620
600
580
560
0 50 100 150 200 250 300 350 400 450 500
Time (ns)
Figure 6.15: Voltage output of the peak detector and the buered version.
6.5. CURRENT REFERENCE 99
Vdd
M3 M4
M5
R
M2
M1 C
95.5 115
95 110
94.5 105
Ibias (uA)
Ibias (uA)
94 100
93.5 95
93 90
92.5 85
0.7 0.8 0.9 1 1.1 0 20 40 60 80
Vdd (V) Temperature (Celsius)
Power Supply
1
0.8
Voltage (V)
0.6
0.4
0.2
0
0.2
0 10 20 30 40 50 60 70 80 90 100
Time (ns)
Output Current (Without Startup Device)
120
100
Current (uA)
80
60
40
20
0
0 10 20 30 40 50 60 70 80 90 100
Time (ns)
Output Current (With Startup Device)
120
100
Current (uA)
80
60
40
20
0
0 10 20 30 40 50 60 70 80 90 100
Time (ns)
supply voltage of 0.9 V is applied as a 1 ns step, shown at the top of Fig. 6.18. The
responses of the circuits with and without the start-up device (transistor M5) are
shown at the bottom and middle of Fig. 6.18, respectively. From the gure, it is
observed that transistor M5 accelerates the start-up of the current reference circuit
signicantly.
Chapter 7
Receiver Performance
7.1 Introduction
In Chapter 5 and 6, circuit blocks of the UWB-FM super-regenerative receiver are
Section 7.2 introduces the simulation setup and presents the results. A test-
bench is designed to simulation the system consisting of all the building blocks in
the circuit level. Simulation results are compared with the receiver specication
procedure leads to further power reduction, since the individual power minimization
for each block does not necessarily yield the minimum power in total.
completely. Only the transient analysis, using the method of time domain numerical
noise generator. Depending on the power of a noise source, the random noise gen-
dynamical system with internal noise. At each integration step, random numbers
101
102 CHAPTER 7. RECEIVER PERFORMANCE
Vfrq SRO
DB WG Iref
are generated at rst, representing the value of noise sources at that time. Then,
these noise signals, together with other deterministic signals are used as stimuli to
the system. After that, nodal analysis is performed to calculate the instantaneous
node voltages and loop currents. At last, the voltages across capacitors and the
currents owing through inductors are calculated by numerical integration for the
We use the transient noise analysis to characterize the noise performance of the
signal. The RMS value of the output is the signal power. Then, several passes of
transient noise analysis are performed to the receiver with no RF excitation. The
mean of the RMS value of the outputs is the noise power. In this way, the output
SNR is obtained and the noise gure of the receiver can be calculated.
There are three issues need to be justied before applying the aforementioned
assumption is valid as long as the SRO is working in the linear region, as indicated
in Equ. 3.31. Secondly, the output noise is implicitly assumed to be stationary and
ergodic. Otherwise, many long noise sample paths are required to calculate the noise
power. Thirdly, the noise samples to calculate the statistical variance is assumed
to be enough. Two passes of 5000 ns transient noise simulation results are used to
calculate the RMS noise power. We do not have enough computation power to do
Gain (dB)
L1 C1 R2
563 nH 11.3 nF 50
15
20
1.6 1.7 1.8 1.9 2 2.1 2.2 2.3 2.4
Frequency (MHz)
front-end to be evaluated consists of all the circuit blocks introduced in the previous
chapters, namely the LNA, SRO, peak detector (PD), waveform generator (WG) for
SRO, dynamic biasing (DB) for LNA, output buer (BUF) and the current reference
(Iref ).
(VCO) being controlled by a 1 MHz triangular subcarrier (Vsc ). The VCO oscillates
at 4.5 GHz when Vsc is zero, and it has a gain of 500 MHz/V. Vsc has a peak-to-peak
value of 1 V and a DC value of zero. In this way, the output of the VCO is an
FM modulated signal having a center frequency of 4.5 GHz and a bandwidth of 500
MHz.
According to Equ. 4.4, the received power is -80 dBm for a communication range
of 10 meters. This signal power should generate a 31.6 uV voltage across the input
impedance of LNA of 100 ohm. To take the LNA matching into consideration, we
plug in two 50 ohm resistors, R1 and R2, and double the voltage output of VCO to
63.2 uV. As a result, the input power to the LNA is -80 dBm if it is power matched.
The output of the receiver is passed through a bandpass lter (shown as BPF in
the gure). This lter has two functions. Firstly, it recovers the subcarrier from the
Secondly, the processing gain is obtained by this lter, so that the noise gure or
in this test-bench. The schematic and the frequency response of this lter are shown
in Fig. 7.2. As shown in the graph, the lter has a 2 MHz center frequency and a
400 kHz bandwidth. As a result, it passes through the FSK modulated subcarrier
The reason that this lter is not integrated on-chip is because the back-end of the
receiver, i.e. the FSK demodulator, may not require this lter at all. For example,
if the noncoherent FSK detection is performed, two detuned bandpass lters can
the input subcarrier, SRO oscillation, its envelope and the output after bandpass
lter are plotted in Fig. 7.3. As shown in the graph, the receiver is capable of
AM signal, and the noncoherent detection of this DSB-AM signal neglects the phase
The transient noise simulation is performed to the test-bench with zero RF input.
The voltage outputs of the SRO, the peak detector and the bandpass lter are plotted
in Fig. 7.4. The SRO oscillation in this simulation is caused by the noise only.
Comparing the amplitudes of the pulses from Fig. 7.4 to that shown in Fig.
7.3, we observe that the noise generates larger pulses than the signal does. In
other words, noise power is larger than the signal power. The only property that
distinguishes signal from noise is that the signal power is concentrated in a specic
frequency band while the noise power is evenly distributed. The bandpass lter in
the test-bench lters out all the out-of-band noise, so that noise power is reduced
while the signal power is left intact. The comparison of the Vbpf signals shown in
The output signal-to-noise ratio is calculated by the RMS value of the signal
voltage of the signal divided by the largest peak-to-peak voltage of the noise yields
The whole receiver excluding the output voltage buer draws 2.273 mA in average
reduction of dynamic range, and consumes more power for the same voltage swing,
bias the SRO. This generator consumes extra power, which is even more than that
of the SRO, as discussed in Section 6.2. It is possible to reduce this extra power but
On the other hand, the biasing circuit for a step-controlled SRO is much simpler.
It can be implemented by a current mirror with its gates periodically pulled down
7.3. GLOBAL POWER REDUCTION: A STEP-CONTROLLED SRO 105
Subcarrier (Vsc)
0.5
Voltage (V)
0.5
0 500 1000 1500 2000 2500 3000 3500 4000 4500 5000
Time (ns)
SRO Oscillation (Vosc)
200
Voltage (mV)
200
0 500 1000 1500 2000 2500 3000 3500 4000 4500 5000
Time (ns)
Peak Detector Output (Venv)
150
Envelope (mV)
100
50
0
0 500 1000 1500 2000 2500 3000 3500 4000 4500 5000
Time (ns)
Bandpass Filter Output (Vbpf)
4
Envelope (mV)
4
0 500 1000 1500 2000 2500 3000 3500 4000 4500 5000
Time (ns)
200
100
Voltage (mV)
100
200
300
0 500 1000 1500 2000 2500 3000 3500 4000 4500 5000
Time (ns)
100
50
0
0 500 1000 1500 2000 2500 3000 3500 4000 4500 5000
Time (ns)
0.5
Envelope (mV)
0.5
1
0 500 1000 1500 2000 2500 3000 3500 4000 4500 5000
Time (ns)
Conductance Waveform
Conductance (mS)
0.5
0.5
1
0 10 20 30 40 50 60 70 80 90 100
Time (ns)
Tailcurrent Waveform
1
Current (mA)
0.5
0 10 20 30 40 50 60 70 80 90 100
Time (ns)
by a clocked switch.
Therefore, applying step-control may lead to global power reduction, despite the
dynamic biasing circuit for the SRO and that for the LNA. In the adapted version
applying the step-control, the SRO is tuned slightly, the biasing waveform generator
is substituted by a switch, and the logic is inverted for the dynamic biasing of the
LNA. The rest of the circuit blocks, namely the LNA, the peak detector, the output
buer and the current reference, are utilized in the new design without modication.
start-up and quenching needs a rectangular waveform. The ideal conductance wave-
form yielding the optimum frequency response is plotted in the top of Fig. 7.5.
In the plot, the negative conductance is set to -0.681 mS according to Tab. 5.1.
And the duration of the negative conductance is 16.5 ns determined by the certain
The required waveform of this source is shown in the bottom of Fig. 7.5.
108 CHAPTER 7. RECEIVER PERFORMANCE
there is still one degree of freedom to select the biasing current or transistor widths.
This selection involves the dynamic range - power trade-o discussed in Subsection
5.2.5. Basically, a small biasing current and large transistors are power saving but
the dynamic range is limited. A large biasing current requires small transistors to
generate a certain negative conductance. This large current density yields large
current density exists for a certain negative conductance and voltage supply.
Extensive simulations show that this optimum is achieved when the biasing tail
current is 1 mA and the width of each transistor of the cross coupled pair is 5 um.
in Fig. 7.6. Both the SRO and LNA are biased by current mirrors with switches
attached to the gates. When either one is quenched, the corresponding switch is
closed to pull down the gate voltage and shut down the current ow.
The switch quenching the SRO is directly controlled by an external clock. The
other one quenching the LNA is controlled by a delayed version of the external clock.
As is shown in the top of Fig. 7.6, the delay-line is a logically inverted version of
the one discussed in Section 6.3. The simulated node voltages and biasing currents
shown in Fig. 7.8 and Fig. 7.9, for signal and noise excitation, respectively. The
same conservative estimation using the peak-to-peak voltage of the signal divided
by the largest peak-to-peak voltage of the noise yields an output SNR of 13.2 dB.
buer draws 1.996 mA in average from a 0.9V voltage supply. Thus, a power con-
the other step-controlled, are designed for UWB-FM reception. Test-bench sim-
ulations indicate that both designs satisfy the system specication. Under this
Vdd
Vref
Vclk M1 C CMP Vcmp
+
M2
Vswt
M3
Vdd
Vamp
SRO LNA
Vclk M4 Vswt M5
Figure 7.6: The dynamic biasing circuits for the SRO and the LNA.
Slope-controlled Step-controlled
Table 7.1: The comparison of current consumption between the slope- and step-
controlled receivers.
110 CHAPTER 7. RECEIVER PERFORMANCE
External Clock
1000
Voltage (mV)
500
0
0 10 20 30 40 50 60 70 80 90 100
Time (ns)
Voltage Ramp
1000
Voltage (mV)
800
600
0 10 20 30 40 50 60 70 80 90 100
Time (ns)
Comparator Output
1000
Voltage (mV)
500
0
0 10 20 30 40 50 60 70 80 90 100
Time (ns)
LNA Switching Voltage
1000
Voltage (mV)
500
0
0 10 20 30 40 50 60 70 80 90 100
Time (ns)
LNA Biasing Current
Current (mA)
0.5
0
0 10 20 30 40 50 60 70 80 90 100
Time (ns)
SRO Biasing Current
Current (mA)
0.5
0
0 10 20 30 40 50 60 70 80 90 100
Time (ns)
Figure 7.7: Delay-line voltages and biasing currents of the SRO and the LNA.
7.3. GLOBAL POWER REDUCTION: A STEP-CONTROLLED SRO 111
Subcarrier (Vsc)
0.5
Voltage (V)
0.5
0 500 1000 1500 2000 2500 3000 3500 4000 4500 5000
Time (ns)
SRO Oscillation (Vosc)
300
200
Voltage (mV)
100
0
100
200
300
0 500 1000 1500 2000 2500 3000 3500 4000 4500 5000
Time (ns)
Peak Detector Output (Venv)
150
Envelope (mV)
100
50
0
0 500 1000 1500 2000 2500 3000 3500 4000 4500 5000
Time (ns)
Bandpass Filter Output (Vbpf)
4
Envelope (mV)
4
0 500 1000 1500 2000 2500 3000 3500 4000 4500 5000
Time (ns)
200
100
Voltage (mV)
100
200
300
0 500 1000 1500 2000 2500 3000 3500 4000 4500 5000
Time (ns)
100
50
0
0 500 1000 1500 2000 2500 3000 3500 4000 4500 5000
Time (ns)
0.5
Envelope (mV)
0.5
1
0 500 1000 1500 2000 2500 3000 3500 4000 4500 5000
Time (ns)
Besides the power consumed by the LNA, peak detector and the biasing, which
are nearly equal for the two receivers, the power dissipation of the SRO and its
dynamic biasing circuit is listed in Tab. 7.1. We can observe from the table that
although the slope-control yields a smaller SRO power consumption than the step-
control does, as predicted theoretically in Subsection 5.2.4, the extra power used to
generate the complex waveform outweighs its benet. In contrast, the step-control
is power consuming in principle, but the simple power management circuit leads to
Conclusions
mand receivers with low complexity and low power consumption. In this research, a
designed to detect 500 MHz bandwidth UWB-FM signals at 4.5 GHz. Circuit sim-
ulations show that a receiver sensitivity of -82.2 dBm is attainable for a 100 kbps
baseband data-rate and 106 bit-error-rate. The whole circuit draws an average of
Tab. 8.1 compares the performance of this work with another two recently
quenching waveform for WBFM detection and a novel low-power driven design pro-
114
8.2. FUTURE WORK 115
surement of this design is necessary to make the point more concrete. Industrial
band interference [28, 38]. The multiuser capability is briey discussed in Section
4.2. The feasibility of using this receiver for subcarrier FDMA requires further study
the most at the center frequency, 4.5 GHz, and the least at 4.25 and 4.75 GHz. The
The current design of this receiver assumes an external clock to quench the os-
cillation periodically. However, it leaves the freedom of generating this clock to the
and presumably low power consumption. The penalty paid is the reduced dynamic
range. Whether the dynamic range reduction is acceptable for UWB-FM applica-
cording to Section 5.2, the lower bound of power consumption is ultimately limited
by the quality factor of the resonator. In the literature, bulk acoustic wave (BAW)
micro-watt power levels. The extra benet of using high-Q devices includes the
State Circuits, IEEE Journal of, vol. 33, pp. 21862196, Dec 1998.
regenerative receiver at 1 ghz, Solid-State Circuits, IEEE Journal of, vol. 36,
Circuits, IEEE Journal of, vol. 36, pp. 10251031, Jul 2001.
[7] J.-Y. Chen, M. Flynn, and J. Hayes, A fully integrated auto-calibrated super-
transceiver with ultra low duty cycle and a 675w high impedance super-
Oct. 2007.
[9] B. Otis, Y. Chee, and J. Rabaey, A 400 /spl mu/w-rx, 1.6mw-tx super-
117
118 BIBLIOGRAPHY
communications, VLSI Circuits, 2008 IEEE Symposium on, pp. 3233, June
2008.
[11] J. Gerrits, J. Farserotu, and J. Long, A wideband fm demodulator for uwb ap-
plications, Research in Microelectronics and Electronics 2006, Ph. D., pp. 461
a low power, fully dierential rf front-end for fm-uwb based p-pan receivers,
Microwave Theory and Techniques, IEEE Transactions on, vol. 55, pp. 1355
[15] D. Ash, A low cost superregenerative saw stabilized receiver, Consumer Elec-
tronics, IEEE Transactions on, vol. CE-33, pp. 395404, Aug. 1987.
Geneva. The 2000 IEEE International Symposium on, vol. 1, pp. 6871 vol.1,
2000.
tions, Circuits and Systems II: Express Briefs, IEEE Transactions on, vol. 52,
[18] M. Pelissier, D. Morche, and P. Vincent, Rf front end of uwb receiver based on
2007. 14th IEEE International Conference on, pp. 935938, Dec. 2007.
BIBLIOGRAPHY 119
ISWPC 2008. 3rd International Symposium on, pp. 773775, May 2008.
possibilities for frequency modulation, Proceedings of the IRE, vol. 32, pp. 591
[22] L. Hernandez and S. Paton, A superregenerative receiver for phase and fre-
quency modulated carriers, Circuits and Systems, 2002. ISCAS 2002. IEEE
Regular Papers, IEEE Transactions on, vol. 52, pp. 5470, Jan. 2005.
Techniques, IEEE Transactions on, vol. 50, pp. 806813, Mar. 2002.
[27] Y. Xue, J. Gerrits, H. Choi, Nikhil, and S. K., Specication for prototyping
from phy and layer 2 (update d3.3.4a), Tech. Rep. IST-507102 D3.3.4b, My
[29] F. C. Commission, First report and order, Revision of Part 15 of the Commis-
2,4 GHz ISM band and using spread spectrum modulation techniques; Part 1:
Technical characteristics and test conditions. No. ETSI EN 300 328-1 in Euro-
[33] IBM, CMOS 9SF Technology Design Manual, vol. ES 88H1175. IBM, Setp.
2007.
cuits, IEEE Journal of, vol. 30, pp. 6567, Jan 1995.
ghz wireless lan in 0.18-/spl mu/m cmos, Solid-State Circuits, IEEE Journal