Lab 2: Getting Started with XILINX ISE

Create, Analyze and Synthesis of a Full Adder Design Using XILINX ISE WebPACK
Revised by: Basawaraj
Xilinx ISE Version: 14.7 WebPACK Edition
Last Modified: 04-26-2014
Introduction
Xilinx ISE is a complete FPGA logic-synthesis and optimization tool. With Xilinx ISE, you can create optimized FPGA netlists from VHDL
code. This lab will help you to learn how to create a design synthesize and implement it using Xilinx ISE. Xilinx ISE is available for use on both
Windows and Linux based machines.
Note: -Xilinx ISE WebPACK and Xilinx ISE Design Suite mainly differ in the availability of IP blocks. Hence the steps shown below, though
based on Xilinx ISE WebPACK, would also work for Xilinx ISE Design Suite edition.

Purpose of Lab2
The purpose of this lab is to introduce students to Xilinx ISE software. In Lab 1 you were introduced to synthesizing a simple VHDL program
using Active-HDL. In this lab you will not only synthesize the VHDL code but also add constraints to the same, but in Xilinx ISE.

Contents

Create a Project
Synthesize design
Create the design implementation
Enter Design Constraints and Controls
Optimize a Design Implementation

Create a Project
Start XILINX project navigator from the Start menu. (Start -> All Programs -> Xilinx Design Tools -> ISE Design Suite 14.7 -> ISE Design Tools
-> 64-bit Project Navigator).
Note: -On a 32-bit machine use the 32-bit version of Project Navigator (Start -> All Programs -> Xilinx Design Tools -> ISE Design Suite 14.7 ->
ISE Design Tools -> 32-bit Project Navigator).

Click OK to close the Tip of the Day window that pops up. You can uncheck Show Tips at Startup if you do not want the Tip of the Day
to popup every time you start the tool.

Create a new project by clicking File menu > New Project.

When the Create New Project window is displayed, choose your working directory (or the directory where you have your Lab 1 stored) and type
your new project name lab2 in the project name field. Select Top-level source type as HDL. Add project description if you need.

Click Next and you will go to the "Select the device and design flow for the project" interface.

Use the following settings to specify device and project properties.

1. Evaluation Development Board: - None Specified (default option)
2. Product Category: - All (default option)
3. Family: - Spartan3E
4. Device: - XC3S250E
5. Package: - CP132
6. Speed: - -4
Note: - Options 3 6 may change if you are using a development board with a different FPGA. For example if you are using the Basys2
board with the smaller gate count FPGA, then option 4 will be XC3S100E.
If you are using an evaluation development board from Xilinx then selecting the appropriate setting under option 1 will automatically set
options 2 6.
7. Top-Level Source Type: - HDL (default option)
8. Synthesis Tool: - XST (VHDL/Verilog)
9. Simulator: - ISim (VHDL/Verilog)
10. Preferred Language: - VHDL
Note: - For the purpose of this course you can use the default settings for the remaining properties.
Note: -The various properties mainly deal with the device selection (top half) and tool settings. Try to learn about the various options available
under each property.

Click Next button and this will lead you to the Project Summary page of the New Project Wizard.

Click Finish to complete new project setup and go to the Project Navigator window.

Create New Source You have three options in creating a new source file.
Option 1: Use the toolbar on the left-hand side of the project navigator window to create a new source. Click on the new source icon (the
topmost) to create a new source.

Option 2: Use the toolbar menu on the top. Project -> New Source to create a new source.

Option 3: Use the project in the Hierarchy section of the Design tab. Select the project (lab2 here), right-click and select New
Source to create a new source.

This brings up the New Source Wizard with options for various source types.

In the "New Source Wizard" interface choose VHDL Module from Select Source Type and enter a name, Adder, for the new source file in the
File Name field.

Make sure that Add to project option is selected. Click Next to continue. You will be asked to input the ports information, you can use the
wizard or you just click Next. Note:-This information will be used by the tool, Xilinx ISE, to create a skeleton code to help you. You can edit the
VHDL code generated if needed, for eg. you can delete, add or modify port signals that might have specified.

In this, we just click Next and then get the following summarized information for this source file.

Click the "Finish" button to continue. You will return to Xilinx ISE interface and see that the new source file, Adder.vhd, has been added to the
project.

You can see in the right-hand window that a template of the VHDL source file, based on information you provided while creating the new source,
is already generated for you by Xilinx ISE. You need to complete the source code based on your own design project. Here, copy and paste the
following code into the Adder.vhd file.
Note:-If you have an existing source file that you would like to add to the project you can either use the Add Source or Add Copy of Source
option. Add Source can be used when the source file is either in the project directory or in a remote directory whereas Add Copy of Source is
used when the source file is in a remote directory. Add Copy of Source copies the source file to the project directory.
Note: You should clearly understand what statements are automatically generated and what are needed to be coded by yourself. Please compare
the automatically generated code with the following code to see this.
library ieee;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_1164.all;
entity adder is
port ( a_in : in std_logic_vector (3 downto 0);
b_in : in std_logic_vector (3 downto 0);
c_out : out std_logic_vector (3 downto 0));
end adder;
architecture adder_arch of adder is
begin
process (a_in, b_in)
variable carry : std_logic_vector (4 downto 0);
variable sum :std_logic_vector (3 downto 0);
begin
carry (0) := '0';
for i in 0 to 3 loop
sum (i) := a_in(i) xor b_in(i) xor carry(i);
carry (i+1) := (a_in(i) and b_in(i)) or
(b_in(i) and carry (i)) or
(carry (i) and a_in(i));
end loop;
c_out <= sum;
end process;
end adder_arch;

Synthesize design
o
o
o

Save the file by click Save All under file menu.

Select top-level entity. Here, adder is already on the top-level.
Double click Synthesize - XST in "Process: adder -adder_arch" window to start the synthesizing process. The Process: section of the

Design tab is also referred to as Process View window.

When this process is finished, "Process "Synthesize - XST" completed successfully" is displayed in the console window.

Note:
Synthesis is the process of converting the abstract circuit behavior, described by a VHDL (or any HDL) code, into a hardware
implementation in terms of logic gates.
o To observe the results of the synthesis, expand Synthesize - XST in "Process: adder -adder_arch" window (click on the + sign). The
"Process: adder -adder_arch" window with Synthesize - XST expanded is shown below.
o

To view the register transfer level (RTL) schematic, click on View RTL Schematic

Click Run. Select RTL/Tech Viewer Startup Mode window pops-up. It provides two options for the startup mode, select the second
option: Start with a schematic of the top-level block. Note: Do try out the other option (option one: Start with the Explorer Wizard)
and see how it differs.

Click OK. This bring up the adder (RTL) tab. Note that the adder RTL tab in the figure below reads adder (RTL4), the number 4
after RTL increments every time you run View RTL Schematic and hence is not critical.

In the figure above the top-level block diagram, with only inputs and outputs, is shown. To see a detailed view of the RTL schematic
double-click inside the adder-block (the green box in adder (RTL) tab of the figure above). The expanded view of the RTL schematic is
shown below.

Click on Zoom to Full View icon to view the complete RTL schematic. The complete RTL schematic is shown in the figure below.

Similarly to view the technology schematic, select View Technology Schematic (it is just below View RTL Schematic option) and click
Run. Following the same steps as those used to view the RTL schematic we obtain the technology schematic, shown in adder Tech tab
of the figure below.

Note that most FPGA architectures are based on configurable logic block (CLB) or logic array block (LAB) that consist of look-up-tables
(LUTs), multiplexers (MUX) and other logical cells. And the technology schematic shows the implementation of the design in terms the
logical cells in the FPGA.
o Observe the result of trying to expand (both Zoom In and double-clicking on blocks in RTL and technology schematics.
o

Create the design implementation

First we need to assign the pin usage for the chip.
Add user constraints file to the project. The process is similar to that of adding the adder.vhd source file earlier. For example in the
Hierarchy section of the Design tab select the project (lab2 here), right-click and select New Source.
o Choose Implementation Constrains File and enter a name for the new source file, PinLock, in the File Name field.
o
o

o
o

Again, make sure that Add to project option is selected. Click Next and Finish.
Expand Adder in the Hierarchy section of Design tab. Select PinLock.ucf (or any other name that you used in the previous step). Right
click and Run Edit Constrains (Text) by expanding User Constrains in Processes window. You can also do the same by jus DoubleClicking on the Edit Constrains (Text) link.

Entering Design Constraints by copying and pasting the following into your user constraint file (PinLock.ucf). This is the pin assignment
for our Spartan 3 device. Youd better understand the syntax of the constrains files and you will be required to assign the pins by yourself
in your final projects.
Note: -The user constraints file (or implementation constraints file) is used to specify the actual pins on the FPGA to which the ports in
the top most entity are mapped. Except for some specific pins, JTAG, power or clock, most pins on an FPGA are I/O. That is, the pins can
either be used as an input or output based on the program. In practice, FPGAs in all applications would have been mounted on a board
with peripheral devices and thus specifying pins as either inputs or outputs based on peripheral connections. If a design is implemented
without the constraints file the tool will, if it does not give an error (due to absence of the constraints file), map the ports according to
some internal criteria (shortest delay or smallest area) and the pins so used might not be appropriate based on the peripheral devices
mounted on the board with the FPGA.
# Pin assignment for SWs / Inputs
NET "a_in<3>" LOC = "N3";
NET "a_in<2>" LOC = "E2";
NET "a_in<1>" LOC = "F3";
NET "a_in<0>" LOC = "G3";
NET "b_in<3>" LOC = "B4";
NET "b_in<2>" LOC = "K3";
NET "b_in<1>" LOC = "L3";
NET "b_in<0>" LOC = "P11";
# Pin assignment for LEDs / Outputs
NET "c_out<3>" LOC = "P6" ;
NET "c_out<2>" LOC = "P7" ;
NET "c_out<1>" LOC = "M11" ;
NET "c_out<0>" LOC = "M5" ;
Note: The lines in the .ucf file are read as follows:
1. # indicates the beginning of comments. Note: Comment in VHDL file (.vhd file) start with --" (two hypens) while
comments in constraints file (.ucf file) start with # (hash).
2. Line 2 of PinLock.ucf, shown above, is: NET "a_in<3>" LOC = "N3";
and is read as follows:
a) NET a_in<3> refers to the MSB (Most Significant Bit) of port a_in, i.e. a_in<3>, in the VHDL code provided at the
begining.
b) LOC = N3 refers to the actual I/O pin on the FPGA chip that a_in(3) on the board is connected to. Note: On the
Digilent board you can read the names of the I/O pins that the buttons (btn), switches, LEDs or seven segment displays are
connected.
c) ; signifies end of line.

Use the online help if you need instructions and information about specific constraints, attributes, and optimization options.
If later you find default constraints are not sufficient for your requirements, you might have to repeat creating and optimizing
implementations to enter constraints.
o Save the constraints file.
o A general user/implementation constraints file with details of all pins on Basys2 board available for use is available at:
Basys2_100_250General.ucf
o
o

Generate Programming File

o

Select Adder in the Hierarchy section of the Design tab, then right-click Generate Programming File and select Process Properties.

On the Process Properties Startup Options window that appears, under Startup options update the FPGA Start-Up Clock to JTAG Clock.

Then click Apply to apply the settings and then click OK to close the window.
At last, double click Implement Design to implement the design (i.e., translate, map and place and route). Then double click Generate
Programming File to produce the bit file. The bit file is the configuration file to download to the chip. Note: -You can directly Generate
Programming File (i.e., without first double clicking on Implement Design) and it will still work, this is because Xilinx ISE project
navigator automatically performs any steps that you might have skipped.
o If the Generate Programming File process is successfully completed the Process "Generate Programming File" completed
successfully message is displayed in the console window.
o The design summary tab lists the summary of the design, including any errors or warnings. This can be accessed from Project -> Design
Summary/Reports in the dropdown menu.
o
o

Processes (Synthesis XST, Implement Design or Generate Programming File) successfully completed will either have a green mark (if no
warnings were generated) or a yellow mark (if warnings were generated) against them. Failed process will have a red cross mark against
them.
o In later labs we will produce workable bit file for more advanced circuits that can also be download to the board. The basic procedures are
as this lab.
o The whole process is well logged and the intermediate files can be used in other XILINX tools.
o You can now close the project (File -> Close Project) and exit the project navigator (File -> Exit).
o

Program the FPGA on Basys2 Development Board

o

Connect the board to your computer using the USB cable provided.

Switch on the power supply to the board (use the switch on the board). For specifications of the Basys2 development board refer to this
link: Basys2 Development Board.
o Start Digilents Adept software. (Start -> All Programs -> Digilent -> Adept -> Adept)
o If the development board is connected and turned on, Adept detects the board (Basys2 250) and the devices on the same (FPGA:
XC3S250E and Flash ROM: XCF025)
o

On the Config tab click on Browse button against the FPGA.

On the file Open window that pops up, navigate to the directory containing the lab2 project folder. In my settings for this example it is
D:\VHDL_Designs\lab2.
o Find adder.bit file the project folder and select it.
o
o

o
o

Click Open to add the file to the programing list.

adder.bit file shows up against the FPGA and the Program button is now activated

Click Program to program the FPGA. If the programming is successful the message Programming Successful is seen in the console
window on the bottom.

The FPGA has now been successfully programmed. You can exit the Adept software if you desire. Note: -Do not disconnect or turn off
the board yet.
o With the board having been programmed you can now verify your design. Remember, from the User/Implementation constraints file, that
the eight switches are used as inputs (four for a_in and four for b_in) and four LEDs are used for c_out. Provide various input
combinations using the switches and verify that the outputs are correct. Note: -The entity does not have carry in or carry out.
o After verifying the design you can switch off the power supply to the development board and disconnect it from your computer.
o

Requirement
Write a lab report. (Limit to Max of 3 Pages.)
Solutions to the following Questions. (Limit to Max of 2 Pages)
1. What can you infer from, the Outputs in the Console window and the Design Summary tab?
2. What are the factors that come into picture in selecting a FPGA for your design implementation?
Submit your lab report and solutions to questions before lab 3.
Note:
1. For the lab report you can use the template: Lab report template. The link is also available near the end of the lab index page.
2. The VHDL files are available in the project working directory. For example the above project (lab2) was created in D:\VHDL_Designs\ and
hence its working directory would be D:\VHDL_Designs\lab2 and all the VHDL source files are available in that directory.
3. To include the RTL, schematics in your report you can use Print Screen option in Windows (or its equivalent in the OS of your choice) to
capture a screen shot of the schematic in Xilinx ISE project navigator and include this in your report. You can also print the schematic using
the print option in Xilinx ISE project navigator.

On the Schematic Print window that pops-up select a physical printer (e.g. your home printer) if you need a paper copy of the schematic. If
you need an electronic copy you can use software such as PDFCreator to print the schematic to a file. You can combine this file with your
report.

[Back to EE4143/5143 Lab Assignments Page]