HDL Model QP

USN
TE44
B. E. Degree (Autonomous) Forth Semester End Examination (SEE), Dec 2014/Jan 2015
Programming in HDL
Model Question Paper- 1
[Time: 3 Hours]
[ Maximum Marks: 100]

Instructions to students:
1. Answer FIVE FULL questions.
2. Answer ANY ONE from Question No. 3 and 4
3. Question No. 1, 2 and 5 are COMPULSORY
1. (a) Mention the types of HDL Descriptions. Explain Structural and Mixed type of Description with
example.
(10 Marks)
(b) Explain Verilog Data types.
(05 Marks)
(c) Discuss the major differences between VHDL and Verilog.
(05 Marks)
2. (a) What do you mean by Data Flow style of Description? Explain its features with a suitable example.
(04 Marks)
(b) Briefly discuss with Illustration of (i) Signal declaration & Signal Assignment statements (with eg)
(ii) Concurrent Signal Assignment Statement (with eg) (06 Marks)
(c)Write a behavioral description of a 4-bit binary counter.
(10 Marks)
3. (a) Write a VHDL Structural Description for full adder.

(06 Marks)
(b) Explain the binding in the following, with example: (i) Between entity and component in VHDL.
(ii) Between two modules in Verilog. (10 Marks)
(c) Explain the use of Generic (in VHDL) and Parameter (in Verilog) with an example.
(04 Marks)
4. (a) Explain the following with Syntax (i) Procedure in VHDL (ii) Tasks in Verilog.
(06 Marks)
(b) Write the VHDL/Verilog code to convert a Fraction Binary to Real using Procedures/Tasks. (10 Marks)
(c) With an example explain VHDL function.
(04 Marks)
5. (a) What is Synthesis? List the general steps involved in Synthesis.
(08 Marks)
(b) Write a behavioral Code in VHDL /Verilog for the Signal Assignment statement Y=X. Explain the
mapping to gate level logic diagram.
(12 Marks)
6. (a) Explain the implementation of single dimensional and two dimensional arrays in VHDL.
(b) Explain the fetch & execute cycles of basic computer for the following operation:
Halt, Add, Mult, XOR, NAND.
(c) What is the necessity of Mixed type Description.
Dr. Ambedkar Institute of Technology, Bengaluru 560056
(An Autonomous Institution Affiliated to Visvesvaraya
Technological University, Belgaum)
(05 Marks)
(10 Marks)
(05 Marks)
7. (a) How to invoke a VHDL entity from a Verilog Module.

(b) Explain Mixed language Description of a Low pass RC filter.
(08 Marks)
(12 Marks)

USN
TE44
Programming in HDL
[Time: 3 Hours]

1. (a) Discuss the needs of HDL.

(05 Marks)
(b) Explain the following data types:
(i) Physical std_logic and bit_vector in VHDL (ii) Nets, parameters & registers in VHDL (10 Marks)
(c) Given A =1000 and B = 0011, perform the following operations:
(i) AXNOR B (ii)Shift B two position left logical (iii) Reduction NAND (iv)Verilog Concatenation{A,B}
(iv) Verilog modulus A % B.
(05 Marks)
2. (a) Explain the use of data type vectors with dataflow description of 2*2 Unsigned Combinational Array
Multiplier in VHDL & Verilog with the Gate-level diagram & Simulation output.
(12 Marks)
(b) Write VHDL code for a D-latch using Variable Assignment & Signal Assignment statements. With
Simulation waveforms clearly distinguish between the 2 statements.
(08 Marks)
3. (a) What is Binding? Discuss the binding between library and components?
(10 Marks)
(b) Write the HDL description of 2:1 multiplexer with active low enable in VHDL/Verilog using Structural
Style.
(10 Marks)
4. (a) Develop VHDL Code for signed vector multiplication, using Procedure and task.
(b) Explain how functions are described in VHDL and Verilog.
(14 Marks)
(06 Marks)
5. (a) Describe Synthesis information extraction from entity and module with examples.
(08 marks)
(b) With an example, explain how mapping of procedure and task takes place in VHDL and Verilog
Synthesis respectively.
(12 marks)
6. (a) How to attach a package to the VHDL module? Explain with an example.
(b) Write the Description of 16*8 SRAM in VHDL/Verilog.
(10 marks)
(10 marks)
7. (a) List the limitations of Mixed Language Description.

(04 marks)
(b) Write a HDL program for Mixed language Descriptions of a JK flip-flop with a clear input. (10 Marks)
(c) Write a mixed language description of an AND gate invoking a Verilog module from a VHDL module
(05 marks)
USN
TE44
Programming in HDL
[Time: 3 Hours]

1. (a) Explain the Structural of VHDL module and Verilog module.

(05 Marks)
(b) Write general syntax and suitable examples, explain logical operators available in VHDL and verilog.(10 Marks)
(c) Explain the difference between Synthesis & Simulation.
(05 Marks)
2. (a) With the help of a truth table and K-maps write Boolean expression for a 2-bit magnitude Comparator. Write
VHDL/Verilog code.
(06 Marks)
(b) Explain Verilog Repeat and Forever statements with an example.
(04 Marks)
(c) Using Booth Algorithm, find the product of two 4 bit numbers -3 and 8. Write a Verilog code using behavioral
style of Description.
(10 Marks)
3. (a) Write the HDL Description of 2:1 multiplexer with active low enable in VHDL/Verilog using Structural style.
(12 marks)
(b) Write the Structural description of a D-latch using VHDL /Verilog Code.
(08 Marks)
4. (a) Write Verilog code to convert a signed binary to Integer using Task.
(08 Marks)
(b) Explain the use of procedure in VHDL and task in Verilog with description of an N-bit ripple carry adder.
(12 Marks)
5. (a) Write the VHDL code for Signal Assignment statement y=2*x+3. Show the synthesized logic symbol and gate
level diagram. Write the Structural code in Verilog using the gate level diagram.
(12 Marks)
(b) What is Synthesis? Give synthesis information extracted, when the input and output are defined as:
(i) bit
(ii) std_logic_vector.
6. (a) Write a block diagram and function table of 128*16 Static memory. Write a Verilog Code. Verify the code by
Simulation waveform by writing data in memory locations 8,18,46,126 and read the contents of two memory
locations 18 and 46.
(08 Marks)
(b) Write a VHDL Code for addition of two 5*5 matrices using a package.
(08 Marks)
(c) Explain the syntax VHDL package and package body.
(04 Marks)

7. (a) Write a mixed language Description of a full adder invoking a VHDL entity from a Verilog module. (10 marks)
(b) Write a mixed language Description of a Master Slave D flipflop invoking a VHDL entity from a Verilog Module.
(10 marks)


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USN

[ Maximum Marks: 100]

3. (a) Write a VHDL Structural Description for full adder.

7. (a) How to invoke a VHDL entity from a Verilog Module.

Dr. Ambedkar Institute of Technology, Bengaluru 560056

[ Maximum Marks: 100]

1. (a) Discuss the needs of HDL.

7. (a) List the limitations of Mixed Language Description.

[ Maximum Marks: 100]

1. (a) Explain the Structural of VHDL module and Verilog module.

Dr. Ambedkar Institute of Technology, Bengaluru 560056

Dr. Ambedkar Institute of Technology, Bengaluru 560056

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