A Rapid Prototyping Environment For Microprocessor Based System-on-Chips and Its Application To The Development of A Network Processor

A Rapid Prototyping Environment for
Microprocessor based System-on-Chips and its

Application to the Development of a Network
Processor?
Andre Brinkmann, Dominik Langen, and Ulrich R
uckert
Department of Electrical Engineering and Heinz Nixdorf Institute
Paderborn University, 33102 Paderborn, Germany.
{brinkman, langen, rueckert}@hni.uni-paderborn.de.
Abstract. The rapid advances in microelectronic circuit design have

dramatically increased the design complexity of modern integrated devices. One approach to fit the time-to-market requirements is the use of
rapid prototyping environments. In this paper we introduce a new FPGA
based prototyping environment, on which a full functional embedded system can be implemented. The main distinction to other environments is
the incorporation of a synthesizable and configurable microprocessor core
into the design space. Furthermore we present the application of this environment to the development of a network processor which consists of
a processor core and an Ethernet controller.
Introduction
During the last decade the rapid advances in microelectronic circuit design led
to an increase in transistor count and clock speed. Todays deep submicron fabrication technologies enable design engineers to put an impressive number of
components like microprocessors and coprocessors on a single chip. These so
called system on chips (SOCs) lower the power consumption and the total fabrication cost of embedded systems while increasing performance and reliability.
The complexity of SOCs is outpacing the capabilities of modern design tools and
verification methodologies, resulting in long and expensive design cycles. To meet
the time-to-market requirements has become a formidable challenge for SOC design engineers. The use of rapid prototyping systems could ease this task [4, 3,
6]. Prototyping environments are normally based on a standard microprocessor,
surrounded by a large amount of memory and interfaces to the outside world.
Only the add-on hardware is realized on field programmable devices (FPGAs).
Improvements of the processor core itself or the interfaces are not possible. This
may be sufficient for a wide number of applications, but excludes the processor
core from the design space. In this paper we will present a new approach which
?
Research partially supported by the DFG-Sonderforschungsbereich 376, Project C5

and Infineon Technologies AG
Fig. 1. The rapid prototyping board.
includes a configurable microprocessor core in the design space. In the next section we will introduce our rapid prototyping environment and the implemented
interfaces. In section 3, we describe the integration of an Ethernet controller
into our prototyping environment. Finally we will draw some conclusions and
describe the next steps.
Rapid Prototyping Environment
Our rapid prototyping environment consists of three main parts: a FPGA board,
a microprocessor core with software support and an Amba AHB interface for
the core. The main distinction to other prototyping environments is the incorporation of the configurable microprocessor core. The core is described in the
hardware description language VHDL and can be used both as a black box or as
part of the design space by altering e.g. the architecture, the instruction set, or
the interface depending on the requirements of the currently developed system.
The FPGA board includes two Xilinx XC4085 re-programmable FPGAs,
256 KByte SRAM, 128 KByte EPROM, a LCD display, a keypad, and off-board
connectors for extension cards. The whole FPGA board has 6 layers and an area
of 130 x 350mm2 (Fig. 1). In this figure the memory subsystem is covered by
the keypad. The two FPGAs are connected via 196 wires with each other, 80 of
these wires can be observed by a logic analyzer. The microprocessor core and
the Amba interface are mapped to the left FPGA. The other FPGA is used for
the implementation of the application specific part, in this case for the Ethernet
controller. The right FPGA is directly connected to a connector with 96 pins.
This connector can be used for extension boards which can provide additional
hardware for the system on the FPGA board. In our case we put the physical
layer of the Ethernet on such an extension board.
The unmodified version of the microprocessor core is fully binary compatible
to the Motorola M-Core processor and can be programmed with a number of
C/C++ environments. The M-Core is a 32-bit RISC one-address machine with

a load/store architecture. Every opcode has a fixed length of 16 bit and every
instruction except of the load and store instructions works only on registers.
Fourteen percent of its opcode space is unoccupied and a hardware accelerator
interface is supported. So the core can be easily enhanced. A detailed description
of the architecture can be found in [7, 8].
The simple bus interface of the M-Core described in [8] has several disadvantages which disqualifies it for advanced applications. The main drawback is, that
the simple bus interface does not support multiple bus masters, e.g. required by
advanced network switches consisting of multiple DMA capable modules [2]. In
a standard rapid prototyping environment, it would not be possible to efficiently
exchange this simple microprocessor bus against a more suitable interface. In
our environment, which incorporates a VHDL description of the microprocessor
core and the bus interface, this drawback could be fixed by a simple rewriting
of the bus interface. This new bus interface could be directly connected to the
microprocessor core without any glue logic. For our application, we have chosen
the Amba Advanced High-performance Bus AHB [1]. The Amba bus supports an
arbitrary number of masters like processor cores and DMA units.
Integration of an Ethernet Controller
As Ethernet networks become more and more widespread, their importance as

a means of communication for (embedded) computer systems grows accordingly
[9]. Therefore, we present the design of an Ethernet medium access control
(MAC) layer [5] for an embedded system and its integration into our rapid
prototyping environment. The logic of the controller is mapped onto the right
FPGA of our prototyping board (see Fig. 1) and it is connected to the M-Core
processor via the Amba AHB bus interface. In the following, we describe the
main modules of the Ethernet controller, the bus interface, the receive module, and the transmit module, and their integration into our rapid prototyping
environment.
The transmit and receive unit of the Ethernet controller have to transfer
data packets between the bus interface and the physical layer and to handle the
Ethernet layer 2 protocol stack. To handle the communication, we use dualported
SRAMs between the bus interface and the transmit and receive unit, respectively.
In the following, we will call them fifo memories, because we use them in a very
similar manner. One unit pushes data packets into the memory and the other
unit reads packets out of it.
The bus interface is connecting the microprocessor core with the receive
and transmit unit of the Ethernet controller via the Amba AHB bus. In this
implementation with a single Ethernet controller we have chosen a simple slave
interface without DMA capabilities. This involves that the microprocessor core
is fully responsible for the transfers to and from the fifo memories. The transfers
can either be triggered by interrupts or the processor polls the status of the
memories. The controller is programmed by a memory mapped register set. An

interface to the MII management register set is also incorporated.
The prototyping board itself does not contain the necessary physical Ethernet
layer and the buffer memory of the controller. To test the Ethernet controller
in a real environment, we have developed an extension card, which contains the
physical Ethernet layer. This card is connected to the prototyping board via the
offboard connectors. The entire system has been tested with a transfer rate of 10
MBit/s in a heterogeneous environment of workstations and personal computers.
Ping, arp and reverse arp were successfully performed. The Ethernet controller
and the physical layer are also capable to support 100 MBit/s. In our case, the
system speed is limited by the speed of the microprocessor core.
Conclusion
We have presented a rapid prototyping environment including a configurable

microprocessor core in the design space. The VHDL description of the core
enables the designer to configure the core according to the requirements of his
current project. In our example, we have exchanged the standard bus interface
against a multimaster capable Amba AHB bus to couple the M-Core processor
with an Ethernet controller. Together with the extension card, the prototyping
environment is able to simulate a whole SOC. In future work we will use Xilinx
Virtex FPGAs to support an increased amount of logic and on-chip RAM. This
will enable us to integrate additional modules like a simple cache or additional
peripheral devices. We also plan to alter the instruction set of the microprocessor
core to increase the resource efficiency (more speed and/or less power) of our
system.
References
1. ARM: AMBAT M Specification (Rev. 2.0) (1999).
2. P. Berenbrink, A. Brinkmann, C. Scheideler: Design of the PRESTO Multimedia
Data Storage Network, Proc. of the Workshop on Communication and Data Management in Large Networks (INFORMATIK 99) (1999).
3. W. B. Gardner and M. Serra: An Object-Oriented Layered Approach for Hardware/Software Codesign of Embedded Systems, Proc. of the 31st Hawaii Conference
on System Science (1998).
4. W. Hardt and W. Rosenstiel: Speed-Up Estimation for HW/SW-Systems, Proc. of
the 4th ACM Workshop on Hardware/Software Codesign (1996).
5. IEEE: IEEE Standard 802.3: Carrier Sense Multiple Access with Collision Detection
(CSMA/CD) Access Methods and Physical Layer Specifications, The Institute of
Electrical and Electronics Engineers, Inc. (1998).
6. H. Kalte, M. Porrmann, U. R
uckert: Rapid Prototyping System f
ur dynamisch
rekonfigurierbare Hardwarestrukturen, Proc. of the AES2000 (2000).
7. Motorola: M-Core Reference Manual (1998).
8. Motorola: MMC2001 Reference Manual (1998).
9. S. R
uping, E. Vonnahme, J. Jasperneite: Analysis of Switched Ethernet Networks
with different Topologies used in Automation Systems, Fieldbus Technology (1999).

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A Rapid Prototyping Environment for

Microprocessor based System-on-Chips and its

Abstract. The rapid advances in microelectronic circuit design have

Research partially supported by the DFG-Sonderforschungsbereich 376, Project C5

Fig. 1. The rapid prototyping board.

Rapid Prototyping Environment

C/C++ environments. The M-Core is a 32-bit RISC one-address machine with

Integration of an Ethernet Controller

As Ethernet networks become more and more widespread, their importance as

memories. The controller is programmed by a memory mapped register set. An

We have presented a rapid prototyping environment including a configurable

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