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    NVL-12.Constant Delay Logic Style

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    sivakumarb92
    The document proposes a constant delay (CD) logic style that aims to reduce delay in high-speed applications like adders and multipliers. CD logic exhibits unique characteristics where the output is pre-evaluated before inputs from preceding stages, offering performance advantages over static and dynamic domino logic styles. Simulation results show the CD logic achieves an average of 94% and 56% speedup over static and dynamic domino logic in gates. For 8-bit adders and 32-bit carry lookahead adders, CD logic has 39% speedup and 64% energy-delay product reduction from static logic.

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    NVL-12.Constant Delay Logic Style

    Uploaded by

    sivakumarb92
    34 views3 pages
    The document proposes a constant delay (CD) logic style that aims to reduce delay in high-speed applications like adders and multipliers. CD logic exhibits unique characteristics where the output is pre-evaluated before inputs from preceding stages, offering performance advantages over static and dynamic domino logic styles. Simulation results show the CD logic achieves an average of 94% and 56% speedup over static and dynamic domino logic in gates. For 8-bit adders and 32-bit carry lookahead adders, CD logic has 39% speedup and 64% energy-delay product reduction from static logic.

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    The document proposes a constant delay (CD) logic style that aims to reduce delay in high-speed applications like adders and multipliers. CD logic exhibits unique characteristics where the output is pre-evaluated before inputs from preceding stages, offering performance advantages over static and dynamic domino logic styles. Simulation results show the CD logic achieves an average of 94% and 56% speedup over static and dynamic domino logic in gates. For 8-bit adders and 32-bit carry lookahead adders, CD logic has 39% speedup and 64% energy-delay product reduction from static logic.

    Copyright:

    © All Rights Reserved
    Download as DOC, PDF, TXT or read online from Scribd
    Download as doc, pdf, or txt
    34 views3 pages

    NVL-12.Constant Delay Logic Style

    Uploaded by

    sivakumarb92
    The document proposes a constant delay (CD) logic style that aims to reduce delay in high-speed applications like adders and multipliers. CD logic exhibits unique characteristics where the output is pre-evaluated before inputs from preceding stages, offering performance advantages over static and dynamic domino logic styles. Simulation results show the CD logic achieves an average of 94% and 56% speedup over static and dynamic domino logic in gates. For 8-bit adders and 32-bit carry lookahead adders, CD logic has 39% speedup and 64% energy-delay product reduction from static logic.

    Copyright:

    © All Rights Reserved
    Download as DOC, PDF, TXT or read online from Scribd
    Download as doc, pdf, or txt
    of 3

    Constant Delay Logic Style

    AIM:
    The main aim of the project is to design Constant Delay Logic Style.

    (ABSTRACT)
    A constant delay (CD) logic style is proposed in this paper, targeting at full-custom
    high-speed applications. The CD characteristic of this logic style regardless of the
    logic type makes it suitable in implementing complicated logic expressions such as
    addition. CD logic exhibits a unique characteristic where the output is preevaluated before the inputs from the preceding stage is ready. This feature offers
    performance advantage over static and dynamic domino logic styles in a singlecycle multistage circuit block. Several design considerations including timing
    window width adjustment and clock distribution are discussed. Using 65-nm
    general-purpose CMOS technology, the proposed logic demonstrates an average
    speed up of 94% and 56% over static and dynamic domino logic, respectively, in
    five different logic gates. Simulation results of 8-bit ripple carry adders show that
    CD logic is 39% and 23% faster than the static and dynamic-based adders,
    respectively. CD logic also demonstrates 39% speedup and 64% (22%) energydelay product (EDP) reduction from static logic at 100% (10%) data activity in 32bit carry look ahead adders. For 8-bit Wallace tree multiplier, CD logic achieves a
    similar speedup with at least 50% EDP reduction across all data activities.
    Proposed Architecture:
    In this architecture delay has been reduced by using constant delay logic for ripple
    carry adder . Further we can implement the constant delay logic for multiplier

    Advantage:
    CD logics advantages in terms of delay and EDP were also demonstrated in 8bit Wallace tree multipliers.
    Compared to 32-bit adders, CD logic achieves a similar delay improvement,
    but has an even better EDP reduction, primarily because the final adder which
    makes up the critical path of the multiplier is a relatively small circuit block of
    the overall circuitry.
    .
    BLOCK DIAGRAM:

    TOOLS: hspice_vA-2008.03, t-spice

    REFERENCE:
    [1] R. Zimmermann and W. Fichtner, Low-power logic styles: CMOS versus
    pass-transistor logic, IEEE J. Solid-State Circuits, vol. 32, no. 7, pp. 10791090,
    Jul. 1997.
    [2] N. Goncalves and H. De Man, NORA: A race free dynamic CMOS technique
    for pipelined logic structures, IEEE J. Solid-State Circuits, vol. 18, no. 3, pp. 261
    266, Jun. 1983.
    [3] C. Lee and E. Szeto, Zipper CMOS,IEEE Circuits Syst. Mag.,vol.2, no. 3, pp.
    1016, May 1986.
    [4] R. Rafati, S. Fakhraie, and K. Smith, A 16-bit barrel-shifter implemented in
    data-driven dynamic logic (D3L),IEEE Trans. Circuits Syst.I, Reg. Papers, vol.
    53, no. 10, pp. 21942202, Oct. 2006.
    [5] F. Frustaci, M. Lanuzza, P. Zicari, S. Perri, and P. Corsonello, Low power
    split-path data-driven dynamic logic, Circuits Dev. Syst. IET, vol. 3, no. 6, pp.
    303312, Dec. 2009

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