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    HW5

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    prakash_shr
    The document provides specifications for a homework assignment to design a finite state machine (FSM) in VHDL or Verilog to control an application specific integrated circuit (ASIC) that performs audio convolution. The FSM must have 8 states to handle initialization, receiving coefficients and input data, performing convolution computations, resetting, and sleeping. Detailed explanations are given for each state and the transitions between states based on control signals and input data patterns.

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    HW5

    Uploaded by

    prakash_shr
    107 views8 pages
    The document provides specifications for a homework assignment to design a finite state machine (FSM) in VHDL or Verilog to control an application specific integrated circuit (ASIC) that performs audio convolution. The FSM must have 8 states to handle initialization, receiving coefficients and input data, performing convolution computations, resetting, and sleeping. Detailed explanations are given for each state and the transitions between states based on control signals and input data patterns.

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    EE 6306 HW5

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    The document provides specifications for a homework assignment to design a finite state machine (FSM) in VHDL or Verilog to control an application specific integrated circuit (ASIC) that performs audio convolution. The FSM must have 8 states to handle initialization, receiving coefficients and input data, performing convolution computations, resetting, and sleeping. Detailed explanations are given for each state and the transitions between states based on control signals and input data patterns.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    107 views8 pages

    HW5

    Uploaded by

    prakash_shr
    The document provides specifications for a homework assignment to design a finite state machine (FSM) in VHDL or Verilog to control an application specific integrated circuit (ASIC) that performs audio convolution. The FSM must have 8 states to handle initialization, receiving coefficients and input data, performing convolution computations, resetting, and sleeping. Detailed explanations are given for each state and the transitions between states based on control signals and input data patterns.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    of 8

    University of Texas at Dallas

    Department of Electrical Engineering


    EEDG 6306 - Application Specific Integrated Circuit Design
    Homework #5
    Due on October 1, 2014
    Submission for Homework #5:
    Homework Report

    Write a VHDL/Verilog code to imitate the FSM diagram based on the


    specifications provided below. All the states and possible states transitions must
    be shown in the report.
    To make it easier, we make several assumptions for this assignment.
    (1. 1) You only need to do one channel, all input data are read on the falling edge.
    (1.2) When 10 consecutive zero input data come, it enters state 8.
    (1.3) You need to prepare Rj, Coeff and input. The format of these should follow
    the specification; however, there is no requirement in their numbers as long as you
    can clarify the states transitions.
    (1.4) For the computation, simply extend 16-bits input to 40-bits and then output it.
    (1.5) The report should include your source code and waveforms to justify the
    state transition
    (1.6) Apply the same name style (as HW3/HW4) to your report file name

    To save the number of pins, the coefficients for the left (right)
    channel are sent into the chip using the input data port InputL
    (InputR). Thus, there are no dedicated pins for sending the
    coefficients.
    When the chip is in sleeping mode, it shall shut down the unnecessary
    clocks and operations to save energy.

    If the external controller detects InReady = 0 sent by the chip,


    controller will not transmit Dclk, Frame or any input samples to the
    chip until the InReady = 1 is detected.
    If the external controller detects InReady = 1 sent by the chip, the
    continuing inactive time to Frame will not be more than 16 data clock
    cycles.

    Sclk (Input)
    System clock running at a frequency of 26.88MHz(you may modify this
    frequency) provides the timing reference for the internal and control signals, as
    well as the output samples. Outputs InReady and OutReady are updated on the
    rising edge of Sclk.
    Dclk (Input)
    Data clock running at a frequency of 768kHz(this frequency is fixed) provides
    the timing reference for the input samples.
    Start (Input)
    When Start is set high, the chip begins to initialize. Start may be asynchronous
    with Sclk or Dclk.
    Reset_n (Input)
    When Reset_n is set low, the chip begins to reset. Reset_n may be asynchronous
    with Sclk or Dclk.
    InReady (Output)
    InReady is set high when the chip is ready to receive coefficients or input samples;
    otherwise it is set low. InReady is updated on the rising edge of Sclk.
    OutReady (Output)
    OutReady is set high when the chip is transmitting output samples; otherwise it is
    set low. OutReady is aligned with the rising edge of Frame.
    InputL (Input)
    InputL carries the left channel coefficients and audio samples in serial form. Bit 0
    is the sign bit and is transmitted first. Bit 15 is the LSB and is transmitted last.
    InputL is read on the falling edge of Dclk.

    InputR (Input)
    InputR carries the right channel coefficients and audio samples in serial form. Bit
    0 is the sign bit and is transmitted first. Bit 15 is the LSB and is transmitted last.
    InputR is read on the falling edge of Dclk.
    OutputL (Output)
    OutputL carries the left channel serial output samples. Bit 0 is the sign bit and is
    transmitted first. Bit 39 is the LSB and is transmitted last. OutputL is updated on
    the rising edge of Sclk. The output frame starts with the rising edge of Frame and
    lasts for 40 Sclk cycles.
    OutputR (Output)
    OutputR carries the right channel serial output samples. Bit 0 is the sign bit and is
    transmitted first. Bit 39 is the LSB and is transmitted last. OutputR is updated on
    the rising edge of Sclk. The output frame starts with the rising edge of Frame and
    lasts for 40 Sclk cycles.
    Frame (Input)
    Frame aligns the serial coefficients, input and output samples. Frame is set high
    for one Dclk cycle when the first bit of the input samples or coefficients is
    received, and then it is set low.

    The frame has a fixed length of 16-bits and Dclk is used. The input audio date is
    16-bits wide, and therefore uses all the bits in the frame. The unused MSB in Rj
    and coefficients have to be zero padded by the controller. InReady is set high by
    the MSDAP to denote that it is ready to receive data. The Frame signal denotes
    the beginning of a frame.

    The timing diagram for the output stream is shown in Figure 3-11. The MSB is
    transmitted first and the LSB last. The output frame is 40-bits. OutReady is set
    high by the MSDAP for the duration of 40-bits clocked serially by Sclk. The Frame
    signal denotes the beginning of a frame. Notice that because Sclk is used for the
    output, the time between consecutive rising edges of Frame (which lasts for 16
    Dclk cycles) is significantly longer than 40-bits.

    FSM

    The above finite state machine works as follows:

    State 0 (Initialization):

    When Start is high, the chip begins the initialization

    process, including clearing all the memories and registers. When the initialization
    process is completed, the chip enters State 1.

    State 1 (Waiting to receive Rj):

    In this state, InReady is set high. If Frame is

    detected to be high, the MSDAP enters State 2.

    State 2 (Reading Rj):

    In this state, the chip reads the Rj values and InReady

    remains high. Once all Rj values have been loaded, the MSDAP enters State 3.

    State 3 (Waiting to receive coefficients): In this state, InReady is set high. If


    Frame signal is detected to be high, the MSDAP enters State 4.

    State 4 (Reading coefficients): In this state, the chip reads the coefficients.
    InReady remains high. Once all the coefficients have been loaded, the MSDAP
    enters State 5.

    State 5 (Waiting to receive data): In this state, InReady is set high. If Frame
    is detected to be high, the chip enters State 6, or if Reset_n is detected to be low,
    the MSDAP enters State 7.

    State 6 (Working):

    In this state, the chip continually reads input samples, does

    the convolution computation, and sends out the computed output data; InReady
    remains high. If Reset_n is detected low, the chip enters State 7 or if the chip
    detects 800 consecutive inputs samples as zero, it enters State 8.

    State 7 (Clearing): In this state, InReady is set low. All input and output samples
    in memories or registers except for Rj and coefficients are cleared to zero. If
    Reset_n is detected to be low again during this process, the chip will come back to

    the beginning of this process. The chip will go back to State 5 when completing the
    task of reset.

    State 8 (Sleeping): In this state, the chip goes into sleeping mode while setting
    InReady high. If any non-zero input sample on either left or right channel is
    detected, the chip enters State 6. If Reset_n is detected low, the chip enters
    State 7.

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