Vijay Kumar Balla

16/1, 3
rd
Cross, Murugesh palya, Bangalore -17
Ph: +91-8861849938
e-mail: [email protected]





Pursue career in ASIC Physical Design where my expertise in ASIC Design and Computer Aided Design
(CAD) will be fully utilized and will help in improving the bottom line of the company.



Physical Design tasks which include Floor plan, Placement, Clock tree synthesis (CTS), Routing,
Timing closure and Physical Verification needed to build a silicon chip from Gate Level Netlist to final
GDSII Layout.
Design for Manufacturability (DFM) concepts which include Crosstalk, Electron Migration, IR Drop,
and Gate Oxide Integrity to increase the manufacturing yield.
Timing Concepts: Static Timing Analysis (STA).
Full Custom Standard Cell Design.
CMOS Circuit Design, Analog & Digital Electronics.
IC Fabrication Process.
RTL Level Design and Verification using Verilog HDL.



Physical Design Tools: Synopsys - IC Compiler
Timing Analysis (STA): Synopsys - Prime Time Suite (PT)
Full Custom Layout tools: Mentor Graphics:
Design Architect IC (Schematic Capture)
IC Station (Layout Editor)
Calibre ( DRC, LVS, PEX )
RTL Synthesis: Synopsys - Design Complier (DC)
Spice Level Simulation: Mentor Graphics ELDO, LT Spice
RTL Design & Verification: Verilog HDL
Questa Sim, Model Sim, Xilinx ISE
Scripting Language: TCL
Assembly Language: Microprocessor 8085, 8086



Master of Science in Electrical Engineering, (May 2010)
Fairleigh Dickinson University, Teaneck, New Jersey, USA.

Bachelor of Technology in Electrical & Electronics Engineering, (April 2008)
Jawaharlal Nehru Technological University, Anantapur, India.



Post Graduate Diploma in ASIC Design, (July 2012 Jan 2013)
RV-VLSI Design Center, Bangalore, India.

Advanced VLSI Design and Verification, (Jan 2012 May 2012)
Maven Silicon VLSI Design & Training Center, Bangalore, India.

OBJECTIVE
EXPERTISE
CAD SKILL SET
TECHNICAL CERTIFICATIONS
EDUCATION


Physical Design of Torpedo Processor
The goal of the project was to obtain a DRC clean db meeting timing and area goals from the
Netlist given.
Performed physical design from Floorplan to signoff using Synopsys IC Compiler in 180nm
technology and captured the various aspects & challenges of VLSI Physical Design Flow.
Project based learning:
Floorplan techniques to consider for the placement of 32 macros block wise by avoiding
stacking, narrow channels, achieving best core utilization and a contiguous core area.
To create the best power network with the appropriate width, pitch to meet the IR drop
constraint without any DRC and floating shapes or pins.
Placement of 43k standard cells, timing closure of setup, understanding the timing reports,
congestion and fixing any floating shapes or pins.
Generating an optimized clock tree meeting the target skew, using Non Default Route for
the clock tree, clock shielding.
Fixing the hold violations and setup violations.
The routing flow, clearing all the DRCs and the constraints to consider for a better routed
chip with no timing violations, reducing crosstalk.
DFM tasks like inserting filler cells, redundant vias, clearing antenna violations.
Post Layout STA in Prime Time after doing a parasitic extraction.
Physical Verification DRC and LVS in Calibre.
Understanding and writing TCL scripts.
Major challenges faced:
Placement of macros by studying the data flow diagram to avoid large delays, avoiding
narrow channels as power routing is tough and to make sure all macros are easily accessible
to the core logic.
Debugging a few timing paths where the constraints at fault has to be modified and in CTS
stage generating a skew file and analyzing the paths where skew can be borrowed for timing
closure.
Fixing 1000 antenna violations by writing a tcl script to extract all the nets from the log file
that have antenna violations and fixing them in one shot which saved plenty of time.
Fixing DRCs after routing has been done like Via spacing, Metal spacing and overlap where
an alternate way has to be found and route manually by following the minimum metal area
rule.

Full Chip Implementation ORCA Chip
Learnt the basic flow of Full chip design by performing a full chip implementation of ORCA
chip Gate level Netlist using Synopsys IC Compiler.
This project which includes 13 macros, 21k standard cells, 91 I/O Pads has introduced the
basic flow of physical design starting from floorplan to DFM.

Static Timing Analysis of Inter Integrated Circuit (I2C) -
Pursued Static Timing Analysis of a functionally verified Gate Level Netlist of I2C.
In this project the set of constraints for timing analysis (.sdc) was developed and Static
Timing Analysis (STA) was performed using Synopsys Prime Time (PT).
Captured various types of timing violations that can occur and fixing them by understanding
the concepts like cell resizing, buffer insertion/removal in clock paths and data paths and
logic restructuring.


PROJECTS
Layout of NAND, NOR, 2:1 MUX, Half Adder
Transistor level schematic of NAND2, NOR2 gates, 2:1 MUX and the Half Adder in Design
Architect IC
Full Custom Layout in IC Station. DRC, LVS and PEX were carried out in Calibre. [Vdd = 1.8v,
TSMC 180nm]

Design of a Level Sensitive Latch & 6-Transistor SRAM cell
During the course work in VLSI Systems at FDU, designed a transistor level schematic of a
level sensitive latch and 6-Transistor SRAM cell in Design Architect IC and simulated in ELDO.
[Vdd = 1.8v, TSMC 180nm]



Graduate Teaching Assistant in Electrical Engineering at Fairleigh Dickinson University.
For Prof. Kalyan Mondal in VLSI Systems, Spring 2010
For Prof. Gloria Reinish in Random Process in Communications, Fall 2009
Lab Assistant in Electrical Engineering Department at Fairleigh Dickinson University.
For Prof. Hong Zhao in Digital System Design Lab for the under graduates.



Procurement Engineer at Gulf Business House International, Abu Dhabi, UAE.
Major responsibilities included: (Oct 2011 Dec 2011)
Meet new and existing suppliers and negotiate purchase agreements.
Evaluate proposals, quotes from sub contractors, choose appropriate supplier and the right
products that comply with the project specifications and requirements.

Electrical Low Voltage/Network Engineer at Almana Network Solutions, Doha, Qatar.
Major responsibilities included: (Sep 2010 Sep 2011)
Review the entire design before implementation and complete testing, commissioning of the
project.
Co-ordinate with clients and other engineers for the successful completion of the project.
Certifications Achieved during my work here:
Cisco Certified Network Associate (CCNA)
HP Certified AIS Accredited Integration Specialist - Network Infrastructure
HP Certified ASP Accredited Sales Professional - Networking
AVAYA Professional Sales Specialist (APSS)



As a Graduate Teaching Assistant I am an active member of the Technical Enrichment and Outreach
Program (TEOP) organized at Fairleigh Dickinson University.
Student organizer of the technical committee and managed a team of 500 students during the
national level technical symposiums EYE 05, EYE 07, EYE 08 organized at my Undergraduate
college.
Skilled in communicating technical information in precise and concise manner.
Ability to work effectively in a group.
Strong analytical and problem solving skills.

Available upon request.
RELATED WORK EXPERIENCE
EMPLOYEMENT HISTORY
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REFERENCES